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khoa-nguyen-18KhiemNguyenT
khoa-nguyen-18
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KhiemNguyenT
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hal: renesas: Update ofs cfg for migrate FSP 6.0.0
Update ofs cfg for migrate FSP 6.0.0 Signed-off-by: Khoa Nguyen <[email protected]>
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‎drivers/ra/CMakeLists.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,6 @@ set(include_dirs
1010
)
1111

1212
set(srcs
13-
fsp/src/bsp/mcu/all/bsp_rom_registers.c
1413
fsp/src/bsp/mcu/all/bsp_clocks.c
1514
fsp/src/bsp/mcu/all/bsp_delay.c
1615
fsp/src/bsp/mcu/all/bsp_register_protection.c
@@ -22,6 +21,7 @@ zephyr_include_directories(${include_dirs})
2221
zephyr_library_sources(${srcs})
2322

2423
zephyr_include_directories(fsp/src/bsp/mcu/${CONFIG_SOC_SERIES})
24+
zephyr_library_sources(fsp/src/bsp/mcu/${CONFIG_SOC_SERIES}/bsp_linker.c)
2525

2626
# Optional build base on feature configuration
2727
zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_SCI_UART

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/bsp_cfg.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
2+
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
33
*
44
* SPDX-License-Identifier: BSD-3-Clause
55
*/
@@ -10,6 +10,7 @@
1010
#include "soc.h"
1111
#include "bsp_clock_cfg.h"
1212
#include "bsp_mcu_family_cfg.h"
13+
#include "bsp_mcu_ofs_cfg.h"
1314

1415
#define SUBCLOCK_STABILIZATION_MAX(x) ((x < 10000) ? x : 10000)
1516

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/bsp_mcu_device_pn_cfg.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
2+
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
33
* Copyright (c) 2024 TOKITA Hiroshi
44
*
55
* SPDX-License-Identifier: BSD-3-Clause
@@ -9,4 +9,5 @@
99
#define BSP_ROM_SIZE_BYTES DT_REG_SIZE(DT_NODELABEL(flash0))
1010
#define BSP_DATA_FLASH_SIZE_BYTES DT_REG_SIZE(DT_NODELABEL(flash1))
1111
#define BSP_PACKAGE_PINS (64)
12+
#define BSP_NUMBER_OF_CORES (1)
1213
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/bsp_mcu_family_cfg.h

Lines changed: 1 addition & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -35,70 +35,13 @@ extern "C" {
3535
#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
3636
#define BSP_CFG_INLINE_IRQ_FUNCTIONS (0)
3737

38-
/* OFS0 WDT configurations */
39-
#ifdef CONFIG_WDT_RENESAS_RA_START_IN_BOOT
40-
#define WDTSTRT (0)
41-
#else
42-
#define WDTSTRT (1)
43-
#endif
44-
45-
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
46-
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
47-
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (WDTSTRT << 17)
48-
#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)
49-
#define OFS_SEQ5 (1 << 28) | (1 << 30)
50-
#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
51-
#define BSP_CFG_ROM_REG_OFS0 \
52-
(OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
53-
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
54-
#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
55-
#define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC)
56-
#define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF)
57-
#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
58-
#define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC)
59-
#define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF)
60-
#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
61-
#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC)
62-
#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF)
63-
#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
64-
#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
65-
#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
66-
#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
67-
#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
68-
#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
69-
#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
70-
#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
71-
#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
7238
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
7339
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
7440
#endif
7541

7642
/* Used to create IELS values for the interrupt initialization table
7743
* g_interrupt_event_link_select. */
78-
#define BSP_PRV_IELS_ENUM(vector) CONCAT(ELC_, vector)
79-
/*
80-
ID Code
81-
Note: To permanently lock and disable the debug interface define the
82-
BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. WARNING: This will
83-
disable debug access to the part and cannot be reversed by a debug probe.
84-
*/
85-
#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
86-
#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
87-
#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
88-
#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
89-
#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
90-
#else
91-
/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
92-
#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
93-
#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
94-
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
95-
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
96-
#endif
97-
98-
#if (0)
99-
#define BSP_SECTION_FLASH_GAP BSP_PLACE_IN_SECTION(".flash_gap")
100-
#endif
101-
44+
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
10245
#ifdef __cplusplus
10346
}
10447
#endif

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/bsp_mcu_ofs_cfg.h

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
/*
2+
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
6+
7+
#ifndef BSP_MCU_OFS_CFG_H_
8+
#define BSP_MCU_OFS_CFG_H_
9+
#define OFS_IWDT (0xA001A001 | 1 << 1 | 3 << 2 | 15 << 4 | 3 << 8 | 3 << 10 | 1 << 12 | 1 << 14)
10+
#define OFS_WDT (1 << 17 | 3 << 18 | 15 << 20 | 3 << 24 | 3 << 26 | 1 << 28 | 1 << 30)
11+
#define BSP_CFG_OPTION_SETTING_OFS0 (OFS_IWDT | OFS_WDT)
12+
#define BSP_CFG_OPTION_SETTING_OFS1_NO_HOCOFRQ (0xFFFF8EC3 | (1 <<2) | (3 << 3) | (1 << 8))
13+
14+
#define BSP_CFG_OPTION_SETTING_OFS1 ((uint32_t) BSP_CFG_OPTION_SETTING_OFS1_NO_HOCOFRQ | ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET))
15+
16+
#ifndef BSP_CFG_OPTION_SETTING_SECMPU
17+
#define BSP_CFG_OPTION_SETTING_SECMPU 0x0003FFFC,0x0003FFFF,0x0003FFFC,0x0003FFFF,0x0003FFFC,0x0003FFFF,0x20007FFC,0x20007FFF,0x400DFFFC,0x400DFFFF,0x400DFFFC,0x400DFFFF,0xFFFFFFFF
18+
#endif
19+
/*
20+
ID Code
21+
Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
22+
WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
23+
*/
24+
#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
25+
/*
26+
ID Code
27+
Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings.
28+
WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled.
29+
Please read the HWM for full details of the clearing process.
30+
*/
31+
#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
32+
#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
33+
#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
34+
#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
35+
#else
36+
/* ID Code: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
37+
38+
#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
39+
40+
#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
41+
42+
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
43+
44+
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
45+
#endif
46+
#define BSP_CFG_OPTION_SETTING_OSIS BSP_CFG_ID_CODE_LONG_1, 0xFFFFFFFF, BSP_CFG_ID_CODE_LONG_2, 0xFFFFFFFF, BSP_CFG_ID_CODE_LONG_3, 0xFFFFFFFF, BSP_CFG_ID_CODE_LONG_4, 0xFFFFFFFF
47+
#endif /* BSP_MCU_OFS_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/bsp_cfg.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
2+
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
33
*
44
* SPDX-License-Identifier: BSD-3-Clause
55
*/
@@ -10,6 +10,7 @@
1010
#include "soc.h"
1111
#include "bsp_clock_cfg.h"
1212
#include "bsp_mcu_family_cfg.h"
13+
#include "bsp_mcu_ofs_cfg.h"
1314

1415
#define SUBCLOCK_STABILIZATION_MAX(x) ((x < 10000) ? x : 10000)
1516

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/bsp_mcu_device_pn_cfg.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,4 +9,5 @@
99
#define BSP_ROM_SIZE_BYTES DT_REG_SIZE(DT_NODELABEL(flash0))
1010
#define BSP_DATA_FLASH_SIZE_BYTES DT_REG_SIZE(DT_NODELABEL(flash1))
1111
#define BSP_PACKAGE_PINS (100)
12+
#define BSP_NUMBER_OF_CORES (1)
1213
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/bsp_mcu_family_cfg.h

Lines changed: 20 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -10,96 +10,40 @@
1010
extern "C" {
1111
#endif
1212

13-
#include "bsp_mcu_device_pn_cfg.h"
13+
#include "bsp_clock_cfg.h"
1414
#include "bsp_mcu_device_cfg.h"
15+
#include "bsp_mcu_device_pn_cfg.h"
1516
#include "bsp_mcu_info.h"
16-
#include "bsp_clock_cfg.h"
1717
#define BSP_MCU_GROUP_RA2L1 (1)
18-
#define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0))
19-
#define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0))
20-
#define BSP_SUB_CLOCK_HZ (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0))
21-
#if BSP_CFG_HOCO_FREQUENCY == 0
22-
#define BSP_HOCO_HZ (24000000)
18+
#define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0))
19+
#define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0))
20+
#define BSP_SUB_CLOCK_HZ (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0))
21+
#if BSP_CFG_HOCO_FREQUENCY == 0
22+
#define BSP_HOCO_HZ (24000000)
2323
#elif BSP_CFG_HOCO_FREQUENCY == 2
24-
#define BSP_HOCO_HZ (32000000)
24+
#define BSP_HOCO_HZ (32000000)
2525
#elif BSP_CFG_HOCO_FREQUENCY == 4
26-
#define BSP_HOCO_HZ (48000000)
26+
#define BSP_HOCO_HZ (48000000)
2727
#elif BSP_CFG_HOCO_FREQUENCY == 5
28-
#define BSP_HOCO_HZ (64000000)
29-
#else
30-
#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
31-
#endif
32-
33-
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
34-
#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
35-
#define BSP_CFG_INLINE_IRQ_FUNCTIONS (0)
36-
37-
/* OFS0 WDT configurations */
38-
#ifdef CONFIG_WDT_RENESAS_RA_START_IN_BOOT
39-
#define WDTSTRT (0)
28+
#define BSP_HOCO_HZ (64000000)
4029
#else
41-
#define WDTSTRT (1)
30+
#error \
31+
"Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
4232
#endif
4333

44-
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
45-
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
46-
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (WDTSTRT << 17)
47-
#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)
48-
#define OFS_SEQ5 (1 << 28) | (1 << 30)
49-
#define BSP_CFG_USE_LOW_VOLTAGE_MODE (0)
50-
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
51-
#define BSP_CFG_ROM_REG_OFS1_ICSATS (1 << 31)
52-
#define BSP_CFG_ROM_REG_OFS1 (0x7FFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8) | (BSP_CFG_ROM_REG_OFS1_ICSATS))
53-
#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
54-
#define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC)
55-
#define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF)
56-
#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
57-
#define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC)
58-
#define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF)
59-
#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
60-
#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC)
61-
#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF)
62-
#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
63-
#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
64-
#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
65-
#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
66-
#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
67-
#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
68-
#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
69-
#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
70-
#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
34+
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
35+
#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
36+
#define BSP_CFG_INLINE_IRQ_FUNCTIONS (0)
7137

7238
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
7339
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
7440
#endif
75-
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
76-
#define BSP_PRV_IELS_ENUM(vector) CONCAT(ICU_, vector)
77-
78-
#define BSP_CFG_DCDC_ENABLE (0)
79-
#define BSP_CFG_DCDC_VOLTAGE_RANGE (BSP_POWER_MODE_DCDC_2V7_TO_3V6)
80-
/*
81-
ID Code
82-
Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings.
83-
WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled.
84-
Please read the HWM for full details of the clearing process.
85-
*/
86-
#if defined(BSP_ID_CODE_LOCKED)
87-
#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
88-
#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
89-
#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
90-
#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
91-
#else
92-
/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
93-
#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
94-
#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
95-
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
96-
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
97-
#endif
98-
99-
#if (0)
100-
#define BSP_SECTION_FLASH_GAP BSP_PLACE_IN_SECTION(".flash_gap")
101-
#endif
41+
/* Used to create IELS values for the interrupt initialization table
42+
* g_interrupt_event_link_select. */
43+
#define BSP_PRV_IELS_ENUM(vector) (ICU_##vector)
10244

45+
#define BSP_CFG_DCDC_ENABLE (0)
46+
#define BSP_CFG_DCDC_VOLTAGE_RANGE (BSP_POWER_MODE_DCDC_2V7_TO_3V6)
10347
#ifdef __cplusplus
10448
}
10549
#endif

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/bsp_mcu_ofs_cfg.h

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
/*
2+
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
6+
7+
#ifndef BSP_MCU_OFS_CFG_H_
8+
#define BSP_MCU_OFS_CFG_H_
9+
#define OFS_IWDT (0xA001A001 | 1 << 1 | 3 << 2 | 15 << 4 | 3 << 8 | 3 << 10 | 1 << 12 | 1 << 14)
10+
#define OFS_WDT (1 << 17 | 3 << 18 | 15 << 20 | 3 << 24 | 3 << 26 | 1 << 28 | 1 << 30)
11+
#define BSP_CFG_OPTION_SETTING_OFS0 (OFS_IWDT | OFS_WDT)
12+
#define BSP_CFG_OPTION_SETTING_OFS1_NO_HOCOFRQ (0x7FFF8EC3 | 1 <<2 | 3 << 3 | 1 << 8 | 1 << 31)
13+
14+
#define BSP_CFG_OPTION_SETTING_OFS1 ((uint32_t) BSP_CFG_OPTION_SETTING_OFS1_NO_HOCOFRQ | ((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET))
15+
16+
#ifndef BSP_CFG_OPTION_SETTING_SECMPU
17+
#define BSP_CFG_OPTION_SETTING_SECMPU 0x0003FFFC,0x0003FFFF,0x0003FFFC,0x0003FFFF,0x0003FFFC,0x0003FFFF,0x20007FFC,0x20007FFF,0x400DFFFC,0x400DFFFF,0x400DFFFC,0x400DFFFF,0xFFFFFFFF
18+
#endif
19+
/*
20+
ID Code
21+
Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings.
22+
WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled.
23+
Please read the HWM for full details of the clearing process.
24+
*/
25+
#if defined(BSP_ID_CODE_LOCKED)
26+
/*
27+
ID Code
28+
Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings.
29+
WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled.
30+
Please read the HWM for full details of the clearing process.
31+
*/
32+
#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
33+
#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
34+
#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
35+
#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
36+
#else
37+
/* ID Code: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
38+
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#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
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#endif
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#define BSP_CFG_OPTION_SETTING_OSIS BSP_CFG_ID_CODE_LONG_1, 0xFFFFFFFF, BSP_CFG_ID_CODE_LONG_2, 0xFFFFFFFF, BSP_CFG_ID_CODE_LONG_3, 0xFFFFFFFF, BSP_CFG_ID_CODE_LONG_4, 0xFFFFFFFF
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#endif /* BSP_MCU_OFS_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e1/bsp_cfg.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
2+
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
@@ -10,6 +10,7 @@
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#include "soc.h"
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#include "bsp_mcu_ofs_cfg.h"
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#define SUBCLOCK_STABILIZATION_MAX(x) ((x < 10000) ? x : 10000)
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