|
| 1 | +/* |
| 2 | +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates |
| 3 | +* |
| 4 | +* SPDX-License-Identifier: BSD-3-Clause |
| 5 | +*/ |
| 6 | + |
| 7 | +#ifndef BSP_ELC_H |
| 8 | +#define BSP_ELC_H |
| 9 | + |
| 10 | +/*******************************************************************************************************************//** |
| 11 | + * @addtogroup BSP_MCU_RA4W1 |
| 12 | + * @{ |
| 13 | + **********************************************************************************************************************/ |
| 14 | + |
| 15 | +/*********************************************************************************************************************** |
| 16 | + * Macro definitions |
| 17 | + **********************************************************************************************************************/ |
| 18 | + |
| 19 | +/*********************************************************************************************************************** |
| 20 | + * Typedef definitions |
| 21 | + **********************************************************************************************************************/ |
| 22 | + |
| 23 | +/*********************************************************************************************************************** |
| 24 | + * Exported global variables |
| 25 | + **********************************************************************************************************************/ |
| 26 | + |
| 27 | +/*********************************************************************************************************************** |
| 28 | + * Exported global functions (to be accessed by other files) |
| 29 | + **********************************************************************************************************************/ |
| 30 | + |
| 31 | +/* UNCRUSTIFY-OFF */ |
| 32 | + |
| 33 | +/** Sources of event signals to be linked to other peripherals or the CPU |
| 34 | + * @note This list is device specific. |
| 35 | + * */ |
| 36 | +typedef enum e_elc_event_ra4w1 |
| 37 | +{ |
| 38 | + ELC_EVENT_NONE = (0x0), // Link disabled |
| 39 | + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 |
| 40 | + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 |
| 41 | + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 |
| 42 | + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 |
| 43 | + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 |
| 44 | + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 |
| 45 | + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 |
| 46 | + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 |
| 47 | + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 |
| 48 | + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 |
| 49 | + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 |
| 50 | + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 |
| 51 | + ELC_EVENT_DMAC0_INT = (0x011), // DMAC0 transfer end |
| 52 | + ELC_EVENT_DMAC1_INT = (0x012), // DMAC1 transfer end |
| 53 | + ELC_EVENT_DMAC2_INT = (0x013), // DMAC2 transfer end |
| 54 | + ELC_EVENT_DMAC3_INT = (0x014), // DMAC3 transfer end |
| 55 | + ELC_EVENT_DTC_COMPLETE = (0x015), // DTC transfer complete |
| 56 | + ELC_EVENT_DTC_END = (0x016), // DTC transfer end |
| 57 | + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x017), // Canceling from Snooze mode |
| 58 | + ELC_EVENT_FCU_FRDYI = (0x018), // Flash ready interrupt |
| 59 | + ELC_EVENT_LVD_LVD1 = (0x019), // Voltage monitor 1 interrupt |
| 60 | + ELC_EVENT_LVD_VBATT = (0x01B), // VBATT low voltage detect |
| 61 | + ELC_EVENT_CGC_MOSC_STOP = (0x01C), // Main Clock oscillation stop |
| 62 | + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x01D), // Snooze entry |
| 63 | + ELC_EVENT_AGT0_INT = (0x01E), // AGT interrupt |
| 64 | + ELC_EVENT_AGT0_COMPARE_A = (0x01F), // Compare match A |
| 65 | + ELC_EVENT_AGT0_COMPARE_B = (0x020), // Compare match B |
| 66 | + ELC_EVENT_AGT1_INT = (0x021), // AGT interrupt |
| 67 | + ELC_EVENT_AGT1_COMPARE_A = (0x022), // Compare match A |
| 68 | + ELC_EVENT_AGT1_COMPARE_B = (0x023), // Compare match B |
| 69 | + ELC_EVENT_IWDT_UNDERFLOW = (0x024), // IWDT underflow |
| 70 | + ELC_EVENT_WDT_UNDERFLOW = (0x025), // WDT0 underflow |
| 71 | + ELC_EVENT_RTC_ALARM = (0x026), // Alarm interrupt |
| 72 | + ELC_EVENT_RTC_PERIOD = (0x027), // Periodic interrupt |
| 73 | + ELC_EVENT_RTC_CARRY = (0x028), // Carry interrupt |
| 74 | + ELC_EVENT_ADC0_SCAN_END = (0x029), // End of A/D scanning operation |
| 75 | + ELC_EVENT_ADC0_SCAN_END_B = (0x02A), // A/D scan end interrupt for group B |
| 76 | + ELC_EVENT_ADC0_WINDOW_A = (0x02B), // Window A Compare match interrupt |
| 77 | + ELC_EVENT_ADC0_WINDOW_B = (0x02C), // Window B Compare match interrupt |
| 78 | + ELC_EVENT_ADC0_COMPARE_MATCH = (0x02D), // Compare match |
| 79 | + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x02E), // Compare mismatch |
| 80 | + ELC_EVENT_ACMPLP0_INT = (0x02F), // Low Power Comparator channel 0 interrupt |
| 81 | + ELC_EVENT_ACMPLP1_INT = (0x030), // Low Power Comparator channel 1 interrupt |
| 82 | + ELC_EVENT_USBFS_FIFO_0 = (0x031), // DMA transfer request 0 |
| 83 | + ELC_EVENT_USBFS_FIFO_1 = (0x032), // DMA transfer request 1 |
| 84 | + ELC_EVENT_USBFS_INT = (0x033), // USBFS interrupt |
| 85 | + ELC_EVENT_USBFS_RESUME = (0x034), // USBFS resume interrupt |
| 86 | + ELC_EVENT_IIC0_RXI = (0x035), // Receive data full |
| 87 | + ELC_EVENT_IIC0_TXI = (0x036), // Transmit data empty |
| 88 | + ELC_EVENT_IIC0_TEI = (0x037), // Transmit end |
| 89 | + ELC_EVENT_IIC0_ERI = (0x038), // Transfer error |
| 90 | + ELC_EVENT_IIC0_WUI = (0x039), // Wakeup interrupt |
| 91 | + ELC_EVENT_IIC1_RXI = (0x03A), // Receive data full |
| 92 | + ELC_EVENT_IIC1_TXI = (0x03B), // Transmit data empty |
| 93 | + ELC_EVENT_IIC1_TEI = (0x03C), // Transmit end |
| 94 | + ELC_EVENT_IIC1_ERI = (0x03D), // Transfer error |
| 95 | + ELC_EVENT_CTSU_WRITE = (0x046), // Write request interrupt |
| 96 | + ELC_EVENT_CTSU_READ = (0x047), // Measurement data transfer request interrupt |
| 97 | + ELC_EVENT_CTSU_END = (0x048), // Measurement end interrupt |
| 98 | + ELC_EVENT_KEY_INT = (0x049), // Key interrupt |
| 99 | + ELC_EVENT_DOC_INT = (0x04A), // Data operation circuit interrupt |
| 100 | + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x04B), // Frequency error interrupt |
| 101 | + ELC_EVENT_CAC_MEASUREMENT_END = (0x04C), // Measurement end interrupt |
| 102 | + ELC_EVENT_CAC_OVERFLOW = (0x04D), // Overflow interrupt |
| 103 | + ELC_EVENT_CAN0_ERROR = (0x04E), // Error interrupt |
| 104 | + ELC_EVENT_CAN0_FIFO_RX = (0x04F), // Receive FIFO interrupt |
| 105 | + ELC_EVENT_CAN0_FIFO_TX = (0x050), // Transmit FIFO interrupt |
| 106 | + ELC_EVENT_CAN0_MAILBOX_RX = (0x051), // Reception complete interrupt |
| 107 | + ELC_EVENT_CAN0_MAILBOX_TX = (0x052), // Transmission complete interrupt |
| 108 | + ELC_EVENT_IOPORT_EVENT_1 = (0x053), // Port 1 event |
| 109 | + ELC_EVENT_IOPORT_EVENT_2 = (0x054), // Port 2 event |
| 110 | + ELC_EVENT_IOPORT_EVENT_3 = (0x055), // Port 3 event |
| 111 | + ELC_EVENT_IOPORT_EVENT_4 = (0x056), // Port 4 event |
| 112 | + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x057), // Software event 0 |
| 113 | + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x058), // Software event 1 |
| 114 | + ELC_EVENT_POEG0_EVENT = (0x059), // Port Output disable 0 interrupt |
| 115 | + ELC_EVENT_POEG1_EVENT = (0x05A), // Port Output disable 1 interrupt |
| 116 | + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x05B), // Capture/Compare match A |
| 117 | + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x05C), // Capture/Compare match B |
| 118 | + ELC_EVENT_GPT0_COMPARE_C = (0x05D), // Compare match C |
| 119 | + ELC_EVENT_GPT0_COMPARE_D = (0x05E), // Compare match D |
| 120 | + ELC_EVENT_GPT0_COMPARE_E = (0x05F), // Compare match E |
| 121 | + ELC_EVENT_GPT0_COMPARE_F = (0x060), // Compare match F |
| 122 | + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x061), // Overflow |
| 123 | + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x062), // Underflow |
| 124 | + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x063), // Capture/Compare match A |
| 125 | + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x064), // Capture/Compare match B |
| 126 | + ELC_EVENT_GPT1_COMPARE_C = (0x065), // Compare match C |
| 127 | + ELC_EVENT_GPT1_COMPARE_D = (0x066), // Compare match D |
| 128 | + ELC_EVENT_GPT1_COMPARE_E = (0x067), // Compare match E |
| 129 | + ELC_EVENT_GPT1_COMPARE_F = (0x068), // Compare match F |
| 130 | + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x069), // Overflow |
| 131 | + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x06A), // Underflow |
| 132 | + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x06B), // Capture/Compare match A |
| 133 | + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x06C), // Capture/Compare match B |
| 134 | + ELC_EVENT_GPT2_COMPARE_C = (0x06D), // Compare match C |
| 135 | + ELC_EVENT_GPT2_COMPARE_D = (0x06E), // Compare match D |
| 136 | + ELC_EVENT_GPT2_COMPARE_E = (0x06F), // Compare match E |
| 137 | + ELC_EVENT_GPT2_COMPARE_F = (0x070), // Compare match F |
| 138 | + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x071), // Overflow |
| 139 | + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x072), // Underflow |
| 140 | + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x073), // Capture/Compare match A |
| 141 | + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x074), // Capture/Compare match B |
| 142 | + ELC_EVENT_GPT3_COMPARE_C = (0x075), // Compare match C |
| 143 | + ELC_EVENT_GPT3_COMPARE_D = (0x076), // Compare match D |
| 144 | + ELC_EVENT_GPT3_COMPARE_E = (0x077), // Compare match E |
| 145 | + ELC_EVENT_GPT3_COMPARE_F = (0x078), // Compare match F |
| 146 | + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x079), // Overflow |
| 147 | + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x07A), // Underflow |
| 148 | + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x07B), // Capture/Compare match A |
| 149 | + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x07C), // Capture/Compare match B |
| 150 | + ELC_EVENT_GPT4_COMPARE_C = (0x07D), // Compare match C |
| 151 | + ELC_EVENT_GPT4_COMPARE_D = (0x07E), // Compare match D |
| 152 | + ELC_EVENT_GPT4_COMPARE_E = (0x07F), // Compare match E |
| 153 | + ELC_EVENT_GPT4_COMPARE_F = (0x080), // Compare match F |
| 154 | + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x081), // Overflow |
| 155 | + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x082), // Underflow |
| 156 | + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x083), // Capture/Compare match A |
| 157 | + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x084), // Capture/Compare match B |
| 158 | + ELC_EVENT_GPT5_COMPARE_C = (0x085), // Compare match C |
| 159 | + ELC_EVENT_GPT5_COMPARE_D = (0x086), // Compare match D |
| 160 | + ELC_EVENT_GPT5_COMPARE_E = (0x087), // Compare match E |
| 161 | + ELC_EVENT_GPT5_COMPARE_F = (0x088), // Compare match F |
| 162 | + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x089), // Overflow |
| 163 | + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x08A), // Underflow |
| 164 | + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x09B), // Capture/Compare match A |
| 165 | + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x09C), // Capture/Compare match B |
| 166 | + ELC_EVENT_GPT8_COMPARE_C = (0x09D), // Compare match C |
| 167 | + ELC_EVENT_GPT8_COMPARE_D = (0x09E), // Compare match D |
| 168 | + ELC_EVENT_GPT8_COMPARE_E = (0x09F), // Compare match E |
| 169 | + ELC_EVENT_GPT8_COMPARE_F = (0x0A0), // Compare match F |
| 170 | + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x0A1), // Overflow |
| 171 | + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x0A2), // Underflow |
| 172 | + ELC_EVENT_OPS_UVW_EDGE = (0x0AB), // UVW edge event |
| 173 | + ELC_EVENT_SCI0_RXI = (0x0AC), // Receive data full |
| 174 | + ELC_EVENT_SCI0_TXI = (0x0AD), // Transmit data empty |
| 175 | + ELC_EVENT_SCI0_TEI = (0x0AE), // Transmit end |
| 176 | + ELC_EVENT_SCI0_ERI = (0x0AF), // Receive error |
| 177 | + ELC_EVENT_SCI0_AM = (0x0B0), // Address match event |
| 178 | + ELC_EVENT_SCI0_RXI_OR_ERI = (0x0B1), // Receive data full/Receive error |
| 179 | + ELC_EVENT_SCI1_RXI = (0x0B2), // Receive data full |
| 180 | + ELC_EVENT_SCI1_TXI = (0x0B3), // Transmit data empty |
| 181 | + ELC_EVENT_SCI1_TEI = (0x0B4), // Transmit end |
| 182 | + ELC_EVENT_SCI1_ERI = (0x0B5), // Receive error |
| 183 | + ELC_EVENT_SCI1_AM = (0x0B6), // Address match event |
| 184 | + ELC_EVENT_SCI4_RXI = (0x0C1), // Receive data full |
| 185 | + ELC_EVENT_SCI4_TXI = (0x0C2), // Transmit data empty |
| 186 | + ELC_EVENT_SCI4_TEI = (0x0C3), // Transmit end |
| 187 | + ELC_EVENT_SCI4_ERI = (0x0C4), // Receive error |
| 188 | + ELC_EVENT_SCI4_AM = (0x0C5), // Address match event |
| 189 | + ELC_EVENT_SCI9_RXI = (0x0C6), // Receive data full |
| 190 | + ELC_EVENT_SCI9_TXI = (0x0C7), // Transmit data empty |
| 191 | + ELC_EVENT_SCI9_TEI = (0x0C8), // Transmit end |
| 192 | + ELC_EVENT_SCI9_ERI = (0x0C9), // Receive error |
| 193 | + ELC_EVENT_SCI9_AM = (0x0CA), // Address match event |
| 194 | + ELC_EVENT_SPI0_RXI = (0x0CB), // Receive buffer full |
| 195 | + ELC_EVENT_SPI0_TXI = (0x0CC), // Transmit buffer empty |
| 196 | + ELC_EVENT_SPI0_IDLE = (0x0CD), // Idle |
| 197 | + ELC_EVENT_SPI0_ERI = (0x0CE), // Error |
| 198 | + ELC_EVENT_SPI0_TEI = (0x0CF), // Transmission complete event |
| 199 | + ELC_EVENT_SPI1_RXI = (0x0D0), // Receive buffer full |
| 200 | + ELC_EVENT_SPI1_TXI = (0x0D1), // Transmit buffer empty |
| 201 | + ELC_EVENT_SPI1_IDLE = (0x0D2), // Idle |
| 202 | + ELC_EVENT_SPI1_ERI = (0x0D3), // Error |
| 203 | + ELC_EVENT_SPI1_TEI = (0x0D4) // Transmission complete event |
| 204 | +} elc_event_t; |
| 205 | + |
| 206 | +#define BSP_PRV_VECT_ENUM(event,group) (ELC_ ## event) |
| 207 | + |
| 208 | +#define ELC_PERIPHERAL_NUM (19U) |
| 209 | +#define BSP_OVERRIDE_ELC_PERIPHERAL_T |
| 210 | +/** Possible peripherals to be linked to event signals |
| 211 | + * @note This list is device specific. |
| 212 | + * */ |
| 213 | +typedef enum e_elc_peripheral |
| 214 | +{ |
| 215 | + ELC_PERIPHERAL_GPT_A = (0), |
| 216 | + ELC_PERIPHERAL_GPT_B = (1), |
| 217 | + ELC_PERIPHERAL_GPT_C = (2), |
| 218 | + ELC_PERIPHERAL_GPT_D = (3), |
| 219 | + ELC_PERIPHERAL_GPT_E = (4), |
| 220 | + ELC_PERIPHERAL_GPT_F = (5), |
| 221 | + ELC_PERIPHERAL_GPT_G = (6), |
| 222 | + ELC_PERIPHERAL_GPT_H = (7), |
| 223 | + ELC_PERIPHERAL_ADC0 = (8), |
| 224 | + ELC_PERIPHERAL_ADC0_B = (9), |
| 225 | + ELC_PERIPHERAL_DAC0 = (12), |
| 226 | + ELC_PERIPHERAL_IOPORT1 = (14), |
| 227 | + ELC_PERIPHERAL_IOPORT2 = (15), |
| 228 | + ELC_PERIPHERAL_IOPORT3 = (16), |
| 229 | + ELC_PERIPHERAL_IOPORT4 = (17), |
| 230 | + ELC_PERIPHERAL_CTSU = (18) |
| 231 | +} elc_peripheral_t; |
| 232 | + |
| 233 | +/** Positions of event link set registers (ELSRs) available on this MCU */ |
| 234 | +#define BSP_ELC_PERIPHERAL_MASK (0x0007D3FFU) |
| 235 | + |
| 236 | +/* UNCRUSTIFY-ON */ |
| 237 | +/** @} (end addtogroup BSP_MCU_RA4W1) */ |
| 238 | + |
| 239 | +#endif |
0 commit comments