Skip to content

Commit 566b115

Browse files
quytranpzzduynguyenxa
quytranpzz
authored and
duynguyenxa
committed
hal: renesas: Add supporting for RA6M5
Add RA6M5 hal support Signed-off-by: Quy Tran <[email protected]>
1 parent 5251081 commit 566b115

File tree

10 files changed

+29855
-0
lines changed

10 files changed

+29855
-0
lines changed

‎drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h‎

Lines changed: 28410 additions & 0 deletions
Large diffs are not rendered by default.

‎drivers/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h‎

Lines changed: 370 additions & 0 deletions
Large diffs are not rendered by default.

‎drivers/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h‎

Lines changed: 445 additions & 0 deletions
Large diffs are not rendered by default.

‎drivers/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature_gen.h‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
/*
2+
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
6+
7+
#ifndef BSP_FEATURE_GEN_H
8+
#define BSP_FEATURE_GEN_H
9+
10+
/***********************************************************************************************************************
11+
* Includes <System Includes> , "Project Includes"
12+
**********************************************************************************************************************/
13+
14+
/***********************************************************************************************************************
15+
* Macro definitions
16+
**********************************************************************************************************************/
17+
18+
/***********************************************************************************************************************
19+
* Typedef definitions
20+
**********************************************************************************************************************/
21+
22+
/***********************************************************************************************************************
23+
* Exported global variables (to be accessed by other files)
24+
**********************************************************************************************************************/
25+
26+
/***********************************************************************************************************************
27+
* Private global variables and functions
28+
**********************************************************************************************************************/
29+
30+
// *UNCRUSTIFY-OFF*
31+
#define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0)
32+
#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0)
33+
#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0)
34+
#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0)
35+
#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0)
36+
#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0)
37+
#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0)
38+
#define BSP_FEATURE_GPT_OPS_SUPPORTED (0)
39+
// *UNCRUSTIFY-ON*
40+
#endif

‎drivers/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h‎

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,44 @@
1+
/*
2+
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
6+
7+
/*******************************************************************************************************************//**
8+
* @ingroup BSP_MCU
9+
* @defgroup BSP_MCU_RA6M5 RA6M5
10+
* @includedoc config_bsp_ra6m5_fsp.html
11+
* @{
12+
**********************************************************************************************************************/
13+
14+
/** @} (end defgroup BSP_MCU_RA6M5) */
15+
16+
#ifndef BSP_MCU_INFO_H
17+
#define BSP_MCU_INFO_H
18+
19+
/***********************************************************************************************************************
20+
* Includes <System Includes> , "Project Includes"
21+
**********************************************************************************************************************/
22+
23+
/* BSP MCU Specific Includes. */
24+
#include "bsp_elc.h"
25+
#include "bsp_feature.h"
26+
27+
/***********************************************************************************************************************
28+
* Macro definitions
29+
**********************************************************************************************************************/
30+
31+
/***********************************************************************************************************************
32+
* Typedef definitions
33+
**********************************************************************************************************************/
34+
typedef elc_event_t bsp_interrupt_event_t;
35+
36+
/***********************************************************************************************************************
37+
* Exported global variables
38+
**********************************************************************************************************************/
39+
40+
/***********************************************************************************************************************
41+
* Exported global functions (to be accessed by other files)
42+
**********************************************************************************************************************/
43+
44+
#endif

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m5/bsp_cfg.h‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
/*
2+
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
6+
7+
#ifndef BSP_CFG_H_
8+
#define BSP_CFG_H_
9+
10+
#include "soc.h"
11+
#include "bsp_clock_cfg.h"
12+
#include "bsp_mcu_family_cfg.h"
13+
14+
#define SUBCLOCK_STABILIZATION_MAX(x) ((x < 10000) ? x : 10000)
15+
16+
/* Disable BSP_CFG_PARAM_CHECKING_ENABLE as default to reduce code size */
17+
#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
18+
19+
/* Add for zephyr porting */
20+
#define BSP_CFG_INTERRUPT_INIT 0
21+
22+
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
23+
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (DT_NODE_HAS_STATUS(DT_NODELABEL(xtal), okay))
24+
#endif
25+
26+
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
27+
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (DT_PROP_OR(DT_NODELABEL(xtal), mosel, 0))
28+
#endif
29+
30+
/* Keep 0 as default as LPM is not supported */
31+
#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
32+
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (DT_PROP_OR(DT_NODELABEL(subclk), drive_capability, 0))
33+
#endif
34+
35+
#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
36+
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (DT_NODE_HAS_STATUS(DT_NODELABEL(subclk), okay))
37+
#endif
38+
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
39+
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS \
40+
SUBCLOCK_STABILIZATION_MAX((DT_PROP_OR(DT_NODELABEL(subclk), stabilization_time, 1000)))
41+
#endif
42+
43+
#define BSP_CFG_PFS_PROTECT (1)
44+
45+
#endif /* BSP_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m5/bsp_clock_cfg.h‎

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
/*
2+
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
6+
7+
#include <zephyr/devicetree.h>
8+
#include <zephyr/dt-bindings/clock/ra_clock.h>
9+
10+
#ifndef BSP_CLOCK_CFG_H_
11+
#define BSP_CLOCK_CFG_H_
12+
13+
#define BSP_CFG_CLOCKS_SECURE (0)
14+
#define BSP_CFG_CLOCKS_OVERRIDE (0)
15+
#define BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \
16+
(COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)))
17+
18+
#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
19+
20+
#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 16000000
21+
#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 16MHz */
22+
#elif DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 18000000
23+
#define BSP_CFG_HOCO_FREQUENCY 1 /* HOCO 18MHz */
24+
#elif DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 20000000
25+
#define BSP_CFG_HOCO_FREQUENCY 2 /* HOCO 20MHz */
26+
#else
27+
#error "Invalid HOCO frequency, only can be set to 16MHz, 18MHz, and 20MHz"
28+
#endif
29+
30+
#define BSP_CFG_PLL_SOURCE \
31+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
32+
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_1)
33+
#define BSP_CFG_PLL_MUL \
34+
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
35+
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
36+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
37+
: BSP_CLOCKS_PLL_MUL(0, 0)
38+
39+
#define BSP_CFG_PLL2_SOURCE \
40+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), source, RA_PLL_SOURCE_DISABLE)
41+
#define BSP_CFG_PLL2_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), div, RA_PLL_DIV_1)
42+
#define BSP_CFG_PLL2_MUL \
43+
DT_NODE_HAS_STATUS(DT_NODELABEL(pll2), okay) \
44+
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 0), \
45+
DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 1)) \
46+
: BSP_CLOCKS_PLL_MUL(0, 0)
47+
48+
#define BSP_CFG_CLOCK_SOURCE \
49+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \
50+
RA_PLL_SOURCE_DISABLE)
51+
52+
#define BSP_CFG_ICLK_DIV \
53+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_1)
54+
#define BSP_CFG_PCLKA_DIV \
55+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclka), clk_div, RA_SYS_CLOCK_DIV_2)
56+
#define BSP_CFG_PCLKB_DIV \
57+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_4)
58+
#define BSP_CFG_PCLKC_DIV \
59+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkc), clk_div, RA_SYS_CLOCK_DIV_4)
60+
#define BSP_CFG_PCLKD_DIV \
61+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_2)
62+
#define BSP_CFG_BCLK_DIV \
63+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(bclk), clk_div, RA_SYS_CLOCK_DIV_2)
64+
#define BSP_CFG_BCLK_OUTPUT BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(bclkout), clk_out_div, 2)
65+
#define BSP_CFG_FCLK_DIV \
66+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), clk_div, RA_SYS_CLOCK_DIV_4)
67+
68+
#define BSP_CFG_UCK_SOURCE \
69+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
70+
#define BSP_CFG_UCK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_div, 0)
71+
#define BSP_CFG_U60CK_SOURCE \
72+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(u60clk), clk_src, RA_CLOCK_SOURCE_DISABLE)
73+
#define BSP_CFG_U60CK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(u60clk), clk_div, 0)
74+
#define BSP_CFG_CLKOUT_SOURCE \
75+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
76+
#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
77+
#define BSP_CFG_CANFDCLK_SOURCE \
78+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(canfdclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
79+
#define BSP_CFG_CANFDCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(canfdclk), clk_div, 0)
80+
#define BSP_CFG_CECCLK_SOURCE \
81+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(cecclk), clk_src, \
82+
RA_CLOCK_SOURCE_DISABLE)
83+
#define BSP_CFG_CECCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(cecclk), clk_div, 0)
84+
#define BSP_CFG_OCTA_SOURCE \
85+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(octaspiclk), clk_src, \
86+
RA_CLOCK_SOURCE_DISABLE)
87+
#define BSP_CFG_OCTA_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(octaspiclk), clk_div, 0)
88+
89+
#endif /* BSP_CLOCK_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m5/bsp_mcu_device_cfg.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
/*
2+
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
6+
7+
#ifndef BSP_MCU_DEVICE_CFG_H_
8+
#define BSP_MCU_DEVICE_CFG_H_
9+
#define BSP_CFG_MCU_PART_SERIES (6)
10+
#endif /* BSP_MCU_DEVICE_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m5/bsp_mcu_device_pn_cfg.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
/*
2+
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
6+
7+
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
8+
#define BSP_MCU_DEVICE_PN_CFG_H_
9+
#define BSP_PACKAGE_PINS (176)
10+
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

0 commit comments

Comments
 (0)