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nhutnguyenkcKhiemNguyenT
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hal: renesas: rzt: Add Counter support for RZ/T series
Add CMTW FSP HAL driver to support Zephyr Counter driver for RZ/T2M Signed-off-by: Nhut Nguyen [email protected] Signed-off-by: Hieu Nguyen [email protected]
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‎drivers/rz/CMakeLists.txt‎

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zephyr_library_sources_ifdef(CONFIG_USE_RZ_FSP_MTU
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fsp/src/${SOC_SERIES_PREFIX}/r_mtu3/r_mtu3.c)
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zephyr_library_sources_ifdef(CONFIG_USE_RZ_FSP_CMTW
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fsp/src/${SOC_SERIES_PREFIX}/r_cmtw/r_cmtw.c)

‎drivers/rz/fsp/inc/instances/rzt/r_cmtw.h‎

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef R_CMTW_H
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#define R_CMTW_H
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/***********************************************************************************************************************
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* Includes
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**********************************************************************************************************************/
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#include "bsp_api.h"
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#include "r_cmtw_cfg.h"
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#include "r_timer_api.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/** Maximum number of clock counts in 16 bit timer. */
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#define CMTW_MAX_CLOCK_COUNTS (UINT32_MAX)
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/** Maximum period value allowed for CMTW. */
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#define CMTW_MAX_PERIOD_32BIT (UINT32_MAX + 1U)
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#define CMTW_MAX_PERIOD_16BIT (UINT16_MAX + 1U)
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/*******************************************************************************************************************//**
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* @addtogroup CMTW
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* @{
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/** Trigger edge for Input capture function. */
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typedef enum e_cmtw_source_edge
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{
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CMTW_SOURCE_EDGE_RISING = 0U, ///< Input capture trigger on rising edge
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CMTW_SOURCE_EDGE_FALLING = 1U, ///< Input capture trigger on falling edge
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CMTW_SOURCE_EDGE_BOTH = 2U, ///< Input capture trigger on both edge
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} cmtw_source_edge_t;
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/** Level of CMTW pin */
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typedef enum e_cmtw_output_pin
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{
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CMTW_OUTPUT_PIN_RETAIN = 0U, ///< Retain output value
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CMTW_OUTPUT_PIN_START_LEVEL_LOW = 1U, ///< Pin level low
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CMTW_OUTPUT_PIN_START_LEVEL_HIGH = 2U, ///< Pin level high
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} cmtw_output_pin_t;
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/** Clear source of CMWCNT */
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typedef enum e_cmtw_clear_source
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{
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CMTW_CLEAR_SOURCE_COMPARE_MATCH_CMWCOR = 0U, ///< Counter is cleared by CMWCOR compare match
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CMTW_CLEAR_SOURCE_DISABLED = 1U, ///< Counter is not cleared
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CMTW_CLEAR_SOURCE_INPUT_CAPTURE_CMWICR0 = 4U, ///< Counter is cleared by CMWICR0 input capture
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CMTW_CLEAR_SOURCE_INPUT_CAPTURE_CMWICR1 = 5U, ///< Counter is cleared by CMWICR1 input capture
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CMTW_CLEAR_SOURCE_COMPARE_MATCH_CMWOCR0 = 6U, ///< Counter is cleared by CMWOCR0 output compare
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CMTW_CLEAR_SOURCE_COMPARE_MATCH_CMWOCR1 = 7U, ///< Counter is cleared by CMWOCR1 output compare
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} cmtw_clear_source_t;
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/** Output pins, used to select */
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typedef enum e_cmtw_io_pin
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{
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CMTW_IO_PIN_TOC0 = 0, ///< TOC0
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CMTW_IO_PIN_TOC1 = 1, ///< TOC1
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CMTW_IO_PIN_TOC0_AND_TOC1 = 2, ///< TOC0 and TOC1
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} cmtw_io_pin_t;
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typedef enum e_cmtw_output_control
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{
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CMTW_OUTPUT_CONTROL_DISABLED = 0U, ///< OutputCompare disabled
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CMTW_OUTPUT_CONTROL_ENABLED = 1U, ///< OutputCompare enabled
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} cmtw_output_control_t;
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typedef enum e_cmtw_input_control
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{
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CMTW_INPUT_CONTROL_DISABLED = 0U, ///< InputCapture disabled
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CMTW_INPUT_CONTROL_ENABLED = 1U, ///< InputCapture enabled
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} cmtw_input_control_t;
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/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */
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typedef struct st_cmtw_instance_ctrl
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{
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uint32_t open; // Whether or not channel is open
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const timer_cfg_t * p_cfg; // Pointer to initial configurations
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R_CMTW0_Type * p_reg; // Base register for this channel
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uint32_t period; // Current timer period (counts)
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uint32_t output_channel_mask; // Output channel bitmask
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void (* p_callback)(timer_callback_args_t *); // Pointer to callback that is called when a timer_event_t occurs.
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timer_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
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void const * p_context; // Pointer to context to be passed into callback function
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} cmtw_instance_ctrl_t;
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/** Optional CMTW extension data structure.*/
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typedef struct st_cmtw_extended_cfg
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{
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cmtw_output_pin_t toc0; ///< Configure TOC0 pin
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cmtw_output_pin_t toc1; ///< Configure TOC1 pin
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cmtw_output_control_t toc0_control; ///< OutputCompare0 enable setting
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cmtw_output_control_t toc1_control; ///< OutputCompare1 enable setting
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cmtw_source_edge_t capture_ic0_source; ///< Event sources that trigger capture of TIC0
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cmtw_source_edge_t capture_ic1_source; ///< Event sources that trigger capture of TIC1
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cmtw_input_control_t ic0_control; ///< InputCapture0 enable setting
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cmtw_input_control_t ic1_control; ///< InputCapture1 enable setting
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cmtw_clear_source_t clear_source; ///< Counter clear source
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timer_variant_t counter_size; ///< Timer counter size
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uint8_t capture_ic0_ipl; ///< InputCapture 0 interrupt priority
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uint8_t capture_ic1_ipl; ///< InputCapture 1 interrupt priority
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IRQn_Type capture_ic0_irq; ///< InputCapture 0 interrupt
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IRQn_Type capture_ic1_irq; ///< InputCapture 1 interrupt
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uint8_t compare_oc0_ipl; ///< OutputCompare 0 interrupt priority
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uint8_t compare_oc1_ipl; ///< OutputCompare 1 interrupt priority
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IRQn_Type compare_oc0_irq; ///< OutputCompare 0 interrupt
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IRQn_Type compare_oc1_irq; ///< OutputCompare 1 interrupt
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} cmtw_extended_cfg_t;
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/**********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/** @cond INC_HEADER_DEFS_SEC */
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/** Filled in Interface API structure for this Instance. */
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extern const timer_api_t g_timer_on_cmtw;
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/** @endcond */
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fsp_err_t R_CMTW_Close(timer_ctrl_t * const p_ctrl);
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fsp_err_t R_CMTW_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts);
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fsp_err_t R_CMTW_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
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fsp_err_t R_CMTW_Reset(timer_ctrl_t * const p_ctrl);
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fsp_err_t R_CMTW_Start(timer_ctrl_t * const p_ctrl);
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fsp_err_t R_CMTW_Enable(timer_ctrl_t * const p_ctrl);
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fsp_err_t R_CMTW_Disable(timer_ctrl_t * const p_ctrl);
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fsp_err_t R_CMTW_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
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fsp_err_t R_CMTW_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
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fsp_err_t R_CMTW_Stop(timer_ctrl_t * const p_ctrl);
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fsp_err_t R_CMTW_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
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fsp_err_t R_CMTW_OutputEnable(timer_ctrl_t * const p_ctrl, cmtw_io_pin_t pin);
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fsp_err_t R_CMTW_OutputDisable(timer_ctrl_t * const p_ctrl, cmtw_io_pin_t pin);
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fsp_err_t R_CMTW_CallbackSet(timer_ctrl_t * const p_ctrl,
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void ( * p_callback)(timer_callback_args_t *),
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void const * const p_context,
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timer_callback_args_t * const p_callback_memory);
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/*******************************************************************************************************************//**
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* @} (end defgroup CMTW)
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**********************************************************************************************************************/
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/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif // R_CMTW_H

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