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| 1 | +/* |
| 2 | +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates |
| 3 | +* |
| 4 | +* SPDX-License-Identifier: BSD-3-Clause |
| 5 | +*/ |
| 6 | + |
| 7 | +#ifndef R_SPI_H |
| 8 | +#define R_SPI_H |
| 9 | + |
| 10 | +/*******************************************************************************************************************//** |
| 11 | + * @addtogroup SPI |
| 12 | + * @{ |
| 13 | + **********************************************************************************************************************/ |
| 14 | + |
| 15 | +/*********************************************************************************************************************** |
| 16 | + * Includes |
| 17 | + **********************************************************************************************************************/ |
| 18 | +#include "r_spi_api.h" |
| 19 | + |
| 20 | +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ |
| 21 | +FSP_HEADER |
| 22 | + |
| 23 | +/*********************************************************************************************************************** |
| 24 | + * Macro definitions |
| 25 | + **********************************************************************************************************************/ |
| 26 | + |
| 27 | +/************************************************************************************************* |
| 28 | + * Type defines for the SPI interface API |
| 29 | + *************************************************************************************************/ |
| 30 | + |
| 31 | +/** 3-Wire or 4-Wire mode. */ |
| 32 | +typedef enum e_spi_ssl_mode |
| 33 | +{ |
| 34 | + SPI_SSL_MODE_SPI, ///< SPI operation (4-wire method) |
| 35 | + SPI_SSL_MODE_CLK_SYN ///< Clock Synchronous operation (3-wire method) |
| 36 | +} spi_ssl_mode_t; |
| 37 | + |
| 38 | +/** Transmit Only (Half Duplex), or Full Duplex. */ |
| 39 | +typedef enum e_spi_communication |
| 40 | +{ |
| 41 | + SPI_COMMUNICATION_FULL_DUPLEX, ///< Full-Duplex synchronous serial communication |
| 42 | + SPI_COMMUNICATION_TRANSMIT_ONLY ///< Transit only serial communication |
| 43 | +} spi_communication_t; |
| 44 | + |
| 45 | +/** Slave Select Polarity. */ |
| 46 | +typedef enum e_spi_sslp |
| 47 | +{ |
| 48 | + SPI_SSLP_LOW, ///< SSLP signal polarity active low |
| 49 | + SPI_SSLP_HIGH ///< SSLP signal polarity active high |
| 50 | +} spi_ssl_polarity_t; |
| 51 | + |
| 52 | +/** The Slave Select Line */ |
| 53 | +typedef enum e_spi_ssl_select |
| 54 | +{ |
| 55 | + SPI_SSL_SELECT_SSL0, ///< Select SSL0 |
| 56 | + SPI_SSL_SELECT_SSL1, ///< Select SSL1 |
| 57 | + SPI_SSL_SELECT_SSL2, ///< Select SSL2 |
| 58 | + SPI_SSL_SELECT_SSL3 ///< Select SSL3 |
| 59 | +} spi_ssl_select_t; |
| 60 | + |
| 61 | +/** MOSI Idle Behavior. */ |
| 62 | +typedef enum e_spi_mosi_idle_value_fixing |
| 63 | +{ |
| 64 | + SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, ///< MOSI output value=value set in MOIFV bit |
| 65 | + SPI_MOSI_IDLE_VALUE_FIXING_LOW, ///< MOSIn level low during MOSI idling |
| 66 | + SPI_MOSI_IDLE_VALUE_FIXING_HIGH ///< MOSIn level high during MOSI idling |
| 67 | +} spi_mosi_idle_value_fixing_t; |
| 68 | + |
| 69 | +/** Parity Mode */ |
| 70 | +typedef enum e_spi_parity_mode |
| 71 | +{ |
| 72 | + SPI_PARITY_MODE_DISABLE, ///< Disable parity |
| 73 | + SPI_PARITY_MODE_ODD, ///< Select even parity |
| 74 | + SPI_PARITY_MODE_EVEN ///< Select odd parity |
| 75 | +} spi_parity_t; |
| 76 | + |
| 77 | +/** Byte Swapping Enable/Disable. */ |
| 78 | +typedef enum |
| 79 | +{ |
| 80 | + SPI_BYTE_SWAP_DISABLE = 0, ///< Disable Byte swapping for 16/32-Bit transfers |
| 81 | + SPI_BYTE_SWAP_ENABLE ///< Enable Byte swapping for 16/32-Bit transfers |
| 82 | +} spi_byte_swap_t; |
| 83 | + |
| 84 | +/** Delay count for SPI delay settings. */ |
| 85 | +typedef enum e_spi_clock_delay_count |
| 86 | +{ |
| 87 | + SPI_DELAY_COUNT_1, ///< Set RSPCK delay count to 1 RSPCK |
| 88 | + SPI_DELAY_COUNT_2, ///< Set RSPCK delay count to 2 RSPCK |
| 89 | + SPI_DELAY_COUNT_3, ///< Set RSPCK delay count to 3 RSPCK |
| 90 | + SPI_DELAY_COUNT_4, ///< Set RSPCK delay count to 4 RSPCK |
| 91 | + SPI_DELAY_COUNT_5, ///< Set RSPCK delay count to 5 RSPCK |
| 92 | + SPI_DELAY_COUNT_6, ///< Set RSPCK delay count to 6 RSPCK |
| 93 | + SPI_DELAY_COUNT_7, ///< Set RSPCK delay count to 7 RSPCK |
| 94 | + SPI_DELAY_COUNT_8 ///< Set RSPCK delay count to 8 RSPCK |
| 95 | +} spi_delay_count_t; |
| 96 | + |
| 97 | +/** SPI Clock Divider settings. */ |
| 98 | +typedef struct |
| 99 | +{ |
| 100 | + uint8_t spbr; ///< SPBR register setting |
| 101 | + uint8_t brdv : 2; ///< BRDV setting in SPCMD0 |
| 102 | +} rspck_div_setting_t; |
| 103 | + |
| 104 | +/** Extended SPI interface configuration */ |
| 105 | +typedef struct st_spi_extended_cfg |
| 106 | +{ |
| 107 | + spi_ssl_mode_t spi_clksyn; ///< Select spi or clock syn mode operation |
| 108 | + spi_communication_t spi_comm; ///< Select full-duplex or transmit-only communication |
| 109 | + spi_ssl_polarity_t ssl_polarity; ///< Select SSLn signal polarity |
| 110 | + spi_ssl_select_t ssl_select; ///< Select which slave to use: 0-SSL0, 1-SSL1, 2-SSL2, 3-SSL3 |
| 111 | + spi_mosi_idle_value_fixing_t mosi_idle; ///< Select MOSI idle fixed value and selection |
| 112 | + spi_parity_t parity; ///< Select parity and enable/disable parity |
| 113 | + spi_byte_swap_t byte_swap; ///< Select byte swap mode |
| 114 | + rspck_div_setting_t spck_div; ///< Register values for configuring the SPI Clock Divider. |
| 115 | + spi_delay_count_t spck_delay; ///< SPI Clock Delay Register Setting |
| 116 | + spi_delay_count_t ssl_negation_delay; ///< SPI Slave Select Negation Delay Register Setting |
| 117 | + spi_delay_count_t next_access_delay; ///< SPI Next-Access Delay Register Setting |
| 118 | +} spi_extended_cfg_t; |
| 119 | + |
| 120 | +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_api_t::open is called. */ |
| 121 | +typedef struct st_spi_instance_ctrl |
| 122 | +{ |
| 123 | + uint32_t open; ///< Indicates whether the open() API has been successfully called. |
| 124 | + spi_cfg_t const * p_cfg; ///< Pointer to instance configuration |
| 125 | + R_SPI0_Type * p_regs; ///< Base register for this channel |
| 126 | + void const * p_tx_data; ///< Buffer to transmit |
| 127 | + void * p_rx_data; ///< Buffer to receive |
| 128 | + uint32_t tx_count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) |
| 129 | + uint32_t rx_count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) |
| 130 | + uint32_t count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) |
| 131 | + spi_bit_width_t bit_width; ///< Bits per Data frame (8-bit, 16-bit, 32-bit) |
| 132 | + |
| 133 | + /* Pointer to callback and optional working memory */ |
| 134 | + void (* p_callback)(spi_callback_args_t *); |
| 135 | + spi_callback_args_t * p_callback_memory; |
| 136 | + |
| 137 | + /* Pointer to context to be passed into callback function */ |
| 138 | + void const * p_context; |
| 139 | +} spi_instance_ctrl_t; |
| 140 | + |
| 141 | +/********************************************************************************************************************** |
| 142 | + * Exported global variables |
| 143 | + **********************************************************************************************************************/ |
| 144 | + |
| 145 | +/** @cond INC_HEADER_DEFS_SEC */ |
| 146 | +/** Filled in Interface API structure for this Instance. */ |
| 147 | +extern const spi_api_t g_spi_on_spi; |
| 148 | + |
| 149 | +/** @endcond */ |
| 150 | + |
| 151 | +/*********************************************************************************************************************** |
| 152 | + * Public APIs |
| 153 | + **********************************************************************************************************************/ |
| 154 | +fsp_err_t R_SPI_Open(spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg); |
| 155 | + |
| 156 | +fsp_err_t R_SPI_Read(spi_ctrl_t * const p_api_ctrl, |
| 157 | + void * p_dest, |
| 158 | + uint32_t const length, |
| 159 | + spi_bit_width_t const bit_width); |
| 160 | + |
| 161 | +fsp_err_t R_SPI_Write(spi_ctrl_t * const p_api_ctrl, |
| 162 | + void const * p_src, |
| 163 | + uint32_t const length, |
| 164 | + spi_bit_width_t const bit_width); |
| 165 | + |
| 166 | +fsp_err_t R_SPI_WriteRead(spi_ctrl_t * const p_api_ctrl, |
| 167 | + void const * p_src, |
| 168 | + void * p_dest, |
| 169 | + uint32_t const length, |
| 170 | + spi_bit_width_t const bit_width); |
| 171 | + |
| 172 | +fsp_err_t R_SPI_Close(spi_ctrl_t * const p_api_ctrl); |
| 173 | + |
| 174 | +fsp_err_t R_SPI_CalculateBitrate(uint32_t bitrate, rspck_div_setting_t * spck_div); |
| 175 | +fsp_err_t R_SPI_CallbackSet(spi_ctrl_t * const p_api_ctrl, |
| 176 | + void ( * p_callback)(spi_callback_args_t *), |
| 177 | + void const * const p_context, |
| 178 | + spi_callback_args_t * const p_callback_memory); |
| 179 | + |
| 180 | +/*******************************************************************************************************************//** |
| 181 | + * @} (end ingroup SPI) |
| 182 | + **********************************************************************************************************************/ |
| 183 | + |
| 184 | +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ |
| 185 | +FSP_FOOTER |
| 186 | + |
| 187 | +#endif |
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