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| 1 | +/* |
| 2 | +* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates |
| 3 | +* |
| 4 | +* SPDX-License-Identifier: BSD-3-Clause |
| 5 | +*/ |
| 6 | + |
| 7 | +/*******************************************************************************************************************//** |
| 8 | + * @addtogroup DMAC_B |
| 9 | + * @{ |
| 10 | + **********************************************************************************************************************/ |
| 11 | + |
| 12 | +#ifndef R_DMAC_B_H |
| 13 | +#define R_DMAC_B_H |
| 14 | + |
| 15 | +/*********************************************************************************************************************** |
| 16 | + * Includes |
| 17 | + **********************************************************************************************************************/ |
| 18 | +#include "bsp_api.h" |
| 19 | +#include "r_transfer_api.h" |
| 20 | + |
| 21 | +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ |
| 22 | +FSP_HEADER |
| 23 | + |
| 24 | +/*********************************************************************************************************************** |
| 25 | + * Macro definitions |
| 26 | + **********************************************************************************************************************/ |
| 27 | + |
| 28 | +/** Max configurable number of transfers in TRANSFER_MODE_NORMAL. */ |
| 29 | +#define DMAC_B_MAX_NORMAL_TRANSFER_LENGTH (0xFFFFFFFF) |
| 30 | + |
| 31 | +/** Max number of transfers per block in TRANSFER_MODE_BLOCK */ |
| 32 | +#define DMAC_B_MAX_BLOCK_TRANSFER_LENGTH (0xFFFFFFFF) |
| 33 | + |
| 34 | +/*********************************************************************************************************************** |
| 35 | + * Typedef definitions |
| 36 | + **********************************************************************************************************************/ |
| 37 | + |
| 38 | +typedef transfer_callback_args_t dmac_b_callback_args_t; |
| 39 | + |
| 40 | +/** Transfer size specifies the size of each individual transfer. */ |
| 41 | +typedef enum e_dmac_b_transfer_size |
| 42 | +{ |
| 43 | + DMAC_B_TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value. |
| 44 | + DMAC_B_TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value. |
| 45 | + DMAC_B_TRANSFER_SIZE_4_BYTE = 2, ///< Each transfer transfers a 32-bit value. |
| 46 | + DMAC_B_TRANSFER_SIZE_8_BYTE = 3, ///< Each transfer transfers a 64-bit value. |
| 47 | + DMAC_B_TRANSFER_SIZE_16_BYTE = 4, ///< Each transfer transfers a 128-bit value. |
| 48 | + DMAC_B_TRANSFER_SIZE_32_BYTE = 5, ///< Each transfer transfers a 256-bit value. |
| 49 | + DMAC_B_TRANSFER_SIZE_64_BYTE = 6, ///< Each transfer transfers a 512-bit value. |
| 50 | + DMAC_B_TRANSFER_SIZE_128_BYTE = 7, ///< Each transfer transfers a 1024-bit value. |
| 51 | +} dmac_b_transfer_size_t; |
| 52 | + |
| 53 | +/** DACK output mode. See RZ/T2M hardware manual Table 14.19 DMA Transfer Request Detection Operation Setting Table. */ |
| 54 | +typedef enum e_dmac_b_ack_mode |
| 55 | +{ |
| 56 | + DMAC_B_ACK_MODE_LEVEL_MODE = 1, ///< Level mode. |
| 57 | + DMAC_B_ACK_MODE_BUS_CYCLE_MODE = 2, ///< Bus cycle mode. |
| 58 | + DMAC_B_ACK_MODE_MASK_DACK_OUTPUT = 4, ///< Output is masked. |
| 59 | +} dmac_b_ack_mode_t; |
| 60 | + |
| 61 | +#ifndef BSP_OVERRIDE_DMAC_B_EXTERNAL_DETECTION_T |
| 62 | + |
| 63 | +/** Detection method of the external DMA request signal. See RZ/T2M hardware manual Table 14.19 DMA Transfer Request Detection Operation Setting Table. */ |
| 64 | +typedef enum e_dmac_b_external_detection |
| 65 | +{ |
| 66 | + DMAC_B_EXTERNAL_DETECTION_LOW_LEVEL = 0, ///< Low level detection. |
| 67 | + DMAC_B_EXTERNAL_DETECTION_FALLING_EDGE = 1, ///< Falling edge detection. |
| 68 | + DMAC_B_EXTERNAL_DETECTION_RISING_EDGE = 2, ///< Rising edge detection. |
| 69 | + DMAC_B_EXTERNAL_DETECTION_FALLING_RISING_EDGE = 3, ///< Falling/Rising edge detection. |
| 70 | +} dmac_b_external_detection_t; |
| 71 | + |
| 72 | +#endif |
| 73 | + |
| 74 | +/** Detection method of the internal DMA request signal. See RZ/T2M hardware manual Table 14.19 DMA Transfer Request Detection Operation Setting Table. */ |
| 75 | +typedef enum e_dmac_b_internal_detection |
| 76 | +{ |
| 77 | + DMAC_B_INTERNAL_DETECTION_NO_DETECTION = 0, ///< Not using hardware detection. |
| 78 | + DMAC_B_INTERNAL_DETECTION_FALLING_EDGE = 1, ///< Falling edge detection. |
| 79 | + DMAC_B_INTERNAL_DETECTION_RISING_EDGE = 2, ///< Rising edge detection. |
| 80 | + DMAC_B_INTERNAL_DETECTION_LOW_LEVEL = 5, ///< Low level detection. |
| 81 | + DMAC_B_INTERNAL_DETECTION_HIGH_LEVEL = 6, ///< High level detection. |
| 82 | +} dmac_b_internal_detection_t; |
| 83 | + |
| 84 | +/** DMA activation request source select. See RZ/T2M hardware manual Table 14.19 DMA Transfer Request Detection Operation Setting Table. */ |
| 85 | +typedef enum e_dmac_b_request_direction |
| 86 | +{ |
| 87 | + DMAC_B_REQUEST_DIRECTION_SOURCE_MODULE = 0, ///< Requested by a transfer source module. |
| 88 | + DMAC_B_REQUEST_DIRECTION_DESTINATION_MODULE = 1, ///< Requested by a transfer destination module. |
| 89 | +} dmac_b_request_direction_t; |
| 90 | + |
| 91 | +/** Select the Next register set to be executed next. */ |
| 92 | +typedef enum e_dmac_b_continuous_setting |
| 93 | +{ |
| 94 | + DMAC_B_CONTINUOUS_SETTING_TRANSFER_ONCE = 0x0, ///< Transfer only once using the Next0 register set. |
| 95 | + DMAC_B_CONTINUOUS_SETTING_TRANSFER_ALTERNATELY = 0x3, ///< Transfers are performed alternately with the Next0 register set and the Next1 register set. |
| 96 | +} dmac_b_continuous_setting_t; |
| 97 | + |
| 98 | +/** Register set settings. */ |
| 99 | +typedef struct st_dmac_b_register_set_setting_t |
| 100 | +{ |
| 101 | + void const * p_src; ///< Source pointer. |
| 102 | + void * p_dest; ///< Destination pointer. |
| 103 | + uint32_t length; ///< Transfer byte. |
| 104 | +} dmac_b_register_set_setting_t; |
| 105 | + |
| 106 | +/** DMAC channel scheduling. */ |
| 107 | +typedef enum e_dmac_b_channel_scheduling |
| 108 | +{ |
| 109 | + DMAC_B_CHANNEL_SCHEDULING_FIXED = 0, ///< Fixed priority mode. |
| 110 | + DMAC_B_CHANNEL_SCHEDULING_ROUND_ROBIN = 1, ///< Round-robin mode. |
| 111 | +} dmac_b_channel_scheduling_t; |
| 112 | + |
| 113 | +/** DMAC mode setting. */ |
| 114 | +typedef enum e_dmac_b_mode_select |
| 115 | +{ |
| 116 | + DMAC_B_MODE_SELECT_REGISTER = 0, ///< Register mode. |
| 117 | + DMAC_B_MODE_SELECT_LINK = 1, ///< Link mode. |
| 118 | +} dmac_b_mode_select_t; |
| 119 | + |
| 120 | +/** Control block used by driver. DO NOT INITIALIZE - this structure will be initialized in @ref transfer_api_t::open. */ |
| 121 | +typedef struct st_dmac_b_instance_ctrl |
| 122 | +{ |
| 123 | + uint32_t open; // Driver ID |
| 124 | + |
| 125 | + transfer_cfg_t const * p_cfg; |
| 126 | + |
| 127 | + /* Pointer to base register. */ |
| 128 | + R_DMAC_B0_Type * p_reg; |
| 129 | + |
| 130 | + void (* p_callback)(dmac_b_callback_args_t *); // Pointer to callback |
| 131 | + dmac_b_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory |
| 132 | + void const * p_context; // Pointer to context to be passed into callback function |
| 133 | +} dmac_b_instance_ctrl_t; |
| 134 | + |
| 135 | +/** DMAC transfer configuration extension. This extension is required. */ |
| 136 | +typedef struct st_dmac_b_extended_cfg |
| 137 | +{ |
| 138 | + uint8_t unit; ///< Unit number |
| 139 | + uint8_t channel; ///< Channel number |
| 140 | + IRQn_Type dmac_int_irq; ///< DMAC interrupt number |
| 141 | + uint8_t dmac_int_ipl; ///< DMAC interrupt priority |
| 142 | + |
| 143 | + /** Select which event will trigger the transfer. */ |
| 144 | + dmac_trigger_event_t activation_source; |
| 145 | + dmac_b_ack_mode_t ack_mode; ///< DACK output mode |
| 146 | + dmac_b_external_input_pin_t dreq_input_pin; ///< DREQ input pin name |
| 147 | + dmac_b_external_output_pin_t ack_output_pin; ///< DACK output pin name |
| 148 | + dmac_b_external_output_pin_t tend_output_pin; ///< TEND output pin name |
| 149 | + dmac_b_external_detection_t external_detection_mode; ///< DMAC request detection method for external pin |
| 150 | + dmac_b_internal_detection_t internal_detection_mode; ///< DMAC request detection method for internal pin |
| 151 | + dmac_b_request_direction_t activation_request_source_select; ///< DMAC activation request source |
| 152 | + |
| 153 | + dmac_b_mode_select_t dmac_mode; ///< DMAC Mode |
| 154 | + dmac_b_continuous_setting_t continuous_setting; ///< Next register operation settings |
| 155 | + uint16_t transfer_interval; ///< DMA transfer interval |
| 156 | + dmac_b_channel_scheduling_t channel_scheduling; ///< DMA channel scheduling |
| 157 | + |
| 158 | + /** Callback for transfer end interrupt. */ |
| 159 | + void (* p_callback)(dmac_b_callback_args_t * cb_data); |
| 160 | + |
| 161 | + /** Placeholder for user data. Passed to the user p_callback in ::transfer_callback_args_t. */ |
| 162 | + void const * p_context; |
| 163 | +} dmac_b_extended_cfg_t; |
| 164 | + |
| 165 | +/** DMAC transfer information configuration extension. This extension is required. */ |
| 166 | +typedef struct st_dmac_b_extended_info |
| 167 | +{ |
| 168 | + /** Select number of source bytes to transfer at once. */ |
| 169 | + dmac_b_transfer_size_t src_size; |
| 170 | + |
| 171 | + /** Select number of destination bytes to transfer at once. */ |
| 172 | + dmac_b_transfer_size_t dest_size; |
| 173 | + |
| 174 | + /** Next1 Register set settings */ |
| 175 | + dmac_b_register_set_setting_t * p_next1_register_setting; |
| 176 | +} dmac_b_extended_info_t; |
| 177 | + |
| 178 | +/********************************************************************************************************************** |
| 179 | + * Exported global variables |
| 180 | + **********************************************************************************************************************/ |
| 181 | + |
| 182 | +/** @cond INC_HEADER_DEFS_SEC */ |
| 183 | +/** Filled in Interface API structure for this Instance. */ |
| 184 | +extern const transfer_api_t g_transfer_on_dmac_b; |
| 185 | + |
| 186 | +/** @endcond */ |
| 187 | + |
| 188 | +/*********************************************************************************************************************** |
| 189 | + * Public Function Prototypes |
| 190 | + **********************************************************************************************************************/ |
| 191 | +fsp_err_t R_DMAC_B_Open(transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg); |
| 192 | +fsp_err_t R_DMAC_B_Reconfigure(transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info); |
| 193 | +fsp_err_t R_DMAC_B_Reset(transfer_ctrl_t * const p_api_ctrl, |
| 194 | + void const * volatile p_src, |
| 195 | + void * volatile p_dest, |
| 196 | + uint16_t const num_transfers); |
| 197 | +fsp_err_t R_DMAC_B_SoftwareStart(transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode); |
| 198 | +fsp_err_t R_DMAC_B_SoftwareStop(transfer_ctrl_t * const p_api_ctrl); |
| 199 | +fsp_err_t R_DMAC_B_Enable(transfer_ctrl_t * const p_api_ctrl); |
| 200 | +fsp_err_t R_DMAC_B_Disable(transfer_ctrl_t * const p_api_ctrl); |
| 201 | +fsp_err_t R_DMAC_B_InfoGet(transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_info); |
| 202 | +fsp_err_t R_DMAC_B_Close(transfer_ctrl_t * const p_api_ctrl); |
| 203 | +fsp_err_t R_DMAC_B_Reload(transfer_ctrl_t * const p_api_ctrl, |
| 204 | + void const * p_src, |
| 205 | + void * p_dest, |
| 206 | + uint32_t const num_transfers); |
| 207 | +fsp_err_t R_DMAC_B_CallbackSet(transfer_ctrl_t * const p_api_ctrl, |
| 208 | + void ( * p_callback)(dmac_b_callback_args_t *), |
| 209 | + void const * const p_context, |
| 210 | + dmac_b_callback_args_t * const p_callback_memory); |
| 211 | + |
| 212 | +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ |
| 213 | +FSP_FOOTER |
| 214 | + |
| 215 | +#endif |
| 216 | + |
| 217 | +/*******************************************************************************************************************//** |
| 218 | + * @} (end defgroup DMAC) |
| 219 | + **********************************************************************************************************************/ |
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