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nhutnguyenkcKhiemNguyenT
nhutnguyenkc
authored and
KhiemNguyenT
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hal: renesas: rza: Add clock control support for RZ/A3UL
Add clock control support for RZ/A3UL. Clock frequency and clock settings are taken from dts. Signed-off-by: Nhut Nguyen <[email protected]> Signed-off-by: Quang Le <[email protected]>
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‎zephyr/rz/rz_cfg/fsp_cfg/bsp/rza3ul/bsp_clock_cfg.h‎

Lines changed: 96 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -4,55 +4,102 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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7+
#include <zephyr/devicetree.h>
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#ifndef BSP_CLOCK_CFG_H_
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#define BSP_CLOCK_CFG_H_
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#define BSP_CFG_CLOCKS_SECURE (0)
10-
#define BSP_CFG_CLOCKS_OVERRIDE (0)
11-
#define BSP_CFG_CLOCK_OSCCLK_HZ (24000000) /* OSC 24000000Hz */
12-
#define BSP_CFG_CLOCK_PLL1_HZ (1000000000) /* PLL1 1000000000Hz */
13-
#define BSP_CFG_DIVPL1_SET_DIV (BSP_CLOCKS_PL1_DIV_1) /* ICLK Div /1 */
14-
#define BSP_CFG_CLOCK_ICLK_HZ (1000000000) /* ICLK 1000000000Hz */
15-
#define BSP_CFG_CLOCK_PLL2_1600_HZ (1600000000) /* PLL2 1600000000Hz */
16-
#define BSP_CFG_CLOCK_PLL2_533_HZ (533000000) /* PLL2 533000000Hz */
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#define BSP_CFG_SEL_SDHI0_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2_400) /* SD0CLK Sel: 400MHz */
18-
#define BSP_CFG_CLOCK_SD0CLK_HZ (400000000) /* SD0CLK 400000000Hz */
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#define BSP_CFG_SEL_SDHI1_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2_400) /* SD1CLK Sel: 400MHz */
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#define BSP_CFG_CLOCK_SD1CLK_HZ (400000000) /* SD1CLK 400000000Hz */
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#define BSP_CFG_DIVPL2A_SET_DIV (BSP_CLOCKS_PL2A_DIV_1) /* P0CLK Div /1 */
22-
#define BSP_CFG_CLOCK_P0CLK_HZ (100000000) /* P0CLK 100000000Hz */
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#define BSP_CFG_CLOCK_TSUCLK_HZ (80000000) /* TSUCLK 80000000Hz */
24-
#define BSP_CFG_CLOCK_PLL3_1600_HZ (1600000000) /* PLL3 1600000000Hz */
25-
#define BSP_CFG_CLOCK_ATCLK_HZ (400000000) /* ATCLK 400000000Hz */
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#define BSP_CFG_DIVPL3CLK200FIX_SET_DIV (BSP_CLOCKS_PL3CLK200FIX_DIV_1) /* I2CLK Div /1 */
27-
#define BSP_CFG_CLOCK_I2CLK_HZ (200000000) /* I2CLK 200000000Hz */
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#define BSP_CFG_DIVPL3B_SET_DIV (BSP_CLOCKS_PL3B_DIV_1) /* P1CLK Div /1 */
29-
#define BSP_CFG_CLOCK_P1CLK_HZ (200000000) /* P1CLK 200000000Hz */
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#define BSP_CFG_CLOCK_M0CLK_HZ (200000000) /* M0CLK 200000000Hz */
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#define BSP_CFG_CLOCK_ZTCLK_HZ (100000000) /* ZTCLK 100000000Hz */
32-
#define BSP_CFG_DIVPL3A_SET_DIV (BSP_CLOCKS_PL3A_DIV_1) /* P2CLK Div /1 */
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#define BSP_CFG_CLOCK_P2CLK_HZ (100000000) /* P2CLK 100000000Hz */
34-
#define BSP_CFG_CLOCK_PLL3_533_HZ (533000000) /* PLL3 533000000Hz */
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#define BSP_CFG_SEL_PLL3_3_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL3_533) /* PLL3_3 Sel: 533MHz */
36-
#define BSP_CFG_DIVPL3C_SET_DIV (BSP_CLOCKS_PL3C_DIV_2) /* PLL3_3 Div /2 */
37-
#define BSP_CFG_CLOCK_SPI0CLK_HZ (133250000) /* SPI0CLK 133250000Hz */
38-
#define BSP_CFG_CLOCK_SPI_QSPI0_SPCLK_HZ (66625000) /* SPI QSPI0_SPCLK 66625000Hz */
39-
#define BSP_CFG_CLOCK_PLL3_400_HZ (400000000) /* PLL3 400000000Hz */
40-
#define BSP_CFG_CLOCK_SPI1CLK_HZ (66625000) /* SPI1CLK 66625000Hz */
41-
#define BSP_CFG_CLOCK_M2CLK_HZ (266500000) /* M2CLK 266500000Hz */
42-
#define BSP_CFG_SEL_PLL3_5_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400) /* PLL3_5 Sel: 400MHz */
43-
#define BSP_CFG_DIVPL3F_SET_DIV (BSP_CLOCKS_PL3F_DIV_1) /* PLL3_5 Div /1 */
44-
#define BSP_CFG_CLOCK_OC0CLK_HZ (200000000) /* OC0CLK 200000000Hz */
45-
#define BSP_CFG_CLOCK_OCTA_QSPI0_SPCLK_HZ (100000000) /* Octa QSPI0_SPCLK 100000000Hz */
46-
#define BSP_CFG_CLOCK_OC1CLK_HZ (100000000) /* OC1CLK 100000000Hz */
47-
#define BSP_CFG_CLOCK_PLL4_HZ (1600000000) /* PLL4 1600MHz */
48-
#define BSP_CFG_SEL_PLL4_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL4_1600) /* Sel: PLL4 */
49-
#define BSP_CFG_CLOCK_S0CLK_HZ (800000000) /* S0CLK 800000000Hz */
50-
#define BSP_CFG_CLOCK_PLL5_1500_HZ (1500000000) /* PLL5 1500000000Hz */
51-
#define BSP_CFG_DIVDSIA_SET_DIV (BSP_CLOCKS_DSIA_DIV_2) /* DSI_A Div /2 */
52-
#define BSP_CFG_DIVDSIB_SET_DIV (BSP_CLOCKS_DSIB_DIV_1) /* DSI_B Div /1 */
53-
#define BSP_CFG_CLOCK_M3CLK_HZ (750000000) /* M3CLK 750000000Hz */
54-
#define BSP_CFG_CLOCK_PLL5_500_HZ (500000000) /* PLL5 500000000Hz */
55-
#define BSP_CFG_CLOCK_PLL6_HZ (500000000) /* PLL6 500000000Hz */
56-
#define BSP_CFG_SEL_PLL6_2_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250) /* PLL6_2 Sel: 250MHz (from PLL6) */
57-
#define BSP_CFG_CLOCK_HPCLK_HZ (250000000) /* HPCLK 250000000Hz */
11+
12+
#define RZ_CPG_DIV(id) DT_PROP_OR(DT_NODELABEL(id), div, 1)
13+
#define RZ_CPG_PLL_POSTSCALER(id) DT_CLOCKS_CELL(DT_NODELABEL(id), postscaler)
14+
#define RZ_CPG_CLK_SRC(id) DT_PROP(DT_CLOCKS_CTLR(DT_NODELABEL(id)), clock_frequency)
15+
16+
#define RZ_CPG_GET_CLOCK(id) (RZ_CPG_CLK_SRC(id) / RZ_CPG_PLL_POSTSCALER(id) / RZ_CPG_DIV(id))
17+
18+
/* Helper macro */
19+
#define RZ_CPG_CLK_DIV(clk) \
20+
UTIL_CAT(RZ_CPG_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(clk)) \
21+
(DT_PROP(clk, div))
22+
23+
#define RZ_CPG_DIV_ICLK(n) UTIL_CAT(BSP_CLOCKS_PL1_DIV_, n)
24+
#define RZ_CPG_DIV_P0CLK(n) UTIL_CAT(BSP_CLOCKS_PL2A_DIV_, n)
25+
#define RZ_CPG_DIV_I2CLK(n) UTIL_CAT(BSP_CLOCKS_PL3CLK200FIX_DIV_, n)
26+
#define RZ_CPG_DIV_P1CLK(n) UTIL_CAT(BSP_CLOCKS_PL3B_DIV_, n)
27+
#define RZ_CPG_DIV_P2CLK(n) UTIL_CAT(BSP_CLOCKS_PL3A_DIV_, n)
28+
#define RZ_CPG_DIV_SPI0CLK(n) UTIL_CAT(BSP_CLOCKS_PL3C_DIV_, n)
29+
#define RZ_CPG_DIV_OC0CLK(n) UTIL_CAT(BSP_CLOCKS_PL3F_DIV_, n)
30+
#define RZ_CPG_DIV_M3CLK(n) UTIL_CAT(BSP_CLOCKS_DSIA_DIV_, n)
31+
32+
#define BSP_CFG_CLOCKS_SECURE (0)
33+
#define BSP_CFG_CLOCKS_OVERRIDE (0)
34+
#define BSP_CFG_CLOCK_OSCCLK_HZ DT_PROP_OR(DT_NODELABEL(osc), clock_frequency, 24000000) /* OSC 24000000Hz */
35+
#define BSP_CFG_CLOCK_PLL1_HZ DT_PROP_OR(DT_NODELABEL(ppl1), clock_frequency, 1000000000) /* PLL1 1000000000Hz */
36+
#define BSP_CFG_CLOCK_ICLK_HZ RZ_CPG_GET_CLOCK(iclk) /* ICLK */
37+
#define BSP_CFG_CLOCK_PLL2_1600_HZ DT_PROP_OR(DT_NODELABEL(pll2_1600), clock_frequency, 1600000000) /* PLL2 1600000000Hz */
38+
#define BSP_CFG_CLOCK_PLL2_533_HZ DT_PROP_OR(DT_NODELABEL(pll2_533), clock_frequency, 533000000) /* PLL2 533000000Hz */
39+
#define BSP_CFG_CLOCK_SD0CLK_HZ RZ_CPG_GET_CLOCK(sd0clk) /* SD0CLK */
40+
#define BSP_CFG_CLOCK_SD1CLK_HZ RZ_CPG_GET_CLOCK(sd1clk) /* SD1CLK */
41+
#define BSP_CFG_CLOCK_P0CLK_HZ RZ_CPG_GET_CLOCK(p0clk) /* P0CLK */
42+
#define BSP_CFG_CLOCK_TSUCLK_HZ RZ_CPG_GET_CLOCK(tsuclk) /* TSUCLK */
43+
#define BSP_CFG_CLOCK_PLL3_1600_HZ DT_PROP_OR(DT_NODELABEL(pll3_1600), clock_frequency, 1600000000) /* PLL3 1600000000Hz */
44+
#define BSP_CFG_CLOCK_ATCLK_HZ RZ_CPG_GET_CLOCK(atclk) /* ATCLK */
45+
#define BSP_CFG_CLOCK_I2CLK_HZ RZ_CPG_GET_CLOCK(i2clk) /* I2CLK */
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#define BSP_CFG_CLOCK_P1CLK_HZ RZ_CPG_GET_CLOCK(p1clk) /* P1CLK */
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#define BSP_CFG_CLOCK_M0CLK_HZ RZ_CPG_GET_CLOCK(m0clk) /* M0CLK */
48+
#define BSP_CFG_CLOCK_ZTCLK_HZ RZ_CPG_GET_CLOCK(ztclk) /* ZTCLK */
49+
#define BSP_CFG_CLOCK_P2CLK_HZ RZ_CPG_GET_CLOCK(p2clk) /* P2CLK */
50+
#define BSP_CFG_CLOCK_PLL3_533_HZ DT_PROP_OR(DT_NODELABEL(pll3_533), clock_frequency, 533000000) /* PLL3 533000000Hz */
51+
#define BSP_CFG_CLOCK_SPI0CLK_HZ RZ_CPG_GET_CLOCK(spi0clk) /* SPI0CLK */
52+
#define BSP_CFG_CLOCK_SPI_QSPI0_SPCLK_HZ (RZ_CPG_GET_CLOCK(spi0clk) >> 1) /* SPI QSPI0_SPCLK */
53+
#define BSP_CFG_CLOCK_PLL3_400_HZ DT_PROP_OR(DT_NODELABEL(pll3_400), clock_frequency, 400000000) /* PLL3 400000000Hz */
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#define BSP_CFG_CLOCK_SPI1CLK_HZ RZ_CPG_GET_CLOCK(spi1clk) /* SPI1CLK */
55+
#define BSP_CFG_CLOCK_M2CLK_HZ RZ_CPG_GET_CLOCK(m2clk) /* M2CLK */
56+
#define BSP_CFG_CLOCK_OC0CLK_HZ RZ_CPG_GET_CLOCK(oc0clk) /* OC0CLK */
57+
#define BSP_CFG_CLOCK_OCTA_QSPI0_SPCLK_HZ (RZ_CPG_GET_CLOCK(oc0clk) >> 1) /* Octa QSPI0_SPCLK */
58+
#define BSP_CFG_CLOCK_OC1CLK_HZ RZ_CPG_GET_CLOCK(oc1clk) /* OC1CLK */
59+
#define BSP_CFG_CLOCK_PLL4_HZ DT_PROP_OR(DT_NODELABEL(pll4), clock_frequency, 1600000000) /* PLL4 1600MHz */
60+
#define BSP_CFG_CLOCK_S0CLK_HZ RZ_CPG_GET_CLOCK(s0clk) /* S0CLK */
61+
#define BSP_CFG_CLOCK_PLL5_1500_HZ DT_PROP_OR(DT_NODELABEL(pll5_1500), clock_frequency, 1500000000) /* PLL5 1500000000Hz */
62+
#define BSP_CFG_DIVDSIB_SET_DIV (BSP_CLOCKS_DSIB_DIV_1) /* DSI_B Div /1 */
63+
#define BSP_CFG_CLOCK_M3CLK_HZ RZ_CPG_GET_CLOCK(m3clk) /* M3CLK */
64+
#define BSP_CFG_CLOCK_PLL5_500_HZ DT_PROP_OR(DT_NODELABEL(pll5_500), clock_frequency, 500000000) /* PLL5 500000000Hz */
65+
#define BSP_CFG_CLOCK_PLL6_HZ DT_PROP_OR(DT_NODELABEL(pll6), clock_frequency, 500000000) /* PLL6 500000000Hz */
66+
#define BSP_CFG_SEL_PLL6_2_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250) /* PLL6_2 Sel: 250MHz (from PLL6) */
67+
#define BSP_CFG_CLOCK_HPCLK_HZ RZ_CPG_GET_CLOCK(hpclk) /* HPCLK */
68+
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/* PLL3_3 Sel */
70+
#define BSP_CFG_SEL_PLL3_3_SET_SOURCE \
71+
((RZ_CPG_CLK_SRC(spi0clk) == 533000000) ? BSP_CLOCKS_SOURCE_CLOCK_PLL3_533 \
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: BSP_CLOCKS_SOURCE_CLOCK_PLL3_400)
73+
74+
/* PLL3_5 Sel */
75+
#define BSP_CFG_SEL_PLL3_5_SET_SOURCE \
76+
((RZ_CPG_CLK_SRC(oc0clk) == 533000000) ? BSP_CLOCKS_SOURCE_CLOCK_PLL3_533 \
77+
: BSP_CLOCKS_SOURCE_CLOCK_PLL3_400)
78+
79+
/* SD0CLK Sel */
80+
#define BSP_CFG_SEL_SDHI0_SET_SOURCE \
81+
((BSP_CFG_CLOCK_SD0CLK_HZ == 533000000) ? BSP_CLOCKS_SOURCE_CLOCK_PLL2_533 \
82+
: (BSP_CFG_CLOCK_SD0CLK_HZ == 400000000) ? BSP_CLOCKS_SOURCE_CLOCK_PLL2_400 \
83+
: BSP_CLOCKS_SOURCE_CLOCK_PLL2_266)
84+
85+
/* SD1CLK Sel */
86+
#define BSP_CFG_SEL_SDHI1_SET_SOURCE \
87+
((BSP_CFG_CLOCK_SD1CLK_HZ == 533000000) ? BSP_CLOCKS_SOURCE_CLOCK_PLL2_533 \
88+
: (BSP_CFG_CLOCK_SD1CLK_HZ == 400000000) ? BSP_CLOCKS_SOURCE_CLOCK_PLL2_400 \
89+
: BSP_CLOCKS_SOURCE_CLOCK_PLL2_266)
90+
91+
/* S0CLK Sel */
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#define BSP_CFG_SEL_PLL4_SET_SOURCE \
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((RZ_CPG_CLK_SRC(s0clk) == 1600000000) ? BSP_CLOCKS_SOURCE_CLOCK_PLL4_1600 \
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: BSP_CLOCKS_SOURCE_CLOCK_OSC_0024)
95+
96+
#define BSP_CFG_DIVPL1_SET_DIV RZ_CPG_CLK_DIV(DT_NODELABEL(iclk)) /* ICLK Div */
97+
#define BSP_CFG_DIVPL2A_SET_DIV RZ_CPG_CLK_DIV(DT_NODELABEL(p0clk)) /* P0CLK Div */
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#define BSP_CFG_DIVPL3CLK200FIX_SET_DIV RZ_CPG_CLK_DIV(DT_NODELABEL(i2clk)) /* I2CLK Div */
99+
#define BSP_CFG_DIVPL3B_SET_DIV RZ_CPG_CLK_DIV(DT_NODELABEL(p1clk)) /* P1CLK Div */
100+
#define BSP_CFG_DIVPL3A_SET_DIV RZ_CPG_CLK_DIV(DT_NODELABEL(p2clk)) /* P2CLK Div */
101+
#define BSP_CFG_DIVPL3C_SET_DIV RZ_CPG_CLK_DIV(DT_NODELABEL(spi0clk)) /* PLL3_3 Div */
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#define BSP_CFG_DIVPL3F_SET_DIV RZ_CPG_CLK_DIV(DT_NODELABEL(oc0clk)) /* PLL3_5 Div */
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#define BSP_CFG_DIVDSIA_SET_DIV RZ_CPG_CLK_DIV(DT_NODELABEL(m3clk)) /* DSI_A Div */
104+
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#endif /* BSP_CLOCK_CFG_H_ */

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