hal: renesas: ra: Disable irq priority configuration

IRQ priority on Zephyr have offset, disable the priority
setting for IRQ in FSP HAL layer so that priority setting
will not be override when Open() API is called

Signed-off-by: Duy Nguyen <[email protected]>

Author: duynguyenxa

drivers/ra/README

@@ -119,3 +119,7 @@ Patch List:
    * Remove include <cmath> in bsp_tfu.h to avoid build error
    Impacted files:
       zephyr/ra/portable/bsp_tfu.h
+
+   * Disable the priority setting for IRQ in FSP HAL layer so that priority setting will not be override when Open() API is called.
+   Impacted files:
+      zephyr/ra/portable/bsp_irq.h

zephyr/ra/portable/bsp_irq.h

@@ -119,19 +119,8 @@ __STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq)
  **********************************************************************************************************************/
 __STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context)
 {
-    /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions
-     * every time a priority is configured in the NVIC. */
- #if (4U == __CORTEX_M)
-    NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX);
- #elif (33 == __CORTEX_M)
-    NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX);
- #elif (23 == __CORTEX_M)
-    NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) |
-                               (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq)));
- #else
-    NVIC_SetPriority(irq, priority);
- #endif
-
+    /* Zephyr interrupt priority will have offset, remove priority config in FSP to prevent override seting on Zephyr */
+    FSP_PARAMETER_NOT_USED(priority);
     /* Store the context. The context is recovered in the ISR. */
     R_FSP_IsrContextSet(irq, p_context);
 }