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Phuc PhamKhiemNguyenT
Phuc Pham
authored and
KhiemNguyenT
committed
hal: renesas: rz: Add initial support for RZ/A
This is the initial hal support for RZ/A series. The hal layer support for RZ/A3UL will based on RZ/A FSP Signed-off-by: Phuc Pham <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>
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‎drivers/rz/README

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@@ -3,11 +3,13 @@ Flexible Software Package (FSP)
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Origin:
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Renesas Electronics Corporation
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RZ/A: https://github.com/renesas/rza-fsp
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RZ/G: https://github.com/renesas/rzg-fsp
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RZ/N: https://github.com/renesas/rzn-fsp
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RZ/T: https://github.com/renesas/rzt-fsp
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Status:
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RZ/A FSP: version v3.3.0
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RZ/G FSP: version v2.1.0
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RZ/N FSP: version v2.1.0
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RZ/T FSP: version v2.2.0
@@ -23,6 +25,9 @@ Dependencies:
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None.
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URL:
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https://github.com/renesas/rza-fsp
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Commit: efa73c09f98e6d124d98692fffc1091eac0bbe47
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https://github.com/renesas/rzg-fsp
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Commit: 8db06f881784144e86361b1266ac4d3c026f6ad8
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‎drivers/rz/fsp/inc/instances/rza/fsp_common_api.h

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‎drivers/rz/fsp/inc/instances/rza/fsp_version.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FSP_VERSION_H
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#define FSP_VERSION_H
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/***********************************************************************************************************************
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* Includes
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**********************************************************************************************************************/
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/* Includes board and MCU related header files. */
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#include "bsp_api.h"
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/*******************************************************************************************************************//**
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* @addtogroup RENESAS_COMMON
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* @{
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**********************************************************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/** FSP pack major version. */
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#define FSP_VERSION_MAJOR (3U)
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/** FSP pack minor version. */
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#define FSP_VERSION_MINOR (3U)
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/** FSP pack patch version. */
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#define FSP_VERSION_PATCH (0U)
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/** FSP pack version build number (currently unused). */
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#define FSP_VERSION_BUILD (0U)
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/** Public FSP version name. */
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#define FSP_VERSION_STRING ("3.3.0")
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/** Unique FSP version ID. */
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#define FSP_VERSION_BUILD_STRING ("Built with RZ/A3UL Flexible Software Package version 3.3.0")
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/**********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/** FSP Pack version structure */
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typedef union st_fsp_pack_version
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{
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/** Version id */
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uint32_t version_id;
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/**
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* Code version parameters, little endian order.
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*/
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struct version_id_b_s
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{
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uint8_t build; ///< Build version of FSP Pack
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uint8_t patch; ///< Patch version of FSP Pack
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uint8_t minor; ///< Minor version of FSP Pack
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uint8_t major; ///< Major version of FSP Pack
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} version_id_b;
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} fsp_pack_version_t;
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif

‎drivers/rz/fsp/src/rza/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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set(srcs
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bsp/mcu/all/bsp_clocks.c
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bsp/mcu/all/bsp_delay.c
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bsp/mcu/all/bsp_irq.c
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bsp/mcu/all/bsp_io.c
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bsp/mcu/all/bsp_gicv3.c
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bsp/mcu/${CONFIG_SOC_SERIES}/bsp_clocks_setup.c
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)
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zephyr_library_sources(${srcs})

‎drivers/rz/fsp/src/rza/bsp/cmsis/Device/RENESAS/Include/base_addresses.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __BASE_ADDRESSES_H
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#define __BASE_ADDRESSES_H
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#if 33U == __CORTEX_M // NOLINT(readability-magic-numbers)
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/* =========================================================================================================================== */
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/* ================ Device Specific Peripheral Address Map ================ */
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/* =========================================================================================================================== */
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/** @addtogroup Device_Peripheral_peripheralAddr
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* @{
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*/
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/** @} */ /* End of group Device_Peripheral_peripheralAddr */
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/* =========================================================================================================================== */
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/* ================ Peripheral declaration ================ */
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/* =========================================================================================================================== */
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/** @addtogroup Device_Peripheral_declaration
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* @{
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*/
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/** @} */ /* End of group Device_Peripheral_declaration */
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#else
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/* =========================================================================================================================== */
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/* ================ Device Specific Peripheral Address Map ================ */
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/* =========================================================================================================================== */
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/** @addtogroup Device_Peripheral_peripheralAddr
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* @{
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*/
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/** @} */ /* End of group Device_Peripheral_peripheralAddr */
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/* =========================================================================================================================== */
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/* ================ Peripheral declaration ================ */
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/* =========================================================================================================================== */
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/** @addtogroup Device_Peripheral_declaration
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* @{
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*/
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/** @} */ /* End of group Device_Peripheral_declaration */
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#endif
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#endif

‎drivers/rz/fsp/src/rza/bsp/cmsis/Device/RENESAS/Include/iobitmask.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**********************************************************************************************************************
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* File Name : iobitmask.h
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* Version : 1.00
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* Description : iobitmask header
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*********************************************************************************************************************/
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#ifndef ___IOBITMASK_HEADER__
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#define ___IOBITMASK_HEADER__
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#include "iobitmasks/adc_iobitmask.h"
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#include "iobitmasks/canfd_iobitmask.h"
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#include "iobitmasks/cpg_iobitmask.h"
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#include "iobitmasks/cru_iobitmask.h"
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#include "iobitmasks/dma_iobitmask.h"
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#include "iobitmasks/eccram_iobitmask.h"
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#include "iobitmasks/ether_iobitmask.h"
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#include "iobitmasks/gpio_iobitmask.h"
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#include "iobitmasks/gtm_iobitmask.h"
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#include "iobitmasks/intc_ia55_iobitmask.h"
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#include "iobitmasks/intc_gic_iobitmask.h"
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#include "iobitmasks/isu_iobitmask.h"
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#include "iobitmasks/lcdc_iobitmask.h"
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#include "iobitmasks/mstp_iobitmask.h"
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#include "iobitmasks/mtu_iobitmask.h"
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#include "iobitmasks/octa_iobitmask.h"
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#include "iobitmasks/riic_iobitmask.h"
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#include "iobitmasks/rspi_iobitmask.h"
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#include "iobitmasks/scifa_iobitmask.h"
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#include "iobitmasks/scig_iobitmask.h"
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#include "iobitmasks/sdhi_iobitmask.h"
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#include "iobitmasks/spibsc_iobitmask.h"
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#include "iobitmasks/ssi_iobitmask.h"
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#include "iobitmasks/sysc_iobitmask.h"
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#include "iobitmasks/tsu_iobitmask.h"
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#include "iobitmasks/usb_iobitmask.h"
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#include "iobitmasks/wdt_iobitmask.h"
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#endif /* ___IOBITMASK_HEADER__ */

‎drivers/rz/fsp/src/rza/bsp/cmsis/Device/RENESAS/Include/iobitmasks/adc_iobitmask.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**********************************************************************************************************************
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* File Name : adc_iobitmask.h
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* Version : 1.00
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* Description : IO bit mask file for adc.
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*********************************************************************************************************************/
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#ifndef ADC_IOBITMASK_H
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#define ADC_IOBITMASK_H
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#define R_ADC_ADM0_ADCE_Msk (0x00000001UL)
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#define R_ADC_ADM0_ADCE_Pos (0UL)
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#define R_ADC_ADM0_ADBSY_Msk (0x00000002UL)
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#define R_ADC_ADM0_ADBSY_Pos (1UL)
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#define R_ADC_ADM0_PWDWNB_Msk (0x00000004UL)
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#define R_ADC_ADM0_PWDWNB_Pos (2UL)
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#define R_ADC_ADM0_SRESB_Msk (0x00008000UL)
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#define R_ADC_ADM0_SRESB_Pos (15UL)
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#define R_ADC_ADM1_TRG_Msk (0x00000001UL)
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#define R_ADC_ADM1_TRG_Pos (0UL)
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#define R_ADC_ADM1_TRGIN_Msk (0x00000002UL)
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#define R_ADC_ADM1_TRGIN_Pos (1UL)
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#define R_ADC_ADM1_MS_Msk (0x00000004UL)
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#define R_ADC_ADM1_MS_Pos (2UL)
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#define R_ADC_ADM1_RPS_Msk (0x00000008UL)
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#define R_ADC_ADM1_RPS_Pos (3UL)
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#define R_ADC_ADM1_BS_Msk (0x00000010UL)
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#define R_ADC_ADM1_BS_Pos (4UL)
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#define R_ADC_ADM1_EGA_Msk (0x00003000UL)
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#define R_ADC_ADM1_EGA_Pos (12UL)
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#define R_ADC_ADM1_TRGEN_Msk (0x003F0000UL)
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#define R_ADC_ADM1_TRGEN_Pos (16UL)
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#define R_ADC_ADM2_CHSEL_Msk (0x00000003UL)
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#define R_ADC_ADM2_CHSEL_Pos (0UL)
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#define R_ADC_ADM3_ADSMP_Msk (0x0000FFFFUL)
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#define R_ADC_ADM3_ADSMP_Pos (0UL)
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#define R_ADC_ADM3_ADCMP_Msk (0x00FF0000UL)
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#define R_ADC_ADM3_ADCMP_Pos (16UL)
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#define R_ADC_ADM3_ADIL_Msk (0xFF000000UL)
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#define R_ADC_ADM3_ADIL_Pos (24UL)
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#define R_ADC_ADINT_INTEN_Msk (0x0000000FUL)
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#define R_ADC_ADINT_INTEN_Pos (0UL)
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#define R_ADC_ADINT_CSEEN_Msk (0x00010000UL)
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#define R_ADC_ADINT_CSEEN_Pos (16UL)
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#define R_ADC_ADINT_INTS_Msk (0x80000000UL)
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#define R_ADC_ADINT_INTS_Pos (31UL)
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#define R_ADC_ADSTS_INTST_Msk (0x0000000FUL)
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#define R_ADC_ADSTS_INTST_Pos (0UL)
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#define R_ADC_ADSTS_CSEST_Msk (0x00010000UL)
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#define R_ADC_ADSTS_CSEST_Pos (16UL)
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#define R_ADC_ADSTS_TRGS_Msk (0x80000000UL)
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#define R_ADC_ADSTS_TRGS_Pos (31UL)
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#define R_ADC_ADIVC_DIVADC_Msk (0x000001FFUL)
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#define R_ADC_ADIVC_DIVADC_Pos (0UL)
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#define R_ADC_ADFIL_FILONOFF_Msk (0x00000001UL)
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#define R_ADC_ADFIL_FILONOFF_Pos (0UL)
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#define R_ADC_ADFIL_FILNUM_Msk (0x00000030UL)
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#define R_ADC_ADFIL_FILNUM_Pos (4UL)
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#define R_ADC_ADCR0_AD0_Msk (0x00000001UL)
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#define R_ADC_ADCR0_AD0_Pos (0UL)
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#define R_ADC_ADCR0_AD1_Msk (0x00000002UL)
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#define R_ADC_ADCR0_AD1_Pos (1UL)
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#define R_ADC_ADCR0_AD2_Msk (0x00000004UL)
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#define R_ADC_ADCR0_AD2_Pos (2UL)
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#define R_ADC_ADCR0_AD3_Msk (0x00000008UL)
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#define R_ADC_ADCR0_AD3_Pos (3UL)
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#define R_ADC_ADCR0_AD4_Msk (0x00000010UL)
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#define R_ADC_ADCR0_AD4_Pos (4UL)
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#define R_ADC_ADCR0_AD5_Msk (0x00000020UL)
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#define R_ADC_ADCR0_AD5_Pos (5UL)
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#define R_ADC_ADCR0_AD6_Msk (0x00000040UL)
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#define R_ADC_ADCR0_AD6_Pos (6UL)
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#define R_ADC_ADCR0_AD7_Msk (0x00000080UL)
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#define R_ADC_ADCR0_AD7_Pos (7UL)
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#define R_ADC_ADCR0_AD8_Msk (0x00000100UL)
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#define R_ADC_ADCR0_AD8_Pos (8UL)
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#define R_ADC_ADCR0_AD9_Msk (0x00000200UL)
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#define R_ADC_ADCR0_AD9_Pos (9UL)
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#define R_ADC_ADCR0_AD10_Msk (0x00000400UL)
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#define R_ADC_ADCR0_AD10_Pos (10UL)
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#define R_ADC_ADCR0_AD11_Msk (0x00000800UL)
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#define R_ADC_ADCR0_AD11_Pos (11UL)
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#define R_ADC_ADCR1_AD0_Msk (0x00000001UL)
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#define R_ADC_ADCR1_AD0_Pos (0UL)
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#define R_ADC_ADCR1_AD1_Msk (0x00000002UL)
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#define R_ADC_ADCR1_AD1_Pos (1UL)
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#define R_ADC_ADCR1_AD2_Msk (0x00000004UL)
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#define R_ADC_ADCR1_AD2_Pos (2UL)
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#define R_ADC_ADCR1_AD3_Msk (0x00000008UL)
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#define R_ADC_ADCR1_AD3_Pos (3UL)
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#define R_ADC_ADCR1_AD4_Msk (0x00000010UL)
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#define R_ADC_ADCR1_AD4_Pos (4UL)
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#define R_ADC_ADCR1_AD5_Msk (0x00000020UL)
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#define R_ADC_ADCR1_AD5_Pos (5UL)
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#define R_ADC_ADCR1_AD6_Msk (0x00000040UL)
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#define R_ADC_ADCR1_AD6_Pos (6UL)
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#define R_ADC_ADCR1_AD7_Msk (0x00000080UL)
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#define R_ADC_ADCR1_AD7_Pos (7UL)
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#define R_ADC_ADCR1_AD8_Msk (0x00000100UL)
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#define R_ADC_ADCR1_AD8_Pos (8UL)
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#define R_ADC_ADCR1_AD9_Msk (0x00000200UL)
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#define R_ADC_ADCR1_AD9_Pos (9UL)
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#define R_ADC_ADCR1_AD10_Msk (0x00000400UL)
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#define R_ADC_ADCR1_AD10_Pos (10UL)
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#define R_ADC_ADCR1_AD11_Msk (0x00000800UL)
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#define R_ADC_ADCR1_AD11_Pos (11UL)
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#define R_ADC_ADCR2_AD0_Msk (0x00000001UL)
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#define R_ADC_ADCR2_AD0_Pos (0UL)
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#define R_ADC_ADCR2_AD1_Msk (0x00000002UL)
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#define R_ADC_ADCR2_AD1_Pos (1UL)
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#define R_ADC_ADCR2_AD2_Msk (0x00000004UL)
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#define R_ADC_ADCR2_AD2_Pos (2UL)
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#define R_ADC_ADCR2_AD3_Msk (0x00000008UL)
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#define R_ADC_ADCR2_AD3_Pos (3UL)
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#define R_ADC_ADCR2_AD4_Msk (0x00000010UL)
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#define R_ADC_ADCR2_AD4_Pos (4UL)
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#define R_ADC_ADCR2_AD5_Msk (0x00000020UL)
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#define R_ADC_ADCR2_AD5_Pos (5UL)
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#define R_ADC_ADCR2_AD6_Msk (0x00000040UL)
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#define R_ADC_ADCR2_AD6_Pos (6UL)
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#define R_ADC_ADCR2_AD7_Msk (0x00000080UL)
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#define R_ADC_ADCR2_AD7_Pos (7UL)
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#define R_ADC_ADCR2_AD8_Msk (0x00000100UL)
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#define R_ADC_ADCR2_AD8_Pos (8UL)
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#define R_ADC_ADCR2_AD9_Msk (0x00000200UL)
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#define R_ADC_ADCR2_AD9_Pos (9UL)
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#define R_ADC_ADCR2_AD10_Msk (0x00000400UL)
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#define R_ADC_ADCR2_AD10_Pos (10UL)
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#define R_ADC_ADCR2_AD11_Msk (0x00000800UL)
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#define R_ADC_ADCR2_AD11_Pos (11UL)
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#define R_ADC_ADCR3_AD0_Msk (0x00000001UL)
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#define R_ADC_ADCR3_AD0_Pos (0UL)
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#define R_ADC_ADCR3_AD1_Msk (0x00000002UL)
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#define R_ADC_ADCR3_AD1_Pos (1UL)
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#define R_ADC_ADCR3_AD2_Msk (0x00000004UL)
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#define R_ADC_ADCR3_AD2_Pos (2UL)
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#define R_ADC_ADCR3_AD3_Msk (0x00000008UL)
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#define R_ADC_ADCR3_AD3_Pos (3UL)
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#define R_ADC_ADCR3_AD4_Msk (0x00000010UL)
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#define R_ADC_ADCR3_AD4_Pos (4UL)
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#define R_ADC_ADCR3_AD5_Msk (0x00000020UL)
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#define R_ADC_ADCR3_AD5_Pos (5UL)
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#define R_ADC_ADCR3_AD6_Msk (0x00000040UL)
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#define R_ADC_ADCR3_AD6_Pos (6UL)
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#define R_ADC_ADCR3_AD7_Msk (0x00000080UL)
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#define R_ADC_ADCR3_AD7_Pos (7UL)
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#define R_ADC_ADCR3_AD8_Msk (0x00000100UL)
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#define R_ADC_ADCR3_AD8_Pos (8UL)
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#define R_ADC_ADCR3_AD9_Msk (0x00000200UL)
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#define R_ADC_ADCR3_AD9_Pos (9UL)
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#define R_ADC_ADCR3_AD10_Msk (0x00000400UL)
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#define R_ADC_ADCR3_AD10_Pos (10UL)
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#define R_ADC_ADCR3_AD11_Msk (0x00000800UL)
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#define R_ADC_ADCR3_AD11_Pos (11UL)
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#endif

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