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Danh DoanKhiemNguyenT
Danh Doan
authored and
KhiemNguyenT
committed
hal: renesas: ra: initial support for sdram controller
Initial support SDRAM on Renesas RA SoC Signed-off-by: Danh Doan <[email protected]>
1 parent 2d91793 commit a271e45

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6 files changed

+275
-293
lines changed

6 files changed

+275
-293
lines changed

‎drivers/ra/README

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -86,11 +86,6 @@ Patch List:
8686
drivers/ra/fsp/inc/instances/r_ether_phy.h
8787
drivers/ra/fsp/inc/instances/r_ether.h
8888

89-
* Add support for SDRAM controllers taken from FSP v5.6.0
90-
Impacted files:
91-
drivers/ra/fsp/src/bsp/mcu/all/bsp_sdram.h
92-
drivers/ra/fsp/src/bsp/mcu/all/bsp_sdram.c
93-
9489
* Create new USB device support for Zephyr HAL (do not use current FSP USB stack)
9590
Impacted files:
9691
drivers/ra/fsp/inc/api/r_usb_device_api.h
@@ -116,3 +111,7 @@ Patch List:
116111
* Add Trigger NO_EDGE enum for comparator module
117112
Impacted files:
118113
drivers/ra/fsp/inc/api/r_comparator_api.h
114+
115+
* Reflect OFS setting for sdram from Zephyr device-tree value
116+
Impacted files:
117+
zephyr/ra/ra_cfg/fsp_cfg/bsp/**/bsp_mcu_family_cfg.h

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m2/bsp_mcu_family_cfg.h

Lines changed: 52 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -90,65 +90,61 @@ extern "C" {
9090
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
9191
#endif
9292

93-
#ifndef BSP_CFG_SDRAM_ENABLED
93+
/* SDRAM controller configuration */
94+
#if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram))
95+
#define BSP_CFG_SDRAM_ENABLED (1)
96+
#define BSP_CFG_SDRAM_TRAS \
97+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
98+
renesas_ra_sdram_timing, 0)
99+
#define BSP_CFG_SDRAM_TRCD \
100+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
101+
renesas_ra_sdram_timing, 1)
102+
#define BSP_CFG_SDRAM_TRP \
103+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
104+
renesas_ra_sdram_timing, 2)
105+
#define BSP_CFG_SDRAM_TWR \
106+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
107+
renesas_ra_sdram_timing, 3)
108+
#define BSP_CFG_SDRAM_TCL \
109+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
110+
renesas_ra_sdram_timing, 4)
111+
#define BSP_CFG_SDRAM_TRFC \
112+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
113+
renesas_ra_sdram_timing, 5)
114+
#define BSP_CFG_SDRAM_TREFW \
115+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
116+
renesas_ra_sdram_timing, 6)
117+
#define BSP_CFG_SDRAM_INIT_ARFI \
118+
DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_interval)
119+
#define BSP_CFG_SDRAM_INIT_ARFC \
120+
DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_count)
121+
#define BSP_CFG_SDRAM_INIT_PRC \
122+
DT_PROP(DT_INST(0, renesas_ra_sdram), precharge_cycle_count)
123+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT \
124+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), multiplex_addr_shift)
125+
#define BSP_CFG_SDRAM_ENDIAN_MODE \
126+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), edian_mode)
127+
#define BSP_CFG_SDRAM_ACCESS_MODE \
128+
DT_PROP(DT_INST(0, renesas_ra_sdram), continuous_access)
129+
#define BSP_CFG_SDRAM_BUS_WIDTH \
130+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), bus_width)
131+
#else
94132
#define BSP_CFG_SDRAM_ENABLED (0)
95-
#endif
96-
97-
#ifndef BSP_CFG_SDRAM_TRAS
98-
#define BSP_CFG_SDRAM_TRAS (6)
99-
#endif
100-
101-
#ifndef BSP_CFG_SDRAM_TRCD
102-
#define BSP_CFG_SDRAM_TRCD (3)
103-
#endif
104-
105-
#ifndef BSP_CFG_SDRAM_TRP
106-
#define BSP_CFG_SDRAM_TRP (3)
107-
#endif
108-
109-
#ifndef BSP_CFG_SDRAM_TWR
110-
#define BSP_CFG_SDRAM_TWR (2)
111-
#endif
112-
113-
#ifndef BSP_CFG_SDRAM_TCL
114-
#define BSP_CFG_SDRAM_TCL (3)
115-
#endif
116-
117-
#ifndef BSP_CFG_SDRAM_TRFC
118-
#define BSP_CFG_SDRAM_TRFC (937)
119-
#endif
120-
121-
#ifndef BSP_CFG_SDRAM_TREFW
122-
#define BSP_CFG_SDRAM_TREFW (8)
123-
#endif
124-
125-
#ifndef BSP_CFG_SDRAM_INIT_ARFI
126-
#define BSP_CFG_SDRAM_INIT_ARFI (10)
127-
#endif
128-
129-
#ifndef BSP_CFG_SDRAM_INIT_ARFC
130-
#define BSP_CFG_SDRAM_INIT_ARFC (8)
131-
#endif
132-
133-
#ifndef BSP_CFG_SDRAM_INIT_PRC
134-
#define BSP_CFG_SDRAM_INIT_PRC (3)
135-
#endif
136-
137-
#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT
138-
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (1)
139-
#endif
140-
141-
#ifndef BSP_CFG_SDRAM_ENDIAN_MODE
133+
#define BSP_CFG_SDRAM_TRAS (0)
134+
#define BSP_CFG_SDRAM_TRCD (0)
135+
#define BSP_CFG_SDRAM_TRP (0)
136+
#define BSP_CFG_SDRAM_TWR (0)
137+
#define BSP_CFG_SDRAM_TCL (0)
138+
#define BSP_CFG_SDRAM_TRFC (0)
139+
#define BSP_CFG_SDRAM_TREFW (0)
140+
#define BSP_CFG_SDRAM_INIT_ARFI (0)
141+
#define BSP_CFG_SDRAM_INIT_ARFC (0)
142+
#define BSP_CFG_SDRAM_INIT_PRC (0)
143+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (0)
142144
#define BSP_CFG_SDRAM_ENDIAN_MODE (0)
143-
#endif
144-
145-
#ifndef BSP_CFG_SDRAM_ACCESS_MODE
146-
#define BSP_CFG_SDRAM_ACCESS_MODE (1)
147-
#endif
148-
149-
#ifndef BSP_CFG_SDRAM_BUS_WIDTH
145+
#define BSP_CFG_SDRAM_ACCESS_MODE (0)
150146
#define BSP_CFG_SDRAM_BUS_WIDTH (0)
151-
#endif
147+
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) */
152148

153149
#ifdef __cplusplus
154150
}

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m3/bsp_mcu_family_cfg.h

Lines changed: 56 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/*
2-
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
3-
*
4-
* SPDX-License-Identifier: BSD-3-Clause
5-
*/
2+
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
66

77
#ifndef BSP_MCU_FAMILY_CFG_H_
88
#define BSP_MCU_FAMILY_CFG_H_
@@ -90,65 +90,61 @@ extern "C" {
9090
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
9191
#endif
9292

93-
#ifndef BSP_CFG_SDRAM_ENABLED
93+
/* SDRAM controller configuration */
94+
#if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram))
95+
#define BSP_CFG_SDRAM_ENABLED (1)
96+
#define BSP_CFG_SDRAM_TRAS \
97+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
98+
renesas_ra_sdram_timing, 0)
99+
#define BSP_CFG_SDRAM_TRCD \
100+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
101+
renesas_ra_sdram_timing, 1)
102+
#define BSP_CFG_SDRAM_TRP \
103+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
104+
renesas_ra_sdram_timing, 2)
105+
#define BSP_CFG_SDRAM_TWR \
106+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
107+
renesas_ra_sdram_timing, 3)
108+
#define BSP_CFG_SDRAM_TCL \
109+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
110+
renesas_ra_sdram_timing, 4)
111+
#define BSP_CFG_SDRAM_TRFC \
112+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
113+
renesas_ra_sdram_timing, 5)
114+
#define BSP_CFG_SDRAM_TREFW \
115+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
116+
renesas_ra_sdram_timing, 6)
117+
#define BSP_CFG_SDRAM_INIT_ARFI \
118+
DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_interval)
119+
#define BSP_CFG_SDRAM_INIT_ARFC \
120+
DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_count)
121+
#define BSP_CFG_SDRAM_INIT_PRC \
122+
DT_PROP(DT_INST(0, renesas_ra_sdram), precharge_cycle_count)
123+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT \
124+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), multiplex_addr_shift)
125+
#define BSP_CFG_SDRAM_ENDIAN_MODE \
126+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), edian_mode)
127+
#define BSP_CFG_SDRAM_ACCESS_MODE \
128+
DT_PROP(DT_INST(0, renesas_ra_sdram), continuous_access)
129+
#define BSP_CFG_SDRAM_BUS_WIDTH \
130+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), bus_width)
131+
#else
94132
#define BSP_CFG_SDRAM_ENABLED (0)
95-
#endif
96-
97-
#ifndef BSP_CFG_SDRAM_TRAS
98-
#define BSP_CFG_SDRAM_TRAS (6)
99-
#endif
100-
101-
#ifndef BSP_CFG_SDRAM_TRCD
102-
#define BSP_CFG_SDRAM_TRCD (3)
103-
#endif
104-
105-
#ifndef BSP_CFG_SDRAM_TRP
106-
#define BSP_CFG_SDRAM_TRP (3)
107-
#endif
108-
109-
#ifndef BSP_CFG_SDRAM_TWR
110-
#define BSP_CFG_SDRAM_TWR (2)
111-
#endif
112-
113-
#ifndef BSP_CFG_SDRAM_TCL
114-
#define BSP_CFG_SDRAM_TCL (3)
115-
#endif
116-
117-
#ifndef BSP_CFG_SDRAM_TRFC
118-
#define BSP_CFG_SDRAM_TRFC (937)
119-
#endif
120-
121-
#ifndef BSP_CFG_SDRAM_TREFW
122-
#define BSP_CFG_SDRAM_TREFW (8)
123-
#endif
124-
125-
#ifndef BSP_CFG_SDRAM_INIT_ARFI
126-
#define BSP_CFG_SDRAM_INIT_ARFI (10)
127-
#endif
128-
129-
#ifndef BSP_CFG_SDRAM_INIT_ARFC
130-
#define BSP_CFG_SDRAM_INIT_ARFC (8)
131-
#endif
132-
133-
#ifndef BSP_CFG_SDRAM_INIT_PRC
134-
#define BSP_CFG_SDRAM_INIT_PRC (3)
135-
#endif
136-
137-
#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT
138-
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (1)
139-
#endif
140-
141-
#ifndef BSP_CFG_SDRAM_ENDIAN_MODE
133+
#define BSP_CFG_SDRAM_TRAS (0)
134+
#define BSP_CFG_SDRAM_TRCD (0)
135+
#define BSP_CFG_SDRAM_TRP (0)
136+
#define BSP_CFG_SDRAM_TWR (0)
137+
#define BSP_CFG_SDRAM_TCL (0)
138+
#define BSP_CFG_SDRAM_TRFC (0)
139+
#define BSP_CFG_SDRAM_TREFW (0)
140+
#define BSP_CFG_SDRAM_INIT_ARFI (0)
141+
#define BSP_CFG_SDRAM_INIT_ARFC (0)
142+
#define BSP_CFG_SDRAM_INIT_PRC (0)
143+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (0)
142144
#define BSP_CFG_SDRAM_ENDIAN_MODE (0)
143-
#endif
144-
145-
#ifndef BSP_CFG_SDRAM_ACCESS_MODE
146-
#define BSP_CFG_SDRAM_ACCESS_MODE (1)
147-
#endif
148-
149-
#ifndef BSP_CFG_SDRAM_BUS_WIDTH
145+
#define BSP_CFG_SDRAM_ACCESS_MODE (0)
150146
#define BSP_CFG_SDRAM_BUS_WIDTH (0)
151-
#endif
147+
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) */
152148

153149
#ifdef __cplusplus
154150
}

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8d1/bsp_mcu_family_cfg.h

Lines changed: 57 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/*
2-
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
3-
*
4-
* SPDX-License-Identifier: BSD-3-Clause
5-
*/
2+
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
3+
*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
66
#ifndef BSP_MCU_FAMILY_CFG_H_
77
#define BSP_MCU_FAMILY_CFG_H_
88
#include "bsp_clock_cfg.h"
@@ -486,63 +486,60 @@
486486
#define BSP_CFG_DCACHE_ENABLED (CONFIG_DCACHE)
487487
#endif
488488

489-
#ifndef BSP_CFG_SDRAM_ENABLED
489+
/* SDRAM controller configuration */
490+
#if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram))
491+
#define BSP_CFG_SDRAM_ENABLED (1)
492+
#define BSP_CFG_SDRAM_TRAS \
493+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
494+
renesas_ra_sdram_timing, 0)
495+
#define BSP_CFG_SDRAM_TRCD \
496+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
497+
renesas_ra_sdram_timing, 1)
498+
#define BSP_CFG_SDRAM_TRP \
499+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
500+
renesas_ra_sdram_timing, 2)
501+
#define BSP_CFG_SDRAM_TWR \
502+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
503+
renesas_ra_sdram_timing, 3)
504+
#define BSP_CFG_SDRAM_TCL \
505+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
506+
renesas_ra_sdram_timing, 4)
507+
#define BSP_CFG_SDRAM_TRFC \
508+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
509+
renesas_ra_sdram_timing, 5)
510+
#define BSP_CFG_SDRAM_TREFW \
511+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
512+
renesas_ra_sdram_timing, 6)
513+
#define BSP_CFG_SDRAM_INIT_ARFI \
514+
DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_interval)
515+
#define BSP_CFG_SDRAM_INIT_ARFC \
516+
DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_count)
517+
#define BSP_CFG_SDRAM_INIT_PRC \
518+
DT_PROP(DT_INST(0, renesas_ra_sdram), precharge_cycle_count)
519+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT \
520+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), multiplex_addr_shift)
521+
#define BSP_CFG_SDRAM_ENDIAN_MODE \
522+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), edian_mode)
523+
#define BSP_CFG_SDRAM_ACCESS_MODE \
524+
DT_PROP(DT_INST(0, renesas_ra_sdram), continuous_access)
525+
#define BSP_CFG_SDRAM_BUS_WIDTH \
526+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), bus_width)
527+
#else
490528
#define BSP_CFG_SDRAM_ENABLED (0)
491-
#endif
492-
493-
#ifndef BSP_CFG_SDRAM_TRAS
494-
#define BSP_CFG_SDRAM_TRAS (6)
495-
#endif
496-
497-
#ifndef BSP_CFG_SDRAM_TRCD
498-
#define BSP_CFG_SDRAM_TRCD (3)
499-
#endif
500-
501-
#ifndef BSP_CFG_SDRAM_TRP
502-
#define BSP_CFG_SDRAM_TRP (3)
503-
#endif
504-
505-
#ifndef BSP_CFG_SDRAM_TWR
506-
#define BSP_CFG_SDRAM_TWR (2)
507-
#endif
508-
509-
#ifndef BSP_CFG_SDRAM_TCL
510-
#define BSP_CFG_SDRAM_TCL (3)
511-
#endif
512-
513-
#ifndef BSP_CFG_SDRAM_TRFC
514-
#define BSP_CFG_SDRAM_TRFC (937)
515-
#endif
516-
517-
#ifndef BSP_CFG_SDRAM_TREFW
518-
#define BSP_CFG_SDRAM_TREFW (8)
519-
#endif
520-
521-
#ifndef BSP_CFG_SDRAM_INIT_ARFI
522-
#define BSP_CFG_SDRAM_INIT_ARFI (10)
523-
#endif
524-
525-
#ifndef BSP_CFG_SDRAM_INIT_ARFC
526-
#define BSP_CFG_SDRAM_INIT_ARFC (8)
527-
#endif
528-
529-
#ifndef BSP_CFG_SDRAM_INIT_PRC
530-
#define BSP_CFG_SDRAM_INIT_PRC (3)
531-
#endif
532-
533-
#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT
534-
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (2)
535-
#endif
536-
537-
#ifndef BSP_CFG_SDRAM_ENDIAN_MODE
529+
#define BSP_CFG_SDRAM_TRAS (0)
530+
#define BSP_CFG_SDRAM_TRCD (0)
531+
#define BSP_CFG_SDRAM_TRP (0)
532+
#define BSP_CFG_SDRAM_TWR (0)
533+
#define BSP_CFG_SDRAM_TCL (0)
534+
#define BSP_CFG_SDRAM_TRFC (0)
535+
#define BSP_CFG_SDRAM_TREFW (0)
536+
#define BSP_CFG_SDRAM_INIT_ARFI (0)
537+
#define BSP_CFG_SDRAM_INIT_ARFC (0)
538+
#define BSP_CFG_SDRAM_INIT_PRC (0)
539+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (0)
538540
#define BSP_CFG_SDRAM_ENDIAN_MODE (0)
539-
#endif
540-
541-
#ifndef BSP_CFG_SDRAM_ACCESS_MODE
542-
#define BSP_CFG_SDRAM_ACCESS_MODE (1)
543-
#endif
544-
545-
#ifndef BSP_CFG_SDRAM_BUS_WIDTH
541+
#define BSP_CFG_SDRAM_ACCESS_MODE (0)
546542
#define BSP_CFG_SDRAM_BUS_WIDTH (0)
547-
#endif
543+
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) */
544+
548545
#endif /* BSP_MCU_FAMILY_CFG_H_ */

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