hal: renesas: rx: Fix implicit conversion build warnings in RX26T src

Fix the implicit conversion from float to double warnings
in RX26T source files

Signed-off-by: Quy Tran <[email protected]>

Author: quytranpzz

drivers/rx/README

@@ -81,3 +81,8 @@ Patch List:
    * Fix the build warnings in LVD driver
    Impacted files:
       drivers/rx/rdp/src/r_lvd_rx/src/r_lvd_rx_hw.c
+
+   * Fix implicit conversion build warnings
+   Impacted files:
+      drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_clocks.c
+      drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t.c

drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_clocks.c

@@ -529,7 +529,7 @@ static void clock_source_select (void)
     #endif
 
     /* Set PLL Multiplier. */
-    SYSTEM.PLLCR.BIT.STC = ((uint8_t)((float)BSP_CFG_PLL_MUL * 2.0)) - 1;
+    SYSTEM.PLLCR.BIT.STC = ((uint8_t)((float)BSP_CFG_PLL_MUL * 2.0f)) - 1;
 
     /* Set the PLL to operating. */
     SYSTEM.PLLCR2.BYTE = 0x00;

drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t.c

@@ -296,7 +296,7 @@ int32_t sci_init_bit_rate(sci_hdl_t const  hdl,
     error     = (((float)pclk / ((baud * divisor) * tmp)) - 1) * 100;
     abs_error = (error < 0) ? (-error) : error;
 
-    if ((abs_error <= 1.0) || (SCI_MODE_ASYNC != hdl->mode))
+    if ((abs_error <= 1.0f) || (SCI_MODE_ASYNC != hdl->mode))
     {
         hdl->rom->regs->SEMR.BIT.BRME = 0;          // disable MDDR