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duynguyenxaandrzej-kaczmarek
duynguyenxa
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andrzej-kaczmarek
committed
hal: renesas: ra: Change BSP macro to support clock config on dts
This change is to support new clock define on device tree, the clock configuration will now base on clock node status to get property value. Remove redundant macro in bsp_mcu_device_pn_cfg.h Signed-off-by: Duy Phuong Hoang. Nguyen <[email protected]>
1 parent 22d1e03 commit c0626e0

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6 files changed

+99
-67
lines changed

6 files changed

+99
-67
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‎zephyr/ra/CMakeLists.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
# SPDX-License-Identifier: Apache-2.0
22

33
add_subdirectory(ra_cfg)
4-
zephyr_include_directories(portable)
4+
zephyr_include_directories(portable)

‎zephyr/ra/ra_cfg/CMakeLists.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
# SPDX-License-Identifier: Apache-2.0
22

33
zephyr_include_directories(fsp_cfg)
4-
zephyr_include_directories(fsp_cfg/bsp/${CONFIG_SOC_SERIES})
4+
zephyr_include_directories(fsp_cfg/bsp/${CONFIG_SOC_SERIES})

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_cfg.h‎

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,26 +10,34 @@
1010
#include "soc.h"
1111
#include "bsp_clock_cfg.h"
1212
#include "bsp_mcu_family_cfg.h"
13+
14+
#define SUBCLOCK_STABILIZATION_MAX(x) ((x < 10000) ? x : 10000)
15+
16+
/* Disable BSP_CFG_PARAM_CHECKING_ENABLE as default to reduce code size */
1317
#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
1418

1519
/* Add for zephyr porting */
1620
#define BSP_CFG_INTERRUPT_INIT 0
17-
#define BSP_CFG_SP_MON_INIT 0
1821

1922
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
20-
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
23+
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (DT_NODE_HAS_STATUS(DT_NODELABEL(xtal), okay))
2124
#endif
25+
2226
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
23-
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
27+
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (DT_PROP_OR(DT_NODELABEL(xtal), mosel, 0))
2428
#endif
29+
30+
/* Keep 0 as default as LPM is not supported */
2531
#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
26-
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
32+
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (DT_PROP_OR(DT_NODELABEL(subclk), drive_capability, 0))
2733
#endif
34+
2835
#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
29-
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
36+
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (DT_NODE_HAS_STATUS(DT_NODELABEL(subclk), okay))
3037
#endif
3138
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
32-
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
39+
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS \
40+
SUBCLOCK_STABILIZATION_MAX((DT_PROP_OR(DT_NODELABEL(subclk), stabilization_time, 1000)))
3341
#endif
3442

3543
#define BSP_CFG_PFS_PROTECT (1)

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_clock_cfg.h‎

Lines changed: 81 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -5,14 +5,17 @@
55
*/
66

77
#include <zephyr/devicetree.h>
8+
#include <zephyr/dt-bindings/clock/ra_clock.h>
89

910
#ifndef BSP_CLOCK_CFG_H_
1011
#define BSP_CLOCK_CFG_H_
1112

1213
#define BSP_CFG_CLOCKS_SECURE (0)
1314
#define BSP_CFG_CLOCKS_OVERRIDE (0)
15+
#define BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \
16+
(COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)))
1417

15-
#define BSP_CFG_XTAL_HZ DT_PROP(DT_NODELABEL(xtal), clock_frequency)
18+
#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
1619

1720
#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 16000000
1821
#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 16MHz */
@@ -28,63 +31,90 @@
2831
#error "Invalid HOCO frequency, only can be set to 16MHz, 18MHz, 20MHz, 32MHz, 48MHz"
2932
#endif
3033

31-
#define BSP_CFG_PLL_SOURCE DT_PROP(DT_NODELABEL(clock), pll_source)
32-
#define BSP_CFG_PLL_DIV DT_PROP(DT_NODELABEL(clock), pll_div)
34+
#define BSP_CFG_PLL_SOURCE \
35+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
36+
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_1)
3337
#define BSP_CFG_PLL_MUL \
34-
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(clock), pll_mul, 0), \
35-
DT_PROP_BY_IDX(DT_NODELABEL(clock), pll_mul, 1))
38+
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
39+
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
40+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
41+
: BSP_CLOCKS_PLL_MUL(0, 0)
3642

37-
#define BSP_CFG_PLODIVP DT_PROP(DT_NODELABEL(clock), pll_divp)
38-
#define BSP_CFG_PLL1P_FREQUENCY_HZ DT_PROP(DT_NODELABEL(clock), pll_freqp)
39-
#define BSP_CFG_PLODIVQ DT_PROP(DT_NODELABEL(clock), pll_divq)
40-
#define BSP_CFG_PLL1Q_FREQUENCY_HZ DT_PROP(DT_NODELABEL(clock), pll_freqq)
41-
#define BSP_CFG_PLODIVR DT_PROP(DT_NODELABEL(clock), pll_divr)
42-
#define BSP_CFG_PLL1R_FREQUENCY_HZ DT_PROP(DT_NODELABEL(clock), pll_freqr)
43+
#define BSP_CFG_PLODIVP BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), divp, RA_PLL_DIV_2)
44+
#define BSP_CFG_PLL1P_FREQUENCY_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqp, 0)
45+
#define BSP_CFG_PLODIVQ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), divq, RA_PLL_DIV_2)
46+
#define BSP_CFG_PLL1Q_FREQUENCY_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqq, 0)
47+
#define BSP_CFG_PLODIVR BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), divr, RA_PLL_DIV_2)
48+
#define BSP_CFG_PLL1R_FREQUENCY_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), freqr, 0)
4349

44-
#define BSP_CFG_PLL2_SOURCE DT_PROP(DT_NODELABEL(clock), pll2_source)
45-
#define BSP_CFG_PLL2_DIV DT_PROP(DT_NODELABEL(clock), pll2_div)
50+
#define BSP_CFG_PLL2_SOURCE \
51+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), source, RA_PLL_SOURCE_DISABLE)
52+
#define BSP_CFG_PLL2_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), div, RA_PLL_DIV_1)
4653
#define BSP_CFG_PLL2_MUL \
47-
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(clock), pll2_mul, 0), \
48-
DT_PROP_BY_IDX(DT_NODELABEL(clock), pll2_mul, 1))
54+
DT_NODE_HAS_STATUS(DT_NODELABEL(pll2), okay) \
55+
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 0), \
56+
DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 1)) \
57+
: BSP_CLOCKS_PLL_MUL(0, 0)
4958

50-
#define BSP_CFG_PL2ODIVP DT_PROP(DT_NODELABEL(clock), pll2_divp)
51-
#define BSP_CFG_PLL2P_FREQUENCY_HZ DT_PROP(DT_NODELABEL(clock), pll2_freqp)
52-
#define BSP_CFG_PL2ODIVQ DT_PROP(DT_NODELABEL(clock), pll2_divq)
53-
#define BSP_CFG_PLL2Q_FREQUENCY_HZ DT_PROP(DT_NODELABEL(clock), pll2_freqq)
54-
#define BSP_CFG_PL2ODIVR DT_PROP(DT_NODELABEL(clock), pll2_divr)
55-
#define BSP_CFG_PLL2R_FREQUENCY_HZ DT_PROP(DT_NODELABEL(clock), pll2_freqr)
59+
#define BSP_CFG_PL2ODIVP BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), divp, RA_PLL_DIV_2)
60+
#define BSP_CFG_PLL2P_FREQUENCY_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqp, 0)
61+
#define BSP_CFG_PL2ODIVQ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), divq, RA_PLL_DIV_2)
62+
#define BSP_CFG_PLL2Q_FREQUENCY_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqq, 0)
63+
#define BSP_CFG_PL2ODIVR BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), divr, RA_PLL_DIV_2)
64+
#define BSP_CFG_PLL2R_FREQUENCY_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), freqr, 0)
5665

57-
#define BSP_CFG_CLOCK_SOURCE DT_PROP(DT_NODELABEL(clock), sysclock_source)
58-
#define BSP_CFG_CPUCLK_DIV DT_PROP(DT_NODELABEL(clock), cpuclk_div)
66+
#define BSP_CFG_CLOCK_SOURCE \
67+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \
68+
RA_PLL_SOURCE_DISABLE)
69+
#define BSP_CFG_CPUCLK_DIV \
70+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(cpuclk), clk_div, RA_SYS_CLOCK_DIV_1)
5971

60-
#define BSP_CFG_ICLK_DIV DT_PROP(DT_NODELABEL(clock), iclk_div)
61-
#define BSP_CFG_PCLKA_DIV DT_PROP(DT_NODELABEL(clock), pclka_div)
62-
#define BSP_CFG_PCLKB_DIV DT_PROP(DT_NODELABEL(clock), pclkb_div)
63-
#define BSP_CFG_PCLKC_DIV DT_PROP(DT_NODELABEL(clock), pclkc_div)
64-
#define BSP_CFG_PCLKD_DIV DT_PROP(DT_NODELABEL(clock), pclkd_div)
65-
#define BSP_CFG_PCLKE_DIV DT_PROP(DT_NODELABEL(clock), pclke_div)
66-
#define BSP_CFG_BCLK_DIV DT_PROP(DT_NODELABEL(clock), bclk_div)
67-
#define BSP_CFG_BCLK_OUTPUT DT_PROP(DT_NODELABEL(clock), bclk_out)
68-
#define BSP_CFG_FCLK_DIV DT_PROP(DT_NODELABEL(clock), fclk_div)
69-
#define BSP_CFG_SDCLK_OUTPUT DT_PROP(DT_NODELABEL(clock), sdclk_out)
72+
#define BSP_CFG_ICLK_DIV \
73+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_2)
74+
#define BSP_CFG_PCLKA_DIV \
75+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclka), clk_div, RA_SYS_CLOCK_DIV_4)
76+
#define BSP_CFG_PCLKB_DIV \
77+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_8)
78+
#define BSP_CFG_PCLKC_DIV \
79+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkc), clk_div, RA_SYS_CLOCK_DIV_8)
80+
#define BSP_CFG_PCLKD_DIV \
81+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_4)
82+
#define BSP_CFG_PCLKE_DIV \
83+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclke), clk_div, RA_SYS_CLOCK_DIV_2)
84+
#define BSP_CFG_BCLK_DIV \
85+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(bclk), clk_div, RA_SYS_CLOCK_DIV_4)
86+
#define BSP_CFG_SDCLK_OUTPUT BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(bclkout), sdclk, 1)
87+
#define BSP_CFG_BCLK_OUTPUT BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(bclkout), clk_out_div, 2)
88+
#define BSP_CFG_FCLK_DIV \
89+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), clk_div, RA_SYS_CLOCK_DIV_8)
7090

71-
#define BSP_CFG_UCK_SOURCE DT_PROP(DT_NODELABEL(clock), uclk_source)
72-
#define BSP_CFG_UCK_DIV DT_PROP(DT_NODELABEL(clock), uclk_div)
73-
#define BSP_CFG_U60CK_SOURCE DT_PROP(DT_NODELABEL(clock), u60clk_source)
74-
#define BSP_CFG_U60CK_DIV DT_PROP(DT_NODELABEL(clock), u60clk_div)
75-
#define BSP_CFG_OCTA_SOURCE DT_PROP(DT_NODELABEL(clock), octaspiclk_source)
76-
#define BSP_CFG_OCTA_DIV DT_PROP(DT_NODELABEL(clock), octaspiclk_div)
77-
#define BSP_CFG_CANFDCLK_SOURCE DT_PROP(DT_NODELABEL(clock), canfdclk_source)
78-
#define BSP_CFG_CANFDCLK_DIV DT_PROP(DT_NODELABEL(clock), canfdclk_div)
79-
#define BSP_CFG_CLKOUT_SOURCE DT_PROP(DT_NODELABEL(clock), clkout_source)
80-
#define BSP_CFG_CLKOUT_DIV DT_PROP(DT_NODELABEL(clock), clkout_div)
81-
#define BSP_CFG_SCICLK_SOURCE DT_PROP(DT_NODELABEL(clock), sciclk_source)
82-
#define BSP_CFG_SCICLK_DIV DT_PROP(DT_NODELABEL(clock), sciclk_div)
83-
#define BSP_CFG_SPICLK_SOURCE DT_PROP(DT_NODELABEL(clock), spiclk_source)
84-
#define BSP_CFG_SPICLK_DIV DT_PROP(DT_NODELABEL(clock), spiclk_div)
85-
#define BSP_CFG_ADCCLK_SOURCE DT_PROP(DT_NODELABEL(clock), adcclk_source)
86-
#define BSP_CFG_ADCCLK_DIV DT_PROP(DT_NODELABEL(clock), adcclk_div)
87-
#define BSP_CFG_I3CCLK_SOURCE DT_PROP(DT_NODELABEL(clock), i3cclk_source)
88-
#define BSP_CFG_I3CCLK_DIV DT_PROP(DT_NODELABEL(clock), i3cclk_div)
91+
#define BSP_CFG_UCK_SOURCE \
92+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
93+
#define BSP_CFG_UCK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_div, 0)
94+
#define BSP_CFG_U60CK_SOURCE \
95+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(u60clk), clk_src, RA_CLOCK_SOURCE_DISABLE)
96+
#define BSP_CFG_U60CK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(u60clk), clk_div, 0)
97+
#define BSP_CFG_OCTA_SOURCE \
98+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(octaspiclk), clk_src, \
99+
RA_CLOCK_SOURCE_DISABLE)
100+
#define BSP_CFG_OCTA_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(octaspiclk), clk_div, 0)
101+
#define BSP_CFG_CANFDCLK_SOURCE \
102+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(canfdclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
103+
#define BSP_CFG_CANFDCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(canfdclk), clk_div, 0)
104+
#define BSP_CFG_CLKOUT_SOURCE \
105+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
106+
#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
107+
#define BSP_CFG_SCICLK_SOURCE \
108+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(sciclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
109+
#define BSP_CFG_SCICLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(sciclk), clk_div, 0)
110+
#define BSP_CFG_SPICLK_SOURCE \
111+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(spiclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
112+
#define BSP_CFG_SPICLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(spiclk), clk_div, 0)
113+
#define BSP_CFG_ADCCLK_SOURCE \
114+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(adcclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
115+
#define BSP_CFG_ADCCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(adcclk), clk_div, 0)
116+
#define BSP_CFG_I3CCLK_SOURCE \
117+
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(i3cclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
118+
#define BSP_CFG_I3CCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(i3cclk), clk_div, 0)
89119

90120
#endif /* BSP_CLOCK_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_mcu_device_pn_cfg.h‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,5 @@
55
*/
66
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
77
#define BSP_MCU_DEVICE_PN_CFG_H_
8-
#define BSP_MCU_R7FA8M1AHECBD
9-
#define BSP_MCU_FEATURE_SET ('A')
10-
#define BSP_ROM_SIZE_BYTES (2064384)
11-
#define BSP_RAM_SIZE_BYTES (917504)
12-
#define BSP_DATA_FLASH_SIZE_BYTES (12288)
13-
#define BSP_PACKAGE_BGA
148
#define BSP_PACKAGE_PINS (224)
159
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_mcu_family_cfg.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@
1111
#include "bsp_mcu_info.h"
1212
#include "bsp_clock_cfg.h"
1313
#define BSP_MCU_GROUP_RA8M1 (1)
14-
#define BSP_LOCO_HZ (32768)
15-
#define BSP_MOCO_HZ (8000000)
14+
#define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0))
15+
#define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0))
1616
#define BSP_SUB_CLOCK_HZ (0)
1717
#if BSP_CFG_HOCO_FREQUENCY == 0
1818
#define BSP_HOCO_HZ (16000000)

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