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nhutnguyenkcKhiemNguyenT
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hal: renesas: rz: Initial support RZ FSP hal driver
This is the initial hal support for RZ family series. The hal layer support for RZ/G3S will base on RZ/G3S FSP. Signed-off-by: Nhut Nguyen <[email protected]> Signed-off-by: Binh Nguyen <[email protected]>
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‎drivers/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory_ifdef(CONFIG_HAS_RENESAS_RA_FSP ra)
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add_subdirectory_ifdef(CONFIG_HAS_RENESAS_RZ_FSP rz)

‎drivers/rz/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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# Extract the RZ family name from CONFIG_SOC_SERIES
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string(SUBSTRING ${CONFIG_SOC_SERIES} 0 3 SOC_SERIES_PREFIX)
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add_subdirectory(fsp/src/${SOC_SERIES_PREFIX})
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set(include_dirs
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fsp/inc
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fsp/inc/api
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fsp/inc/instances/${SOC_SERIES_PREFIX}
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fsp/src/${SOC_SERIES_PREFIX}/bsp/mcu/all
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fsp/src/${SOC_SERIES_PREFIX}/bsp/cmsis/Device/RENESAS/Include
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fsp/src/${SOC_SERIES_PREFIX}/bsp/mcu/${CONFIG_SOC_SERIES}
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)
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zephyr_include_directories(${include_dirs})
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# Optional build base on feature configuration
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zephyr_library_sources_ifdef(CONFIG_USE_RZ_FSP_IOPORT
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fsp/src/${SOC_SERIES_PREFIX}/r_ioport/r_ioport.c)
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zephyr_library_sources_ifdef(CONFIG_USE_RZ_FSP_SCIF_UART
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fsp/src/${SOC_SERIES_PREFIX}/r_scif_uart/r_scif_uart.c)

‎drivers/rz/README

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Flexible Software Package (FSP)
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###############################
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Origin:
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Renesas Electronics Corporation
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https://github.com/renesas/rzg-fsp
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Status:
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version v2.1.0
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Purpose:
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Flexible Software Package (FSP) for Renesas RZ MPU Family.
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Description:
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This package is a snapshot from the RZ FSP software released by Renesas Electronics Corporation
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It contain the HAL and a set of CMSIS headers files for the Renesas RZ MPUs
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Dependencies:
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None.
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URL:
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https://github.com/renesas/rzg-fsp
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Commit:
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8db06f881784144e86361b1266ac4d3c026f6ad8
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Maintained-by:
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Renesas Electronics Corporation
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License:
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BSD-3-Clause
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License Link:
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https://opensource.org/licenses/BSD-3-Clause

‎drivers/rz/fsp/inc/api/r_ioport_api.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*******************************************************************************************************************//**
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* @ingroup RENESAS_INTERFACES
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* @defgroup IOPORT_API I/O Port Interface
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* @brief Interface for accessing I/O ports and configuring I/O functionality.
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*
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* @section IOPORT_API_SUMMARY Summary
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* The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level.
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* Port and pin direction can be changed.
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*
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* IOPORT Interface description: @ref IOPORT
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*
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* @{
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**********************************************************************************************************************/
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#ifndef R_IOPORT_API_H
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#define R_IOPORT_API_H
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/***********************************************************************************************************************
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* Includes
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**********************************************************************************************************************/
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/* Common error codes and definitions. */
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#include "bsp_api.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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/**********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/**********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/** IO port type used with ports */
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typedef uint16_t ioport_size_t; ///< IO port size on this device
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/** PFS writing enable/disable. */
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typedef enum e_ioport_pwpr
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{
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IOPORT_PFS_WRITE_DISABLE = 0, ///< Disable PFS write access
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IOPORT_PFS_WRITE_ENABLE = 1 ///< Enable PFS write access
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} ioport_pwpr_t;
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/** Pin identifier and Pin Function Setting (PFS) value */
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typedef struct st_ioport_pin_cfg
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{
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uint32_t pin_cfg; ///< Pin PFS configuration - Use ioport_cfg_options_t parameters to configure
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bsp_io_port_pin_t pin; ///< Pin identifier
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} ioport_pin_cfg_t;
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/** Multiple pin configuration data for loading into each GPIO register by R_IOPORT_Init() */
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typedef struct st_ioport_cfg
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{
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uint16_t number_of_pins; ///< Number of pins for which there is configuration data
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ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data
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const void * p_extend; ///< Pointer to hardware extend configuration
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} ioport_cfg_t;
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/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls.
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* @par Implemented as
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* - ioport_instance_ctrl_t
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*/
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typedef void ioport_ctrl_t;
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/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */
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typedef struct st_ioport_api
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{
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/** Initialize internal driver data and initial pin configurations. Called during startup. Do
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* not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of
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* multiple pins.
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* @par Implemented as
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* - @ref R_IOPORT_Open()
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* @param[in] p_cfg Pointer to pin configuration data array.
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*/
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fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
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/** Close the API.
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* @par Implemented as
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* - @ref R_IOPORT_Close()
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*
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* @param[in] p_ctrl Pointer to control structure.
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**/
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fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl);
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/** Configure multiple pins.
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* @par Implemented as
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* - @ref R_IOPORT_PinsCfg()
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* @param[in] p_cfg Pointer to pin configuration data array.
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*/
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fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
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/** Configure settings for an individual pin.
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* @par Implemented as
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* - @ref R_IOPORT_PinCfg()
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* @param[in] pin Pin to be read.
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* @param[in] cfg Configuration options for the pin.
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*/
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fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
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/** Read the event input data of the specified pin and return the level.
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* @par Implemented as
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* - @ref R_IOPORT_PinEventInputRead()
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* @param[in] pin Pin to be read.
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* @param[in] p_pin_event Pointer to return the event data.
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*/
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fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
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/** Write pin event data.
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* @par Implemented as
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* - @ref R_IOPORT_PinEventOutputWrite()
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* @param[in] pin Pin event data is to be written to.
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* @param[in] pin_value Level to be written to pin output event.
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*/
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fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
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/** Read level of a pin.
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* @par Implemented as
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* - @ref R_IOPORT_PinRead()
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* @param[in] pin Pin to be read.
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* @param[in] p_pin_value Pointer to return the pin level.
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*/
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fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
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/** Write specified level to a pin.
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* @par Implemented as
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* - @ref R_IOPORT_PinWrite()
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* @param[in] pin Pin to be written to.
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* @param[in] level State to be written to the pin.
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*/
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fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
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/** Set the direction of one or more pins on a port.
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* @par Implemented as
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* - @ref R_IOPORT_PortDirectionSet()
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* @param[in] port Port being configured.
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* @param[in] direction_values Value controlling direction of pins on port
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* (3 - output (input enable), 2 - output (input disable), 1 input, 0 - Hi-Z).
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* @param[in] mask Mask controlling which pins on the port are to be configured.
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*/
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fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values,
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ioport_size_t mask);
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/** Read captured event data for a port.
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* @par Implemented as
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* - @ref R_IOPORT_PortEventInputRead()
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* @param[in] port Port to be read.
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* @param[in] p_event_data Pointer to return the event data.
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*/
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fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
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/** Write event output data for a port.
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* @par Implemented as
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* - @ref R_IOPORT_PortEventOutputWrite()
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* @param[in] port Port event data will be written to.
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* @param[in] event_data Data to be written as event data to specified port.
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* @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data.
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* being written to port.
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*/
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fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data,
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ioport_size_t mask_value);
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/** Read states of pins on the specified port.
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* @par Implemented as
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* - @ref R_IOPORT_PortRead()
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* @param[in] port Port to be read.
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* @param[in] p_port_value Pointer to return the port value.
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*/
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fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
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/** Write to multiple pins on a port.
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* @par Implemented as
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* - @ref R_IOPORT_PortWrite()
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* @param[in] port Port to be written to.
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* @param[in] value Value to be written to the port.
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* @param[in] mask Mask controlling which pins on the port are written to.
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*/
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fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
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} ioport_api_t;
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/** This structure encompasses everything that is needed to use an instance of this interface. */
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typedef struct st_ioport_instance
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{
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ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
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ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
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ioport_api_t const * p_api; ///< Pointer to the API structure for this instance
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} ioport_instance_t;
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/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif
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/*******************************************************************************************************************//**
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* @} (end defgroup IOPORT_API)
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**********************************************************************************************************************/

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