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hal: renesas: rz: Initial support for UART of RZ/V
Initial HAL support for UART of RZ/V Signed-off-by: Hieu Nguyen <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>
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‎drivers/rz/fsp/inc/instances/rzv/r_scif_uart.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef R_SCIF_UART_H
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#define R_SCIF_UART_H
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/*******************************************************************************************************************//**
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* @addtogroup SCIF_UART
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* @{
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Includes
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**********************************************************************************************************************/
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#include "bsp_api.h"
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#include "r_uart_api.h"
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#include "r_scif_uart_cfg.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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#define SCIF_UART_INVALID_16BIT_PARAM (0xFFFFU)
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#define SCIF_UART_INVALID_8BIT_PARAM (0xFFU)
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/**********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/** Enumeration for SCIF clock source */
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typedef enum e_scif_clk_src
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{
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SCIF_UART_CLOCK_INT, ///< Use internal clock for baud generation
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SCIF_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK
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SCIF_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate
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SCIF_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate
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} scif_clk_src_t;
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/** UART communication mode definition */
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typedef enum e_scif_uart_mode
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{
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SCIF_UART_MODE_RS232, ///< Enables RS232 communication mode
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SCIF_UART_MODE_RS485_HD, ///< Enables RS485 half duplex communication mode
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SCIF_UART_MODE_RS485_FD, ///< Enables RS485 full duplex communication mode
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} scif_uart_mode_t;
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/** UART automatic flow control definition */
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typedef enum e_scif_uart_flow_control
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{
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SCIF_UART_FLOW_CONTROL_NONE, ///< Disables flow control
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SCIF_UART_FLOW_CONTROL_AUTO, ///< Enables automatic RTS/CTS flow control
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} scif_uart_flow_control_t;
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/** Noise cancellation configuration. */
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typedef enum e_scif_uart_noise_cancellation
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{
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SCIF_UART_NOISE_CANCELLATION_DISABLE, ///< Disable noise cancellation
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SCIF_UART_NOISE_CANCELLATION_ENABLE, ///< Enable noise cancellation
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} scif_uart_noise_cancellation_t;
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/** RS-485 Enable/Disable. */
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typedef enum e_scif_uart_rs485_enable
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{
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SCIF_UART_RS485_DISABLE = 0, ///< RS-485 disabled.
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SCIF_UART_RS485_ENABLE = 1, ///< RS-485 enabled.
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} scif_uart_rs485_enable_t;
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/** The polarity of the RS-485 DE signal. */
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typedef enum e_scif_uart_rs485_de_polarity
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{
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SCIF_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress.
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SCIF_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress.
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} scif_uart_rs485_de_polarity_t;
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/** Receive FIFO trigger configuration. */
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typedef enum e_scif_uart_rx_fifo_trigger
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{
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SCIF_UART_RX_FIFO_TRIGGER_ONE, ///< Interrupt at least one byte is in FIFO
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SCIF_UART_RX_FIFO_TRIGGER_QUARTER, ///< Interrupt at least quarter of FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_HALF, ///< Interrupt at least half of FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_MAX, ///< Interrupt at almost full in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_1, ///< Interrupt at least 1 byte is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_2, ///< Interrupt at least 2 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_3, ///< Interrupt at least 3 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_4, ///< Interrupt at least 4 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_5, ///< Interrupt at least 5 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_6, ///< Interrupt at least 6 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_7, ///< Interrupt at least 7 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_8, ///< Interrupt at least 8 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_9, ///< Interrupt at least 9 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_10, ///< Interrupt at least 10 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_11, ///< Interrupt at least 11 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_12, ///< Interrupt at least 12 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_13, ///< Interrupt at least 13 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_14, ///< Interrupt at least 14 bytes is in FIFO or 15ETU past from last receive
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SCIF_UART_RX_FIFO_TRIGGER_15, ///< Interrupt at least 15 bytes is in FIFO or 15ETU past from last receive
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} scif_uart_rx_fifo_trigger_t;
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/** RTS trigger level. */
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typedef enum e_scif_uart_rts_trigger
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{
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SCIF_UART_RTS_TRIGGER_1, ///< RTS trigger level = 1
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SCIF_UART_RTS_TRIGGER_4, ///< RTS trigger level = 4
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SCIF_UART_RTS_TRIGGER_6, ///< RTS trigger level = 6
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SCIF_UART_RTS_TRIGGER_8, ///< RTS trigger level = 8
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SCIF_UART_RTS_TRIGGER_10, ///< RTS trigger level = 10
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SCIF_UART_RTS_TRIGGER_12, ///< RTS trigger level = 12
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SCIF_UART_RTS_TRIGGER_14, ///< RTS trigger level = 14
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SCIF_UART_RTS_TRIGGER_15, ///< RTS trigger level = 15
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SCIF_UART_RTS_TRIGGER_DISABLE, ///< Disable RTS trigger
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} scif_uart_rts_trigger_t;
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/** UART instance control block. */
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typedef struct st_scif_uart_instance_ctrl
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{
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/* Parameters to control UART peripheral device */
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uint32_t open; // Used to determine if the channel is configured
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bsp_io_port_pin_t driver_enable_pin;
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/* Source buffer pointer used to fill hardware FIFO from transmit ISR. */
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uint8_t const * p_tx_src;
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/* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */
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uint32_t tx_src_bytes;
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/* Destination buffer pointer used for receiving data. */
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uint8_t * p_rx_dest;
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/* Size of destination buffer pointer used for receiving data. */
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uint32_t rx_dest_bytes;
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/* Pointer to the configuration block. */
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uart_cfg_t const * p_cfg;
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/* Base register for this channel */
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R_SCIFA0_Type * p_reg;
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/* Backup SPTR value for writing */
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uint16_t sptr;
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void (* p_callback)(uart_callback_args_t * p_arg); // Pointer to callback
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uart_callback_args_t * p_callback_memory; // Pointer to pre-allocated callback argument
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/* Pointer to context to be passed into callback function */
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void const * p_context;
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} scif_uart_instance_ctrl_t;
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/** Register settings to achieve a desired baud rate and modulation duty. */
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typedef struct st_scif_baud_setting
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{
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struct
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{
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uint8_t abcs : 1; ///< Asynchronous Mode Base Clock Select
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uint8_t brme : 1; ///< Bit Rate Modulation Enable
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uint8_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select
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uint8_t cks : 2; ///< CKS value to get divisor (CKS = N)
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} semr_baudrate_bits_b;
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uint8_t brr; ///< Bit Rate Register setting
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uint8_t mddr; ///< Modulation Duty Register setting
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} scif_baud_setting_t;
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/** Configuration settings for controlling the DE signal for RS-485. */
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typedef struct st_scif_uart_rs485_setting
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{
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scif_uart_rs485_enable_t enable; ///< Enable the DE signal.
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scif_uart_rs485_de_polarity_t polarity; ///< DE signal polarity.
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bsp_io_port_pin_t de_control_pin; ///< UART Driver Enable pin.
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} scif_uart_rs485_setting_t;
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/** UART on SCIF device Configuration */
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typedef struct st_scif_uart_extended_cfg
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{
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uint8_t bri_ipl; ///< Break interrupt priority
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IRQn_Type bri_irq; ///< Break interrupt IRQ number
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scif_clk_src_t clock; ///< The source clock for the baud-rate generator.
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scif_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting
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scif_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate.
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scif_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level.
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scif_uart_rts_trigger_t rts_fifo_trigger; ///< RTS trigger level.
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scif_uart_mode_t uart_mode; ///< UART communication mode selection
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scif_uart_flow_control_t flow_control; ///< CTS/RTS function
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scif_uart_rs485_setting_t rs485_setting; ///< RS-485 settings.
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} scif_uart_extended_cfg_t;
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/**********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/** @cond INC_HEADER_DEFS_SEC */
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/** Filled in Interface API structure for this Instance. */
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extern const uart_api_t g_uart_on_scif;
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/** @endcond */
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fsp_err_t R_SCIF_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg);
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fsp_err_t R_SCIF_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes);
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fsp_err_t R_SCIF_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes);
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fsp_err_t R_SCIF_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting);
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fsp_err_t R_SCIF_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info);
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fsp_err_t R_SCIF_UART_Close(uart_ctrl_t * const p_api_ctrl);
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fsp_err_t R_SCIF_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort);
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fsp_err_t R_SCIF_UART_BaudCalculate(uart_ctrl_t * const p_api_ctrl,
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uint32_t baudrate,
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bool bitrate_modulation,
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uint32_t baud_rate_error_x_1000,
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scif_baud_setting_t * const p_baud_setting);
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fsp_err_t R_SCIF_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl,
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void ( * p_callback)(uart_callback_args_t * p_arg),
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void const * const p_context,
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uart_callback_args_t * const p_callback_memory);
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fsp_err_t R_SCIF_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes);
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/*******************************************************************************************************************//**
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* @} (end addtogroup SCIF_UART)
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**********************************************************************************************************************/
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/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif /* R_SCIF_UART_H */

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