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Hieu NguyenKhiemNguyenT
Hieu Nguyen
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KhiemNguyenT
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hal: renesas: rza: Initial PWM support for RZ/A series
Add MTU FSP HAL driver to support PWM driver for RZ/A series Signed-off-by: Hieu Nguyen <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>
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‎drivers/rz/CMakeLists.txt

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@@ -82,3 +82,6 @@ else()
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zephyr_library_sources_ifdef(CONFIG_USE_RZ_FSP_SCI_UART
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fsp/src/${SOC_SERIES_PREFIX}/r_sci_uart/r_sci_uart.c)
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endif()
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zephyr_library_sources_ifdef(CONFIG_USE_RZ_FSP_MTU
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fsp/src/${SOC_SERIES_PREFIX}/r_mtu3/r_mtu3.c)

‎drivers/rz/fsp/inc/instances/rza/r_mtu3.h

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef R_MTU3_H
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#define R_MTU3_H
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/*******************************************************************************************************************//**
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* @addtogroup MTU3
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* @{
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Includes
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**********************************************************************************************************************/
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#include "bsp_api.h"
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#include "r_timer_api.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/** I/O Level Select */
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typedef enum e_mtu3_io_pin_level
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{
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MTU3_IO_PIN_LEVEL_NO_OUTPUT = 0, ///< Output prohibited
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MTU3_IO_PIN_LEVEL_INITIAL_LOW_COMPARE_LOW = 1, ///< Initial output is low. Low output at compare match.
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MTU3_IO_PIN_LEVEL_INITIAL_LOW_COMPARE_HIGH = 2, ///< Initial output is low. High output at compare match.
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MTU3_IO_PIN_LEVEL_INITIAL_LOW_COMPARE_TOGGLE = 3, ///< Initial output is low. Toggle output at compare match.
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MTU3_IO_PIN_LEVEL_INITIAL_HIGH_COMPARE_LOW = 5, ///< Initial output is high. Low output at compare match.
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MTU3_IO_PIN_LEVEL_INITIAL_HIGH_COMPARE_HIGH = 6, ///< Initial output is high. High output at compare match.
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MTU3_IO_PIN_LEVEL_INITIAL_HIGH_COMPARE_TOGGLE = 7, ///< Initial output is high. Toggle output at compare match.
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MTU3_IO_PIN_LEVEL_INPUT_RISING_EDGE = 8, ///< Input capture at rising edge.
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MTU3_IO_PIN_LEVEL_INPUT_FALLING_EDGE = 9, ///< Input capture at falling edge.
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MTU3_IO_PIN_LEVEL_INPUT_BOTH_EDGE = 10, ///< Input capture at both edges.
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} mtu3_io_pin_level_t;
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/** Clock Edge Select */
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typedef enum e_mtu3_clock_edge
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{
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MTU3_CLOCK_EDGE_RISING = 0x0, ///< Count at rising edge
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MTU3_CLOCK_EDGE_FALLING = 0x1, ///< Count at falling edge
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MTU3_CLOCK_EDGE_BOTH = 0x2, ///< Count at both edges
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} mtu3_clock_edge_t;
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/** Time Prescaler Select */
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typedef enum e_mtu3_clock_div
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{
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MTU3_CLOCK_DIV_1 = 0x0, ///< CLOCK divided by 1 (common ch)
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MTU3_CLOCK_DIV_4 = 0x1, ///< CLOCK divided by 4 (common ch)
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MTU3_CLOCK_DIV_16 = 0x2, ///< CLOCK divided by 16 (common ch)
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MTU3_CLOCK_DIV_64 = 0x3, ///< CLOCK divided by 64 (common ch)
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MTU3_CLOCK_DIV_2 = 0x8, ///< CLOCK divided by 2 (common ch)
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MTU3_CLOCK_DIV_8 = 0x10, ///< CLOCK divided by 8 (common ch)
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MTU3_CLOCK_DIV_32 = 0x18, ///< CLOCK divided by 32 (common ch)
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MTU3_CLOCK_DIV_MTCLKA_CH_0 = 0x4, ///< External clock: counts on MTCLKA pin input (ch0)
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MTU3_CLOCK_DIV_MTCLKB_CH_0 = 0x5, ///< External clock: counts on MTCLKB pin input (ch0)
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MTU3_CLOCK_DIV_MTCLKC_CH_0 = 0x6, ///< External clock: counts on MTCLKC pin input (ch0)
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MTU3_CLOCK_DIV_MTCLKD_CH_0 = 0x7, ///< External clock: counts on MTCLKD pin input (ch0)
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MTU3_CLOCK_DIV_256_CH_0 = 0x20, ///< CLOCK divided by 256 (ch0)
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MTU3_CLOCK_DIV_1024_CH_0 = 0x28, ///< CLOCK divided by 1024 (ch0)
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MTU3_CLOCK_DIV_MTIOC1A_CH_0 = 0x38, ///< External clock: counts on MTIOC1A pin input (ch0)
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MTU3_CLOCK_DIV_MTCLKA_CH_1 = 0x4, ///< External clock: counts on MTCLKA pin input (ch1)
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MTU3_CLOCK_DIV_MTCLKB_CH_1 = 0x5, ///< External clock: counts on MTCLKB pin input (ch1)
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MTU3_CLOCK_DIV_256_CH_1 = 0x6, ///< CLOCK divided by 256 (ch1)
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MTU3_CLOCK_DIV_TCNT_CH1 = 0x7, ///< Overflow/underflow of MTU2.TCNT
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MTU3_CLOCK_DIV_1024_CH_1 = 0x20, ///< CLOCK divided by 1024 (ch1)
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MTU3_CLOCK_DIV_MTCLKA_CH_2 = 0x4, ///< External clock: counts on MTCLKA pin input (ch2)
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MTU3_CLOCK_DIV_MTCLKB_CH_2 = 0x5, ///< External clock: counts on MTCLKB pin input (ch2)
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MTU3_CLOCK_DIV_MTCLKC_CH_2 = 0x6, ///< External clock: counts on MTCLKC pin input (ch2)
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MTU3_CLOCK_DIV_1024_CH_2 = 0x7, ///< CLOCK divided by 1024 (ch2)
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MTU3_CLOCK_DIV_256_CH_2 = 0x20, ///< CLOCK divided by 256 (ch2)
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MTU3_CLOCK_DIV_256_CH_3_4_6_7_8 = 0x4, ///< CLOCK divided by 256 (ch3-4, 6-8)
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MTU3_CLOCK_DIV_1024_CH_3_4_6_7_8 = 0x5, ///< CLOCK divided by 1024 (ch3-4, 6-8)
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MTU3_CLOCK_DIV_MTCLKA_CH_3_4_6_7_8 = 0x6, ///< External clock: counts on MTCLKA pin input (ch3-4, 6-8)
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MTU3_CLOCK_DIV_MTCLKB_CH_3_4_6_7_8 = 0x7, ///< External clock: counts on MTCLKB pin input (ch3-4, 6-8)
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} mtu3_clock_div_t;
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/** Counter Clear Source Select */
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typedef enum e_mtu3_tcnt_clear
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{
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MTU3_TCNT_CLEAR_DISABLE = 0x0, ///< TCNT clearing disabled
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MTU3_TCNT_CLEAR_TGRA = 0x1, ///< TCNT cleared by TGRA compare match/input capture
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MTU3_TCNT_CLEAR_TGRB = 0x2, ///< TCNT cleared by TGRB compare match/input capture
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} mtu3_tcnt_clear_t;
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/** Level of MTU3 pin */
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typedef enum e_mtu3_io_pin
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{
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MTU3_IO_PIN_MTIOCA = 0, ///< MTIOCA
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MTU3_IO_PIN_MTIOCB = 1, ///< MTIOCB
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MTU3_IO_PIN_MTIOCA_AND_MTIOCB = 2, ///< MTIOCA and MTIOCB
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} mtu3_io_pin_t;
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/** Configurations for output pins. */
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typedef struct st_mtu3_output_pin
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{
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mtu3_io_pin_level_t output_pin_level_a; ///< I/O Control A
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mtu3_io_pin_level_t output_pin_level_b; ///< I/O Control B
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} mtu3_output_pin_t;
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/** Disables or enables the noise filter for input from the MTIOCnA pin */
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typedef enum e_mtu3_noise_filter
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{
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MTU3_NOISE_FILTER_DISABLE = 0U, ///< The noise filter for the MTIOC pin is disabled
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MTU3_NOISE_FILTER_A_ENABLE = 1U, ///< The noise filter for the MTIOCA pin is enabled
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MTU3_NOISE_FILTER_B_ENABLE = 2U, ///< The noise filter for the MTIOCB pin is enabled
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} mtu3_noise_filter_t;
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/** Disables or enables the noise filter for the external clock input pins of the MTU */
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typedef enum e_mtu3_noise_filter_external
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{
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MTU3_NOISE_FILTER_MTCLK_DISABLE = 0U, ///< The noise filter for the MTCLK pin is disabled
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MTU3_NOISE_FILTER_MTCLK_A_ENABLE = 1U, ///< The noise filter for the MTCLKA pin is enabled.
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MTU3_NOISE_FILTER_MTCLK_B_ENABLE = 2U, ///< The noise filter for the MTCLKB pin is enabled.
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MTU3_NOISE_FILTER_MTCLK_C_ENABLE = 4U, ///< The noise filter for the MTCLKC pin is enabled.
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MTU3_NOISE_FILTER_MTCLK_D_ENABLE = 8U, ///< The noise filter for the MTCLKD pin is enabled.
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} mtu3_noise_filter_mtclk_t;
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typedef enum e_mtu3_noise_filter_clock
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{
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MTU3_NOISE_FILTER_CLOCK_DIV_1 = 0U, ///< CLK/1 - fast sampling
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MTU3_NOISE_FILTER_CLOCK_DIV_8 = 1U, ///< CLK/8
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MTU3_NOISE_FILTER_CLOCK_DIV_32 = 2U, ///< CLK/32 - slow sampling
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MTU3_NOISE_FILTER_CLOCK_SOURCE = 3U, ///< Clock source for counting
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} mtu3_noise_filter_clock_t;
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typedef enum e_mtu3_noise_filter_external_clock
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{
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MTU3_NOISE_FILTER_EXTERNAL_CLOCK_DIV_1 = 0U, ///< CLK/1 - fast sampling
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MTU3_NOISE_FILTER_EXTERNAL_CLOCK_DIV_2 = 1U, ///< CLK/2
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MTU3_NOISE_FILTER_EXTERNAL_CLOCK_DIV_8 = 2U, ///< CLK/8
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MTU3_NOISE_FILTER_EXTERNAL_CLOCK_DIV_32 = 3U, ///< CLK/32 - slow sampling
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} mtu3_noise_filter_external_clock_t;
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/** Interrupt Skipping Function Select */
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typedef enum e_mtu3_interrupt_skip_mode
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{
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MTU3_INTERRUPT_SKIP_MODE_1 = 0U, ///< Setting the TITCR1A or TITCR1B register enables
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MTU3_INTERRUPT_SKIP_MODE_2 = 1U, ///< Setting the TITCR2A or TITCR2B register enables
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} mtu3_interrupt_skip_mode_t;
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/** Number of interrupts to skip between events */
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typedef enum e_mtu3_interrupt_skip_count
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{
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MTU3_INTERRUPT_SKIP_COUNT_0 = 0U, ///< Do not skip interrupts
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MTU3_INTERRUPT_SKIP_COUNT_1, ///< Skip one interrupt
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MTU3_INTERRUPT_SKIP_COUNT_2, ///< Skip two interrupts
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MTU3_INTERRUPT_SKIP_COUNT_3, ///< Skip three interrupts
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MTU3_INTERRUPT_SKIP_COUNT_4, ///< Skip four interrupts
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MTU3_INTERRUPT_SKIP_COUNT_5, ///< Skip five interrupts
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MTU3_INTERRUPT_SKIP_COUNT_6, ///< Skip six interrupts
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MTU3_INTERRUPT_SKIP_COUNT_7, ///< Skip seven interrupts
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} mtu3_interrupt_skip_count_t;
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/** Trigger options to start A/D conversion. */
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typedef enum e_mtu3_adc_compare_match
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{
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MTU3_ADC_COMPARE_MATCH_ADC_A = 0x1U, ///< Set A/D conversion start request value for MTU3 A/D converter start request A
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MTU3_ADC_COMPARE_MATCH_ADC_B = 0x2U, ///< Set A/D conversion start request value for MTU3 A/D converter start request B
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} mtu3_adc_compare_match_t;
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typedef enum e_mtu3_adc_tgra_compare_match
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{
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MTU3_ADC_TGRA_COMPARE_MATCH_DISABLE = 0U, ///< A/D Converter Activation by TGRA Input Capture/Compare Match Disable
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MTU3_ADC_TGRA_COMPARE_MATCH_ENABLE = 1U, ///< A/D Converter Activation by TGRA Input Capture/Compare Match Enable
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} mtu3_adc_activation_tgra_compare_match_t;
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/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */
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typedef struct st_mtu3_instance_ctrl
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{
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uint32_t open; ///< Whether or not channel is open
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const timer_cfg_t * p_cfg; ///< Pointer to initial configurations
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void * p_reg; ///< Base register for this channel
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R_MTU_Type * p_reg_com; ///< Base register for this channel(common ch)
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void * p_reg_nf; ///< Base register for this channel(noise fileter)
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uint32_t channel_mask; ///< Channel bitmask
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void (* p_callback)(timer_callback_args_t *); ///< Pointer to callback
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timer_callback_args_t * p_callback_memory; ///< Pointer to optional callback argument memory
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void const * p_context; ///< Pointer to context to be passed into callback function
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} mtu3_instance_ctrl_t;
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/** MTU3 extension for advanced PWM features. */
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typedef struct st_mtu3_extended_pwm_cfg
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{
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mtu3_interrupt_skip_mode_t interrupt_skip_mode_a; ///< Selects interrupt skipping function 1 or 2(TIMTRA)
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mtu3_interrupt_skip_mode_t interrupt_skip_mode_b; ///< Selects interrupt skipping function 1 or 2(TIMTRB)
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uint16_t adc_a_compare_match; ///< Timer A/D Converter Start Request Cycle A (MTU4 or MTU7)
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uint16_t adc_b_compare_match; ///< Timer A/D Converter Start Request Cycle B (MTU4 or MTU7)
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mtu3_interrupt_skip_count_t interrupt_skip_count_tciv4; ///< TCIV4 Interrupt Skipping Count Setting(TITCR1A)
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mtu3_interrupt_skip_count_t interrupt_skip_count_tgia3; ///< TGIA3 Interrupt Skipping Count Setting(TITCR1A)
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mtu3_interrupt_skip_count_t interrupt_skip_count_tciv7; ///< TCIV7 Interrupt Skipping Count Setting(TITCR1B)
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mtu3_interrupt_skip_count_t interrupt_skip_count_tgia6; ///< TGIA6 Interrupt Skipping Count Setting(TITCR1B)
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mtu3_interrupt_skip_count_t interrupt_skip_count_tgr4an_bn; ///< TRG4AN/TRG4BN Interrupt Skipping Count Setting(TITCR2A)
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mtu3_interrupt_skip_count_t interrupt_skip_count_tgr7an_bn; ///< TRG7AN/TRG7BN Interrupt Skipping Count Setting(TITCR2B)
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} mtu3_extended_pwm_cfg_t;
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/** The MTU3 extension constitutes a unique feature of MTU3. */
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typedef struct st_mtu3_extended_cfg
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{
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uint32_t tgra_val; ///< Capture/Compare match A register
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uint32_t tgrb_val; ///< Capture/Compare match B register
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uint32_t tgrc_val; ///< Capture/Compare match C register (Does not exist in MTU ch1-2)
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uint32_t tgrd_val; ///< Capture/Compare match D register (Does not exist in MTU ch1-2)
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mtu3_clock_div_t mtu3_clk_div; ///< Time Prescaler Select
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mtu3_clock_edge_t clk_edge; ///< Clock Edge Select
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mtu3_tcnt_clear_t mtu3_clear; ///< Counter Clear Source Select
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mtu3_output_pin_t mtioc_ctrl_setting; ///< I/O Control A, B
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/* Debounce filter for MTIOCxA or MTIOCxB input signal pin. */
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mtu3_noise_filter_t noise_filter_mtioc_setting;
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mtu3_noise_filter_clock_t noise_filter_mtioc_clk;
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/* Debounce filter for MTCLKx input signal pin. */
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mtu3_noise_filter_mtclk_t noise_filter_mtclk_setting;
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mtu3_noise_filter_external_clock_t noise_filter_mtclk_clk;
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/* A/D Converter Activation by TGRA Input Capture/Compare Match. */
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mtu3_adc_activation_tgra_compare_match_t adc_activation_setting;
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/* Used for other than MTU5 */
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uint8_t capture_a_ipl; ///< Capture/Compare match A interrupt priority
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uint8_t capture_b_ipl; ///< Capture/Compare match B interrupt priority
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IRQn_Type capture_a_irq; ///< Capture/Compare match A interrupt
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IRQn_Type capture_b_irq; ///< Capture/Compare match B interrupt
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mtu3_extended_pwm_cfg_t const * p_pwm_cfg; ///< Advanced PWM features, optional
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} mtu3_extended_cfg_t;
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/**********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/** @cond INC_HEADER_DEFS_SEC */
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/** Filled in Interface API structure for this Instance. */
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extern const timer_api_t g_timer_on_mtu3;
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/** @endcond */
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/***********************************************************************************************************************
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* Public APIs
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**********************************************************************************************************************/
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fsp_err_t R_MTU3_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
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fsp_err_t R_MTU3_Stop(timer_ctrl_t * const p_ctrl);
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fsp_err_t R_MTU3_Start(timer_ctrl_t * const p_ctrl);
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fsp_err_t R_MTU3_Reset(timer_ctrl_t * const p_ctrl);
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fsp_err_t R_MTU3_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts);
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fsp_err_t R_MTU3_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
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fsp_err_t R_MTU3_CompareMatchSet(timer_ctrl_t * const p_ctrl,
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uint32_t const compare_match_value,
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timer_compare_match_t const match_channel);
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fsp_err_t R_MTU3_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
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fsp_err_t R_MTU3_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
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fsp_err_t R_MTU3_CounterSet(timer_ctrl_t * const p_ctrl, uint32_t counter);
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fsp_err_t R_MTU3_OutputEnable(timer_ctrl_t * const p_ctrl, mtu3_output_pin_t pin_level);
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fsp_err_t R_MTU3_OutputDisable(timer_ctrl_t * const p_ctrl, mtu3_io_pin_t pin);
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fsp_err_t R_MTU3_Enable(timer_ctrl_t * const p_ctrl);
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fsp_err_t R_MTU3_Disable(timer_ctrl_t * const p_ctrl);
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fsp_err_t R_MTU3_AdcTriggerSet(timer_ctrl_t * const p_ctrl,
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mtu3_adc_compare_match_t which_compare_match,
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uint16_t compare_match_value);
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fsp_err_t R_MTU3_CallbackSet(timer_ctrl_t * const p_api_ctrl,
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void ( * p_callback)(timer_callback_args_t *),
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void const * const p_context,
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timer_callback_args_t * const p_callback_memory);
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fsp_err_t R_MTU3_Close(timer_ctrl_t * const p_ctrl);
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/*******************************************************************************************************************//**
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* @} (end defgroup MTU3)
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**********************************************************************************************************************/
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/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif

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