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thaoluonguwandrzej-kaczmarek
thaoluonguw
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andrzej-kaczmarek
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hal: renesas: ra: Add bsp configuration files for ra8m1
Move cfg files from zephyr OS to hal_renesas Signed-off-by: Thao Luong <[email protected]>
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‎ra/CMakeLists.txt‎

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@@ -21,6 +21,7 @@ zephyr_library_sources(${srcs})
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message(${CONFIG_SOC_SERIES})
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zephyr_include_directories(fsp/ra/fsp/src/bsp/mcu/${CONFIG_SOC_SERIES})
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zephyr_include_directories(ra_cfg/fsp_cfg/bsp/${CONFIG_SOC_SERIES})
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# Optional build base on feature configuration
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zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_SCI_B_UART

‎ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_cfg.h‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RA_COMMON_BSP_CFG_H_
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#define ZEPHYR_SOC_RENESAS_RA_COMMON_BSP_CFG_H_
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#include "soc.h"
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
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/* Add for zephyr porting */
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#define BSP_CFG_INTERRUPT_INIT 0
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#define BSP_CFG_SP_MON_INIT 0
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#endif
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#endif /* ZEPHYR_SOC_RENESAS_RA_COMMON_BSP_CFG_H_ */

‎ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_clock_cfg.h‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <zephyr/devicetree.h>
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#ifndef BSP_CLOCK_CFG_H_
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#define BSP_CLOCK_CFG_H_
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#define BSP_CFG_CLOCKS_SECURE (0)
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#define BSP_CFG_CLOCKS_OVERRIDE (0)
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#define BSP_CFG_XTAL_HZ DT_PROP(DT_NODELABEL(xtal), clock_frequency)
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#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 16000000
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#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 16MHz */
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#elif DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 18000000
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#define BSP_CFG_HOCO_FREQUENCY 1 /* HOCO 18MHz */
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#elif DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 20000000
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#define BSP_CFG_HOCO_FREQUENCY 2 /* HOCO 20MHz */
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#elif DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 32000000
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#define BSP_CFG_HOCO_FREQUENCY 4 /* HOCO 32MHz */
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#elif DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 48000000
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#define BSP_CFG_HOCO_FREQUENCY 7 /* HOCO 48MHz */
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#else
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#error "Invalid HOCO frequency, only can be set to 16MHz, 18MHz, 20MHz, 32MHz, 48MHz"
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#endif
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#define BSP_CFG_PLL_SOURCE DT_PROP(DT_NODELABEL(clock), pll_source)
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#define BSP_CFG_PLL_DIV DT_PROP(DT_NODELABEL(clock), pll_div)
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#define BSP_CFG_PLL_MUL \
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BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(clock), pll_mul, 0), \
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DT_PROP_BY_IDX(DT_NODELABEL(clock), pll_mul, 1))
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#define BSP_CFG_PLODIVP DT_PROP(DT_NODELABEL(clock), pll_divp)
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#define BSP_CFG_PLL1P_FREQUENCY_HZ DT_PROP(DT_NODELABEL(clock), pll_freqp)
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#define BSP_CFG_PLODIVQ DT_PROP(DT_NODELABEL(clock), pll_divq)
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#define BSP_CFG_PLL1Q_FREQUENCY_HZ DT_PROP(DT_NODELABEL(clock), pll_freqq)
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#define BSP_CFG_PLODIVR DT_PROP(DT_NODELABEL(clock), pll_divr)
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#define BSP_CFG_PLL1R_FREQUENCY_HZ DT_PROP(DT_NODELABEL(clock), pll_freqr)
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#define BSP_CFG_PLL2_SOURCE DT_PROP(DT_NODELABEL(clock), pll2_source)
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#define BSP_CFG_PLL2_DIV DT_PROP(DT_NODELABEL(clock), pll2_div)
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#define BSP_CFG_PLL2_MUL \
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BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(clock), pll2_mul, 0), \
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DT_PROP_BY_IDX(DT_NODELABEL(clock), pll2_mul, 1))
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#define BSP_CFG_PL2ODIVP DT_PROP(DT_NODELABEL(clock), pll2_divp)
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#define BSP_CFG_PLL2P_FREQUENCY_HZ DT_PROP(DT_NODELABEL(clock), pll2_freqp)
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#define BSP_CFG_PL2ODIVQ DT_PROP(DT_NODELABEL(clock), pll2_divq)
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#define BSP_CFG_PLL2Q_FREQUENCY_HZ DT_PROP(DT_NODELABEL(clock), pll2_freqq)
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#define BSP_CFG_PL2ODIVR DT_PROP(DT_NODELABEL(clock), pll2_divr)
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#define BSP_CFG_PLL2R_FREQUENCY_HZ DT_PROP(DT_NODELABEL(clock), pll2_freqr)
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#define BSP_CFG_CLOCK_SOURCE DT_PROP(DT_NODELABEL(clock), sysclock_source)
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#define BSP_CFG_CPUCLK_DIV DT_PROP(DT_NODELABEL(clock), cpuclk_div)
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#define BSP_CFG_ICLK_DIV DT_PROP(DT_NODELABEL(clock), iclk_div)
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#define BSP_CFG_PCLKA_DIV DT_PROP(DT_NODELABEL(clock), pclka_div)
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#define BSP_CFG_PCLKB_DIV DT_PROP(DT_NODELABEL(clock), pclkb_div)
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#define BSP_CFG_PCLKC_DIV DT_PROP(DT_NODELABEL(clock), pclkc_div)
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#define BSP_CFG_PCLKD_DIV DT_PROP(DT_NODELABEL(clock), pclkd_div)
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#define BSP_CFG_PCLKE_DIV DT_PROP(DT_NODELABEL(clock), pclke_div)
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#define BSP_CFG_BCLK_DIV DT_PROP(DT_NODELABEL(clock), bclk_div)
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#define BSP_CFG_BCLK_OUTPUT DT_PROP(DT_NODELABEL(clock), bclk_out)
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#define BSP_CFG_FCLK_DIV DT_PROP(DT_NODELABEL(clock), fclk_div)
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#define BSP_CFG_SDCLK_OUTPUT DT_PROP(DT_NODELABEL(clock), sdclk_out)
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#define BSP_CFG_UCK_SOURCE DT_PROP(DT_NODELABEL(clock), uclk_source)
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#define BSP_CFG_UCK_DIV DT_PROP(DT_NODELABEL(clock), uclk_div)
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#define BSP_CFG_U60CK_SOURCE DT_PROP(DT_NODELABEL(clock), u60clk_source)
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#define BSP_CFG_U60CK_DIV DT_PROP(DT_NODELABEL(clock), u60clk_div)
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#define BSP_CFG_OCTA_SOURCE DT_PROP(DT_NODELABEL(clock), octaspiclk_source)
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#define BSP_CFG_OCTA_DIV DT_PROP(DT_NODELABEL(clock), octaspiclk_div)
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#define BSP_CFG_CANFDCLK_SOURCE DT_PROP(DT_NODELABEL(clock), canfdclk_source)
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#define BSP_CFG_CANFDCLK_DIV DT_PROP(DT_NODELABEL(clock), canfdclk_div)
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#define BSP_CFG_CLKOUT_SOURCE DT_PROP(DT_NODELABEL(clock), clkout_source)
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#define BSP_CFG_CLKOUT_DIV DT_PROP(DT_NODELABEL(clock), clkout_div)
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#define BSP_CFG_SCICLK_SOURCE DT_PROP(DT_NODELABEL(clock), sciclk_source)
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#define BSP_CFG_SCICLK_DIV DT_PROP(DT_NODELABEL(clock), sciclk_div)
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#define BSP_CFG_SPICLK_SOURCE DT_PROP(DT_NODELABEL(clock), spiclk_source)
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#define BSP_CFG_SPICLK_DIV DT_PROP(DT_NODELABEL(clock), spiclk_div)
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#define BSP_CFG_ADCCLK_SOURCE DT_PROP(DT_NODELABEL(clock), adcclk_source)
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#define BSP_CFG_ADCCLK_DIV DT_PROP(DT_NODELABEL(clock), adcclk_div)
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#define BSP_CFG_I3CCLK_SOURCE DT_PROP(DT_NODELABEL(clock), i3cclk_source)
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#define BSP_CFG_I3CCLK_DIV DT_PROP(DT_NODELABEL(clock), i3cclk_div)
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#endif /* BSP_CLOCK_CFG_H_ */

‎ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_mcu_device_cfg.h‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSP_MCU_DEVICE_CFG_H_
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#define BSP_MCU_DEVICE_CFG_H_
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#define BSP_CFG_MCU_PART_SERIES (8)
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#endif /* BSP_MCU_DEVICE_CFG_H_ */

‎ra/ra_cfg/fsp_cfg/bsp/ra8m1/bsp_mcu_device_pn_cfg.h‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSP_MCU_DEVICE_PN_CFG_H_
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#if defined(CONFIG_SOC_R7FA8M1AHECBD)
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#define BSP_MCU_R7FA8M1AHECBD
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#define BSP_MCU_FEATURE_SET ('A')
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#define BSP_ROM_SIZE_BYTES (2064384)
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#define BSP_RAM_SIZE_BYTES (917504)
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#define BSP_DATA_FLASH_SIZE_BYTES (12288)
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#define BSP_PACKAGE_BGA
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#define BSP_PACKAGE_PINS (224)
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#endif
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#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

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