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Danh DoanKhiemNguyenT
Danh Doan
authored and
KhiemNguyenT
committed
hal: renesas: ra: initial support for sdram controller
Initial support SDRAM on Renesas RA SoC Signed-off-by: Danh Doan <[email protected]>
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5 files changed

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-280
lines changed

5 files changed

+263
-280
lines changed

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m2/bsp_mcu_family_cfg.h

Lines changed: 52 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -45,65 +45,61 @@ extern "C" {
4545
* g_interrupt_event_link_select. */
4646
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
4747

48-
#ifndef BSP_CFG_SDRAM_ENABLED
48+
/* SDRAM controller configuration */
49+
#if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram))
50+
#define BSP_CFG_SDRAM_ENABLED (1)
51+
#define BSP_CFG_SDRAM_TRAS \
52+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
53+
renesas_ra_sdram_timing, 0)
54+
#define BSP_CFG_SDRAM_TRCD \
55+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
56+
renesas_ra_sdram_timing, 1)
57+
#define BSP_CFG_SDRAM_TRP \
58+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
59+
renesas_ra_sdram_timing, 2)
60+
#define BSP_CFG_SDRAM_TWR \
61+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
62+
renesas_ra_sdram_timing, 3)
63+
#define BSP_CFG_SDRAM_TCL \
64+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
65+
renesas_ra_sdram_timing, 4)
66+
#define BSP_CFG_SDRAM_TRFC \
67+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
68+
renesas_ra_sdram_timing, 5)
69+
#define BSP_CFG_SDRAM_TREFW \
70+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
71+
renesas_ra_sdram_timing, 6)
72+
#define BSP_CFG_SDRAM_INIT_ARFI \
73+
DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_interval)
74+
#define BSP_CFG_SDRAM_INIT_ARFC \
75+
DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_count)
76+
#define BSP_CFG_SDRAM_INIT_PRC \
77+
DT_PROP(DT_INST(0, renesas_ra_sdram), precharge_cycle_count)
78+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT \
79+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), multiplex_addr_shift)
80+
#define BSP_CFG_SDRAM_ENDIAN_MODE \
81+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), edian_mode)
82+
#define BSP_CFG_SDRAM_ACCESS_MODE \
83+
DT_PROP(DT_INST(0, renesas_ra_sdram), continuous_access)
84+
#define BSP_CFG_SDRAM_BUS_WIDTH \
85+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), bus_width)
86+
#else
4987
#define BSP_CFG_SDRAM_ENABLED (0)
50-
#endif
51-
52-
#ifndef BSP_CFG_SDRAM_TRAS
53-
#define BSP_CFG_SDRAM_TRAS (6)
54-
#endif
55-
56-
#ifndef BSP_CFG_SDRAM_TRCD
57-
#define BSP_CFG_SDRAM_TRCD (3)
58-
#endif
59-
60-
#ifndef BSP_CFG_SDRAM_TRP
61-
#define BSP_CFG_SDRAM_TRP (3)
62-
#endif
63-
64-
#ifndef BSP_CFG_SDRAM_TWR
65-
#define BSP_CFG_SDRAM_TWR (2)
66-
#endif
67-
68-
#ifndef BSP_CFG_SDRAM_TCL
69-
#define BSP_CFG_SDRAM_TCL (3)
70-
#endif
71-
72-
#ifndef BSP_CFG_SDRAM_TRFC
73-
#define BSP_CFG_SDRAM_TRFC (937)
74-
#endif
75-
76-
#ifndef BSP_CFG_SDRAM_TREFW
77-
#define BSP_CFG_SDRAM_TREFW (8)
78-
#endif
79-
80-
#ifndef BSP_CFG_SDRAM_INIT_ARFI
81-
#define BSP_CFG_SDRAM_INIT_ARFI (10)
82-
#endif
83-
84-
#ifndef BSP_CFG_SDRAM_INIT_ARFC
85-
#define BSP_CFG_SDRAM_INIT_ARFC (8)
86-
#endif
87-
88-
#ifndef BSP_CFG_SDRAM_INIT_PRC
89-
#define BSP_CFG_SDRAM_INIT_PRC (3)
90-
#endif
91-
92-
#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT
93-
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (1)
94-
#endif
95-
96-
#ifndef BSP_CFG_SDRAM_ENDIAN_MODE
88+
#define BSP_CFG_SDRAM_TRAS (0)
89+
#define BSP_CFG_SDRAM_TRCD (0)
90+
#define BSP_CFG_SDRAM_TRP (0)
91+
#define BSP_CFG_SDRAM_TWR (0)
92+
#define BSP_CFG_SDRAM_TCL (0)
93+
#define BSP_CFG_SDRAM_TRFC (0)
94+
#define BSP_CFG_SDRAM_TREFW (0)
95+
#define BSP_CFG_SDRAM_INIT_ARFI (0)
96+
#define BSP_CFG_SDRAM_INIT_ARFC (0)
97+
#define BSP_CFG_SDRAM_INIT_PRC (0)
98+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (0)
9799
#define BSP_CFG_SDRAM_ENDIAN_MODE (0)
98-
#endif
99-
100-
#ifndef BSP_CFG_SDRAM_ACCESS_MODE
101-
#define BSP_CFG_SDRAM_ACCESS_MODE (1)
102-
#endif
103-
104-
#ifndef BSP_CFG_SDRAM_BUS_WIDTH
100+
#define BSP_CFG_SDRAM_ACCESS_MODE (0)
105101
#define BSP_CFG_SDRAM_BUS_WIDTH (0)
106-
#endif
102+
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) */
107103

108104
#ifdef __cplusplus
109105
}

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m3/bsp_mcu_family_cfg.h

Lines changed: 52 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -45,65 +45,61 @@ extern "C" {
4545
* g_interrupt_event_link_select. */
4646
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
4747

48-
#ifndef BSP_CFG_SDRAM_ENABLED
48+
/* SDRAM controller configuration */
49+
#if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram))
50+
#define BSP_CFG_SDRAM_ENABLED (1)
51+
#define BSP_CFG_SDRAM_TRAS \
52+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
53+
renesas_ra_sdram_timing, 0)
54+
#define BSP_CFG_SDRAM_TRCD \
55+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
56+
renesas_ra_sdram_timing, 1)
57+
#define BSP_CFG_SDRAM_TRP \
58+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
59+
renesas_ra_sdram_timing, 2)
60+
#define BSP_CFG_SDRAM_TWR \
61+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
62+
renesas_ra_sdram_timing, 3)
63+
#define BSP_CFG_SDRAM_TCL \
64+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
65+
renesas_ra_sdram_timing, 4)
66+
#define BSP_CFG_SDRAM_TRFC \
67+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
68+
renesas_ra_sdram_timing, 5)
69+
#define BSP_CFG_SDRAM_TREFW \
70+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
71+
renesas_ra_sdram_timing, 6)
72+
#define BSP_CFG_SDRAM_INIT_ARFI \
73+
DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_interval)
74+
#define BSP_CFG_SDRAM_INIT_ARFC \
75+
DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_count)
76+
#define BSP_CFG_SDRAM_INIT_PRC \
77+
DT_PROP(DT_INST(0, renesas_ra_sdram), precharge_cycle_count)
78+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT \
79+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), multiplex_addr_shift)
80+
#define BSP_CFG_SDRAM_ENDIAN_MODE \
81+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), edian_mode)
82+
#define BSP_CFG_SDRAM_ACCESS_MODE \
83+
DT_PROP(DT_INST(0, renesas_ra_sdram), continuous_access)
84+
#define BSP_CFG_SDRAM_BUS_WIDTH \
85+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), bus_width)
86+
#else
4987
#define BSP_CFG_SDRAM_ENABLED (0)
50-
#endif
51-
52-
#ifndef BSP_CFG_SDRAM_TRAS
53-
#define BSP_CFG_SDRAM_TRAS (6)
54-
#endif
55-
56-
#ifndef BSP_CFG_SDRAM_TRCD
57-
#define BSP_CFG_SDRAM_TRCD (3)
58-
#endif
59-
60-
#ifndef BSP_CFG_SDRAM_TRP
61-
#define BSP_CFG_SDRAM_TRP (3)
62-
#endif
63-
64-
#ifndef BSP_CFG_SDRAM_TWR
65-
#define BSP_CFG_SDRAM_TWR (2)
66-
#endif
67-
68-
#ifndef BSP_CFG_SDRAM_TCL
69-
#define BSP_CFG_SDRAM_TCL (3)
70-
#endif
71-
72-
#ifndef BSP_CFG_SDRAM_TRFC
73-
#define BSP_CFG_SDRAM_TRFC (937)
74-
#endif
75-
76-
#ifndef BSP_CFG_SDRAM_TREFW
77-
#define BSP_CFG_SDRAM_TREFW (8)
78-
#endif
79-
80-
#ifndef BSP_CFG_SDRAM_INIT_ARFI
81-
#define BSP_CFG_SDRAM_INIT_ARFI (10)
82-
#endif
83-
84-
#ifndef BSP_CFG_SDRAM_INIT_ARFC
85-
#define BSP_CFG_SDRAM_INIT_ARFC (8)
86-
#endif
87-
88-
#ifndef BSP_CFG_SDRAM_INIT_PRC
89-
#define BSP_CFG_SDRAM_INIT_PRC (3)
90-
#endif
91-
92-
#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT
93-
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (1)
94-
#endif
95-
96-
#ifndef BSP_CFG_SDRAM_ENDIAN_MODE
88+
#define BSP_CFG_SDRAM_TRAS (0)
89+
#define BSP_CFG_SDRAM_TRCD (0)
90+
#define BSP_CFG_SDRAM_TRP (0)
91+
#define BSP_CFG_SDRAM_TWR (0)
92+
#define BSP_CFG_SDRAM_TCL (0)
93+
#define BSP_CFG_SDRAM_TRFC (0)
94+
#define BSP_CFG_SDRAM_TREFW (0)
95+
#define BSP_CFG_SDRAM_INIT_ARFI (0)
96+
#define BSP_CFG_SDRAM_INIT_ARFC (0)
97+
#define BSP_CFG_SDRAM_INIT_PRC (0)
98+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (0)
9799
#define BSP_CFG_SDRAM_ENDIAN_MODE (0)
98-
#endif
99-
100-
#ifndef BSP_CFG_SDRAM_ACCESS_MODE
101-
#define BSP_CFG_SDRAM_ACCESS_MODE (1)
102-
#endif
103-
104-
#ifndef BSP_CFG_SDRAM_BUS_WIDTH
100+
#define BSP_CFG_SDRAM_ACCESS_MODE (0)
105101
#define BSP_CFG_SDRAM_BUS_WIDTH (0)
106-
#endif
102+
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) */
107103

108104
#ifdef __cplusplus
109105
}

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8d1/bsp_mcu_family_cfg.h

Lines changed: 53 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -361,63 +361,60 @@
361361
#define BSP_CFG_DCACHE_ENABLED (CONFIG_DCACHE)
362362
#endif
363363

364-
#ifndef BSP_CFG_SDRAM_ENABLED
364+
/* SDRAM controller configuration */
365+
#if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram))
366+
#define BSP_CFG_SDRAM_ENABLED (1)
367+
#define BSP_CFG_SDRAM_TRAS \
368+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
369+
renesas_ra_sdram_timing, 0)
370+
#define BSP_CFG_SDRAM_TRCD \
371+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
372+
renesas_ra_sdram_timing, 1)
373+
#define BSP_CFG_SDRAM_TRP \
374+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
375+
renesas_ra_sdram_timing, 2)
376+
#define BSP_CFG_SDRAM_TWR \
377+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
378+
renesas_ra_sdram_timing, 3)
379+
#define BSP_CFG_SDRAM_TCL \
380+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
381+
renesas_ra_sdram_timing, 4)
382+
#define BSP_CFG_SDRAM_TRFC \
383+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
384+
renesas_ra_sdram_timing, 5)
385+
#define BSP_CFG_SDRAM_TREFW \
386+
DT_PROP_BY_IDX(DT_CHILD(DT_INST(0, renesas_ra_sdram), bank_0), \
387+
renesas_ra_sdram_timing, 6)
388+
#define BSP_CFG_SDRAM_INIT_ARFI \
389+
DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_interval)
390+
#define BSP_CFG_SDRAM_INIT_ARFC \
391+
DT_PROP(DT_INST(0, renesas_ra_sdram), auto_refresh_count)
392+
#define BSP_CFG_SDRAM_INIT_PRC \
393+
DT_PROP(DT_INST(0, renesas_ra_sdram), precharge_cycle_count)
394+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT \
395+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), multiplex_addr_shift)
396+
#define BSP_CFG_SDRAM_ENDIAN_MODE \
397+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), edian_mode)
398+
#define BSP_CFG_SDRAM_ACCESS_MODE \
399+
DT_PROP(DT_INST(0, renesas_ra_sdram), continuous_access)
400+
#define BSP_CFG_SDRAM_BUS_WIDTH \
401+
DT_ENUM_IDX(DT_INST(0, renesas_ra_sdram), bus_width)
402+
#else
365403
#define BSP_CFG_SDRAM_ENABLED (0)
366-
#endif
367-
368-
#ifndef BSP_CFG_SDRAM_TRAS
369-
#define BSP_CFG_SDRAM_TRAS (6)
370-
#endif
371-
372-
#ifndef BSP_CFG_SDRAM_TRCD
373-
#define BSP_CFG_SDRAM_TRCD (3)
374-
#endif
375-
376-
#ifndef BSP_CFG_SDRAM_TRP
377-
#define BSP_CFG_SDRAM_TRP (3)
378-
#endif
379-
380-
#ifndef BSP_CFG_SDRAM_TWR
381-
#define BSP_CFG_SDRAM_TWR (2)
382-
#endif
383-
384-
#ifndef BSP_CFG_SDRAM_TCL
385-
#define BSP_CFG_SDRAM_TCL (3)
386-
#endif
387-
388-
#ifndef BSP_CFG_SDRAM_TRFC
389-
#define BSP_CFG_SDRAM_TRFC (937)
390-
#endif
391-
392-
#ifndef BSP_CFG_SDRAM_TREFW
393-
#define BSP_CFG_SDRAM_TREFW (8)
394-
#endif
395-
396-
#ifndef BSP_CFG_SDRAM_INIT_ARFI
397-
#define BSP_CFG_SDRAM_INIT_ARFI (10)
398-
#endif
399-
400-
#ifndef BSP_CFG_SDRAM_INIT_ARFC
401-
#define BSP_CFG_SDRAM_INIT_ARFC (8)
402-
#endif
403-
404-
#ifndef BSP_CFG_SDRAM_INIT_PRC
405-
#define BSP_CFG_SDRAM_INIT_PRC (3)
406-
#endif
407-
408-
#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT
409-
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (2)
410-
#endif
411-
412-
#ifndef BSP_CFG_SDRAM_ENDIAN_MODE
404+
#define BSP_CFG_SDRAM_TRAS (0)
405+
#define BSP_CFG_SDRAM_TRCD (0)
406+
#define BSP_CFG_SDRAM_TRP (0)
407+
#define BSP_CFG_SDRAM_TWR (0)
408+
#define BSP_CFG_SDRAM_TCL (0)
409+
#define BSP_CFG_SDRAM_TRFC (0)
410+
#define BSP_CFG_SDRAM_TREFW (0)
411+
#define BSP_CFG_SDRAM_INIT_ARFI (0)
412+
#define BSP_CFG_SDRAM_INIT_ARFC (0)
413+
#define BSP_CFG_SDRAM_INIT_PRC (0)
414+
#define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (0)
413415
#define BSP_CFG_SDRAM_ENDIAN_MODE (0)
414-
#endif
415-
416-
#ifndef BSP_CFG_SDRAM_ACCESS_MODE
417-
#define BSP_CFG_SDRAM_ACCESS_MODE (1)
418-
#endif
419-
420-
#ifndef BSP_CFG_SDRAM_BUS_WIDTH
416+
#define BSP_CFG_SDRAM_ACCESS_MODE (0)
421417
#define BSP_CFG_SDRAM_BUS_WIDTH (0)
422-
#endif
418+
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_INST(0, renesas_ra_sdram)) */
419+
423420
#endif /* BSP_MCU_FAMILY_CFG_H_ */

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