Skip to content

Commit f969ed4

Browse files
quytranpzzduynguyenxa
quytranpzz
authored and
duynguyenxa
committed
hal: renesas: Update pll multiple calculation
Update PLL multiple calculation value Signed-off-by: Quy Tran <[email protected]>
1 parent 11dbaac commit f969ed4

File tree

12 files changed

+107
-74
lines changed

12 files changed

+107
-74
lines changed

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/bsp_clock_cfg.h‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,11 +31,13 @@
3131
#define BSP_CFG_PLL_SOURCE \
3232
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
3333
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_1)
34+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
3435
#define BSP_CFG_PLL_MUL \
35-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
36-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37-
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
38-
: BSP_CLOCKS_PLL_MUL(0, 0)
36+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
38+
#else
39+
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
40+
#endif
3941

4042
#define BSP_CFG_CLOCK_SOURCE \
4143
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/bsp_clock_cfg.h‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -33,11 +33,13 @@
3333
#define BSP_CFG_PLL_SOURCE \
3434
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
3535
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_2)
36+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
3637
#define BSP_CFG_PLL_MUL \
37-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
38-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
39-
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
40-
: BSP_CLOCKS_PLL_MUL(0, 0)
38+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
39+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
40+
#else
41+
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
42+
#endif
4143

4244
#define BSP_CFG_CLOCK_SOURCE \
4345
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m2/bsp_clock_cfg.h‎

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -31,20 +31,24 @@
3131
#define BSP_CFG_PLL_SOURCE \
3232
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
3333
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_3)
34+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
3435
#define BSP_CFG_PLL_MUL \
35-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
36-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37-
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
38-
: BSP_CLOCKS_PLL_MUL(0, 0)
36+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
38+
#else
39+
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
40+
#endif
3941

4042
#define BSP_CFG_PLL2_SOURCE \
4143
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), source, RA_PLL_SOURCE_DISABLE)
4244
#define BSP_CFG_PLL2_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), div, RA_PLL_DIV_2)
43-
#define BSP_CFG_PLL2_MUL \
44-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll2), okay) \
45-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 0), \
46-
DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 1)) \
47-
: BSP_CLOCKS_PLL_MUL(0, 0)
45+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll2), okay)
46+
#define BSP_CFG_PLL2_MUL \
47+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 0), \
48+
DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 1))
49+
#else
50+
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(0, 0)
51+
#endif
4852

4953
#define BSP_CFG_CLOCK_SOURCE \
5054
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m3/bsp_clock_cfg.h‎

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -31,20 +31,24 @@
3131
#define BSP_CFG_PLL_SOURCE \
3232
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
3333
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_3)
34+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
3435
#define BSP_CFG_PLL_MUL \
35-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
36-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37-
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
38-
: BSP_CLOCKS_PLL_MUL(0, 0)
36+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
38+
#else
39+
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
40+
#endif
3941

4042
#define BSP_CFG_PLL2_SOURCE \
4143
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), source, RA_PLL_SOURCE_DISABLE)
4244
#define BSP_CFG_PLL2_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), div, RA_PLL_DIV_2)
43-
#define BSP_CFG_PLL2_MUL \
44-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll2), okay) \
45-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 0), \
46-
DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 1)) \
47-
: BSP_CLOCKS_PLL_MUL(0, 0)
45+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll2), okay)
46+
#define BSP_CFG_PLL2_MUL \
47+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 0), \
48+
DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 1))
49+
#else
50+
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(0, 0)
51+
#endif
4852

4953
#define BSP_CFG_CLOCK_SOURCE \
5054
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4w1/bsp_clock_cfg.h‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,11 +32,13 @@
3232
#define BSP_CFG_PLL_SOURCE \
3333
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
3434
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_2)
35+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
3536
#define BSP_CFG_PLL_MUL \
36-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
37-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
38-
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
39-
: BSP_CLOCKS_PLL_MUL(0, 0)
37+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
38+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
39+
#else
40+
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
41+
#endif
4042

4143
#define BSP_CFG_CLOCK_SOURCE \
4244
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e1/bsp_clock_cfg.h‎

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -30,20 +30,24 @@
3030
#define BSP_CFG_PLL_SOURCE \
3131
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
3232
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_1)
33+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
3334
#define BSP_CFG_PLL_MUL \
34-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
35-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
36-
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
37-
: BSP_CLOCKS_PLL_MUL(0, 0)
35+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
36+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
37+
#else
38+
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
39+
#endif
3840

3941
#define BSP_CFG_PLL2_SOURCE \
4042
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), source, RA_PLL_SOURCE_DISABLE)
4143
#define BSP_CFG_PLL2_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll2), div, RA_PLL_DIV_1)
42-
#define BSP_CFG_PLL2_MUL \
43-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll2), okay) \
44-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 0), \
45-
DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 1)) \
46-
: BSP_CLOCKS_PLL_MUL(0, 0)
44+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll2), okay)
45+
#define BSP_CFG_PLL2_MUL \
46+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 0), \
47+
DT_PROP_BY_IDX(DT_NODELABEL(pll2), mul, 1))
48+
#else
49+
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(0, 0)
50+
#endif
4751

4852
#define BSP_CFG_CLOCK_SOURCE \
4953
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e2/bsp_clock_cfg.h‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -31,12 +31,13 @@
3131
#define BSP_CFG_PLL_SOURCE \
3232
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
3333
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_1)
34+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
3435
#define BSP_CFG_PLL_MUL \
35-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
36-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37-
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
38-
: BSP_CLOCKS_PLL_MUL(0, 0)
39-
36+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
38+
#else
39+
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
40+
#endif
4041
#define BSP_CFG_CLOCK_SOURCE \
4142
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \
4243
RA_PLL_SOURCE_DISABLE)

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m1/bsp_clock_cfg.h‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,11 +31,13 @@
3131
#define BSP_CFG_PLL_SOURCE \
3232
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
3333
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_1)
34+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
3435
#define BSP_CFG_PLL_MUL \
35-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
36-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37-
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
38-
: BSP_CLOCKS_PLL_MUL(0, 0)
36+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
38+
#else
39+
#define BSP_CFG_PLL_MULv BSP_CLOCKS_PLL_MUL(0, 0)
40+
#endif
3941

4042
#define BSP_CFG_CLOCK_SOURCE \
4143
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m2/bsp_clock_cfg.h‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,11 +31,13 @@
3131
#define BSP_CFG_PLL_SOURCE \
3232
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
3333
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_1)
34+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
3435
#define BSP_CFG_PLL_MUL \
35-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
36-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37-
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
38-
: BSP_CLOCKS_PLL_MUL(0, 0)
36+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
38+
#else
39+
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
40+
#endif
3941

4042
#define BSP_CFG_CLOCK_SOURCE \
4143
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m3/bsp_clock_cfg.h‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,11 +31,13 @@
3131
#define BSP_CFG_PLL_SOURCE \
3232
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
3333
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_2)
34+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
3435
#define BSP_CFG_PLL_MUL \
35-
DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
36-
? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37-
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
38-
: BSP_CLOCKS_PLL_MUL(0, 0)
36+
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
37+
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
38+
#else
39+
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
40+
#endif
3941

4042
#define BSP_CFG_CLOCK_SOURCE \
4143
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \

0 commit comments

Comments
 (0)