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hal: renesas: Add BSP config RA4M1
Initial support bsp config for RA4M1 board Signed-off-by: TriNguyen <[email protected]> Signed-off-by: TriNguyen <[email protected]>
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‎drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h‎

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‎drivers/ra/fsp/src/bsp/mcu/ra4m1/bsp_elc.h‎

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‎drivers/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h‎

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‎drivers/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature_gen.h‎

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSP_FEATURE_GEN_H
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#define BSP_FEATURE_GEN_H
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/***********************************************************************************************************************
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* Includes <System Includes> , "Project Includes"
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Exported global variables (to be accessed by other files)
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Private global variables and functions
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**********************************************************************************************************************/
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// *UNCRUSTIFY-OFF*
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#define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0)
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#define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0)
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#define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0)
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#define BSP_FEATURE_GPT_GPTE_SUPPORTED (0)
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#define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0)
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#define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0)
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#define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0)
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#define BSP_FEATURE_GPT_OPS_SUPPORTED (0)
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// *UNCRUSTIFY-ON*
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#endif

‎drivers/ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h‎

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*******************************************************************************************************************//**
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* @ingroup BSP_MCU
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* @defgroup BSP_MCU_RA4M1 RA4M1
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* @includedoc config_bsp_ra4m1_fsp.html
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* @{
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**********************************************************************************************************************/
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/** @} (end defgroup BSP_MCU_RA4M1) */
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#ifndef BSP_MCU_INFO_H
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#define BSP_MCU_INFO_H
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/***********************************************************************************************************************
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* Includes <System Includes> , "Project Includes"
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**********************************************************************************************************************/
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/* BSP MCU Specific Includes. */
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#include "bsp_elc.h"
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#include "bsp_feature.h"
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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typedef elc_event_t bsp_interrupt_event_t;
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/***********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Exported global functions (to be accessed by other files)
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**********************************************************************************************************************/
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#endif

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/bsp_cfg.h‎

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSP_CFG_H_
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#define BSP_CFG_H_
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#include "soc.h"
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#define SUBCLOCK_STABILIZATION_MAX(x) ((x < 10000) ? x : 10000)
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/* Disable BSP_CFG_PARAM_CHECKING_ENABLE as default to reduce code size */
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#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
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/* Add for zephyr porting */
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#define BSP_CFG_INTERRUPT_INIT 0
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#define BSP_CFG_SP_MON_INIT 0
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (DT_NODE_HAS_STATUS(DT_NODELABEL(xtal), okay))
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (DT_PROP_OR(DT_NODELABEL(xtal), mosel, 0))
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#endif
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/* Keep 0 as default as LPM is not supported */
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (DT_PROP_OR(DT_NODELABEL(subclk), drive_capability, 0))
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (DT_NODE_HAS_STATUS(DT_NODELABEL(subclk), okay))
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS \
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SUBCLOCK_STABILIZATION_MAX((DT_PROP_OR(DT_NODELABEL(subclk), stabilization_time, 1000)))
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#endif
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#define BSP_CFG_PFS_PROTECT (1)
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#endif /* BSP_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/bsp_clock_cfg.h‎

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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#ifndef BSP_CLOCK_CFG_H_
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#define BSP_CLOCK_CFG_H_
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#define BSP_CFG_CLOCKS_SECURE (0)
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#define BSP_CFG_CLOCKS_OVERRIDE (0)
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#define BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \
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(COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)))
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#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
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#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 24000000
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#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 24MHz */
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#elif DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 32000000
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#define BSP_CFG_HOCO_FREQUENCY 2 /* HOCO 32MHz */
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#elif DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 48000000
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#define BSP_CFG_HOCO_FREQUENCY 4 /* HOCO 48MHz */
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#elif DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 64000000
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#define BSP_CFG_HOCO_FREQUENCY 5 /* HOCO 64MHz */
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#else
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#error "Invalid HOCO frequency, only can be set to 24MHz, 32MHz, 48MHz and 64MHz"
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#endif
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#define BSP_CFG_PLL_SOURCE \
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BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
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#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_2)
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#define BSP_CFG_PLL_MUL \
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DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) \
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? BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
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DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) \
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: BSP_CLOCKS_PLL_MUL(0, 0)
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#define BSP_CFG_CLOCK_SOURCE \
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BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \
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RA_PLL_SOURCE_DISABLE)
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#define BSP_CFG_ICLK_DIV \
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BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_1)
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#define BSP_CFG_PCLKA_DIV \
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BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclka), clk_div, RA_SYS_CLOCK_DIV_1)
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#define BSP_CFG_PCLKB_DIV \
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BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_2)
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#define BSP_CFG_PCLKC_DIV \
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BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkc), clk_div, RA_SYS_CLOCK_DIV_1)
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#define BSP_CFG_PCLKD_DIV \
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BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_1)
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#define BSP_CFG_FCLK_DIV \
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BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), clk_div, RA_SYS_CLOCK_DIV_2)
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#define BSP_CFG_UCK_SOURCE \
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BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
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#define BSP_CFG_UCK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_div, 0)
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#define BSP_CFG_CLKOUT_SOURCE \
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BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
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#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
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#endif /* BSP_CLOCK_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/bsp_mcu_device_cfg.h‎

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSP_MCU_DEVICE_CFG_H_
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#define BSP_MCU_DEVICE_CFG_H_
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#define BSP_CFG_MCU_PART_SERIES (4)
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#endif /* BSP_MCU_DEVICE_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/bsp_mcu_device_pn_cfg.h‎

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_PACKAGE_PINS (100)
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#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

‎zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/bsp_mcu_family_cfg.h‎

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/*
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* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BSP_MCU_FAMILY_CFG_H_
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#define BSP_MCU_FAMILY_CFG_H_
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#include "bsp_mcu_device_pn_cfg.h"
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#include "bsp_mcu_device_cfg.h"
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#include "bsp_mcu_info.h"
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#include "bsp_clock_cfg.h"
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#define BSP_MCU_GROUP_RA4M1 (1)
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#define BSP_LOCO_HZ (DT_PROP_OR(DT_NODELABEL(loco), clock_frequency, 0))
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#define BSP_MOCO_HZ (DT_PROP_OR(DT_NODELABEL(moco), clock_frequency, 0))
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#define BSP_SUB_CLOCK_HZ (DT_PROP_OR(DT_NODELABEL(subclk), clock_frequency, 0))
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#if BSP_CFG_HOCO_FREQUENCY == 0
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#define BSP_HOCO_HZ (24000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 2
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#define BSP_HOCO_HZ (32000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 4
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#define BSP_HOCO_HZ (48000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 5
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#define BSP_HOCO_HZ (64000000)
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#else
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#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
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#endif
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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
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#define BSP_CFG_INLINE_IRQ_FUNCTIONS (1)
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#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
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#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
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#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
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#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)
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#define OFS_SEQ5 (1 << 28) | (1 << 30)
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#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
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#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
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#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
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#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
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#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
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#endif
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/* Used to create IELS values for the interrupt initialization
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* table g_interrupt_event_link_select.
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*/
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#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
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/*
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* ID Code
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* Note: To permanently lock and disable the debug interface
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* define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
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* WARNING: This will disable debug access to the part and cannot
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* be reversed by a debug probe.
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*/
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#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
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#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
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#else
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/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
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#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
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#endif
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#endif /* BSP_MCU_FAMILY_CFG_H_ */

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