diff --git a/drivers/rx/rdp/src/r_bsp/board/generic_rx26t/r_bsp.h b/drivers/rx/rdp/src/r_bsp/board/generic_rx26t/r_bsp.h new file mode 100644 index 00000000..7a9e8dd7 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/board/generic_rx26t/r_bsp.h @@ -0,0 +1,64 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : r_bsp.h +* H/W Platform : GENERIC_RX26T +* Description : Has the header files that should be included for this platform. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 26.02.2025 1.01 Changed the disclaimer. +***********************************************************************************************************************/ + +/* Make sure that no other platforms have already been defined. Do not touch this! */ +#ifdef PLATFORM_DEFINED +#error "Error - Multiple platforms defined in platform.h!" +#else +#define PLATFORM_DEFINED +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** +INCLUDE APPROPRIATE MCU AND BOARD FILES +***********************************************************************************************************************/ +#include "r_bsp_config.h" +#include "r_bsp_common.h" +#include "r_rx_compiler.h" + +#if defined(__CCRX__) +#include "mcu/rx26t/register_access/ccrx/iodefine.h" +#elif defined(__GNUC__) +#include "mcu/rx26t/register_access/gnuc/iodefine.h" +#elif defined(__ICCRX__) +#include "mcu/rx26t/register_access/iccrx/iodefine.h" +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ +#include "r_bsp_cpu.h" +#include "mcu_clocks.h" +#include "mcu_info.h" +#include "mcu_init.h" +#include "mcu_interrupts.h" +#include "mcu_locks.h" +#include "mcu/rx26t/mcu_mapped_interrupts_private.h" +#include "mcu/rx26t/mcu_mapped_interrupts.h" +#include "vecttbl.h" + +#include "r_bsp_interrupts.h" +#include "r_bsp_software_interrupt.h" +#include "r_rx_intrinsic_functions.h" + +#ifdef __cplusplus +} +#endif + +#ifndef BSP_BOARD_GENERIC_RX26T +#define BSP_BOARD_GENERIC_RX26T + +#endif /* BSP_BOARD_GENERIC_RX26T */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_clocks.c b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_clocks.c new file mode 100644 index 00000000..659a761d --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_clocks.c @@ -0,0 +1,708 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_clocks.c +* Description : Contains clock specific routines +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 21.11.2023 1.01 Added compile switch of BSP_CFG_BOOTLOADER_PROJECT. +* Added the bsp_mcu_clock_reset_bootloader function. +* Changed MOFCR setting timing. +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_CKSEL_LOCO (0x0) +#define BSP_PRV_CKSEL_HOCO (0x1) +#define BSP_PRV_CKSEL_MAIN_OSC (0x2) +#define BSP_PRV_CKSEL_PLL (0x4) + +#define BSP_PRV_NORMALIZE_X10 (10) /* used to avoid floating point arithmetic */ + +/* This macro runs or stops the PLL circuit. + If the following conditions are satisfied, PLL circuit will operate. + 1. System clock source is PLL circuit. + */ +#if (BSP_CFG_CLOCK_SOURCE == 4) + #define BSP_PRV_PLL_CLK_OPERATING (1) /* PLL circuit is operating. */ +#else /* PLL is not used as clock source. */ + #define BSP_PRV_PLL_CLK_OPERATING (0) /* PLL circuit is stopped. */ +#endif + +#if BSP_CFG_BOOTLOADER_PROJECT == 1 +/* Enable the following macro definitions in the bootloader project. */ +#define BSP_PRV_SCKCR_RESET_VALUE (0x00000000) +#define BSP_PRV_SCKCR2_RESET_VALUE (0x1011) +#define BSP_PRV_SCKCR3_RESET_VALUE (0x0000) +#define BSP_PRV_PLLCR_RESET_VALUE (0x1d00) +#define BSP_PRV_PLLCR2_RESET_VALUE (0x01) +#define BSP_PRV_MOSCCR_RESET_VALUE (0x01) +#define BSP_PRV_MOSCWTCR_RESET_VALUE (0x53) +#define BSP_PRV_MOFCR_RESET_VALUE (0x00) +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 1 */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +static void operating_frequency_set(void); +static void clock_source_select(void); +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +/*********************************************************************************************************************** +* Function Name: get_iclk_freq_hz +* Description : Return the current ICLK frequency in Hz. Called by R_BSP_GetIClkFreqHz(). +* The system clock source can be changed at any time via SYSTEM.SCKCR3.BIT.CKSEL, so in order to +* determine the ICLK frequency we need to first find the current system clock source and then, +* in some cases where the clock source can be configured for multiple frequencies, calculate the +* frequency at which it is currently running. +* Arguments : None +* Return Value : uint32_t - the iclk frequency in Hz +***********************************************************************************************************************/ +uint32_t get_iclk_freq_hz(void) +{ + uint32_t sys_clock_src_freq; + uint32_t pll_multiplier; + uint32_t pll_source_freq; + uint32_t hoco_frequency[3] = {16000000, 18000000, 20000000}; + + /* Casting is valid because it matches the type to the retern value. */ + uint8_t cksel = (uint8_t)SYSTEM.SCKCR3.BIT.CKSEL; + + switch (cksel) + { + case BSP_PRV_CKSEL_LOCO: + sys_clock_src_freq = BSP_LOCO_HZ; + break; + + case BSP_PRV_CKSEL_HOCO: + + /* Set HOCO frequency. */ + sys_clock_src_freq = hoco_frequency[SYSTEM.HOCOCR2.BIT.HCFRQ]; + break; + + case BSP_PRV_CKSEL_MAIN_OSC: + sys_clock_src_freq = BSP_CFG_XTAL_HZ; + break; + + case BSP_PRV_CKSEL_PLL: + + /* The RX26T have two possible sources for the PLL */ + + /* Casting is valid because it matches the type to the retern value. */ + pll_multiplier = ((((uint32_t)(SYSTEM.PLLCR.BIT.STC + 1)) * BSP_PRV_NORMALIZE_X10) / 2); + + /* Default to the MAIN OSC as the PLL source */ + pll_source_freq = BSP_CFG_XTAL_HZ; + + /* If 1 then the HOCO is the PLL source */ + if (0x1 == SYSTEM.PLLCR.BIT.PLLSRCSEL) + { + /* Set HOCO frequency. */ + pll_source_freq = hoco_frequency[SYSTEM.HOCOCR2.BIT.HCFRQ]; + } + + /* Casting is valid because it matches the type to the retern value. */ + sys_clock_src_freq = ((pll_source_freq / (((uint32_t)(SYSTEM.PLLCR.BIT.PLIDIV + 1)) * BSP_PRV_NORMALIZE_X10)) * pll_multiplier); + break; + + default: + + /* Should never arrive here. Use the Main OSC freq as a default... */ + sys_clock_src_freq = BSP_CFG_XTAL_HZ; + break; + } + + /* Finally, divide the system clock source frequency by the currently set ICLK divider to get the ICLK frequency */ + return (sys_clock_src_freq / (uint32_t)(1 << SYSTEM.SCKCR.BIT.ICK)); +} /* End of function get_iclk_freq_hz() */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +* Function name: mcu_clock_setup +* Description : Contains clock functions called at device restart. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +void mcu_clock_setup(void) +{ + /* Switch to high-speed operation */ + operating_frequency_set(); +} /* End of function mcu_clock_setup() */ + +/*********************************************************************************************************************** +* Function name: operating_frequency_set +* Description : Configures the clock settings for each of the device clocks +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void operating_frequency_set (void) +{ + /* Used for constructing value to write to SCKCR, SCKCR2, and SCKCR3 registers. */ + uint32_t tmp_clock = 0; + uint32_t tmp2_clock = 0; + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50B; + + /* Select the clock based upon user's choice. */ + clock_source_select(); + + /* Figure out setting for FCK bits. */ +#if BSP_CFG_FCK_DIV == 1 + /* Do nothing since FCK bits should be 0. */ +#elif BSP_CFG_FCK_DIV == 2 + tmp_clock |= 0x10000000; +#elif BSP_CFG_FCK_DIV == 4 + tmp_clock |= 0x20000000; +#elif BSP_CFG_FCK_DIV == 8 + tmp_clock |= 0x30000000; +#elif BSP_CFG_FCK_DIV == 16 + tmp_clock |= 0x40000000; +#elif BSP_CFG_FCK_DIV == 32 + tmp_clock |= 0x50000000; +#elif BSP_CFG_FCK_DIV == 64 + tmp_clock |= 0x60000000; +#else + #error "Error! Invalid setting for BSP_CFG_FCK_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for ICK bits. */ +#if BSP_CFG_ICK_DIV == 1 + /* Do nothing since ICK bits should be 0. */ +#elif BSP_CFG_ICK_DIV == 2 + tmp_clock |= 0x01000000; +#elif BSP_CFG_ICK_DIV == 4 + tmp_clock |= 0x02000000; +#elif BSP_CFG_ICK_DIV == 8 + tmp_clock |= 0x03000000; +#elif BSP_CFG_ICK_DIV == 16 + tmp_clock |= 0x04000000; +#elif BSP_CFG_ICK_DIV == 32 + tmp_clock |= 0x05000000; +#elif BSP_CFG_ICK_DIV == 64 + tmp_clock |= 0x06000000; +#else + #error "Error! Invalid setting for BSP_CFG_ICK_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKA bits. */ +#if BSP_CFG_PCKA_DIV == 1 + /* Do nothing since PCKA bits should be 0. */ +#elif BSP_CFG_PCKA_DIV == 2 + tmp_clock |= 0x00001000; +#elif BSP_CFG_PCKA_DIV == 4 + tmp_clock |= 0x00002000; +#elif BSP_CFG_PCKA_DIV == 8 + tmp_clock |= 0x00003000; +#elif BSP_CFG_PCKA_DIV == 16 + tmp_clock |= 0x00004000; +#elif BSP_CFG_PCKA_DIV == 32 + tmp_clock |= 0x00005000; +#elif BSP_CFG_PCKA_DIV == 64 + tmp_clock |= 0x00006000; +#else + #error "Error! Invalid setting for BSP_CFG_PCKA_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKB bits. */ +#if BSP_CFG_PCKB_DIV == 1 + /* Do nothing since PCKB bits should be 0. */ +#elif BSP_CFG_PCKB_DIV == 2 + tmp_clock |= 0x00000100; +#elif BSP_CFG_PCKB_DIV == 4 + tmp_clock |= 0x00000200; +#elif BSP_CFG_PCKB_DIV == 8 + tmp_clock |= 0x00000300; +#elif BSP_CFG_PCKB_DIV == 16 + tmp_clock |= 0x00000400; +#elif BSP_CFG_PCKB_DIV == 32 + tmp_clock |= 0x00000500; +#elif BSP_CFG_PCKB_DIV == 64 + tmp_clock |= 0x00000600; +#else + #error "Error! Invalid setting for BSP_CFG_PCKB_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKC bits. */ +#if BSP_CFG_PCKC_DIV == 1 + /* Do nothing since PCKA bits should be 0. */ +#elif BSP_CFG_PCKC_DIV == 2 + tmp_clock |= 0x00000010; +#elif BSP_CFG_PCKC_DIV == 4 + tmp_clock |= 0x00000020; +#elif BSP_CFG_PCKC_DIV == 8 + tmp_clock |= 0x00000030; +#elif BSP_CFG_PCKC_DIV == 16 + tmp_clock |= 0x00000040; +#elif BSP_CFG_PCKC_DIV == 32 + tmp_clock |= 0x00000050; +#elif BSP_CFG_PCKC_DIV == 64 + tmp_clock |= 0x00000060; +#else + #error "Error! Invalid setting for BSP_CFG_PCKC_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKD bits. */ +#if BSP_CFG_PCKD_DIV == 1 + /* Do nothing since PCKD bits should be 0. */ +#elif BSP_CFG_PCKD_DIV == 2 + tmp_clock |= 0x00000001; +#elif BSP_CFG_PCKD_DIV == 4 + tmp_clock |= 0x00000002; +#elif BSP_CFG_PCKD_DIV == 8 + tmp_clock |= 0x00000003; +#elif BSP_CFG_PCKD_DIV == 16 + tmp_clock |= 0x00000004; +#elif BSP_CFG_PCKD_DIV == 32 + tmp_clock |= 0x00000005; +#elif BSP_CFG_PCKD_DIV == 64 + tmp_clock |= 0x00000006; +#else + #error "Error! Invalid setting for BSP_CFG_PCKD_DIV in r_bsp_config.h" +#endif + + /* b19 to b16 should be set the same value as the ICK bit. */ + tmp2_clock = tmp_clock; + tmp2_clock &= 0x0F000000; + tmp2_clock >>= 8; + tmp_clock |= tmp2_clock; + + /* b23 to b20 should be 0x0. */ + + /* Set SCKCR register. */ + SYSTEM.SCKCR.LONG = tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(tmp_clock == SYSTEM.SCKCR.LONG) + { + R_BSP_NOP(); + } + + /* Re-init tmp_clock to use to set SCKCR2. */ + tmp_clock = 0; + + /* Figure out setting for CFDCK bits. */ +#if BSP_CFG_CFDCK_DIV == 2 + tmp_clock |= 0x00001000; +#elif BSP_CFG_CFDCK_DIV == 4 + tmp_clock |= 0x00002000; +#elif BSP_CFG_CFDCK_DIV == 8 + tmp_clock |= 0x00003000; +#else + #error "Error! Invalid setting for BSP_CFG_CFDCK_DIV in r_bsp_config.h" +#endif + + /* Set SCKCR2 register. */ + SYSTEM.SCKCR2.WORD = (uint16_t)tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if((uint16_t)tmp_clock == SYSTEM.SCKCR2.WORD) + { + R_BSP_NOP(); + } + + /* Choose clock source. Default for r_bsp_config.h is PLL. */ + tmp_clock = ((uint16_t)BSP_CFG_CLOCK_SOURCE) << 8; + + /* Casting is valid because it matches the type to the retern value. */ + SYSTEM.SCKCR3.WORD = (uint16_t)tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if((uint16_t)tmp_clock == SYSTEM.SCKCR3.WORD) + { + R_BSP_NOP(); + } + +#if BSP_CFG_BOOTLOADER_PROJECT == 0 +/* Disable the following functions in the bootloader project. */ +#if BSP_CFG_IWDT_CLOCK_OSCILLATE_ENABLE == 1 + /* IWDT clock is stopped after reset. Oscillate the IWDT. */ + SYSTEM.ILOCOCR.BIT.ILCSTP = 0; + + /* WAIT_LOOP */ + while (1 != SYSTEM.OSCOVFSR.BIT.ILCOVF) + { + /* If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } +#endif + +#if BSP_CFG_LOCO_OSCILLATE_ENABLE == 0 + /* We can now turn LOCO off since it is not going to be used. */ + SYSTEM.LOCOCR.BYTE = 0x01; + + /* Wait for five the LOCO cycles */ + /* 5 count of LOCO : (1000000/216000)*5 = 23.148148148us + 23 + 2 = 25us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)25, BSP_DELAY_MICROSECS); +#endif +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function operating_frequency_set() */ + +/*********************************************************************************************************************** +* Function name: clock_source_select +* Description : Enables and disables clocks as chosen by the user. This function also implements the delays +* needed for the clocks to stabilize. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void clock_source_select (void) +{ +#if BSP_CFG_HOCO_OSCILLATE_ENABLE == 1 + /* HOCO is chosen. Start it operating if it is not already operating. */ + if (1 == SYSTEM.HOCOCR.BIT.HCSTP) + { + /* Turn on power to HOCO. */ + SYSTEM.HOCOPCR.BYTE = 0x00; + + /* Stop HOCO. */ + SYSTEM.HOCOCR.BYTE = 0x01; + + /* WAIT_LOOP */ + while(1 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stopped. */ + R_BSP_NOP(); + } + + /* Set HOCO frequency. */ + #if (BSP_CFG_HOCO_FREQUENCY == 0) + SYSTEM.HOCOCR2.BYTE = 0x00; //16MHz + #elif (BSP_CFG_HOCO_FREQUENCY == 1) + SYSTEM.HOCOCR2.BYTE = 0x01; //18MHz + #elif (BSP_CFG_HOCO_FREQUENCY == 2) + SYSTEM.HOCOCR2.BYTE = 0x02; //20MHz + #else + #error "Error! Invalid setting for BSP_CFG_HOCO_FREQUENCY in r_bsp_config.h" + #endif + + /* HOCO is chosen. Start it operating. */ + SYSTEM.HOCOCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x00 == SYSTEM.HOCOCR.BYTE) + { + R_BSP_NOP(); + } + } + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } +#else /* (BSP_CFG_HOCO_OSCILLATE_ENABLE == 0) */ + #if BSP_CFG_BOOTLOADER_PROJECT == 0 + /* Disable the following functions in the bootloader project. */ + /* If HOCO is already operating, it doesn't stop. */ + if (1 == SYSTEM.HOCOCR.BIT.HCSTP) + { + /* Turn off power to HOCO. */ + SYSTEM.HOCOPCR.BYTE = 0x01; + } + else + { + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } + } + #endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ +#endif /* BSP_CFG_HOCO_OSCILLATE_ENABLE == 1 */ + +#if BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 1 + /* Main clock oscillator is chosen. Start it operating. */ + + /* Set the oscillation source of the main clock oscillator. */ + SYSTEM.MOFCR.BIT.MOSEL = BSP_CFG_MAIN_CLOCK_SOURCE; + + /* If the main oscillator is >10MHz then the main clock oscillator forced oscillation control register (MOFCR) must + be changed. */ + if (BSP_CFG_XTAL_HZ > 20000000) + { + /* 20 - 24MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 0; + } + else if (BSP_CFG_XTAL_HZ > 16000000) + { + /* 16 - 20MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 1; + } + else if (BSP_CFG_XTAL_HZ > 8000000) + { + /* 8 - 16MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 2; + } + else + { + /* 8MHz. */ + SYSTEM.MOFCR.BIT.MODRV2 = 3; + } + + /* Set the oscillation stabilization wait time of the main clock oscillator. */ +#if BSP_CFG_MAIN_CLOCK_SOURCE == 0 /* Resonator */ + SYSTEM.MOSCWTCR.BYTE = BSP_CFG_MOSC_WAIT_TIME; +#elif BSP_CFG_MAIN_CLOCK_SOURCE == 1 /* External oscillator input */ + SYSTEM.MOSCWTCR.BYTE = 0x00; +#else + #error "Error! Invalid setting for BSP_CFG_MAIN_CLOCK_SOURCE in r_bsp_config.h" +#endif + + /* Set the main clock to operating. */ + SYSTEM.MOSCCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x00 == SYSTEM.MOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.MOOVF) + { + /* The delay period needed is to make sure that the Main clock has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } +#else /* (BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 0) */ + /* Main clock is stopped after reset. */ +#endif /* BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 1 */ + +#if BSP_PRV_PLL_CLK_OPERATING == 1 + + /* Set PLL Input Divisor. */ + SYSTEM.PLLCR.BIT.PLIDIV = BSP_CFG_PLL_DIV - 1; + + #if BSP_CFG_PLL_SRC == 0 + /* Clear PLL clock source if PLL clock source is Main clock. */ + SYSTEM.PLLCR.BIT.PLLSRCSEL = 0; + #else + /* Set PLL clock source if PLL clock source is HOCO clock. */ + SYSTEM.PLLCR.BIT.PLLSRCSEL = 1; + #endif + + /* Set PLL Multiplier. */ + SYSTEM.PLLCR.BIT.STC = ((uint8_t)((float)BSP_CFG_PLL_MUL * 2.0f)) - 1; + + /* Set the PLL to operating. */ + SYSTEM.PLLCR2.BYTE = 0x00; + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.PLOVF) + { + /* The delay period needed is to make sure that the PLL has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } +#else + /* PLL is stopped after reset. */ +#endif + + /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn + it off until another clock has been enabled and is ready to use. */ +#if BSP_CFG_LOCO_OSCILLATE_ENABLE == 1 + /* LOCO is chosen. This is the default out of reset. */ +#else + /* LOCO is not chosen but it cannot be turned off yet since it is still being used. */ +#endif + +} /* End of function clock_source_select() */ + +#if BSP_CFG_BOOTLOADER_PROJECT == 1 +/*********************************************************************************************************************** +* Function name: bsp_mcu_clock_reset_bootloader +* Description : Returns the MCU clock settings to the reset state. The system clock returns to LOCO. PLL circuit will +* stop. Main clock will stop. +* Arguments : none +* Return value : none +* Note : Enable this functions in the bootloader project. This function for bootloader only. +***********************************************************************************************************************/ +void bsp_mcu_clock_reset_bootloader (void) +{ + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA503; + + /* Is not Clock source LOCO? */ + if(BSP_PRV_SCKCR3_RESET_VALUE != SYSTEM.SCKCR3.WORD) + { + /* Reset clock source. Change to LOCO. */ + SYSTEM.SCKCR3.WORD = BSP_PRV_SCKCR3_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_SCKCR3_RESET_VALUE == SYSTEM.SCKCR3.WORD) + { + R_BSP_NOP(); + } + } + + /* Is not SCKCR2 reset value? */ + if(BSP_PRV_SCKCR2_RESET_VALUE != SYSTEM.SCKCR2.WORD) + { + /* Reset SCKCR2 register. */ + SYSTEM.SCKCR2.WORD = BSP_PRV_SCKCR2_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_SCKCR2_RESET_VALUE == SYSTEM.SCKCR2.WORD) + { + R_BSP_NOP(); + } + } + + /* Is not SCKCR reset value? */ + if(BSP_PRV_SCKCR_RESET_VALUE != SYSTEM.SCKCR.LONG) + { + /* Reset SCKCR register. */ + SYSTEM.SCKCR.LONG = BSP_PRV_SCKCR_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_SCKCR_RESET_VALUE == SYSTEM.SCKCR.LONG) + { + R_BSP_NOP(); + } + } + +#if BSP_PRV_PLL_CLK_OPERATING == 1 + /* PLL operating? */ + if(BSP_PRV_PLLCR2_RESET_VALUE != SYSTEM.PLLCR2.BYTE) + { + /* Stop PLL. */ + SYSTEM.PLLCR2.BYTE = BSP_PRV_PLLCR2_RESET_VALUE; + + /* WAIT_LOOP */ + while(1 == SYSTEM.OSCOVFSR.BIT.PLOVF) + { + /* The delay period needed is to make sure that the PLL has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } + } + + /* Is not PLLCR reset value? */ + if(BSP_PRV_PLLCR_RESET_VALUE != SYSTEM.PLLCR.WORD) + { + /* Reset PLL. */ + SYSTEM.PLLCR.WORD = BSP_PRV_PLLCR_RESET_VALUE; + } +#endif /* BSP_PRV_PLL_CLK_OPERATING == 1 */ + +#if BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 1 + /* main clock operating? */ + if(BSP_PRV_MOSCCR_RESET_VALUE != SYSTEM.MOSCCR.BYTE) + { + /* Stop the main clock. */ + SYSTEM.MOSCCR.BYTE = BSP_PRV_MOSCCR_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_MOSCCR_RESET_VALUE == SYSTEM.MOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while(1 == SYSTEM.OSCOVFSR.BIT.MOOVF) + { + /* The delay period needed is to make sure that the Main clock has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } + } + + /* Is not MOSCWTCR reset value? */ + if(BSP_PRV_MOSCWTCR_RESET_VALUE != SYSTEM.MOSCWTCR.BYTE) + { + /* Reset MOSCWTCR */ + SYSTEM.MOSCWTCR.BYTE = BSP_PRV_MOSCWTCR_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_MOSCWTCR_RESET_VALUE == SYSTEM.MOSCWTCR.BYTE) + { + R_BSP_NOP(); + } + } + + /* Is not MOFCR reset value? */ + if(BSP_PRV_MOFCR_RESET_VALUE != SYSTEM.MOFCR.BYTE) + { + /* Reset MOFCR */ + SYSTEM.MOFCR.BYTE = BSP_PRV_MOFCR_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_MOFCR_RESET_VALUE == SYSTEM.MOFCR.BYTE) + { + R_BSP_NOP(); + } + } +#endif /* BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 1 */ + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function bsp_mcu_clock_reset_bootloader() */ +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 1 */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_clocks.h b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_clocks.h new file mode 100644 index 00000000..1bdda977 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_clocks.h @@ -0,0 +1,45 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_clocks.h +* Description : Contains clock specific routines. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 21.11.2023 1.01 Added definition of bsp_mcu_clock_reset_bootloader function. +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_CLOCKS_H +#define MCU_CLOCKS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +uint32_t get_iclk_freq_hz(void); +void mcu_clock_setup(void); + +#if BSP_CFG_BOOTLOADER_PROJECT == 1 +/* Enable the following functions in the bootloader project. */ +void bsp_mcu_clock_reset_bootloader(void); +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 1 */ + +/* End of multiple inclusion prevention macro */ +#endif + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_info.h b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_info.h new file mode 100644 index 00000000..ed3c8fd6 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_info.h @@ -0,0 +1,208 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_info.h +* Device(s) : RX26T +* Description : Information about the MCU. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 21.11.2023 1.01 Deleted the macro definition of BSP_BCLK_HZ and BSP_UCLK_HZ. +* Added the macro definition of BSP_CFDCLK_HZ. +* Modified comment. +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Gets MCU configuration information. */ +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INFO +#define MCU_INFO + +#if BSP_CFG_CONFIGURATOR_VERSION < 2120 + /* The following macros are updated to invalid value by Smart configurator if you are using Smart Configurator for + RX V2.11.0 (equivalent to e2 studio 2021-10) or earlier version. + - BSP_CFG_MCU_PART_GROUP, BSP_CFG_MCU_PART_SERIES + The following macros are not updated by Smart configurator if you are using Smart Configurator for RX V2.11.0 + (equivalent to e2 studio 2021-10) or earlier version. + - BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE, BSP_CFG_HOCO_OSCILLATE_ENABLE, BSP_CFG_LOCO_OSCILLATE_ENABLE, + BSP_CFG_IWDT_CLOCK_OSCILLATE_ENABLE, BSP_CFG_CPLUSPLUS + Please update Smart configurator to Smart Configurator for RX V2.14.0 (equivalent to e2 studio 2022-07) or + later version. + */ + #error "To use this version of BSP, you need to upgrade Smart configurator. Please upgrade Smart configurator. If you don't use Smart Configurator, please change value of BSP_CFG_CONFIGURATOR_VERSION in r_bsp_config.h." +#endif + +/* MCU CPU Version */ +#define BSP_MCU_CPU_VERSION (3) + +/* CPU cycles. Known number of RXv3 CPU cycles required to execute the delay_wait() loop */ +#define CPU_CYCLES_PER_LOOP (3) + +/* MCU Series. */ +#define BSP_MCU_SERIES_RX200 (1) + +/* This macro means that this MCU is part of the RX26x collection of MCUs (i.e. RX26T). */ +#define BSP_MCU_RX26_ALL (1) + +/* MCU Group name. */ +#define BSP_MCU_RX26T (1) + +/* Package. */ +#if BSP_CFG_MCU_PART_PACKAGE == 0x0 + #define BSP_PACKAGE_LFQFP100 (1) + #define BSP_PACKAGE_PINS (100) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x1 + #define BSP_PACKAGE_LFQFP80 (1) + #define BSP_PACKAGE_PINS (80) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x8 + #define BSP_PACKAGE_LFQFP64 (1) + #define BSP_PACKAGE_PINS (64) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x6 + #define BSP_PACKAGE_LFQFP48 (1) + #define BSP_PACKAGE_PINS (48) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x5 + #define BSP_PACKAGE_HWQFN64 (1) + #define BSP_PACKAGE_PINS (64) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x7 + #define BSP_PACKAGE_HWQFN48 (1) + #define BSP_PACKAGE_PINS (48) +#else + #error "ERROR - BSP_CFG_MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h" +#endif + +/* Memory size of your MCU. */ +#if BSP_CFG_MCU_PART_MEMORY_SIZE == 0xF + #define BSP_ROM_SIZE_BYTES (524288) + #define BSP_RAM_SIZE_BYTES (65536) + #define BSP_DATA_FLASH_SIZE_BYTES (16384) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0xB + #define BSP_ROM_SIZE_BYTES (262144) + #define BSP_RAM_SIZE_BYTES (65536) + #define BSP_DATA_FLASH_SIZE_BYTES (16384) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0xA + #define BSP_ROM_SIZE_BYTES (262144) + #define BSP_RAM_SIZE_BYTES (49152) + #define BSP_DATA_FLASH_SIZE_BYTES (16384) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x9 + #define BSP_ROM_SIZE_BYTES (131072) + #define BSP_RAM_SIZE_BYTES (65536) + #define BSP_DATA_FLASH_SIZE_BYTES (16384) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x8 + #define BSP_ROM_SIZE_BYTES (131072) + #define BSP_RAM_SIZE_BYTES (49152) + #define BSP_DATA_FLASH_SIZE_BYTES (16384) +#else + #error "ERROR - BSP_CFG_MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h" +#endif + +/* These macros define clock speeds for fixed speed clocks. */ +#define BSP_LOCO_HZ (240000) + +/* Define frequency of HOCO. */ +#if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) +#else + #error "ERROR - Invalid HOCO frequency chosen in r_bsp_config.h! Set valid value for BSP_CFG_HOCO_FREQUENCY." +#endif + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 4 = PLL Circuit +*/ +#if BSP_CFG_CLOCK_SOURCE == 0 + #define BSP_SELECTED_CLOCK_HZ (BSP_LOCO_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 1 + #define BSP_SELECTED_CLOCK_HZ (BSP_HOCO_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 2 + #define BSP_SELECTED_CLOCK_HZ (BSP_CFG_XTAL_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 4 + #if BSP_CFG_PLL_SRC == 0 + #define BSP_SELECTED_CLOCK_HZ ((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) + #elif BSP_CFG_PLL_SRC == 1 + #define BSP_SELECTED_CLOCK_HZ ((BSP_HOCO_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) + #else + #error "ERROR - Valid PLL clock source must be chosen in r_bsp_config.h using BSP_CFG_PLL_SRC macro." + #endif +#else + #error "ERROR - BSP_CFG_CLOCK_SOURCE - Unknown clock source chosen in r_bsp_config.h" +#endif + +/* System clock speed in Hz. */ +#define BSP_ICLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_ICK_DIV) +/* Peripheral Module Clock A speed in Hz. */ +#define BSP_PCLKA_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKA_DIV) +/* Peripheral Module Clock B speed in Hz. */ +#define BSP_PCLKB_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKB_DIV) +/* Peripheral Module Clock C speed in Hz. */ +#define BSP_PCLKC_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKC_DIV) +/* Peripheral Module Clock D speed in Hz. */ +#define BSP_PCLKD_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKD_DIV) +/* FlashIF clock speed in Hz. */ +#define BSP_FCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_FCK_DIV) +/* CANFD clock speed in Hz. */ +#define BSP_CFDCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_CFDCK_DIV) + +/* Null argument definitions. */ +#define FIT_NO_FUNC ((void (*)(void *))0x10000000) /* Reserved space on RX */ +#define FIT_NO_PTR ((void *)0x10000000) /* Reserved space on RX */ + +/* Mininum and maximum IPL levels available for this MCU. */ +#define BSP_MCU_IPL_MAX (0xF) +#define BSP_MCU_IPL_MIN (0) + +/* MCU TFU Version */ +#define BSP_MCU_TFU_VERSION (2) + +/* MCU functions */ +#define BSP_MCU_REGISTER_WRITE_PROTECTION +#define BSP_MCU_RCPC_PRC0 +#define BSP_MCU_RCPC_PRC1 +#define BSP_MCU_RCPC_PRC3 +#define BSP_MCU_FLOATING_POINT +#define BSP_MCU_EXCEPTION_TABLE +#define BSP_MCU_GROUP_INTERRUPT +#define BSP_MCU_GROUP_INTERRUPT_BL0 +#define BSP_MCU_GROUP_INTERRUPT_BL1 +#define BSP_MCU_GROUP_INTERRUPT_BL2 +#define BSP_MCU_GROUP_INTERRUPT_AL0 +#define BSP_MCU_GROUP_INTERRUPT_AL1 +#define BSP_MCU_SOFTWARE_CONFIGURABLE_INTERRUPT +#define BSP_MCU_VOLTAGE_LEVEL_SETTING +#define BSP_MCU_VOLTAGE_LEVEL_SETTING_RIIC +#define BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +#define BSP_MCU_EXCEP_ACCESS_ISR +#define BSP_MCU_EXCEP_UNDEFINED_INST_ISR +#define BSP_MCU_EXCEP_FLOATING_POINT_ISR +#define BSP_MCU_NON_MASKABLE_ISR +#define BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +#define BSP_MCU_BUS_ERROR_ISR +#define BSP_MCU_TRIGONOMETRIC + +#define BSP_MCU_NMI_EXC_NMI_PIN +#define BSP_MCU_NMI_OSC_STOP_DETECT +#define BSP_MCU_NMI_WDT_ERROR +#define BSP_MCU_NMI_IWDT_ERROR +#define BSP_MCU_NMI_LVD1 +#define BSP_MCU_NMI_LVD2 +#define BSP_MCU_NMI_RAM + +#endif /* MCU_INFO */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_init.c b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_init.c new file mode 100644 index 00000000..06b9b568 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_init.c @@ -0,0 +1,198 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_init.c +* Description : Performs initialization common to all MCUs in this Group +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 21.11.2023 1.01 Modified comment. +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Get specifics on this MCU. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* RX MCUs come in different packages and different pin counts. + * Each bit of PORTm.PDR corresponds to each pin of port m; I/O direction can be specified in 1-bit units. + * Each bit of PDR corresponding to port m that does not exist is reserved. + * Also, each bit of PDR corresponding to PE2 pins is reserved, because such pins are input only. + * Make settings of the reserved bit according to the description in section 20.5.1, Initialization of the Port + * Direction Register (PDR). These values are then ORed into the direction registers to set non-existent pins as + * outputs or inputs, which can help save power. + */ +#if BSP_PACKAGE_PINS == 100 + /* Refer User's Manual: Hardware Table 20.4. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT9_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTN_NE_PIN_MASK (0x00) +#elif BSP_PACKAGE_PINS == 80 + /* Refer User's Manual: Hardware Table 20.5. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x18) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x0C) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x0E) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x07) + #define BSP_PRV_PORT9_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x17) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x80) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x03) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x23) + #define BSP_PRV_PORTN_NE_PIN_MASK (0x00) +#elif BSP_PACKAGE_PINS == 64 + /* Refer User's Manual: Hardware Table 20.6. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x01) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x98) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x0F) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x23) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x0F) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x07) + #define BSP_PRV_PORT9_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x3F) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x80) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x07) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x3B) + #define BSP_PRV_PORTN_NE_PIN_MASK (0x00) +#elif BSP_PACKAGE_PINS == 48 + /* Refer User's Manual: Hardware Table 20.7. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x02) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x9C) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x0F) + #define BSP_PRV_PORT4_NE_PIN_MASK (0xE0) + #define BSP_PRV_PORT5_NE_PIN_MASK (0x33) + #define BSP_PRV_PORT6_NE_PIN_MASK (0x3B) + #define BSP_PRV_PORT7_NE_PIN_MASK (0x01) + #define BSP_PRV_PORT8_NE_PIN_MASK (0x07) + #define BSP_PRV_PORT9_NE_PIN_MASK (0x41) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x3F) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x80) + #define BSP_PRV_PORTD_NE_PIN_MASK (0x57) + #define BSP_PRV_PORTE_NE_PIN_MASK (0x3B) + #define BSP_PRV_PORTN_NE_PIN_MASK (0x00) +#else /* (BSP_PACKAGE_PINS != 100)&&(BSP_PACKAGE_PINS != 80)&&(BSP_PACKAGE_PINS != 64)&&(BSP_PACKAGE_PINS != 48) */ + #error "ERROR - This package is not defined in mcu_init.c" +#endif /* BSP_PACKAGE_PINS == 100 */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_non_existent_port_init +* Description : For MCUs that do not have the maximum number of pins for their group (e.g. MCU with 80 pins when +* maximum is 100 pins) these 'non-existent' pins that are not bonded out need to be initialized to save +* power. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_non_existent_port_init (void) +{ + /* OR in missing pin masks from above. */ + + /* Set PORT0.PDR */ + PORT0.PDR.BYTE |= BSP_PRV_PORT0_NE_PIN_MASK; + + /* Set PORT1.PDR */ + PORT1.PDR.BYTE |= BSP_PRV_PORT1_NE_PIN_MASK; + + /* Set PORT2.PDR */ + PORT2.PDR.BYTE |= BSP_PRV_PORT2_NE_PIN_MASK; + + /* Set PORT3.PDR */ + PORT3.PDR.BYTE |= BSP_PRV_PORT3_NE_PIN_MASK; + + /* Set PORT4.PDR */ + PORT4.PDR.BYTE |= BSP_PRV_PORT4_NE_PIN_MASK; + + /* Set PORT5.PDR */ + PORT5.PDR.BYTE |= BSP_PRV_PORT5_NE_PIN_MASK; + + /* Set PORT6.PDR */ + PORT6.PDR.BYTE |= BSP_PRV_PORT6_NE_PIN_MASK; + + /* Set PORT7.PDR */ + PORT7.PDR.BYTE |= BSP_PRV_PORT7_NE_PIN_MASK; + + /* Set PORT8.PDR */ + PORT8.PDR.BYTE |= BSP_PRV_PORT8_NE_PIN_MASK; + + /* Set PORT9.PDR */ + PORT9.PDR.BYTE |= BSP_PRV_PORT9_NE_PIN_MASK; + + /* Set PORTA.PDR */ + PORTA.PDR.BYTE |= BSP_PRV_PORTA_NE_PIN_MASK; + + /* Set PORTB.PDR */ + PORTB.PDR.BYTE |= BSP_PRV_PORTB_NE_PIN_MASK; + + /* Set PORTD.PDR */ + PORTD.PDR.BYTE |= BSP_PRV_PORTD_NE_PIN_MASK; + + /* Set PORTE.PDR */ + PORTE.PDR.BYTE |= BSP_PRV_PORTE_NE_PIN_MASK; + + /* Set PORTN.PDR */ + PORTN.PDR.BYTE |= BSP_PRV_PORTN_NE_PIN_MASK; +} /* End of function bsp_non_existent_port_init() */ + +/*********************************************************************************************************************** +* Function Name: bsp_tfu_init +* Description : This function does the following as TFU initialization. +* Set the unit and format of the input values in fixed-point sincos operations. +* Set the format of the output values in fixed-point sincos operations. +* Set the unit and format of the output values of atan calculations in fixed-point atanhypot_k +* operations. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +#if BSP_CFG_TFU_INITIALIZE_ENABLE == 1 +void bsp_tfu_init(void) +{ + /* Set the unit and format of the input values in fixed-point sincos operations. */ + TFU.FXSCIOC.BIT.IUF = BSP_CFG_TFU_SINCOS_INPUT_UNIT_FORMAT; + + /* Set the format of the output values in fixed-point sincos operations. */ + TFU.FXSCIOC.BIT.OF = BSP_CFG_TFU_SINCOS_OUTPUT_FORMAT; + + /* Set the unit and format of the output values of atan calculations in fixed-point atanhypot_k operations. */ + TFU.FXATIOC.BIT.OUF = BSP_CFG_TFU_ATAN_OUTPUT_UNIT_FORMAT; +} /* End of function bsp_tfu_init() */ +#endif diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_init.h b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_init.h new file mode 100644 index 00000000..5ca50987 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_init.h @@ -0,0 +1,39 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_init.h +* Description : Performs initialization common to all MCUs in this Group +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 26.02.2025 1.01 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INIT_H +#define MCU_INIT_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void bsp_non_existent_port_init(void); //r_bsp internal function. DO NOT CALL. +#if BSP_CFG_TFU_INITIALIZE_ENABLE == 1 +void bsp_tfu_init(void); +#endif /* BSP_CFG_TFU_INITIALIZE_ENABLE == 1 */ +#endif /* MCU_INIT_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.c b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.c new file mode 100644 index 00000000..0f84106f --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.c @@ -0,0 +1,639 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.c +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 21.11.2023 1.01 Added timeout detection processing to bus error processing. +* Added processing to control only illegal address access detection to bus error +* processing. +* Added processing to control only timeout detection to bus error processing. +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Access to r_bsp. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Let FPSW EV, EO, EZ, EU, EX=1 (FPU exceptions enabled.) */ +#define BSP_PRV_FPU_EXCEPTIONS_ENABLE (0x00007C00) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl0_handler_isr, VECT(ICU,GROUPBL0)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl1_handler_isr, VECT(ICU,GROUPBL1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl2_handler_isr, VECT(ICU,GROUPBL2)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_al0_handler_isr, VECT(ICU,GROUPAL0)) +R_BSP_PRAGMA_STATIC_INTERRUPT(group_al1_handler_isr, VECT(ICU,GROUPAL1)) + +/*********************************************************************************************************************** +* Function Name: bsp_interrupt_enable_disable +* Description : Either enables or disables an interrupt. +* Arguments : vector - +* Which vector to enable or disable. +* enable - +* Whether to enable or disable the interrupt. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_UNSUPPORTED - +* API does not support enabling/disabling for this vector. +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable (bsp_int_src_t vector, bool enable) +{ +#ifdef __FPU + uint32_t tmp_fpsw; +#endif + bsp_int_err_t err = BSP_INT_SUCCESS; + + switch (vector) + { + case (BSP_INT_SRC_BUS_ERROR): + if (true == enable) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU*/ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + + /* Enable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 1; + + /* Enable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 1; + } + else + { + /* Disable the bus error interrupt. */ + /* Disable the interrupt in the ICU*/ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + + /* Disable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 0; + + /* Disable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 0; + } + break; + + case (BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS): + if (true == enable) + { + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU. */ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + } + + /* Enable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 1; + } + else + { + /* Disable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 0; + + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Disable the bus error interrupt in the ICU. */ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + } + } + break; + + case (BSP_INT_SRC_BUS_ERROR_TIMEOUT): + if (true == enable) + { + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU. */ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + } + + /* Enable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 1; + } + else + { + /* Disable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 0; + + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Disable the bus error interrupt in the ICU. */ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + } + } + break; + +#ifdef __FPU + case (BSP_INT_SRC_EXC_FPU): + + /* Get current FPSW. */ + tmp_fpsw = (uint32_t)R_BSP_GET_FPSW(); + + if (true == enable) + { + /* Set the FPU exception flags. */ + R_BSP_SET_FPSW((tmp_fpsw | (uint32_t)BSP_PRV_FPU_EXCEPTIONS_ENABLE)); + } + else + { + /* Clear only the FPU exception flags. */ + R_BSP_SET_FPSW((tmp_fpsw & (uint32_t)~BSP_PRV_FPU_EXCEPTIONS_ENABLE)); + } + break; +#endif + + case (BSP_INT_SRC_EXC_NMI_PIN): + if (true == enable) + { + /* Enable NMI pin interrupt (cannot undo!) */ + ICU.NMIER.BIT.NMIEN = 1; + } + else + { + /* NMI pin interrupts cannot be disabled after being enabled. */ + err = BSP_INT_ERR_UNSUPPORTED; + } + break; + + default: + err = BSP_INT_ERR_UNSUPPORTED; + break; + } + + return err; +} /* End of function bsp_interrupt_enable_disable() */ + +/*********************************************************************************************************************** +* Function Name: group_bl0_handler_isr +* Description : Interrupt handler for Group BL0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl0_handler_isr (void) +{ + /* BL0 IS3 */ + if (1 == ICU.GRPBL0.BIT.IS3) + { + /* BSP_INT_SRC_BL0_SCI1_ERI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_ERI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS2 */ + if (1 == ICU.GRPBL0.BIT.IS2) + { + /* BSP_INT_SRC_BL0_SCI1_TEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_TEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS11 */ + if (1 == ICU.GRPBL0.BIT.IS11) + { + /* BSP_INT_SRC_BL0_SCI5_ERI5 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_ERI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS10 */ + if (1 == ICU.GRPBL0.BIT.IS10) + { + /* BSP_INT_SRC_BL0_SCI5_TEI5 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_TEI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS13 */ + if (1 == ICU.GRPBL0.BIT.IS13) + { + /* BSP_INT_SRC_BL0_SCI6_ERI6 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_ERI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS12 */ + if (1 == ICU.GRPBL0.BIT.IS12) + { + /* BSP_INT_SRC_BL0_SCI6_TEI6 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_TEI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS17 */ + if (1 == ICU.GRPBL0.BIT.IS17) + { + /* BSP_INT_SRC_BL0_SCI12_ERI12 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_ERI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS16 */ + if (1 == ICU.GRPBL0.BIT.IS16) + { + /* BSP_INT_SRC_BL0_SCI12_TEI12 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_TEI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS118 */ + if (1 == ICU.GRPBL0.BIT.IS18) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS19 */ + if (1 == ICU.GRPBL0.BIT.IS19) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS20 */ + if (1 == ICU.GRPBL0.BIT.IS20) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS21 */ + if (1 == ICU.GRPBL0.BIT.IS21) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS26 */ + if (1 == ICU.GRPBL0.BIT.IS26) + { + /* BSP_INT_SRC_BL0_CAC_FERRI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_FERRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS27 */ + if (1 == ICU.GRPBL0.BIT.IS27) + { + /* BSP_INT_SRC_BL0_CAC_MENDI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_MENDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS28 */ + if (1 == ICU.GRPBL0.BIT.IS28) + { + /* BSP_INT_SRC_BL0_CAC_OVFI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_OVFI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS29 */ + if (1 == ICU.GRPBL0.BIT.IS29) + { + /* BSP_INT_SRC_BL0_DOC_DOPCI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_DOC_DOPCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_bl1_handler_isr +* Description : Interrupt handler for Group BL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl1_handler_isr (void) +{ + /* BL1 IS0 */ + if (1 == ICU.GRPBL1.BIT.IS0) + { + /* BSP_INT_SRC_BL1_POEG_POEGGAI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS1 */ + if (1 == ICU.GRPBL1.BIT.IS1) + { + /* BSP_INT_SRC_BL1_POEG_POEGGBI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS2 */ + if (1 == ICU.GRPBL1.BIT.IS2) + { + /* BSP_INT_SRC_BL1_POEG_POEGGCI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS3 */ + if (1 == ICU.GRPBL1.BIT.IS3) + { + /* BSP_INT_SRC_BL1_POEG_POEGGDI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS8 */ + if (1 == ICU.GRPBL1.BIT.IS8) + { + /* BSP_INT_SRC_BL1_POE3_OEI5 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS9 */ + if (1 == ICU.GRPBL1.BIT.IS9) + { + /* BSP_INT_SRC_BL1_POE3_OEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS10 */ + if (1 == ICU.GRPBL1.BIT.IS10) + { + /* BSP_INT_SRC_BL1_POE3_OEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS11 */ + if (1 == ICU.GRPBL1.BIT.IS11) + { + /* BSP_INT_SRC_BL1_POE3_OEI3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS12 */ + if (1 == ICU.GRPBL1.BIT.IS12) + { + /* BSP_INT_SRC_BL1_POE3_OEI4 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS14 */ + if (1 == ICU.GRPBL1.BIT.IS14) + { + /* BSP_INT_SRC_BL1_RIIC0_EEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_EEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS13 */ + if (1 == ICU.GRPBL1.BIT.IS13) + { + /* BSP_INT_SRC_BL1_RIIC0_TEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_TEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS18 */ + if (1 == ICU.GRPBL1.BIT.IS18) + { + /* BSP_INT_SRC_BL1_S12AD2_S12CMPAI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD2_S12CMPAI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS19 */ + if (1 == ICU.GRPBL1.BIT.IS19) + { + /* BSP_INT_SRC_BL1_S12AD2_S12CMPBI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD2_S12CMPBI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS20 */ + if (1 == ICU.GRPBL1.BIT.IS20) + { + /* BSP_INT_SRC_BL1_S12AD0_S12CMPAI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS21 */ + if (1 == ICU.GRPBL1.BIT.IS21) + { + /* BSP_INT_SRC_BL1_S12AD0_S12CMPBI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS22 */ + if (1 == ICU.GRPBL1.BIT.IS22) + { + /* BSP_INT_SRC_BL1_S12AD1_S12CMPAI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS23 */ + if (1 == ICU.GRPBL1.BIT.IS23) + { + /* BSP_INT_SRC_BL1_S12AD1_S12CMPBI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS25 */ + if (1 == ICU.GRPBL1.BIT.IS25) + { + /* BSP_INT_SRC_BL1_RSCI8_ERI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI8_ERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS24 */ + if (1 == ICU.GRPBL1.BIT.IS24) + { + /* BSP_INT_SRC_BL1_RSCI8_TEI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI8_TEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS27 */ + if (1 == ICU.GRPBL1.BIT.IS27) + { + /* BSP_INT_SRC_BL1_RSCI9_ERI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI9_ERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS26 */ + if (1 == ICU.GRPBL1.BIT.IS26) + { + /* BSP_INT_SRC_BL1_RSCI9_TEI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI9_TEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS31 */ + if (1 == ICU.GRPBL1.BIT.IS31) + { + /* BSP_INT_SRC_BL1_RSCI9_BFD */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI9_BFD, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl1_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_bl2_handler_isr +* Description : Interrupt handler for Group BL2 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl2_handler_isr (void) +{ + /* BL2 IS1 */ + if (1 == ICU.GRPBL2.BIT.IS1) + { + /* BSP_INT_SRC_BL2_CANFD0_CHEI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD0_CHEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS2 */ + if (1 == ICU.GRPBL2.BIT.IS2) + { + /* BSP_INT_SRC_BL2_CANFD0_CFRI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD0_CFRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS3 */ + if (1 == ICU.GRPBL2.BIT.IS3) + { + /* BSP_INT_SRC_BL2_CANFD_GLEI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD_GLEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS4 */ + if (1 == ICU.GRPBL2.BIT.IS4) + { + /* BSP_INT_SRC_BL2_CANFD_RFRI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD_RFRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS5 */ + if (1 == ICU.GRPBL2.BIT.IS5) + { + /* BSP_INT_SRC_BL2_CANFD0_CHTI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD0_CHTI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS6 */ + if (1 == ICU.GRPBL2.BIT.IS6) + { + /* BSP_INT_SRC_BL2_CANFD_RMRI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD_RMRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl2_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_al0_handler_isr +* Description : Interrupt handler for Group AL0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_al0_handler_isr (void) +{ + /* AL0 IS13 */ + if (1 == ICU.GRPAL0.BIT.IS13) + { + /* BSP_INT_SRC_AL0_RSCI11_ERI */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSCI11_ERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS12 */ + if (1 == ICU.GRPAL0.BIT.IS12) + { + /* BSP_INT_SRC_AL0_RSCI11_TEI */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSCI11_TEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS14 */ + if (1 == ICU.GRPAL0.BIT.IS14) + { + /* BSP_INT_SRC_AL0_RSCI11_BFD */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSCI11_BFD, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS17 */ + if (1 == ICU.GRPAL0.BIT.IS17) + { + /* BSP_INT_SRC_AL0_RSPI0_SPEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS16 */ + if (1 == ICU.GRPAL0.BIT.IS16) + { + /* BSP_INT_SRC_AL0_RSPI0_SPII0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPII0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS23 */ + if (1 == ICU.GRPAL0.BIT.IS23) + { + /* BSP_INT_SRC_AL0_RSPIA0_SPEI */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPIA0_SPEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS22 */ + if (1 == ICU.GRPAL0.BIT.IS22) + { + /* BSP_INT_SRC_AL0_RSPIA0_SPII */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPIA0_SPII, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_al0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_al1_handler_isr +* Description : Interrupt handler for Group AL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void group_al1_handler_isr (void) +{ + /* AL1 IS13 */ + if (1 == ICU.GRPAL1.BIT.IS13) + { + /* BSP_INT_SRC_AL1_RI3C0_EEI */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_RI3C0_EEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_al1_handler_isr() */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.h b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.h new file mode 100644 index 00000000..57923ae8 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.h @@ -0,0 +1,190 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.h +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 21.11.2023 1.01 Added the following enumeration constant. +* - BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS +* - BSP_INT_SRC_BUS_ERROR_TIMEOUT +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INTERRUPTS_H +#define MCU_INTERRUPTS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Available return codes. */ +typedef enum +{ + BSP_INT_SUCCESS = 0, + BSP_INT_ERR_NO_REGISTERED_CALLBACK, /* There is not a registered callback for this interrupt source */ + BSP_INT_ERR_INVALID_ARG, /* Illegal argument input */ + BSP_INT_ERR_UNSUPPORTED, /* Operation is not supported by this API */ + BSP_INT_ERR_GROUP_STILL_ENABLED, /* Not all group interrupts were disabled so group interrupt was not + disabled */ + BSP_INT_ERR_INVALID_IPL /* Illegal IPL value input */ +} bsp_int_err_t; + +/* Available interrupts to register a callback for. */ +typedef enum +{ + BSP_INT_SRC_EXC_SUPERVISOR_INSTR = 0, /* Occurs when privileged instruction is executed in User Mode */ + BSP_INT_SRC_EXC_UNDEFINED_INSTR, /* Occurs when MCU encounters an unknown instruction */ + BSP_INT_SRC_EXC_NMI_PIN, /* NMI Pin interrupt */ + BSP_INT_SRC_EXC_FPU, /* FPU exception */ + BSP_INT_SRC_EXC_ACCESS, /* Access exception */ + BSP_INT_SRC_OSC_STOP_DETECT, /* Oscillation stop is detected */ + BSP_INT_SRC_WDT_ERROR, /* WDT underflow/refresh error has occurred */ + BSP_INT_SRC_IWDT_ERROR, /* IWDT underflow/refresh error has occurred */ + BSP_INT_SRC_LVD1, /* Voltage monitoring 1 interrupt */ + BSP_INT_SRC_LVD2, /* Voltage monitoring 2 interrupt */ + BSP_INT_SRC_UNDEFINED_INTERRUPT, /* Interrupt has triggered for a vector that user did not write a handler. */ + BSP_INT_SRC_BUS_ERROR, /* Bus error: illegal address access or timeout */ + BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS, /* Bus error: illegal address access. Use this when you want to set only Illegal address access detection. */ + BSP_INT_SRC_BUS_ERROR_TIMEOUT, /* Bus error: timeout. Use this when you want to set only Bus timeout detection. */ + BSP_INT_SRC_RAM, /* RAM error interrupt */ + + BSP_INT_SRC_GR_INT_TOP, + + /* IE0 Group Interrupts */ + BSP_INT_SRC_GR_INT_IE0_TOP, + + /* BE0 Group Interrupts */ + BSP_INT_SRC_GR_INT_BE0_TOP, + + /* BL0 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL0_TOP, + BSP_INT_SRC_BL0_SCI1_TEI1, + BSP_INT_SRC_BL0_SCI1_ERI1, + BSP_INT_SRC_BL0_SCI5_TEI5, + BSP_INT_SRC_BL0_SCI5_ERI5, + BSP_INT_SRC_BL0_SCI6_TEI6, + BSP_INT_SRC_BL0_SCI6_ERI6, + BSP_INT_SRC_BL0_SCI12_TEI12, + BSP_INT_SRC_BL0_SCI12_ERI12, + BSP_INT_SRC_BL0_SCI12_SCIX0, + BSP_INT_SRC_BL0_SCI12_SCIX1, + BSP_INT_SRC_BL0_SCI12_SCIX2, + BSP_INT_SRC_BL0_SCI12_SCIX3, + BSP_INT_SRC_BL0_CAC_FERRI, + BSP_INT_SRC_BL0_CAC_MENDI, + BSP_INT_SRC_BL0_CAC_OVFI, + BSP_INT_SRC_BL0_DOC_DOPCI, + + /* BL1 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL1_TOP, + BSP_INT_SRC_BL1_POEG_POEGGAI, + BSP_INT_SRC_BL1_POEG_POEGGBI, + BSP_INT_SRC_BL1_POEG_POEGGCI, + BSP_INT_SRC_BL1_POEG_POEGGDI, + BSP_INT_SRC_BL1_POE3_OEI5, + BSP_INT_SRC_BL1_POE3_OEI1, + BSP_INT_SRC_BL1_POE3_OEI2, + BSP_INT_SRC_BL1_POE3_OEI3, + BSP_INT_SRC_BL1_POE3_OEI4, + BSP_INT_SRC_BL1_RIIC0_TEI0, + BSP_INT_SRC_BL1_RIIC0_EEI0, + BSP_INT_SRC_BL1_S12AD2_S12CMPAI2, + BSP_INT_SRC_BL1_S12AD2_S12CMPBI2, + BSP_INT_SRC_BL1_S12AD0_S12CMPAI, + BSP_INT_SRC_BL1_S12AD0_S12CMPBI, + BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, + BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, + BSP_INT_SRC_BL1_RSCI8_TEI, + BSP_INT_SRC_BL1_RSCI8_ERI, + BSP_INT_SRC_BL1_RSCI9_TEI, + BSP_INT_SRC_BL1_RSCI9_ERI, + BSP_INT_SRC_BL1_RSCI9_BFD, + + /* BL2 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL2_TOP, + BSP_INT_SRC_BL2_CANFD0_CHEI, + BSP_INT_SRC_BL2_CANFD0_CFRI, + BSP_INT_SRC_BL2_CANFD_GLEI, + BSP_INT_SRC_BL2_CANFD_RFRI, + BSP_INT_SRC_BL2_CANFD0_CHTI, + BSP_INT_SRC_BL2_CANFD_RMRI, + + /* AL0 Group Interrupts. */ + BSP_INT_SRC_GR_INT_AL0_TOP, + BSP_INT_SRC_AL0_RSCI11_TEI, + BSP_INT_SRC_AL0_RSCI11_ERI, + BSP_INT_SRC_AL0_RSCI11_BFD, + BSP_INT_SRC_AL0_RSPI0_SPII0, + BSP_INT_SRC_AL0_RSPI0_SPEI0, + BSP_INT_SRC_AL0_RSPIA0_SPII, + BSP_INT_SRC_AL0_RSPIA0_SPEI, + + /* AL1 Group Interrupts. */ + BSP_INT_SRC_GR_INT_AL1_TOP, + BSP_INT_SRC_AL1_RI3C0_EEI, + + BSP_INT_SRC_GR_INT_END, + BSP_INT_SRC_EMPTY, + BSP_INT_SRC_TOTAL_ITEMS /* DO NOT MODIFY! This is used for sizing the interrupt callback array. */ +} bsp_int_src_t; + +/* Available commands for R_BSP_InterruptControl() function. */ +typedef enum +{ + BSP_INT_CMD_CALL_CALLBACK = 0, /* Calls registered callback function if one exists */ + BSP_INT_CMD_INTERRUPT_ENABLE, /* Enables a given interrupt (Available for NMI pin, FPU, and Bus Error) */ + BSP_INT_CMD_INTERRUPT_DISABLE, /* Disables a given interrupt (Available for FPU, and Bus Error) */ + BSP_INT_CMD_GROUP_INTERRUPT_ENABLE, /* Enables a group interrupt when a group interrupt source is given. The + pdata argument should give the IPL to be used using the bsp_int_ctrl_t + type. If a group interrupt is enabled multiple times with different IPL + levels it will use the highest given IPL. */ + BSP_INT_CMD_GROUP_INTERRUPT_DISABLE, /* Disables a group interrupt when a group interrupt source is given. + This will only disable a group interrupt when all interrupt + sources for that group are already disabled. */ + BSP_INT_CMD_FIT_INTERRUPT_ENABLE, /* Enables interrupt by control of IPL. */ + BSP_INT_CMD_FIT_INTERRUPT_DISABLE /* Disables interrupt by control of IPL. */ +} bsp_int_cmd_t; + +/* Type to be used for pdata argument in Control function. */ +typedef union +{ + uint32_t ipl; /* Used at the following times. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command. + - When disabling an interrupt to save that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_DISABLE command. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_ENABLE command. */ +} bsp_int_ctrl_t; + +/* Easy to use typedef for callback functions. */ +typedef void (*bsp_int_cb_t)(void *); + +/* This structure is the common one that is passed as the 'void *' argument to callback functions when an + * exception occurs. + */ +typedef struct +{ + bsp_int_src_t vector; /* Which vector caused this interrupt */ +} bsp_int_cb_args_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable(bsp_int_src_t vector, bool enable); + +#endif /* MCU_INTERRUPTS_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_locks.h b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_locks.h new file mode 100644 index 00000000..a0b0de63 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_locks.h @@ -0,0 +1,172 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_locks.h +* Device(s) : RX26T +* Description : This source file has 1 lock per MCU resource. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 26.02.2025 1.01 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Gets MCU configuration information. */ +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_LOCKS_H +#define MCU_LOCKS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* This enum defines all of the available hardware locks for this MCU. If you delete an entry out of this list then you + will decrease the size of the locks array but will not be able to use that lock. For example, if your design is not + using CAN at all then you can safely remove the BSP_LOCK_CAN# entries below. */ +typedef enum +{ + BSP_LOCK_BSC = 0, + BSP_LOCK_CAC, + BSP_LOCK_CANFD0, + BSP_LOCK_CMPC0, + BSP_LOCK_CMPC1, + BSP_LOCK_CMPC2, + BSP_LOCK_CMPC3, + BSP_LOCK_CMPC4, + BSP_LOCK_CMPC5, + BSP_LOCK_CMT, + BSP_LOCK_CMT0, + BSP_LOCK_CMT1, + BSP_LOCK_CMT2, + BSP_LOCK_CMT3, + BSP_LOCK_CMTW0, + BSP_LOCK_CMTW1, + BSP_LOCK_CRC, + BSP_LOCK_DA, + BSP_LOCK_DMAC, + BSP_LOCK_DMAC0, + BSP_LOCK_DMAC1, + BSP_LOCK_DMAC2, + BSP_LOCK_DMAC3, + BSP_LOCK_DMAC4, + BSP_LOCK_DMAC5, + BSP_LOCK_DMAC6, + BSP_LOCK_DMAC7, + BSP_LOCK_DOC, + BSP_LOCK_DTC, + BSP_LOCK_ELC, + BSP_LOCK_FLASH, + BSP_LOCK_FLASHCONST, + BSP_LOCK_GPTW0, + BSP_LOCK_GPTW1, + BSP_LOCK_GPTW2, + BSP_LOCK_GPTW3, + BSP_LOCK_GPTW4, + BSP_LOCK_GPTW5, + BSP_LOCK_GPTW6, + BSP_LOCK_GPTW7, + BSP_LOCK_HRPWM, + BSP_LOCK_IRQ0, + BSP_LOCK_IRQ1, + BSP_LOCK_IRQ2, + BSP_LOCK_IRQ3, + BSP_LOCK_IRQ4, + BSP_LOCK_IRQ5, + BSP_LOCK_IRQ6, + BSP_LOCK_IRQ7, + BSP_LOCK_IRQ8, + BSP_LOCK_IRQ9, + BSP_LOCK_IRQ10, + BSP_LOCK_IRQ11, + BSP_LOCK_IRQ12, + BSP_LOCK_IRQ13, + BSP_LOCK_IRQ14, + BSP_LOCK_IRQ15, + BSP_LOCK_ICU, + BSP_LOCK_IWDT, + BSP_LOCK_MPC, + BSP_LOCK_MPU, + BSP_LOCK_MTU, + BSP_LOCK_MTU0, + BSP_LOCK_MTU1, + BSP_LOCK_MTU2, + BSP_LOCK_MTU3, + BSP_LOCK_MTU4, + BSP_LOCK_MTU5, + BSP_LOCK_MTU6, + BSP_LOCK_MTU7, + BSP_LOCK_MTU9, + BSP_LOCK_POE, + BSP_LOCK_POEG, + BSP_LOCK_RAM, + BSP_LOCK_RI3C0, + BSP_LOCK_RIIC0, + BSP_LOCK_RSCI8, + BSP_LOCK_RSCI9, + BSP_LOCK_RSCI11, + BSP_LOCK_RSPI0, + BSP_LOCK_RSPIA0, + BSP_LOCK_S12AD, + BSP_LOCK_S12AD1, + BSP_LOCK_S12AD2, + BSP_LOCK_SCI1, + BSP_LOCK_SCI5, + BSP_LOCK_SCI6, + BSP_LOCK_SCI12, + BSP_LOCK_SYSTEM, + BSP_LOCK_TEMPS, + BSP_LOCK_TMR0, + BSP_LOCK_TMR1, + BSP_LOCK_TMR2, + BSP_LOCK_TMR3, + BSP_LOCK_TMR4, + BSP_LOCK_TMR5, + BSP_LOCK_TMR6, + BSP_LOCK_TMR7, + BSP_LOCK_TMR01, + BSP_LOCK_TMR23, + BSP_LOCK_TMR45, + BSP_LOCK_TMR67, + BSP_LOCK_WDT, + BSP_LOCK_SWINT, + BSP_LOCK_SWINT2, + BSP_NUM_LOCKS //This entry is not a valid lock. It is used for sizing g_bsp_Locks[] array below. Do not touch! +} mcu_lock_t; + +typedef struct +{ + /* The actual lock. int32_t is used because this is what the xchg() instruction takes as parameters. */ + int32_t lock; + + /* Could add a ID for locking and unlocking. In this could protect against any function being able to unlock. */ +} bsp_lock_t; + +/*********************************************************************************************************************** +Error checking +***********************************************************************************************************************/ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 +#undef BSP_CFG_USER_LOCKING_TYPE +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t +#else + #if !defined(BSP_CFG_USER_LOCKING_TYPE) + #error "R_BSP ERROR - If you are using your own locking mechanism then you must define BSP_CFG_USER_LOCKING_TYPE in r_bsp_config.h." + #endif +#endif + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +extern BSP_CFG_USER_LOCKING_TYPE g_bsp_Locks[]; + +#endif /* MCU_LOCKS_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_mapped_interrupts.c b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_mapped_interrupts.c new file mode 100644 index 00000000..8bfa3b48 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_mapped_interrupts.c @@ -0,0 +1,714 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_mapped_interrupts.c +* Description : This module maps Interrupt A interrupts. Which interrupts are mapped depends on the macros in +* r_bsp_interrupt_config.h. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 21.11.2023 1.01 Added processing to clear the IR flag. +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Access to r_bsp. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_mapped_interrupt_open +* Description : Initializes mapped interrupts. This code does the following for each possible mapped interrupt: +* 1) PREPROCCESOR - Test to see if this interrupt is chosen to be used +* 2) PREPROCESSOR - Figure out which interrupt select register needs to be written to +* 3) RUNTIME C - Set the appropriate select register with the number of this mapped interrupt +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void bsp_mapped_interrupt_open (void) +{ +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) = BSP_PRV_INT_A_NUM_MTU0_TGIA0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) = BSP_PRV_INT_A_NUM_MTU0_TGIB0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) = BSP_PRV_INT_A_NUM_MTU0_TGIC0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) = BSP_PRV_INT_A_NUM_MTU0_TGID0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) = BSP_PRV_INT_A_NUM_MTU0_TCIV0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) = BSP_PRV_INT_A_NUM_MTU0_TGIE0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) = BSP_PRV_INT_A_NUM_MTU0_TGIF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) = BSP_PRV_INT_A_NUM_MTU1_TGIA1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) = BSP_PRV_INT_A_NUM_MTU1_TGIB1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) = BSP_PRV_INT_A_NUM_MTU1_TCIV1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) = BSP_PRV_INT_A_NUM_MTU1_TCIU1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) = BSP_PRV_INT_A_NUM_MTU2_TGIA2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) = BSP_PRV_INT_A_NUM_MTU2_TGIB2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) = BSP_PRV_INT_A_NUM_MTU2_TCIV2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) = BSP_PRV_INT_A_NUM_MTU2_TCIU2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) = BSP_PRV_INT_A_NUM_MTU3_TGIA3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) = BSP_PRV_INT_A_NUM_MTU3_TGIB3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) = BSP_PRV_INT_A_NUM_MTU3_TGIC3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) = BSP_PRV_INT_A_NUM_MTU3_TGID3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) = BSP_PRV_INT_A_NUM_MTU3_TCIV3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) = BSP_PRV_INT_A_NUM_MTU4_TGIA4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) = BSP_PRV_INT_A_NUM_MTU4_TGIB4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) = BSP_PRV_INT_A_NUM_MTU4_TGIC4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) = BSP_PRV_INT_A_NUM_MTU4_TGID4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) = BSP_PRV_INT_A_NUM_MTU4_TCIV4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) = BSP_PRV_INT_A_NUM_MTU5_TGIU5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) = BSP_PRV_INT_A_NUM_MTU5_TGIV5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) = BSP_PRV_INT_A_NUM_MTU5_TGIW5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) = BSP_PRV_INT_A_NUM_MTU6_TGIA6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) = BSP_PRV_INT_A_NUM_MTU6_TGIB6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) = BSP_PRV_INT_A_NUM_MTU6_TGIC6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) = BSP_PRV_INT_A_NUM_MTU6_TGID6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) = BSP_PRV_INT_A_NUM_MTU6_TCIV6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) = BSP_PRV_INT_A_NUM_MTU7_TGIA7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) = BSP_PRV_INT_A_NUM_MTU7_TGIB7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) = BSP_PRV_INT_A_NUM_MTU7_TGIC7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) = BSP_PRV_INT_A_NUM_MTU7_TGID7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) = BSP_PRV_INT_A_NUM_MTU7_TCIV7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIA9) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIA9) = BSP_PRV_INT_A_NUM_MTU9_TGIA9; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIB9) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIB9) = BSP_PRV_INT_A_NUM_MTU9_TGIB9; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIC9) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIC9) = BSP_PRV_INT_A_NUM_MTU9_TGIC9; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGID9) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGID9) = BSP_PRV_INT_A_NUM_MTU9_TGID9; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TCIV9) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TCIV9) = BSP_PRV_INT_A_NUM_MTU9_TCIV9; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIE9) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIE9) = BSP_PRV_INT_A_NUM_MTU9_TGIE9; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIF9) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIF9) = BSP_PRV_INT_A_NUM_MTU9_TGIF9; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIA0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIB0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIC0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) = BSP_PRV_INT_A_NUM_GPTW0_GTCID0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) = BSP_PRV_INT_A_NUM_GPTW0_GDTE0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIE0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIF0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIV0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) = BSP_PRV_INT_A_NUM_GPTW0_GTCIU0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIA1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIB1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIC1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) = BSP_PRV_INT_A_NUM_GPTW1_GTCID1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) = BSP_PRV_INT_A_NUM_GPTW1_GDTE1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIE1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIF1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIV1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) = BSP_PRV_INT_A_NUM_GPTW1_GTCIU1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIA2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIB2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIC2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) = BSP_PRV_INT_A_NUM_GPTW2_GTCID2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) = BSP_PRV_INT_A_NUM_GPTW2_GDTE2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIE2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIF2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIV2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) = BSP_PRV_INT_A_NUM_GPTW2_GTCIU2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIA3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIB3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIC3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) = BSP_PRV_INT_A_NUM_GPTW3_GTCID3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) = BSP_PRV_INT_A_NUM_GPTW3_GDTE3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIE3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIF3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIV3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) = BSP_PRV_INT_A_NUM_GPTW3_GTCIU3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIA4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIA4) = BSP_PRV_INT_A_NUM_GPTW4_GTCIA4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIB4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIB4) = BSP_PRV_INT_A_NUM_GPTW4_GTCIB4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIC4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIC4) = BSP_PRV_INT_A_NUM_GPTW4_GTCIC4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCID4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCID4) = BSP_PRV_INT_A_NUM_GPTW4_GTCID4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GDTE4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GDTE4) = BSP_PRV_INT_A_NUM_GPTW4_GDTE4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIE4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIE4) = BSP_PRV_INT_A_NUM_GPTW4_GTCIE4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIF4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIF4) = BSP_PRV_INT_A_NUM_GPTW4_GTCIF4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIV4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIV4) = BSP_PRV_INT_A_NUM_GPTW4_GTCIV4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIU4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIU4) = BSP_PRV_INT_A_NUM_GPTW4_GTCIU4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIA5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIA5) = BSP_PRV_INT_A_NUM_GPTW5_GTCIA5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIB5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIB5) = BSP_PRV_INT_A_NUM_GPTW5_GTCIB5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIC5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIC5) = BSP_PRV_INT_A_NUM_GPTW5_GTCIC5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCID5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCID5) = BSP_PRV_INT_A_NUM_GPTW5_GTCID5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GDTE5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GDTE5) = BSP_PRV_INT_A_NUM_GPTW5_GDTE5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIE5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIE5) = BSP_PRV_INT_A_NUM_GPTW5_GTCIE5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIF5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIF5) = BSP_PRV_INT_A_NUM_GPTW5_GTCIF5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIV5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIV5) = BSP_PRV_INT_A_NUM_GPTW5_GTCIV5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIU5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIU5) = BSP_PRV_INT_A_NUM_GPTW5_GTCIU5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIA6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIA6) = BSP_PRV_INT_A_NUM_GPTW6_GTCIA6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIB6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIB6) = BSP_PRV_INT_A_NUM_GPTW6_GTCIB6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIC6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIC6) = BSP_PRV_INT_A_NUM_GPTW6_GTCIC6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCID6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCID6) = BSP_PRV_INT_A_NUM_GPTW6_GTCID6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GDTE6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GDTE6) = BSP_PRV_INT_A_NUM_GPTW6_GDTE6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIE6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIE6) = BSP_PRV_INT_A_NUM_GPTW6_GTCIE6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIF6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIF6) = BSP_PRV_INT_A_NUM_GPTW6_GTCIF6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIV6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIV6) = BSP_PRV_INT_A_NUM_GPTW6_GTCIV6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIU6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIU6) = BSP_PRV_INT_A_NUM_GPTW6_GTCIU6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIA7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIA7) = BSP_PRV_INT_A_NUM_GPTW7_GTCIA7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIB7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIB7) = BSP_PRV_INT_A_NUM_GPTW7_GTCIB7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIC7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIC7) = BSP_PRV_INT_A_NUM_GPTW7_GTCIC7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCID7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCID7) = BSP_PRV_INT_A_NUM_GPTW7_GTCID7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GDTE7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GDTE7) = BSP_PRV_INT_A_NUM_GPTW7_GDTE7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIE7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIE7) = BSP_PRV_INT_A_NUM_GPTW7_GTCIE7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIF7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIF7) = BSP_PRV_INT_A_NUM_GPTW7_GTCIF7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIV7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIV7) = BSP_PRV_INT_A_NUM_GPTW7_GTCIV7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIU7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIU7) = BSP_PRV_INT_A_NUM_GPTW7_GTCIU7; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_RSPIA0_SPCI) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSPIA0_SPCI) = BSP_PRV_INT_A_NUM_RSPIA0_SPCI; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_RSPI0_SPCI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSPI0_SPCI0) = BSP_PRV_INT_A_NUM_RSPI0_SPCI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_RSCI11_AED) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSCI11_AED) = BSP_PRV_INT_A_NUM_RSCI11_AED; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC1EI) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC1EI) = BSP_PRV_INT_A_NUM_CANFD_EC1EI; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC2EI) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC2EI) = BSP_PRV_INT_A_NUM_CANFD_EC2EI; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_ECOVI) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_ECOVI) = BSP_PRV_INT_A_NUM_CANFD_ECOVI; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCEI0) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCEI0) = BSP_PRV_INT_A_NUM_GPTW0_GTCEI0; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCEI1) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCEI1) = BSP_PRV_INT_A_NUM_GPTW1_GTCEI1; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCEI2) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCEI2) = BSP_PRV_INT_A_NUM_GPTW2_GTCEI2; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCEI3) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCEI3) = BSP_PRV_INT_A_NUM_GPTW3_GTCEI3; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCEI4) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCEI4) = BSP_PRV_INT_A_NUM_GPTW4_GTCEI4; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCEI5) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCEI5) = BSP_PRV_INT_A_NUM_GPTW5_GTCEI5; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCEI6) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCEI6) = BSP_PRV_INT_A_NUM_GPTW6_GTCEI6; +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCEI7) + /* Casting is valid because it matches the type to the right side or argument. */ + BSP_PRV_INT_SELECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCEI7) = BSP_PRV_INT_A_NUM_GPTW7_GTCEI7; +#endif + + /* Write 0 to the IRn.IR flag. */ + /* WAIT_LOOP */ + for(uint16_t i = IR_PERIA_INTA208;i <= IR_PERIA_INTA255; i++) + { + ICU.IR[i].BIT.IR = 0; + } + +} /* End of function bsp_mapped_interrupt_open() */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_mapped_interrupts.h b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_mapped_interrupts.h new file mode 100644 index 00000000..48e15abb --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_mapped_interrupts.h @@ -0,0 +1,1357 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_mapped_interrupts.c +* Description : This module maps Interrupt A interrupts. Which interrupts are mapped depends on the macros in +* r_bsp_interrupt_config.h. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 26.02.2025 1.01 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_MAPPED_INTERRUPTS_H +#define MCU_MAPPED_INTERRUPTS_H + +/* The following macros define the number for each interrupt request source as it pertains to being an Interrupt A + * interrupt. These values are used when setting the interrupt select registers (i.e. SLIARn). + */ +/* Available Interrupt A Sources. */ +#define BSP_PRV_INT_A_NUM_MTU0_TGIA0 1 +#define BSP_PRV_INT_A_NUM_MTU0_TGIB0 2 +#define BSP_PRV_INT_A_NUM_MTU0_TGIC0 3 +#define BSP_PRV_INT_A_NUM_MTU0_TGID0 4 +#define BSP_PRV_INT_A_NUM_MTU0_TCIV0 5 +#define BSP_PRV_INT_A_NUM_MTU0_TGIE0 6 +#define BSP_PRV_INT_A_NUM_MTU0_TGIF0 7 +#define BSP_PRV_INT_A_NUM_MTU1_TGIA1 8 +#define BSP_PRV_INT_A_NUM_MTU1_TGIB1 9 +#define BSP_PRV_INT_A_NUM_MTU1_TCIV1 10 +#define BSP_PRV_INT_A_NUM_MTU1_TCIU1 11 +#define BSP_PRV_INT_A_NUM_MTU2_TGIA2 12 +#define BSP_PRV_INT_A_NUM_MTU2_TGIB2 13 +#define BSP_PRV_INT_A_NUM_MTU2_TCIV2 14 +#define BSP_PRV_INT_A_NUM_MTU2_TCIU2 15 +#define BSP_PRV_INT_A_NUM_MTU3_TGIA3 16 +#define BSP_PRV_INT_A_NUM_MTU3_TGIB3 17 +#define BSP_PRV_INT_A_NUM_MTU3_TGIC3 18 +#define BSP_PRV_INT_A_NUM_MTU3_TGID3 19 +#define BSP_PRV_INT_A_NUM_MTU3_TCIV3 20 +#define BSP_PRV_INT_A_NUM_MTU4_TGIA4 21 +#define BSP_PRV_INT_A_NUM_MTU4_TGIB4 22 +#define BSP_PRV_INT_A_NUM_MTU4_TGIC4 23 +#define BSP_PRV_INT_A_NUM_MTU4_TGID4 24 +#define BSP_PRV_INT_A_NUM_MTU4_TCIV4 25 +#define BSP_PRV_INT_A_NUM_MTU5_TGIU5 27 +#define BSP_PRV_INT_A_NUM_MTU5_TGIV5 28 +#define BSP_PRV_INT_A_NUM_MTU5_TGIW5 29 +#define BSP_PRV_INT_A_NUM_MTU6_TGIA6 30 +#define BSP_PRV_INT_A_NUM_MTU6_TGIB6 31 +#define BSP_PRV_INT_A_NUM_MTU6_TGIC6 32 +#define BSP_PRV_INT_A_NUM_MTU6_TGID6 33 +#define BSP_PRV_INT_A_NUM_MTU6_TCIV6 34 +#define BSP_PRV_INT_A_NUM_MTU7_TGIA7 35 +#define BSP_PRV_INT_A_NUM_MTU7_TGIB7 36 +#define BSP_PRV_INT_A_NUM_MTU7_TGIC7 37 +#define BSP_PRV_INT_A_NUM_MTU7_TGID7 38 +#define BSP_PRV_INT_A_NUM_MTU7_TCIV7 39 +#define BSP_PRV_INT_A_NUM_MTU9_TGIA9 47 +#define BSP_PRV_INT_A_NUM_MTU9_TGIB9 48 +#define BSP_PRV_INT_A_NUM_MTU9_TGIC9 49 +#define BSP_PRV_INT_A_NUM_MTU9_TGID9 50 +#define BSP_PRV_INT_A_NUM_MTU9_TCIV9 51 +#define BSP_PRV_INT_A_NUM_MTU9_TGIE9 52 +#define BSP_PRV_INT_A_NUM_MTU9_TGIF9 53 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIA0 56 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIB0 57 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIC0 58 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCID0 59 +#define BSP_PRV_INT_A_NUM_GPTW0_GDTE0 60 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIE0 61 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIF0 62 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIV0 63 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCIU0 64 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIA1 65 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIB1 66 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIC1 67 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCID1 68 +#define BSP_PRV_INT_A_NUM_GPTW1_GDTE1 69 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIE1 70 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIF1 71 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIV1 72 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCIU1 73 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIA2 74 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIB2 75 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIC2 76 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCID2 77 +#define BSP_PRV_INT_A_NUM_GPTW2_GDTE2 78 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIE2 79 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIF2 80 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIV2 81 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCIU2 82 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIA3 83 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIB3 84 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIC3 85 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCID3 86 +#define BSP_PRV_INT_A_NUM_GPTW3_GDTE3 87 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIE3 88 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIF3 89 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIV3 90 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCIU3 91 +#define BSP_PRV_INT_A_NUM_GPTW4_GTCIA4 92 +#define BSP_PRV_INT_A_NUM_GPTW4_GTCIB4 93 +#define BSP_PRV_INT_A_NUM_GPTW4_GTCIC4 94 +#define BSP_PRV_INT_A_NUM_GPTW4_GTCID4 95 +#define BSP_PRV_INT_A_NUM_GPTW4_GDTE4 96 +#define BSP_PRV_INT_A_NUM_GPTW4_GTCIE4 97 +#define BSP_PRV_INT_A_NUM_GPTW4_GTCIF4 98 +#define BSP_PRV_INT_A_NUM_GPTW4_GTCIV4 99 +#define BSP_PRV_INT_A_NUM_GPTW4_GTCIU4 100 +#define BSP_PRV_INT_A_NUM_GPTW5_GTCIA5 101 +#define BSP_PRV_INT_A_NUM_GPTW5_GTCIB5 102 +#define BSP_PRV_INT_A_NUM_GPTW5_GTCIC5 103 +#define BSP_PRV_INT_A_NUM_GPTW5_GTCID5 104 +#define BSP_PRV_INT_A_NUM_GPTW5_GDTE5 105 +#define BSP_PRV_INT_A_NUM_GPTW5_GTCIE5 106 +#define BSP_PRV_INT_A_NUM_GPTW5_GTCIF5 107 +#define BSP_PRV_INT_A_NUM_GPTW5_GTCIV5 108 +#define BSP_PRV_INT_A_NUM_GPTW5_GTCIU5 109 +#define BSP_PRV_INT_A_NUM_GPTW6_GTCIA6 110 +#define BSP_PRV_INT_A_NUM_GPTW6_GTCIB6 111 +#define BSP_PRV_INT_A_NUM_GPTW6_GTCIC6 112 +#define BSP_PRV_INT_A_NUM_GPTW6_GTCID6 113 +#define BSP_PRV_INT_A_NUM_GPTW6_GDTE6 114 +#define BSP_PRV_INT_A_NUM_GPTW6_GTCIE6 115 +#define BSP_PRV_INT_A_NUM_GPTW6_GTCIF6 116 +#define BSP_PRV_INT_A_NUM_GPTW6_GTCIV6 117 +#define BSP_PRV_INT_A_NUM_GPTW6_GTCIU6 118 +#define BSP_PRV_INT_A_NUM_GPTW7_GTCIA7 119 +#define BSP_PRV_INT_A_NUM_GPTW7_GTCIB7 120 +#define BSP_PRV_INT_A_NUM_GPTW7_GTCIC7 121 +#define BSP_PRV_INT_A_NUM_GPTW7_GTCID7 122 +#define BSP_PRV_INT_A_NUM_GPTW7_GDTE7 123 +#define BSP_PRV_INT_A_NUM_GPTW7_GTCIE7 124 +#define BSP_PRV_INT_A_NUM_GPTW7_GTCIF7 125 +#define BSP_PRV_INT_A_NUM_GPTW7_GTCIV7 126 +#define BSP_PRV_INT_A_NUM_GPTW7_GTCIU7 127 +#define BSP_PRV_INT_A_NUM_RSPIA0_SPCI 146 +#define BSP_PRV_INT_A_NUM_RSPI0_SPCI0 147 +#define BSP_PRV_INT_A_NUM_RSCI11_AED 151 +#define BSP_PRV_INT_A_NUM_CANFD_EC1EI 152 +#define BSP_PRV_INT_A_NUM_CANFD_EC2EI 153 +#define BSP_PRV_INT_A_NUM_CANFD_ECOVI 154 +#define BSP_PRV_INT_A_NUM_GPTW0_GTCEI0 160 +#define BSP_PRV_INT_A_NUM_GPTW1_GTCEI1 161 +#define BSP_PRV_INT_A_NUM_GPTW2_GTCEI2 162 +#define BSP_PRV_INT_A_NUM_GPTW3_GTCEI3 163 +#define BSP_PRV_INT_A_NUM_GPTW4_GTCEI4 164 +#define BSP_PRV_INT_A_NUM_GPTW5_GTCEI5 165 +#define BSP_PRV_INT_A_NUM_GPTW6_GTCEI6 166 +#define BSP_PRV_INT_A_NUM_GPTW7_GTCEI7 167 + +/* The appropriate macros will now be defined based on the vector selections made by the user. + * These are the same macros that are defined for constant-mapped interrupts (vectors 0-127). This means that the + * code can define, setup, and use mapped interrupts the same as would be done for constant-mapped interrupts. + */ +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IR_MTU1_TGIA1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define DTCE_MTU1_TGIA1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IER_MTU1_TGIA1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IPR_MTU1_TGIA1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define IEN_MTU1_TGIA1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#define VECT_MTU1_TGIA1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIA1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IR_MTU0_TGIA0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define DTCE_MTU0_TGIA0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IER_MTU0_TGIA0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IPR_MTU0_TGIA0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define IEN_MTU0_TGIA0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#define VECT_MTU0_TGIA0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIA0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IR_MTU0_TGIB0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define DTCE_MTU0_TGIB0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IER_MTU0_TGIB0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IPR_MTU0_TGIB0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define IEN_MTU0_TGIB0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#define VECT_MTU0_TGIB0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIB0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IR_MTU0_TGIC0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define DTCE_MTU0_TGIC0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IER_MTU0_TGIC0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IPR_MTU0_TGIC0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define IEN_MTU0_TGIC0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#define VECT_MTU0_TGIC0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIC0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IR_MTU0_TGID0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define DTCE_MTU0_TGID0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IER_MTU0_TGID0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IPR_MTU0_TGID0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define IEN_MTU0_TGID0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#define VECT_MTU0_TGID0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGID0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IR_MTU0_TCIV0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define DTCE_MTU0_TCIV0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IER_MTU0_TCIV0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IPR_MTU0_TCIV0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define IEN_MTU0_TCIV0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#define VECT_MTU0_TCIV0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TCIV0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IR_MTU0_TGIE0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define DTCE_MTU0_TGIE0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IER_MTU0_TGIE0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IPR_MTU0_TGIE0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define IEN_MTU0_TGIE0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#define VECT_MTU0_TGIE0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIE0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IR_MTU0_TGIF0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define DTCE_MTU0_TGIF0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IER_MTU0_TGIF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IPR_MTU0_TGIF0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define IEN_MTU0_TGIF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#define VECT_MTU0_TGIF0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU0_TGIF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IR_MTU1_TGIB1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define DTCE_MTU1_TGIB1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IER_MTU1_TGIB1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IPR_MTU1_TGIB1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define IEN_MTU1_TGIB1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#define VECT_MTU1_TGIB1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TGIB1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IR_MTU1_TCIV1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define DTCE_MTU1_TCIV1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IER_MTU1_TCIV1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IPR_MTU1_TCIV1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define IEN_MTU1_TCIV1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#define VECT_MTU1_TCIV1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIV1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IR_MTU1_TCIU1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define DTCE_MTU1_TCIU1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IER_MTU1_TCIU1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IPR_MTU1_TCIU1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define IEN_MTU1_TCIU1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#define VECT_MTU1_TCIU1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU1_TCIU1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IR_MTU2_TGIA2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define DTCE_MTU2_TGIA2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IER_MTU2_TGIA2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IPR_MTU2_TGIA2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define IEN_MTU2_TGIA2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#define VECT_MTU2_TGIA2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIA2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IR_MTU2_TGIB2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define DTCE_MTU2_TGIB2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IER_MTU2_TGIB2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IPR_MTU2_TGIB2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define IEN_MTU2_TGIB2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#define VECT_MTU2_TGIB2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TGIB2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IR_MTU2_TCIV2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define DTCE_MTU2_TCIV2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IER_MTU2_TCIV2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IPR_MTU2_TCIV2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define IEN_MTU2_TCIV2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#define VECT_MTU2_TCIV2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIV2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IR_MTU2_TCIU2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define DTCE_MTU2_TCIU2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IER_MTU2_TCIU2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IPR_MTU2_TCIU2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define IEN_MTU2_TCIU2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#define VECT_MTU2_TCIU2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU2_TCIU2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IR_MTU3_TGIA3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define DTCE_MTU3_TGIA3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IER_MTU3_TGIA3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IPR_MTU3_TGIA3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define IEN_MTU3_TGIA3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#define VECT_MTU3_TGIA3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIA3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IR_MTU3_TGIB3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define DTCE_MTU3_TGIB3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IER_MTU3_TGIB3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IPR_MTU3_TGIB3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define IEN_MTU3_TGIB3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#define VECT_MTU3_TGIB3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIB3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IR_MTU3_TGIC3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define DTCE_MTU3_TGIC3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IER_MTU3_TGIC3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IPR_MTU3_TGIC3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define IEN_MTU3_TGIC3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#define VECT_MTU3_TGIC3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGIC3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IR_MTU3_TGID3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define DTCE_MTU3_TGID3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IER_MTU3_TGID3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IPR_MTU3_TGID3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define IEN_MTU3_TGID3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#define VECT_MTU3_TGID3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TGID3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IR_MTU3_TCIV3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define DTCE_MTU3_TCIV3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IER_MTU3_TCIV3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IPR_MTU3_TCIV3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define IEN_MTU3_TCIV3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#define VECT_MTU3_TCIV3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU3_TCIV3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IR_MTU4_TGIA4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define DTCE_MTU4_TGIA4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IER_MTU4_TGIA4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IPR_MTU4_TGIA4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define IEN_MTU4_TGIA4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#define VECT_MTU4_TGIA4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIA4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IR_MTU4_TGIB4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define DTCE_MTU4_TGIB4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IER_MTU4_TGIB4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IPR_MTU4_TGIB4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define IEN_MTU4_TGIB4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#define VECT_MTU4_TGIB4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIB4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IR_MTU4_TGIC4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define DTCE_MTU4_TGIC4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IER_MTU4_TGIC4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IPR_MTU4_TGIC4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define IEN_MTU4_TGIC4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#define VECT_MTU4_TGIC4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGIC4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IR_MTU4_TGID4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define DTCE_MTU4_TGID4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IER_MTU4_TGID4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IPR_MTU4_TGID4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define IEN_MTU4_TGID4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#define VECT_MTU4_TGID4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TGID4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IR_MTU4_TCIV4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define DTCE_MTU4_TCIV4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IER_MTU4_TCIV4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IPR_MTU4_TCIV4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define IEN_MTU4_TCIV4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#define VECT_MTU4_TCIV4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU4_TCIV4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IR_MTU5_TGIU5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define DTCE_MTU5_TGIU5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IER_MTU5_TGIU5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IPR_MTU5_TGIU5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define IEN_MTU5_TGIU5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#define VECT_MTU5_TGIU5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIU5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IR_MTU5_TGIV5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define DTCE_MTU5_TGIV5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IER_MTU5_TGIV5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IPR_MTU5_TGIV5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define IEN_MTU5_TGIV5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#define VECT_MTU5_TGIV5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIV5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IR_MTU5_TGIW5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define DTCE_MTU5_TGIW5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IER_MTU5_TGIW5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IPR_MTU5_TGIW5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define IEN_MTU5_TGIW5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#define VECT_MTU5_TGIW5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU5_TGIW5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IR_MTU6_TGIA6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define DTCE_MTU6_TGIA6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IER_MTU6_TGIA6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IPR_MTU6_TGIA6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define IEN_MTU6_TGIA6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#define VECT_MTU6_TGIA6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIA6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IR_MTU6_TGIB6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define DTCE_MTU6_TGIB6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IER_MTU6_TGIB6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IPR_MTU6_TGIB6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define IEN_MTU6_TGIB6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#define VECT_MTU6_TGIB6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIB6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IR_MTU6_TGIC6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define DTCE_MTU6_TGIC6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IER_MTU6_TGIC6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IPR_MTU6_TGIC6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define IEN_MTU6_TGIC6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#define VECT_MTU6_TGIC6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGIC6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IR_MTU6_TGID6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define DTCE_MTU6_TGID6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IER_MTU6_TGID6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IPR_MTU6_TGID6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define IEN_MTU6_TGID6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#define VECT_MTU6_TGID6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TGID6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IR_MTU6_TCIV6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define DTCE_MTU6_TCIV6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IER_MTU6_TCIV6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IPR_MTU6_TCIV6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define IEN_MTU6_TCIV6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#define VECT_MTU6_TCIV6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU6_TCIV6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IR_MTU7_TGIA7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define DTCE_MTU7_TGIA7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IER_MTU7_TGIA7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IPR_MTU7_TGIA7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define IEN_MTU7_TGIA7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#define VECT_MTU7_TGIA7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIA7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IR_MTU7_TGIB7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define DTCE_MTU7_TGIB7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IER_MTU7_TGIB7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IPR_MTU7_TGIB7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define IEN_MTU7_TGIB7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#define VECT_MTU7_TGIB7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIB7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IR_MTU7_TGIC7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define DTCE_MTU7_TGIC7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IER_MTU7_TGIC7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IPR_MTU7_TGIC7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define IEN_MTU7_TGIC7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#define VECT_MTU7_TGIC7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGIC7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IR_MTU7_TGID7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define DTCE_MTU7_TGID7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IER_MTU7_TGID7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IPR_MTU7_TGID7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define IEN_MTU7_TGID7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#define VECT_MTU7_TGID7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TGID7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IR_MTU7_TCIV7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define DTCE_MTU7_TCIV7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IER_MTU7_TCIV7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IPR_MTU7_TCIV7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define IEN_MTU7_TCIV7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#define VECT_MTU7_TCIV7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU7_TCIV7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIA9) +#define IR_MTU9_TGIA9 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIA9) +#define DTCE_MTU9_TGIA9 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIA9) +#define IER_MTU9_TGIA9 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIA9) +#define IPR_MTU9_TGIA9 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIA9) +#define IEN_MTU9_TGIA9 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIA9) +#define VECT_MTU9_TGIA9 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIA9) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIB9) +#define IR_MTU9_TGIB9 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIB9) +#define DTCE_MTU9_TGIB9 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIB9) +#define IER_MTU9_TGIB9 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIB9) +#define IPR_MTU9_TGIB9 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIB9) +#define IEN_MTU9_TGIB9 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIB9) +#define VECT_MTU9_TGIB9 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIB9) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIC9) +#define IR_MTU9_TGIC9 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIC9) +#define DTCE_MTU9_TGIC9 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIC9) +#define IER_MTU9_TGIC9 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIC9) +#define IPR_MTU9_TGIC9 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIC9) +#define IEN_MTU9_TGIC9 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIC9) +#define VECT_MTU9_TGIC9 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIC9) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGID9) +#define IR_MTU9_TGID9 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGID9) +#define DTCE_MTU9_TGID9 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGID9) +#define IER_MTU9_TGID9 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGID9) +#define IPR_MTU9_TGID9 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGID9) +#define IEN_MTU9_TGID9 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGID9) +#define VECT_MTU9_TGID9 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGID9) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TCIV9) +#define IR_MTU9_TCIV9 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TCIV9) +#define DTCE_MTU9_TCIV9 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TCIV9) +#define IER_MTU9_TCIV9 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TCIV9) +#define IPR_MTU9_TCIV9 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TCIV9) +#define IEN_MTU9_TCIV9 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TCIV9) +#define VECT_MTU9_TCIV9 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TCIV9) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIE9) +#define IR_MTU9_TGIE9 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIE9) +#define DTCE_MTU9_TGIE9 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIE9) +#define IER_MTU9_TGIE9 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIE9) +#define IPR_MTU9_TGIE9 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIE9) +#define IEN_MTU9_TGIE9 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIE9) +#define VECT_MTU9_TGIE9 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIE9) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIF9) +#define IR_MTU9_TGIF9 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIF9) +#define DTCE_MTU9_TGIF9 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIF9) +#define IER_MTU9_TGIF9 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIF9) +#define IPR_MTU9_TGIF9 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIF9) +#define IEN_MTU9_TGIF9 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIF9) +#define VECT_MTU9_TGIF9 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_MTU9_TGIF9) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IR_GPTW0_GTCIA0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define DTCE_GPTW0_GTCIA0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IER_GPTW0_GTCIA0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IPR_GPTW0_GTCIA0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define IEN_GPTW0_GTCIA0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#define VECT_GPTW0_GTCIA0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIA0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IR_GPTW0_GTCIB0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define DTCE_GPTW0_GTCIB0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IER_GPTW0_GTCIB0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IPR_GPTW0_GTCIB0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define IEN_GPTW0_GTCIB0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#define VECT_GPTW0_GTCIB0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIB0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IR_GPTW0_GTCIC0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define DTCE_GPTW0_GTCIC0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IER_GPTW0_GTCIC0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IPR_GPTW0_GTCIC0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define IEN_GPTW0_GTCIC0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#define VECT_GPTW0_GTCIC0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIC0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IR_GPTW0_GTCID0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define DTCE_GPTW0_GTCID0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IER_GPTW0_GTCID0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IPR_GPTW0_GTCID0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define IEN_GPTW0_GTCID0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#define VECT_GPTW0_GTCID0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCID0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IR_GPTW0_GDTE0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define DTCE_GPTW0_GDTE0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IER_GPTW0_GDTE0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IPR_GPTW0_GDTE0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define IEN_GPTW0_GDTE0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#define VECT_GPTW0_GDTE0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GDTE0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IR_GPTW0_GTCIE0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define DTCE_GPTW0_GTCIE0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IER_GPTW0_GTCIE0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IPR_GPTW0_GTCIE0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define IEN_GPTW0_GTCIE0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#define VECT_GPTW0_GTCIE0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIE0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IR_GPTW0_GTCIF0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define DTCE_GPTW0_GTCIF0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IER_GPTW0_GTCIF0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IPR_GPTW0_GTCIF0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define IEN_GPTW0_GTCIF0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#define VECT_GPTW0_GTCIF0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIF0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IR_GPTW0_GTCIV0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define DTCE_GPTW0_GTCIV0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IER_GPTW0_GTCIV0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IPR_GPTW0_GTCIV0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define IEN_GPTW0_GTCIV0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#define VECT_GPTW0_GTCIV0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIV0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IR_GPTW0_GTCIU0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define DTCE_GPTW0_GTCIU0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IER_GPTW0_GTCIU0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IPR_GPTW0_GTCIU0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define IEN_GPTW0_GTCIU0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#define VECT_GPTW0_GTCIU0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCIU0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IR_GPTW1_GTCIA1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define DTCE_GPTW1_GTCIA1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IER_GPTW1_GTCIA1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IPR_GPTW1_GTCIA1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define IEN_GPTW1_GTCIA1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#define VECT_GPTW1_GTCIA1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIA1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IR_GPTW1_GTCIB1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define DTCE_GPTW1_GTCIB1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IER_GPTW1_GTCIB1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IPR_GPTW1_GTCIB1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define IEN_GPTW1_GTCIB1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#define VECT_GPTW1_GTCIB1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIB1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IR_GPTW1_GTCIC1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define DTCE_GPTW1_GTCIC1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IER_GPTW1_GTCIC1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IPR_GPTW1_GTCIC1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define IEN_GPTW1_GTCIC1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#define VECT_GPTW1_GTCIC1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIC1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IR_GPTW1_GTCID1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define DTCE_GPTW1_GTCID1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IER_GPTW1_GTCID1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IPR_GPTW1_GTCID1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define IEN_GPTW1_GTCID1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#define VECT_GPTW1_GTCID1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCID1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IR_GPTW1_GDTE1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define DTCE_GPTW1_GDTE1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IER_GPTW1_GDTE1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IPR_GPTW1_GDTE1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define IEN_GPTW1_GDTE1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#define VECT_GPTW1_GDTE1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GDTE1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IR_GPTW1_GTCIE1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define DTCE_GPTW1_GTCIE1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IER_GPTW1_GTCIE1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IPR_GPTW1_GTCIE1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define IEN_GPTW1_GTCIE1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#define VECT_GPTW1_GTCIE1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIE1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IR_GPTW1_GTCIF1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define DTCE_GPTW1_GTCIF1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IER_GPTW1_GTCIF1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IPR_GPTW1_GTCIF1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define IEN_GPTW1_GTCIF1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#define VECT_GPTW1_GTCIF1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIF1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IR_GPTW1_GTCIV1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define DTCE_GPTW1_GTCIV1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IER_GPTW1_GTCIV1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IPR_GPTW1_GTCIV1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define IEN_GPTW1_GTCIV1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#define VECT_GPTW1_GTCIV1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIV1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IR_GPTW1_GTCIU1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define DTCE_GPTW1_GTCIU1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IER_GPTW1_GTCIU1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IPR_GPTW1_GTCIU1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define IEN_GPTW1_GTCIU1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#define VECT_GPTW1_GTCIU1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCIU1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IR_GPTW2_GTCIA2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define DTCE_GPTW2_GTCIA2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IER_GPTW2_GTCIA2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IPR_GPTW2_GTCIA2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define IEN_GPTW2_GTCIA2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#define VECT_GPTW2_GTCIA2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIA2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IR_GPTW2_GTCIB2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define DTCE_GPTW2_GTCIB2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IER_GPTW2_GTCIB2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IPR_GPTW2_GTCIB2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define IEN_GPTW2_GTCIB2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#define VECT_GPTW2_GTCIB2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIB2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IR_GPTW2_GTCIC2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define DTCE_GPTW2_GTCIC2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IER_GPTW2_GTCIC2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IPR_GPTW2_GTCIC2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define IEN_GPTW2_GTCIC2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#define VECT_GPTW2_GTCIC2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIC2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IR_GPTW2_GTCID2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define DTCE_GPTW2_GTCID2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IER_GPTW2_GTCID2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IPR_GPTW2_GTCID2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define IEN_GPTW2_GTCID2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#define VECT_GPTW2_GTCID2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCID2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IR_GPTW2_GDTE2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define DTCE_GPTW2_GDTE2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IER_GPTW2_GDTE2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IPR_GPTW2_GDTE2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define IEN_GPTW2_GDTE2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#define VECT_GPTW2_GDTE2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GDTE2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IR_GPTW2_GTCIE2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define DTCE_GPTW2_GTCIE2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IER_GPTW2_GTCIE2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IPR_GPTW2_GTCIE2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define IEN_GPTW2_GTCIE2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#define VECT_GPTW2_GTCIE2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIE2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IR_GPTW2_GTCIF2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define DTCE_GPTW2_GTCIF2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IER_GPTW2_GTCIF2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IPR_GPTW2_GTCIF2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define IEN_GPTW2_GTCIF2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#define VECT_GPTW2_GTCIF2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIF2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IR_GPTW2_GTCIV2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define DTCE_GPTW2_GTCIV2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IER_GPTW2_GTCIV2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IPR_GPTW2_GTCIV2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define IEN_GPTW2_GTCIV2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#define VECT_GPTW2_GTCIV2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIV2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IR_GPTW2_GTCIU2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define DTCE_GPTW2_GTCIU2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IER_GPTW2_GTCIU2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IPR_GPTW2_GTCIU2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define IEN_GPTW2_GTCIU2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#define VECT_GPTW2_GTCIU2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCIU2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IR_GPTW3_GTCIA3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define DTCE_GPTW3_GTCIA3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IER_GPTW3_GTCIA3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IPR_GPTW3_GTCIA3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define IEN_GPTW3_GTCIA3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#define VECT_GPTW3_GTCIA3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIA3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IR_GPTW3_GTCIB3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define DTCE_GPTW3_GTCIB3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IER_GPTW3_GTCIB3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IPR_GPTW3_GTCIB3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define IEN_GPTW3_GTCIB3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#define VECT_GPTW3_GTCIB3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIB3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IR_GPTW3_GTCIC3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define DTCE_GPTW3_GTCIC3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IER_GPTW3_GTCIC3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IPR_GPTW3_GTCIC3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define IEN_GPTW3_GTCIC3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#define VECT_GPTW3_GTCIC3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIC3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IR_GPTW3_GTCID3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define DTCE_GPTW3_GTCID3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IER_GPTW3_GTCID3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IPR_GPTW3_GTCID3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define IEN_GPTW3_GTCID3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#define VECT_GPTW3_GTCID3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCID3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IR_GPTW3_GDTE3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define DTCE_GPTW3_GDTE3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IER_GPTW3_GDTE3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IPR_GPTW3_GDTE3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define IEN_GPTW3_GDTE3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#define VECT_GPTW3_GDTE3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GDTE3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IR_GPTW3_GTCIE3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define DTCE_GPTW3_GTCIE3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IER_GPTW3_GTCIE3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IPR_GPTW3_GTCIE3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define IEN_GPTW3_GTCIE3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#define VECT_GPTW3_GTCIE3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIE3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IR_GPTW3_GTCIF3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define DTCE_GPTW3_GTCIF3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IER_GPTW3_GTCIF3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IPR_GPTW3_GTCIF3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define IEN_GPTW3_GTCIF3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#define VECT_GPTW3_GTCIF3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIF3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IR_GPTW3_GTCIV3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define DTCE_GPTW3_GTCIV3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IER_GPTW3_GTCIV3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IPR_GPTW3_GTCIV3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define IEN_GPTW3_GTCIV3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#define VECT_GPTW3_GTCIV3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIV3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IR_GPTW3_GTCIU3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define DTCE_GPTW3_GTCIU3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IER_GPTW3_GTCIU3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IPR_GPTW3_GTCIU3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define IEN_GPTW3_GTCIU3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#define VECT_GPTW3_GTCIU3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCIU3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIA4) +#define IR_GPTW4_GTCIA4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIA4) +#define DTCE_GPTW4_GTCIA4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIA4) +#define IER_GPTW4_GTCIA4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIA4) +#define IPR_GPTW4_GTCIA4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIA4) +#define IEN_GPTW4_GTCIA4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIA4) +#define VECT_GPTW4_GTCIA4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIA4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIB4) +#define IR_GPTW4_GTCIB4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIB4) +#define DTCE_GPTW4_GTCIB4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIB4) +#define IER_GPTW4_GTCIB4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIB4) +#define IPR_GPTW4_GTCIB4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIB4) +#define IEN_GPTW4_GTCIB4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIB4) +#define VECT_GPTW4_GTCIB4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIB4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIC4) +#define IR_GPTW4_GTCIC4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIC4) +#define DTCE_GPTW4_GTCIC4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIC4) +#define IER_GPTW4_GTCIC4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIC4) +#define IPR_GPTW4_GTCIC4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIC4) +#define IEN_GPTW4_GTCIC4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIC4) +#define VECT_GPTW4_GTCIC4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIC4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCID4) +#define IR_GPTW4_GTCID4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCID4) +#define DTCE_GPTW4_GTCID4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCID4) +#define IER_GPTW4_GTCID4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCID4) +#define IPR_GPTW4_GTCID4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCID4) +#define IEN_GPTW4_GTCID4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCID4) +#define VECT_GPTW4_GTCID4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCID4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GDTE4) +#define IR_GPTW4_GDTE4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GDTE4) +#define DTCE_GPTW4_GDTE4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GDTE4) +#define IER_GPTW4_GDTE4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GDTE4) +#define IPR_GPTW4_GDTE4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GDTE4) +#define IEN_GPTW4_GDTE4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GDTE4) +#define VECT_GPTW4_GDTE4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GDTE4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIE4) +#define IR_GPTW4_GTCIE4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIE4) +#define DTCE_GPTW4_GTCIE4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIE4) +#define IER_GPTW4_GTCIE4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIE4) +#define IPR_GPTW4_GTCIE4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIE4) +#define IEN_GPTW4_GTCIE4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIE4) +#define VECT_GPTW4_GTCIE4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIE4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIF4) +#define IR_GPTW4_GTCIF4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIF4) +#define DTCE_GPTW4_GTCIF4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIF4) +#define IER_GPTW4_GTCIF4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIF4) +#define IPR_GPTW4_GTCIF4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIF4) +#define IEN_GPTW4_GTCIF4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIF4) +#define VECT_GPTW4_GTCIF4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIF4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIV4) +#define IR_GPTW4_GTCIV4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIV4) +#define DTCE_GPTW4_GTCIV4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIV4) +#define IER_GPTW4_GTCIV4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIV4) +#define IPR_GPTW4_GTCIV4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIV4) +#define IEN_GPTW4_GTCIV4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIV4) +#define VECT_GPTW4_GTCIV4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIV4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIU4) +#define IR_GPTW4_GTCIU4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIU4) +#define DTCE_GPTW4_GTCIU4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIU4) +#define IER_GPTW4_GTCIU4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIU4) +#define IPR_GPTW4_GTCIU4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIU4) +#define IEN_GPTW4_GTCIU4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIU4) +#define VECT_GPTW4_GTCIU4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCIU4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIA5) +#define IR_GPTW5_GTCIA5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIA5) +#define DTCE_GPTW5_GTCIA5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIA5) +#define IER_GPTW5_GTCIA5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIA5) +#define IPR_GPTW5_GTCIA5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIA5) +#define IEN_GPTW5_GTCIA5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIA5) +#define VECT_GPTW5_GTCIA5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIA5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIB5) +#define IR_GPTW5_GTCIB5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIB5) +#define DTCE_GPTW5_GTCIB5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIB5) +#define IER_GPTW5_GTCIB5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIB5) +#define IPR_GPTW5_GTCIB5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIB5) +#define IEN_GPTW5_GTCIB5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIB5) +#define VECT_GPTW5_GTCIB5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIB5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIC5) +#define IR_GPTW5_GTCIC5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIC5) +#define DTCE_GPTW5_GTCIC5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIC5) +#define IER_GPTW5_GTCIC5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIC5) +#define IPR_GPTW5_GTCIC5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIC5) +#define IEN_GPTW5_GTCIC5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIC5) +#define VECT_GPTW5_GTCIC5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIC5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCID5) +#define IR_GPTW5_GTCID5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCID5) +#define DTCE_GPTW5_GTCID5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCID5) +#define IER_GPTW5_GTCID5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCID5) +#define IPR_GPTW5_GTCID5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCID5) +#define IEN_GPTW5_GTCID5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCID5) +#define VECT_GPTW5_GTCID5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCID5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GDTE5) +#define IR_GPTW5_GDTE5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GDTE5) +#define DTCE_GPTW5_GDTE5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GDTE5) +#define IER_GPTW5_GDTE5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GDTE5) +#define IPR_GPTW5_GDTE5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GDTE5) +#define IEN_GPTW5_GDTE5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GDTE5) +#define VECT_GPTW5_GDTE5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GDTE5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIE5) +#define IR_GPTW5_GTCIE5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIE5) +#define DTCE_GPTW5_GTCIE5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIE5) +#define IER_GPTW5_GTCIE5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIE5) +#define IPR_GPTW5_GTCIE5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIE5) +#define IEN_GPTW5_GTCIE5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIE5) +#define VECT_GPTW5_GTCIE5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIE5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIF5) +#define IR_GPTW5_GTCIF5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIF5) +#define DTCE_GPTW5_GTCIF5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIF5) +#define IER_GPTW5_GTCIF5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIF5) +#define IPR_GPTW5_GTCIF5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIF5) +#define IEN_GPTW5_GTCIF5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIF5) +#define VECT_GPTW5_GTCIF5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIF5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIV5) +#define IR_GPTW5_GTCIV5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIV5) +#define DTCE_GPTW5_GTCIV5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIV5) +#define IER_GPTW5_GTCIV5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIV5) +#define IPR_GPTW5_GTCIV5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIV5) +#define IEN_GPTW5_GTCIV5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIV5) +#define VECT_GPTW5_GTCIV5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIV5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIU5) +#define IR_GPTW5_GTCIU5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIU5) +#define DTCE_GPTW5_GTCIU5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIU5) +#define IER_GPTW5_GTCIU5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIU5) +#define IPR_GPTW5_GTCIU5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIU5) +#define IEN_GPTW5_GTCIU5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIU5) +#define VECT_GPTW5_GTCIU5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCIU5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIA6) +#define IR_GPTW6_GTCIA6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIA6) +#define DTCE_GPTW6_GTCIA6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIA6) +#define IER_GPTW6_GTCIA6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIA6) +#define IPR_GPTW6_GTCIA6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIA6) +#define IEN_GPTW6_GTCIA6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIA6) +#define VECT_GPTW6_GTCIA6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIA6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIB6) +#define IR_GPTW6_GTCIB6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIB6) +#define DTCE_GPTW6_GTCIB6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIB6) +#define IER_GPTW6_GTCIB6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIB6) +#define IPR_GPTW6_GTCIB6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIB6) +#define IEN_GPTW6_GTCIB6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIB6) +#define VECT_GPTW6_GTCIB6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIB6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIC6) +#define IR_GPTW6_GTCIC6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIC6) +#define DTCE_GPTW6_GTCIC6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIC6) +#define IER_GPTW6_GTCIC6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIC6) +#define IPR_GPTW6_GTCIC6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIC6) +#define IEN_GPTW6_GTCIC6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIC6) +#define VECT_GPTW6_GTCIC6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIC6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCID6) +#define IR_GPTW6_GTCID6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCID6) +#define DTCE_GPTW6_GTCID6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCID6) +#define IER_GPTW6_GTCID6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCID6) +#define IPR_GPTW6_GTCID6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCID6) +#define IEN_GPTW6_GTCID6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCID6) +#define VECT_GPTW6_GTCID6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCID6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GDTE6) +#define IR_GPTW6_GDTE6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GDTE6) +#define DTCE_GPTW6_GDTE6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GDTE6) +#define IER_GPTW6_GDTE6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GDTE6) +#define IPR_GPTW6_GDTE6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GDTE6) +#define IEN_GPTW6_GDTE6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GDTE6) +#define VECT_GPTW6_GDTE6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GDTE6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIE6) +#define IR_GPTW6_GTCIE6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIE6) +#define DTCE_GPTW6_GTCIE6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIE6) +#define IER_GPTW6_GTCIE6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIE6) +#define IPR_GPTW6_GTCIE6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIE6) +#define IEN_GPTW6_GTCIE6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIE6) +#define VECT_GPTW6_GTCIE6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIE6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIF6) +#define IR_GPTW6_GTCIF6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIF6) +#define DTCE_GPTW6_GTCIF6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIF6) +#define IER_GPTW6_GTCIF6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIF6) +#define IPR_GPTW6_GTCIF6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIF6) +#define IEN_GPTW6_GTCIF6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIF6) +#define VECT_GPTW6_GTCIF6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIF6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIV6) +#define IR_GPTW6_GTCIV6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIV6) +#define DTCE_GPTW6_GTCIV6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIV6) +#define IER_GPTW6_GTCIV6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIV6) +#define IPR_GPTW6_GTCIV6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIV6) +#define IEN_GPTW6_GTCIV6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIV6) +#define VECT_GPTW6_GTCIV6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIV6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIU6) +#define IR_GPTW6_GTCIU6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIU6) +#define DTCE_GPTW6_GTCIU6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIU6) +#define IER_GPTW6_GTCIU6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIU6) +#define IPR_GPTW6_GTCIU6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIU6) +#define IEN_GPTW6_GTCIU6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIU6) +#define VECT_GPTW6_GTCIU6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCIU6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIA7) +#define IR_GPTW7_GTCIA7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIA7) +#define DTCE_GPTW7_GTCIA7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIA7) +#define IER_GPTW7_GTCIA7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIA7) +#define IPR_GPTW7_GTCIA7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIA7) +#define IEN_GPTW7_GTCIA7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIA7) +#define VECT_GPTW7_GTCIA7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIA7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIB7) +#define IR_GPTW7_GTCIB7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIB7) +#define DTCE_GPTW7_GTCIB7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIB7) +#define IER_GPTW7_GTCIB7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIB7) +#define IPR_GPTW7_GTCIB7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIB7) +#define IEN_GPTW7_GTCIB7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIB7) +#define VECT_GPTW7_GTCIB7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIB7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIC7) +#define IR_GPTW7_GTCIC7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIC7) +#define DTCE_GPTW7_GTCIC7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIC7) +#define IER_GPTW7_GTCIC7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIC7) +#define IPR_GPTW7_GTCIC7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIC7) +#define IEN_GPTW7_GTCIC7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIC7) +#define VECT_GPTW7_GTCIC7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIC7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCID7) +#define IR_GPTW7_GTCID7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCID7) +#define DTCE_GPTW7_GTCID7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCID7) +#define IER_GPTW7_GTCID7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCID7) +#define IPR_GPTW7_GTCID7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCID7) +#define IEN_GPTW7_GTCID7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCID7) +#define VECT_GPTW7_GTCID7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCID7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GDTE7) +#define IR_GPTW7_GDTE7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GDTE7) +#define DTCE_GPTW7_GDTE7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GDTE7) +#define IER_GPTW7_GDTE7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GDTE7) +#define IPR_GPTW7_GDTE7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GDTE7) +#define IEN_GPTW7_GDTE7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GDTE7) +#define VECT_GPTW7_GDTE7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GDTE7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIE7) +#define IR_GPTW7_GTCIE7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIE7) +#define DTCE_GPTW7_GTCIE7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIE7) +#define IER_GPTW7_GTCIE7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIE7) +#define IPR_GPTW7_GTCIE7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIE7) +#define IEN_GPTW7_GTCIE7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIE7) +#define VECT_GPTW7_GTCIE7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIE7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIF7) +#define IR_GPTW7_GTCIF7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIF7) +#define DTCE_GPTW7_GTCIF7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIF7) +#define IER_GPTW7_GTCIF7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIF7) +#define IPR_GPTW7_GTCIF7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIF7) +#define IEN_GPTW7_GTCIF7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIF7) +#define VECT_GPTW7_GTCIF7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIF7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIV7) +#define IR_GPTW7_GTCIV7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIV7) +#define DTCE_GPTW7_GTCIV7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIV7) +#define IER_GPTW7_GTCIV7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIV7) +#define IPR_GPTW7_GTCIV7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIV7) +#define IEN_GPTW7_GTCIV7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIV7) +#define VECT_GPTW7_GTCIV7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIV7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIU7) +#define IR_GPTW7_GTCIU7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIU7) +#define DTCE_GPTW7_GTCIU7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIU7) +#define IER_GPTW7_GTCIU7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIU7) +#define IPR_GPTW7_GTCIU7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIU7) +#define IEN_GPTW7_GTCIU7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIU7) +#define VECT_GPTW7_GTCIU7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCIU7) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_RSPIA0_SPCI) +#define IR_RSPIA0_SPCI BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSPIA0_SPCI) +#define DTCE_RSPIA0_SPCI BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSPIA0_SPCI) +#define IER_RSPIA0_SPCI BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_RSPIA0_SPCI) +#define IPR_RSPIA0_SPCI BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSPIA0_SPCI) +#define IEN_RSPIA0_SPCI BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_RSPIA0_SPCI) +#define VECT_RSPIA0_SPCI BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSPIA0_SPCI) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_RSPI0_SPCI0) +#define IR_RSPI0_SPCI0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSPI0_SPCI0) +#define DTCE_RSPI0_SPCI0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSPI0_SPCI0) +#define IER_RSPI0_SPCI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_RSPI0_SPCI0) +#define IPR_RSPI0_SPCI0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSPI0_SPCI0) +#define IEN_RSPI0_SPCI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_RSPI0_SPCI0) +#define VECT_RSPI0_SPCI0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSPI0_SPCI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_RSCI11_AED) +#define IR_RSCI11_AED BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSCI11_AED) +#define DTCE_RSCI11_AED BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSCI11_AED) +#define IER_RSCI11_AED BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_RSCI11_AED) +#define IPR_RSCI11_AED BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSCI11_AED) +#define IEN_RSCI11_AED BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_RSCI11_AED) +#define VECT_RSCI11_AED BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_RSCI11_AED) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC1EI) +#define IR_CANFD_EC1EI BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC1EI) +#define DTCE_CANFD_EC1EI BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC1EI) +#define IER_CANFD_EC1EI BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC1EI) +#define IPR_CANFD_EC1EI BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC1EI) +#define IEN_CANFD_EC1EI BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC1EI) +#define VECT_CANFD_EC1EI BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC1EI) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC2EI) +#define IR_CANFD_EC2EI BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC2EI) +#define DTCE_CANFD_EC2EI BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC2EI) +#define IER_CANFD_EC2EI BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC2EI) +#define IPR_CANFD_EC2EI BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC2EI) +#define IEN_CANFD_EC2EI BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC2EI) +#define VECT_CANFD_EC2EI BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_EC2EI) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_ECOVI) +#define IR_CANFD_ECOVI BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_ECOVI) +#define DTCE_CANFD_ECOVI BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_ECOVI) +#define IER_CANFD_ECOVI BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_CANFD_ECOVI) +#define IPR_CANFD_ECOVI BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_ECOVI) +#define IEN_CANFD_ECOVI BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_CANFD_ECOVI) +#define VECT_CANFD_ECOVI BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_CANFD_ECOVI) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCEI0) +#define IR_GPTW0_GTCEI0 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCEI0) +#define DTCE_GPTW0_GTCEI0 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCEI0) +#define IER_GPTW0_GTCEI0 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCEI0) +#define IPR_GPTW0_GTCEI0 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCEI0) +#define IEN_GPTW0_GTCEI0 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCEI0) +#define VECT_GPTW0_GTCEI0 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW0_GTCEI0) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCEI1) +#define IR_GPTW1_GTCEI1 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCEI1) +#define DTCE_GPTW1_GTCEI1 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCEI1) +#define IER_GPTW1_GTCEI1 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCEI1) +#define IPR_GPTW1_GTCEI1 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCEI1) +#define IEN_GPTW1_GTCEI1 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCEI1) +#define VECT_GPTW1_GTCEI1 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW1_GTCEI1) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCEI2) +#define IR_GPTW2_GTCEI2 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCEI2) +#define DTCE_GPTW2_GTCEI2 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCEI2) +#define IER_GPTW2_GTCEI2 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCEI2) +#define IPR_GPTW2_GTCEI2 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCEI2) +#define IEN_GPTW2_GTCEI2 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCEI2) +#define VECT_GPTW2_GTCEI2 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW2_GTCEI2) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCEI3) +#define IR_GPTW3_GTCEI3 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCEI3) +#define DTCE_GPTW3_GTCEI3 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCEI3) +#define IER_GPTW3_GTCEI3 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCEI3) +#define IPR_GPTW3_GTCEI3 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCEI3) +#define IEN_GPTW3_GTCEI3 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCEI3) +#define VECT_GPTW3_GTCEI3 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW3_GTCEI3) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCEI4) +#define IR_GPTW4_GTCEI4 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCEI4) +#define DTCE_GPTW4_GTCEI4 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCEI4) +#define IER_GPTW4_GTCEI4 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCEI4) +#define IPR_GPTW4_GTCEI4 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCEI4) +#define IEN_GPTW4_GTCEI4 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCEI4) +#define VECT_GPTW4_GTCEI4 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW4_GTCEI4) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCEI5) +#define IR_GPTW5_GTCEI5 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCEI5) +#define DTCE_GPTW5_GTCEI5 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCEI5) +#define IER_GPTW5_GTCEI5 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCEI5) +#define IPR_GPTW5_GTCEI5 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCEI5) +#define IEN_GPTW5_GTCEI5 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCEI5) +#define VECT_GPTW5_GTCEI5 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW5_GTCEI5) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCEI6) +#define IR_GPTW6_GTCEI6 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCEI6) +#define DTCE_GPTW6_GTCEI6 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCEI6) +#define IER_GPTW6_GTCEI6 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCEI6) +#define IPR_GPTW6_GTCEI6 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCEI6) +#define IEN_GPTW6_GTCEI6 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCEI6) +#define VECT_GPTW6_GTCEI6 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW6_GTCEI6) +#endif + +#if BSP_PRV_VALID_MAP_INT(A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCEI7) +#define IR_GPTW7_GTCEI7 BSP_PRV_IR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCEI7) +#define DTCE_GPTW7_GTCEI7 BSP_PRV_DTCE(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCEI7) +#define IER_GPTW7_GTCEI7 BSP_PRIV_CALC_IER_REG(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCEI7) +#define IPR_GPTW7_GTCEI7 BSP_PRV_IPR(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCEI7) +#define IEN_GPTW7_GTCEI7 BSP_PRV_IEN(BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCEI7) +#define VECT_GPTW7_GTCEI7 BSP_PRV_VECT(BSP_PRV_A, BSP_MAPPED_INT_CFG_A_VECT_GPTW7_GTCEI7) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void bsp_mapped_interrupt_open(void); //r_bsp internal function. DO NOT CALL. + +#endif /* MCU_MAPPED_INTERRUPTS_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_mapped_interrupts_private.h b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_mapped_interrupts_private.h new file mode 100644 index 00000000..fccd1718 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_mapped_interrupts_private.h @@ -0,0 +1,182 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_mapped_interrupts_private.h +* Description : This module contains macros used for mapping interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 26.02.2025 1.01 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_MAPPED_INTERRUPTS_PRIVATE_H +#define MCU_MAPPED_INTERRUPTS_PRIVATE_H + +/* These macros are calculated values for x % 8. These macros are used when preprocessor arithmetic cannot be used. + * For example, 'IEN0'-'IEN7' needs to be defined for a macro based on 'vector_number % 8' but preprocessor arithmetic + * is only evaluated at compile-time when it is used in a preprocessor conditional. For this reason the calculated + * value of 'vector_number % 8' must be calculated before compile-time. + */ +#define BSP_PRV_CALC_208_MOD_8 0 +#define BSP_PRV_CALC_209_MOD_8 1 +#define BSP_PRV_CALC_210_MOD_8 2 +#define BSP_PRV_CALC_211_MOD_8 3 +#define BSP_PRV_CALC_212_MOD_8 4 +#define BSP_PRV_CALC_213_MOD_8 5 +#define BSP_PRV_CALC_214_MOD_8 6 +#define BSP_PRV_CALC_215_MOD_8 7 +#define BSP_PRV_CALC_216_MOD_8 0 +#define BSP_PRV_CALC_217_MOD_8 1 +#define BSP_PRV_CALC_218_MOD_8 2 +#define BSP_PRV_CALC_219_MOD_8 3 +#define BSP_PRV_CALC_220_MOD_8 4 +#define BSP_PRV_CALC_221_MOD_8 5 +#define BSP_PRV_CALC_222_MOD_8 6 +#define BSP_PRV_CALC_223_MOD_8 7 +#define BSP_PRV_CALC_224_MOD_8 0 +#define BSP_PRV_CALC_225_MOD_8 1 +#define BSP_PRV_CALC_226_MOD_8 2 +#define BSP_PRV_CALC_227_MOD_8 3 +#define BSP_PRV_CALC_228_MOD_8 4 +#define BSP_PRV_CALC_229_MOD_8 5 +#define BSP_PRV_CALC_230_MOD_8 6 +#define BSP_PRV_CALC_231_MOD_8 7 +#define BSP_PRV_CALC_232_MOD_8 0 +#define BSP_PRV_CALC_233_MOD_8 1 +#define BSP_PRV_CALC_234_MOD_8 2 +#define BSP_PRV_CALC_235_MOD_8 3 +#define BSP_PRV_CALC_236_MOD_8 4 +#define BSP_PRV_CALC_237_MOD_8 5 +#define BSP_PRV_CALC_238_MOD_8 6 +#define BSP_PRV_CALC_239_MOD_8 7 +#define BSP_PRV_CALC_240_MOD_8 0 +#define BSP_PRV_CALC_241_MOD_8 1 +#define BSP_PRV_CALC_242_MOD_8 2 +#define BSP_PRV_CALC_243_MOD_8 3 +#define BSP_PRV_CALC_244_MOD_8 4 +#define BSP_PRV_CALC_245_MOD_8 5 +#define BSP_PRV_CALC_246_MOD_8 6 +#define BSP_PRV_CALC_247_MOD_8 7 +#define BSP_PRV_CALC_248_MOD_8 0 +#define BSP_PRV_CALC_249_MOD_8 1 +#define BSP_PRV_CALC_250_MOD_8 2 +#define BSP_PRV_CALC_251_MOD_8 3 +#define BSP_PRV_CALC_252_MOD_8 4 +#define BSP_PRV_CALC_253_MOD_8 5 +#define BSP_PRV_CALC_254_MOD_8 6 +#define BSP_PRV_CALC_255_MOD_8 7 + +/* Interrupt A interrupts are also defined even though there is only 1 select register. */ +#define BSP_PRV_INT_A_SELECT_208 ICU.SLIAR208.BYTE +#define BSP_PRV_INT_A_SELECT_209 ICU.SLIAR209.BYTE +#define BSP_PRV_INT_A_SELECT_210 ICU.SLIAR210.BYTE +#define BSP_PRV_INT_A_SELECT_211 ICU.SLIAR211.BYTE +#define BSP_PRV_INT_A_SELECT_212 ICU.SLIAR212.BYTE +#define BSP_PRV_INT_A_SELECT_213 ICU.SLIAR213.BYTE +#define BSP_PRV_INT_A_SELECT_214 ICU.SLIAR214.BYTE +#define BSP_PRV_INT_A_SELECT_215 ICU.SLIAR215.BYTE +#define BSP_PRV_INT_A_SELECT_216 ICU.SLIAR216.BYTE +#define BSP_PRV_INT_A_SELECT_217 ICU.SLIAR217.BYTE +#define BSP_PRV_INT_A_SELECT_218 ICU.SLIAR218.BYTE +#define BSP_PRV_INT_A_SELECT_219 ICU.SLIAR219.BYTE +#define BSP_PRV_INT_A_SELECT_220 ICU.SLIAR220.BYTE +#define BSP_PRV_INT_A_SELECT_221 ICU.SLIAR221.BYTE +#define BSP_PRV_INT_A_SELECT_222 ICU.SLIAR222.BYTE +#define BSP_PRV_INT_A_SELECT_223 ICU.SLIAR223.BYTE +#define BSP_PRV_INT_A_SELECT_224 ICU.SLIAR224.BYTE +#define BSP_PRV_INT_A_SELECT_225 ICU.SLIAR225.BYTE +#define BSP_PRV_INT_A_SELECT_226 ICU.SLIAR226.BYTE +#define BSP_PRV_INT_A_SELECT_227 ICU.SLIAR227.BYTE +#define BSP_PRV_INT_A_SELECT_228 ICU.SLIAR228.BYTE +#define BSP_PRV_INT_A_SELECT_229 ICU.SLIAR229.BYTE +#define BSP_PRV_INT_A_SELECT_230 ICU.SLIAR230.BYTE +#define BSP_PRV_INT_A_SELECT_231 ICU.SLIAR231.BYTE +#define BSP_PRV_INT_A_SELECT_232 ICU.SLIAR232.BYTE +#define BSP_PRV_INT_A_SELECT_233 ICU.SLIAR233.BYTE +#define BSP_PRV_INT_A_SELECT_234 ICU.SLIAR234.BYTE +#define BSP_PRV_INT_A_SELECT_235 ICU.SLIAR235.BYTE +#define BSP_PRV_INT_A_SELECT_236 ICU.SLIAR236.BYTE +#define BSP_PRV_INT_A_SELECT_237 ICU.SLIAR237.BYTE +#define BSP_PRV_INT_A_SELECT_238 ICU.SLIAR238.BYTE +#define BSP_PRV_INT_A_SELECT_239 ICU.SLIAR239.BYTE +#define BSP_PRV_INT_A_SELECT_240 ICU.SLIAR240.BYTE +#define BSP_PRV_INT_A_SELECT_241 ICU.SLIAR241.BYTE +#define BSP_PRV_INT_A_SELECT_242 ICU.SLIAR242.BYTE +#define BSP_PRV_INT_A_SELECT_243 ICU.SLIAR243.BYTE +#define BSP_PRV_INT_A_SELECT_244 ICU.SLIAR244.BYTE +#define BSP_PRV_INT_A_SELECT_245 ICU.SLIAR245.BYTE +#define BSP_PRV_INT_A_SELECT_246 ICU.SLIAR246.BYTE +#define BSP_PRV_INT_A_SELECT_247 ICU.SLIAR247.BYTE +#define BSP_PRV_INT_A_SELECT_248 ICU.SLIAR248.BYTE +#define BSP_PRV_INT_A_SELECT_249 ICU.SLIAR249.BYTE +#define BSP_PRV_INT_A_SELECT_250 ICU.SLIAR250.BYTE +#define BSP_PRV_INT_A_SELECT_251 ICU.SLIAR251.BYTE +#define BSP_PRV_INT_A_SELECT_252 ICU.SLIAR252.BYTE +#define BSP_PRV_INT_A_SELECT_253 ICU.SLIAR253.BYTE +#define BSP_PRV_INT_A_SELECT_254 ICU.SLIAR254.BYTE +#define BSP_PRV_INT_A_SELECT_255 ICU.SLIAR255.BYTE + +/* Start and end of Interrupt A vectors. */ +#define BSP_PRV_A_INT_VECTOR_START (208) +#define BSP_PRV_A_INT_VECTOR_END (255) + +/* Start and end of Interrupt A select registers. */ +#define BSP_PRV_SLIAR_START (208) +#define BSP_PRV_SLIAR_END (255) + +/* Starting IER register for mapped interrupts. This is used for calculating the IER register based on the + * given vector number. + */ +#define BSP_PRV_MAP_INT_IER_START (0x1A) + +/* These are used in function-like macros to expand to letters. */ +#define BSP_PRV_A A + +/* Test to see if chosen vector is valid for a mapped interrupt. */ +#define BSP_PRV_VALID_MAP_INT(x, y) (((y + 0) >= BSP_PRV_ ## x ## _INT_VECTOR_START) && \ + ((y + 0) <= BSP_PRV_ ## x ## _INT_VECTOR_END)) + +/* Calculation for getting IER register. */ +#define BSP_PRIV_CALC_IER_REG(x) (((x - BSP_PRV_A_INT_VECTOR_START)/8) + BSP_PRV_MAP_INT_IER_START) + +/* These macros generate the macros needed to use the function-like macros from iodefine.h */ +#define BSP_PRV_IR(x, y) _BSP_PRV_IR(x, y) +#define _BSP_PRV_IR(x, y) IR_PERI ## x ## _INT ## x ## y +#define BSP_PRV_DTCE(x, y) _BSP_PRV_DTCE(x, y) +#define _BSP_PRV_DTCE(x, y) DTCE_PERI ## x ## _INT ## x ## y +#define BSP_PRV_IPR(x, y) _BSP_PRV_IPR(x, y) +#define _BSP_PRV_IPR(x, y) IPR_PERI ## x ## _INT ## x ## y +#define BSP_PRV_VECT(x, y) _BSP_PRV_VECT(x, y) +#define _BSP_PRV_VECT(x, y) VECT_PERI ## x ## _INT ## x ## y + +#define BSP_PRV_IEN(x) _BSP_PRV_IEN(x) +#define _BSP_PRV_IEN(x) __BSP_PRV_IEN(BSP_PRV_CALC_ ## x ## _MOD_8) +#define __BSP_PRV_IEN(x) ___BSP_PRV_IEN(x) +#define ___BSP_PRV_IEN(x) IEN ## x + +/* Chooses the correct interrupt select register. */ +#define BSP_PRV_INT_SELECT(x, y) _BSP_PRV_INT_SELECT(x, y) +#define _BSP_PRV_INT_SELECT(x, y) BSP_PRV_INT_ ## x ## _SELECT_ ## y + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* MCU_MAPPED_INTERRUPTS_PRIVATE_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/r_bsp_cpu.h b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/r_bsp_cpu.h new file mode 100644 index 00000000..e0ede327 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/r_bsp_cpu.h @@ -0,0 +1,81 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : r_bsp_cpu.h +* Description : This module implements CPU specific functions. An example is enabling/disabling interrupts. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 21.11.2023 1.01 Added bsp_bus_priority_initialize function. +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef CPU_H +#define CPU_H + +/* Control pattern specified as argument of R_BSP_VoltageLevelSetting function. */ +#define BSP_VOL_RIIC_4_5V_OROVER (0x10) +#define BSP_VOL_RIIC_UNDER_4_5V (0x20) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* The different types of registers that can be protected. */ +typedef enum +{ + /* PRC0 + Enables writing to the registers related to the clock generation circuit: SCKCR, SCKCR2, SCKCR3, PLLCR, + PLLCR2, MOSCCR, LOCOCR, ILOCOCR, HOCOCR, HOCOCR2, OSTDCR, OSTDSR. */ + BSP_REG_PROTECT_CGC = 0, + + /* PRC1 + Enables writing to the registers related to operating modes, low power consumption, the clock generation circuit, + and software reset: SYSCR1, VOLSR, SBYCR, MSTPCRA, MSTPCRB, MSTPCRC, MSTPCRD, RSTCKCR, + MOSCWTCR, MOFCR, HOCOPCR, SWRR. */ + BSP_REG_PROTECT_LPC_CGC_SWR, + + /* PRC3 + Enables writing to the registers related to the LVD:LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, + LVD2CR1, LVD2SR. */ + BSP_REG_PROTECT_LVD, + + /* MPC.PWPR + Enables writing to MPC's PFS registers. */ + BSP_REG_PROTECT_MPC, + + /* This entry is used for getting the number of enum items. This must be the last entry. DO NOT REMOVE THIS ENTRY!*/ + BSP_REG_PROTECT_TOTAL_ITEMS +} bsp_reg_protect_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_InterruptsDisable(void); +void R_BSP_InterruptsEnable(void); +uint32_t R_BSP_CpuInterruptLevelRead(void); +bool R_BSP_CpuInterruptLevelWrite(uint32_t level); +void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); +void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); +bool R_BSP_VoltageLevelSetting(uint8_t ctrl_ptn); +void R_BSP_SoftwareReset(void); + +void bsp_register_protect_open(void); //r_bsp internal function. DO NOT CALL. +void bsp_ram_initialize(void); +#if BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE == 1 +void bsp_bus_priority_initialize(void); +#endif + +#endif /* CPU_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/r_bsp_locking.h b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/r_bsp_locking.h new file mode 100644 index 00000000..c66bf3c1 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/r_bsp_locking.h @@ -0,0 +1,55 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : r_bsp_locking.h +* Description : This implements a locking mechanism that can be used by all code. The locking is done atomically so +* common resources can be accessed safely. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 26.02.2025 1.01 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Lock types. */ +#include "mcu_locks.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef LOCKING_H +#define LOCKING_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +bool R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool R_BSP_HardwareLock(mcu_lock_t const hw_index); +bool R_BSP_HardwareUnlock(mcu_lock_t const hw_index); + +#if BSP_CFG_USER_LOCKING_ENABLED != 0 +/* Is user is using their own lock functions then these are the prototypes. */ +bool BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t const hw_index); +bool BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t const hw_index); +#endif + +#endif /* LOCKING_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/register_access/gnuc/iodefine.h b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/register_access/gnuc/iodefine.h new file mode 100644 index 00000000..4c57887c --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/register_access/gnuc/iodefine.h @@ -0,0 +1,28857 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************/ +/* */ +/* Device : RX/RX200/RX26T */ +/* File Name : iodefine.h */ +/* Abstract : Definition of I/O Register. */ +/* History : V0.40 (2022-04-28) [Hardware Manual Revision : 0.40] */ +/* : V0.50 (2022-06-01) [Hardware Manual Revision : 0.50] */ +/* : V0.50A (2022-07-04) [Hardware Manual Revision : 0.50] */ +/* : V0.50B (2022-08-25) [Hardware Manual Revision : 0.50] */ +/* : V1.00 (2022-12-13) [Hardware Manual Revision : 0.60] */ +/* : V1.00A (2023-01-27) [Hardware Manual Revision : 1.00] */ +/* : V1.10 (2023-07-07) [Hardware Manual Revision : 1.10] */ +/* : V1.10A (2023-08-22) [Hardware Manual Revision : 1.10] */ +/* : V1.10B (2024-05-21) [Hardware Manual Revision : 1.10] */ +/* Note : This is a typical example. */ +/* */ +/* Copyright(c) 2022 (2023-2024) Renesas Electronics Corporation. */ +/* */ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX26T */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(BSC,BUSERR) = 0; expands to : */ +/* ICU.IR[16].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(ICU,SWINT2) = 2; expands to : */ +/* IPR(ICU,SWI ) = 2; // SWINT2,SWINT share IPR level. */ +/* ICU.IPR[3].BIT.IPR = 2; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,... expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX26TIODEFINE_HEADER__ +#define __RX26TIODEFINE_HEADER__ + +#define IEN_BSC_BUSERR IEN0 +#define IEN_RAM_RAMERR IEN2 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT2 IEN2 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMT2_CMI2 IEN6 +#define IEN_CMT3_CMI3 IEN7 +#define IEN_RSPI0_SPRI0 IEN6 +#define IEN_RSPI0_SPTI0 IEN7 +#define IEN_RI3C0_RESPI IEN0 +#define IEN_RI3C0_CMDI IEN1 +#define IEN_RI3C0_IBII IEN2 +#define IEN_RI3C0_RCVI IEN3 +#define IEN_RSPIA0_SPRI IEN0 +#define IEN_RSPIA0_SPTI IEN1 +#define IEN_RIIC0_RXI0 IEN4 +#define IEN_RIIC0_TXI0 IEN5 +#define IEN_SCI1_RXI1 IEN4 +#define IEN_SCI1_TXI1 IEN5 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_SCI5_RXI5 IEN4 +#define IEN_SCI5_TXI5 IEN5 +#define IEN_SCI6_RXI6 IEN6 +#define IEN_SCI6_TXI6 IEN7 +#define IEN_LVD1_LVD1 IEN0 +#define IEN_LVD2_LVD2 IEN1 +#define IEN_IWDT_IWUNI IEN7 +#define IEN_WDT_WUNI IEN0 +#define IEN_RSCI8_RXI IEN4 +#define IEN_RSCI8_TXI IEN5 +#define IEN_RSCI9_RXI IEN6 +#define IEN_RSCI9_TXI IEN7 +#define IEN_ICU_GROUPBL2 IEN3 +#define IEN_ICU_GROUPBL0 IEN6 +#define IEN_ICU_GROUPBL1 IEN7 +#define IEN_ICU_GROUPAL0 IEN0 +#define IEN_ICU_GROUPAL1 IEN1 +#define IEN_RSCI11_RXI IEN2 +#define IEN_RSCI11_TXI IEN3 +#define IEN_SCI12_RXI12 IEN4 +#define IEN_SCI12_TXI12 IEN5 +#define IEN_RI3C0_RXI IEN6 +#define IEN_RI3C0_TXI IEN7 +#define IEN_DMAC_DMAC0I IEN0 +#define IEN_DMAC_DMAC1I IEN1 +#define IEN_DMAC_DMAC2I IEN2 +#define IEN_DMAC_DMAC3I IEN3 +#define IEN_DMAC_DMAC74I IEN4 +#define IEN_OST_OSTDI IEN5 +#define IEN_S12AD_S12ADI IEN0 +#define IEN_S12AD_S12GBADI IEN1 +#define IEN_S12AD_S12GCADI IEN2 +#define IEN_S12AD1_S12ADI1 IEN4 +#define IEN_S12AD1_S12GBADI1 IEN5 +#define IEN_S12AD1_S12GCADI1 IEN6 +#define IEN_S12AD2_S12ADI2 IEN0 +#define IEN_S12AD2_S12GBADI2 IEN1 +#define IEN_S12AD2_S12GCADI2 IEN2 +#define IEN_CANFD_RFDREQ0 IEN4 +#define IEN_CANFD_RFDREQ1 IEN5 +#define IEN_CANFD0_CFDREQ0 IEN6 +#define IEN_TMR0_CMIA0 IEN2 +#define IEN_TMR0_CMIB0 IEN3 +#define IEN_TMR0_OVI0 IEN4 +#define IEN_TMR1_CMIA1 IEN5 +#define IEN_TMR1_CMIB1 IEN6 +#define IEN_TMR1_OVI1 IEN7 +#define IEN_TMR2_CMIA2 IEN0 +#define IEN_TMR2_CMIB2 IEN1 +#define IEN_TMR2_OVI2 IEN2 +#define IEN_TMR3_CMIA3 IEN3 +#define IEN_TMR3_CMIB3 IEN4 +#define IEN_TMR3_OVI3 IEN5 +#define IEN_TMR4_CMIA4 IEN6 +#define IEN_TMR4_CMIB4 IEN7 +#define IEN_TMR4_OVI4 IEN0 +#define IEN_TMR5_CMIA5 IEN1 +#define IEN_TMR5_CMIB5 IEN2 +#define IEN_TMR5_OVI5 IEN3 +#define IEN_TMR6_CMIA6 IEN4 +#define IEN_TMR6_CMIB6 IEN5 +#define IEN_TMR6_OVI6 IEN6 +#define IEN_TMR7_CMIA7 IEN7 +#define IEN_TMR7_CMIB7 IEN0 +#define IEN_TMR7_OVI7 IEN1 +#define IEN_ELC_ELSR18I IEN7 +#define IEN_ELC_ELSR19I IEN0 +#define IEN_TSIP_RD IEN1 +#define IEN_TSIP_WR IEN2 +#define IEN_TSIP_ERR IEN3 +#define IEN_CMPC0_CMPC0 IEN4 +#define IEN_CMPC1_CMPC1 IEN5 +#define IEN_CMPC2_CMPC2 IEN6 +#define IEN_CMPC3_CMPC3 IEN7 +#define IEN_CMPC4_CMPC4 IEN0 +#define IEN_CMPC5_CMPC5 IEN1 +#define IEN_CMTW0_CMWI0 IEN2 +#define IEN_CMTW0_IC0I0 IEN3 +#define IEN_CMTW0_IC1I0 IEN4 +#define IEN_CMTW0_OC0I0 IEN5 +#define IEN_CMTW0_OC1I0 IEN6 +#define IEN_CMTW1_CMWI1 IEN7 +#define IEN_CMTW1_IC0I1 IEN0 +#define IEN_CMTW1_IC1I1 IEN1 +#define IEN_CMTW1_OC0I1 IEN2 +#define IEN_CMTW1_OC1I1 IEN3 +#define IEN_RSCI9_AED IEN5 +#define IEN_PERIA_INTA208 IEN0 +#define IEN_PERIA_INTA209 IEN1 +#define IEN_PERIA_INTA210 IEN2 +#define IEN_PERIA_INTA211 IEN3 +#define IEN_PERIA_INTA212 IEN4 +#define IEN_PERIA_INTA213 IEN5 +#define IEN_PERIA_INTA214 IEN6 +#define IEN_PERIA_INTA215 IEN7 +#define IEN_PERIA_INTA216 IEN0 +#define IEN_PERIA_INTA217 IEN1 +#define IEN_PERIA_INTA218 IEN2 +#define IEN_PERIA_INTA219 IEN3 +#define IEN_PERIA_INTA220 IEN4 +#define IEN_PERIA_INTA221 IEN5 +#define IEN_PERIA_INTA222 IEN6 +#define IEN_PERIA_INTA223 IEN7 +#define IEN_PERIA_INTA224 IEN0 +#define IEN_PERIA_INTA225 IEN1 +#define IEN_PERIA_INTA226 IEN2 +#define IEN_PERIA_INTA227 IEN3 +#define IEN_PERIA_INTA228 IEN4 +#define IEN_PERIA_INTA229 IEN5 +#define IEN_PERIA_INTA230 IEN6 +#define IEN_PERIA_INTA231 IEN7 +#define IEN_PERIA_INTA232 IEN0 +#define IEN_PERIA_INTA233 IEN1 +#define IEN_PERIA_INTA234 IEN2 +#define IEN_PERIA_INTA235 IEN3 +#define IEN_PERIA_INTA236 IEN4 +#define IEN_PERIA_INTA237 IEN5 +#define IEN_PERIA_INTA238 IEN6 +#define IEN_PERIA_INTA239 IEN7 +#define IEN_PERIA_INTA240 IEN0 +#define IEN_PERIA_INTA241 IEN1 +#define IEN_PERIA_INTA242 IEN2 +#define IEN_PERIA_INTA243 IEN3 +#define IEN_PERIA_INTA244 IEN4 +#define IEN_PERIA_INTA245 IEN5 +#define IEN_PERIA_INTA246 IEN6 +#define IEN_PERIA_INTA247 IEN7 +#define IEN_PERIA_INTA248 IEN0 +#define IEN_PERIA_INTA249 IEN1 +#define IEN_PERIA_INTA250 IEN2 +#define IEN_PERIA_INTA251 IEN3 +#define IEN_PERIA_INTA252 IEN4 +#define IEN_PERIA_INTA253 IEN5 +#define IEN_PERIA_INTA254 IEN6 +#define IEN_PERIA_INTA255 IEN7 + +#define VECT_BSC_BUSERR 16 +#define VECT_RAM_RAMERR 18 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT2 26 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMT2_CMI2 30 +#define VECT_CMT3_CMI3 31 +#define VECT_RSPI0_SPRI0 38 +#define VECT_RSPI0_SPTI0 39 +#define VECT_RI3C0_RESPI 40 +#define VECT_RI3C0_CMDI 41 +#define VECT_RI3C0_IBII 42 +#define VECT_RI3C0_RCVI 43 +#define VECT_RSPIA0_SPRI 48 +#define VECT_RSPIA0_SPTI 49 +#define VECT_RIIC0_RXI0 52 +#define VECT_RIIC0_TXI0 53 +#define VECT_SCI1_RXI1 60 +#define VECT_SCI1_TXI1 61 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_SCI5_RXI5 84 +#define VECT_SCI5_TXI5 85 +#define VECT_SCI6_RXI6 86 +#define VECT_SCI6_TXI6 87 +#define VECT_LVD1_LVD1 88 +#define VECT_LVD2_LVD2 89 +#define VECT_IWDT_IWUNI 95 +#define VECT_WDT_WUNI 96 +#define VECT_RSCI8_RXI 100 +#define VECT_RSCI8_TXI 101 +#define VECT_RSCI9_RXI 102 +#define VECT_RSCI9_TXI 103 +#define VECT_ICU_GROUPBL2 107 +#define VECT_ICU_GROUPBL0 110 +#define VECT_ICU_GROUPBL1 111 +#define VECT_ICU_GROUPAL0 112 +#define VECT_ICU_GROUPAL1 113 +#define VECT_RSCI11_RXI 114 +#define VECT_RSCI11_TXI 115 +#define VECT_SCI12_RXI12 116 +#define VECT_SCI12_TXI12 117 +#define VECT_RI3C0_RXI 118 +#define VECT_RI3C0_TXI 119 +#define VECT_DMAC_DMAC0I 120 +#define VECT_DMAC_DMAC1I 121 +#define VECT_DMAC_DMAC2I 122 +#define VECT_DMAC_DMAC3I 123 +#define VECT_DMAC_DMAC74I 124 +#define VECT_OST_OSTDI 125 +#define VECT_S12AD_S12ADI 128 +#define VECT_S12AD_S12GBADI 129 +#define VECT_S12AD_S12GCADI 130 +#define VECT_S12AD1_S12ADI1 132 +#define VECT_S12AD1_S12GBADI1 133 +#define VECT_S12AD1_S12GCADI1 134 +#define VECT_S12AD2_S12ADI2 136 +#define VECT_S12AD2_S12GBADI2 137 +#define VECT_S12AD2_S12GCADI2 138 +#define VECT_CANFD_RFDREQ0 140 +#define VECT_CANFD_RFDREQ1 141 +#define VECT_CANFD0_CFDREQ0 142 +#define VECT_TMR0_CMIA0 146 +#define VECT_TMR0_CMIB0 147 +#define VECT_TMR0_OVI0 148 +#define VECT_TMR1_CMIA1 149 +#define VECT_TMR1_CMIB1 150 +#define VECT_TMR1_OVI1 151 +#define VECT_TMR2_CMIA2 152 +#define VECT_TMR2_CMIB2 153 +#define VECT_TMR2_OVI2 154 +#define VECT_TMR3_CMIA3 155 +#define VECT_TMR3_CMIB3 156 +#define VECT_TMR3_OVI3 157 +#define VECT_TMR4_CMIA4 158 +#define VECT_TMR4_CMIB4 159 +#define VECT_TMR4_OVI4 160 +#define VECT_TMR5_CMIA5 161 +#define VECT_TMR5_CMIB5 162 +#define VECT_TMR5_OVI5 163 +#define VECT_TMR6_CMIA6 164 +#define VECT_TMR6_CMIB6 165 +#define VECT_TMR6_OVI6 166 +#define VECT_TMR7_CMIA7 167 +#define VECT_TMR7_CMIB7 168 +#define VECT_TMR7_OVI7 169 +#define VECT_ELC_ELSR18I 175 +#define VECT_ELC_ELSR19I 176 +#define VECT_TSIP_RD 177 +#define VECT_TSIP_WR 178 +#define VECT_TSIP_ERR 179 +#define VECT_CMPC0_CMPC0 180 +#define VECT_CMPC1_CMPC1 181 +#define VECT_CMPC2_CMPC2 182 +#define VECT_CMPC3_CMPC3 183 +#define VECT_CMPC4_CMPC4 184 +#define VECT_CMPC5_CMPC5 185 +#define VECT_CMTW0_CMWI0 186 +#define VECT_CMTW0_IC0I0 187 +#define VECT_CMTW0_IC1I0 188 +#define VECT_CMTW0_OC0I0 189 +#define VECT_CMTW0_OC1I0 190 +#define VECT_CMTW1_CMWI1 191 +#define VECT_CMTW1_IC0I1 192 +#define VECT_CMTW1_IC1I1 193 +#define VECT_CMTW1_OC0I1 194 +#define VECT_CMTW1_OC1I1 195 +#define VECT_RSCI9_AED 197 +#define VECT_PERIA_INTA208 208 +#define VECT_PERIA_INTA209 209 +#define VECT_PERIA_INTA210 210 +#define VECT_PERIA_INTA211 211 +#define VECT_PERIA_INTA212 212 +#define VECT_PERIA_INTA213 213 +#define VECT_PERIA_INTA214 214 +#define VECT_PERIA_INTA215 215 +#define VECT_PERIA_INTA216 216 +#define VECT_PERIA_INTA217 217 +#define VECT_PERIA_INTA218 218 +#define VECT_PERIA_INTA219 219 +#define VECT_PERIA_INTA220 220 +#define VECT_PERIA_INTA221 221 +#define VECT_PERIA_INTA222 222 +#define VECT_PERIA_INTA223 223 +#define VECT_PERIA_INTA224 224 +#define VECT_PERIA_INTA225 225 +#define VECT_PERIA_INTA226 226 +#define VECT_PERIA_INTA227 227 +#define VECT_PERIA_INTA228 228 +#define VECT_PERIA_INTA229 229 +#define VECT_PERIA_INTA230 230 +#define VECT_PERIA_INTA231 231 +#define VECT_PERIA_INTA232 232 +#define VECT_PERIA_INTA233 233 +#define VECT_PERIA_INTA234 234 +#define VECT_PERIA_INTA235 235 +#define VECT_PERIA_INTA236 236 +#define VECT_PERIA_INTA237 237 +#define VECT_PERIA_INTA238 238 +#define VECT_PERIA_INTA239 239 +#define VECT_PERIA_INTA240 240 +#define VECT_PERIA_INTA241 241 +#define VECT_PERIA_INTA242 242 +#define VECT_PERIA_INTA243 243 +#define VECT_PERIA_INTA244 244 +#define VECT_PERIA_INTA245 245 +#define VECT_PERIA_INTA246 246 +#define VECT_PERIA_INTA247 247 +#define VECT_PERIA_INTA248 248 +#define VECT_PERIA_INTA249 249 +#define VECT_PERIA_INTA250 250 +#define VECT_PERIA_INTA251 251 +#define VECT_PERIA_INTA252 252 +#define VECT_PERIA_INTA253 253 +#define VECT_PERIA_INTA254 254 +#define VECT_PERIA_INTA255 255 + +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC4 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC5 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC6 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC7 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_S12AD2 SYSTEM.MSTPCRA.BIT.MSTPA23 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_S12AD1 SYSTEM.MSTPCRA.BIT.MSTPA16 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU9 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_GPTW SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW0 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW1 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW2 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW3 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW4 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW5 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW6 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_GPTW7 SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_HRPWM SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_POEG SYSTEM.MSTPCRA.BIT.MSTPA7 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR4 SYSTEM.MSTPCRA.BIT.MSTPA3 +#define MSTP_TMR5 SYSTEM.MSTPCRA.BIT.MSTPA3 +#define MSTP_TMR45 SYSTEM.MSTPCRA.BIT.MSTPA3 +#define MSTP_TMR6 SYSTEM.MSTPCRA.BIT.MSTPA2 +#define MSTP_TMR7 SYSTEM.MSTPCRA.BIT.MSTPA2 +#define MSTP_TMR67 SYSTEM.MSTPCRA.BIT.MSTPA2 +#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPA1 +#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPA0 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_CMPC0 SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_CMPC1 SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_CMPC2 SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_CMPC3 SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_CMPC4 SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_CMPC5 SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_RSCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_RSCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_RSCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RAM SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_TSIP SYSTEM.MSTPCRD.BIT.MSTPD27 +#define MSTP_RSPIA0 SYSTEM.MSTPCRD.BIT.MSTPD26 +#define MSTP_CANFD SYSTEM.MSTPCRD.BIT.MSTPD10 +#define MSTP_CANFD0 SYSTEM.MSTPCRD.BIT.MSTPD10 +#define MSTP_RI3C0 SYSTEM.MSTPCRD.BIT.MSTPD5 + +#define IS_SCI1_TEI1 IS2 +#define IS_SCI1_ERI1 IS3 +#define IS_SCI5_TEI5 IS10 +#define IS_SCI5_ERI5 IS11 +#define IS_SCI6_TEI6 IS12 +#define IS_SCI6_ERI6 IS13 +#define IS_SCI12_TEI12 IS16 +#define IS_SCI12_ERI12 IS17 +#define IS_SCI12_SCIX0 IS18 +#define IS_SCI12_SCIX1 IS19 +#define IS_SCI12_SCIX2 IS20 +#define IS_SCI12_SCIX3 IS21 +#define IS_CAC_FERRI IS26 +#define IS_CAC_MENDI IS27 +#define IS_CAC_OVFI IS28 +#define IS_DOC_DOPCI IS29 +#define IS_POEG_POEGGAI IS0 +#define IS_POEG_POEGGBI IS1 +#define IS_POEG_POEGGCI IS2 +#define IS_POEG_POEGGDI IS3 +#define IS_POE_OEI5 IS8 +#define IS_POE_OEI1 IS9 +#define IS_POE_OEI2 IS10 +#define IS_POE_OEI3 IS11 +#define IS_POE_OEI4 IS12 +#define IS_RIIC0_TEI0 IS13 +#define IS_RIIC0_EEI0 IS14 +#define IS_S12AD2_S12CMPAI2 IS18 +#define IS_S12AD2_S12CMPBI2 IS19 +#define IS_S12AD_S12CMPAI IS20 +#define IS_S12AD_S12CMPBI IS21 +#define IS_S12AD1_S12CMPAI1 IS22 +#define IS_S12AD1_S12CMPBI1 IS23 +#define IS_RSCI8_TEI IS24 +#define IS_RSCI8_ERI IS25 +#define IS_RSCI9_TEI IS26 +#define IS_RSCI9_ERI IS27 +#define IS_RSCI9_BFD IS31 +#define IS_CANFD0_CHEI IS1 +#define IS_CANFD0_CFRI IS2 +#define IS_CANFD_GLEI IS3 +#define IS_CANFD_RFRI IS4 +#define IS_CANFD0_CHTI IS5 +#define IS_CANFD_RMRI IS6 +#define IS_RSCI11_TEI IS12 +#define IS_RSCI11_ERI IS13 +#define IS_RSCI11_BFD IS14 +#define IS_RSPI0_SPII0 IS16 +#define IS_RSPI0_SPEI0 IS17 +#define IS_RSPIA0_SPII IS22 +#define IS_RSPIA0_SPEI IS23 +#define IS_RI3C0_EEI IS13 + +#define EN_SCI1_TEI1 EN2 +#define EN_SCI1_ERI1 EN3 +#define EN_SCI5_TEI5 EN10 +#define EN_SCI5_ERI5 EN11 +#define EN_SCI6_TEI6 EN12 +#define EN_SCI6_ERI6 EN13 +#define EN_SCI12_TEI12 EN16 +#define EN_SCI12_ERI12 EN17 +#define EN_SCI12_SCIX0 EN18 +#define EN_SCI12_SCIX1 EN19 +#define EN_SCI12_SCIX2 EN20 +#define EN_SCI12_SCIX3 EN21 +#define EN_CAC_FERRI EN26 +#define EN_CAC_MENDI EN27 +#define EN_CAC_OVFI EN28 +#define EN_DOC_DOPCI EN29 +#define EN_POEG_POEGGAI EN0 +#define EN_POEG_POEGGBI EN1 +#define EN_POEG_POEGGCI EN2 +#define EN_POEG_POEGGDI EN3 +#define EN_POE_OEI5 EN8 +#define EN_POE_OEI1 EN9 +#define EN_POE_OEI2 EN10 +#define EN_POE_OEI3 EN11 +#define EN_POE_OEI4 EN12 +#define EN_RIIC0_TEI0 EN13 +#define EN_RIIC0_EEI0 EN14 +#define EN_S12AD2_S12CMPAI2 EN18 +#define EN_S12AD2_S12CMPBI2 EN19 +#define EN_S12AD_S12CMPAI EN20 +#define EN_S12AD_S12CMPBI EN21 +#define EN_S12AD1_S12CMPAI1 EN22 +#define EN_S12AD1_S12CMPBI1 EN23 +#define EN_RSCI8_TEI EN24 +#define EN_RSCI8_ERI EN25 +#define EN_RSCI9_TEI EN26 +#define EN_RSCI9_ERI EN27 +#define EN_RSCI9_BFD EN31 +#define EN_CANFD0_CHEI EN1 +#define EN_CANFD0_CFRI EN2 +#define EN_CANFD_GLEI EN3 +#define EN_CANFD_RFRI EN4 +#define EN_CANFD0_CHTI EN5 +#define EN_CANFD_RMRI EN6 +#define EN_RSCI11_TEI EN12 +#define EN_RSCI11_ERI EN13 +#define EN_RSCI11_BFD EN14 +#define EN_RSPI0_SPII0 EN16 +#define EN_RSPI0_SPEI0 EN17 +#define EN_RSPIA0_SPII EN22 +#define EN_RSPIA0_SPEI EN23 +#define EN_RI3C0_EEI EN13 + +#define GEN_SCI1_TEI1 GENBL0 +#define GEN_SCI1_ERI1 GENBL0 +#define GEN_SCI5_TEI5 GENBL0 +#define GEN_SCI5_ERI5 GENBL0 +#define GEN_SCI6_TEI6 GENBL0 +#define GEN_SCI6_ERI6 GENBL0 +#define GEN_SCI12_TEI12 GENBL0 +#define GEN_SCI12_ERI12 GENBL0 +#define GEN_SCI12_SCIX0 GENBL0 +#define GEN_SCI12_SCIX1 GENBL0 +#define GEN_SCI12_SCIX2 GENBL0 +#define GEN_SCI12_SCIX3 GENBL0 +#define GEN_CAC_FERRI GENBL0 +#define GEN_CAC_MENDI GENBL0 +#define GEN_CAC_OVFI GENBL0 +#define GEN_DOC_DOPCI GENBL0 +#define GEN_POEG_POEGGAI GENBL1 +#define GEN_POEG_POEGGBI GENBL1 +#define GEN_POEG_POEGGCI GENBL1 +#define GEN_POEG_POEGGDI GENBL1 +#define GEN_POE_OEI5 GENBL1 +#define GEN_POE_OEI1 GENBL1 +#define GEN_POE_OEI2 GENBL1 +#define GEN_POE_OEI3 GENBL1 +#define GEN_POE_OEI4 GENBL1 +#define GEN_RIIC0_TEI0 GENBL1 +#define GEN_RIIC0_EEI0 GENBL1 +#define GEN_S12AD2_S12CMPAI2 GENBL1 +#define GEN_S12AD2_S12CMPBI2 GENBL1 +#define GEN_S12AD_S12CMPAI GENBL1 +#define GEN_S12AD_S12CMPBI GENBL1 +#define GEN_S12AD1_S12CMPAI1 GENBL1 +#define GEN_S12AD1_S12CMPBI1 GENBL1 +#define GEN_RSCI8_TEI GENBL1 +#define GEN_RSCI8_ERI GENBL1 +#define GEN_RSCI9_TEI GENBL1 +#define GEN_RSCI9_ERI GENBL1 +#define GEN_RSCI9_BFD GENBL1 +#define GEN_CANFD0_CHEI GENBL2 +#define GEN_CANFD0_CFRI GENBL2 +#define GEN_CANFD_GLEI GENBL2 +#define GEN_CANFD_RFRI GENBL2 +#define GEN_CANFD0_CHTI GENBL2 +#define GEN_CANFD_RMRI GENBL2 +#define GEN_RSCI11_TEI GENAL0 +#define GEN_RSCI11_ERI GENAL0 +#define GEN_RSCI11_BFD GENAL0 +#define GEN_RSPI0_SPII0 GENAL0 +#define GEN_RSPI0_SPEI0 GENAL0 +#define GEN_RSPIA0_SPII GENAL0 +#define GEN_RSPIA0_SPEI GENAL0 +#define GEN_RI3C0_EEI GENAL1 + +#define GRP_SCI1_TEI1 GRPBL0 +#define GRP_SCI1_ERI1 GRPBL0 +#define GRP_SCI5_TEI5 GRPBL0 +#define GRP_SCI5_ERI5 GRPBL0 +#define GRP_SCI6_TEI6 GRPBL0 +#define GRP_SCI6_ERI6 GRPBL0 +#define GRP_SCI12_TEI12 GRPBL0 +#define GRP_SCI12_ERI12 GRPBL0 +#define GRP_SCI12_SCIX0 GRPBL0 +#define GRP_SCI12_SCIX1 GRPBL0 +#define GRP_SCI12_SCIX2 GRPBL0 +#define GRP_SCI12_SCIX3 GRPBL0 +#define GRP_CAC_FERRI GRPBL0 +#define GRP_CAC_MENDI GRPBL0 +#define GRP_CAC_OVFI GRPBL0 +#define GRP_DOC_DOPCI GRPBL0 +#define GRP_POEG_POEGGAI GRPBL1 +#define GRP_POEG_POEGGBI GRPBL1 +#define GRP_POEG_POEGGCI GRPBL1 +#define GRP_POEG_POEGGDI GRPBL1 +#define GRP_POE_OEI5 GRPBL1 +#define GRP_POE_OEI1 GRPBL1 +#define GRP_POE_OEI2 GRPBL1 +#define GRP_POE_OEI3 GRPBL1 +#define GRP_POE_OEI4 GRPBL1 +#define GRP_RIIC0_TEI0 GRPBL1 +#define GRP_RIIC0_EEI0 GRPBL1 +#define GRP_S12AD2_S12CMPAI2 GRPBL1 +#define GRP_S12AD2_S12CMPBI2 GRPBL1 +#define GRP_S12AD_S12CMPAI GRPBL1 +#define GRP_S12AD_S12CMPBI GRPBL1 +#define GRP_S12AD1_S12CMPAI1 GRPBL1 +#define GRP_S12AD1_S12CMPBI1 GRPBL1 +#define GRP_RSCI8_TEI GRPBL1 +#define GRP_RSCI8_ERI GRPBL1 +#define GRP_RSCI9_TEI GRPBL1 +#define GRP_RSCI9_ERI GRPBL1 +#define GRP_RSCI9_BFD GRPBL1 +#define GRP_CANFD0_CHEI GRPBL2 +#define GRP_CANFD0_CFRI GRPBL2 +#define GRP_CANFD_GLEI GRPBL2 +#define GRP_CANFD_RFRI GRPBL2 +#define GRP_CANFD0_CHTI GRPBL2 +#define GRP_CANFD_RMRI GRPBL2 +#define GRP_RSCI11_TEI GRPAL0 +#define GRP_RSCI11_ERI GRPAL0 +#define GRP_RSCI11_BFD GRPAL0 +#define GRP_RSPI0_SPII0 GRPAL0 +#define GRP_RSPI0_SPEI0 GRPAL0 +#define GRP_RSPIA0_SPII GRPAL0 +#define GRP_RSPIA0_SPEI GRPAL0 +#define GRP_RI3C0_EEI GRPAL1 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define __IS( x ) ICU.GRP ## x.BIT.IS ## x +#define _IS( x ) __IS( x ) +#define IS( x , y ) _IS( _ ## x ## _ ## y ) +#define __EN( x ) ICU.GEN ## x.BIT.EN ## x +#define _EN( x ) __EN( x ) +#define EN( x , y ) _EN( _ ## x ## _ ## y ) +#define __CLR( x ) ICU.GCR ## x.BIT.CLR ## x +#define _CLR( x ) __CLR( x ) +#define CLR( x , y ) _CLR( _ ## x ## _ ## y ) + +#define BSC (*(volatile struct st_bsc *)0x81300) +#define CAC (*(volatile struct st_cac *)0x8B000) +#define CANFD (*(volatile struct st_canfd *)0xA8014) +#define CANFD0 (*(volatile struct st_canfd0 *)0xA8000) +#define CMPC0 (*(volatile struct st_cmpc *)0xA0C80) +#define CMPC1 (*(volatile struct st_cmpc *)0xA0CA0) +#define CMPC2 (*(volatile struct st_cmpc *)0xA0CC0) +#define CMPC3 (*(volatile struct st_cmpc *)0xA0CE0) +#define CMPC4 (*(volatile struct st_cmpc *)0xA0D00) +#define CMPC5 (*(volatile struct st_cmpc *)0xA0D20) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 *)0x88018) +#define CMTW0 (*(volatile struct st_cmtw *)0x94200) +#define CMTW1 (*(volatile struct st_cmtw *)0x94280) +#define CRC (*(volatile struct st_crc *)0x88280) +#define DA (*(volatile struct st_da *)0x88040) +#define DMAC (*(volatile struct st_dmac *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 *)0x820C0) +#define DMAC4 (*(volatile struct st_dmac1 *)0x82100) +#define DMAC5 (*(volatile struct st_dmac1 *)0x82140) +#define DMAC6 (*(volatile struct st_dmac1 *)0x82180) +#define DMAC7 (*(volatile struct st_dmac1 *)0x821C0) +#define DOC (*(volatile struct st_doc *)0xA0580) +#define DTC (*(volatile struct st_dtc *)0x82400) +#define ELC (*(volatile struct st_elc *)0x8B100) +#define FLASH (*(volatile struct st_flash *)0x8C294) +#define GPTW (*(volatile struct st_gptw *)0xC2B00) +#define GPTW0 (*(volatile struct st_gptw0 *)0xC2000) +#define GPTW1 (*(volatile struct st_gptw0 *)0xC2100) +#define GPTW2 (*(volatile struct st_gptw0 *)0xC2200) +#define GPTW3 (*(volatile struct st_gptw0 *)0xC2300) +#define GPTW4 (*(volatile struct st_gptw0 *)0xC2400) +#define GPTW5 (*(volatile struct st_gptw0 *)0xC2500) +#define GPTW6 (*(volatile struct st_gptw0 *)0xC2600) +#define GPTW7 (*(volatile struct st_gptw0 *)0xC2700) +#define HRPWM (*(volatile struct st_hrpwm *)0xC2A00) +#define ICU (*(volatile struct st_icu *)0x87000) +#define IWDT (*(volatile struct st_iwdt *)0x88030) +#define MPC (*(volatile struct st_mpc *)0x8C11F) +#define MPU (*(volatile struct st_mpu *)0x86400) +#define MTU (*(volatile struct st_mtu *)0xC120A) +#define MTU0 (*(volatile struct st_mtu0 *)0xC1290) +#define MTU1 (*(volatile struct st_mtu1 *)0xC1290) +#define MTU2 (*(volatile struct st_mtu2 *)0xC1292) +#define MTU3 (*(volatile struct st_mtu3 *)0xC1200) +#define MTU4 (*(volatile struct st_mtu4 *)0xC1200) +#define MTU5 (*(volatile struct st_mtu5 *)0xC1A94) +#define MTU6 (*(volatile struct st_mtu6 *)0xC1A00) +#define MTU7 (*(volatile struct st_mtu7 *)0xC1A00) +#define MTU9 (*(volatile struct st_mtu9 *)0xC1296) +#define OFSM (*(volatile struct st_ofsm *)0x120040) +#define POE (*(volatile struct st_poe *)0x9E400) +#define POEG (*(volatile struct st_poeg *)0x9E000) +#define PORT (*(volatile struct st_port *)0x8C110) +#define PORT0 (*(volatile struct st_port0 *)0x8C000) +#define PORT1 (*(volatile struct st_port1 *)0x8C001) +#define PORT2 (*(volatile struct st_port2 *)0x8C002) +#define PORT3 (*(volatile struct st_port3 *)0x8C003) +#define PORT4 (*(volatile struct st_port4 *)0x8C004) +#define PORT5 (*(volatile struct st_port5 *)0x8C005) +#define PORT6 (*(volatile struct st_port6 *)0x8C006) +#define PORT7 (*(volatile struct st_port7 *)0x8C007) +#define PORT8 (*(volatile struct st_port8 *)0x8C008) +#define PORT9 (*(volatile struct st_port9 *)0x8C009) +#define PORTA (*(volatile struct st_porta *)0x8C00A) +#define PORTB (*(volatile struct st_portb *)0x8C00B) +#define PORTD (*(volatile struct st_portd *)0x8C00D) +#define PORTE (*(volatile struct st_porte *)0x8C00E) +#define PORTN (*(volatile struct st_portn *)0x8C016) +#define RAM (*(volatile struct st_ram *)0x81200) +#define RI3C0 (*(volatile struct st_ri3c *)0xEC000) +#define RIIC0 (*(volatile struct st_riic *)0x88300) +#define RSCI8 (*(volatile struct st_rsci8 *)0xA1400) +#define RSCI9 (*(volatile struct st_rsci9 *)0xA1480) +#define RSCI11 (*(volatile struct st_rsci11 *)0xE2080) +#define RSPI0 (*(volatile struct st_rspi *)0xD0100) +#define RSPIA0 (*(volatile struct st_rspia *)0xE2800) +#define S12AD (*(volatile struct st_s12ad *)0x89000) +#define S12AD1 (*(volatile struct st_s12ad1 *)0x89200) +#define S12AD2 (*(volatile struct st_s12ad2 *)0x89400) +#define SCI1 (*(volatile struct st_sci1 *)0x8A020) +#define SCI5 (*(volatile struct st_sci1 *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci1 *)0x8A0C0) +#define SCI12 (*(volatile struct st_sci12 *)0x8B300) +#define SMCI1 (*(volatile struct st_smci *)0x8A020) +#define SMCI5 (*(volatile struct st_smci *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci *)0x8A0C0) +#define SMCI12 (*(volatile struct st_smci *)0x8B300) +#define SYSTEM (*(volatile struct st_system *)0x80000) +#define TEMPS (*(volatile struct st_temps *)0x7FB17C) +#define TFU (*(volatile struct st_tfu *)0x81404) +#define TMR0 (*(volatile struct st_tmr0 *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 *)0x88211) +#define TMR4 (*(volatile struct st_tmr4 *)0x88220) +#define TMR5 (*(volatile struct st_tmr5 *)0x88221) +#define TMR6 (*(volatile struct st_tmr4 *)0x88230) +#define TMR7 (*(volatile struct st_tmr5 *)0x88231) +#define TMR01 (*(volatile struct st_tmr01 *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 *)0x88214) +#define TMR45 (*(volatile struct st_tmr01 *)0x88224) +#define TMR67 (*(volatile struct st_tmr01 *)0x88234) +#define WDT (*(volatile struct st_wdt *)0x88020) + +typedef enum enum_ir { +IR_BSC_BUSERR=16,IR_RAM_RAMERR=18, +IR_FCU_FIFERR=21,IR_FCU_FRDYI=23, +IR_ICU_SWINT2=26,IR_ICU_SWINT, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMT2_CMI2, +IR_CMT3_CMI3, +IR_RSPI0_SPRI0=38,IR_RSPI0_SPTI0, +IR_RI3C0_RESPI,IR_RI3C0_CMDI,IR_RI3C0_IBII,IR_RI3C0_RCVI, +IR_RSPIA0_SPRI=48,IR_RSPIA0_SPTI, +IR_RIIC0_RXI0=52,IR_RIIC0_TXI0, +IR_SCI1_RXI1=60,IR_SCI1_TXI1, +IR_ICU_IRQ0=64,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15, +IR_SCI5_RXI5=84,IR_SCI5_TXI5, +IR_SCI6_RXI6,IR_SCI6_TXI6, +IR_LVD1_LVD1, +IR_LVD2_LVD2, +IR_IWDT_IWUNI=95, +IR_WDT_WUNI, +IR_RSCI8_RXI=100,IR_RSCI8_TXI, +IR_RSCI9_RXI,IR_RSCI9_TXI, +IR_ICU_GROUPBL2=107,IR_ICU_GROUPBL0=110,IR_ICU_GROUPBL1,IR_ICU_GROUPAL0,IR_ICU_GROUPAL1, +IR_RSCI11_RXI,IR_RSCI11_TXI, +IR_SCI12_RXI12,IR_SCI12_TXI12, +IR_RI3C0_RXI,IR_RI3C0_TXI, +IR_DMAC_DMAC0I,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I,IR_DMAC_DMAC74I, +IR_OST_OSTDI, +IR_S12AD_S12ADI=128,IR_S12AD_S12GBADI,IR_S12AD_S12GCADI, +IR_S12AD1_S12ADI1=132,IR_S12AD1_S12GBADI1,IR_S12AD1_S12GCADI1, +IR_S12AD2_S12ADI2=136,IR_S12AD2_S12GBADI2,IR_S12AD2_S12GCADI2, +IR_CANFD_RFDREQ0=140,IR_CANFD_RFDREQ1, +IR_CANFD0_CFDREQ0, +IR_TMR0_CMIA0=146,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_TMR4_CMIA4,IR_TMR4_CMIB4,IR_TMR4_OVI4, +IR_TMR5_CMIA5,IR_TMR5_CMIB5,IR_TMR5_OVI5, +IR_TMR6_CMIA6,IR_TMR6_CMIB6,IR_TMR6_OVI6, +IR_TMR7_CMIA7,IR_TMR7_CMIB7,IR_TMR7_OVI7, +IR_ELC_ELSR18I=175,IR_ELC_ELSR19I, +IR_TSIP_RD,IR_TSIP_WR,IR_TSIP_ERR, +IR_CMPC0_CMPC0, +IR_CMPC1_CMPC1, +IR_CMPC2_CMPC2, +IR_CMPC3_CMPC3, +IR_CMPC4_CMPC4, +IR_CMPC5_CMPC5, +IR_CMTW0_CMWI0,IR_CMTW0_IC0I0,IR_CMTW0_IC1I0,IR_CMTW0_OC0I0,IR_CMTW0_OC1I0, +IR_CMTW1_CMWI1,IR_CMTW1_IC0I1,IR_CMTW1_IC1I1,IR_CMTW1_OC0I1,IR_CMTW1_OC1I1, +IR_RSCI9_AED=197, +IR_PERIA_INTA208=208,IR_PERIA_INTA209,IR_PERIA_INTA210,IR_PERIA_INTA211,IR_PERIA_INTA212,IR_PERIA_INTA213, +IR_PERIA_INTA214,IR_PERIA_INTA215,IR_PERIA_INTA216,IR_PERIA_INTA217,IR_PERIA_INTA218,IR_PERIA_INTA219, +IR_PERIA_INTA220,IR_PERIA_INTA221,IR_PERIA_INTA222,IR_PERIA_INTA223,IR_PERIA_INTA224,IR_PERIA_INTA225, +IR_PERIA_INTA226,IR_PERIA_INTA227,IR_PERIA_INTA228,IR_PERIA_INTA229,IR_PERIA_INTA230,IR_PERIA_INTA231, +IR_PERIA_INTA232,IR_PERIA_INTA233,IR_PERIA_INTA234,IR_PERIA_INTA235,IR_PERIA_INTA236,IR_PERIA_INTA237, +IR_PERIA_INTA238,IR_PERIA_INTA239,IR_PERIA_INTA240,IR_PERIA_INTA241,IR_PERIA_INTA242,IR_PERIA_INTA243, +IR_PERIA_INTA244,IR_PERIA_INTA245,IR_PERIA_INTA246,IR_PERIA_INTA247,IR_PERIA_INTA248,IR_PERIA_INTA249, +IR_PERIA_INTA250,IR_PERIA_INTA251,IR_PERIA_INTA252,IR_PERIA_INTA253,IR_PERIA_INTA254,IR_PERIA_INTA255 +} enum_ir_t; + +typedef enum enum_dtce { +DTCE_ICU_SWINT2=26,DTCE_ICU_SWINT, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMT2_CMI2, +DTCE_CMT3_CMI3, +DTCE_RSPI0_SPRI0=38,DTCE_RSPI0_SPTI0, +DTCE_RI3C0_RESPI,DTCE_RI3C0_CMDI,DTCE_RI3C0_IBII,DTCE_RI3C0_RCVI, +DTCE_RSPIA0_SPRI=48,DTCE_RSPIA0_SPTI, +DTCE_RIIC0_RXI0=52,DTCE_RIIC0_TXI0, +DTCE_SCI1_RXI1=60,DTCE_SCI1_TXI1, +DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_SCI5_RXI5=84,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6,DTCE_SCI6_TXI6, +DTCE_RSCI8_RXI=100,DTCE_RSCI8_TXI, +DTCE_RSCI9_RXI,DTCE_RSCI9_TXI, +DTCE_RSCI11_RXI=114,DTCE_RSCI11_TXI, +DTCE_SCI12_RXI12,DTCE_SCI12_TXI12, +DTCE_RI3C0_RXI,DTCE_RI3C0_TXI, +DTCE_DMAC_DMAC0I,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_S12AD_S12ADI=128,DTCE_S12AD_S12GBADI,DTCE_S12AD_S12GCADI, +DTCE_S12AD1_S12ADI1=132,DTCE_S12AD1_S12GBADI1,DTCE_S12AD1_S12GCADI1, +DTCE_S12AD2_S12ADI2=136,DTCE_S12AD2_S12GBADI2,DTCE_S12AD2_S12GCADI2, +DTCE_CANFD_RFDREQ0=140,DTCE_CANFD_RFDREQ1, +DTCE_CANFD0_CFDREQ0, +DTCE_TMR0_CMIA0=146,DTCE_TMR0_CMIB0, +DTCE_TMR1_CMIA1=149,DTCE_TMR1_CMIB1, +DTCE_TMR2_CMIA2=152,DTCE_TMR2_CMIB2, +DTCE_TMR3_CMIA3=155,DTCE_TMR3_CMIB3, +DTCE_TMR4_CMIA4=158,DTCE_TMR4_CMIB4, +DTCE_TMR5_CMIA5=161,DTCE_TMR5_CMIB5, +DTCE_TMR6_CMIA6=164,DTCE_TMR6_CMIB6, +DTCE_TMR7_CMIA7=167,DTCE_TMR7_CMIB7, +DTCE_ELC_ELSR18I=175,DTCE_ELC_ELSR19I, +DTCE_TSIP_RD,DTCE_TSIP_WR, +DTCE_CMPC0_CMPC0=180, +DTCE_CMPC1_CMPC1, +DTCE_CMPC2_CMPC2, +DTCE_CMPC3_CMPC3, +DTCE_CMPC4_CMPC4, +DTCE_CMPC5_CMPC5, +DTCE_CMTW0_CMWI0,DTCE_CMTW0_IC0I0,DTCE_CMTW0_IC1I0,DTCE_CMTW0_OC0I0,DTCE_CMTW0_OC1I0, +DTCE_CMTW1_CMWI1,DTCE_CMTW1_IC0I1,DTCE_CMTW1_IC1I1,DTCE_CMTW1_OC0I1,DTCE_CMTW1_OC1I1, +DTCE_RSCI9_AED=197, +DTCE_PERIA_INTA208=208,DTCE_PERIA_INTA209,DTCE_PERIA_INTA210,DTCE_PERIA_INTA211,DTCE_PERIA_INTA212,DTCE_PERIA_INTA213, +DTCE_PERIA_INTA214,DTCE_PERIA_INTA215,DTCE_PERIA_INTA216,DTCE_PERIA_INTA217,DTCE_PERIA_INTA218,DTCE_PERIA_INTA219, +DTCE_PERIA_INTA220,DTCE_PERIA_INTA221,DTCE_PERIA_INTA222,DTCE_PERIA_INTA223,DTCE_PERIA_INTA224,DTCE_PERIA_INTA225, +DTCE_PERIA_INTA226,DTCE_PERIA_INTA227,DTCE_PERIA_INTA228,DTCE_PERIA_INTA229,DTCE_PERIA_INTA230,DTCE_PERIA_INTA231, +DTCE_PERIA_INTA232,DTCE_PERIA_INTA233,DTCE_PERIA_INTA234,DTCE_PERIA_INTA235,DTCE_PERIA_INTA236,DTCE_PERIA_INTA237, +DTCE_PERIA_INTA238,DTCE_PERIA_INTA239,DTCE_PERIA_INTA240,DTCE_PERIA_INTA241,DTCE_PERIA_INTA242,DTCE_PERIA_INTA243, +DTCE_PERIA_INTA244,DTCE_PERIA_INTA245,DTCE_PERIA_INTA246,DTCE_PERIA_INTA247,DTCE_PERIA_INTA248,DTCE_PERIA_INTA249, +DTCE_PERIA_INTA250,DTCE_PERIA_INTA251,DTCE_PERIA_INTA252,DTCE_PERIA_INTA253,DTCE_PERIA_INTA254,DTCE_PERIA_INTA255 +} enum_dtce_t; + +typedef enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_RAM_RAMERR=0x02, +IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02, +IER_ICU_SWINT2=0x03,IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMT2_CMI2=0x03, +IER_CMT3_CMI3=0x03, +IER_RSPI0_SPRI0=0x04,IER_RSPI0_SPTI0=0x04, +IER_RI3C0_RESPI=0x05,IER_RI3C0_CMDI=0x05,IER_RI3C0_IBII=0x05,IER_RI3C0_RCVI=0x05, +IER_RSPIA0_SPRI=0x06,IER_RSPIA0_SPTI=0x06, +IER_RIIC0_RXI0=0x06,IER_RIIC0_TXI0=0x06, +IER_SCI1_RXI1=0x07,IER_SCI1_TXI1=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09, +IER_SCI5_RXI5=0x0A,IER_SCI5_TXI5=0x0A, +IER_SCI6_RXI6=0x0A,IER_SCI6_TXI6=0x0A, +IER_LVD1_LVD1=0x0B, +IER_LVD2_LVD2=0x0B, +IER_IWDT_IWUNI=0x0B, +IER_WDT_WUNI=0x0C, +IER_RSCI8_RXI=0x0C,IER_RSCI8_TXI=0x0C, +IER_RSCI9_RXI=0x0C,IER_RSCI9_TXI=0x0C, +IER_ICU_GROUPBL2=0x0D,IER_ICU_GROUPBL0=0x0D,IER_ICU_GROUPBL1=0x0D,IER_ICU_GROUPAL0=0x0E,IER_ICU_GROUPAL1=0x0E, +IER_RSCI11_RXI=0x0E,IER_RSCI11_TXI=0x0E, +IER_SCI12_RXI12=0x0E,IER_SCI12_TXI12=0x0E, +IER_RI3C0_RXI=0x0E,IER_RI3C0_TXI=0x0E, +IER_DMAC_DMAC0I=0x0F,IER_DMAC_DMAC1I=0x0F,IER_DMAC_DMAC2I=0x0F,IER_DMAC_DMAC3I=0x0F,IER_DMAC_DMAC74I=0x0F, +IER_OST_OSTDI=0x0F, +IER_S12AD_S12ADI=0x10,IER_S12AD_S12GBADI=0x10,IER_S12AD_S12GCADI=0x10, +IER_S12AD1_S12ADI1=0x10,IER_S12AD1_S12GBADI1=0x10,IER_S12AD1_S12GCADI1=0x10, +IER_S12AD2_S12ADI2=0x11,IER_S12AD2_S12GBADI2=0x11,IER_S12AD2_S12GCADI2=0x11, +IER_CANFD_RFDREQ0=0x11,IER_CANFD_RFDREQ1=0x11, +IER_CANFD0_CFDREQ0=0x11, +IER_TMR0_CMIA0=0x12,IER_TMR0_CMIB0=0x12,IER_TMR0_OVI0=0x12, +IER_TMR1_CMIA1=0x12,IER_TMR1_CMIB1=0x12,IER_TMR1_OVI1=0x12, +IER_TMR2_CMIA2=0x13,IER_TMR2_CMIB2=0x13,IER_TMR2_OVI2=0x13, +IER_TMR3_CMIA3=0x13,IER_TMR3_CMIB3=0x13,IER_TMR3_OVI3=0x13, +IER_TMR4_CMIA4=0x13,IER_TMR4_CMIB4=0x13,IER_TMR4_OVI4=0x14, +IER_TMR5_CMIA5=0x14,IER_TMR5_CMIB5=0x14,IER_TMR5_OVI5=0x14, +IER_TMR6_CMIA6=0x14,IER_TMR6_CMIB6=0x14,IER_TMR6_OVI6=0x14, +IER_TMR7_CMIA7=0x14,IER_TMR7_CMIB7=0x15,IER_TMR7_OVI7=0x15, +IER_ELC_ELSR18I=0x15,IER_ELC_ELSR19I=0x16, +IER_TSIP_RD=0x16,IER_TSIP_WR=0x16,IER_TSIP_ERR=0x16, +IER_CMPC0_CMPC0=0x16, +IER_CMPC1_CMPC1=0x16, +IER_CMPC2_CMPC2=0x16, +IER_CMPC3_CMPC3=0x16, +IER_CMPC4_CMPC4=0x17, +IER_CMPC5_CMPC5=0x17, +IER_CMTW0_CMWI0=0x17,IER_CMTW0_IC0I0=0x17,IER_CMTW0_IC1I0=0x17,IER_CMTW0_OC0I0=0x17,IER_CMTW0_OC1I0=0x17, +IER_CMTW1_CMWI1=0x17,IER_CMTW1_IC0I1=0x18,IER_CMTW1_IC1I1=0x18,IER_CMTW1_OC0I1=0x18,IER_CMTW1_OC1I1=0x18, +IER_RSCI9_AED=0x18, +IER_PERIA_INTA208=0x1A,IER_PERIA_INTA209=0x1A,IER_PERIA_INTA210=0x1A,IER_PERIA_INTA211=0x1A,IER_PERIA_INTA212=0x1A,IER_PERIA_INTA213=0x1A,IER_PERIA_INTA214=0x1A, +IER_PERIA_INTA215=0x1A,IER_PERIA_INTA216=0x1B,IER_PERIA_INTA217=0x1B,IER_PERIA_INTA218=0x1B,IER_PERIA_INTA219=0x1B,IER_PERIA_INTA220=0x1B,IER_PERIA_INTA221=0x1B, +IER_PERIA_INTA222=0x1B,IER_PERIA_INTA223=0x1B,IER_PERIA_INTA224=0x1C,IER_PERIA_INTA225=0x1C,IER_PERIA_INTA226=0x1C,IER_PERIA_INTA227=0x1C,IER_PERIA_INTA228=0x1C, +IER_PERIA_INTA229=0x1C,IER_PERIA_INTA230=0x1C,IER_PERIA_INTA231=0x1C,IER_PERIA_INTA232=0x1D,IER_PERIA_INTA233=0x1D,IER_PERIA_INTA234=0x1D,IER_PERIA_INTA235=0x1D, +IER_PERIA_INTA236=0x1D,IER_PERIA_INTA237=0x1D,IER_PERIA_INTA238=0x1D,IER_PERIA_INTA239=0x1D,IER_PERIA_INTA240=0x1E,IER_PERIA_INTA241=0x1E,IER_PERIA_INTA242=0x1E, +IER_PERIA_INTA243=0x1E,IER_PERIA_INTA244=0x1E,IER_PERIA_INTA245=0x1E,IER_PERIA_INTA246=0x1E,IER_PERIA_INTA247=0x1E,IER_PERIA_INTA248=0x1F,IER_PERIA_INTA249=0x1F, +IER_PERIA_INTA250=0x1F,IER_PERIA_INTA251=0x1F,IER_PERIA_INTA252=0x1F,IER_PERIA_INTA253=0x1F,IER_PERIA_INTA254=0x1F,IER_PERIA_INTA255=0x1F +} enum_ier_t; + +typedef enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_RAM_RAMERR=0, +IPR_FCU_FIFERR=1,IPR_FCU_FRDYI=2, +IPR_ICU_SWINT2=3,IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4, +IPR_CMT1_CMI1=5, +IPR_CMT2_CMI2=6, +IPR_CMT3_CMI3=7, +IPR_RSPI0_SPRI0=38,IPR_RSPI0_SPTI0=39, +IPR_RI3C0_RESPI=40,IPR_RI3C0_CMDI=41,IPR_RI3C0_IBII=42,IPR_RI3C0_RCVI=43, +IPR_RSPIA0_SPRI=48,IPR_RSPIA0_SPTI=49, +IPR_RIIC0_RXI0=52,IPR_RIIC0_TXI0=53, +IPR_SCI1_RXI1=60,IPR_SCI1_TXI1=61, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71, +IPR_ICU_IRQ8=72,IPR_ICU_IRQ9=73,IPR_ICU_IRQ10=74,IPR_ICU_IRQ11=75,IPR_ICU_IRQ12=76,IPR_ICU_IRQ13=77,IPR_ICU_IRQ14=78,IPR_ICU_IRQ15=79, +IPR_SCI5_RXI5=84,IPR_SCI5_TXI5=85, +IPR_SCI6_RXI6=86,IPR_SCI6_TXI6=87, +IPR_LVD1_LVD1=88, +IPR_LVD2_LVD2=89, +IPR_IWDT_IWUNI=95, +IPR_WDT_WUNI=96, +IPR_RSCI8_RXI=100,IPR_RSCI8_TXI=101, +IPR_RSCI9_RXI=102,IPR_RSCI9_TXI=103, +IPR_ICU_GROUPBL2=107,IPR_ICU_GROUPBL0=110,IPR_ICU_GROUPBL1=111,IPR_ICU_GROUPAL0=112,IPR_ICU_GROUPAL1=113, +IPR_RSCI11_RXI=114,IPR_RSCI11_TXI=115, +IPR_SCI12_RXI12=116,IPR_SCI12_TXI12=117, +IPR_RI3C0_RXI=118,IPR_RI3C0_TXI=119, +IPR_DMAC_DMAC0I=120,IPR_DMAC_DMAC1I=121,IPR_DMAC_DMAC2I=122,IPR_DMAC_DMAC3I=123,IPR_DMAC_DMAC74I=124, +IPR_OST_OSTDI=125, +IPR_S12AD_S12ADI=128,IPR_S12AD_S12GBADI=129,IPR_S12AD_S12GCADI=130, +IPR_S12AD1_S12ADI1=132,IPR_S12AD1_S12GBADI1=133,IPR_S12AD1_S12GCADI1=134, +IPR_S12AD2_S12ADI2=136,IPR_S12AD2_S12GBADI2=137,IPR_S12AD2_S12GCADI2=138, +IPR_CANFD_RFDREQ0=140,IPR_CANFD_RFDREQ1=141, +IPR_CANFD0_CFDREQ0=142, +IPR_TMR0_CMIA0=146,IPR_TMR0_CMIB0=146,IPR_TMR0_OVI0=146, +IPR_TMR1_CMIA1=149,IPR_TMR1_CMIB1=149,IPR_TMR1_OVI1=149, +IPR_TMR2_CMIA2=152,IPR_TMR2_CMIB2=152,IPR_TMR2_OVI2=152, +IPR_TMR3_CMIA3=155,IPR_TMR3_CMIB3=155,IPR_TMR3_OVI3=155, +IPR_TMR4_CMIA4=158,IPR_TMR4_CMIB4=158,IPR_TMR4_OVI4=158, +IPR_TMR5_CMIA5=161,IPR_TMR5_CMIB5=161,IPR_TMR5_OVI5=161, +IPR_TMR6_CMIA6=164,IPR_TMR6_CMIB6=164,IPR_TMR6_OVI6=164, +IPR_TMR7_CMIA7=167,IPR_TMR7_CMIB7=167,IPR_TMR7_OVI7=167, +IPR_ELC_ELSR18I=175,IPR_ELC_ELSR19I=176, +IPR_TSIP_RD=177,IPR_TSIP_WR=177,IPR_TSIP_ERR=179, +IPR_CMPC0_CMPC0=180, +IPR_CMPC1_CMPC1=181, +IPR_CMPC2_CMPC2=182, +IPR_CMPC3_CMPC3=183, +IPR_CMPC4_CMPC4=184, +IPR_CMPC5_CMPC5=185, +IPR_CMTW0_CMWI0=186,IPR_CMTW0_IC0I0=187,IPR_CMTW0_IC1I0=188,IPR_CMTW0_OC0I0=189,IPR_CMTW0_OC1I0=190, +IPR_CMTW1_CMWI1=191,IPR_CMTW1_IC0I1=192,IPR_CMTW1_IC1I1=193,IPR_CMTW1_OC0I1=194,IPR_CMTW1_OC1I1=195, +IPR_RSCI9_AED=197, +IPR_PERIA_INTA208=208,IPR_PERIA_INTA209=209,IPR_PERIA_INTA210=210,IPR_PERIA_INTA211=211,IPR_PERIA_INTA212=212,IPR_PERIA_INTA213=213, +IPR_PERIA_INTA214=214,IPR_PERIA_INTA215=215,IPR_PERIA_INTA216=216,IPR_PERIA_INTA217=217,IPR_PERIA_INTA218=218,IPR_PERIA_INTA219=219, +IPR_PERIA_INTA220=220,IPR_PERIA_INTA221=221,IPR_PERIA_INTA222=222,IPR_PERIA_INTA223=223,IPR_PERIA_INTA224=224,IPR_PERIA_INTA225=225, +IPR_PERIA_INTA226=226,IPR_PERIA_INTA227=227,IPR_PERIA_INTA228=228,IPR_PERIA_INTA229=229,IPR_PERIA_INTA230=230,IPR_PERIA_INTA231=231, +IPR_PERIA_INTA232=232,IPR_PERIA_INTA233=233,IPR_PERIA_INTA234=234,IPR_PERIA_INTA235=235,IPR_PERIA_INTA236=236,IPR_PERIA_INTA237=237, +IPR_PERIA_INTA238=238,IPR_PERIA_INTA239=239,IPR_PERIA_INTA240=240,IPR_PERIA_INTA241=241,IPR_PERIA_INTA242=242,IPR_PERIA_INTA243=243, +IPR_PERIA_INTA244=244,IPR_PERIA_INTA245=245,IPR_PERIA_INTA246=246,IPR_PERIA_INTA247=247,IPR_PERIA_INTA248=248,IPR_PERIA_INTA249=249, +IPR_PERIA_INTA250=250,IPR_PERIA_INTA251=251,IPR_PERIA_INTA252=252,IPR_PERIA_INTA253=253,IPR_PERIA_INTA254=254,IPR_PERIA_INTA255=255, +IPR_ICU_SWI=3, +IPR_CMT0_=4, +IPR_CMT1_=5, +IPR_CMT2_=6, +IPR_CMT3_=7, +IPR_LVD1_=88, +IPR_LVD2_=89, +IPR_IWDT_=95, +IPR_WDT_=96, +IPR_OST_=125, +IPR_CANFD0_=142, +IPR_TMR0_=146, +IPR_TMR1_=149, +IPR_TMR2_=152, +IPR_TMR3_=155, +IPR_TMR4_=158, +IPR_TMR5_=161, +IPR_TMR6_=164, +IPR_TMR7_=167, +IPR_CMPC0_=180, +IPR_CMPC1_=181, +IPR_CMPC2_=182, +IPR_CMPC3_=183, +IPR_CMPC4_=184, +IPR_CMPC5_=185 +} enum_ipr_t; + + +#pragma pack(4) + + +typedef struct st_bsc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char STSCLR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char STSCLR : 1; +#endif + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IGAEN : 1; + unsigned char TOEN : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TOEN : 1; + unsigned char IGAEN : 1; +#endif + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IA : 1; + unsigned char TO : 1; + unsigned char : 2; + unsigned char MST : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MST : 3; + unsigned char : 2; + unsigned char TO : 1; + unsigned char IA : 1; +#endif + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 3; + unsigned short ADDR : 13; +#else + unsigned short ADDR : 13; + unsigned short : 3; +#endif + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BPRA : 2; + unsigned short BPRO : 2; + unsigned short BPIB : 2; + unsigned short BPGB : 2; + unsigned short BPHB : 2; + unsigned short BPFB : 2; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short BPFB : 2; + unsigned short BPHB : 2; + unsigned short BPGB : 2; + unsigned short BPIB : 2; + unsigned short BPRO : 2; + unsigned short BPRA : 2; +#endif + } BIT; + } BUSPRI; +} st_bsc_t; + +typedef struct st_cac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CFME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CFME : 1; +#endif + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CACREFE : 1; + unsigned char FMCS : 3; + unsigned char TCSS : 2; + unsigned char EDGES : 2; +#else + unsigned char EDGES : 2; + unsigned char TCSS : 2; + unsigned char FMCS : 3; + unsigned char CACREFE : 1; +#endif + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RPS : 1; + unsigned char RSCS : 3; + unsigned char RCDS : 2; + unsigned char DFS : 2; +#else + unsigned char DFS : 2; + unsigned char RCDS : 2; + unsigned char RSCS : 3; + unsigned char RPS : 1; +#endif + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRIE : 1; + unsigned char MENDIE : 1; + unsigned char OVFIE : 1; + unsigned char : 1; + unsigned char FERRFCL : 1; + unsigned char MENDFCL : 1; + unsigned char OVFFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char OVFFCL : 1; + unsigned char MENDFCL : 1; + unsigned char FERRFCL : 1; + unsigned char : 1; + unsigned char OVFIE : 1; + unsigned char MENDIE : 1; + unsigned char FERRIE : 1; +#endif + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRF : 1; + unsigned char MENDF : 1; + unsigned char OVFF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char OVFF : 1; + unsigned char MENDF : 1; + unsigned char FERRF : 1; +#endif + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +} st_cac_t; + +typedef struct st_canfd { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TPRI : 1; + unsigned long DCE : 1; + unsigned long DRE : 1; + unsigned long MME : 1; + unsigned long DLLCS : 1; + unsigned long OMRC : 1; + unsigned long : 2; + unsigned long TSP : 4; + unsigned long TSCS : 1; + unsigned long : 3; + unsigned long ITP : 16; +#else + unsigned long ITP : 16; + unsigned long : 3; + unsigned long TSCS : 1; + unsigned long TSP : 4; + unsigned long : 2; + unsigned long OMRC : 1; + unsigned long DLLCS : 1; + unsigned long MME : 1; + unsigned long DRE : 1; + unsigned long DCE : 1; + unsigned long TPRI : 1; +#endif + } BIT; + } GCFG; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MDC : 2; + unsigned long SLPRQ : 1; + unsigned long : 5; + unsigned long DEIE : 1; + unsigned long MLIE : 1; + unsigned long THLIE : 1; + unsigned long POIE : 1; + unsigned long : 4; + unsigned long TSCR : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long TSCR : 1; + unsigned long : 4; + unsigned long POIE : 1; + unsigned long THLIE : 1; + unsigned long MLIE : 1; + unsigned long DEIE : 1; + unsigned long : 5; + unsigned long SLPRQ : 1; + unsigned long MDC : 2; +#endif + } BIT; + } GCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSTST : 1; + unsigned long HLTST : 1; + unsigned long SLPST : 1; + unsigned long RAMST : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long RAMST : 1; + unsigned long SLPST : 1; + unsigned long HLTST : 1; + unsigned long RSTST : 1; +#endif + } BIT; + } GSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DEDF : 1; + unsigned long MLDF : 1; + unsigned long THLDF : 1; + unsigned long PODF : 1; + unsigned long : 12; + unsigned long EEDF0 : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long EEDF0 : 1; + unsigned long : 12; + unsigned long PODF : 1; + unsigned long THLDF : 1; + unsigned long MLDF : 1; + unsigned long DEDF : 1; +#endif + } BIT; + } GESR; + unsigned long TSCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PAGE : 1; + unsigned long : 7; + unsigned long AFLWE : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long AFLWE : 1; + unsigned long : 7; + unsigned long PAGE : 1; +#endif + } BIT; + } AFCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long RN0 : 6; + unsigned long : 10; +#else + unsigned long : 10; + unsigned long RN0 : 6; + unsigned long : 16; +#endif + } BIT; + } AFCFG; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long NMB : 6; + unsigned long : 2; + unsigned long PLS : 3; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long PLS : 3; + unsigned long : 2; + unsigned long NMB : 6; +#endif + } BIT; + } RMCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long NDF : 32; +#else + unsigned long NDF : 32; +#endif + } BIT; + } RMNDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RMIE0 : 1; + unsigned long RMIE1 : 1; + unsigned long RMIE2 : 1; + unsigned long RMIE3 : 1; + unsigned long RMIE4 : 1; + unsigned long RMIE5 : 1; + unsigned long RMIE6 : 1; + unsigned long RMIE7 : 1; + unsigned long RMIE8 : 1; + unsigned long RMIE9 : 1; + unsigned long RMIE10 : 1; + unsigned long RMIE11 : 1; + unsigned long RMIE12 : 1; + unsigned long RMIE13 : 1; + unsigned long RMIE14 : 1; + unsigned long RMIE15 : 1; + unsigned long RMIE16 : 1; + unsigned long RMIE17 : 1; + unsigned long RMIE18 : 1; + unsigned long RMIE19 : 1; + unsigned long RMIE20 : 1; + unsigned long RMIE21 : 1; + unsigned long RMIE22 : 1; + unsigned long RMIE23 : 1; + unsigned long RMIE24 : 1; + unsigned long RMIE25 : 1; + unsigned long RMIE26 : 1; + unsigned long RMIE27 : 1; + unsigned long RMIE28 : 1; + unsigned long RMIE29 : 1; + unsigned long RMIE30 : 1; + unsigned long RMIE31 : 1; +#else + unsigned long RMIE31 : 1; + unsigned long RMIE30 : 1; + unsigned long RMIE29 : 1; + unsigned long RMIE28 : 1; + unsigned long RMIE27 : 1; + unsigned long RMIE26 : 1; + unsigned long RMIE25 : 1; + unsigned long RMIE24 : 1; + unsigned long RMIE23 : 1; + unsigned long RMIE22 : 1; + unsigned long RMIE21 : 1; + unsigned long RMIE20 : 1; + unsigned long RMIE19 : 1; + unsigned long RMIE18 : 1; + unsigned long RMIE17 : 1; + unsigned long RMIE16 : 1; + unsigned long RMIE15 : 1; + unsigned long RMIE14 : 1; + unsigned long RMIE13 : 1; + unsigned long RMIE12 : 1; + unsigned long RMIE11 : 1; + unsigned long RMIE10 : 1; + unsigned long RMIE9 : 1; + unsigned long RMIE8 : 1; + unsigned long RMIE7 : 1; + unsigned long RMIE6 : 1; + unsigned long RMIE5 : 1; + unsigned long RMIE4 : 1; + unsigned long RMIE3 : 1; + unsigned long RMIE2 : 1; + unsigned long RMIE1 : 1; + unsigned long RMIE0 : 1; +#endif + } BIT; + } RMIER; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFE : 1; + unsigned long RFIE : 1; + unsigned long : 2; + unsigned long PLS : 3; + unsigned long : 1; + unsigned long FDS : 3; + unsigned long : 1; + unsigned long RFIM : 1; + unsigned long RFITH : 3; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long RFITH : 3; + unsigned long RFIM : 1; + unsigned long : 1; + unsigned long FDS : 3; + unsigned long : 1; + unsigned long PLS : 3; + unsigned long : 2; + unsigned long RFIE : 1; + unsigned long RFE : 1; +#endif + } BIT; + } RFCR[2]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EMPTY : 1; + unsigned long FULL : 1; + unsigned long LOST : 1; + unsigned long RFIF : 1; + unsigned long : 4; + unsigned long FLVL : 6; + unsigned long : 18; +#else + unsigned long : 18; + unsigned long FLVL : 6; + unsigned long : 4; + unsigned long RFIF : 1; + unsigned long LOST : 1; + unsigned long FULL : 1; + unsigned long EMPTY : 1; +#endif + } BIT; + } RFSR[2]; + unsigned long RFPCR[2]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CFE : 1; + unsigned long CFRIE : 1; + unsigned long CFTIE : 1; + unsigned long : 1; + unsigned long PLS : 3; + unsigned long : 1; + unsigned long MODE : 1; + unsigned long : 1; + unsigned long ITCS : 1; + unsigned long ITR : 1; + unsigned long CFIM : 1; + unsigned long CFITH : 3; + unsigned long LTM : 2; + unsigned long : 3; + unsigned long FDS : 3; + unsigned long TINT : 8; +#else + unsigned long TINT : 8; + unsigned long FDS : 3; + unsigned long : 3; + unsigned long LTM : 2; + unsigned long CFITH : 3; + unsigned long CFIM : 1; + unsigned long ITR : 1; + unsigned long ITCS : 1; + unsigned long : 1; + unsigned long MODE : 1; + unsigned long : 1; + unsigned long PLS : 3; + unsigned long : 1; + unsigned long CFTIE : 1; + unsigned long CFRIE : 1; + unsigned long CFE : 1; +#endif + } BIT; + } CFCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EMPTY : 1; + unsigned long FULL : 1; + unsigned long LOST : 1; + unsigned long CFRIF : 1; + unsigned long CFTIF : 1; + unsigned long : 3; + unsigned long FLVL : 6; + unsigned long : 18; +#else + unsigned long : 18; + unsigned long FLVL : 6; + unsigned long : 3; + unsigned long CFTIF : 1; + unsigned long CFRIF : 1; + unsigned long LOST : 1; + unsigned long FULL : 1; + unsigned long EMPTY : 1; +#endif + } BIT; + } CFSR0; + unsigned long CFPCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFEMP0 : 1; + unsigned long RFEMP1 : 1; + unsigned long : 6; + unsigned long CFEMP0 : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long CFEMP0 : 1; + unsigned long : 6; + unsigned long RFEMP1 : 1; + unsigned long RFEMP0 : 1; +#endif + } BIT; + } FESR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFFUL0 : 1; + unsigned long RFFUL1 : 1; + unsigned long : 6; + unsigned long CFFUL0 : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long CFFUL0 : 1; + unsigned long : 6; + unsigned long RFFUL1 : 1; + unsigned long RFFUL0 : 1; +#endif + } BIT; + } FFSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFML0 : 1; + unsigned long RFML1 : 1; + unsigned long : 6; + unsigned long CFML0 : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long CFML0 : 1; + unsigned long : 6; + unsigned long RFML1 : 1; + unsigned long RFML0 : 1; +#endif + } BIT; + } FMLSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFIF0 : 1; + unsigned long RFIF1 : 1; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long RFIF1 : 1; + unsigned long RFIF0 : 1; +#endif + } BIT; + } RFISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TXRQ : 1; + unsigned char TARQ : 1; + unsigned char ONESHOT : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char ONESHOT : 1; + unsigned char TARQ : 1; + unsigned char TXRQ : 1; +#endif + } BIT; + } TMCR[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TXSF : 1; + unsigned char TXRF : 2; + unsigned char TXRQS : 1; + unsigned char TARQS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TARQS : 1; + unsigned char TXRQS : 1; + unsigned char TXRF : 2; + unsigned char TXSF : 1; +#endif + } BIT; + } TMSR[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TXRQS0 : 1; + unsigned long TXRQS1 : 1; + unsigned long TXRQS2 : 1; + unsigned long TXRQS3 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long TXRQS3 : 1; + unsigned long TXRQS2 : 1; + unsigned long TXRQS1 : 1; + unsigned long TXRQS0 : 1; +#endif + } BIT; + } TMTRSR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TARQS0 : 1; + unsigned long TARQS1 : 1; + unsigned long TARQS2 : 1; + unsigned long TARQS3 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long TARQS3 : 1; + unsigned long TARQS2 : 1; + unsigned long TARQS1 : 1; + unsigned long TARQS0 : 1; +#endif + } BIT; + } TMARSR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TXCF0 : 1; + unsigned long TXCF1 : 1; + unsigned long TXCF2 : 1; + unsigned long TXCF3 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long TXCF3 : 1; + unsigned long TXCF2 : 1; + unsigned long TXCF1 : 1; + unsigned long TXCF0 : 1; +#endif + } BIT; + } TMTCSR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TAF0 : 1; + unsigned long TAF1 : 1; + unsigned long TAF2 : 1; + unsigned long TAF3 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long TAF3 : 1; + unsigned long TAF2 : 1; + unsigned long TAF1 : 1; + unsigned long TAF0 : 1; +#endif + } BIT; + } TMTASR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TMIE0 : 1; + unsigned long TMIE1 : 1; + unsigned long TMIE2 : 1; + unsigned long TMIE3 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long TMIE3 : 1; + unsigned long TMIE2 : 1; + unsigned long TMIE1 : 1; + unsigned long TMIE0 : 1; +#endif + } BIT; + } TMIER0; + char wk0[24]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TSIF0 : 1; + unsigned long TAIF0 : 1; + unsigned long TQIF0 : 1; + unsigned long CFTIF0 : 1; + unsigned long THIF0 : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long THIF0 : 1; + unsigned long CFTIF0 : 1; + unsigned long TQIF0 : 1; + unsigned long TAIF0 : 1; + unsigned long TSIF0 : 1; +#endif + } BIT; + } TISR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long RTPS : 4; + unsigned long : 12; +#else + unsigned long : 12; + unsigned long RTPS : 4; + unsigned long : 16; +#endif + } BIT; + } GTMCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 2; + unsigned long RTME : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long RTME : 1; + unsigned long : 2; +#endif + } BIT; + } GTMER; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PXEDIS : 1; + unsigned long : 7; + unsigned long TSCPS : 2; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long TSCPS : 2; + unsigned long : 7; + unsigned long PXEDIS : 1; +#endif + } BIT; + } GFDCFG; + char wk1[4]; + unsigned long GTMLKR; + char wk2[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IGES : 5; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long IGES : 5; +#endif + } BIT; + } AFIGSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IGEE : 1; + unsigned long : 7; + unsigned long KEY : 8; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long KEY : 8; + unsigned long : 7; + unsigned long IGEE : 1; +#endif + } BIT; + } AFIGER; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFDTE0 : 1; + unsigned long RFDTE1 : 1; + unsigned long : 6; + unsigned long CFDTE0 : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long CFDTE0 : 1; + unsigned long : 6; + unsigned long RFDTE1 : 1; + unsigned long RFDTE0 : 1; +#endif + } BIT; + } DTCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFDTS0 : 1; + unsigned long RFDTS1 : 1; + unsigned long : 6; + unsigned long CFDTS0 : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long CFDTS0 : 1; + unsigned long : 6; + unsigned long RFDTS1 : 1; + unsigned long RFDTS0 : 1; +#endif + } BIT; + } DTSR; + char wk3[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SRST : 1; + unsigned long : 7; + unsigned long KEY : 8; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long KEY : 8; + unsigned long : 7; + unsigned long SRST : 1; +#endif + } BIT; + } GRCR; + char wk4[68]; + struct { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long LPC : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long LPC : 1; + unsigned long ID : 29; +#endif + } BIT; + } IDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IDM : 29; + unsigned long IFL1 : 1; + unsigned long RTRM : 1; + unsigned long IDEM : 1; +#else + unsigned long IDEM : 1; + unsigned long RTRM : 1; + unsigned long IFL1 : 1; + unsigned long IDM : 29; +#endif + } BIT; + } MASK; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DLC : 4; + unsigned long : 3; + unsigned long IFL0 : 1; + unsigned long DMB : 5; + unsigned long : 2; + unsigned long DMBE : 1; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long DMBE : 1; + unsigned long : 2; + unsigned long DMB : 5; + unsigned long IFL0 : 1; + unsigned long : 3; + unsigned long DLC : 4; +#endif + } BIT; + } PTR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RF0E : 1; + unsigned long RF1E : 1; + unsigned long : 6; + unsigned long CF0E : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long CF0E : 1; + unsigned long : 6; + unsigned long RF1E : 1; + unsigned long RF0E : 1; +#endif + } BIT; + } PTR1; + } AFL[16]; + char wk5[96]; + unsigned long RTPAR[64]; + char wk6[416]; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RFB[2]; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long THENT : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long THENT : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } CFB[1]; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long THENT : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long THENT : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 28; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 28; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } TMB[4]; + char wk7[492]; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB0; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB1; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB2; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB3; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB4; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB5; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB6; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB7; + char wk8[416]; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB8; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB9; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB10; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB11; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB12; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB13; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB14; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB15; + char wk9[416]; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB16; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB17; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB18; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB19; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB20; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB21; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB22; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB23; + char wk10[416]; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB24; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB25; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB26; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB27; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB28; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB29; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB30; + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ID : 29; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long ID : 29; +#endif + } BIT; + } HF0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TS : 16; + unsigned long : 12; + unsigned long DLC : 4; +#else + unsigned long DLC : 4; + unsigned long : 12; + unsigned long TS : 16; +#endif + } BIT; + } HF1; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ESI : 1; + unsigned long BRS : 1; + unsigned long FDF : 1; + unsigned long : 5; + unsigned long IFL : 2; + unsigned long : 6; + unsigned long PTR : 16; +#else + unsigned long PTR : 16; + unsigned long : 6; + unsigned long IFL : 2; + unsigned long : 5; + unsigned long FDF : 1; + unsigned long BRS : 1; + unsigned long ESI : 1; +#endif + } BIT; + } HF2; + union { + unsigned long DF[16]; + unsigned char DATA[64]; + }; + } RMB31; + char wk11[276608]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ECEF : 1; + unsigned long EC1EF : 1; + unsigned long EC2EF : 1; + unsigned long EC1EIE : 1; + unsigned long EC2EIE : 1; + unsigned long EC1ECD : 1; + unsigned long ECEDE : 1; + unsigned long : 2; + unsigned long EC1EC : 1; + unsigned long EC2EC : 1; + unsigned long ECOVF : 1; + unsigned long : 2; + unsigned long ECEDWC : 2; + unsigned long EC1EAS : 1; + unsigned long EC2EAS : 1; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long EC2EAS : 1; + unsigned long EC1EAS : 1; + unsigned long ECEDWC : 2; + unsigned long : 2; + unsigned long ECOVF : 1; + unsigned long EC2EC : 1; + unsigned long EC1EC : 1; + unsigned long : 2; + unsigned long ECEDE : 1; + unsigned long EC1ECD : 1; + unsigned long EC2EIE : 1; + unsigned long EC1EIE : 1; + unsigned long EC2EF : 1; + unsigned long EC1EF : 1; + unsigned long ECEF : 1; +#endif + } BIT; + } ECCSR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short ECDIS : 1; + unsigned short : 5; + unsigned short ECTME : 1; + unsigned short : 6; + unsigned short ECTMWC : 2; +#else + unsigned short ECTMWC : 2; + unsigned short : 6; + unsigned short ECTME : 1; + unsigned short : 5; + unsigned short ECDIS : 1; + unsigned short : 1; +#endif + } BIT; + } ECTMR; + char wk12[6]; + unsigned long ECTDR; + unsigned long ECEAR; +} st_canfd_t; + +typedef struct st_canfd0 { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BRP : 10; + unsigned long SJW : 7; + unsigned long TSEG1 : 8; + unsigned long TSEG2 : 7; +#else + unsigned long TSEG2 : 7; + unsigned long TSEG1 : 8; + unsigned long SJW : 7; + unsigned long BRP : 10; +#endif + } BIT; + } NBCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MDC : 2; + unsigned long SLPRQ : 1; + unsigned long RTBO : 1; + unsigned long : 4; + unsigned long BEIE : 1; + unsigned long EWIE : 1; + unsigned long EPIE : 1; + unsigned long BOEIE : 1; + unsigned long BORIE : 1; + unsigned long OLIE : 1; + unsigned long BLIE : 1; + unsigned long ALIE : 1; + unsigned long TAIE : 1; + unsigned long ECOVIE : 1; + unsigned long SCOVIE : 1; + unsigned long TDCVIE : 1; + unsigned long : 1; + unsigned long BOM : 2; + unsigned long EDM : 1; + unsigned long CTME : 1; + unsigned long CTMS : 2; + unsigned long : 3; + unsigned long BFT : 1; + unsigned long ROME : 1; +#else + unsigned long ROME : 1; + unsigned long BFT : 1; + unsigned long : 3; + unsigned long CTMS : 2; + unsigned long CTME : 1; + unsigned long EDM : 1; + unsigned long BOM : 2; + unsigned long : 1; + unsigned long TDCVIE : 1; + unsigned long SCOVIE : 1; + unsigned long ECOVIE : 1; + unsigned long TAIE : 1; + unsigned long ALIE : 1; + unsigned long BLIE : 1; + unsigned long OLIE : 1; + unsigned long BORIE : 1; + unsigned long BOEIE : 1; + unsigned long EPIE : 1; + unsigned long EWIE : 1; + unsigned long BEIE : 1; + unsigned long : 4; + unsigned long RTBO : 1; + unsigned long SLPRQ : 1; + unsigned long MDC : 2; +#endif + } BIT; + } CHCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSTST : 1; + unsigned long HLTST : 1; + unsigned long SLPST : 1; + unsigned long EPST : 1; + unsigned long BOST : 1; + unsigned long TRMST : 1; + unsigned long RECST : 1; + unsigned long CRDY : 1; + unsigned long RESI : 1; + unsigned long : 7; + unsigned long REC : 8; + unsigned long TEC : 8; +#else + unsigned long TEC : 8; + unsigned long REC : 8; + unsigned long : 7; + unsigned long RESI : 1; + unsigned long CRDY : 1; + unsigned long RECST : 1; + unsigned long TRMST : 1; + unsigned long BOST : 1; + unsigned long EPST : 1; + unsigned long SLPST : 1; + unsigned long HLTST : 1; + unsigned long RSTST : 1; +#endif + } BIT; + } CHSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BEDF : 1; + unsigned long EWDF : 1; + unsigned long EPDF : 1; + unsigned long BOEDF : 1; + unsigned long BORDF : 1; + unsigned long OLDF : 1; + unsigned long BLDF : 1; + unsigned long ALDF : 1; + unsigned long SEDF : 1; + unsigned long FEDF : 1; + unsigned long AEDF : 1; + unsigned long CEDF : 1; + unsigned long B1EDF : 1; + unsigned long B0EDF : 1; + unsigned long ADEDF : 1; + unsigned long : 1; + unsigned long CRC15 : 15; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CRC15 : 15; + unsigned long : 1; + unsigned long ADEDF : 1; + unsigned long B0EDF : 1; + unsigned long B1EDF : 1; + unsigned long CEDF : 1; + unsigned long AEDF : 1; + unsigned long FEDF : 1; + unsigned long SEDF : 1; + unsigned long ALDF : 1; + unsigned long BLDF : 1; + unsigned long OLDF : 1; + unsigned long BORDF : 1; + unsigned long BOEDF : 1; + unsigned long EPDF : 1; + unsigned long EWDF : 1; + unsigned long BEDF : 1; +#endif + } BIT; + } CHESR; + char wk0[124]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TQE : 1; + unsigned long : 4; + unsigned long TQIE : 1; + unsigned long : 1; + unsigned long TQIM : 1; + unsigned long QDS : 2; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long QDS : 2; + unsigned long TQIM : 1; + unsigned long : 1; + unsigned long TQIE : 1; + unsigned long : 4; + unsigned long TQE : 1; +#endif + } BIT; + } TQCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EMPTY : 1; + unsigned long FULL : 1; + unsigned long TQIF : 1; + unsigned long : 5; + unsigned long FLVL : 3; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long FLVL : 3; + unsigned long : 5; + unsigned long TQIF : 1; + unsigned long FULL : 1; + unsigned long EMPTY : 1; +#endif + } BIT; + } TQSR0; + unsigned long TQPCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long THE : 1; + unsigned long : 7; + unsigned long THIE : 1; + unsigned long THIM : 1; + unsigned long THRC : 1; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long THRC : 1; + unsigned long THIM : 1; + unsigned long THIE : 1; + unsigned long : 7; + unsigned long THE : 1; +#endif + } BIT; + } THCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EMPTY : 1; + unsigned long FULL : 1; + unsigned long LOST : 1; + unsigned long THIF : 1; + unsigned long : 4; + unsigned long FLVL : 4; + unsigned long : 20; +#else + unsigned long : 20; + unsigned long FLVL : 4; + unsigned long : 4; + unsigned long THIF : 1; + unsigned long LOST : 1; + unsigned long FULL : 1; + unsigned long EMPTY : 1; +#endif + } BIT; + } THSR; + unsigned long THPCR; + char wk1[92]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BRP : 8; + unsigned long TSEG1 : 5; + unsigned long : 3; + unsigned long TSEG2 : 4; + unsigned long : 4; + unsigned long SJW : 4; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long SJW : 4; + unsigned long : 4; + unsigned long TSEG2 : 4; + unsigned long : 3; + unsigned long TSEG1 : 5; + unsigned long BRP : 8; +#endif + } BIT; + } DBCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ECC : 3; + unsigned long : 5; + unsigned long SSPC : 1; + unsigned long TDCE : 1; + unsigned long TESI : 1; + unsigned long : 5; + unsigned long TDCO : 8; + unsigned long : 4; + unsigned long FDOE : 1; + unsigned long REFE : 1; + unsigned long CLOE : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CLOE : 1; + unsigned long REFE : 1; + unsigned long FDOE : 1; + unsigned long : 4; + unsigned long TDCO : 8; + unsigned long : 5; + unsigned long TESI : 1; + unsigned long TDCE : 1; + unsigned long SSPC : 1; + unsigned long : 5; + unsigned long ECC : 3; +#endif + } BIT; + } FDCFG; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ECCL : 1; + unsigned long SCCL : 1; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long SCCL : 1; + unsigned long ECCL : 1; +#endif + } BIT; + } FDCTR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TDCR : 8; + unsigned long ECOV : 1; + unsigned long SCOV : 1; + unsigned long : 5; + unsigned long TDCV : 1; + unsigned long EC : 8; + unsigned long SC : 8; +#else + unsigned long SC : 8; + unsigned long EC : 8; + unsigned long TDCV : 1; + unsigned long : 5; + unsigned long SCOV : 1; + unsigned long ECOV : 1; + unsigned long TDCR : 8; +#endif + } BIT; + } FDSTS; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CRC21 : 21; + unsigned long : 3; + unsigned long SBC : 4; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long SBC : 4; + unsigned long : 3; + unsigned long CRC21 : 21; +#endif + } BIT; + } FDCRC; + char wk2[1580]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BT : 3; + unsigned long BN : 2; + unsigned long : 11; + unsigned long TS : 16; +#else + unsigned long TS : 16; + unsigned long : 11; + unsigned long BN : 2; + unsigned long BT : 3; +#endif + } BIT; + } THACR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PTR : 16; + unsigned long IFL : 2; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long IFL : 2; + unsigned long PTR : 16; +#endif + } BIT; + } THACR1; +} st_canfd0_t; + +typedef struct st_cmpc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CINV : 1; + unsigned char COE : 1; + unsigned char : 1; + unsigned char CEG : 2; + unsigned char CDFS : 2; + unsigned char HCMPON : 1; +#else + unsigned char HCMPON : 1; + unsigned char CDFS : 2; + unsigned char CEG : 2; + unsigned char : 1; + unsigned char COE : 1; + unsigned char CINV : 1; +#endif + } BIT; + } CMPCTL; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSEL : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CMPSEL : 4; +#endif + } BIT; + } CMPSEL0; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CVRS : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CVRS : 4; +#endif + } BIT; + } CMPSEL1; + char wk2[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPMON0 : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CMPMON0 : 1; +#endif + } BIT; + } CMPMON; + char wk3[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPOE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CPOE : 1; +#endif + } BIT; + } CMPIOC; + char wk4[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CNFS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CNFS : 1; +#endif + } BIT; + } CMPCTL2; +} st_cmpc_t; + +typedef struct st_cmt { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR0 : 1; + unsigned short STR1 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR1 : 1; + unsigned short STR0 : 1; +#endif + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR2 : 1; + unsigned short STR3 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR3 : 1; + unsigned short STR2 : 1; +#endif + } BIT; + } CMSTR1; +} st_cmt_t; + +typedef struct st_cmt0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 4; + unsigned short CMIE : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMIE : 1; + unsigned short : 4; + unsigned short CKS : 2; +#endif + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +} st_cmt0_t; + +typedef struct st_cmtw { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short STR : 1; +#endif + } BIT; + } CMWSTR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 1; + unsigned short CMWIE : 1; + unsigned short IC0IE : 1; + unsigned short IC1IE : 1; + unsigned short OC0IE : 1; + unsigned short OC1IE : 1; + unsigned short : 1; + unsigned short CMS : 1; + unsigned short : 3; + unsigned short CCLR : 3; +#else + unsigned short CCLR : 3; + unsigned short : 3; + unsigned short CMS : 1; + unsigned short : 1; + unsigned short OC1IE : 1; + unsigned short OC0IE : 1; + unsigned short IC1IE : 1; + unsigned short IC0IE : 1; + unsigned short CMWIE : 1; + unsigned short : 1; + unsigned short CKS : 2; +#endif + } BIT; + } CMWCR; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short IC0 : 2; + unsigned short IC1 : 2; + unsigned short IC0E : 1; + unsigned short IC1E : 1; + unsigned short : 2; + unsigned short OC0 : 2; + unsigned short OC1 : 2; + unsigned short OC0E : 1; + unsigned short OC1E : 1; + unsigned short : 1; + unsigned short CMWE : 1; +#else + unsigned short CMWE : 1; + unsigned short : 1; + unsigned short OC1E : 1; + unsigned short OC0E : 1; + unsigned short OC1 : 2; + unsigned short OC0 : 2; + unsigned short : 2; + unsigned short IC1E : 1; + unsigned short IC0E : 1; + unsigned short IC1 : 2; + unsigned short IC0 : 2; +#endif + } BIT; + } CMWIOR; + char wk2[6]; + unsigned long CMWCNT; + unsigned long CMWCOR; + unsigned long CMWICR0; + unsigned long CMWICR1; + unsigned long CMWOCR0; + unsigned long CMWOCR1; +} st_cmtw_t; + +typedef struct st_crc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char GPS : 3; + unsigned char : 3; + unsigned char LMS : 1; + unsigned char DORCLR : 1; +#else + unsigned char DORCLR : 1; + unsigned char LMS : 1; + unsigned char : 3; + unsigned char GPS : 3; +#endif + } BIT; + } CRCCR; + char wk0[3]; + union { + unsigned long LONG; + unsigned char BYTE; + } CRCDIR; + union { + unsigned long LONG; + unsigned short WORD; + unsigned char BYTE; + } CRCDOR; +} st_crc_t; + +typedef struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char DAE : 1; + unsigned char DAOE0 : 1; + unsigned char DAOE1 : 1; +#else + unsigned char DAOE1 : 1; + unsigned char DAOE0 : 1; + unsigned char DAE : 1; + unsigned char : 5; +#endif + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DPSEL : 1; +#else + unsigned char DPSEL : 1; + unsigned char : 7; +#endif + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DAADST : 1; +#else + unsigned char DAADST : 1; + unsigned char : 7; +#endif + } BIT; + } DAADSCR; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OUTDA0 : 1; + unsigned char OUTDA1 : 1; + unsigned char OUTREF0 : 1; + unsigned char OUTREF1 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OUTREF1 : 1; + unsigned char OUTREF0 : 1; + unsigned char OUTDA1 : 1; + unsigned char OUTDA0 : 1; +#endif + } BIT; + } DADSELR; +} st_da_t; + +typedef struct st_dmac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DMST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DMST : 1; +#endif + } BIT; + } DMAST; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char DMIS4 : 1; + unsigned char DMIS5 : 1; + unsigned char DMIS6 : 1; + unsigned char DMIS7 : 1; +#else + unsigned char DMIS7 : 1; + unsigned char DMIS6 : 1; + unsigned char DMIS5 : 1; + unsigned char DMIS4 : 1; + unsigned char : 4; +#endif + } BIT; + } DMIST; +} st_dmac_t; + +typedef struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DARA : 5; + unsigned short : 1; + unsigned short DM : 2; + unsigned short SARA : 5; + unsigned short : 1; + unsigned short SM : 2; +#else + unsigned short SM : 2; + unsigned short : 1; + unsigned short SARA : 5; + unsigned short DM : 2; + unsigned short : 1; + unsigned short DARA : 5; +#endif + } BIT; + } DMAMD; + char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DISEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DISEL : 1; +#endif + } BIT; + } DMCSL; +} st_dmac0_t; + +typedef struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DARA : 5; + unsigned short : 1; + unsigned short DM : 2; + unsigned short SARA : 5; + unsigned short : 1; + unsigned short SM : 2; +#else + unsigned short SM : 2; + unsigned short : 1; + unsigned short SARA : 5; + unsigned short DM : 2; + unsigned short : 1; + unsigned short DARA : 5; +#endif + } BIT; + } DMAMD; + char wk2[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DISEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DISEL : 1; +#endif + } BIT; + } DMCSL; +} st_dmac1_t; + +typedef struct st_doc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OMS : 2; + unsigned char : 1; + unsigned char DOPSZ : 1; + unsigned char DCSEL : 3; + unsigned char DOPCIE : 1; +#else + unsigned char DOPCIE : 1; + unsigned char DCSEL : 3; + unsigned char DOPSZ : 1; + unsigned char : 1; + unsigned char OMS : 2; +#endif + } BIT; + } DOCR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DOPCF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DOPCF : 1; +#endif + } BIT; + } DOSR; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DOPCFCL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DOPCFCL : 1; +#endif + } BIT; + } DOSCR; + char wk2[3]; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + } DODIR; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + } DODSR0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + } DODSR1; +} st_doc_t; + +typedef struct st_dtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char RRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char RRS : 1; + unsigned char : 4; +#endif + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHORT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHORT : 1; +#endif + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCST : 1; +#endif + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ACT : 1; +#else + unsigned short ACT : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif + } BIT; + } DTCSTS; + void *DTCIBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SQTFRL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SQTFRL : 1; +#endif + } BIT; + } DTCOR; + char wk3[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ESPSEL : 1; +#else + unsigned short ESPSEL : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif + } BIT; + } DTCSQE; + unsigned long DTCDISP; +} st_dtc_t; + +typedef struct st_elc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ELCON : 1; +#else + unsigned char ELCON : 1; + unsigned char : 7; +#endif + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR0; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR4; + char wk1[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR7; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR10; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR11; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR12; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR13; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR15; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR16; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR18; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR19; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR20; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR21; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR22; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR23; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR24; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR25; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR26; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR27; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR28; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU0MD : 2; + unsigned char : 4; + unsigned char MTU3MD : 2; +#else + unsigned char MTU3MD : 2; + unsigned char : 4; + unsigned char MTU0MD : 2; +#endif + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU4MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MTU4MD : 2; +#endif + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char CMT1MD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CMT1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMR0MD : 2; + unsigned char TMR1MD : 2; + unsigned char TMR2MD : 2; + unsigned char TMR3MD : 2; +#else + unsigned char TMR3MD : 2; + unsigned char TMR2MD : 2; + unsigned char TMR1MD : 2; + unsigned char TMR0MD : 2; +#endif + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEG : 1; + unsigned char : 5; + unsigned char WE : 1; + unsigned char WI : 1; +#else + unsigned char WI : 1; + unsigned char WE : 1; + unsigned char : 5; + unsigned char SEG : 1; +#endif + } BIT; + } ELSEGR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR30; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR31; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR33; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR45; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU6MD : 2; + unsigned char MTU7MD : 2; + unsigned char : 2; + unsigned char MTU9MD : 2; +#else + unsigned char MTU9MD : 2; + unsigned char : 2; + unsigned char MTU7MD : 2; + unsigned char MTU6MD : 2; +#endif + } BIT; + } ELOPE; + char wk8[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMTW0MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMTW0MD : 2; +#endif + } BIT; + } ELOPH; + char wk9[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR46; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR47; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR48; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR49; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR50; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR51; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR52; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR53; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR54; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR55; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR56; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR57; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR58; +} st_elc_t; + +typedef struct st_flash { + char wk00[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLWE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char FLWE : 2; +#endif + } BIT; + } FWEPROR; + char wk0[7794397]; + unsigned long UIDR0; + char wk1[108]; + unsigned long UIDR1; + unsigned long UIDR2; + char wk2[11812]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char DFAE : 1; + unsigned char CMDLK : 1; + unsigned char : 2; + unsigned char CFAE : 1; +#else + unsigned char CFAE : 1; + unsigned char : 2; + unsigned char CMDLK : 1; + unsigned char DFAE : 1; + unsigned char : 3; +#endif + } BIT; + } FASTAT; + char wk3[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char DFAEIE : 1; + unsigned char CMDLKIE : 1; + unsigned char : 2; + unsigned char CFAEIE : 1; +#else + unsigned char CFAEIE : 1; + unsigned char : 2; + unsigned char CMDLKIE : 1; + unsigned char DFAEIE : 1; + unsigned char : 3; +#endif + } BIT; + } FAEINT; + char wk4[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FRDYIE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char FRDYIE : 1; +#endif + } BIT; + } FRDYIE; + char wk5[23]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FSADDR : 32; +#else + unsigned long FSADDR : 32; +#endif + } BIT; + } FSADDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FEADDR : 32; +#else + unsigned long FEADDR : 32; +#endif + } BIT; + } FEADDR; + char wk6[72]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 6; + unsigned long FLWEERR : 1; + unsigned long : 1; + unsigned long PRGSPD : 1; + unsigned long ERSSPD : 1; + unsigned long DBFULL : 1; + unsigned long SUSRDY : 1; + unsigned long PRGERR : 1; + unsigned long ERSERR : 1; + unsigned long ILGLERR : 1; + unsigned long FRDY : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long FRDY : 1; + unsigned long ILGLERR : 1; + unsigned long ERSERR : 1; + unsigned long PRGERR : 1; + unsigned long SUSRDY : 1; + unsigned long DBFULL : 1; + unsigned long ERSSPD : 1; + unsigned long PRGSPD : 1; + unsigned long : 1; + unsigned long FLWEERR : 1; + unsigned long : 6; +#endif + } BIT; + } FSTATR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FENTRYC : 1; + unsigned short : 6; + unsigned short FENTRYD : 1; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short FENTRYD : 1; + unsigned short : 6; + unsigned short FENTRYC : 1; +#endif + } BIT; + } FENTRYR; + char wk7[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SUINIT : 1; + unsigned short : 7; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 7; + unsigned short SUINIT : 1; +#endif + } BIT; + } FSUINITR; + char wk8[18]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PCMDR : 8; + unsigned short CMDR : 8; +#else + unsigned short CMDR : 8; + unsigned short PCMDR : 8; +#endif + } BIT; + } FCMDR; + char wk9[30]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PEERRST : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short PEERRST : 8; +#endif + } BIT; + } FPESTAT; + char wk10[14]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCDIR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCDIR : 1; +#endif + } BIT; + } FBCCNT; + char wk11[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCST : 1; +#endif + } BIT; + } FBCSTAT; + char wk12[3]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PSADR : 19; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long PSADR : 19; +#endif + } BIT; + } FPSADDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FAWS : 13; + unsigned long : 2; + unsigned long FSPR : 1; + unsigned long FAWE : 13; + unsigned long : 2; + unsigned long BTFLG : 1; +#else + unsigned long BTFLG : 1; + unsigned long : 2; + unsigned long FAWE : 13; + unsigned long FSPR : 1; + unsigned long : 2; + unsigned long FAWS : 13; +#endif + } BIT; + } FAWMON; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ESUSPMD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short ESUSPMD : 1; +#endif + } BIT; + } FCPSR; + char wk13[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PCKA : 8; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short PCKA : 8; +#endif + } BIT; + } FPCKAR; + char wk14[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SAS : 2; + unsigned short : 6; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 6; + unsigned short SAS : 2; +#endif + } BIT; + } FSUACR; +} st_flash_t; + +typedef struct st_gptw { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long UF : 1; + unsigned long VF : 1; + unsigned long WF : 1; + unsigned long : 1; + unsigned long U : 1; + unsigned long V : 1; + unsigned long W : 1; + unsigned long : 1; + unsigned long EN : 1; + unsigned long : 7; + unsigned long FB : 1; + unsigned long P : 1; + unsigned long N : 1; + unsigned long INV : 1; + unsigned long RV : 1; + unsigned long ALIGN : 1; + unsigned long : 2; + unsigned long GRP : 2; + unsigned long GODF : 1; + unsigned long : 2; + unsigned long NFEN : 1; + unsigned long NFCS : 2; +#else + unsigned long NFCS : 2; + unsigned long NFEN : 1; + unsigned long : 2; + unsigned long GODF : 1; + unsigned long GRP : 2; + unsigned long : 2; + unsigned long ALIGN : 1; + unsigned long RV : 1; + unsigned long INV : 1; + unsigned long N : 1; + unsigned long P : 1; + unsigned long FB : 1; + unsigned long : 7; + unsigned long EN : 1; + unsigned long : 1; + unsigned long W : 1; + unsigned long V : 1; + unsigned long U : 1; + unsigned long : 1; + unsigned long WF : 1; + unsigned long VF : 1; + unsigned long UF : 1; +#endif + } BIT; + } OPSCR; +} st_gptw_t; + +typedef struct st_gptw0 { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long WP : 1; + unsigned long STRWP : 1; + unsigned long STPWP : 1; + unsigned long CLRWP : 1; + unsigned long CMNWP : 1; + unsigned long : 3; + unsigned long PRKEY : 8; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long PRKEY : 8; + unsigned long : 3; + unsigned long CMNWP : 1; + unsigned long CLRWP : 1; + unsigned long STPWP : 1; + unsigned long STRWP : 1; + unsigned long WP : 1; +#endif + } BIT; + } GTWP; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSTRT0 : 1; + unsigned long CSTRT1 : 1; + unsigned long CSTRT2 : 1; + unsigned long CSTRT3 : 1; + unsigned long CSTRT4 : 1; + unsigned long CSTRT5 : 1; + unsigned long CSTRT6 : 1; + unsigned long CSTRT7 : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long CSTRT7 : 1; + unsigned long CSTRT6 : 1; + unsigned long CSTRT5 : 1; + unsigned long CSTRT4 : 1; + unsigned long CSTRT3 : 1; + unsigned long CSTRT2 : 1; + unsigned long CSTRT1 : 1; + unsigned long CSTRT0 : 1; +#endif + } BIT; + } GTSTR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSTOP0 : 1; + unsigned long CSTOP1 : 1; + unsigned long CSTOP2 : 1; + unsigned long CSTOP3 : 1; + unsigned long CSTOP4 : 1; + unsigned long CSTOP5 : 1; + unsigned long CSTOP6 : 1; + unsigned long CSTOP7 : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long CSTOP7 : 1; + unsigned long CSTOP6 : 1; + unsigned long CSTOP5 : 1; + unsigned long CSTOP4 : 1; + unsigned long CSTOP3 : 1; + unsigned long CSTOP2 : 1; + unsigned long CSTOP1 : 1; + unsigned long CSTOP0 : 1; +#endif + } BIT; + } GTSTP; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CCLR0 : 1; + unsigned long CCLR1 : 1; + unsigned long CCLR2 : 1; + unsigned long CCLR3 : 1; + unsigned long CCLR4 : 1; + unsigned long CCLR5 : 1; + unsigned long CCLR6 : 1; + unsigned long CCLR7 : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long CCLR7 : 1; + unsigned long CCLR6 : 1; + unsigned long CCLR5 : 1; + unsigned long CCLR4 : 1; + unsigned long CCLR3 : 1; + unsigned long CCLR2 : 1; + unsigned long CCLR1 : 1; + unsigned long CCLR0 : 1; +#endif + } BIT; + } GTCLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SSGTRGAR : 1; + unsigned long SSGTRGAF : 1; + unsigned long SSGTRGBR : 1; + unsigned long SSGTRGBF : 1; + unsigned long SSGTRGCR : 1; + unsigned long SSGTRGCF : 1; + unsigned long SSGTRGDR : 1; + unsigned long SSGTRGDF : 1; + unsigned long SSCARBL : 1; + unsigned long SSCARBH : 1; + unsigned long SSCAFBL : 1; + unsigned long SSCAFBH : 1; + unsigned long SSCBRAL : 1; + unsigned long SSCBRAH : 1; + unsigned long SSCBFAL : 1; + unsigned long SSCBFAH : 1; + unsigned long SSELCA : 1; + unsigned long SSELCB : 1; + unsigned long SSELCC : 1; + unsigned long SSELCD : 1; + unsigned long SSELCE : 1; + unsigned long SSELCF : 1; + unsigned long SSELCG : 1; + unsigned long SSELCH : 1; + unsigned long : 7; + unsigned long CSTRT : 1; +#else + unsigned long CSTRT : 1; + unsigned long : 7; + unsigned long SSELCH : 1; + unsigned long SSELCG : 1; + unsigned long SSELCF : 1; + unsigned long SSELCE : 1; + unsigned long SSELCD : 1; + unsigned long SSELCC : 1; + unsigned long SSELCB : 1; + unsigned long SSELCA : 1; + unsigned long SSCBFAH : 1; + unsigned long SSCBFAL : 1; + unsigned long SSCBRAH : 1; + unsigned long SSCBRAL : 1; + unsigned long SSCAFBH : 1; + unsigned long SSCAFBL : 1; + unsigned long SSCARBH : 1; + unsigned long SSCARBL : 1; + unsigned long SSGTRGDF : 1; + unsigned long SSGTRGDR : 1; + unsigned long SSGTRGCF : 1; + unsigned long SSGTRGCR : 1; + unsigned long SSGTRGBF : 1; + unsigned long SSGTRGBR : 1; + unsigned long SSGTRGAF : 1; + unsigned long SSGTRGAR : 1; +#endif + } BIT; + } GTSSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PSGTRGAR : 1; + unsigned long PSGTRGAF : 1; + unsigned long PSGTRGBR : 1; + unsigned long PSGTRGBF : 1; + unsigned long PSGTRGCR : 1; + unsigned long PSGTRGCF : 1; + unsigned long PSGTRGDR : 1; + unsigned long PSGTRGDF : 1; + unsigned long PSCARBL : 1; + unsigned long PSCARBH : 1; + unsigned long PSCAFBL : 1; + unsigned long PSCAFBH : 1; + unsigned long PSCBRAL : 1; + unsigned long PSCBRAH : 1; + unsigned long PSCBFAL : 1; + unsigned long PSCBFAH : 1; + unsigned long PSELCA : 1; + unsigned long PSELCB : 1; + unsigned long PSELCC : 1; + unsigned long PSELCD : 1; + unsigned long PSELCE : 1; + unsigned long PSELCF : 1; + unsigned long PSELCG : 1; + unsigned long PSELCH : 1; + unsigned long : 7; + unsigned long CSTOP : 1; +#else + unsigned long CSTOP : 1; + unsigned long : 7; + unsigned long PSELCH : 1; + unsigned long PSELCG : 1; + unsigned long PSELCF : 1; + unsigned long PSELCE : 1; + unsigned long PSELCD : 1; + unsigned long PSELCC : 1; + unsigned long PSELCB : 1; + unsigned long PSELCA : 1; + unsigned long PSCBFAH : 1; + unsigned long PSCBFAL : 1; + unsigned long PSCBRAH : 1; + unsigned long PSCBRAL : 1; + unsigned long PSCAFBH : 1; + unsigned long PSCAFBL : 1; + unsigned long PSCARBH : 1; + unsigned long PSCARBL : 1; + unsigned long PSGTRGDF : 1; + unsigned long PSGTRGDR : 1; + unsigned long PSGTRGCF : 1; + unsigned long PSGTRGCR : 1; + unsigned long PSGTRGBF : 1; + unsigned long PSGTRGBR : 1; + unsigned long PSGTRGAF : 1; + unsigned long PSGTRGAR : 1; +#endif + } BIT; + } GTPSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSGTRGAR : 1; + unsigned long CSGTRGAF : 1; + unsigned long CSGTRGBR : 1; + unsigned long CSGTRGBF : 1; + unsigned long CSGTRGCR : 1; + unsigned long CSGTRGCF : 1; + unsigned long CSGTRGDR : 1; + unsigned long CSGTRGDF : 1; + unsigned long CSCARBL : 1; + unsigned long CSCARBH : 1; + unsigned long CSCAFBL : 1; + unsigned long CSCAFBH : 1; + unsigned long CSCBRAL : 1; + unsigned long CSCBRAH : 1; + unsigned long CSCBFAL : 1; + unsigned long CSCBFAH : 1; + unsigned long CSELCA : 1; + unsigned long CSELCB : 1; + unsigned long CSELCC : 1; + unsigned long CSELCD : 1; + unsigned long CSELCE : 1; + unsigned long CSELCF : 1; + unsigned long CSELCG : 1; + unsigned long CSELCH : 1; + unsigned long CSCMSC : 3; + unsigned long CP1CCE : 1; + unsigned long : 3; + unsigned long CCLR : 1; +#else + unsigned long CCLR : 1; + unsigned long : 3; + unsigned long CP1CCE : 1; + unsigned long CSCMSC : 3; + unsigned long CSELCH : 1; + unsigned long CSELCG : 1; + unsigned long CSELCF : 1; + unsigned long CSELCE : 1; + unsigned long CSELCD : 1; + unsigned long CSELCC : 1; + unsigned long CSELCB : 1; + unsigned long CSELCA : 1; + unsigned long CSCBFAH : 1; + unsigned long CSCBFAL : 1; + unsigned long CSCBRAH : 1; + unsigned long CSCBRAL : 1; + unsigned long CSCAFBH : 1; + unsigned long CSCAFBL : 1; + unsigned long CSCARBH : 1; + unsigned long CSCARBL : 1; + unsigned long CSGTRGDF : 1; + unsigned long CSGTRGDR : 1; + unsigned long CSGTRGCF : 1; + unsigned long CSGTRGCR : 1; + unsigned long CSGTRGBF : 1; + unsigned long CSGTRGBR : 1; + unsigned long CSGTRGAF : 1; + unsigned long CSGTRGAR : 1; +#endif + } BIT; + } GTCSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long USGTRGAR : 1; + unsigned long USGTRGAF : 1; + unsigned long USGTRGBR : 1; + unsigned long USGTRGBF : 1; + unsigned long USGTRGCR : 1; + unsigned long USGTRGCF : 1; + unsigned long USGTRGDR : 1; + unsigned long USGTRGDF : 1; + unsigned long USCARBL : 1; + unsigned long USCARBH : 1; + unsigned long USCAFBL : 1; + unsigned long USCAFBH : 1; + unsigned long USCBRAL : 1; + unsigned long USCBRAH : 1; + unsigned long USCBFAL : 1; + unsigned long USCBFAH : 1; + unsigned long USELCA : 1; + unsigned long USELCB : 1; + unsigned long USELCC : 1; + unsigned long USELCD : 1; + unsigned long USELCE : 1; + unsigned long USELCF : 1; + unsigned long USELCG : 1; + unsigned long USELCH : 1; + unsigned long USILVL : 4; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long USILVL : 4; + unsigned long USELCH : 1; + unsigned long USELCG : 1; + unsigned long USELCF : 1; + unsigned long USELCE : 1; + unsigned long USELCD : 1; + unsigned long USELCC : 1; + unsigned long USELCB : 1; + unsigned long USELCA : 1; + unsigned long USCBFAH : 1; + unsigned long USCBFAL : 1; + unsigned long USCBRAH : 1; + unsigned long USCBRAL : 1; + unsigned long USCAFBH : 1; + unsigned long USCAFBL : 1; + unsigned long USCARBH : 1; + unsigned long USCARBL : 1; + unsigned long USGTRGDF : 1; + unsigned long USGTRGDR : 1; + unsigned long USGTRGCF : 1; + unsigned long USGTRGCR : 1; + unsigned long USGTRGBF : 1; + unsigned long USGTRGBR : 1; + unsigned long USGTRGAF : 1; + unsigned long USGTRGAR : 1; +#endif + } BIT; + } GTUPSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DSGTRGAR : 1; + unsigned long DSGTRGAF : 1; + unsigned long DSGTRGBR : 1; + unsigned long DSGTRGBF : 1; + unsigned long DSGTRGCR : 1; + unsigned long DSGTRGCF : 1; + unsigned long DSGTRGDR : 1; + unsigned long DSGTRGDF : 1; + unsigned long DSCARBL : 1; + unsigned long DSCARBH : 1; + unsigned long DSCAFBL : 1; + unsigned long DSCAFBH : 1; + unsigned long DSCBRAL : 1; + unsigned long DSCBRAH : 1; + unsigned long DSCBFAL : 1; + unsigned long DSCBFAH : 1; + unsigned long DSELCA : 1; + unsigned long DSELCB : 1; + unsigned long DSELCC : 1; + unsigned long DSELCD : 1; + unsigned long DSELCE : 1; + unsigned long DSELCF : 1; + unsigned long DSELCG : 1; + unsigned long DSELCH : 1; + unsigned long DSILVL : 4; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long DSILVL : 4; + unsigned long DSELCH : 1; + unsigned long DSELCG : 1; + unsigned long DSELCF : 1; + unsigned long DSELCE : 1; + unsigned long DSELCD : 1; + unsigned long DSELCC : 1; + unsigned long DSELCB : 1; + unsigned long DSELCA : 1; + unsigned long DSCBFAH : 1; + unsigned long DSCBFAL : 1; + unsigned long DSCBRAH : 1; + unsigned long DSCBRAL : 1; + unsigned long DSCAFBH : 1; + unsigned long DSCAFBL : 1; + unsigned long DSCARBH : 1; + unsigned long DSCARBL : 1; + unsigned long DSGTRGDF : 1; + unsigned long DSGTRGDR : 1; + unsigned long DSGTRGCF : 1; + unsigned long DSGTRGCR : 1; + unsigned long DSGTRGBF : 1; + unsigned long DSGTRGBR : 1; + unsigned long DSGTRGAF : 1; + unsigned long DSGTRGAR : 1; +#endif + } BIT; + } GTDNSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ASGTRGAR : 1; + unsigned long ASGTRGAF : 1; + unsigned long ASGTRGBR : 1; + unsigned long ASGTRGBF : 1; + unsigned long ASGTRGCR : 1; + unsigned long ASGTRGCF : 1; + unsigned long ASGTRGDR : 1; + unsigned long ASGTRGDF : 1; + unsigned long ASCARBL : 1; + unsigned long ASCARBH : 1; + unsigned long ASCAFBL : 1; + unsigned long ASCAFBH : 1; + unsigned long ASCBRAL : 1; + unsigned long ASCBRAH : 1; + unsigned long ASCBFAL : 1; + unsigned long ASCBFAH : 1; + unsigned long ASELCA : 1; + unsigned long ASELCB : 1; + unsigned long ASELCC : 1; + unsigned long ASELCD : 1; + unsigned long ASELCE : 1; + unsigned long ASELCF : 1; + unsigned long ASELCG : 1; + unsigned long ASELCH : 1; + unsigned long ASOC : 1; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long ASOC : 1; + unsigned long ASELCH : 1; + unsigned long ASELCG : 1; + unsigned long ASELCF : 1; + unsigned long ASELCE : 1; + unsigned long ASELCD : 1; + unsigned long ASELCC : 1; + unsigned long ASELCB : 1; + unsigned long ASELCA : 1; + unsigned long ASCBFAH : 1; + unsigned long ASCBFAL : 1; + unsigned long ASCBRAH : 1; + unsigned long ASCBRAL : 1; + unsigned long ASCAFBH : 1; + unsigned long ASCAFBL : 1; + unsigned long ASCARBH : 1; + unsigned long ASCARBL : 1; + unsigned long ASGTRGDF : 1; + unsigned long ASGTRGDR : 1; + unsigned long ASGTRGCF : 1; + unsigned long ASGTRGCR : 1; + unsigned long ASGTRGBF : 1; + unsigned long ASGTRGBR : 1; + unsigned long ASGTRGAF : 1; + unsigned long ASGTRGAR : 1; +#endif + } BIT; + } GTICASR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BSGTRGAR : 1; + unsigned long BSGTRGAF : 1; + unsigned long BSGTRGBR : 1; + unsigned long BSGTRGBF : 1; + unsigned long BSGTRGCR : 1; + unsigned long BSGTRGCF : 1; + unsigned long BSGTRGDR : 1; + unsigned long BSGTRGDF : 1; + unsigned long BSCARBL : 1; + unsigned long BSCARBH : 1; + unsigned long BSCAFBL : 1; + unsigned long BSCAFBH : 1; + unsigned long BSCBRAL : 1; + unsigned long BSCBRAH : 1; + unsigned long BSCBFAL : 1; + unsigned long BSCBFAH : 1; + unsigned long BSELCA : 1; + unsigned long BSELCB : 1; + unsigned long BSELCC : 1; + unsigned long BSELCD : 1; + unsigned long BSELCE : 1; + unsigned long BSELCF : 1; + unsigned long BSELCG : 1; + unsigned long BSELCH : 1; + unsigned long BSOC : 1; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long BSOC : 1; + unsigned long BSELCH : 1; + unsigned long BSELCG : 1; + unsigned long BSELCF : 1; + unsigned long BSELCE : 1; + unsigned long BSELCD : 1; + unsigned long BSELCC : 1; + unsigned long BSELCB : 1; + unsigned long BSELCA : 1; + unsigned long BSCBFAH : 1; + unsigned long BSCBFAL : 1; + unsigned long BSCBRAH : 1; + unsigned long BSCBRAL : 1; + unsigned long BSCAFBH : 1; + unsigned long BSCAFBL : 1; + unsigned long BSCARBH : 1; + unsigned long BSCARBL : 1; + unsigned long BSGTRGDF : 1; + unsigned long BSGTRGDR : 1; + unsigned long BSGTRGCF : 1; + unsigned long BSGTRGCR : 1; + unsigned long BSGTRGBF : 1; + unsigned long BSGTRGBR : 1; + unsigned long BSGTRGAF : 1; + unsigned long BSGTRGAR : 1; +#endif + } BIT; + } GTICBSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CST : 1; + unsigned long : 7; + unsigned long ICDS : 1; + unsigned long SCGTIOC : 1; + unsigned long SSCGRP : 2; + unsigned long : 3; + unsigned long SSCEN : 1; + unsigned long MD : 4; + unsigned long : 3; + unsigned long TPCS : 4; + unsigned long CKEG : 2; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CKEG : 2; + unsigned long TPCS : 4; + unsigned long : 3; + unsigned long MD : 4; + unsigned long SSCEN : 1; + unsigned long : 3; + unsigned long SSCGRP : 2; + unsigned long SCGTIOC : 1; + unsigned long ICDS : 1; + unsigned long : 7; + unsigned long CST : 1; +#endif + } BIT; + } GTCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long UD : 1; + unsigned long UDF : 1; + unsigned long : 14; + unsigned long OADTY : 2; + unsigned long OADTYF : 1; + unsigned long OADTYR : 1; + unsigned long : 4; + unsigned long OBDTY : 2; + unsigned long OBDTYF : 1; + unsigned long OBDTYR : 1; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long OBDTYR : 1; + unsigned long OBDTYF : 1; + unsigned long OBDTY : 2; + unsigned long : 4; + unsigned long OADTYR : 1; + unsigned long OADTYF : 1; + unsigned long OADTY : 2; + unsigned long : 14; + unsigned long UDF : 1; + unsigned long UD : 1; +#endif + } BIT; + } GTUDDTYC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GTIOA : 5; + unsigned long CPSCIR : 1; + unsigned long OADFLT : 1; + unsigned long OAHLD : 1; + unsigned long OAE : 1; + unsigned long OADF : 2; + unsigned long OAEOCD : 1; + unsigned long PSYE : 1; + unsigned long NFAEN : 1; + unsigned long NFCSA : 2; + unsigned long GTIOB : 5; + unsigned long : 1; + unsigned long OBDFLT : 1; + unsigned long OBHLD : 1; + unsigned long OBE : 1; + unsigned long OBDF : 2; + unsigned long OBEOCD : 1; + unsigned long : 1; + unsigned long NFBEN : 1; + unsigned long NFCSB : 2; +#else + unsigned long NFCSB : 2; + unsigned long NFBEN : 1; + unsigned long : 1; + unsigned long OBEOCD : 1; + unsigned long OBDF : 2; + unsigned long OBE : 1; + unsigned long OBHLD : 1; + unsigned long OBDFLT : 1; + unsigned long : 1; + unsigned long GTIOB : 5; + unsigned long NFCSA : 2; + unsigned long NFAEN : 1; + unsigned long PSYE : 1; + unsigned long OAEOCD : 1; + unsigned long OADF : 2; + unsigned long OAE : 1; + unsigned long OAHLD : 1; + unsigned long OADFLT : 1; + unsigned long CPSCIR : 1; + unsigned long GTIOA : 5; +#endif + } BIT; + } GTIOR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GTINTA : 1; + unsigned long GTINTB : 1; + unsigned long GTINTC : 1; + unsigned long GTINTD : 1; + unsigned long GTINTE : 1; + unsigned long GTINTF : 1; + unsigned long GTINTPR : 2; + unsigned long SCFA : 1; + unsigned long SCFB : 1; + unsigned long SCFC : 1; + unsigned long SCFD : 1; + unsigned long SCFE : 1; + unsigned long SCFF : 1; + unsigned long SCFPO : 1; + unsigned long SCFPU : 1; + unsigned long ADTRAUEN : 1; + unsigned long ADTRADEN : 1; + unsigned long ADTRBUEN : 1; + unsigned long ADTRBDEN : 1; + unsigned long : 4; + unsigned long GRP : 2; + unsigned long : 2; + unsigned long GRPDTE : 1; + unsigned long GRPABH : 1; + unsigned long GRPABL : 1; + unsigned long GTINTPC : 1; +#else + unsigned long GTINTPC : 1; + unsigned long GRPABL : 1; + unsigned long GRPABH : 1; + unsigned long GRPDTE : 1; + unsigned long : 2; + unsigned long GRP : 2; + unsigned long : 4; + unsigned long ADTRBDEN : 1; + unsigned long ADTRBUEN : 1; + unsigned long ADTRADEN : 1; + unsigned long ADTRAUEN : 1; + unsigned long SCFPU : 1; + unsigned long SCFPO : 1; + unsigned long SCFF : 1; + unsigned long SCFE : 1; + unsigned long SCFD : 1; + unsigned long SCFC : 1; + unsigned long SCFB : 1; + unsigned long SCFA : 1; + unsigned long GTINTPR : 2; + unsigned long GTINTF : 1; + unsigned long GTINTE : 1; + unsigned long GTINTD : 1; + unsigned long GTINTC : 1; + unsigned long GTINTB : 1; + unsigned long GTINTA : 1; +#endif + } BIT; + } GTINTAD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TCFA : 1; + unsigned long TCFB : 1; + unsigned long TCFC : 1; + unsigned long TCFD : 1; + unsigned long TCFE : 1; + unsigned long TCFF : 1; + unsigned long TCFPO : 1; + unsigned long TCFPU : 1; + unsigned long ITCNT : 3; + unsigned long : 4; + unsigned long TUCF : 1; + unsigned long ADTRAUF : 1; + unsigned long ADTRADF : 1; + unsigned long ADTRBUF : 1; + unsigned long ADTRBDF : 1; + unsigned long : 4; + unsigned long ODF : 1; + unsigned long : 3; + unsigned long DTEF : 1; + unsigned long OABHF : 1; + unsigned long OABLF : 1; + unsigned long PCF : 1; +#else + unsigned long PCF : 1; + unsigned long OABLF : 1; + unsigned long OABHF : 1; + unsigned long DTEF : 1; + unsigned long : 3; + unsigned long ODF : 1; + unsigned long : 4; + unsigned long ADTRBDF : 1; + unsigned long ADTRBUF : 1; + unsigned long ADTRADF : 1; + unsigned long ADTRAUF : 1; + unsigned long TUCF : 1; + unsigned long : 4; + unsigned long ITCNT : 3; + unsigned long TCFPU : 1; + unsigned long TCFPO : 1; + unsigned long TCFF : 1; + unsigned long TCFE : 1; + unsigned long TCFD : 1; + unsigned long TCFC : 1; + unsigned long TCFB : 1; + unsigned long TCFA : 1; +#endif + } BIT; + } GTST; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BD : 4; + unsigned long : 4; + unsigned long DBRTECA : 1; + unsigned long DBRTSCA : 1; + unsigned long DBRTECB : 1; + unsigned long DBRTSCB : 1; + unsigned long DBRTEADA : 1; + unsigned long DBRTSADA : 1; + unsigned long DBRTEADB : 1; + unsigned long DBRTSADB : 1; + unsigned long CCRA : 2; + unsigned long CCRB : 2; + unsigned long PR : 2; + unsigned long CCRSWT : 1; + unsigned long : 1; + unsigned long ADTTA : 2; + unsigned long ADTDA : 1; + unsigned long : 1; + unsigned long ADTTB : 2; + unsigned long ADTDB : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long ADTDB : 1; + unsigned long ADTTB : 2; + unsigned long : 1; + unsigned long ADTDA : 1; + unsigned long ADTTA : 2; + unsigned long : 1; + unsigned long CCRSWT : 1; + unsigned long PR : 2; + unsigned long CCRB : 2; + unsigned long CCRA : 2; + unsigned long DBRTSADB : 1; + unsigned long DBRTEADB : 1; + unsigned long DBRTSADA : 1; + unsigned long DBRTEADA : 1; + unsigned long DBRTSCB : 1; + unsigned long DBRTECB : 1; + unsigned long DBRTSCA : 1; + unsigned long DBRTECA : 1; + unsigned long : 4; + unsigned long BD : 4; +#endif + } BIT; + } GTBER; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ITLA : 1; + unsigned long ITLB : 1; + unsigned long ITLC : 1; + unsigned long ITLD : 1; + unsigned long ITLE : 1; + unsigned long ITLF : 1; + unsigned long IVTC : 2; + unsigned long IVTT : 3; + unsigned long : 1; + unsigned long ADTAL : 1; + unsigned long : 1; + unsigned long ADTBL : 1; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long ADTBL : 1; + unsigned long : 1; + unsigned long ADTAL : 1; + unsigned long : 1; + unsigned long IVTT : 3; + unsigned long IVTC : 2; + unsigned long ITLF : 1; + unsigned long ITLE : 1; + unsigned long ITLD : 1; + unsigned long ITLC : 1; + unsigned long ITLB : 1; + unsigned long ITLA : 1; +#endif + } BIT; + } GTITC; + unsigned long GTCNT; + unsigned long GTCCRA; + unsigned long GTCCRB; + unsigned long GTCCRC; + unsigned long GTCCRE; + unsigned long GTCCRD; + unsigned long GTCCRF; + unsigned long GTPR; + unsigned long GTPBR; + unsigned long GTPDBR; + unsigned long GTADTRA; + unsigned long GTADTBRA; + unsigned long GTADTDBRA; + unsigned long GTADTRB; + unsigned long GTADTBRB; + unsigned long GTADTDBRB; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TDE : 1; + unsigned long : 3; + unsigned long TDBUE : 1; + unsigned long TDBDE : 1; + unsigned long : 2; + unsigned long TDFER : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long TDFER : 1; + unsigned long : 2; + unsigned long TDBDE : 1; + unsigned long TDBUE : 1; + unsigned long : 3; + unsigned long TDE : 1; +#endif + } BIT; + } GTDTCR; + unsigned long GTDVU; + unsigned long GTDVD; + unsigned long GTDBU; + unsigned long GTDBD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SOS : 2; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long SOS : 2; +#endif + } BIT; + } GTSOS; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SOTR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long SOTR : 1; +#endif + } BIT; + } GTSOTR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ADSMS0 : 2; + unsigned long : 6; + unsigned long ADSMEN0 : 1; + unsigned long : 7; + unsigned long ADSMS1 : 2; + unsigned long : 6; + unsigned long ADSMEN1 : 1; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long ADSMEN1 : 1; + unsigned long : 6; + unsigned long ADSMS1 : 2; + unsigned long : 7; + unsigned long ADSMEN0 : 1; + unsigned long : 6; + unsigned long ADSMS0 : 2; +#endif + } BIT; + } GTADSMR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EIVTC1 : 2; + unsigned long : 2; + unsigned long EIVTT1 : 4; + unsigned long : 4; + unsigned long EITCNT1 : 4; + unsigned long EIVTC2 : 2; + unsigned long : 2; + unsigned long EIVTT2 : 4; + unsigned long EITCNT2IV : 4; + unsigned long EITCNT2 : 4; +#else + unsigned long EITCNT2 : 4; + unsigned long EITCNT2IV : 4; + unsigned long EIVTT2 : 4; + unsigned long : 2; + unsigned long EIVTC2 : 2; + unsigned long EITCNT1 : 4; + unsigned long : 4; + unsigned long EIVTT1 : 4; + unsigned long : 2; + unsigned long EIVTC1 : 2; +#endif + } BIT; + } GTEITC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EITLA : 3; + unsigned long : 1; + unsigned long EITLB : 3; + unsigned long : 1; + unsigned long EITLC : 3; + unsigned long : 1; + unsigned long EITLD : 3; + unsigned long : 1; + unsigned long EITLE : 3; + unsigned long : 1; + unsigned long EITLF : 3; + unsigned long : 1; + unsigned long EITLV : 3; + unsigned long : 1; + unsigned long EITLU : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long EITLU : 3; + unsigned long : 1; + unsigned long EITLV : 3; + unsigned long : 1; + unsigned long EITLF : 3; + unsigned long : 1; + unsigned long EITLE : 3; + unsigned long : 1; + unsigned long EITLD : 3; + unsigned long : 1; + unsigned long EITLC : 3; + unsigned long : 1; + unsigned long EITLB : 3; + unsigned long : 1; + unsigned long EITLA : 3; +#endif + } BIT; + } GTEITLI1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EADTAL : 3; + unsigned long : 1; + unsigned long EADTBL : 3; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long EADTBL : 3; + unsigned long : 1; + unsigned long EADTAL : 3; +#endif + } BIT; + } GTEITLI2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EBTLCA : 3; + unsigned long : 1; + unsigned long EBTLCB : 3; + unsigned long : 1; + unsigned long EBTLPR : 3; + unsigned long : 5; + unsigned long EBTLADA : 3; + unsigned long : 1; + unsigned long EBTLADB : 3; + unsigned long : 1; + unsigned long EBTLDVU : 3; + unsigned long : 1; + unsigned long EBTLDVD : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long EBTLDVD : 3; + unsigned long : 1; + unsigned long EBTLDVU : 3; + unsigned long : 1; + unsigned long EBTLADB : 3; + unsigned long : 1; + unsigned long EBTLADA : 3; + unsigned long : 5; + unsigned long EBTLPR : 3; + unsigned long : 1; + unsigned long EBTLCB : 3; + unsigned long : 1; + unsigned long EBTLCA : 3; +#endif + } BIT; + } GTEITLB; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ICLFA : 3; + unsigned long : 1; + unsigned long ICLFSELC : 6; + unsigned long : 6; + unsigned long ICLFB : 3; + unsigned long : 1; + unsigned long ICLFSELD : 6; + unsigned long : 6; +#else + unsigned long : 6; + unsigned long ICLFSELD : 6; + unsigned long : 1; + unsigned long ICLFB : 3; + unsigned long : 6; + unsigned long ICLFSELC : 6; + unsigned long : 1; + unsigned long ICLFA : 3; +#endif + } BIT; + } GTICLF; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCEN : 1; + unsigned long : 7; + unsigned long ASTP : 1; + unsigned long : 7; + unsigned long PCNT : 12; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long PCNT : 12; + unsigned long : 7; + unsigned long ASTP : 1; + unsigned long : 7; + unsigned long PCEN : 1; +#endif + } BIT; + } GTPC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ADCMSC1 : 2; + unsigned long : 2; + unsigned long ADCMST1 : 4; + unsigned long ADCMSCNT1IV : 4; + unsigned long ADCMSCNT1 : 4; + unsigned long ADCMSC2 : 2; + unsigned long : 2; + unsigned long ADCMST2 : 4; + unsigned long ADCMSCNT2IV : 4; + unsigned long ADCMSCNT2 : 4; +#else + unsigned long ADCMSCNT2 : 4; + unsigned long ADCMSCNT2IV : 4; + unsigned long ADCMST2 : 4; + unsigned long : 2; + unsigned long ADCMSC2 : 2; + unsigned long ADCMSCNT1 : 4; + unsigned long ADCMSCNT1IV : 4; + unsigned long ADCMST1 : 4; + unsigned long : 2; + unsigned long ADCMSC1 : 2; +#endif + } BIT; + } GTADCMSC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ADCMSAL : 3; + unsigned long : 1; + unsigned long ADCMSBL : 3; + unsigned long : 9; + unsigned long ADCMBSA : 3; + unsigned long : 1; + unsigned long ADCMBSB : 3; + unsigned long : 9; +#else + unsigned long : 9; + unsigned long ADCMBSB : 3; + unsigned long : 1; + unsigned long ADCMBSA : 3; + unsigned long : 9; + unsigned long ADCMSBL : 3; + unsigned long : 1; + unsigned long ADCMSAL : 3; +#endif + } BIT; + } GTADCMSS; + char wk0[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SECSEL0 : 1; + unsigned long SECSEL1 : 1; + unsigned long SECSEL2 : 1; + unsigned long SECSEL3 : 1; + unsigned long SECSEL4 : 1; + unsigned long SECSEL5 : 1; + unsigned long SECSEL6 : 1; + unsigned long SECSEL7 : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long SECSEL7 : 1; + unsigned long SECSEL6 : 1; + unsigned long SECSEL5 : 1; + unsigned long SECSEL4 : 1; + unsigned long SECSEL3 : 1; + unsigned long SECSEL2 : 1; + unsigned long SECSEL1 : 1; + unsigned long SECSEL0 : 1; +#endif + } BIT; + } GTSECSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SBDCE : 1; + unsigned long SBDPE : 1; + unsigned long SBDAE : 1; + unsigned long SBDDE : 1; + unsigned long : 4; + unsigned long SBDCD : 1; + unsigned long SBDPD : 1; + unsigned long SBDAD : 1; + unsigned long SBDDD : 1; + unsigned long : 4; + unsigned long SPCE : 1; + unsigned long SSCE : 1; + unsigned long : 6; + unsigned long SPCD : 1; + unsigned long SSCD : 1; + unsigned long : 6; +#else + unsigned long : 6; + unsigned long SSCD : 1; + unsigned long SPCD : 1; + unsigned long : 6; + unsigned long SSCE : 1; + unsigned long SPCE : 1; + unsigned long : 4; + unsigned long SBDDD : 1; + unsigned long SBDAD : 1; + unsigned long SBDPD : 1; + unsigned long SBDCD : 1; + unsigned long : 4; + unsigned long SBDDE : 1; + unsigned long SBDAE : 1; + unsigned long SBDPE : 1; + unsigned long SBDCE : 1; +#endif + } BIT; + } GTSECR; + char wk1[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CCTCA : 1; + unsigned long CCTCB : 1; + unsigned long CCTPR : 1; + unsigned long CCTADA : 1; + unsigned long CCTADB : 1; + unsigned long CCTDV : 1; + unsigned long : 2; + unsigned long CMTCA : 2; + unsigned long CMTCB : 2; + unsigned long : 1; + unsigned long CMTADA : 1; + unsigned long CMTADB : 1; + unsigned long : 1; + unsigned long CPTCA : 1; + unsigned long CPTCB : 1; + unsigned long CPTPR : 1; + unsigned long CPTADA : 1; + unsigned long CPTADB : 1; + unsigned long CPTDV : 1; + unsigned long : 2; + unsigned long CP3DB : 1; + unsigned long CPBTD : 1; + unsigned long OLTTA : 2; + unsigned long OLTTB : 2; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long OLTTB : 2; + unsigned long OLTTA : 2; + unsigned long CPBTD : 1; + unsigned long CP3DB : 1; + unsigned long : 2; + unsigned long CPTDV : 1; + unsigned long CPTADB : 1; + unsigned long CPTADA : 1; + unsigned long CPTPR : 1; + unsigned long CPTCB : 1; + unsigned long CPTCA : 1; + unsigned long : 1; + unsigned long CMTADB : 1; + unsigned long CMTADA : 1; + unsigned long : 1; + unsigned long CMTCB : 2; + unsigned long CMTCA : 2; + unsigned long : 2; + unsigned long CCTDV : 1; + unsigned long CCTADB : 1; + unsigned long CCTADA : 1; + unsigned long CCTPR : 1; + unsigned long CCTCB : 1; + unsigned long CCTCA : 1; +#endif + } BIT; + } GTBER2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GTIOAB : 5; + unsigned long : 11; + unsigned long GTIOBB : 5; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long GTIOBB : 5; + unsigned long : 11; + unsigned long GTIOAB : 5; +#endif + } BIT; + } GTOLBR; + char wk2[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ICAFA : 1; + unsigned long ICAFB : 1; + unsigned long ICAFC : 1; + unsigned long ICAFD : 1; + unsigned long ICAFE : 1; + unsigned long ICAFF : 1; + unsigned long ICAFPO : 1; + unsigned long ICAFPU : 1; + unsigned long ICACLK : 1; + unsigned long : 5; + unsigned long ICAGRP : 2; + unsigned long ICBFA : 1; + unsigned long ICBFB : 1; + unsigned long ICBFC : 1; + unsigned long ICBFD : 1; + unsigned long ICBFE : 1; + unsigned long ICBFF : 1; + unsigned long ICBFPO : 1; + unsigned long ICBFPU : 1; + unsigned long ICBCLK : 1; + unsigned long : 5; + unsigned long ICBGRP : 2; +#else + unsigned long ICBGRP : 2; + unsigned long : 5; + unsigned long ICBCLK : 1; + unsigned long ICBFPU : 1; + unsigned long ICBFPO : 1; + unsigned long ICBFF : 1; + unsigned long ICBFE : 1; + unsigned long ICBFD : 1; + unsigned long ICBFC : 1; + unsigned long ICBFB : 1; + unsigned long ICBFA : 1; + unsigned long ICAGRP : 2; + unsigned long : 5; + unsigned long ICACLK : 1; + unsigned long ICAFPU : 1; + unsigned long ICAFPO : 1; + unsigned long ICAFF : 1; + unsigned long ICAFE : 1; + unsigned long ICAFD : 1; + unsigned long ICAFC : 1; + unsigned long ICAFB : 1; + unsigned long ICAFA : 1; +#endif + } BIT; + } GTICCR; +} st_gptw0_t; + +typedef struct st_hrpwm { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLLEN : 1; + unsigned short HRRST : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short HRRST : 1; + unsigned short DLLEN : 1; +#endif + } BIT; + } HROCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short HRSEL0 : 1; + unsigned short HRSEL1 : 1; + unsigned short HRSEL2 : 1; + unsigned short HRSEL3 : 1; + unsigned short : 4; + unsigned short HRDIS0 : 1; + unsigned short HRDIS1 : 1; + unsigned short HRDIS2 : 1; + unsigned short HRDIS3 : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short HRDIS3 : 1; + unsigned short HRDIS2 : 1; + unsigned short HRDIS1 : 1; + unsigned short HRDIS0 : 1; + unsigned short : 4; + unsigned short HRSEL3 : 1; + unsigned short HRSEL2 : 1; + unsigned short HRSEL1 : 1; + unsigned short HRSEL0 : 1; +#endif + } BIT; + } HROCR2; + char wk0[20]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRREAR0A; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRREAR0B; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRREAR1A; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRREAR1B; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRREAR2A; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRREAR2B; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRREAR3A; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRREAR3B; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRFEAR0A; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRFEAR0B; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRFEAR1A; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRFEAR1B; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRFEAR2A; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRFEAR2B; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRFEAR3A; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DLY : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short DLY : 5; +#endif + } BIT; + } HRFEAR3B; +} st_hrpwm_t; + +typedef struct st_icu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IR : 1; +#endif + } BIT; + } IR[256]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCE : 1; +#endif + } BIT; + } DTCER[256]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IEN0 : 1; + unsigned char IEN1 : 1; + unsigned char IEN2 : 1; + unsigned char IEN3 : 1; + unsigned char IEN4 : 1; + unsigned char IEN5 : 1; + unsigned char IEN6 : 1; + unsigned char IEN7 : 1; +#else + unsigned char IEN7 : 1; + unsigned char IEN6 : 1; + unsigned char IEN5 : 1; + unsigned char IEN4 : 1; + unsigned char IEN3 : 1; + unsigned char IEN2 : 1; + unsigned char IEN1 : 1; + unsigned char IEN0 : 1; +#endif + } BIT; + } IER[32]; + char wk0[192]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT : 1; +#endif + } BIT; + } SWINTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT2 : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT2 : 1; +#endif + } BIT; + } SWINT2R; + char wk1[14]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FVCT : 8; + unsigned short : 7; + unsigned short FIEN : 1; +#else + unsigned short FIEN : 1; + unsigned short : 7; + unsigned short FVCT : 8; +#endif + } BIT; + } FIR; + char wk2[14]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IPR : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IPR : 4; +#endif + } BIT; + } IPR[256]; + unsigned char DMRSR0; + char wk3[3]; + unsigned char DMRSR1; + char wk4[3]; + unsigned char DMRSR2; + char wk5[3]; + unsigned char DMRSR3; + char wk6[3]; + unsigned char DMRSR4; + char wk7[3]; + unsigned char DMRSR5; + char wk8[3]; + unsigned char DMRSR6; + char wk9[3]; + unsigned char DMRSR7; + char wk10[227]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRQMD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IRQMD : 2; + unsigned char : 2; +#endif + } BIT; + } IRQCR[16]; + char wk11[16]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN0 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN7 : 1; +#else + unsigned char FLTEN7 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN0 : 1; +#endif + } BIT; + } IRQFLTE0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN8 : 1; + unsigned char FLTEN9 : 1; + unsigned char FLTEN10 : 1; + unsigned char FLTEN11 : 1; + unsigned char FLTEN12 : 1; + unsigned char FLTEN13 : 1; + unsigned char FLTEN14 : 1; + unsigned char FLTEN15 : 1; +#else + unsigned char FLTEN15 : 1; + unsigned char FLTEN14 : 1; + unsigned char FLTEN13 : 1; + unsigned char FLTEN12 : 1; + unsigned char FLTEN11 : 1; + unsigned char FLTEN10 : 1; + unsigned char FLTEN9 : 1; + unsigned char FLTEN8 : 1; +#endif + } BIT; + } IRQFLTE1; + char wk12[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL0 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL7 : 2; +#else + unsigned short FCLKSEL7 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL0 : 2; +#endif + } BIT; + } IRQFLTC0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL8 : 2; + unsigned short FCLKSEL9 : 2; + unsigned short FCLKSEL10 : 2; + unsigned short FCLKSEL11 : 2; + unsigned short FCLKSEL12 : 2; + unsigned short FCLKSEL13 : 2; + unsigned short FCLKSEL14 : 2; + unsigned short FCLKSEL15 : 2; +#else + unsigned short FCLKSEL15 : 2; + unsigned short FCLKSEL14 : 2; + unsigned short FCLKSEL13 : 2; + unsigned short FCLKSEL12 : 2; + unsigned short FCLKSEL11 : 2; + unsigned short FCLKSEL10 : 2; + unsigned short FCLKSEL9 : 2; + unsigned short FCLKSEL8 : 2; +#endif + } BIT; + } IRQFLTC1; + char wk13[84]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIST : 1; + unsigned char OSTST : 1; + unsigned char WDTST : 1; + unsigned char IWDTST : 1; + unsigned char LVD1ST : 1; + unsigned char LVD2ST : 1; + unsigned char RAMST : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char RAMST : 1; + unsigned char LVD2ST : 1; + unsigned char LVD1ST : 1; + unsigned char IWDTST : 1; + unsigned char WDTST : 1; + unsigned char OSTST : 1; + unsigned char NMIST : 1; +#endif + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIEN : 1; + unsigned char OSTEN : 1; + unsigned char WDTEN : 1; + unsigned char IWDTEN : 1; + unsigned char LVD1EN : 1; + unsigned char LVD2EN : 1; + unsigned char RAMEN : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char RAMEN : 1; + unsigned char LVD2EN : 1; + unsigned char LVD1EN : 1; + unsigned char IWDTEN : 1; + unsigned char WDTEN : 1; + unsigned char OSTEN : 1; + unsigned char NMIEN : 1; +#endif + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMICLR : 1; + unsigned char OSTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char IWDTCLR : 1; + unsigned char LVD1CLR : 1; + unsigned char LVD2CLR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2CLR : 1; + unsigned char LVD1CLR : 1; + unsigned char IWDTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char OSTCLR : 1; + unsigned char NMICLR : 1; +#endif + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char NMIMD : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NMIMD : 1; + unsigned char : 3; +#endif + } BIT; + } NMICR; + char wk14[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFLTEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char NFLTEN : 1; +#endif + } BIT; + } NMIFLTE; + char wk15[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCLKSEL : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char NFCLKSEL : 2; +#endif + } BIT; + } NMIFLTC; + char wk16[155]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPBL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPBL1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPBL2; + char wk17[52]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENBL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENBL1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENBL2; + char wk18[436]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPAL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif + } BIT; + } GRPAL1; + char wk19[56]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENAL0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif + } BIT; + } GENAL1; + char wk20[136]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR4; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR5; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR6; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR7; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR8; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR9; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIARA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIARB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIARC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIARD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIARE; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIARF; + char wk21[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR12; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR13; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PIR0 : 1; + unsigned char PIR1 : 1; + unsigned char PIR2 : 1; + unsigned char PIR3 : 1; + unsigned char PIR4 : 1; + unsigned char PIR5 : 1; + unsigned char PIR6 : 1; + unsigned char PIR7 : 1; +#else + unsigned char PIR7 : 1; + unsigned char PIR6 : 1; + unsigned char PIR5 : 1; + unsigned char PIR4 : 1; + unsigned char PIR3 : 1; + unsigned char PIR2 : 1; + unsigned char PIR1 : 1; + unsigned char PIR0 : 1; +#endif + } BIT; + } PIAR14; + char wk22[187]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR208; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR209; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR210; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR211; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR212; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR213; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR214; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR215; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR216; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR217; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR218; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR219; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR220; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR221; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR222; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR223; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR224; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR225; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR226; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR227; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR228; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR229; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR230; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR231; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR232; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR233; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR234; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR235; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR236; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR237; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR238; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR239; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR240; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR241; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR242; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR243; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR244; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR245; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR246; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR247; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR248; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR249; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR250; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR251; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR252; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR253; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR254; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif + } BIT; + } SLIAR255; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WPRC : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char WPRC : 1; +#endif + } BIT; + } SLIPRCR; +} st_icu_t; + +typedef struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char SLCSTP : 1; +#else + unsigned char SLCSTP : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTCSTPR; +} st_iwdt_t; + +typedef struct st_mpc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PFSWE : 1; + unsigned char B0WI : 1; +#else + unsigned char B0WI : 1; + unsigned char PFSWE : 1; + unsigned char : 6; +#endif + } BIT; + } PWPR; + char wk0[32]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P00PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P01PFS; + char wk1[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P10PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P11PFS; + char wk2[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P24PFS; + char wk3[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P32PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P33PFS; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P36PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P37PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P47PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P52PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P53PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P55PFS; + char wk5[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P60PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P61PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P62PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P63PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P64PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } P65PFS; + char wk6[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P70PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P71PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P72PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P73PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P74PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P75PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P76PFS; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P80PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P81PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P82PFS; + char wk8[5]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P90PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P91PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P92PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P93PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } P94PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P95PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } P96PFS; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PA5PFS; + char wk10[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PB7PFS; + char wk11[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PD7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PE5PFS; + char wk12[65]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif + } BIT; + } PN7PFS; +} st_mpc_t; + +typedef struct st_mpu { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE7; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE7; + char wk0[192]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MPEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long MPEN : 1; +#endif + } BIT; + } MPEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UBAC : 3; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long UBAC : 3; + unsigned long : 1; +#endif + } BIT; + } MPBAC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long CLR : 1; +#endif + } BIT; + } MPECLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IMPER : 1; + unsigned long DMPER : 1; + unsigned long DRW : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long DRW : 1; + unsigned long DMPER : 1; + unsigned long IMPER : 1; +#endif + } BIT; + } MPESTS; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DEA : 32; +#else + unsigned long DEA : 32; +#endif + } BIT; + } MPDEA; + char wk2[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SA : 32; +#else + unsigned long SA : 32; +#endif + } BIT; + } MPSA; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short S : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short S : 1; +#endif + } BIT; + } MPOPS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short INV : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short INV : 1; +#endif + } BIT; + } MPOPI; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UHACI : 3; + unsigned long : 12; + unsigned long HITI : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long HITI : 8; + unsigned long : 12; + unsigned long UHACI : 3; + unsigned long : 1; +#endif + } BIT; + } MHITI; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UHACD : 3; + unsigned long : 12; + unsigned long HITD : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long HITD : 8; + unsigned long : 12; + unsigned long UHACD : 3; + unsigned long : 1; +#endif + } BIT; + } MHITD; +} st_mpu_t; + +typedef struct st_mtu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE3B : 1; + unsigned char OE4A : 1; + unsigned char OE4B : 1; + unsigned char OE3D : 1; + unsigned char OE4C : 1; + unsigned char OE4D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE4D : 1; + unsigned char OE4C : 1; + unsigned char OE3D : 1; + unsigned char OE4B : 1; + unsigned char OE4A : 1; + unsigned char OE3B : 1; +#endif + } BIT; + } TOERA; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UF : 1; + unsigned char VF : 1; + unsigned char WF : 1; + unsigned char FB : 1; + unsigned char P : 1; + unsigned char N : 1; + unsigned char BDC : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BDC : 1; + unsigned char N : 1; + unsigned char P : 1; + unsigned char FB : 1; + unsigned char WF : 1; + unsigned char VF : 1; + unsigned char UF : 1; +#endif + } BIT; + } TGCRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif + } BIT; + } TOCR1A; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOCR2A; + char wk1[4]; + unsigned short TCDRA; + unsigned short TDDRA; + char wk2[8]; + unsigned short TCNTSA; + unsigned short TCBRA; + char wk3[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCOR : 3; + unsigned char T4VEN : 1; + unsigned char T3ACOR : 3; + unsigned char T3AEN : 1; +#else + unsigned char T3AEN : 1; + unsigned char T3ACOR : 3; + unsigned char T4VEN : 1; + unsigned char T4VCOR : 3; +#endif + } BIT; + } TITCR1A; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCNT : 3; + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; + unsigned char T4VCNT : 3; +#endif + } BIT; + } TITCNT1A; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif + } BIT; + } TBTERA; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif + } BIT; + } TDERA; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOLBRA; + char wk6[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TITM : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TITM : 1; +#endif + } BIT; + } TITMRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG4COR : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG4COR : 3; +#endif + } BIT; + } TITCR2A; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG4CNT : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG4CNT : 3; +#endif + } BIT; + } TITCNT2A; + char wk7[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char SCC : 1; + unsigned char : 5; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 5; + unsigned char SCC : 1; + unsigned char WRE : 1; +#endif + } BIT; + } TWCRA; + char wk8[15]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DRS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DRS : 1; +#endif + } BIT; + } TMDR2A; + char wk9[15]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char : 1; + unsigned char CST9 : 1; + unsigned char : 1; + unsigned char CST3 : 1; + unsigned char CST4 : 1; +#else + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char : 1; + unsigned char CST9 : 1; + unsigned char : 1; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif + } BIT; + } TSTRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char SYNC9 : 1; + unsigned char : 2; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; +#else + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char : 2; + unsigned char SYNC9 : 1; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif + } BIT; + } TSYRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCH7 : 1; + unsigned char SCH6 : 1; + unsigned char SCH9 : 1; + unsigned char SCH4 : 1; + unsigned char SCH3 : 1; + unsigned char SCH2 : 1; + unsigned char SCH1 : 1; + unsigned char SCH0 : 1; +#else + unsigned char SCH0 : 1; + unsigned char SCH1 : 1; + unsigned char SCH2 : 1; + unsigned char SCH3 : 1; + unsigned char SCH4 : 1; + unsigned char SCH9 : 1; + unsigned char SCH6 : 1; + unsigned char SCH7 : 1; +#endif + } BIT; + } TCSYSTR; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif + } BIT; + } TRWERA; + char wk11[1925]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE6B : 1; + unsigned char OE7A : 1; + unsigned char OE7B : 1; + unsigned char OE6D : 1; + unsigned char OE7C : 1; + unsigned char OE7D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE7D : 1; + unsigned char OE7C : 1; + unsigned char OE6D : 1; + unsigned char OE7B : 1; + unsigned char OE7A : 1; + unsigned char OE6B : 1; +#endif + } BIT; + } TOERB; + char wk12[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UF : 1; + unsigned char VF : 1; + unsigned char WF : 1; + unsigned char FB : 1; + unsigned char P : 1; + unsigned char N : 1; + unsigned char BDC : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BDC : 1; + unsigned char N : 1; + unsigned char P : 1; + unsigned char FB : 1; + unsigned char WF : 1; + unsigned char VF : 1; + unsigned char UF : 1; +#endif + } BIT; + } TGCRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif + } BIT; + } TOCR1B; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOCR2B; + char wk13[4]; + unsigned short TCDRB; + unsigned short TDDRB; + char wk14[8]; + unsigned short TCNTSB; + unsigned short TCBRB; + char wk15[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T7VCOR : 3; + unsigned char T7VEN : 1; + unsigned char T6ACOR : 3; + unsigned char T6AEN : 1; +#else + unsigned char T6AEN : 1; + unsigned char T6ACOR : 3; + unsigned char T7VEN : 1; + unsigned char T7VCOR : 3; +#endif + } BIT; + } TITCR1B; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T7VCNT : 3; + unsigned char : 1; + unsigned char T6ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T6ACNT : 3; + unsigned char : 1; + unsigned char T7VCNT : 3; +#endif + } BIT; + } TITCNT1B; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif + } BIT; + } TBTERB; + char wk16[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif + } BIT; + } TDERB; + char wk17[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOLBRB; + char wk18[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TITM : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TITM : 1; +#endif + } BIT; + } TITMRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG7COR : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG7COR : 3; +#endif + } BIT; + } TITCR2B; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG7CNT : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG7CNT : 3; +#endif + } BIT; + } TITCNT2B; + char wk19[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char SCC : 1; + unsigned char : 5; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 5; + unsigned char SCC : 1; + unsigned char WRE : 1; +#endif + } BIT; + } TWCRB; + char wk20[15]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DRS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DRS : 1; +#endif + } BIT; + } TMDR2B; + char wk21[15]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char CST6 : 1; + unsigned char CST7 : 1; +#else + unsigned char CST7 : 1; + unsigned char CST6 : 1; + unsigned char : 6; +#endif + } BIT; + } TSTRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char SYNC6 : 1; + unsigned char SYNC7 : 1; +#else + unsigned char SYNC7 : 1; + unsigned char SYNC6 : 1; + unsigned char : 6; +#endif + } BIT; + } TSYRB; + char wk22[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif + } BIT; + } TRWERB; + char wk23[683]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TADSTRS0 : 5; + unsigned char : 2; + unsigned char TADSMEN0 : 1; +#else + unsigned char TADSMEN0 : 1; + unsigned char : 2; + unsigned char TADSTRS0 : 5; +#endif + } BIT; + } TADSTRGR0; + char wk24[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TADSTRS1 : 5; + unsigned char : 2; + unsigned char TADSMEN1 : 1; +#else + unsigned char TADSMEN1 : 1; + unsigned char : 2; + unsigned char TADSTRS1 : 5; +#endif + } BIT; + } TADSTRGR1; +} st_mtu_t; + +typedef struct st_mtu0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR0; + char wk0[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCRC; + char wk1[102]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk2[1]; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk3[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEE : 1; + unsigned char TGIEF : 1; + unsigned char : 5; + unsigned char TTGE2 : 1; +#else + unsigned char TTGE2 : 1; + unsigned char : 5; + unsigned char TGIEF : 1; + unsigned char TGIEE : 1; +#endif + } BIT; + } TIER2; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; +} st_mtu0_t; + +typedef struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR1; + char wk1[238]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char I1AE : 1; + unsigned char I1BE : 1; + unsigned char I2AE : 1; + unsigned char I2BE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char I2BE : 1; + unsigned char I2AE : 1; + unsigned char I1BE : 1; + unsigned char I1AE : 1; +#endif + } BIT; + } TICCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LWA : 1; + unsigned char PHCKSEL : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char PHCKSEL : 1; + unsigned char LWA : 1; +#endif + } BIT; + } TMDR3; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char PCB : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PCB : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk5[11]; + unsigned long TCNTLW; + unsigned long TGRALW; + unsigned long TGRBLW; +} st_mtu1_t; + +typedef struct st_mtu2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR2; + char wk0[365]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char PCB : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PCB : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; +} st_mtu2_t; + +typedef struct st_mtu3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk8[19]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk9[37]; + unsigned short TGRE; + char wk10[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR3; +} st_mtu3_t; + +typedef struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITA3AE : 1; + unsigned short DT4BE : 1; + unsigned short UT4BE : 1; + unsigned short DT4AE : 1; + unsigned short UT4AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT4AE : 1; + unsigned short DT4AE : 1; + unsigned short UT4BE : 1; + unsigned short DT4BE : 1; + unsigned short ITA3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITB4VE : 1; +#endif + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR4; +} st_mtu4_t; + +typedef struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFUEN : 1; + unsigned char NFVEN : 1; + unsigned char NFWEN : 1; + unsigned char : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 1; + unsigned char NFWEN : 1; + unsigned char NFVEN : 1; + unsigned char NFUEN : 1; +#endif + } BIT; + } NFCR5; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRU; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char CKEG : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CKEG : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2U; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORU; + char wk2[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRV; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char CKEG : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CKEG : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2V; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORV; + char wk3[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRW; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char CKEG : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CKEG : 2; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2W; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORW; + char wk4[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIE5W : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TGIE5U : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5W : 1; +#endif + } BIT; + } TIER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CSTW5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTU5 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CSTU5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTW5 : 1; +#endif + } BIT; + } TSTR; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCLR5W : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CMPCLR5U : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5W : 1; +#endif + } BIT; + } TCNTCMPCLR; +} st_mtu5_t; + +typedef struct st_mtu6 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk8[19]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk9[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CE2B : 1; + unsigned char CE2A : 1; + unsigned char CE1B : 1; + unsigned char CE1A : 1; + unsigned char CE0D : 1; + unsigned char CE0C : 1; + unsigned char CE0B : 1; + unsigned char CE0A : 1; +#else + unsigned char CE0A : 1; + unsigned char CE0B : 1; + unsigned char CE0C : 1; + unsigned char CE0D : 1; + unsigned char CE1A : 1; + unsigned char CE1B : 1; + unsigned char CE2A : 1; + unsigned char CE2B : 1; +#endif + } BIT; + } TSYCR; + char wk10[33]; + unsigned short TGRE; + char wk11[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR6; +} st_mtu6_t; + +typedef struct st_mtu7 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB7VE : 1; + unsigned short ITB6AE : 1; + unsigned short ITA7VE : 1; + unsigned short ITA6AE : 1; + unsigned short DT7BE : 1; + unsigned short UT7BE : 1; + unsigned short DT7AE : 1; + unsigned short UT7AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT7AE : 1; + unsigned short DT7AE : 1; + unsigned short UT7BE : 1; + unsigned short DT7BE : 1; + unsigned short ITA6AE : 1; + unsigned short ITA7VE : 1; + unsigned short ITB6AE : 1; + unsigned short ITB7VE : 1; +#endif + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR7; +} st_mtu7_t; + +typedef struct st_mtu9 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR9; + char wk0[745]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk1[1]; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk2[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEE : 1; + unsigned char TGIEF : 1; + unsigned char : 5; + unsigned char TTGE2 : 1; +#else + unsigned char TTGE2 : 1; + unsigned char : 5; + unsigned char TGIEF : 1; + unsigned char TGIEE : 1; +#endif + } BIT; + } TIER2; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif + } BIT; + } TCR2; +} st_mtu9_t; + +typedef struct st_ofsm { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 17; + unsigned long OCDE : 1; + unsigned long : 6; + unsigned long IDE : 1; + unsigned long : 2; + unsigned long SPE : 1; + unsigned long : 1; + unsigned long SEPR : 1; + unsigned long WRPR : 1; + unsigned long RDPR : 1; +#else + unsigned long RDPR : 1; + unsigned long WRPR : 1; + unsigned long SEPR : 1; + unsigned long : 1; + unsigned long SPE : 1; + unsigned long : 2; + unsigned long IDE : 1; + unsigned long : 6; + unsigned long OCDE : 1; + unsigned long : 17; +#endif + } BIT; + } SPCC; + char wk0[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 24; + unsigned long TMEF : 3; + unsigned long : 1; + unsigned long TMEFDB : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long TMEFDB : 3; + unsigned long : 1; + unsigned long TMEF : 3; + unsigned long : 24; +#endif + } BIT; + } TMEF; + char wk1[4]; + union { + struct { + unsigned long ID4:8; + unsigned long ID3:8; + unsigned long ID2:8; + unsigned long ID1:8; + unsigned long ID8:8; + unsigned long ID7:8; + unsigned long ID6:8; + unsigned long ID5:8; + unsigned long ID12:8; + unsigned long ID11:8; + unsigned long ID10:8; + unsigned long ID9:8; + unsigned long ID16:8; + unsigned long ID15:8; + unsigned long ID14:8; + unsigned long ID13:8; + } BIT; + } OSIS; + unsigned long TMINF; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MDE : 3; + unsigned long : 1; + unsigned long BANKMD : 3; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long BANKMD : 3; + unsigned long : 1; + unsigned long MDE : 3; +#endif + } BIT; + } MDE; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long IWDTSTRT : 1; + unsigned long IWDTTOPS : 2; + unsigned long IWDTCKS : 4; + unsigned long IWDTRPES : 2; + unsigned long IWDTRPSS : 2; + unsigned long IWDTRSTIRQS : 1; + unsigned long : 1; + unsigned long IWDTSLCSTP : 1; + unsigned long : 2; + unsigned long WDTSTRT : 1; + unsigned long WDTTOPS : 2; + unsigned long WDTCKS : 4; + unsigned long WDTRPES : 2; + unsigned long WDTRPSS : 2; + unsigned long WDTRSTIRQS : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long WDTRSTIRQS : 1; + unsigned long WDTRPSS : 2; + unsigned long WDTRPES : 2; + unsigned long WDTCKS : 4; + unsigned long WDTTOPS : 2; + unsigned long WDTSTRT : 1; + unsigned long : 2; + unsigned long IWDTSLCSTP : 1; + unsigned long : 1; + unsigned long IWDTRSTIRQS : 1; + unsigned long IWDTRPSS : 2; + unsigned long IWDTRPES : 2; + unsigned long IWDTCKS : 4; + unsigned long IWDTTOPS : 2; + unsigned long IWDTSTRT : 1; + unsigned long : 1; +#endif + } BIT; + } OFS0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VDSEL : 2; + unsigned long LVDAS : 1; + unsigned long : 5; + unsigned long HOCOEN : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long HOCOEN : 1; + unsigned long : 5; + unsigned long LVDAS : 1; + unsigned long VDSEL : 2; +#endif + } BIT; + } OFS1; + char wk2[32]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BANKSWP : 3; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long BANKSWP : 3; +#endif + } BIT; + } BANKSEL; + char wk3[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FAWS : 13; + unsigned long : 2; + unsigned long FSPR : 1; + unsigned long FAWE : 13; + unsigned long : 2; + unsigned long BTFLG : 1; +#else + unsigned long BTFLG : 1; + unsigned long : 2; + unsigned long FAWE : 13; + unsigned long FSPR : 1; + unsigned long : 2; + unsigned long FAWS : 13; +#endif + } BIT; + } FAW; +} st_ofsm_t; + +typedef struct st_poe { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE0M : 4; + unsigned short POE0M2 : 4; + unsigned short PIE1 : 1; + unsigned short : 3; + unsigned short POE0F : 1; + unsigned short : 2; + unsigned short INV : 1; +#else + unsigned short INV : 1; + unsigned short : 2; + unsigned short POE0F : 1; + unsigned short : 3; + unsigned short PIE1 : 1; + unsigned short POE0M2 : 4; + unsigned short POE0M : 4; +#endif + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE1 : 1; + unsigned short OCE1 : 1; + unsigned short : 5; + unsigned short OSF1 : 1; +#else + unsigned short OSF1 : 1; + unsigned short : 5; + unsigned short OCE1 : 1; + unsigned short OIE1 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE4M : 4; + unsigned short POE4M2 : 4; + unsigned short PIE2 : 1; + unsigned short : 3; + unsigned short POE4F : 1; + unsigned short : 2; + unsigned short INV : 1; +#else + unsigned short INV : 1; + unsigned short : 2; + unsigned short POE4F : 1; + unsigned short : 3; + unsigned short PIE2 : 1; + unsigned short POE4M2 : 4; + unsigned short POE4M : 4; +#endif + } BIT; + } ICSR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE2 : 1; + unsigned short OCE2 : 1; + unsigned short : 5; + unsigned short OSF2 : 1; +#else + unsigned short OSF2 : 1; + unsigned short : 5; + unsigned short OCE2 : 1; + unsigned short OIE2 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE8M : 4; + unsigned short POE8M2 : 4; + unsigned short PIE3 : 1; + unsigned short POE8E : 1; + unsigned short : 2; + unsigned short POE8F : 1; + unsigned short : 2; + unsigned short INV : 1; +#else + unsigned short INV : 1; + unsigned short : 2; + unsigned short POE8F : 1; + unsigned short : 2; + unsigned short POE8E : 1; + unsigned short PIE3 : 1; + unsigned short POE8M2 : 4; + unsigned short POE8M : 4; +#endif + } BIT; + } ICSR3; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU0AZE : 1; + unsigned char MTU0BZE : 1; + unsigned char MTU0CZE : 1; + unsigned char MTU0DZE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MTU0DZE : 1; + unsigned char MTU0CZE : 1; + unsigned char MTU0BZE : 1; + unsigned char MTU0AZE : 1; +#endif + } BIT; + } POECR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MTU7BDZE : 1; + unsigned short MTU7ACZE : 1; + unsigned short MTU6BDZE : 1; + unsigned short : 5; + unsigned short MTU4BDZE : 1; + unsigned short MTU4ACZE : 1; + unsigned short MTU3BDZE : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short MTU3BDZE : 1; + unsigned short MTU4ACZE : 1; + unsigned short MTU4BDZE : 1; + unsigned short : 5; + unsigned short MTU6BDZE : 1; + unsigned short MTU7ACZE : 1; + unsigned short MTU7BDZE : 1; +#endif + } BIT; + } POECR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GPT0ABZE : 1; + unsigned short GPT1ABZE : 1; + unsigned short GPT2ABZE : 1; + unsigned short GPT3ABZE : 1; + unsigned short GPT4ABZE : 1; + unsigned short GPT5ABZE : 1; + unsigned short GPT6ABZE : 1; + unsigned short GPT7ABZE : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short GPT7ABZE : 1; + unsigned short GPT6ABZE : 1; + unsigned short GPT5ABZE : 1; + unsigned short GPT4ABZE : 1; + unsigned short GPT3ABZE : 1; + unsigned short GPT2ABZE : 1; + unsigned short GPT1ABZE : 1; + unsigned short GPT0ABZE : 1; +#endif + } BIT; + } POECR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMADDMT34ZE : 1; + unsigned short IC1ADDMT34ZE : 1; + unsigned short IC2ADDMT34ZE : 1; + unsigned short IC3ADDMT34ZE : 1; + unsigned short IC4ADDMT34ZE : 1; + unsigned short IC5ADDMT34ZE : 1; + unsigned short IC6ADDMT34ZE : 1; + unsigned short : 1; + unsigned short IC8ADDMT34ZE : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short IC8ADDMT34ZE : 1; + unsigned short : 1; + unsigned short IC6ADDMT34ZE : 1; + unsigned short IC5ADDMT34ZE : 1; + unsigned short IC4ADDMT34ZE : 1; + unsigned short IC3ADDMT34ZE : 1; + unsigned short IC2ADDMT34ZE : 1; + unsigned short IC1ADDMT34ZE : 1; + unsigned short CMADDMT34ZE : 1; +#endif + } BIT; + } POECR4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMADDMT0ZE : 1; + unsigned short IC1ADDMT0ZE : 1; + unsigned short IC2ADDMT0ZE : 1; + unsigned short IC3ADDMT0ZE : 1; + unsigned short IC4ADDMT0ZE : 1; + unsigned short IC5ADDMT0ZE : 1; + unsigned short IC6ADDMT0ZE : 1; + unsigned short : 1; + unsigned short IC8ADDMT0ZE : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short IC8ADDMT0ZE : 1; + unsigned short : 1; + unsigned short IC6ADDMT0ZE : 1; + unsigned short IC5ADDMT0ZE : 1; + unsigned short IC4ADDMT0ZE : 1; + unsigned short IC3ADDMT0ZE : 1; + unsigned short IC2ADDMT0ZE : 1; + unsigned short IC1ADDMT0ZE : 1; + unsigned short CMADDMT0ZE : 1; +#endif + } BIT; + } POECR5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMADDGPT01ZE : 1; + unsigned short IC1ADDGPT01ZE : 1; + unsigned short IC2ADDGPT01ZE : 1; + unsigned short IC3ADDGPT01ZE : 1; + unsigned short IC4ADDGPT01ZE : 1; + unsigned short IC5ADDGPT01ZE : 1; + unsigned short IC6ADDGPT01ZE : 1; + unsigned short : 1; + unsigned short IC8ADDGPT01ZE : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short IC8ADDGPT01ZE : 1; + unsigned short : 1; + unsigned short IC6ADDGPT01ZE : 1; + unsigned short IC5ADDGPT01ZE : 1; + unsigned short IC4ADDGPT01ZE : 1; + unsigned short IC3ADDGPT01ZE : 1; + unsigned short IC2ADDGPT01ZE : 1; + unsigned short IC1ADDGPT01ZE : 1; + unsigned short CMADDGPT01ZE : 1; +#endif + } BIT; + } POECR6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE10M : 4; + unsigned short POE10M2 : 4; + unsigned short PIE4 : 1; + unsigned short POE10E : 1; + unsigned short : 2; + unsigned short POE10F : 1; + unsigned short : 2; + unsigned short INV : 1; +#else + unsigned short INV : 1; + unsigned short : 2; + unsigned short POE10F : 1; + unsigned short : 2; + unsigned short POE10E : 1; + unsigned short PIE4 : 1; + unsigned short POE10M2 : 4; + unsigned short POE10M : 4; +#endif + } BIT; + } ICSR4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE11M : 4; + unsigned short POE11M2 : 4; + unsigned short PIE5 : 1; + unsigned short POE11E : 1; + unsigned short : 2; + unsigned short POE11F : 1; + unsigned short : 2; + unsigned short INV : 1; +#else + unsigned short INV : 1; + unsigned short : 2; + unsigned short POE11F : 1; + unsigned short : 2; + unsigned short POE11E : 1; + unsigned short PIE5 : 1; + unsigned short POE11M2 : 4; + unsigned short POE11M : 4; +#endif + } BIT; + } ICSR5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short OLSG0A : 1; + unsigned short OLSG0B : 1; + unsigned short OLSG1A : 1; + unsigned short OLSG1B : 1; + unsigned short OLSG2A : 1; + unsigned short OLSG2B : 1; + unsigned short : 1; + unsigned short OLSEN : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short OLSEN : 1; + unsigned short : 1; + unsigned short OLSG2B : 1; + unsigned short OLSG2A : 1; + unsigned short OLSG1B : 1; + unsigned short OLSG1A : 1; + unsigned short OLSG0B : 1; + unsigned short OLSG0A : 1; +#endif + } BIT; + } ALR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 9; + unsigned short OSTSTE : 1; + unsigned short : 2; + unsigned short OSTSTF : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short OSTSTF : 1; + unsigned short : 2; + unsigned short OSTSTE : 1; + unsigned short : 9; +#endif + } BIT; + } ICSR6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short OLSG4A : 1; + unsigned short OLSG4B : 1; + unsigned short OLSG5A : 1; + unsigned short OLSG5B : 1; + unsigned short OLSG6A : 1; + unsigned short OLSG6B : 1; + unsigned short : 1; + unsigned short OLSEN : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short OLSEN : 1; + unsigned short : 1; + unsigned short OLSG6B : 1; + unsigned short OLSG6A : 1; + unsigned short OLSG5B : 1; + unsigned short OLSG5A : 1; + unsigned short OLSG4B : 1; + unsigned short OLSG4A : 1; +#endif + } BIT; + } ALR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE12M : 4; + unsigned short POE12M2 : 4; + unsigned short PIE7 : 1; + unsigned short POE12E : 1; + unsigned short : 2; + unsigned short POE12F : 1; + unsigned short : 2; + unsigned short INV : 1; +#else + unsigned short INV : 1; + unsigned short : 2; + unsigned short POE12F : 1; + unsigned short : 2; + unsigned short POE12E : 1; + unsigned short PIE7 : 1; + unsigned short POE12M2 : 4; + unsigned short POE12M : 4; +#endif + } BIT; + } ICSR7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MTU9AZE : 1; + unsigned short MTU9BZE : 1; + unsigned short MTU9CZE : 1; + unsigned short MTU9DZE : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short MTU9DZE : 1; + unsigned short MTU9CZE : 1; + unsigned short MTU9BZE : 1; + unsigned short MTU9AZE : 1; +#endif + } BIT; + } POECR7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMADDMT9ZE : 1; + unsigned short IC1ADDMT9ZE : 1; + unsigned short IC2ADDMT9ZE : 1; + unsigned short IC3ADDMT9ZE : 1; + unsigned short IC4ADDMT9ZE : 1; + unsigned short IC5ADDMT9ZE : 1; + unsigned short IC6ADDMT9ZE : 1; + unsigned short : 1; + unsigned short IC8ADDMT9ZE : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short IC8ADDMT9ZE : 1; + unsigned short : 1; + unsigned short IC6ADDMT9ZE : 1; + unsigned short IC5ADDMT9ZE : 1; + unsigned short IC4ADDMT9ZE : 1; + unsigned short IC3ADDMT9ZE : 1; + unsigned short IC2ADDMT9ZE : 1; + unsigned short IC1ADDMT9ZE : 1; + unsigned short CMADDMT9ZE : 1; +#endif + } BIT; + } POECR8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short C0FLAG : 1; + unsigned short C1FLAG : 1; + unsigned short C2FLAG : 1; + unsigned short C3FLAG : 1; + unsigned short C4FLAG : 1; + unsigned short C5FLAG : 1; + unsigned short : 10; +#else + unsigned short : 10; + unsigned short C5FLAG : 1; + unsigned short C4FLAG : 1; + unsigned short C3FLAG : 1; + unsigned short C2FLAG : 1; + unsigned short C1FLAG : 1; + unsigned short C0FLAG : 1; +#endif + } BIT; + } POECMPFR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POEREQ0 : 1; + unsigned short POEREQ1 : 1; + unsigned short POEREQ2 : 1; + unsigned short POEREQ3 : 1; + unsigned short POEREQ4 : 1; + unsigned short POEREQ5 : 1; + unsigned short : 10; +#else + unsigned short : 10; + unsigned short POEREQ5 : 1; + unsigned short POEREQ4 : 1; + unsigned short POEREQ3 : 1; + unsigned short POEREQ2 : 1; + unsigned short POEREQ1 : 1; + unsigned short POEREQ0 : 1; +#endif + } BIT; + } POECMPSEL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE3 : 1; + unsigned short OCE3 : 1; + unsigned short : 5; + unsigned short OSF3 : 1; +#else + unsigned short OSF3 : 1; + unsigned short : 5; + unsigned short OCE3 : 1; + unsigned short OIE3 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short OLSG0A : 1; + unsigned short OLSG0B : 1; + unsigned short OLSG1A : 1; + unsigned short OLSG1B : 1; + unsigned short OLSG2A : 1; + unsigned short OLSG2B : 1; + unsigned short : 1; + unsigned short OLSEN : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short OLSEN : 1; + unsigned short : 1; + unsigned short OLSG2B : 1; + unsigned short OLSG2A : 1; + unsigned short OLSG1B : 1; + unsigned short OLSG1A : 1; + unsigned short OLSG0B : 1; + unsigned short OLSG0A : 1; +#endif + } BIT; + } ALR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MTUCH34HIZ : 1; + unsigned short MTUCH67HIZ : 1; + unsigned short MTUCH0HIZ : 1; + unsigned short GPT01HIZ : 1; + unsigned short GPT23HIZ : 1; + unsigned short : 1; + unsigned short MTUCH9HIZ : 1; + unsigned short : 1; + unsigned short GPT02HIZ : 1; + unsigned short GPT46HIZ : 1; + unsigned short GPT79HIZ : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short GPT79HIZ : 1; + unsigned short GPT46HIZ : 1; + unsigned short GPT02HIZ : 1; + unsigned short : 1; + unsigned short MTUCH9HIZ : 1; + unsigned short : 1; + unsigned short GPT23HIZ : 1; + unsigned short GPT01HIZ : 1; + unsigned short MTUCH0HIZ : 1; + unsigned short MTUCH67HIZ : 1; + unsigned short MTUCH34HIZ : 1; +#endif + } BIT; + } SPOER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MTU0AME : 1; + unsigned short MTU0BME : 1; + unsigned short MTU0CME : 1; + unsigned short MTU0DME : 1; + unsigned short : 4; + unsigned short MTU9AME : 1; + unsigned short MTU9BME : 1; + unsigned short MTU9CME : 1; + unsigned short MTU9DME : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short MTU9DME : 1; + unsigned short MTU9CME : 1; + unsigned short MTU9BME : 1; + unsigned short MTU9AME : 1; + unsigned short : 4; + unsigned short MTU0DME : 1; + unsigned short MTU0CME : 1; + unsigned short MTU0BME : 1; + unsigned short MTU0AME : 1; +#endif + } BIT; + } PMMCR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MTU7BME : 1; + unsigned short MTU7AME : 1; + unsigned short MTU6BME : 1; + unsigned short MTU7DME : 1; + unsigned short MTU7CME : 1; + unsigned short MTU6DME : 1; + unsigned short : 2; + unsigned short MTU4BME : 1; + unsigned short MTU4AME : 1; + unsigned short MTU3BME : 1; + unsigned short MTU4DME : 1; + unsigned short MTU4CME : 1; + unsigned short MTU3DME : 1; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short MTU3DME : 1; + unsigned short MTU4CME : 1; + unsigned short MTU4DME : 1; + unsigned short MTU3BME : 1; + unsigned short MTU4AME : 1; + unsigned short MTU4BME : 1; + unsigned short : 2; + unsigned short MTU6DME : 1; + unsigned short MTU7CME : 1; + unsigned short MTU7DME : 1; + unsigned short MTU6BME : 1; + unsigned short MTU7AME : 1; + unsigned short MTU7BME : 1; +#endif + } BIT; + } PMMCR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GPT0AME : 1; + unsigned short GPT0BME : 1; + unsigned short GPT1AME : 1; + unsigned short GPT1BME : 1; + unsigned short GPT2AME : 1; + unsigned short GPT2BME : 1; + unsigned short GPT3AME : 1; + unsigned short GPT3BME : 1; + unsigned short GPT4AME : 1; + unsigned short GPT4BME : 1; + unsigned short GPT5AME : 1; + unsigned short GPT5BME : 1; + unsigned short GPT6AME : 1; + unsigned short GPT6BME : 1; + unsigned short GPT7AME : 1; + unsigned short GPT7BME : 1; +#else + unsigned short GPT7BME : 1; + unsigned short GPT7AME : 1; + unsigned short GPT6BME : 1; + unsigned short GPT6AME : 1; + unsigned short GPT5BME : 1; + unsigned short GPT5AME : 1; + unsigned short GPT4BME : 1; + unsigned short GPT4AME : 1; + unsigned short GPT3BME : 1; + unsigned short GPT3AME : 1; + unsigned short GPT2BME : 1; + unsigned short GPT2AME : 1; + unsigned short GPT1BME : 1; + unsigned short GPT1AME : 1; + unsigned short GPT0BME : 1; + unsigned short GPT0AME : 1; +#endif + } BIT; + } PMMCR2; + char wk1[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POEREQ0 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POEREQ5 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ0 : 1; +#endif + } BIT; + } POECMPEX0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POEREQ0 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POEREQ5 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ0 : 1; +#endif + } BIT; + } POECMPEX1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POEREQ0 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POEREQ5 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ0 : 1; +#endif + } BIT; + } POECMPEX2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POEREQ0 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POEREQ5 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ0 : 1; +#endif + } BIT; + } POECMPEX3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POEREQ0 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POEREQ5 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ0 : 1; +#endif + } BIT; + } POECMPEX4; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POEREQ0 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POEREQ5 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ0 : 1; +#endif + } BIT; + } POECMPEX5; + char wk2[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE9M : 4; + unsigned short POE9M2 : 4; + unsigned short PIE8 : 1; + unsigned short POE9E : 1; + unsigned short : 2; + unsigned short POE9F : 1; + unsigned short : 2; + unsigned short INV : 1; +#else + unsigned short INV : 1; + unsigned short : 2; + unsigned short POE9F : 1; + unsigned short : 2; + unsigned short POE9E : 1; + unsigned short PIE8 : 1; + unsigned short POE9M2 : 4; + unsigned short POE9M : 4; +#endif + } BIT; + } ICSR8; + char wk3[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE4 : 1; + unsigned short OCE4 : 1; + unsigned short : 5; + unsigned short OSF4 : 1; +#else + unsigned short OSF4 : 1; + unsigned short : 5; + unsigned short OCE4 : 1; + unsigned short OIE4 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE5 : 1; + unsigned short OCE5 : 1; + unsigned short : 5; + unsigned short OSF5 : 1; +#else + unsigned short OSF5 : 1; + unsigned short : 5; + unsigned short OCE5 : 1; + unsigned short OIE5 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short OLSG0A : 1; + unsigned short OLSG0B : 1; + unsigned short OLSG1A : 1; + unsigned short OLSG1B : 1; + unsigned short OLSG2A : 1; + unsigned short OLSG2B : 1; + unsigned short : 1; + unsigned short OLSEN : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short OLSEN : 1; + unsigned short : 1; + unsigned short OLSG2B : 1; + unsigned short OLSG2A : 1; + unsigned short OLSG1B : 1; + unsigned short OLSG1A : 1; + unsigned short OLSG0B : 1; + unsigned short OLSG0A : 1; +#endif + } BIT; + } ALR4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short OLSG0A : 1; + unsigned short OLSG0B : 1; + unsigned short : 5; + unsigned short OLSEN : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short OLSEN : 1; + unsigned short : 5; + unsigned short OLSG0B : 1; + unsigned short OLSG0A : 1; +#endif + } BIT; + } ALR5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMADDMT67ZE : 1; + unsigned short IC1ADDMT67ZE : 1; + unsigned short IC2ADDMT67ZE : 1; + unsigned short IC3ADDMT67ZE : 1; + unsigned short IC4ADDMT67ZE : 1; + unsigned short IC5ADDMT67ZE : 1; + unsigned short IC6ADDMT67ZE : 1; + unsigned short : 1; + unsigned short IC8ADDMT67ZE : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short IC8ADDMT67ZE : 1; + unsigned short : 1; + unsigned short IC6ADDMT67ZE : 1; + unsigned short IC5ADDMT67ZE : 1; + unsigned short IC4ADDMT67ZE : 1; + unsigned short IC3ADDMT67ZE : 1; + unsigned short IC2ADDMT67ZE : 1; + unsigned short IC1ADDMT67ZE : 1; + unsigned short CMADDMT67ZE : 1; +#endif + } BIT; + } POECR4B; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMADDGPT23ZE : 1; + unsigned short IC1ADDGPT23ZE : 1; + unsigned short IC2ADDGPT23ZE : 1; + unsigned short IC3ADDGPT23ZE : 1; + unsigned short IC4ADDGPT23ZE : 1; + unsigned short IC5ADDGPT23ZE : 1; + unsigned short IC6ADDGPT23ZE : 1; + unsigned short : 1; + unsigned short IC8ADDGPT23ZE : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short IC8ADDGPT23ZE : 1; + unsigned short : 1; + unsigned short IC6ADDGPT23ZE : 1; + unsigned short IC5ADDGPT23ZE : 1; + unsigned short IC4ADDGPT23ZE : 1; + unsigned short IC3ADDGPT23ZE : 1; + unsigned short IC2ADDGPT23ZE : 1; + unsigned short IC1ADDGPT23ZE : 1; + unsigned short CMADDGPT23ZE : 1; +#endif + } BIT; + } POECR6B; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMADDGPT02ZE : 1; + unsigned short IC1ADDGPT02ZE : 1; + unsigned short IC2ADDGPT02ZE : 1; + unsigned short IC3ADDGPT02ZE : 1; + unsigned short IC4ADDGPT02ZE : 1; + unsigned short IC5ADDGPT02ZE : 1; + unsigned short IC6ADDGPT02ZE : 1; + unsigned short : 1; + unsigned short IC8ADDGPT02ZE : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short IC8ADDGPT02ZE : 1; + unsigned short : 1; + unsigned short IC6ADDGPT02ZE : 1; + unsigned short IC5ADDGPT02ZE : 1; + unsigned short IC4ADDGPT02ZE : 1; + unsigned short IC3ADDGPT02ZE : 1; + unsigned short IC2ADDGPT02ZE : 1; + unsigned short IC1ADDGPT02ZE : 1; + unsigned short CMADDGPT02ZE : 1; +#endif + } BIT; + } POECR9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMADDGPT46ZE : 1; + unsigned short IC1ADDGPT46ZE : 1; + unsigned short IC2ADDGPT46ZE : 1; + unsigned short IC3ADDGPT46ZE : 1; + unsigned short IC4ADDGPT46ZE : 1; + unsigned short IC5ADDGPT46ZE : 1; + unsigned short IC6ADDGPT46ZE : 1; + unsigned short : 1; + unsigned short IC8ADDGPT46ZE : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short IC8ADDGPT46ZE : 1; + unsigned short : 1; + unsigned short IC6ADDGPT46ZE : 1; + unsigned short IC5ADDGPT46ZE : 1; + unsigned short IC4ADDGPT46ZE : 1; + unsigned short IC3ADDGPT46ZE : 1; + unsigned short IC2ADDGPT46ZE : 1; + unsigned short IC1ADDGPT46ZE : 1; + unsigned short CMADDGPT46ZE : 1; +#endif + } BIT; + } POECR10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMADDGPT79ZE : 1; + unsigned short IC1ADDGPT79ZE : 1; + unsigned short IC2ADDGPT79ZE : 1; + unsigned short IC3ADDGPT79ZE : 1; + unsigned short IC4ADDGPT79ZE : 1; + unsigned short IC5ADDGPT79ZE : 1; + unsigned short IC6ADDGPT79ZE : 1; + unsigned short : 1; + unsigned short IC8ADDGPT79ZE : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short IC8ADDGPT79ZE : 1; + unsigned short : 1; + unsigned short IC6ADDGPT79ZE : 1; + unsigned short IC5ADDGPT79ZE : 1; + unsigned short IC4ADDGPT79ZE : 1; + unsigned short IC3ADDGPT79ZE : 1; + unsigned short IC2ADDGPT79ZE : 1; + unsigned short IC1ADDGPT79ZE : 1; + unsigned short CMADDGPT79ZE : 1; +#endif + } BIT; + } POECR11; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POEREQ0 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POEREQ5 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ0 : 1; +#endif + } BIT; + } POECMPEX6; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POEREQ0 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POEREQ5 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ0 : 1; +#endif + } BIT; + } POECMPEX7; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POEREQ0 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POEREQ5 : 1; + unsigned char POEREQ4 : 1; + unsigned char POEREQ3 : 1; + unsigned char POEREQ2 : 1; + unsigned char POEREQ1 : 1; + unsigned char POEREQ0 : 1; +#endif + } BIT; + } POECMPEX8; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POE0MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POE0MS : 6; +#endif + } BIT; + } IMCR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POE4MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POE4MS : 6; +#endif + } BIT; + } IMCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POE8MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POE8MS : 6; +#endif + } BIT; + } IMCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POE10MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POE10MS : 6; +#endif + } BIT; + } IMCR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M0ASEL : 4; + unsigned char M0BSEL : 4; +#else + unsigned char M0BSEL : 4; + unsigned char M0ASEL : 4; +#endif + } BIT; + } M0SELR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M0CSEL : 4; + unsigned char M0DSEL : 4; +#else + unsigned char M0DSEL : 4; + unsigned char M0CSEL : 4; +#endif + } BIT; + } M0SELR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M3BSEL : 4; + unsigned char M3DSEL : 4; +#else + unsigned char M3DSEL : 4; + unsigned char M3BSEL : 4; +#endif + } BIT; + } M3SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M4ASEL : 4; + unsigned char M4CSEL : 4; +#else + unsigned char M4CSEL : 4; + unsigned char M4ASEL : 4; +#endif + } BIT; + } M4SELR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M4BSEL : 4; + unsigned char M4DSEL : 4; +#else + unsigned char M4DSEL : 4; + unsigned char M4BSEL : 4; +#endif + } BIT; + } M4SELR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M6BSEL : 4; + unsigned char M6DSEL : 4; +#else + unsigned char M6DSEL : 4; + unsigned char M6BSEL : 4; +#endif + } BIT; + } M6SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M7ASEL : 4; + unsigned char M7CSEL : 4; +#else + unsigned char M7CSEL : 4; + unsigned char M7ASEL : 4; +#endif + } BIT; + } M7SELR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M7BSEL : 4; + unsigned char M7DSEL : 4; +#else + unsigned char M7DSEL : 4; + unsigned char M7BSEL : 4; +#endif + } BIT; + } M7SELR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M9ASEL : 4; + unsigned char M9BSEL : 4; +#else + unsigned char M9BSEL : 4; + unsigned char M9ASEL : 4; +#endif + } BIT; + } M9SELR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M9CSEL : 4; + unsigned char M9DSEL : 4; +#else + unsigned char M9DSEL : 4; + unsigned char M9CSEL : 4; +#endif + } BIT; + } M9SELR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0ASEL : 4; + unsigned char G0BSEL : 4; +#else + unsigned char G0BSEL : 4; + unsigned char G0ASEL : 4; +#endif + } BIT; + } G0SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G1ASEL : 4; + unsigned char G1BSEL : 4; +#else + unsigned char G1BSEL : 4; + unsigned char G1ASEL : 4; +#endif + } BIT; + } G1SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G2ASEL : 4; + unsigned char G2BSEL : 4; +#else + unsigned char G2BSEL : 4; + unsigned char G2ASEL : 4; +#endif + } BIT; + } G2SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G3ASEL : 4; + unsigned char G3BSEL : 4; +#else + unsigned char G3BSEL : 4; + unsigned char G3ASEL : 4; +#endif + } BIT; + } G3SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G4ASEL : 4; + unsigned char G4BSEL : 4; +#else + unsigned char G4BSEL : 4; + unsigned char G4ASEL : 4; +#endif + } BIT; + } G4SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G5ASEL : 4; + unsigned char G5BSEL : 4; +#else + unsigned char G5BSEL : 4; + unsigned char G5ASEL : 4; +#endif + } BIT; + } G5SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G6ASEL : 4; + unsigned char G6BSEL : 4; +#else + unsigned char G6BSEL : 4; + unsigned char G6ASEL : 4; +#endif + } BIT; + } G6SELR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G7ASEL : 4; + unsigned char G7BSEL : 4; +#else + unsigned char G7BSEL : 4; + unsigned char G7ASEL : 4; +#endif + } BIT; + } G7SELR; + char wk5[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POE11MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POE11MS : 6; +#endif + } BIT; + } IMCR4; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POE12MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POE12MS : 6; +#endif + } BIT; + } IMCR5; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POE9MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char POE9MS : 6; +#endif + } BIT; + } IMCR6; + char wk6[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMP0MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CMP0MS : 6; +#endif + } BIT; + } IMCR9; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMP1MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CMP1MS : 6; +#endif + } BIT; + } IMCR10; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMP2MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CMP2MS : 6; +#endif + } BIT; + } IMCR11; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMP3MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CMP3MS : 6; +#endif + } BIT; + } IMCR12; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMP4MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CMP4MS : 6; +#endif + } BIT; + } IMCR13; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMP5MS : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CMP5MS : 6; +#endif + } BIT; + } IMCR14; +} st_poe_t; + +typedef struct st_poeg { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PIDF : 1; + unsigned long IOCF : 1; + unsigned long OSTPF : 1; + unsigned long SSF : 1; + unsigned long PIDE : 1; + unsigned long IOCE : 1; + unsigned long OSTPE : 1; + unsigned long : 1; + unsigned long CDRE0 : 1; + unsigned long CDRE1 : 1; + unsigned long CDRE2 : 1; + unsigned long CDRE3 : 1; + unsigned long CDRE4 : 1; + unsigned long CDRE5 : 1; + unsigned long : 2; + unsigned long ST : 1; + unsigned long : 7; + unsigned long NFPSC : 1; + unsigned long ELSEL : 1; + unsigned long NFSN : 2; + unsigned long INV : 1; + unsigned long NFEN : 1; + unsigned long NFCS : 2; +#else + unsigned long NFCS : 2; + unsigned long NFEN : 1; + unsigned long INV : 1; + unsigned long NFSN : 2; + unsigned long ELSEL : 1; + unsigned long NFPSC : 1; + unsigned long : 7; + unsigned long ST : 1; + unsigned long : 2; + unsigned long CDRE5 : 1; + unsigned long CDRE4 : 1; + unsigned long CDRE3 : 1; + unsigned long CDRE2 : 1; + unsigned long CDRE1 : 1; + unsigned long CDRE0 : 1; + unsigned long : 1; + unsigned long OSTPE : 1; + unsigned long IOCE : 1; + unsigned long PIDE : 1; + unsigned long SSF : 1; + unsigned long OSTPF : 1; + unsigned long IOCF : 1; + unsigned long PIDF : 1; +#endif + } BIT; + } POEGGA; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSEL : 5; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long MSEL : 5; +#endif + } BIT; + } POEGICRA; + char wk0[56]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WP : 1; + unsigned short : 7; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 7; + unsigned short WP : 1; +#endif + } BIT; + } GTONCWPA; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short NE : 1; + unsigned short : 3; + unsigned short NFS : 4; + unsigned short NFV : 1; + unsigned short : 2; + unsigned short MSEL : 5; +#else + unsigned short MSEL : 5; + unsigned short : 2; + unsigned short NFV : 1; + unsigned short NFS : 4; + unsigned short : 3; + unsigned short NE : 1; +#endif + } BIT; + } GTONCCRA; + char wk2[186]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PIDF : 1; + unsigned long IOCF : 1; + unsigned long OSTPF : 1; + unsigned long SSF : 1; + unsigned long PIDE : 1; + unsigned long IOCE : 1; + unsigned long OSTPE : 1; + unsigned long : 1; + unsigned long CDRE0 : 1; + unsigned long CDRE1 : 1; + unsigned long CDRE2 : 1; + unsigned long CDRE3 : 1; + unsigned long CDRE4 : 1; + unsigned long CDRE5 : 1; + unsigned long : 2; + unsigned long ST : 1; + unsigned long : 7; + unsigned long NFPSC : 1; + unsigned long ELSEL : 1; + unsigned long NFSN : 2; + unsigned long INV : 1; + unsigned long NFEN : 1; + unsigned long NFCS : 2; +#else + unsigned long NFCS : 2; + unsigned long NFEN : 1; + unsigned long INV : 1; + unsigned long NFSN : 2; + unsigned long ELSEL : 1; + unsigned long NFPSC : 1; + unsigned long : 7; + unsigned long ST : 1; + unsigned long : 2; + unsigned long CDRE5 : 1; + unsigned long CDRE4 : 1; + unsigned long CDRE3 : 1; + unsigned long CDRE2 : 1; + unsigned long CDRE1 : 1; + unsigned long CDRE0 : 1; + unsigned long : 1; + unsigned long OSTPE : 1; + unsigned long IOCE : 1; + unsigned long PIDE : 1; + unsigned long SSF : 1; + unsigned long OSTPF : 1; + unsigned long IOCF : 1; + unsigned long PIDF : 1; +#endif + } BIT; + } POEGGB; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSEL : 5; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long MSEL : 5; +#endif + } BIT; + } POEGICRB; + char wk3[56]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WP : 1; + unsigned short : 7; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 7; + unsigned short WP : 1; +#endif + } BIT; + } GTONCWPB; + char wk4[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short NE : 1; + unsigned short : 3; + unsigned short NFS : 4; + unsigned short NFV : 1; + unsigned short : 2; + unsigned short MSEL : 5; +#else + unsigned short MSEL : 5; + unsigned short : 2; + unsigned short NFV : 1; + unsigned short NFS : 4; + unsigned short : 3; + unsigned short NE : 1; +#endif + } BIT; + } GTONCCRB; + char wk5[186]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PIDF : 1; + unsigned long IOCF : 1; + unsigned long OSTPF : 1; + unsigned long SSF : 1; + unsigned long PIDE : 1; + unsigned long IOCE : 1; + unsigned long OSTPE : 1; + unsigned long : 1; + unsigned long CDRE0 : 1; + unsigned long CDRE1 : 1; + unsigned long CDRE2 : 1; + unsigned long CDRE3 : 1; + unsigned long CDRE4 : 1; + unsigned long CDRE5 : 1; + unsigned long : 2; + unsigned long ST : 1; + unsigned long : 7; + unsigned long NFPSC : 1; + unsigned long ELSEL : 1; + unsigned long NFSN : 2; + unsigned long INV : 1; + unsigned long NFEN : 1; + unsigned long NFCS : 2; +#else + unsigned long NFCS : 2; + unsigned long NFEN : 1; + unsigned long INV : 1; + unsigned long NFSN : 2; + unsigned long ELSEL : 1; + unsigned long NFPSC : 1; + unsigned long : 7; + unsigned long ST : 1; + unsigned long : 2; + unsigned long CDRE5 : 1; + unsigned long CDRE4 : 1; + unsigned long CDRE3 : 1; + unsigned long CDRE2 : 1; + unsigned long CDRE1 : 1; + unsigned long CDRE0 : 1; + unsigned long : 1; + unsigned long OSTPE : 1; + unsigned long IOCE : 1; + unsigned long PIDE : 1; + unsigned long SSF : 1; + unsigned long OSTPF : 1; + unsigned long IOCF : 1; + unsigned long PIDF : 1; +#endif + } BIT; + } POEGGC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSEL : 5; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long MSEL : 5; +#endif + } BIT; + } POEGICRC; + char wk6[56]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WP : 1; + unsigned short : 7; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 7; + unsigned short WP : 1; +#endif + } BIT; + } GTONCWPC; + char wk7[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short NE : 1; + unsigned short : 3; + unsigned short NFS : 4; + unsigned short NFV : 1; + unsigned short : 2; + unsigned short MSEL : 5; +#else + unsigned short MSEL : 5; + unsigned short : 2; + unsigned short NFV : 1; + unsigned short NFS : 4; + unsigned short : 3; + unsigned short NE : 1; +#endif + } BIT; + } GTONCCRC; + char wk8[186]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PIDF : 1; + unsigned long IOCF : 1; + unsigned long OSTPF : 1; + unsigned long SSF : 1; + unsigned long PIDE : 1; + unsigned long IOCE : 1; + unsigned long OSTPE : 1; + unsigned long : 1; + unsigned long CDRE0 : 1; + unsigned long CDRE1 : 1; + unsigned long CDRE2 : 1; + unsigned long CDRE3 : 1; + unsigned long CDRE4 : 1; + unsigned long CDRE5 : 1; + unsigned long : 2; + unsigned long ST : 1; + unsigned long : 7; + unsigned long NFPSC : 1; + unsigned long ELSEL : 1; + unsigned long NFSN : 2; + unsigned long INV : 1; + unsigned long NFEN : 1; + unsigned long NFCS : 2; +#else + unsigned long NFCS : 2; + unsigned long NFEN : 1; + unsigned long INV : 1; + unsigned long NFSN : 2; + unsigned long ELSEL : 1; + unsigned long NFPSC : 1; + unsigned long : 7; + unsigned long ST : 1; + unsigned long : 2; + unsigned long CDRE5 : 1; + unsigned long CDRE4 : 1; + unsigned long CDRE3 : 1; + unsigned long CDRE2 : 1; + unsigned long CDRE1 : 1; + unsigned long CDRE0 : 1; + unsigned long : 1; + unsigned long OSTPE : 1; + unsigned long IOCE : 1; + unsigned long PIDE : 1; + unsigned long SSF : 1; + unsigned long OSTPF : 1; + unsigned long IOCF : 1; + unsigned long PIDF : 1; +#endif + } BIT; + } POEGGD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSEL : 5; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long MSEL : 5; +#endif + } BIT; + } POEGICRD; + char wk9[56]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WP : 1; + unsigned short : 7; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 7; + unsigned short WP : 1; +#endif + } BIT; + } GTONCWPD; + char wk10[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short NE : 1; + unsigned short : 3; + unsigned short NFS : 4; + unsigned short NFV : 1; + unsigned short : 2; + unsigned short MSEL : 5; +#else + unsigned short MSEL : 5; + unsigned short : 2; + unsigned short NFV : 1; + unsigned short NFS : 4; + unsigned short : 3; + unsigned short NE : 1; +#endif + } BIT; + } GTONCCRD; +} st_poeg_t; + +typedef struct st_port { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short P0HLD : 1; + unsigned short P1HLD : 1; + unsigned short P2HLD : 1; + unsigned short P3HLD : 1; + unsigned short P4HLD : 1; + unsigned short P5HLD : 1; + unsigned short P6HLD : 1; + unsigned short P7HLD : 1; + unsigned short P8HLD : 1; + unsigned short P9HLD : 1; + unsigned short PAHLD : 1; + unsigned short PBHLD : 1; + unsigned short : 1; + unsigned short PDHLD : 1; + unsigned short PEHLD : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short PEHLD : 1; + unsigned short PDHLD : 1; + unsigned short : 1; + unsigned short PBHLD : 1; + unsigned short PAHLD : 1; + unsigned short P9HLD : 1; + unsigned short P8HLD : 1; + unsigned short P7HLD : 1; + unsigned short P6HLD : 1; + unsigned short P5HLD : 1; + unsigned short P4HLD : 1; + unsigned short P3HLD : 1; + unsigned short P2HLD : 1; + unsigned short P1HLD : 1; + unsigned short P0HLD : 1; +#endif + } BIT; + } POHSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 7; + unsigned short PNHLD : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short PNHLD : 1; + unsigned short : 7; +#endif + } BIT; + } POHSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POHE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char POHE : 1; +#endif + } BIT; + } POHCR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char GPSEMLE : 1; + unsigned char GPSMD : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char GPSMD : 1; + unsigned char GPSEMLE : 1; +#endif + } BIT; + } GPSEXT; +} st_port_t; + +typedef struct st_port0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + char wk4[63]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +} st_port0_t; + +typedef struct st_port1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + char wk4[62]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +} st_port1_t; + +typedef struct st_port2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 5; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 5; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +} st_port2_t; + +typedef struct st_port3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +} st_port3_t; + +typedef struct st_port4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[58]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_port4_t; + +typedef struct st_port5 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_port5_t; + +typedef struct st_port6 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[37]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[56]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_port6_t; + +typedef struct st_port7 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[38]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[55]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } DSCR2; +} st_port7_t; + +typedef struct st_port8 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[39]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + char wk4[55]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } DSCR2; +} st_port8_t; + +typedef struct st_port9 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[40]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[53]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR2; +} st_port9_t; + +typedef struct st_porta { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +} st_porta_t; + +typedef struct st_portb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 5; +#endif + } BIT; + } DSCR2; +} st_portb_t; + +typedef struct st_portd { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[44]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[49]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; + char wk6[71]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } DSCR2; +} st_portd_t; + +typedef struct st_porte { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 3; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 3; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +} st_porte_t; + +typedef struct st_portn { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } PMR; + char wk3[54]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } ODR1; + char wk4[40]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } DSCR; +} st_portn_t; + +typedef struct st_ram { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMMODE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char RAMMODE : 2; +#endif + } BIT; + } RAMMODE; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RAMERR : 1; +#endif + } BIT; + } RAMSTS; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMPRCR : 1; + unsigned char KW : 7; +#else + unsigned char KW : 7; + unsigned char RAMPRCR : 1; +#endif + } BIT; + } RAMPRCR; + char wk1[3]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long READ : 16; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long READ : 16; + unsigned long : 3; +#endif + } BIT; + } RAMECAD; +} st_ram_t; + +typedef struct st_ri3c { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OMS : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long OMS : 1; +#endif + } BIT; + } ICMR; + char wk0[16]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IBAINC : 1; + unsigned long : 7; + unsigned long HJC : 1; + unsigned long : 20; + unsigned long ABORT : 1; + unsigned long RESUME : 1; + unsigned long ICE : 1; +#else + unsigned long ICE : 1; + unsigned long RESUME : 1; + unsigned long ABORT : 1; + unsigned long : 20; + unsigned long HJC : 1; + unsigned long : 7; + unsigned long IBAINC : 1; +#endif + } BIT; + } ICCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long DADR : 7; + unsigned long : 8; + unsigned long DAV : 1; +#else + unsigned long DAV : 1; + unsigned long : 8; + unsigned long DADR : 7; + unsigned long : 16; +#endif + } BIT; + } ICCAR; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MRST : 1; + unsigned long CQRST : 1; + unsigned long RQRST : 1; + unsigned long TBRST : 1; + unsigned long RBRST : 1; + unsigned long IQRST : 1; + unsigned long SQRST : 1; + unsigned long : 9; + unsigned long ISRST : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long ISRST : 1; + unsigned long : 9; + unsigned long SQRST : 1; + unsigned long IQRST : 1; + unsigned long RBRST : 1; + unsigned long TBRST : 1; + unsigned long RQRST : 1; + unsigned long CQRST : 1; + unsigned long MRST : 1; +#endif + } BIT; + } ICRCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 2; + unsigned long ACF : 1; + unsigned long : 4; + unsigned long WP : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long WP : 1; + unsigned long : 4; + unsigned long ACF : 1; + unsigned long : 2; +#endif + } BIT; + } ICMMR; + char wk2[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 10; + unsigned long BERF : 1; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long BERF : 1; + unsigned long : 10; +#endif + } BIT; + } ICISR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 10; + unsigned long BERDE : 1; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long BERDE : 1; + unsigned long : 10; +#endif + } BIT; + } ICISER; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 10; + unsigned long BERIE : 1; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long BERIE : 1; + unsigned long : 10; +#endif + } BIT; + } ICISIER; + char wk3[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 19; + unsigned long INDEX : 5; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long INDEX : 5; + unsigned long : 19; +#endif + } BIT; + } ICDCTIR; + char wk4[16]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RHJRN : 1; + unsigned long RCRRN : 1; + unsigned long : 1; + unsigned long RTIRN : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long RTIRN : 1; + unsigned long : 1; + unsigned long RCRRN : 1; + unsigned long RHJRN : 1; +#endif + } BIT; + } ICINCR; + char wk5[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long TA0DE : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long TA0DE : 1; + unsigned long : 16; +#endif + } BIT; + } ICTCR; + char wk6[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ODLW : 8; + unsigned long ODHW : 8; + unsigned long PPLW : 6; + unsigned long : 2; + unsigned long PPHW : 6; + unsigned long : 1; + unsigned long ODDBL : 1; +#else + unsigned long ODDBL : 1; + unsigned long : 1; + unsigned long PPHW : 6; + unsigned long : 2; + unsigned long PPLW : 6; + unsigned long ODHW : 8; + unsigned long ODLW : 8; +#endif + } BIT; + } ICSBR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ODLW : 8; + unsigned long ODHW : 8; + unsigned long PPLW : 6; + unsigned long : 2; + unsigned long PPHW : 6; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long PPHW : 6; + unsigned long : 2; + unsigned long PPLW : 6; + unsigned long ODHW : 8; + unsigned long ODLW : 8; +#endif + } BIT; + } ICEBR; + unsigned long ICBFTR; + unsigned long ICBATR; + unsigned long ICBITR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SDAO : 1; + unsigned long SCLO : 1; + unsigned long SOWP : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long SOWP : 1; + unsigned long SCLO : 1; + unsigned long SDAO : 1; +#endif + } BIT; + } ICOCR; + char wk7[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TMOS : 2; + unsigned long : 2; + unsigned long TMOL : 1; + unsigned long TMOH : 1; + unsigned long TMOM : 2; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long TMOM : 2; + unsigned long TMOH : 1; + unsigned long TMOL : 1; + unsigned long : 2; + unsigned long TMOS : 2; +#endif + } BIT; + } ICTOR; + char wk8[28]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STT : 16; + unsigned long : 12; + unsigned long AASE : 1; + unsigned long : 1; + unsigned long PBSE : 1; + unsigned long APSE : 1; +#else + unsigned long APSE : 1; + unsigned long PBSE : 1; + unsigned long : 1; + unsigned long AASE : 1; + unsigned long : 12; + unsigned long STT : 16; +#endif + } BIT; + } ICSTCR; + char wk9[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long DLGTH : 16; +#else + unsigned long DLGTH : 16; + unsigned long : 16; +#endif + } BIT; + } ICTDLR; + char wk10[140]; + unsigned long ICCQR; + unsigned long ICRQR; + union { + unsigned long LONG; + unsigned char BYTE; + } ICDR; + char wk11[32]; + unsigned long ICIQR; + unsigned long ICSQR; + char wk12[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CQTH : 8; + unsigned long RQTH : 8; + unsigned long IDSS : 8; + unsigned long IQTH : 8; +#else + unsigned long IQTH : 8; + unsigned long IDSS : 8; + unsigned long RQTH : 8; + unsigned long CQTH : 8; +#endif + } BIT; + } ICQBTCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TETH : 3; + unsigned long : 5; + unsigned long RFTH : 3; + unsigned long : 5; + unsigned long TSTH : 3; + unsigned long : 5; + unsigned long RSTH : 3; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long RSTH : 3; + unsigned long : 5; + unsigned long TSTH : 3; + unsigned long : 5; + unsigned long RFTH : 3; + unsigned long : 5; + unsigned long TETH : 3; +#endif + } BIT; + } ICDBTCR; + char wk13[40]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SQTH : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long SQTH : 8; +#endif + } BIT; + } ICSQTCR; + char wk14[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long START : 1; + unsigned long STOP : 1; + unsigned long HDRXDF : 1; + unsigned long : 17; + unsigned long TMOF : 1; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long TMOF : 1; + unsigned long : 17; + unsigned long HDRXDF : 1; + unsigned long STOP : 1; + unsigned long START : 1; +#endif + } BIT; + } ICSR2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STDE : 1; + unsigned long SPDE : 1; + unsigned long HDRXDE : 1; + unsigned long : 17; + unsigned long TMOE : 1; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long TMOE : 1; + unsigned long : 17; + unsigned long HDRXDE : 1; + unsigned long SPDE : 1; + unsigned long STDE : 1; +#endif + } BIT; + } ICSER; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STIE : 1; + unsigned long SPIE : 1; + unsigned long HDRXIE : 1; + unsigned long : 17; + unsigned long TMOIE : 1; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long TMOIE : 1; + unsigned long : 17; + unsigned long HDRXIE : 1; + unsigned long SPIE : 1; + unsigned long STIE : 1; +#endif + } BIT; + } ICSIER; + char wk15[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TDRE : 1; + unsigned long RDRF : 1; + unsigned long IQEFF : 1; + unsigned long CQEF : 1; + unsigned long RQFF : 1; + unsigned long DTAF : 1; + unsigned long : 3; + unsigned long DTEF : 1; + unsigned long : 10; + unsigned long SQFF : 1; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long SQFF : 1; + unsigned long : 10; + unsigned long DTEF : 1; + unsigned long : 3; + unsigned long DTAF : 1; + unsigned long RQFF : 1; + unsigned long CQEF : 1; + unsigned long IQEFF : 1; + unsigned long RDRF : 1; + unsigned long TDRE : 1; +#endif + } BIT; + } ICCSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TDE : 1; + unsigned long RDE : 1; + unsigned long IQEFDE : 1; + unsigned long CQEDE : 1; + unsigned long RQFDE : 1; + unsigned long DTADE : 1; + unsigned long : 3; + unsigned long DTEDE : 1; + unsigned long : 10; + unsigned long SQFDE : 1; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long SQFDE : 1; + unsigned long : 10; + unsigned long DTEDE : 1; + unsigned long : 3; + unsigned long DTADE : 1; + unsigned long RQFDE : 1; + unsigned long CQEDE : 1; + unsigned long IQEFDE : 1; + unsigned long RDE : 1; + unsigned long TDE : 1; +#endif + } BIT; + } ICCSER; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TIE : 1; + unsigned long RIE : 1; + unsigned long IQEFIE : 1; + unsigned long CQEIE : 1; + unsigned long RQFIE : 1; + unsigned long DTAIE : 1; + unsigned long : 3; + unsigned long DTEIE : 1; + unsigned long : 10; + unsigned long SQFIE : 1; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long SQFIE : 1; + unsigned long : 10; + unsigned long DTEIE : 1; + unsigned long : 3; + unsigned long DTAIE : 1; + unsigned long RQFIE : 1; + unsigned long CQEIE : 1; + unsigned long IQEFIE : 1; + unsigned long RIE : 1; + unsigned long TIE : 1; +#endif + } BIT; + } ICCSIER; + char wk16[36]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BFREE : 1; + unsigned long BAVL : 1; + unsigned long BIDL : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long BIDL : 1; + unsigned long BAVL : 1; + unsigned long BFREE : 1; +#endif + } BIT; + } ICBSR; + char wk17[16]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SADR : 7; + unsigned long : 5; + unsigned long IBIPL : 1; + unsigned long TIRRJ : 1; + unsigned long CRRRJ : 1; + unsigned long IBITSE : 1; + unsigned long DADR : 8; + unsigned long : 5; + unsigned long NACKRC : 2; + unsigned long TYPE : 1; +#else + unsigned long TYPE : 1; + unsigned long NACKRC : 2; + unsigned long : 5; + unsigned long DADR : 8; + unsigned long IBITSE : 1; + unsigned long CRRRJ : 1; + unsigned long TIRRJ : 1; + unsigned long IBIPL : 1; + unsigned long : 5; + unsigned long SADR : 7; +#endif + } BIT; + } ICTDATR0; + char wk18[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SADR : 7; + unsigned long : 5; + unsigned long IBIPL : 1; + unsigned long TIRRJ : 1; + unsigned long CRRRJ : 1; + unsigned long IBITSE : 1; + unsigned long DADR : 8; + unsigned long : 5; + unsigned long NACKRC : 2; + unsigned long TYPE : 1; +#else + unsigned long TYPE : 1; + unsigned long NACKRC : 2; + unsigned long : 5; + unsigned long DADR : 8; + unsigned long IBITSE : 1; + unsigned long CRRRJ : 1; + unsigned long TIRRJ : 1; + unsigned long IBIPL : 1; + unsigned long : 5; + unsigned long SADR : 7; +#endif + } BIT; + } ICTDATR1; + char wk19[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SADR : 7; + unsigned long : 5; + unsigned long IBIPL : 1; + unsigned long TIRRJ : 1; + unsigned long CRRRJ : 1; + unsigned long IBITSE : 1; + unsigned long DADR : 8; + unsigned long : 5; + unsigned long NACKRC : 2; + unsigned long TYPE : 1; +#else + unsigned long TYPE : 1; + unsigned long NACKRC : 2; + unsigned long : 5; + unsigned long DADR : 8; + unsigned long IBITSE : 1; + unsigned long CRRRJ : 1; + unsigned long TIRRJ : 1; + unsigned long IBIPL : 1; + unsigned long : 5; + unsigned long SADR : 7; +#endif + } BIT; + } ICTDATR2; + char wk20[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SADR : 7; + unsigned long : 5; + unsigned long IBIPL : 1; + unsigned long TIRRJ : 1; + unsigned long CRRRJ : 1; + unsigned long IBITSE : 1; + unsigned long DADR : 8; + unsigned long : 5; + unsigned long NACKRC : 2; + unsigned long TYPE : 1; +#else + unsigned long TYPE : 1; + unsigned long NACKRC : 2; + unsigned long : 5; + unsigned long DADR : 8; + unsigned long IBITSE : 1; + unsigned long CRRRJ : 1; + unsigned long TIRRJ : 1; + unsigned long IBIPL : 1; + unsigned long : 5; + unsigned long SADR : 7; +#endif + } BIT; + } ICTDATR3; + char wk21[96]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SADR : 7; + unsigned long : 9; + unsigned long DADR : 8; + unsigned long : 5; + unsigned long NACKRC : 2; + unsigned long TYPE : 1; +#else + unsigned long TYPE : 1; + unsigned long NACKRC : 2; + unsigned long : 5; + unsigned long DADR : 8; + unsigned long : 9; + unsigned long SADR : 7; +#endif + } BIT; + } ICEDATR; + char wk22[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SADR : 10; + unsigned long : 2; + unsigned long IBIPL : 1; + unsigned long : 3; + unsigned long DADR : 7; + unsigned long : 9; +#else + unsigned long : 9; + unsigned long DADR : 7; + unsigned long : 3; + unsigned long IBIPL : 1; + unsigned long : 2; + unsigned long SADR : 10; +#endif + } BIT; + } ICDAR0; + char wk23[28]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long LIMIT : 1; + unsigned long IBIRQC : 1; + unsigned long IBIPL : 1; + unsigned long OFLC : 1; + unsigned long : 2; + unsigned long ROLE : 2; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ROLE : 2; + unsigned long : 2; + unsigned long OFLC : 1; + unsigned long IBIPL : 1; + unsigned long IBIRQC : 1; + unsigned long LIMIT : 1; + unsigned long : 8; +#endif + } BIT; + } ICTDCTR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long LIMIT : 1; + unsigned long IBIRQC : 1; + unsigned long IBIPL : 1; + unsigned long OFLC : 1; + unsigned long : 2; + unsigned long ROLE : 2; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ROLE : 2; + unsigned long : 2; + unsigned long OFLC : 1; + unsigned long IBIPL : 1; + unsigned long IBIRQC : 1; + unsigned long LIMIT : 1; + unsigned long : 8; +#endif + } BIT; + } ICTDCTR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long LIMIT : 1; + unsigned long IBIRQC : 1; + unsigned long IBIPL : 1; + unsigned long OFLC : 1; + unsigned long : 2; + unsigned long ROLE : 2; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ROLE : 2; + unsigned long : 2; + unsigned long OFLC : 1; + unsigned long IBIPL : 1; + unsigned long IBIRQC : 1; + unsigned long LIMIT : 1; + unsigned long : 8; +#endif + } BIT; + } ICTDCTR2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long LIMIT : 1; + unsigned long IBIRQC : 1; + unsigned long IBIPL : 1; + unsigned long OFLC : 1; + unsigned long : 2; + unsigned long ROLE : 2; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ROLE : 2; + unsigned long : 2; + unsigned long OFLC : 1; + unsigned long IBIPL : 1; + unsigned long IBIRQC : 1; + unsigned long LIMIT : 1; + unsigned long : 8; +#endif + } BIT; + } ICTDCTR3; + char wk24[64]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DCR : 8; + unsigned long LIMIT : 1; + unsigned long IBIRQC : 1; + unsigned long IBIPL : 1; + unsigned long OFLC : 1; + unsigned long : 2; + unsigned long ROLE : 2; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ROLE : 2; + unsigned long : 2; + unsigned long OFLC : 1; + unsigned long IBIPL : 1; + unsigned long IBIRQC : 1; + unsigned long LIMIT : 1; + unsigned long DCR : 8; +#endif + } BIT; + } ICDCTR; + unsigned long ICPIDLR; + unsigned long ICPIDHR; + char wk25[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long TADR : 10; + unsigned long : 4; + unsigned long SAV : 1; + unsigned long DAV : 1; +#else + unsigned long DAV : 1; + unsigned long SAV : 1; + unsigned long : 4; + unsigned long TADR : 10; + unsigned long : 16; +#endif + } BIT; + } ICDAMR0; + char wk26[28]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ENINT : 1; + unsigned long ENCR : 1; + unsigned long : 1; + unsigned long ENHJ : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long ENHJ : 1; + unsigned long : 1; + unsigned long ENCR : 1; + unsigned long ENINT : 1; +#endif + } BIT; + } ICTEVR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ENTAS0 : 1; + unsigned long ENTAS1 : 1; + unsigned long ENTAS2 : 1; + unsigned long ENTAS3 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long ENTAS3 : 1; + unsigned long ENTAS2 : 1; + unsigned long ENTAS1 : 1; + unsigned long ENTAS0 : 1; +#endif + } BIT; + } ICASR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MWL : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MWL : 16; +#endif + } BIT; + } ICMWLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MRL : 16; + unsigned long IBIPL : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long IBIPL : 8; + unsigned long MRL : 16; +#endif + } BIT; + } ICMRLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TM : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long TM : 8; +#endif + } BIT; + } ICTMR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PNDINT : 4; + unsigned long : 1; + unsigned long PERR : 1; + unsigned long CAS : 2; + unsigned long VRSV : 8; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long VRSV : 8; + unsigned long CAS : 2; + unsigned long PERR : 1; + unsigned long : 1; + unsigned long PNDINT : 4; +#endif + } BIT; + } ICDSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSWDR : 3; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long MSWDR : 3; +#endif + } BIT; + } ICMWSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSRDR : 3; + unsigned long TSCO : 3; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long TSCO : 3; + unsigned long MSRDR : 3; +#endif + } BIT; + } ICMRSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MRTT : 24; + unsigned long : 7; + unsigned long MRTTE : 1; +#else + unsigned long MRTTE : 1; + unsigned long : 7; + unsigned long MRTT : 24; +#endif + } BIT; + } ICMTTR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long FREQ : 8; + unsigned long INAC : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long INAC : 8; + unsigned long FREQ : 8; + unsigned long : 8; +#endif + } BIT; + } ICTSIR; + char wk27[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BC : 5; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long BC : 5; +#endif + } BIT; + } ICBCR; + char wk28[16]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CQFL : 8; + unsigned long RQFL : 8; + unsigned long IQFL : 8; + unsigned long ISC : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long ISC : 5; + unsigned long IQFL : 8; + unsigned long RQFL : 8; + unsigned long CQFL : 8; +#endif + } BIT; + } ICQBSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TBFL : 8; + unsigned long RBFL : 8; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long RBFL : 8; + unsigned long TBFL : 8; +#endif + } BIT; + } ICDBSR; + char wk29[36]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SQFL : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long SQFL : 8; +#endif + } BIT; + } ICSQSR; + char wk30[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SCLI : 1; + unsigned long SDAI : 1; + unsigned long SCLO : 1; + unsigned long SDAO : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long SDAO : 1; + unsigned long SCLO : 1; + unsigned long SDAI : 1; + unsigned long SCLI : 1; +#endif + } BIT; + } ICIMR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CE2C : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long CE2C : 8; +#endif + } BIT; + } ICCECR; +} st_ri3c_t; + +typedef struct st_riic { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDAI : 1; + unsigned char SCLI : 1; + unsigned char SDAO : 1; + unsigned char SCLO : 1; + unsigned char SOWP : 1; + unsigned char CLO : 1; + unsigned char IICRST : 1; + unsigned char ICE : 1; +#else + unsigned char ICE : 1; + unsigned char IICRST : 1; + unsigned char CLO : 1; + unsigned char SOWP : 1; + unsigned char SCLO : 1; + unsigned char SDAO : 1; + unsigned char SCLI : 1; + unsigned char SDAI : 1; +#endif + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char ST : 1; + unsigned char RS : 1; + unsigned char SP : 1; + unsigned char : 1; + unsigned char TRS : 1; + unsigned char MST : 1; + unsigned char BBSY : 1; +#else + unsigned char BBSY : 1; + unsigned char MST : 1; + unsigned char TRS : 1; + unsigned char : 1; + unsigned char SP : 1; + unsigned char RS : 1; + unsigned char ST : 1; + unsigned char : 1; +#endif + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BC : 3; + unsigned char BCWP : 1; + unsigned char CKS : 3; + unsigned char MTWP : 1; +#else + unsigned char MTWP : 1; + unsigned char CKS : 3; + unsigned char BCWP : 1; + unsigned char BC : 3; +#endif + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOS : 1; + unsigned char TMOL : 1; + unsigned char TMOH : 1; + unsigned char : 1; + unsigned char SDDL : 3; + unsigned char DLCS : 1; +#else + unsigned char DLCS : 1; + unsigned char SDDL : 3; + unsigned char : 1; + unsigned char TMOH : 1; + unsigned char TMOL : 1; + unsigned char TMOS : 1; +#endif + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NF : 2; + unsigned char ACKBR : 1; + unsigned char ACKBT : 1; + unsigned char ACKWP : 1; + unsigned char RDRFS : 1; + unsigned char WAIT : 1; + unsigned char SMBS : 1; +#else + unsigned char SMBS : 1; + unsigned char WAIT : 1; + unsigned char RDRFS : 1; + unsigned char ACKWP : 1; + unsigned char ACKBT : 1; + unsigned char ACKBR : 1; + unsigned char NF : 2; +#endif + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOE : 1; + unsigned char MALE : 1; + unsigned char NALE : 1; + unsigned char SALE : 1; + unsigned char NACKE : 1; + unsigned char NFE : 1; + unsigned char SCLE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SCLE : 1; + unsigned char NFE : 1; + unsigned char NACKE : 1; + unsigned char SALE : 1; + unsigned char NALE : 1; + unsigned char MALE : 1; + unsigned char TMOE : 1; +#endif + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SAR0E : 1; + unsigned char SAR1E : 1; + unsigned char SAR2E : 1; + unsigned char GCAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char HOAE : 1; +#else + unsigned char HOAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char GCAE : 1; + unsigned char SAR2E : 1; + unsigned char SAR1E : 1; + unsigned char SAR0E : 1; +#endif + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOIE : 1; + unsigned char ALIE : 1; + unsigned char STIE : 1; + unsigned char SPIE : 1; + unsigned char NAKIE : 1; + unsigned char RIE : 1; + unsigned char TEIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char TEIE : 1; + unsigned char RIE : 1; + unsigned char NAKIE : 1; + unsigned char SPIE : 1; + unsigned char STIE : 1; + unsigned char ALIE : 1; + unsigned char TMOIE : 1; +#endif + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AAS0 : 1; + unsigned char AAS1 : 1; + unsigned char AAS2 : 1; + unsigned char GCA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char HOA : 1; +#else + unsigned char HOA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char GCA : 1; + unsigned char AAS2 : 1; + unsigned char AAS1 : 1; + unsigned char AAS0 : 1; +#endif + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOF : 1; + unsigned char AL : 1; + unsigned char START : 1; + unsigned char STOP : 1; + unsigned char NACKF : 1; + unsigned char RDRF : 1; + unsigned char TEND : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char TEND : 1; + unsigned char RDRF : 1; + unsigned char NACKF : 1; + unsigned char STOP : 1; + unsigned char START : 1; + unsigned char AL : 1; + unsigned char TMOF : 1; +#endif + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRL : 5; +#endif + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRH : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRH : 5; +#endif + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +} st_riic_t; + +typedef struct st_rsci8 { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RDAT : 9; + unsigned long MPB : 1; + unsigned long DR : 1; + unsigned long PER : 1; + unsigned long FER : 1; + unsigned long : 11; + unsigned long ORER : 1; + unsigned long : 2; + unsigned long APER : 1; + unsigned long AFER : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long AFER : 1; + unsigned long APER : 1; + unsigned long : 2; + unsigned long ORER : 1; + unsigned long : 11; + unsigned long FER : 1; + unsigned long PER : 1; + unsigned long DR : 1; + unsigned long MPB : 1; + unsigned long RDAT : 9; +#endif + } BIT; + } RDR; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TDAT : 9; + unsigned long MPBT : 1; + unsigned long : 2; + unsigned long SYNC : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long SYNC : 1; + unsigned long : 2; + unsigned long MPBT : 1; + unsigned long TDAT : 9; +#endif + } BIT; + } TDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RE : 1; + unsigned long : 3; + unsigned long TE : 1; + unsigned long : 3; + unsigned long MPIE : 1; + unsigned long DCME : 1; + unsigned long IDSEL : 1; + unsigned long : 5; + unsigned long RIE : 1; + unsigned long : 3; + unsigned long TIE : 1; + unsigned long TEIE : 1; + unsigned long : 2; + unsigned long SSE : 1; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long SSE : 1; + unsigned long : 2; + unsigned long TEIE : 1; + unsigned long TIE : 1; + unsigned long : 3; + unsigned long RIE : 1; + unsigned long : 5; + unsigned long IDSEL : 1; + unsigned long DCME : 1; + unsigned long MPIE : 1; + unsigned long : 3; + unsigned long TE : 1; + unsigned long : 3; + unsigned long RE : 1; +#endif + } BIT; + } SCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CTSE : 1; + unsigned long CRSEP : 1; + unsigned long : 2; + unsigned long SPB2DT : 1; + unsigned long SPB2IO : 1; + unsigned long : 2; + unsigned long PE : 1; + unsigned long PM : 1; + unsigned long : 2; + unsigned long TINV : 1; + unsigned long RINV : 1; + unsigned long : 2; + unsigned long LOOP : 1; + unsigned long : 3; + unsigned long HDSEL : 1; + unsigned long : 3; + unsigned long NFCS : 3; + unsigned long : 1; + unsigned long NFEN : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long NFEN : 1; + unsigned long : 1; + unsigned long NFCS : 3; + unsigned long : 3; + unsigned long HDSEL : 1; + unsigned long : 3; + unsigned long LOOP : 1; + unsigned long : 2; + unsigned long RINV : 1; + unsigned long TINV : 1; + unsigned long : 2; + unsigned long PM : 1; + unsigned long PE : 1; + unsigned long : 2; + unsigned long SPB2IO : 1; + unsigned long SPB2DT : 1; + unsigned long : 2; + unsigned long CRSEP : 1; + unsigned long CTSE : 1; +#endif + } BIT; + } SCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BCP : 3; + unsigned long : 1; + unsigned long BGDM : 1; + unsigned long ABCS : 1; + unsigned long ABCSE : 1; + unsigned long : 1; + unsigned long BRR : 8; + unsigned long BRME : 1; + unsigned long : 3; + unsigned long CKS : 2; + unsigned long : 2; + unsigned long MDDR : 8; +#else + unsigned long MDDR : 8; + unsigned long : 2; + unsigned long CKS : 2; + unsigned long : 3; + unsigned long BRME : 1; + unsigned long BRR : 8; + unsigned long : 1; + unsigned long ABCSE : 1; + unsigned long ABCS : 1; + unsigned long BGDM : 1; + unsigned long : 1; + unsigned long BCP : 3; +#endif + } BIT; + } SCR2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CPHA : 1; + unsigned long CPOL : 1; + unsigned long : 5; + unsigned long SYNDIS : 1; + unsigned long CHR : 2; + unsigned long : 2; + unsigned long DDIR : 1; + unsigned long DINV : 1; + unsigned long STOP : 1; + unsigned long RXDESEL : 1; + unsigned long MOD : 3; + unsigned long MP : 1; + unsigned long FM : 1; + unsigned long DEEN : 1; + unsigned long : 2; + unsigned long CKE : 2; + unsigned long : 2; + unsigned long GM : 1; + unsigned long BLK : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long BLK : 1; + unsigned long GM : 1; + unsigned long : 2; + unsigned long CKE : 2; + unsigned long : 2; + unsigned long DEEN : 1; + unsigned long FM : 1; + unsigned long MP : 1; + unsigned long MOD : 3; + unsigned long RXDESEL : 1; + unsigned long STOP : 1; + unsigned long DINV : 1; + unsigned long DDIR : 1; + unsigned long : 2; + unsigned long CHR : 2; + unsigned long SYNDIS : 1; + unsigned long : 5; + unsigned long CPOL : 1; + unsigned long CPHA : 1; +#endif + } BIT; + } SCR3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMPD : 9; + unsigned long : 7; + unsigned long RTADJ : 1; + unsigned long TTADJ : 1; + unsigned long : 6; + unsigned long RTMG : 4; + unsigned long TTMG : 4; +#else + unsigned long TTMG : 4; + unsigned long RTMG : 4; + unsigned long : 6; + unsigned long TTADJ : 1; + unsigned long RTADJ : 1; + unsigned long : 7; + unsigned long CMPD : 9; +#endif + } BIT; + } SCR4; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HBSE : 1; + unsigned char : 1; + unsigned char AOE : 1; + unsigned char LPS : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char LPS : 1; + unsigned char AOE : 1; + unsigned char : 1; + unsigned char HBSE : 1; +#endif + } BIT; + } HBSCR; + char wk1[1]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IICDL : 5; + unsigned long : 3; + unsigned long IICINTM : 1; + unsigned long IICCSC : 1; + unsigned long : 3; + unsigned long IICACKT : 1; + unsigned long : 2; + unsigned long IICSTAREQ : 1; + unsigned long IICRSTAREQ : 1; + unsigned long IICSTPREQ : 1; + unsigned long : 1; + unsigned long IICSDAS : 2; + unsigned long IICSCLS : 2; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long IICSCLS : 2; + unsigned long IICSDAS : 2; + unsigned long : 1; + unsigned long IICSTPREQ : 1; + unsigned long IICRSTAREQ : 1; + unsigned long IICSTAREQ : 1; + unsigned long : 2; + unsigned long IICACKT : 1; + unsigned long : 3; + unsigned long IICCSC : 1; + unsigned long IICINTM : 1; + unsigned long : 3; + unsigned long IICDL : 5; +#endif + } BIT; + } SIMR; + char wk2[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DELVL : 1; + unsigned long : 7; + unsigned long DESU : 5; + unsigned long : 3; + unsigned long DEHLD : 5; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long DEHLD : 5; + unsigned long : 3; + unsigned long DESU : 5; + unsigned long : 7; + unsigned long DELVL : 1; +#endif + } BIT; + } DECR; + char wk3[20]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long ERS : 1; + unsigned long : 10; + unsigned long RXDMON : 1; + unsigned long DCMF : 1; + unsigned long DPER : 1; + unsigned long DFER : 1; + unsigned long : 5; + unsigned long ORER : 1; + unsigned long : 1; + unsigned long MFF : 1; + unsigned long APER : 1; + unsigned long AFER : 1; + unsigned long TDRE : 1; + unsigned long TEND : 1; + unsigned long RDRF : 1; +#else + unsigned long RDRF : 1; + unsigned long TEND : 1; + unsigned long TDRE : 1; + unsigned long AFER : 1; + unsigned long APER : 1; + unsigned long MFF : 1; + unsigned long : 1; + unsigned long ORER : 1; + unsigned long : 5; + unsigned long DFER : 1; + unsigned long DPER : 1; + unsigned long DCMF : 1; + unsigned long RXDMON : 1; + unsigned long : 10; + unsigned long ERS : 1; + unsigned long : 4; +#endif + } BIT; + } SSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IICACKR : 1; + unsigned long : 2; + unsigned long IICSTIF : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long IICSTIF : 1; + unsigned long : 2; + unsigned long IICACKR : 1; +#endif + } BIT; + } SISR; + char wk4[24]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long ERSC : 1; + unsigned long : 11; + unsigned long DCMFC : 1; + unsigned long DPERC : 1; + unsigned long DFERC : 1; + unsigned long : 5; + unsigned long ORERC : 1; + unsigned long : 1; + unsigned long MFFC : 1; + unsigned long APERC : 1; + unsigned long AFERC : 1; + unsigned long TDREC : 1; + unsigned long : 1; + unsigned long RDRFC : 1; +#else + unsigned long RDRFC : 1; + unsigned long : 1; + unsigned long TDREC : 1; + unsigned long AFERC : 1; + unsigned long APERC : 1; + unsigned long MFFC : 1; + unsigned long : 1; + unsigned long ORERC : 1; + unsigned long : 5; + unsigned long DFERC : 1; + unsigned long DPERC : 1; + unsigned long DCMFC : 1; + unsigned long : 11; + unsigned long ERSC : 1; + unsigned long : 4; +#endif + } BIT; + } SSCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long IICSTIFC : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long IICSTIFC : 1; + unsigned long : 3; +#endif + } BIT; + } SISCR; +} st_rsci8_t; + +typedef struct st_rsci9 { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RDAT : 9; + unsigned long MPB : 1; + unsigned long DR : 1; + unsigned long PER : 1; + unsigned long FER : 1; + unsigned long : 11; + unsigned long ORER : 1; + unsigned long : 2; + unsigned long APER : 1; + unsigned long AFER : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long AFER : 1; + unsigned long APER : 1; + unsigned long : 2; + unsigned long ORER : 1; + unsigned long : 11; + unsigned long FER : 1; + unsigned long PER : 1; + unsigned long DR : 1; + unsigned long MPB : 1; + unsigned long RDAT : 9; +#endif + } BIT; + } RDR; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TDAT : 9; + unsigned long MPBT : 1; + unsigned long : 2; + unsigned long SYNC : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long SYNC : 1; + unsigned long : 2; + unsigned long MPBT : 1; + unsigned long TDAT : 9; +#endif + } BIT; + } TDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RE : 1; + unsigned long : 3; + unsigned long TE : 1; + unsigned long : 3; + unsigned long MPIE : 1; + unsigned long DCME : 1; + unsigned long IDSEL : 1; + unsigned long : 5; + unsigned long RIE : 1; + unsigned long : 3; + unsigned long TIE : 1; + unsigned long TEIE : 1; + unsigned long : 2; + unsigned long SSE : 1; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long SSE : 1; + unsigned long : 2; + unsigned long TEIE : 1; + unsigned long TIE : 1; + unsigned long : 3; + unsigned long RIE : 1; + unsigned long : 5; + unsigned long IDSEL : 1; + unsigned long DCME : 1; + unsigned long MPIE : 1; + unsigned long : 3; + unsigned long TE : 1; + unsigned long : 3; + unsigned long RE : 1; +#endif + } BIT; + } SCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CTSE : 1; + unsigned long CRSEP : 1; + unsigned long : 2; + unsigned long SPB2DT : 1; + unsigned long SPB2IO : 1; + unsigned long : 2; + unsigned long PE : 1; + unsigned long PM : 1; + unsigned long : 2; + unsigned long TINV : 1; + unsigned long RINV : 1; + unsigned long : 2; + unsigned long LOOP : 1; + unsigned long : 3; + unsigned long HDSEL : 1; + unsigned long : 3; + unsigned long NFCS : 3; + unsigned long : 1; + unsigned long NFEN : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long NFEN : 1; + unsigned long : 1; + unsigned long NFCS : 3; + unsigned long : 3; + unsigned long HDSEL : 1; + unsigned long : 3; + unsigned long LOOP : 1; + unsigned long : 2; + unsigned long RINV : 1; + unsigned long TINV : 1; + unsigned long : 2; + unsigned long PM : 1; + unsigned long PE : 1; + unsigned long : 2; + unsigned long SPB2IO : 1; + unsigned long SPB2DT : 1; + unsigned long : 2; + unsigned long CRSEP : 1; + unsigned long CTSE : 1; +#endif + } BIT; + } SCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BCP : 3; + unsigned long : 1; + unsigned long BGDM : 1; + unsigned long ABCS : 1; + unsigned long ABCSE : 1; + unsigned long : 1; + unsigned long BRR : 8; + unsigned long BRME : 1; + unsigned long : 3; + unsigned long CKS : 2; + unsigned long : 2; + unsigned long MDDR : 8; +#else + unsigned long MDDR : 8; + unsigned long : 2; + unsigned long CKS : 2; + unsigned long : 3; + unsigned long BRME : 1; + unsigned long BRR : 8; + unsigned long : 1; + unsigned long ABCSE : 1; + unsigned long ABCS : 1; + unsigned long BGDM : 1; + unsigned long : 1; + unsigned long BCP : 3; +#endif + } BIT; + } SCR2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CPHA : 1; + unsigned long CPOL : 1; + unsigned long : 5; + unsigned long SYNDIS : 1; + unsigned long CHR : 2; + unsigned long : 2; + unsigned long DDIR : 1; + unsigned long DINV : 1; + unsigned long STOP : 1; + unsigned long RXDESEL : 1; + unsigned long MOD : 3; + unsigned long MP : 1; + unsigned long FM : 1; + unsigned long DEEN : 1; + unsigned long : 2; + unsigned long CKE : 2; + unsigned long : 2; + unsigned long GM : 1; + unsigned long BLK : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long BLK : 1; + unsigned long GM : 1; + unsigned long : 2; + unsigned long CKE : 2; + unsigned long : 2; + unsigned long DEEN : 1; + unsigned long FM : 1; + unsigned long MP : 1; + unsigned long MOD : 3; + unsigned long RXDESEL : 1; + unsigned long STOP : 1; + unsigned long DINV : 1; + unsigned long DDIR : 1; + unsigned long : 2; + unsigned long CHR : 2; + unsigned long SYNDIS : 1; + unsigned long : 5; + unsigned long CPOL : 1; + unsigned long CPHA : 1; +#endif + } BIT; + } SCR3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMPD : 9; + unsigned long : 7; + unsigned long RTADJ : 1; + unsigned long TTADJ : 1; + unsigned long : 6; + unsigned long RTMG : 4; + unsigned long TTMG : 4; +#else + unsigned long TTMG : 4; + unsigned long RTMG : 4; + unsigned long : 6; + unsigned long TTADJ : 1; + unsigned long RTADJ : 1; + unsigned long : 7; + unsigned long CMPD : 9; +#endif + } BIT; + } SCR4; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HBSE : 1; + unsigned char : 1; + unsigned char AOE : 1; + unsigned char LPS : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char LPS : 1; + unsigned char AOE : 1; + unsigned char : 1; + unsigned char HBSE : 1; +#endif + } BIT; + } HBSCR; + char wk1[1]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IICDL : 5; + unsigned long : 3; + unsigned long IICINTM : 1; + unsigned long IICCSC : 1; + unsigned long : 3; + unsigned long IICACKT : 1; + unsigned long : 2; + unsigned long IICSTAREQ : 1; + unsigned long IICRSTAREQ : 1; + unsigned long IICSTPREQ : 1; + unsigned long : 1; + unsigned long IICSDAS : 2; + unsigned long IICSCLS : 2; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long IICSCLS : 2; + unsigned long IICSDAS : 2; + unsigned long : 1; + unsigned long IICSTPREQ : 1; + unsigned long IICRSTAREQ : 1; + unsigned long IICSTAREQ : 1; + unsigned long : 2; + unsigned long IICACKT : 1; + unsigned long : 3; + unsigned long IICCSC : 1; + unsigned long IICINTM : 1; + unsigned long : 3; + unsigned long IICDL : 5; +#endif + } BIT; + } SIMR; + char wk2[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DECS : 1; + unsigned long ENCS : 1; + unsigned long SADJE : 1; + unsigned long : 1; + unsigned long SBPTN : 1; + unsigned long SYNCE : 1; + unsigned long SBLEN : 1; + unsigned long : 1; + unsigned long TPLEN : 4; + unsigned long TPPAT : 2; + unsigned long : 2; + unsigned long RPLEN : 4; + unsigned long RPPAT : 2; + unsigned long : 2; + unsigned long PFERIE : 1; + unsigned long SYERIE : 1; + unsigned long SBERIE : 1; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long SBERIE : 1; + unsigned long SYERIE : 1; + unsigned long PFERIE : 1; + unsigned long : 2; + unsigned long RPPAT : 2; + unsigned long RPLEN : 4; + unsigned long : 2; + unsigned long TPPAT : 2; + unsigned long TPLEN : 4; + unsigned long : 1; + unsigned long SBLEN : 1; + unsigned long SYNCE : 1; + unsigned long SBPTN : 1; + unsigned long : 1; + unsigned long SADJE : 1; + unsigned long ENCS : 1; + unsigned long DECS : 1; +#endif + } BIT; + } MMCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DELVL : 1; + unsigned long : 7; + unsigned long DESU : 5; + unsigned long : 3; + unsigned long DEHLD : 5; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long DEHLD : 5; + unsigned long : 3; + unsigned long DESU : 5; + unsigned long : 7; + unsigned long DELVL : 1; +#endif + } BIT; + } DECR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TCSS : 2; + unsigned long : 6; + unsigned long BFE : 1; + unsigned long CF0RE : 1; + unsigned long CF1DS : 2; + unsigned long PIBE : 1; + unsigned long PIBS : 3; + unsigned long BFOIE : 1; + unsigned long BCDIE : 1; + unsigned long : 2; + unsigned long BFDIE : 1; + unsigned long COFIE : 1; + unsigned long AEDIE : 1; + unsigned long : 1; + unsigned long BCCS : 2; + unsigned long : 6; +#else + unsigned long : 6; + unsigned long BCCS : 2; + unsigned long : 1; + unsigned long AEDIE : 1; + unsigned long COFIE : 1; + unsigned long BFDIE : 1; + unsigned long : 2; + unsigned long BCDIE : 1; + unsigned long BFOIE : 1; + unsigned long PIBS : 3; + unsigned long PIBE : 1; + unsigned long CF1DS : 2; + unsigned long CF0RE : 1; + unsigned long BFE : 1; + unsigned long : 6; + unsigned long TCSS : 2; +#endif + } BIT; + } XCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TCST : 1; + unsigned long : 3; + unsigned long SDST : 1; + unsigned long BRME : 1; + unsigned long : 2; + unsigned long PCF1D : 8; + unsigned long SCF1D : 8; + unsigned long CF1CE : 8; +#else + unsigned long CF1CE : 8; + unsigned long SCF1D : 8; + unsigned long PCF1D : 8; + unsigned long : 2; + unsigned long BRME : 1; + unsigned long SDST : 1; + unsigned long : 3; + unsigned long TCST : 1; +#endif + } BIT; + } XCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CF0D : 8; + unsigned long CF0CE : 8; + unsigned long BFLW : 16; +#else + unsigned long BFLW : 16; + unsigned long CF0CE : 8; + unsigned long CF0D : 8; +#endif + } BIT; + } XCR2; + char wk3[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long ERS : 1; + unsigned long : 10; + unsigned long RXDMON : 1; + unsigned long DCMF : 1; + unsigned long DPER : 1; + unsigned long DFER : 1; + unsigned long : 5; + unsigned long ORER : 1; + unsigned long : 1; + unsigned long MFF : 1; + unsigned long APER : 1; + unsigned long AFER : 1; + unsigned long TDRE : 1; + unsigned long TEND : 1; + unsigned long RDRF : 1; +#else + unsigned long RDRF : 1; + unsigned long TEND : 1; + unsigned long TDRE : 1; + unsigned long AFER : 1; + unsigned long APER : 1; + unsigned long MFF : 1; + unsigned long : 1; + unsigned long ORER : 1; + unsigned long : 5; + unsigned long DFER : 1; + unsigned long DPER : 1; + unsigned long DCMF : 1; + unsigned long RXDMON : 1; + unsigned long : 10; + unsigned long ERS : 1; + unsigned long : 4; +#endif + } BIT; + } SSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IICACKR : 1; + unsigned long : 2; + unsigned long IICSTIF : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long IICSTIF : 1; + unsigned long : 2; + unsigned long IICACKR : 1; +#endif + } BIT; + } SISR; + char wk4[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PFER : 1; + unsigned long SYER : 1; + unsigned long SBER : 1; + unsigned long : 1; + unsigned long MCER : 1; + unsigned long : 1; + unsigned long RSYNC : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long RSYNC : 1; + unsigned long : 1; + unsigned long MCER : 1; + unsigned long : 1; + unsigned long SBER : 1; + unsigned long SYER : 1; + unsigned long PFER : 1; +#endif + } BIT; + } MMSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SFSF : 1; + unsigned long RXDSF : 1; + unsigned long : 6; + unsigned long BFOF : 1; + unsigned long BCDF : 1; + unsigned long BFDF : 1; + unsigned long CF0MF : 1; + unsigned long CF1MF : 1; + unsigned long PIBDF : 1; + unsigned long COF : 1; + unsigned long AEDF : 1; + unsigned long CF0RD : 8; + unsigned long CF1RD : 8; +#else + unsigned long CF1RD : 8; + unsigned long CF0RD : 8; + unsigned long AEDF : 1; + unsigned long COF : 1; + unsigned long PIBDF : 1; + unsigned long CF1MF : 1; + unsigned long CF0MF : 1; + unsigned long BFDF : 1; + unsigned long BCDF : 1; + unsigned long BFOF : 1; + unsigned long : 6; + unsigned long RXDSF : 1; + unsigned long SFSF : 1; +#endif + } BIT; + } XSR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CCV : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long CCV : 16; +#endif + } BIT; + } XSR1; + char wk5[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long ERSC : 1; + unsigned long : 11; + unsigned long DCMFC : 1; + unsigned long DPERC : 1; + unsigned long DFERC : 1; + unsigned long : 5; + unsigned long ORERC : 1; + unsigned long : 1; + unsigned long MFFC : 1; + unsigned long APERC : 1; + unsigned long AFERC : 1; + unsigned long TDREC : 1; + unsigned long : 1; + unsigned long RDRFC : 1; +#else + unsigned long RDRFC : 1; + unsigned long : 1; + unsigned long TDREC : 1; + unsigned long AFERC : 1; + unsigned long APERC : 1; + unsigned long MFFC : 1; + unsigned long : 1; + unsigned long ORERC : 1; + unsigned long : 5; + unsigned long DFERC : 1; + unsigned long DPERC : 1; + unsigned long DCMFC : 1; + unsigned long : 11; + unsigned long ERSC : 1; + unsigned long : 4; +#endif + } BIT; + } SSCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long IICSTIFC : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long IICSTIFC : 1; + unsigned long : 3; +#endif + } BIT; + } SISCR; + char wk6[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PFERC : 1; + unsigned long SYERC : 1; + unsigned long SBERC : 1; + unsigned long : 1; + unsigned long MCERC : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long MCERC : 1; + unsigned long : 1; + unsigned long SBERC : 1; + unsigned long SYERC : 1; + unsigned long PFERC : 1; +#endif + } BIT; + } MMSCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long BFOC : 1; + unsigned long BCDCL : 1; + unsigned long BFDCL : 1; + unsigned long CF0MCL : 1; + unsigned long CF1MCL : 1; + unsigned long PIBDCL : 1; + unsigned long COFC : 1; + unsigned long AEDCL : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long AEDCL : 1; + unsigned long COFC : 1; + unsigned long PIBDCL : 1; + unsigned long CF1MCL : 1; + unsigned long CF0MCL : 1; + unsigned long BFDCL : 1; + unsigned long BCDCL : 1; + unsigned long BFOC : 1; + unsigned long : 8; +#endif + } BIT; + } XSCR; +} st_rsci9_t; + +typedef struct st_rsci11 { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RDAT : 9; + unsigned long MPB : 1; + unsigned long DR : 1; + unsigned long PER : 1; + unsigned long FER : 1; + unsigned long : 11; + unsigned long ORER : 1; + unsigned long : 2; + unsigned long APER : 1; + unsigned long AFER : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long AFER : 1; + unsigned long APER : 1; + unsigned long : 2; + unsigned long ORER : 1; + unsigned long : 11; + unsigned long FER : 1; + unsigned long PER : 1; + unsigned long DR : 1; + unsigned long MPB : 1; + unsigned long RDAT : 9; +#endif + } BIT; + } RDR; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TDAT : 9; + unsigned long MPBT : 1; + unsigned long : 2; + unsigned long SYNC : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long SYNC : 1; + unsigned long : 2; + unsigned long MPBT : 1; + unsigned long TDAT : 9; +#endif + } BIT; + } TDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RE : 1; + unsigned long : 3; + unsigned long TE : 1; + unsigned long : 3; + unsigned long MPIE : 1; + unsigned long DCME : 1; + unsigned long IDSEL : 1; + unsigned long : 5; + unsigned long RIE : 1; + unsigned long : 3; + unsigned long TIE : 1; + unsigned long TEIE : 1; + unsigned long : 2; + unsigned long SSE : 1; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long SSE : 1; + unsigned long : 2; + unsigned long TEIE : 1; + unsigned long TIE : 1; + unsigned long : 3; + unsigned long RIE : 1; + unsigned long : 5; + unsigned long IDSEL : 1; + unsigned long DCME : 1; + unsigned long MPIE : 1; + unsigned long : 3; + unsigned long TE : 1; + unsigned long : 3; + unsigned long RE : 1; +#endif + } BIT; + } SCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CTSE : 1; + unsigned long CRSEP : 1; + unsigned long : 2; + unsigned long SPB2DT : 1; + unsigned long SPB2IO : 1; + unsigned long : 2; + unsigned long PE : 1; + unsigned long PM : 1; + unsigned long : 2; + unsigned long TINV : 1; + unsigned long RINV : 1; + unsigned long : 2; + unsigned long LOOP : 1; + unsigned long : 3; + unsigned long HDSEL : 1; + unsigned long : 3; + unsigned long NFCS : 3; + unsigned long : 1; + unsigned long NFEN : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long NFEN : 1; + unsigned long : 1; + unsigned long NFCS : 3; + unsigned long : 3; + unsigned long HDSEL : 1; + unsigned long : 3; + unsigned long LOOP : 1; + unsigned long : 2; + unsigned long RINV : 1; + unsigned long TINV : 1; + unsigned long : 2; + unsigned long PM : 1; + unsigned long PE : 1; + unsigned long : 2; + unsigned long SPB2IO : 1; + unsigned long SPB2DT : 1; + unsigned long : 2; + unsigned long CRSEP : 1; + unsigned long CTSE : 1; +#endif + } BIT; + } SCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BCP : 3; + unsigned long : 1; + unsigned long BGDM : 1; + unsigned long ABCS : 1; + unsigned long ABCSE : 1; + unsigned long : 1; + unsigned long BRR : 8; + unsigned long BRME : 1; + unsigned long : 3; + unsigned long CKS : 2; + unsigned long : 2; + unsigned long MDDR : 8; +#else + unsigned long MDDR : 8; + unsigned long : 2; + unsigned long CKS : 2; + unsigned long : 3; + unsigned long BRME : 1; + unsigned long BRR : 8; + unsigned long : 1; + unsigned long ABCSE : 1; + unsigned long ABCS : 1; + unsigned long BGDM : 1; + unsigned long : 1; + unsigned long BCP : 3; +#endif + } BIT; + } SCR2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CPHA : 1; + unsigned long CPOL : 1; + unsigned long : 5; + unsigned long SYNDIS : 1; + unsigned long CHR : 2; + unsigned long : 2; + unsigned long DDIR : 1; + unsigned long DINV : 1; + unsigned long STOP : 1; + unsigned long RXDESEL : 1; + unsigned long MOD : 3; + unsigned long MP : 1; + unsigned long FM : 1; + unsigned long DEEN : 1; + unsigned long : 2; + unsigned long CKE : 2; + unsigned long : 2; + unsigned long GM : 1; + unsigned long BLK : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long BLK : 1; + unsigned long GM : 1; + unsigned long : 2; + unsigned long CKE : 2; + unsigned long : 2; + unsigned long DEEN : 1; + unsigned long FM : 1; + unsigned long MP : 1; + unsigned long MOD : 3; + unsigned long RXDESEL : 1; + unsigned long STOP : 1; + unsigned long DINV : 1; + unsigned long DDIR : 1; + unsigned long : 2; + unsigned long CHR : 2; + unsigned long SYNDIS : 1; + unsigned long : 5; + unsigned long CPOL : 1; + unsigned long CPHA : 1; +#endif + } BIT; + } SCR3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMPD : 9; + unsigned long : 7; + unsigned long RTADJ : 1; + unsigned long TTADJ : 1; + unsigned long : 6; + unsigned long RTMG : 4; + unsigned long TTMG : 4; +#else + unsigned long TTMG : 4; + unsigned long RTMG : 4; + unsigned long : 6; + unsigned long TTADJ : 1; + unsigned long RTADJ : 1; + unsigned long : 7; + unsigned long CMPD : 9; +#endif + } BIT; + } SCR4; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HBSE : 1; + unsigned char : 1; + unsigned char AOE : 1; + unsigned char LPS : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char LPS : 1; + unsigned char AOE : 1; + unsigned char : 1; + unsigned char HBSE : 1; +#endif + } BIT; + } HBSCR; + char wk1[1]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IICDL : 5; + unsigned long : 3; + unsigned long IICINTM : 1; + unsigned long IICCSC : 1; + unsigned long : 3; + unsigned long IICACKT : 1; + unsigned long : 2; + unsigned long IICSTAREQ : 1; + unsigned long IICRSTAREQ : 1; + unsigned long IICSTPREQ : 1; + unsigned long : 1; + unsigned long IICSDAS : 2; + unsigned long IICSCLS : 2; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long IICSCLS : 2; + unsigned long IICSDAS : 2; + unsigned long : 1; + unsigned long IICSTPREQ : 1; + unsigned long IICRSTAREQ : 1; + unsigned long IICSTAREQ : 1; + unsigned long : 2; + unsigned long IICACKT : 1; + unsigned long : 3; + unsigned long IICCSC : 1; + unsigned long IICINTM : 1; + unsigned long : 3; + unsigned long IICDL : 5; +#endif + } BIT; + } SIMR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DRES : 1; + unsigned long : 7; + unsigned long TTRG : 5; + unsigned long : 2; + unsigned long TFRST : 1; + unsigned long RTRG : 5; + unsigned long : 2; + unsigned long RFRST : 1; + unsigned long RSTRG : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long RSTRG : 5; + unsigned long RFRST : 1; + unsigned long : 2; + unsigned long RTRG : 5; + unsigned long TFRST : 1; + unsigned long : 2; + unsigned long TTRG : 5; + unsigned long : 7; + unsigned long DRES : 1; +#endif + } BIT; + } FCR; + char wk2[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DECS : 1; + unsigned long ENCS : 1; + unsigned long SADJE : 1; + unsigned long : 1; + unsigned long SBPTN : 1; + unsigned long SYNCE : 1; + unsigned long SBLEN : 1; + unsigned long : 1; + unsigned long TPLEN : 4; + unsigned long TPPAT : 2; + unsigned long : 2; + unsigned long RPLEN : 4; + unsigned long RPPAT : 2; + unsigned long : 2; + unsigned long PFERIE : 1; + unsigned long SYERIE : 1; + unsigned long SBERIE : 1; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long SBERIE : 1; + unsigned long SYERIE : 1; + unsigned long PFERIE : 1; + unsigned long : 2; + unsigned long RPPAT : 2; + unsigned long RPLEN : 4; + unsigned long : 2; + unsigned long TPPAT : 2; + unsigned long TPLEN : 4; + unsigned long : 1; + unsigned long SBLEN : 1; + unsigned long SYNCE : 1; + unsigned long SBPTN : 1; + unsigned long : 1; + unsigned long SADJE : 1; + unsigned long ENCS : 1; + unsigned long DECS : 1; +#endif + } BIT; + } MMCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DELVL : 1; + unsigned long : 7; + unsigned long DESU : 5; + unsigned long : 3; + unsigned long DEHLD : 5; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long DEHLD : 5; + unsigned long : 3; + unsigned long DESU : 5; + unsigned long : 7; + unsigned long DELVL : 1; +#endif + } BIT; + } DECR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TCSS : 2; + unsigned long : 6; + unsigned long BFE : 1; + unsigned long CF0RE : 1; + unsigned long CF1DS : 2; + unsigned long PIBE : 1; + unsigned long PIBS : 3; + unsigned long BFOIE : 1; + unsigned long BCDIE : 1; + unsigned long : 2; + unsigned long BFDIE : 1; + unsigned long COFIE : 1; + unsigned long AEDIE : 1; + unsigned long : 1; + unsigned long BCCS : 2; + unsigned long : 6; +#else + unsigned long : 6; + unsigned long BCCS : 2; + unsigned long : 1; + unsigned long AEDIE : 1; + unsigned long COFIE : 1; + unsigned long BFDIE : 1; + unsigned long : 2; + unsigned long BCDIE : 1; + unsigned long BFOIE : 1; + unsigned long PIBS : 3; + unsigned long PIBE : 1; + unsigned long CF1DS : 2; + unsigned long CF0RE : 1; + unsigned long BFE : 1; + unsigned long : 6; + unsigned long TCSS : 2; +#endif + } BIT; + } XCR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TCST : 1; + unsigned long : 3; + unsigned long SDST : 1; + unsigned long BRME : 1; + unsigned long : 2; + unsigned long PCF1D : 8; + unsigned long SCF1D : 8; + unsigned long CF1CE : 8; +#else + unsigned long CF1CE : 8; + unsigned long SCF1D : 8; + unsigned long PCF1D : 8; + unsigned long : 2; + unsigned long BRME : 1; + unsigned long SDST : 1; + unsigned long : 3; + unsigned long TCST : 1; +#endif + } BIT; + } XCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CF0D : 8; + unsigned long CF0CE : 8; + unsigned long BFLW : 16; +#else + unsigned long BFLW : 16; + unsigned long CF0CE : 8; + unsigned long CF0D : 8; +#endif + } BIT; + } XCR2; + char wk3[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long ERS : 1; + unsigned long : 10; + unsigned long RXDMON : 1; + unsigned long DCMF : 1; + unsigned long DPER : 1; + unsigned long DFER : 1; + unsigned long : 5; + unsigned long ORER : 1; + unsigned long : 1; + unsigned long MFF : 1; + unsigned long APER : 1; + unsigned long AFER : 1; + unsigned long TDRE : 1; + unsigned long TEND : 1; + unsigned long RDRF : 1; +#else + unsigned long RDRF : 1; + unsigned long TEND : 1; + unsigned long TDRE : 1; + unsigned long AFER : 1; + unsigned long APER : 1; + unsigned long MFF : 1; + unsigned long : 1; + unsigned long ORER : 1; + unsigned long : 5; + unsigned long DFER : 1; + unsigned long DPER : 1; + unsigned long DCMF : 1; + unsigned long RXDMON : 1; + unsigned long : 10; + unsigned long ERS : 1; + unsigned long : 4; +#endif + } BIT; + } SSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IICACKR : 1; + unsigned long : 2; + unsigned long IICSTIF : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long IICSTIF : 1; + unsigned long : 2; + unsigned long IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DR : 1; + unsigned long : 7; + unsigned long R : 6; + unsigned long : 2; + unsigned long PEC : 6; + unsigned long : 2; + unsigned long FEC : 6; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long FEC : 6; + unsigned long : 2; + unsigned long PEC : 6; + unsigned long : 2; + unsigned long R : 6; + unsigned long : 7; + unsigned long DR : 1; +#endif + } BIT; + } RFSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long T : 6; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long T : 6; +#endif + } BIT; + } TFSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PFER : 1; + unsigned long SYER : 1; + unsigned long SBER : 1; + unsigned long : 1; + unsigned long MCER : 1; + unsigned long : 1; + unsigned long RSYNC : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long RSYNC : 1; + unsigned long : 1; + unsigned long MCER : 1; + unsigned long : 1; + unsigned long SBER : 1; + unsigned long SYER : 1; + unsigned long PFER : 1; +#endif + } BIT; + } MMSR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SFSF : 1; + unsigned long RXDSF : 1; + unsigned long : 6; + unsigned long BFOF : 1; + unsigned long BCDF : 1; + unsigned long BFDF : 1; + unsigned long CF0MF : 1; + unsigned long CF1MF : 1; + unsigned long PIBDF : 1; + unsigned long COF : 1; + unsigned long AEDF : 1; + unsigned long CF0RD : 8; + unsigned long CF1RD : 8; +#else + unsigned long CF1RD : 8; + unsigned long CF0RD : 8; + unsigned long AEDF : 1; + unsigned long COF : 1; + unsigned long PIBDF : 1; + unsigned long CF1MF : 1; + unsigned long CF0MF : 1; + unsigned long BFDF : 1; + unsigned long BCDF : 1; + unsigned long BFOF : 1; + unsigned long : 6; + unsigned long RXDSF : 1; + unsigned long SFSF : 1; +#endif + } BIT; + } XSR0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CCV : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long CCV : 16; +#endif + } BIT; + } XSR1; + char wk4[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long ERSC : 1; + unsigned long : 11; + unsigned long DCMFC : 1; + unsigned long DPERC : 1; + unsigned long DFERC : 1; + unsigned long : 5; + unsigned long ORERC : 1; + unsigned long : 1; + unsigned long MFFC : 1; + unsigned long APERC : 1; + unsigned long AFERC : 1; + unsigned long TDREC : 1; + unsigned long : 1; + unsigned long RDRFC : 1; +#else + unsigned long RDRFC : 1; + unsigned long : 1; + unsigned long TDREC : 1; + unsigned long AFERC : 1; + unsigned long APERC : 1; + unsigned long MFFC : 1; + unsigned long : 1; + unsigned long ORERC : 1; + unsigned long : 5; + unsigned long DFERC : 1; + unsigned long DPERC : 1; + unsigned long DCMFC : 1; + unsigned long : 11; + unsigned long ERSC : 1; + unsigned long : 4; +#endif + } BIT; + } SSCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long IICSTIFC : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long IICSTIFC : 1; + unsigned long : 3; +#endif + } BIT; + } SISCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DRC : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long DRC : 1; +#endif + } BIT; + } RFSCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PFERC : 1; + unsigned long SYERC : 1; + unsigned long SBERC : 1; + unsigned long : 1; + unsigned long MCERC : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long MCERC : 1; + unsigned long : 1; + unsigned long SBERC : 1; + unsigned long SYERC : 1; + unsigned long PFERC : 1; +#endif + } BIT; + } MMSCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long BFOC : 1; + unsigned long BCDCL : 1; + unsigned long BFDCL : 1; + unsigned long CF0MCL : 1; + unsigned long CF1MCL : 1; + unsigned long PIBDCL : 1; + unsigned long COFC : 1; + unsigned long AEDCL : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long AEDCL : 1; + unsigned long COFC : 1; + unsigned long PIBDCL : 1; + unsigned long CF1MCL : 1; + unsigned long CF0MCL : 1; + unsigned long BFDCL : 1; + unsigned long BCDCL : 1; + unsigned long BFOC : 1; + unsigned long : 8; +#endif + } BIT; + } XSCR; +} st_rsci11_t; + +typedef struct st_rspi { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPMS : 1; + unsigned char TXMD : 1; + unsigned char MODFEN : 1; + unsigned char MSTR : 1; + unsigned char SPEIE : 1; + unsigned char SPTIE : 1; + unsigned char SPE : 1; + unsigned char SPRIE : 1; +#else + unsigned char SPRIE : 1; + unsigned char SPE : 1; + unsigned char SPTIE : 1; + unsigned char SPEIE : 1; + unsigned char MSTR : 1; + unsigned char MODFEN : 1; + unsigned char TXMD : 1; + unsigned char SPMS : 1; +#endif + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSL0P : 1; + unsigned char SSL1P : 1; + unsigned char SSL2P : 1; + unsigned char SSL3P : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char SSL3P : 1; + unsigned char SSL2P : 1; + unsigned char SSL1P : 1; + unsigned char SSL0P : 1; +#endif + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char SPLP2 : 1; + unsigned char : 2; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 2; + unsigned char SPLP2 : 1; + unsigned char SPLP : 1; +#endif + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OVRF : 1; + unsigned char IDLNF : 1; + unsigned char MODF : 1; + unsigned char PERF : 1; + unsigned char UDRF : 1; + unsigned char SPTEF : 1; + unsigned char SPCF : 1; + unsigned char SPRF : 1; +#else + unsigned char SPRF : 1; + unsigned char SPCF : 1; + unsigned char SPTEF : 1; + unsigned char UDRF : 1; + unsigned char PERF : 1; + unsigned char MODF : 1; + unsigned char IDLNF : 1; + unsigned char OVRF : 1; +#endif + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SPDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSLN : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPSLN : 3; +#endif + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPCP : 3; + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; + unsigned char SPCP : 3; +#endif + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPFC : 2; + unsigned char : 2; + unsigned char SPRDTD : 1; + unsigned char SPLW : 1; + unsigned char SPBYT : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPBYT : 1; + unsigned char SPLW : 1; + unsigned char SPRDTD : 1; + unsigned char : 2; + unsigned char SPFC : 2; +#endif + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPPE : 1; + unsigned char SPOE : 1; + unsigned char SPIIE : 1; + unsigned char PTE : 1; + unsigned char SCKASE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SCKASE : 1; + unsigned char PTE : 1; + unsigned char SPIIE : 1; + unsigned char SPOE : 1; + unsigned char SPPE : 1; +#endif + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD7; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BYSW : 1; + unsigned char DINV : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char DINV : 1; + unsigned char BYSW : 1; +#endif + } BIT; + } SPDCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RXMD : 1; + unsigned char SCKDDIS : 1; + unsigned char : 2; + unsigned char SPCIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SPCIE : 1; + unsigned char : 2; + unsigned char SCKDDIS : 1; + unsigned char RXMD : 1; +#endif + } BIT; + } SPCR3; +} st_rspi_t; + +typedef struct st_rspia { + union { + unsigned long LONG; + struct { + unsigned short L; + } WORD; + struct { + unsigned char LL; + } BYTE; + } SPDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif + } BIT; + } SPND; + char wk0[1]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SPE : 1; + unsigned long : 6; + unsigned long MRCKS : 1; + unsigned long SPPE : 1; + unsigned long SPOE : 1; + unsigned long : 1; + unsigned long PTE : 1; + unsigned long SCKASE : 1; + unsigned long SCKDDIS : 1; + unsigned long MODFEN : 1; + unsigned long : 1; + unsigned long SPEIE : 1; + unsigned long SPRIE : 1; + unsigned long SPIIE : 1; + unsigned long RDRIS : 1; + unsigned long SPTIE : 1; + unsigned long SPCIE : 1; + unsigned long : 2; + unsigned long SPMS : 1; + unsigned long FRFS : 1; + unsigned long : 2; + unsigned long CMMD : 2; + unsigned long MSTR : 1; + unsigned long SYNDIS : 1; +#else + unsigned long SYNDIS : 1; + unsigned long MSTR : 1; + unsigned long CMMD : 2; + unsigned long : 2; + unsigned long FRFS : 1; + unsigned long SPMS : 1; + unsigned long : 2; + unsigned long SPCIE : 1; + unsigned long SPTIE : 1; + unsigned long RDRIS : 1; + unsigned long SPIIE : 1; + unsigned long SPRIE : 1; + unsigned long SPEIE : 1; + unsigned long : 1; + unsigned long MODFEN : 1; + unsigned long SCKDDIS : 1; + unsigned long SCKASE : 1; + unsigned long PTE : 1; + unsigned long : 1; + unsigned long SPOE : 1; + unsigned long SPPE : 1; + unsigned long MRCKS : 1; + unsigned long : 6; + unsigned long SPE : 1; +#endif + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RFC : 5; + unsigned char : 1; + unsigned char TERM : 1; + unsigned char START : 1; +#else + unsigned char START : 1; + unsigned char TERM : 1; + unsigned char : 1; + unsigned char RFC : 5; +#endif + } BIT; + } SPRMCR; + unsigned char SPDRCSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char SPLP2 : 1; + unsigned char : 2; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 2; + unsigned char SPLP2 : 1; + unsigned char SPLP : 1; +#endif + } BIT; + } SPPCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSL0P : 1; + unsigned char SSL1P : 1; + unsigned char SSL2P : 1; + unsigned char SSL3P : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char SSL3P : 1; + unsigned char SSL2P : 1; + unsigned char SSL1P : 1; + unsigned char SSL0P : 1; +#endif + } BIT; + } SSLP; + unsigned char SPBR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSLN : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPSLN : 3; +#endif + } BIT; + } SPSCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CPHA : 1; + unsigned long CPOL : 1; + unsigned long BRDV : 2; + unsigned long : 3; + unsigned long SSLKP : 1; + unsigned long : 4; + unsigned long LSBF : 1; + unsigned long SPNDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SCKDEN : 1; + unsigned long SPB : 5; + unsigned long : 3; + unsigned long SSLA : 3; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long SSLA : 3; + unsigned long : 3; + unsigned long SPB : 5; + unsigned long SCKDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SPNDEN : 1; + unsigned long LSBF : 1; + unsigned long : 4; + unsigned long SSLKP : 1; + unsigned long : 3; + unsigned long BRDV : 2; + unsigned long CPOL : 1; + unsigned long CPHA : 1; +#endif + } BIT; + } SPCMD0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CPHA : 1; + unsigned long CPOL : 1; + unsigned long BRDV : 2; + unsigned long : 3; + unsigned long SSLKP : 1; + unsigned long : 4; + unsigned long LSBF : 1; + unsigned long SPNDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SCKDEN : 1; + unsigned long SPB : 5; + unsigned long : 3; + unsigned long SSLA : 3; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long SSLA : 3; + unsigned long : 3; + unsigned long SPB : 5; + unsigned long SCKDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SPNDEN : 1; + unsigned long LSBF : 1; + unsigned long : 4; + unsigned long SSLKP : 1; + unsigned long : 3; + unsigned long BRDV : 2; + unsigned long CPOL : 1; + unsigned long CPHA : 1; +#endif + } BIT; + } SPCMD1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CPHA : 1; + unsigned long CPOL : 1; + unsigned long BRDV : 2; + unsigned long : 3; + unsigned long SSLKP : 1; + unsigned long : 4; + unsigned long LSBF : 1; + unsigned long SPNDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SCKDEN : 1; + unsigned long SPB : 5; + unsigned long : 3; + unsigned long SSLA : 3; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long SSLA : 3; + unsigned long : 3; + unsigned long SPB : 5; + unsigned long SCKDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SPNDEN : 1; + unsigned long LSBF : 1; + unsigned long : 4; + unsigned long SSLKP : 1; + unsigned long : 3; + unsigned long BRDV : 2; + unsigned long CPOL : 1; + unsigned long CPHA : 1; +#endif + } BIT; + } SPCMD2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CPHA : 1; + unsigned long CPOL : 1; + unsigned long BRDV : 2; + unsigned long : 3; + unsigned long SSLKP : 1; + unsigned long : 4; + unsigned long LSBF : 1; + unsigned long SPNDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SCKDEN : 1; + unsigned long SPB : 5; + unsigned long : 3; + unsigned long SSLA : 3; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long SSLA : 3; + unsigned long : 3; + unsigned long SPB : 5; + unsigned long SCKDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SPNDEN : 1; + unsigned long LSBF : 1; + unsigned long : 4; + unsigned long SSLKP : 1; + unsigned long : 3; + unsigned long BRDV : 2; + unsigned long CPOL : 1; + unsigned long CPHA : 1; +#endif + } BIT; + } SPCMD3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CPHA : 1; + unsigned long CPOL : 1; + unsigned long BRDV : 2; + unsigned long : 3; + unsigned long SSLKP : 1; + unsigned long : 4; + unsigned long LSBF : 1; + unsigned long SPNDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SCKDEN : 1; + unsigned long SPB : 5; + unsigned long : 3; + unsigned long SSLA : 3; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long SSLA : 3; + unsigned long : 3; + unsigned long SPB : 5; + unsigned long SCKDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SPNDEN : 1; + unsigned long LSBF : 1; + unsigned long : 4; + unsigned long SSLKP : 1; + unsigned long : 3; + unsigned long BRDV : 2; + unsigned long CPOL : 1; + unsigned long CPHA : 1; +#endif + } BIT; + } SPCMD4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CPHA : 1; + unsigned long CPOL : 1; + unsigned long BRDV : 2; + unsigned long : 3; + unsigned long SSLKP : 1; + unsigned long : 4; + unsigned long LSBF : 1; + unsigned long SPNDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SCKDEN : 1; + unsigned long SPB : 5; + unsigned long : 3; + unsigned long SSLA : 3; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long SSLA : 3; + unsigned long : 3; + unsigned long SPB : 5; + unsigned long SCKDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SPNDEN : 1; + unsigned long LSBF : 1; + unsigned long : 4; + unsigned long SSLKP : 1; + unsigned long : 3; + unsigned long BRDV : 2; + unsigned long CPOL : 1; + unsigned long CPHA : 1; +#endif + } BIT; + } SPCMD5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CPHA : 1; + unsigned long CPOL : 1; + unsigned long BRDV : 2; + unsigned long : 3; + unsigned long SSLKP : 1; + unsigned long : 4; + unsigned long LSBF : 1; + unsigned long SPNDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SCKDEN : 1; + unsigned long SPB : 5; + unsigned long : 3; + unsigned long SSLA : 3; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long SSLA : 3; + unsigned long : 3; + unsigned long SPB : 5; + unsigned long SCKDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SPNDEN : 1; + unsigned long LSBF : 1; + unsigned long : 4; + unsigned long SSLKP : 1; + unsigned long : 3; + unsigned long BRDV : 2; + unsigned long CPOL : 1; + unsigned long CPHA : 1; +#endif + } BIT; + } SPCMD6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CPHA : 1; + unsigned long CPOL : 1; + unsigned long BRDV : 2; + unsigned long : 3; + unsigned long SSLKP : 1; + unsigned long : 4; + unsigned long LSBF : 1; + unsigned long SPNDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SCKDEN : 1; + unsigned long SPB : 5; + unsigned long : 3; + unsigned long SSLA : 3; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long SSLA : 3; + unsigned long : 3; + unsigned long SPB : 5; + unsigned long SCKDEN : 1; + unsigned long SLNDEN : 1; + unsigned long SPNDEN : 1; + unsigned long LSBF : 1; + unsigned long : 4; + unsigned long SSLKP : 1; + unsigned long : 3; + unsigned long BRDV : 2; + unsigned long CPOL : 1; + unsigned long CPHA : 1; +#endif + } BIT; + } SPCMD7; + char wk3[12]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BYSW : 1; + unsigned short : 2; + unsigned short SPRDTD : 1; + unsigned short DINV : 1; + unsigned short : 3; + unsigned short SPFC : 2; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short SPFC : 2; + unsigned short : 3; + unsigned short DINV : 1; + unsigned short SPRDTD : 1; + unsigned short : 2; + unsigned short BYSW : 1; +#endif + } BIT; + } SPDCR; + char wk4[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RTRG : 2; + unsigned short : 6; + unsigned short TTRG : 2; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short TTRG : 2; + unsigned short : 6; + unsigned short RTRG : 2; +#endif + } BIT; + } SPFCR; + char wk5[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPCP : 3; + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; + unsigned char SPCP : 3; +#endif + } BIT; + } SPSSR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 7; + unsigned short RRDYF : 1; + unsigned short OVRF : 1; + unsigned short IDLNF : 1; + unsigned short MODF : 1; + unsigned short PERF : 1; + unsigned short UDRF : 1; + unsigned short SPTEF : 1; + unsigned short SPCF : 1; + unsigned short SPRF : 1; +#else + unsigned short SPRF : 1; + unsigned short SPCF : 1; + unsigned short SPTEF : 1; + unsigned short UDRF : 1; + unsigned short PERF : 1; + unsigned short MODF : 1; + unsigned short IDLNF : 1; + unsigned short OVRF : 1; + unsigned short RRDYF : 1; + unsigned short : 7; +#endif + } BIT; + } SPSR; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FREE : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char FREE : 3; +#endif + } BIT; + } SPTFSR; + char wk7[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FILL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char FILL : 3; +#endif + } BIT; + } SPRFSR; + char wk8[13]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 7; + unsigned short RRDYFC : 1; + unsigned short OVRFC : 1; + unsigned short : 1; + unsigned short MODFC : 1; + unsigned short PERFC : 1; + unsigned short UDRFC : 1; + unsigned short SPTEFC : 1; + unsigned short SPCFC : 1; + unsigned short SPRFC : 1; +#else + unsigned short SPRFC : 1; + unsigned short SPCFC : 1; + unsigned short SPTEFC : 1; + unsigned short UDRFC : 1; + unsigned short PERFC : 1; + unsigned short MODFC : 1; + unsigned short : 1; + unsigned short OVRFC : 1; + unsigned short RRDYFC : 1; + unsigned short : 7; +#endif + } BIT; + } SPSCLR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FCLR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char FCLR : 1; +#endif + } BIT; + } SPFCLR; +} st_rspia_t; + +typedef struct st_s12ad { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short : 2; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 2; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA000 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA006 : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short ANSA006 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA000 : 1; +#endif + } BIT; + } ADANSA0; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS000 : 1; + unsigned short ADS001 : 1; + unsigned short ADS002 : 1; + unsigned short ADS003 : 1; + unsigned short ADS004 : 1; + unsigned short ADS005 : 1; + unsigned short ADS006 : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short ADS006 : 1; + unsigned short ADS005 : 1; + unsigned short ADS004 : 1; + unsigned short ADS003 : 1; + unsigned short ADS002 : 1; + unsigned short ADS001 : 1; + unsigned short ADS000 : 1; +#endif + } BIT; + } ADADS0; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 3; + unsigned char : 4; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 4; + unsigned char ADC : 3; +#endif + } BIT; + } ADADC; + char wk3[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short ACE : 1; + unsigned short ASE : 1; + unsigned short : 1; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 1; + unsigned short ASE : 1; + unsigned short ACE : 1; + unsigned short : 5; +#endif + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 7; + unsigned short : 1; + unsigned short TRSA : 7; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short TRSA : 7; + unsigned short : 1; + unsigned short TRSB : 7; +#endif + } BIT; + } ADSTRGR; + char wk4[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB000 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB006 : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short ANSB006 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB000 : 1; +#endif + } BIT; + } ADANSB0; + char wk5[2]; + unsigned short ADDBLDR; + char wk6[4]; + union { + unsigned short WORD; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif + } RIGHT; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + char wk7[56]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SSTSH : 8; + unsigned short SHANS : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short SHANS : 3; + unsigned short SSTSH : 8; +#endif + } BIT; + } ADSHCR; + char wk8[18]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif + } BIT; + } ADDISCR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHMD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHMD : 1; +#endif + } BIT; + } ADSHMSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELCC : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char ELCC : 3; +#endif + } BIT; + } ADELCCR; + char wk10[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 12; + unsigned short LGRRS : 1; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short LGRRS : 1; + unsigned short : 12; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif + } BIT; + } ADGSPCR; + char wk11[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk12[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MONCOMB : 1; + unsigned char : 3; + unsigned char MONCMPA : 1; + unsigned char MONCMPB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MONCMPB : 1; + unsigned char MONCMPA : 1; + unsigned char : 3; + unsigned char MONCOMB : 1; +#endif + } BIT; + } ADWINMON; + char wk13[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPAB : 2; + unsigned short : 7; + unsigned short CMPBE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPAIE : 1; +#else + unsigned short CMPAIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPBIE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBE : 1; + unsigned short : 7; + unsigned short CMPAB : 2; +#endif + } BIT; + } ADCMPCR; + char wk14[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA000 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA006 : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA000 : 1; +#endif + } BIT; + } ADCMPANSR0; + char wk15[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA000 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA000 : 1; +#endif + } BIT; + } ADCMPLR0; + char wk16[2]; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA000 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA000 : 1; +#endif + } BIT; + } ADCMPSR0; + char wk17[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCHB : 6; + unsigned char : 1; + unsigned char CMPLB : 1; +#else + unsigned char CMPLB : 1; + unsigned char : 1; + unsigned char CMPCHB : 6; +#endif + } BIT; + } ADCMPBNSR; + char wk18[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTB : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CMPSTB : 1; +#endif + } BIT; + } ADCMPBSR; + char wk19[39]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSC000 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC003 : 1; + unsigned short ANSC004 : 1; + unsigned short ANSC005 : 1; + unsigned short ANSC006 : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short ANSC006 : 1; + unsigned short ANSC005 : 1; + unsigned short ANSC004 : 1; + unsigned short ANSC003 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC000 : 1; +#endif + } BIT; + } ADANSC0; + char wk20[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRSC : 6; + unsigned char GCADIE : 1; + unsigned char GRCE : 1; +#else + unsigned char GRCE : 1; + unsigned char GCADIE : 1; + unsigned char TRSC : 6; +#endif + } BIT; + } ADGCTRGR; + char wk21[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRSC6 : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TRSC6 : 1; +#endif + } BIT; + } ADGCTRGR2; + char wk22[3]; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + char wk23[185]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short P000CR : 4; + unsigned short P001CR : 4; + unsigned short P002CR : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short P002CR : 4; + unsigned short P001CR : 4; + unsigned short P000CR : 4; +#endif + } BIT; + } ADPGACR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short P000GAIN : 4; + unsigned short P001GAIN : 4; + unsigned short P002GAIN : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short P002GAIN : 4; + unsigned short P001GAIN : 4; + unsigned short P000GAIN : 4; +#endif + } BIT; + } ADPGAGS0; + char wk24[28]; + unsigned char ADSCS0; + unsigned char ADSCS1; + unsigned char ADSCS2; + unsigned char ADSCS3; + unsigned char ADSCS4; + unsigned char ADSCS5; + unsigned char ADSCS6; +} st_s12ad_t; + +typedef struct st_s12ad1 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short : 2; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 2; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA000 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA003 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short ANSA003 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA000 : 1; +#endif + } BIT; + } ADANSA0; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS000 : 1; + unsigned short ADS001 : 1; + unsigned short ADS002 : 1; + unsigned short ADS003 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short ADS003 : 1; + unsigned short ADS002 : 1; + unsigned short ADS001 : 1; + unsigned short ADS000 : 1; +#endif + } BIT; + } ADADS0; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 3; + unsigned char : 4; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 4; + unsigned char ADC : 3; +#endif + } BIT; + } ADADC; + char wk3[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short ACE : 1; + unsigned short ASE : 1; + unsigned short : 1; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 1; + unsigned short ASE : 1; + unsigned short ACE : 1; + unsigned short : 5; +#endif + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 7; + unsigned short : 1; + unsigned short TRSA : 7; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short TRSA : 7; + unsigned short : 1; + unsigned short TRSB : 7; +#endif + } BIT; + } ADSTRGR; + char wk4[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB000 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB003 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short ANSB003 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB000 : 1; +#endif + } BIT; + } ADANSB0; + char wk5[2]; + unsigned short ADDBLDR; + char wk6[4]; + union { + unsigned short WORD; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif + } RIGHT; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + char wk7[62]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SSTSH : 8; + unsigned short SHANS : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short SHANS : 3; + unsigned short SSTSH : 8; +#endif + } BIT; + } ADSHCR; + char wk8[18]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif + } BIT; + } ADDISCR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHMD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHMD : 1; +#endif + } BIT; + } ADSHMSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELCC : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char ELCC : 3; +#endif + } BIT; + } ADELCCR; + char wk10[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 12; + unsigned short LGRRS : 1; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short LGRRS : 1; + unsigned short : 12; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif + } BIT; + } ADGSPCR; + char wk11[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk12[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MONCOMB : 1; + unsigned char : 3; + unsigned char MONCMPA : 1; + unsigned char MONCMPB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MONCMPB : 1; + unsigned char MONCMPA : 1; + unsigned char : 3; + unsigned char MONCOMB : 1; +#endif + } BIT; + } ADWINMON; + char wk13[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPAB : 2; + unsigned short : 7; + unsigned short CMPBE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPAIE : 1; +#else + unsigned short CMPAIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPBIE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBE : 1; + unsigned short : 7; + unsigned short CMPAB : 2; +#endif + } BIT; + } ADCMPCR; + char wk14[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA000 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA003 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA000 : 1; +#endif + } BIT; + } ADCMPANSR0; + char wk15[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA000 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA000 : 1; +#endif + } BIT; + } ADCMPLR0; + char wk16[2]; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA000 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA000 : 1; +#endif + } BIT; + } ADCMPSR0; + char wk17[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCHB : 6; + unsigned char : 1; + unsigned char CMPLB : 1; +#else + unsigned char CMPLB : 1; + unsigned char : 1; + unsigned char CMPCHB : 6; +#endif + } BIT; + } ADCMPBNSR; + char wk18[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTB : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CMPSTB : 1; +#endif + } BIT; + } ADCMPBSR; + char wk19[39]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSC000 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC003 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short ANSC003 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC000 : 1; +#endif + } BIT; + } ADANSC0; + char wk20[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRSC : 6; + unsigned char GCADIE : 1; + unsigned char GRCE : 1; +#else + unsigned char GRCE : 1; + unsigned char GCADIE : 1; + unsigned char TRSC : 6; +#endif + } BIT; + } ADGCTRGR; + char wk21[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRSC6 : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TRSC6 : 1; +#endif + } BIT; + } ADGCTRGR2; + char wk22[3]; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + char wk23[188]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short P100CR : 4; + unsigned short P101CR : 4; + unsigned short P102CR : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short P102CR : 4; + unsigned short P101CR : 4; + unsigned short P100CR : 4; +#endif + } BIT; + } ADPGACR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short P100GAIN : 4; + unsigned short P101GAIN : 4; + unsigned short P102GAIN : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short P102GAIN : 4; + unsigned short P101GAIN : 4; + unsigned short P100GAIN : 4; +#endif + } BIT; + } ADPGAGS0; + char wk24[28]; + unsigned char ADSCS0; + unsigned char ADSCS1; + unsigned char ADSCS2; + unsigned char ADSCS3; +} st_s12ad1_t; + +typedef struct st_s12ad2 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short : 2; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 2; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA000 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA007 : 1; + unsigned short ANSA008 : 1; + unsigned short ANSA009 : 1; + unsigned short ANSA010 : 1; + unsigned short ANSA011 : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short ANSA011 : 1; + unsigned short ANSA010 : 1; + unsigned short ANSA009 : 1; + unsigned short ANSA008 : 1; + unsigned short ANSA007 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA000 : 1; +#endif + } BIT; + } ADANSA0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA100 : 1; + unsigned short ANSA101 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short ANSA101 : 1; + unsigned short ANSA100 : 1; +#endif + } BIT; + } ADANSA1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS000 : 1; + unsigned short ADS001 : 1; + unsigned short ADS002 : 1; + unsigned short ADS003 : 1; + unsigned short ADS004 : 1; + unsigned short ADS005 : 1; + unsigned short ADS006 : 1; + unsigned short ADS007 : 1; + unsigned short ADS008 : 1; + unsigned short ADS009 : 1; + unsigned short ADS010 : 1; + unsigned short ADS011 : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short ADS011 : 1; + unsigned short ADS010 : 1; + unsigned short ADS009 : 1; + unsigned short ADS008 : 1; + unsigned short ADS007 : 1; + unsigned short ADS006 : 1; + unsigned short ADS005 : 1; + unsigned short ADS004 : 1; + unsigned short ADS003 : 1; + unsigned short ADS002 : 1; + unsigned short ADS001 : 1; + unsigned short ADS000 : 1; +#endif + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS100 : 1; + unsigned short ADS101 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short ADS101 : 1; + unsigned short ADS100 : 1; +#endif + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 3; + unsigned char : 4; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 4; + unsigned char ADC : 3; +#endif + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short ACE : 1; + unsigned short ASE : 1; + unsigned short : 1; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 1; + unsigned short ASE : 1; + unsigned short ACE : 1; + unsigned short : 5; +#endif + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 7; + unsigned short : 1; + unsigned short TRSA : 7; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short TRSA : 7; + unsigned short : 1; + unsigned short TRSB : 7; +#endif + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSSAD : 1; + unsigned short OCSAD : 1; + unsigned short : 6; + unsigned short TSSA : 1; + unsigned short OCSA : 1; + unsigned short TSSB : 1; + unsigned short OCSB : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short OCSB : 1; + unsigned short TSSB : 1; + unsigned short OCSA : 1; + unsigned short TSSA : 1; + unsigned short : 6; + unsigned short OCSAD : 1; + unsigned short TSSAD : 1; +#endif + } BIT; + } ADEXICR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB000 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB007 : 1; + unsigned short ANSB008 : 1; + unsigned short ANSB009 : 1; + unsigned short ANSB010 : 1; + unsigned short ANSB011 : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short ANSB011 : 1; + unsigned short ANSB010 : 1; + unsigned short ANSB009 : 1; + unsigned short ANSB008 : 1; + unsigned short ANSB007 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB000 : 1; +#endif + } BIT; + } ADANSB0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB100 : 1; + unsigned short ANSB101 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short ANSB101 : 1; + unsigned short ANSB100 : 1; +#endif + } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union { + unsigned short WORD; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif + } RIGHT; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + unsigned short ADDR8; + unsigned short ADDR9; + unsigned short ADDR10; + unsigned short ADDR11; + char wk2[8]; + unsigned short ADDR16; + unsigned short ADDR17; + char wk3[54]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif + } BIT; + } ADDISCR; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELCC : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char ELCC : 3; +#endif + } BIT; + } ADELCCR; + char wk5[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 12; + unsigned short LGRRS : 1; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short LGRRS : 1; + unsigned short : 12; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif + } BIT; + } ADGSPCR; + char wk6[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk7[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MONCOMB : 1; + unsigned char : 3; + unsigned char MONCMPA : 1; + unsigned char MONCMPB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MONCMPB : 1; + unsigned char MONCMPA : 1; + unsigned char : 3; + unsigned char MONCOMB : 1; +#endif + } BIT; + } ADWINMON; + char wk8[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPAB : 2; + unsigned short : 7; + unsigned short CMPBE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPAIE : 1; +#else + unsigned short CMPAIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPBIE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBE : 1; + unsigned short : 7; + unsigned short CMPAB : 2; +#endif + } BIT; + } ADCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTS : 1; + unsigned char CMPSOC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPSOC : 1; + unsigned char CMPSTS : 1; +#endif + } BIT; + } ADCMPANSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPLTS : 1; + unsigned char CMPLOC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPLOC : 1; + unsigned char CMPLTS : 1; +#endif + } BIT; + } ADCMPLER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA000 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA008 : 1; + unsigned short CMPCHA009 : 1; + unsigned short CMPCHA010 : 1; + unsigned short CMPCHA011 : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short CMPCHA011 : 1; + unsigned short CMPCHA010 : 1; + unsigned short CMPCHA009 : 1; + unsigned short CMPCHA008 : 1; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA000 : 1; +#endif + } BIT; + } ADCMPANSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA100 : 1; + unsigned short CMPCHA101 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA100 : 1; +#endif + } BIT; + } ADCMPANSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA000 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA008 : 1; + unsigned short CMPLCHA009 : 1; + unsigned short CMPLCHA010 : 1; + unsigned short CMPLCHA011 : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short CMPLCHA011 : 1; + unsigned short CMPLCHA010 : 1; + unsigned short CMPLCHA009 : 1; + unsigned short CMPLCHA008 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA000 : 1; +#endif + } BIT; + } ADCMPLR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA100 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA100 : 1; +#endif + } BIT; + } ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA000 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA008 : 1; + unsigned short CMPSTCHA009 : 1; + unsigned short CMPSTCHA010 : 1; + unsigned short CMPSTCHA011 : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short CMPSTCHA011 : 1; + unsigned short CMPSTCHA010 : 1; + unsigned short CMPSTCHA009 : 1; + unsigned short CMPSTCHA008 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA000 : 1; +#endif + } BIT; + } ADCMPSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA100 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA100 : 1; +#endif + } BIT; + } ADCMPSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPFTS : 1; + unsigned char CMPFOC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPFOC : 1; + unsigned char CMPFTS : 1; +#endif + } BIT; + } ADCMPSER; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCHB : 6; + unsigned char : 1; + unsigned char CMPLB : 1; +#else + unsigned char CMPLB : 1; + unsigned char : 1; + unsigned char CMPCHB : 6; +#endif + } BIT; + } ADCMPBNSR; + char wk10[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTB : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CMPSTB : 1; +#endif + } BIT; + } ADCMPBSR; + char wk11[39]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSC000 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC003 : 1; + unsigned short ANSC004 : 1; + unsigned short ANSC005 : 1; + unsigned short ANSC006 : 1; + unsigned short ANSC007 : 1; + unsigned short ANSC008 : 1; + unsigned short ANSC009 : 1; + unsigned short ANSC010 : 1; + unsigned short ANSC011 : 1; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short ANSC011 : 1; + unsigned short ANSC010 : 1; + unsigned short ANSC009 : 1; + unsigned short ANSC008 : 1; + unsigned short ANSC007 : 1; + unsigned short ANSC006 : 1; + unsigned short ANSC005 : 1; + unsigned short ANSC004 : 1; + unsigned short ANSC003 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC000 : 1; +#endif + } BIT; + } ADANSC0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSC100 : 1; + unsigned short ANSC101 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short ANSC101 : 1; + unsigned short ANSC100 : 1; +#endif + } BIT; + } ADANSC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TSSC : 1; + unsigned char OCSC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char OCSC : 1; + unsigned char TSSC : 1; +#endif + } BIT; + } ADGCEXCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRSC : 6; + unsigned char GCADIE : 1; + unsigned char GRCE : 1; +#else + unsigned char GRCE : 1; + unsigned char GCADIE : 1; + unsigned char TRSC : 6; +#endif + } BIT; + } ADGCTRGR; + char wk12[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRSC6 : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TRSC6 : 1; +#endif + } BIT; + } ADGCTRGR2; + unsigned char ADSSTRL; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; + unsigned char ADSSTR8; + unsigned char ADSSTR9; + unsigned char ADSSTR10; + unsigned char ADSSTR11; + char wk13[212]; + unsigned char ADSCS0; + unsigned char ADSCS1; + unsigned char ADSCS2; + unsigned char ADSCS3; + unsigned char ADSCS4; + unsigned char ADSCS5; + unsigned char ADSCS6; + unsigned char ADSCS7; + unsigned char ADSCS8; + unsigned char ADSCS9; + unsigned char ADSCS10; + unsigned char ADSCS11; + char wk14[4]; + unsigned char ADSCS12; + unsigned char ADSCS13; + char wk15[16]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char VDE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char VDE : 1; +#endif + } BIT; + } ADVMONCR; + char wk16[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char VDO : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char VDO : 1; +#endif + } BIT; + } ADVMONO; +} st_s12ad2_t; + +typedef struct st_sci1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char ITE : 1; + unsigned char BRME : 1; + unsigned char ABCSE : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char ABCSE : 1; + unsigned char BRME : 1; + unsigned char ITE : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCMF : 1; + unsigned char : 2; + unsigned char DPER : 1; + unsigned char DFER : 1; + unsigned char : 1; + unsigned char IDSEL : 1; + unsigned char DCME : 1; +#else + unsigned char DCME : 1; + unsigned char IDSEL : 1; + unsigned char : 1; + unsigned char DFER : 1; + unsigned char DPER : 1; + unsigned char : 2; + unsigned char DCMF : 1; +#endif + } BIT; + } DCCR; + char wk0[6]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPD : 9; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short CMPD : 9; +#endif + } BIT; + } CDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RXDMON : 1; + unsigned char SPB2DT : 1; + unsigned char SPB2IO : 1; + unsigned char : 1; + unsigned char RINV : 1; + unsigned char TINV : 1; + unsigned char RTADJ : 1; + unsigned char TTADJ : 1; +#else + unsigned char TTADJ : 1; + unsigned char RTADJ : 1; + unsigned char TINV : 1; + unsigned char RINV : 1; + unsigned char : 1; + unsigned char SPB2IO : 1; + unsigned char SPB2DT : 1; + unsigned char RXDMON : 1; +#endif + } BIT; + } SPTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RTMG : 4; + unsigned char TTMG : 4; +#else + unsigned char TTMG : 4; + unsigned char RTMG : 4; +#endif + } BIT; + } TMGR; +} st_sci1_t; + +typedef struct st_sci12 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char ITE : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char ITE : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ESME : 1; +#endif + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SFSF : 1; + unsigned char RXDSF : 1; + unsigned char BRME : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char BRME : 1; + unsigned char RXDSF : 1; + unsigned char SFSF : 1; + unsigned char : 1; +#endif + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFE : 1; + unsigned char CF0RE : 1; + unsigned char CF1DS : 2; + unsigned char PIBE : 1; + unsigned char PIBS : 3; +#else + unsigned char PIBS : 3; + unsigned char PIBE : 1; + unsigned char CF1DS : 2; + unsigned char CF0RE : 1; + unsigned char BFE : 1; +#endif + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFCS : 3; + unsigned char : 1; + unsigned char BCCS : 2; + unsigned char RTS : 2; +#else + unsigned char RTS : 2; + unsigned char BCCS : 2; + unsigned char : 1; + unsigned char DFCS : 3; +#endif + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SDST : 1; +#endif + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TXDXPS : 1; + unsigned char RXDXPS : 1; + unsigned char : 2; + unsigned char SHARPS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SHARPS : 1; + unsigned char : 2; + unsigned char RXDXPS : 1; + unsigned char TXDXPS : 1; +#endif + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDIE : 1; + unsigned char CF0MIE : 1; + unsigned char CF1MIE : 1; + unsigned char PIBDIE : 1; + unsigned char BCDIE : 1; + unsigned char AEDIE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDIE : 1; + unsigned char BCDIE : 1; + unsigned char PIBDIE : 1; + unsigned char CF1MIE : 1; + unsigned char CF0MIE : 1; + unsigned char BFDIE : 1; +#endif + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDF : 1; + unsigned char CF0MF : 1; + unsigned char CF1MF : 1; + unsigned char PIBDF : 1; + unsigned char BCDF : 1; + unsigned char AEDF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDF : 1; + unsigned char BCDF : 1; + unsigned char PIBDF : 1; + unsigned char CF1MF : 1; + unsigned char CF0MF : 1; + unsigned char BFDF : 1; +#endif + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDCL : 1; + unsigned char CF0MCL : 1; + unsigned char CF1MCL : 1; + unsigned char PIBDCL : 1; + unsigned char BCDCL : 1; + unsigned char AEDCL : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDCL : 1; + unsigned char BCDCL : 1; + unsigned char PIBDCL : 1; + unsigned char CF1MCL : 1; + unsigned char CF0MCL : 1; + unsigned char BFDCL : 1; +#endif + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0CE0 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE7 : 1; +#else + unsigned char CF0CE7 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE0 : 1; +#endif + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF1CE0 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE7 : 1; +#else + unsigned char CF1CE7 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE0 : 1; +#endif + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCST : 1; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TOMS : 2; + unsigned char : 1; + unsigned char TWRC : 1; + unsigned char TCSS : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char TCSS : 3; + unsigned char TWRC : 1; + unsigned char : 1; + unsigned char TOMS : 2; +#endif + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +} st_sci12_t; + +typedef struct st_smci { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char BCP : 2; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char BLK : 1; + unsigned char GM : 1; +#else + unsigned char GM : 1; + unsigned char BLK : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char BCP : 2; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char ERS : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char ERS : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; +} st_smci_t; + +typedef struct st_system { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short MD : 1; +#endif + } BIT; + } MDMONR; + char wk0[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RAME : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RAME : 1; +#endif + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short SSBY : 1; +#else + unsigned short SSBY : 1; + unsigned short : 15; +#endif + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPA0 : 1; + unsigned long MSTPA1 : 1; + unsigned long MSTPA2 : 1; + unsigned long MSTPA3 : 1; + unsigned long MSTPA4 : 1; + unsigned long MSTPA5 : 1; + unsigned long : 1; + unsigned long MSTPA7 : 1; + unsigned long : 1; + unsigned long MSTPA9 : 1; + unsigned long : 4; + unsigned long MSTPA14 : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA16 : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA19 : 1; + unsigned long : 3; + unsigned long MSTPA23 : 1; + unsigned long MSTPA24 : 1; + unsigned long : 2; + unsigned long MSTPA27 : 1; + unsigned long MSTPA28 : 1; + unsigned long MSTPA29 : 1; + unsigned long : 1; + unsigned long ACSE : 1; +#else + unsigned long ACSE : 1; + unsigned long : 1; + unsigned long MSTPA29 : 1; + unsigned long MSTPA28 : 1; + unsigned long MSTPA27 : 1; + unsigned long : 2; + unsigned long MSTPA24 : 1; + unsigned long MSTPA23 : 1; + unsigned long : 3; + unsigned long MSTPA19 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long MSTPA16 : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA14 : 1; + unsigned long : 4; + unsigned long MSTPA9 : 1; + unsigned long : 1; + unsigned long MSTPA7 : 1; + unsigned long : 1; + unsigned long MSTPA5 : 1; + unsigned long MSTPA4 : 1; + unsigned long MSTPA3 : 1; + unsigned long MSTPA2 : 1; + unsigned long MSTPA1 : 1; + unsigned long MSTPA0 : 1; +#endif + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long MSTPB4 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 2; + unsigned long MSTPB9 : 1; + unsigned long MSTPB10 : 1; + unsigned long : 6; + unsigned long MSTPB17 : 1; + unsigned long : 3; + unsigned long MSTPB21 : 1; + unsigned long : 1; + unsigned long MSTPB23 : 1; + unsigned long : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB26 : 1; + unsigned long : 3; + unsigned long MSTPB30 : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long MSTPB30 : 1; + unsigned long : 3; + unsigned long MSTPB26 : 1; + unsigned long MSTPB25 : 1; + unsigned long : 1; + unsigned long MSTPB23 : 1; + unsigned long : 1; + unsigned long MSTPB21 : 1; + unsigned long : 3; + unsigned long MSTPB17 : 1; + unsigned long : 6; + unsigned long MSTPB10 : 1; + unsigned long MSTPB9 : 1; + unsigned long : 2; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB4 : 1; + unsigned long : 4; +#endif + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPC0 : 1; + unsigned long : 18; + unsigned long MSTPC19 : 1; + unsigned long : 4; + unsigned long MSTPC24 : 1; + unsigned long : 1; + unsigned long MSTPC26 : 1; + unsigned long MSTPC27 : 1; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long MSTPC27 : 1; + unsigned long MSTPC26 : 1; + unsigned long : 1; + unsigned long MSTPC24 : 1; + unsigned long : 4; + unsigned long MSTPC19 : 1; + unsigned long : 18; + unsigned long MSTPC0 : 1; +#endif + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 5; + unsigned long MSTPD5 : 1; + unsigned long : 4; + unsigned long MSTPD10 : 1; + unsigned long : 15; + unsigned long MSTPD26 : 1; + unsigned long MSTPD27 : 1; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long MSTPD27 : 1; + unsigned long MSTPD26 : 1; + unsigned long : 15; + unsigned long MSTPD10 : 1; + unsigned long : 4; + unsigned long MSTPD5 : 1; + unsigned long : 5; +#endif + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKD : 4; + unsigned long PCKC : 4; + unsigned long PCKB : 4; + unsigned long PCKA : 4; + unsigned long : 8; + unsigned long ICK : 4; + unsigned long FCK : 4; +#else + unsigned long FCK : 4; + unsigned long ICK : 4; + unsigned long : 8; + unsigned long PCKA : 4; + unsigned long PCKB : 4; + unsigned long PCKC : 4; + unsigned long PCKD : 4; +#endif + } BIT; + } SCKCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 12; + unsigned short CFDCK : 4; +#else + unsigned short CFDCK : 4; + unsigned short : 12; +#endif + } BIT; + } SCKCR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKSEL : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CKSEL : 3; + unsigned short : 8; +#endif + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PLIDIV : 2; + unsigned short : 2; + unsigned short PLLSRCSEL : 1; + unsigned short : 3; + unsigned short STC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short STC : 6; + unsigned short : 3; + unsigned short PLLSRCSEL : 1; + unsigned short : 2; + unsigned short PLIDIV : 2; +#endif + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PLLEN : 1; +#endif + } BIT; + } PLLCR2; + char wk3[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MOSTP : 1; +#endif + } BIT; + } MOSCCR; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LCSTP : 1; +#endif + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ILCSTP : 1; +#endif + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HCSTP : 1; +#endif + } BIT; + } HOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCFRQ : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char HCFRQ : 2; +#endif + } BIT; + } HOCOCR2; + char wk5[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOOVF : 1; + unsigned char : 1; + unsigned char PLOVF : 1; + unsigned char HCOVF : 1; + unsigned char ILCOVF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ILCOVF : 1; + unsigned char HCOVF : 1; + unsigned char PLOVF : 1; + unsigned char : 1; + unsigned char MOOVF : 1; +#endif + } BIT; + } OSCOVFSR; + char wk6[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDIE : 1; + unsigned char : 6; + unsigned char OSTDE : 1; +#else + unsigned char OSTDE : 1; + unsigned char : 6; + unsigned char OSTDIE : 1; +#endif + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char OSTDF : 1; +#endif + } BIT; + } OSTDSR; + char wk7[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RSTCKSEL : 3; + unsigned char : 4; + unsigned char RSTCKEN : 1; +#else + unsigned char RSTCKEN : 1; + unsigned char : 4; + unsigned char RSTCKSEL : 3; +#endif + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MSTS : 8; +#else + unsigned char MSTS : 8; +#endif + } BIT; + } MOSCWTCR; + char wk8[29]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IWDTRF : 1; + unsigned char WDTRF : 1; + unsigned char SWRF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SWRF : 1; + unsigned char WDTRF : 1; + unsigned char IWDTRF : 1; +#endif + } BIT; + } RSTSR2; + char wk9[1]; + unsigned short SWRR; + char wk10[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 10; + unsigned long SCI5RXD : 2; + unsigned long : 4; + unsigned long SCI8RXD : 2; + unsigned long SCI9RXD : 2; + unsigned long : 2; + unsigned long SCI11RXD : 2; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long SCI11RXD : 2; + unsigned long : 2; + unsigned long SCI9RXD : 2; + unsigned long SCI8RXD : 2; + unsigned long : 4; + unsigned long SCI5RXD : 2; + unsigned long : 10; +#endif + } BIT; + } PRDFR0; + char wk11[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1IDTSEL : 2; + unsigned char LVD1IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD1IRQSEL : 1; + unsigned char LVD1IDTSEL : 2; +#endif + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1DET : 1; + unsigned char LVD1MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD1MON : 1; + unsigned char LVD1DET : 1; +#endif + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2IDTSEL : 2; + unsigned char LVD2IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD2IRQSEL : 1; + unsigned char LVD2IDTSEL : 2; +#endif + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2DET : 1; + unsigned char LVD2MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD2MON : 1; + unsigned char LVD2DET : 1; +#endif + } BIT; + } LVD2SR; + char wk12[794]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PRC0 : 1; + unsigned short PRC1 : 1; + unsigned short : 1; + unsigned short PRC3 : 1; + unsigned short : 4; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 4; + unsigned short PRC3 : 1; + unsigned short : 1; + unsigned short PRC1 : 1; + unsigned short PRC0 : 1; +#endif + } BIT; + } PRCR; + char wk13[48784]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PORF : 1; + unsigned char LVD0RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD2RF : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char LVD2RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD0RF : 1; + unsigned char PORF : 1; +#endif + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CWSF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CWSF : 1; +#endif + } BIT; + } RSTSR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char MODRV2 : 2; + unsigned char MOSEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MOSEL : 1; + unsigned char MODRV2 : 2; + unsigned char : 4; +#endif + } BIT; + } MOFCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOCOPCNT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HOCOPCNT : 1; +#endif + } BIT; + } HOCOPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RICVLS : 1; +#else + unsigned char RICVLS : 1; + unsigned char : 7; +#endif + } BIT; + } VOLSR; + char wk15[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char LVD1E : 1; + unsigned char LVD2E : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LVD2E : 1; + unsigned char LVD1E : 1; + unsigned char : 5; +#endif + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1LVL : 4; + unsigned char LVD2LVL : 4; +#else + unsigned char LVD2LVL : 4; + unsigned char LVD1LVL : 4; +#endif + } BIT; + } LVDLVLR; + char wk16[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1RIE : 1; + unsigned char LVD1DFDIS : 1; + unsigned char LVD1CMPE : 1; + unsigned char : 1; + unsigned char LVD1FSAMP : 2; + unsigned char LVD1RI : 1; + unsigned char LVD1RN : 1; +#else + unsigned char LVD1RN : 1; + unsigned char LVD1RI : 1; + unsigned char LVD1FSAMP : 2; + unsigned char : 1; + unsigned char LVD1CMPE : 1; + unsigned char LVD1DFDIS : 1; + unsigned char LVD1RIE : 1; +#endif + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2RIE : 1; + unsigned char LVD2DFDIS : 1; + unsigned char LVD2CMPE : 1; + unsigned char : 1; + unsigned char LVD2FSAMP : 2; + unsigned char LVD2RI : 1; + unsigned char LVD2RN : 1; +#else + unsigned char LVD2RN : 1; + unsigned char LVD2RI : 1; + unsigned char LVD2FSAMP : 2; + unsigned char : 1; + unsigned char LVD2CMPE : 1; + unsigned char LVD2DFDIS : 1; + unsigned char LVD2RIE : 1; +#endif + } BIT; + } LVD2CR0; +} st_system_t; + +typedef struct st_temps { + unsigned long TSCDR; +} st_temps_t; + +typedef struct st_tfu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IUF : 1; + unsigned char : 3; + unsigned char OF : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OF : 2; + unsigned char : 3; + unsigned char IUF : 1; +#endif + } BIT; + } FXSCIOC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char OUF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char OUF : 1; + unsigned char : 4; +#endif + } BIT; + } FXATIOC; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BSYF : 1; + unsigned char ERRF : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char ERRF : 1; + unsigned char BSYF : 1; +#endif + } BIT; + } TRGSTS; + char wk1[7]; + float FPSCDT0; + float FPSCDT1; + float FPATDT0; + float FPATDT1; + signed long FXSCDT0; + signed long FXSCDT1; + signed long FXATDT0; + signed long FXATDT1; + unsigned long DTSR0; + unsigned long DTSR1; +} st_tfu_t; + +typedef struct st_tmr0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char ADTE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADTE : 1; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif + } BIT; + } TCSTR; +} st_tmr0_t; + +typedef struct st_tmr1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif + } BIT; + } TCSTR; +} st_tmr1_t; + +typedef struct st_tmr4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char ADTE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADTE : 1; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; +} st_tmr4_t; + +typedef struct st_tmr5 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; +} st_tmr5_t; + +typedef struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +} st_tmr01_t; + +typedef struct st_wdt { + unsigned char WDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } WDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } WDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } WDTRCR; +} st_wdt_t; + + +#pragma pack() + +#endif + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/vecttbl.c b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/vecttbl.c new file mode 100644 index 00000000..52693f0b --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/vecttbl.c @@ -0,0 +1,230 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : vecttbl.c +* Device(s) : RX26T +* Description : Definition of the exception vector table, reset vector, and user boot options. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 26.02.2025 1.01 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* BSP configuration. */ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +R_BSP_POR_FUNCTION(R_BSP_POWER_ON_RESET_FUNCTION); + +/*********************************************************************************************************************** +* The following array fills in the option function select registers and the ID code protection bytes. +***********************************************************************************************************************/ +#ifdef __BIG + #define BSP_PRV_MDE_VALUE (0xfffffff8) /* big */ +#else + #define BSP_PRV_MDE_VALUE (0xffffffff) /* little */ +#endif + +#if BSP_CFG_ID_CODE_ENABLE == 1 + #define BSP_PRV_SPCC_IDE (0xfeffffff) /* ID code protection is enabled after a reset. */ +#else + #define BSP_PRV_SPCC_IDE (0xffffffff) /* ID code protection is disabled after a reset. */ +#endif + +#if (BSP_CFG_BLOCK_ERASE_CMD_PROTECT_ENABLE == 1) || (BSP_CFG_ID_CODE_ENABLE == 1) + #define BSP_PRV_SPCC_SEPR (0xdfffffff) /* Block erasure command protection after a reset is enabled. */ +#else + #define BSP_PRV_SPCC_SEPR (0xffffffff) /* Block erasure command protection after a reset is disabled. */ +#endif + +#if (BSP_CFG_PROGRAM_CMD_PROTECT_ENABLE == 1) || (BSP_CFG_ID_CODE_ENABLE == 1) + #define BSP_PRV_SPCC_WRPR (0xbfffffff) /* Programming command protection after a reset is enabled. */ +#else + #define BSP_PRV_SPCC_WRPR (0xffffffff) /* Programming command protection after a reset is disabled. */ +#endif + +#if (BSP_CFG_READ_CMD_PROTECT_ENABLE == 1) || (BSP_CFG_ID_CODE_ENABLE == 1) + #define BSP_PRV_SPCC_RDPR (0x7fffffff) /* Read command protection after a reset is enabled. */ +#else + #define BSP_PRV_SPCC_RDPR (0xffffffff) /* Read command protection after a reset is disabled. */ +#endif + +#if BSP_CFG_SERIAL_PROGRAMMER_CONECT_ENABLE == 0 + #define BSP_PRV_SPCC_SPE (0xf7ffffff) /* Connection of a serial programmer after a reset is prohibited. */ +#else + #define BSP_PRV_SPCC_SPE (0xffffffff) /* Connection of a serial programmer after a reset is permitted. */ +#endif + +#define BSP_PRV_SPCC_VALUE ((((BSP_PRV_SPCC_IDE & BSP_PRV_SPCC_SEPR) & BSP_PRV_SPCC_WRPR) & BSP_PRV_SPCC_RDPR) & BSP_PRV_SPCC_SPE) + +#if BSP_CFG_MCU_PART_MEMORY_SIZE == 0xF + #if BSP_CFG_CODE_FLASH_BANK_MODE == 0 /* In the case of 512Kbyte ROM capacity. */ + #define BSP_PRV_BANK_MODE_VALUE (0xffffff8f) /* dual */ + #else + #define BSP_PRV_BANK_MODE_VALUE (0xffffffff) /* linear */ + #endif +#else + #define BSP_PRV_BANK_MODE_VALUE (0xffffffff) /* linear */ +#endif + +#if BSP_CFG_MCU_PART_MEMORY_SIZE == 0xF + #if BSP_CFG_CODE_FLASH_START_BANK == 0 + /* The address range of bank 1 from FFF80000h to FFFBFFFFh and bank 0 from FFFC0000h to FFFFFFFFh. */ + #define BSP_PRV_START_BANK_VALUE (0xffffffff) + #else + /* The address range of bank 1 from FFFC0000h to FFFFFFFFh and bank 0 from FFF80000h to FFFBFFFFh. */ + #define BSP_PRV_START_BANK_VALUE (0xfffffff8) + #endif +#endif + +#if defined(__CCRX__) + +#pragma address __SPCCreg = 0x00120040 +#pragma address __TMEFreg = 0x00120048 +#pragma address __OSIS1reg = 0x00120050 +#pragma address __OSIS2reg = 0x00120054 +#pragma address __OSIS3reg = 0x00120058 +#pragma address __OSIS4reg = 0x0012005c +#pragma address __TMINFreg = 0x00120060 +#pragma address __MDEreg = 0x00120064 +#pragma address __OFS0reg = 0x00120068 +#pragma address __OFS1reg = 0x0012006c +#if BSP_CFG_MCU_PART_MEMORY_SIZE == 0xF +#pragma address __BANKSELreg = 0x00120090 +#endif +#pragma address __FAWreg = 0x001200A0 + +const uint32_t __SPCCreg = BSP_PRV_SPCC_VALUE; +const uint32_t __TMEFreg = BSP_CFG_TRUSTED_MODE_FUNCTION; +const uint32_t __OSIS1reg = BSP_CFG_ID_CODE_LONG_1; +const uint32_t __OSIS2reg = BSP_CFG_ID_CODE_LONG_2; +const uint32_t __OSIS3reg = BSP_CFG_ID_CODE_LONG_3; +const uint32_t __OSIS4reg = BSP_CFG_ID_CODE_LONG_4; +const uint32_t __TMINFreg = 0xffffffff; +const uint32_t __MDEreg = (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE); +const uint32_t __OFS0reg = BSP_CFG_OFS0_REG_VALUE; +const uint32_t __OFS1reg = BSP_CFG_OFS1_REG_VALUE; +#if BSP_CFG_MCU_PART_MEMORY_SIZE == 0xF +const uint32_t __BANKSELreg = BSP_PRV_START_BANK_VALUE; +#endif +const uint32_t __FAWreg = BSP_CFG_FAW_REG_VALUE; + +#elif defined(__GNUC__) + +const uint32_t __SPCCreg __attribute__ ((section(".ofs1"))) = BSP_PRV_SPCC_VALUE; +const uint32_t __TMEFreg __attribute__ ((section(".ofs2"))) = BSP_CFG_TRUSTED_MODE_FUNCTION; +const st_ofsm_sec_ofs3_t __ofsm_sec_ofs3 __attribute__ ((section(".ofs3"))) = { + BSP_CFG_ID_CODE_LONG_1, /* __OSIS1reg */ + BSP_CFG_ID_CODE_LONG_2, /* __OSIS2reg */ + BSP_CFG_ID_CODE_LONG_3, /* __OSIS3reg */ + BSP_CFG_ID_CODE_LONG_4 /* __OSIS4reg */ +}; +const st_ofsm_sec_ofs4_t __ofsm_sec_ofs4 __attribute__ ((section(".ofs4"))) = { + 0xffffffff, /* __TMINFreg */ + (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE), /* __MDEreg */ + BSP_CFG_OFS0_REG_VALUE, /* __OFS0reg */ + BSP_CFG_OFS1_REG_VALUE /* __OFS1reg */ +}; +#if BSP_CFG_MCU_PART_MEMORY_SIZE == 0xF +const uint32_t __BANKSELreg __attribute__ ((section(".ofs5"))) = BSP_PRV_START_BANK_VALUE; +#endif +const uint32_t __FAWreg __attribute__ ((section(".ofs6"))) = BSP_CFG_FAW_REG_VALUE; + +#elif defined(__ICCRX__) + +#pragma public_equ = "__SPCC", BSP_PRV_SPCC_VALUE +#pragma public_equ = "__TMINF", 0xffffffff +#pragma public_equ = "__OSIS_1", BSP_CFG_ID_CODE_LONG_1 +#pragma public_equ = "__OSIS_2", BSP_CFG_ID_CODE_LONG_2 +#pragma public_equ = "__OSIS_3", BSP_CFG_ID_CODE_LONG_3 +#pragma public_equ = "__OSIS_4", BSP_CFG_ID_CODE_LONG_4 +#pragma public_equ = "__TMEF", BSP_CFG_TRUSTED_MODE_FUNCTION +#pragma public_equ = "__MDE", (BSP_PRV_MDE_VALUE & BSP_PRV_BANK_MODE_VALUE) +#pragma public_equ = "__OFS0", BSP_CFG_OFS0_REG_VALUE +#pragma public_equ = "__OFS1", BSP_CFG_OFS1_REG_VALUE +#if BSP_CFG_MCU_PART_MEMORY_SIZE == 0xF +#pragma public_equ = "__BANKSEL", BSP_PRV_START_BANK_VALUE +#endif +#pragma public_equ = "__FAW", BSP_CFG_FAW_REG_VALUE + +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* The following array fills in the exception vector table. +***********************************************************************************************************************/ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + /* System configurator generates the ritble.src as interrupt & exception vector tables. */ +#else /* BSP_CFG_RTOS_USED!=4 */ + +#if defined(__CCRX__) || defined(__GNUC__) +R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT void (* const Except_Vectors[])(void) = +{ + /* Offset from EXTB: Reserved area - must be all 0xFF */ + (void (*)(void))0xFFFFFFFF, /* 0x00 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x04 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x08 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x0c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x10 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x14 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x18 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x1c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x20 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x24 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x28 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x2c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x30 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x34 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x38 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x3c - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x40 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x44 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x48 - Reserved */ + (void (*)(void))0xFFFFFFFF, /* 0x4c - Reserved */ + + /* Exception vector table */ + excep_supervisor_inst_isr, /* 0x50 Exception(Supervisor Instruction) */ + excep_access_isr, /* 0x54 Exception(Access exception) */ + undefined_interrupt_source_isr, /* 0x58 Reserved */ + excep_undefined_inst_isr, /* 0x5c Exception(Undefined Instruction) */ + undefined_interrupt_source_isr, /* 0x60 Reserved */ + excep_floating_point_isr, /* 0x64 Exception(Floating Point) */ + undefined_interrupt_source_isr, /* 0x68 Reserved */ + undefined_interrupt_source_isr, /* 0x6c Reserved */ + undefined_interrupt_source_isr, /* 0x70 Reserved */ + undefined_interrupt_source_isr, /* 0x74 Reserved */ + non_maskable_isr, /* 0x78 NMI */ +}; +R_BSP_ATTRIB_SECTION_CHANGE_END +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +/*********************************************************************************************************************** +* The following array fills in the reset vector. +***********************************************************************************************************************/ +#if defined(__CCRX__) || defined(__GNUC__) +R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT void (* const Reset_Vector[])(void) = +{ + R_BSP_POWER_ON_RESET_FUNCTION /* 0xfffffffc RESET */ +}; +R_BSP_ATTRIB_SECTION_CHANGE_END +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +#endif/* BSP_CFG_RTOS_USED */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/vecttbl.h b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/vecttbl.h new file mode 100644 index 00000000..e74d8039 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/vecttbl.h @@ -0,0 +1,53 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : vecttbl.h +* Description : Has function prototypes for exception callback functions. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 26.02.2025 1.01 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef VECTTBL_HEADER_INC +#define VECTTBL_HEADER_INC + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if defined(__GNUC__) +typedef struct st_ofsm_sec_ofs3 +{ + uint32_t __OSIS1reg; + uint32_t __OSIS2reg; + uint32_t __OSIS3reg; + uint32_t __OSIS4reg; +} st_ofsm_sec_ofs3_t; + +typedef struct st_ofsm_sec_ofs4 +{ + uint32_t __TMINFreg; + uint32_t __MDEreg; + uint32_t __OFS0reg; + uint32_t __OFS1reg; +} st_ofsm_sec_ofs4_t; +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* VECTTBL_HEADER_INC */ + diff --git a/drivers/rx/rdp/src/r_bsp/platform.h b/drivers/rx/rdp/src/r_bsp/platform.h index 4b40e9c5..24300028 100644 --- a/drivers/rx/rdp/src/r_bsp/platform.h +++ b/drivers/rx/rdp/src/r_bsp/platform.h @@ -205,7 +205,9 @@ DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING. //#include "./board/generic_rx261/r_bsp.h" /* GENERIC_RX26T */ -//#include "./board/generic_rx26t/r_bsp.h" +#if defined(CONFIG_SOC_SERIES_RX26T) +#include "./board/generic_rx26t/r_bsp.h" +#endif /* GENERIC_RX261 */ #if defined(CONFIG_SOC_SERIES_RX261) diff --git a/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx26t/r_gpio_rx26t.c b/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx26t/r_gpio_rx26t.c new file mode 100644 index 00000000..a62fc0fa --- /dev/null +++ b/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx26t/r_gpio_rx26t.c @@ -0,0 +1,190 @@ +/*********************************************************************************************************************** +* Copyright (c) 2023 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx26t.c +* Description : Data for r_gpio_rx driver specific to RX26T. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 07.04.2023 1.00 First Release +* : 15.03.2025 5.11 Updated disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" + +#if defined(BSP_MCU_RX26T) + +/* Public interface header file for this package. */ +#include "r_gpio_rx_if.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* These arrays hold which pins have extra functionality. For example, not all pins have the option of enabling + * open-drain N-channel output instead of the default CMOS output. Each entry in the array corresponds to a port. + * Each bit in each entry corresponds to a pin on that port. If bit 3 of array entry [4] was set to 1 then that would + * mean that PORT 4 PIN 3 supported the feature that array represented. + * + * These arrays are only used when GPIO_CFG_PARAM_CHECKING_ENABLE is set to 1 (checking enabled). If you know that + * your code does not need to check the pins then you can set this macro to 0 and save a little execution time + * and ROM space. + * + * Note: These arrays are defined for the largest package part. For smaller packages where some pins do not exist, + * pin checking is filtered by the enumerated port_pin list for that package as defined in r_gpio_rx26t.h. + */ + +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) +const uint8_t g_gpio_open_drain_n_support[GPIO_INFO_NUM_PORTS] = +{ + 0x03, //PORT0 P00, P01 + 0x03, //PORT1 P10, P11 + 0x9F, //PORT2 P20 to P24, P27 + 0xCF, //PORT3 P30 to P33, P36, P37 + 0xFF, //PORT4 P40 to P47 + 0x3F, //PORT5 P50 to P55 + 0x3F, //PORT6 P60 to P65 + 0x7F, //PORT7 P70 to P76 + 0x07, //PORT8 P80 to P82 + 0x7F, //PORT9 P90 to P96 + 0x3F, //PORTA PA0 to PA5 + 0xFF, //PORTB PB0 to PB7 + 0x00, //PORTC None + 0xFF, //PORTD PD0 to PD7 + 0x3B, //PORTE PE0, PE1, PE3 to PE5 + 0x00, //PORTF None + 0x00, //PORTG None + 0x00, //PORTH None + 0x00, //PORTJ None + 0x00, //PORTK None + 0x00, //PORTL None + 0x00, //PORTM None + 0x40, //PORTN PN6 +}; + +const uint8_t g_gpio_open_drain_p_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, //PORT0 None + 0x00, //PORT1 None + 0x00, //PORT2 None + 0x00, //PORT3 None + 0x00, //PORT4 None + 0x00, //PORT5 None + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0x00, //PORTA None + 0x00, //PORTB None + 0x00, //PORTC None + 0x00, //PORTD None + 0x00, //PORTE None + 0x00, //PORTF None + 0x00, //PORTG None + 0x00, //PORTH None + 0x00, //PORTJ None + 0x00, //PORTK None + 0x00, //PORTL None + 0x00, //PORTM None + 0x00, //PORTN None +}; + +const uint8_t g_gpio_pull_up_support[GPIO_INFO_NUM_PORTS] = +{ + 0x03, //PORT0 P00, P01 + 0x03, //PORT1 P10, P11 + 0x9F, //PORT2 P20 to P24, P27 + 0xCF, //PORT3 P30 to P33, P36, P37 + 0xFF, //PORT4 P40 to P47 + 0x3F, //PORT5 P50 to P55 + 0x3F, //PORT6 P60 to P65 + 0x7F, //PORT7 P70 to P76 + 0x07, //PORT8 P80 to P82 + 0x7F, //PORT9 P90 to P96 + 0x3F, //PORTA PA0 to PA5 + 0xFF, //PORTB PB0 to PB7 + 0x00, //PORTC None + 0xFF, //PORTD PD0 to PD7 + 0x3B, //PORTE PE0, PE1, PE3 to PE5 + 0x00, //PORTF None + 0x00, //PORTG None + 0x00, //PORTH None + 0x00, //PORTJ None + 0x00, //PORTK None + 0x00, //PORTL None + 0x00, //PORTM None + 0xC0, //PORTN PN6, PN7 +}; + +const uint8_t g_gpio_dscr_support[GPIO_INFO_NUM_PORTS] = +{ + 0x03, //PORT0 P00, P01 + 0x03, //PORT1 P10, P11 + 0x9F, //PORT2 P20 to P24, P27 + 0x0F, //PORT3 P30 to P33 + 0x00, //PORT4 None + 0x00, //PORT5 None + 0x00, //PORT6 None + 0x7F, //PORT7 P70 to P76 + 0x07, //PORT8 P80 to P82 + 0x7F, //PORT9 P90 to P96 + 0x3F, //PORTA PA0 to PA5 + 0xFF, //PORTB PB0 to PB7 + 0x00, //PORTC None + 0xFF, //PORTD PD0 to PD7 + 0x3B, //PORTE PE0, PE1, PE3 to PE5 + 0x00, //PORTF None + 0x00, //PORTG None + 0x00, //PORTH None + 0x00, //PORTJ None + 0x00, //PORTK None + 0x00, //PORTL None + 0x00, //PORTM None + 0x40, //PORTN PN6 +}; + +const uint8_t g_gpio_dscr2_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, //PORT0 None + 0x00, //PORT1 None + 0x00, //PORT2 None + 0x00, //PORT3 None + 0x00, //PORT4 None + 0x00, //PORT5 None + 0x00, //PORT6 None + 0x7E, //PORT7 P71 to P76 + 0x02, //PORT8 P81 + 0x3F, //PORT9 P90 to P95 + 0x00, //PORTA None + 0x20, //PORTB PB5 + 0x00, //PORTC None + 0x08, //PORTD PD3 + 0x00, //PORTE None + 0x00, //PORTF None + 0x00, //PORTG None + 0x00, //PORTH None + 0x00, //PORTJ None + 0x00, //PORTK None + 0x00, //PORTL None + 0x00, //PORTM None + 0x00, //PORTN None +}; + +#endif /* GPIO_CFG_PARAM_CHECKING_ENABLE */ + +#endif /* BSP_MCU_RX26T */ + diff --git a/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx26t/r_gpio_rx26t.h b/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx26t/r_gpio_rx26t.h new file mode 100644 index 00000000..26dd2698 --- /dev/null +++ b/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx26t/r_gpio_rx26t.h @@ -0,0 +1,487 @@ +/*********************************************************************************************************************** +* Copyright (c) 2023 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx26t.h +* Description : Specifics for the r_gpio_rx driver for the RX26T. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 07.04.2023 1.00 First Release +* : 15.03.2025 5.11 Updated disclaimer. +***********************************************************************************************************************/ +#ifndef GPIO_RX26T +#define GPIO_RX26T + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +#if defined(BSP_MCU_RX26T) /* Prevents the compiler from finding multiple definitions of constant in this file */ + +/* Configuration for this package. */ +#include "r_gpio_rx_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* General information about number of ports and pins on this device. */ +#define GPIO_INFO_NUM_PORTS (23) + +#if (BSP_PACKAGE_PINS == 100) + #define GPIO_INFO_NUM_PINS (83) +#elif (BSP_PACKAGE_PINS == 80) + #define GPIO_INFO_NUM_PINS (63) +#elif (BSP_PACKAGE_PINS == 64) + #define GPIO_INFO_NUM_PINS (50) +#elif (BSP_PACKAGE_PINS == 48) + #define GPIO_INFO_NUM_PINS (38) +#else + #error "r_gpio_rx does not have information about this RX26T package. Please update r_gpio_rx26t.h" +#endif + +/* Base registers used for offsets on output data registers. */ +#define GPIO_PRV_BASE_ADDR_OUTPUT ((uint8_t volatile *)&PORT0.PODR.BYTE) +/* Base registers used for offsets on input data registers. */ +#define GPIO_PRV_BASE_ADDR_INPUT ((uint8_t volatile *)&PORT0.PIDR.BYTE) +/* Base registers used for offsets on direction registers. */ +#define GPIO_PRV_BASE_ADDR_DIRECTION ((uint8_t volatile *)&PORT0.PDR.BYTE) +/* Base registers used for offsets on mode registers. */ +#define GPIO_PRV_BASE_ADDR_MODE ((uint8_t volatile *)&PORT0.PMR.BYTE) +/* Base registers used for offsets on output type registers. */ +#define GPIO_PRV_BASE_ADDR_OUT_TYPE ((uint8_t volatile *)&PORT0.ODR0.BYTE) +/* Base registers used for offsets on pull-up registers. */ +#define GPIO_PRV_BASE_ADDR_PULL_UP ((uint8_t volatile *)&PORT0.PCR.BYTE) +/* Base registers used for offsets on drive capacity control registers. */ +#define GPIO_PRV_BASE_ADDR_DSCR ((uint8_t volatile *)&PORT0.DSCR.BYTE) +/* Base registers used for offsets on drive capacity control registers 2. (Large current high-drive) */ +#define GPIO_PRV_BASE_ADDR_DSCR2 ((uint8_t volatile *)&PORT7.DSCR2.BYTE-7) + +#define GPIO_DSCR_IS_SUPPORTED /* High-drive is supported for the RX26T */ +#define GPIO_DSCR2_IS_SUPPORTED /* Large current output, high-drive output is supported for the RX26T */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if (BSP_PACKAGE_PINS == 100) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_8 = 0x0800, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_N = 0x1600, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0x03, /* Available pins: P00, P01 */ + GPIO_PORT1_PIN_MASK = 0x03, /* Available pins: P10, P11 */ + GPIO_PORT2_PIN_MASK = 0x9F, /* Available pins: P20 to P24, P27 */ + GPIO_PORT3_PIN_MASK = 0xCF, /* Available pins: P30 to P33, P36, P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x3F, /* Available pins: P50 to P55 */ + GPIO_PORT6_PIN_MASK = 0x3F, /* Available pins: P60 to P65 */ + GPIO_PORT7_PIN_MASK = 0x7F, /* Available pins: P70 to P76 */ + GPIO_PORT8_PIN_MASK = 0x07, /* Available pins: P80 to P82 */ + GPIO_PORT9_PIN_MASK = 0x7F, /* Available pins: P90 to P96 */ + GPIO_PORTA_PIN_MASK = 0x3F, /* Available pins: PA0 to PA5 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0x3F, /* Available pins: PE0 to PE5 */ + GPIO_PORTN_PIN_MASK = 0xC0, /* Available pins: PN6, PN7 */ +} gpio_pin_bit_mask_t; + +/* This enumerator has each available GPIO pin on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_0_PIN_1 = 0x0001, + GPIO_PORT_1_PIN_0 = 0x0100, + GPIO_PORT_1_PIN_1 = 0x0101, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_6_PIN_0 = 0x0600, + GPIO_PORT_6_PIN_1 = 0x0601, + GPIO_PORT_6_PIN_2 = 0x0602, + GPIO_PORT_6_PIN_3 = 0x0603, + GPIO_PORT_6_PIN_4 = 0x0604, + GPIO_PORT_6_PIN_5 = 0x0605, + GPIO_PORT_7_PIN_0 = 0x0700, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_8_PIN_0 = 0x0800, + GPIO_PORT_8_PIN_1 = 0x0801, + GPIO_PORT_8_PIN_2 = 0x0802, + GPIO_PORT_9_PIN_0 = 0x0900, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_9_PIN_4 = 0x0904, + GPIO_PORT_9_PIN_5 = 0x0905, + GPIO_PORT_9_PIN_6 = 0x0906, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_N_PIN_6 = 0x1606, + GPIO_PORT_N_PIN_7 = 0x1607, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 80) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_N = 0x1600, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0x03, /* Available pins: P00, P01 */ + GPIO_PORT1_PIN_MASK = 0x03, /* Available pins: P10, P11 */ + GPIO_PORT2_PIN_MASK = 0x87, /* Available pins: P20 to P22, P27 */ + GPIO_PORT3_PIN_MASK = 0xC3, /* Available pins: P30, P31, P36, P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x3F, /* Available pins: P50 to P55 */ + GPIO_PORT6_PIN_MASK = 0x31, /* Available pins: P60, P64, P65 */ + GPIO_PORT7_PIN_MASK = 0x7F, /* Available pins: P70 to P76 */ + GPIO_PORT9_PIN_MASK = 0x7F, /* Available pins: P90 to P96 */ + GPIO_PORTA_PIN_MASK = 0x28, /* Available pins: PA3, PA5 */ + GPIO_PORTB_PIN_MASK = 0x7F, /* Available pins: PB0 to PB6 */ + GPIO_PORTD_PIN_MASK = 0xFC, /* Available pins: PD2 to PD7 */ + GPIO_PORTE_PIN_MASK = 0x1C, /* Available pins: PE2 to PE4 */ + GPIO_PORTN_PIN_MASK = 0xC0, /* Available pins: PN6, PN7 */ +} gpio_pin_bit_mask_t; + +/* This enumerator has each available GPIO pin on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_0_PIN_1 = 0x0001, + GPIO_PORT_1_PIN_0 = 0x0100, + GPIO_PORT_1_PIN_1 = 0x0101, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_6_PIN_0 = 0x0600, + GPIO_PORT_6_PIN_4 = 0x0604, + GPIO_PORT_6_PIN_5 = 0x0605, + GPIO_PORT_7_PIN_0 = 0x0700, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_9_PIN_0 = 0x0900, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_9_PIN_4 = 0x0904, + GPIO_PORT_9_PIN_5 = 0x0905, + GPIO_PORT_9_PIN_6 = 0x0906, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_N_PIN_6 = 0x1606, + GPIO_PORT_N_PIN_7 = 0x1607, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 64) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_N = 0x1600, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0x03, /* Available pins: P00, P01 */ + GPIO_PORT1_PIN_MASK = 0x02, /* Available pins: P11 */ + GPIO_PORT2_PIN_MASK = 0x07, /* Available pins: P20 to P22 */ + GPIO_PORT3_PIN_MASK = 0xC0, /* Available pins: P36, P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x1C, /* Available pins: P52 to P54 */ + GPIO_PORT6_PIN_MASK = 0x30, /* Available pins: P64, P65 */ + GPIO_PORT7_PIN_MASK = 0x7F, /* Available pins: P70 to P76 */ + GPIO_PORT9_PIN_MASK = 0x7F, /* Available pins: P90 to P96 */ + GPIO_PORTB_PIN_MASK = 0x7F, /* Available pins: PB0 to PB6 */ + GPIO_PORTD_PIN_MASK = 0xF8, /* Available pins: PD3 to PD7 */ + GPIO_PORTE_PIN_MASK = 0x04, /* Available pins: PE2 */ + GPIO_PORTN_PIN_MASK = 0xC0, /* Available pins: PN6, PN7 */ +} gpio_pin_bit_mask_t; + +/* This enumerator has each available GPIO pin on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_0_PIN_1 = 0x0001, + GPIO_PORT_1_PIN_1 = 0x0101, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_6_PIN_4 = 0x0604, + GPIO_PORT_6_PIN_5 = 0x0605, + GPIO_PORT_7_PIN_0 = 0x0700, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_9_PIN_0 = 0x0900, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_9_PIN_4 = 0x0904, + GPIO_PORT_9_PIN_5 = 0x0905, + GPIO_PORT_9_PIN_6 = 0x0906, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_N_PIN_6 = 0x1606, + GPIO_PORT_N_PIN_7 = 0x1607, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 48) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_6 = 0x0600, + GPIO_PORT_7 = 0x0700, + GPIO_PORT_9 = 0x0900, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_N = 0x1600, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0x01, /* Available pins: P00 */ + GPIO_PORT1_PIN_MASK = 0x03, /* Available pins: P10, P11 */ + GPIO_PORT2_PIN_MASK = 0x03, /* Available pins: P20, P21 */ + GPIO_PORT3_PIN_MASK = 0xC0, /* Available pins: P36, P37 */ + GPIO_PORT4_PIN_MASK = 0x1F, /* Available pins: P40 to P44 */ + GPIO_PORT5_PIN_MASK = 0x0C, /* Available pins: P52, P53 */ + GPIO_PORT6_PIN_MASK = 0x04, /* Available pins: P62 */ + GPIO_PORT7_PIN_MASK = 0x7E, /* Available pins: P71 to P76 */ + GPIO_PORT9_PIN_MASK = 0x3E, /* Available pins: P91 to P95 */ + GPIO_PORTB_PIN_MASK = 0x7F, /* Available pins: PB0 to PB6 */ + GPIO_PORTD_PIN_MASK = 0xA8, /* Available pins: PD3, PD5, PD7 */ + GPIO_PORTE_PIN_MASK = 0x04, /* Available pins: PE2 */ + GPIO_PORTN_PIN_MASK = 0x40, /* Available pins: PN6 */ +} gpio_pin_bit_mask_t; + +/* This enumerator has each available GPIO pin on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0_PIN_0 = 0x0000, + GPIO_PORT_1_PIN_0 = 0x0100, + GPIO_PORT_1_PIN_1 = 0x0101, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_6_PIN_2 = 0x0602, + GPIO_PORT_7_PIN_1 = 0x0701, + GPIO_PORT_7_PIN_2 = 0x0702, + GPIO_PORT_7_PIN_3 = 0x0703, + GPIO_PORT_7_PIN_4 = 0x0704, + GPIO_PORT_7_PIN_5 = 0x0705, + GPIO_PORT_7_PIN_6 = 0x0706, + GPIO_PORT_9_PIN_1 = 0x0901, + GPIO_PORT_9_PIN_2 = 0x0902, + GPIO_PORT_9_PIN_3 = 0x0903, + GPIO_PORT_9_PIN_4 = 0x0904, + GPIO_PORT_9_PIN_5 = 0x0905, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_N_PIN_6 = 0x1606, +} gpio_port_pin_t; +#endif + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* BSP_MCU_RX26T */ +#endif /* GPIO_RX26T */ diff --git a/drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t.c b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t.c new file mode 100644 index 00000000..a3866bc3 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t.c @@ -0,0 +1,1286 @@ +/*********************************************************************************************************************** +* Copyright (c) 2023 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx26t.c +* Description : Functions for using SCI on the RX26T device. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 31.03.2023 1.00 Initial Release. +* 28.06.2024 5.30 Corrected the typecasting formula in sci_init_bit_rate(). +* 01.11.2024 5.40 Fixed the issue that data cannot be sent when using the SCI_CMD_TX_Q_FLUSH command +* with the R_SCI_Control() function before executing the R_SCI_Send() function. +* 15.03.2025 5.41 Updated disclaimer +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +#include "r_sci_rx26t_private.h" + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/***************************************************************************** +* Function Name: sci_mcu_param_check +* Description : This function parameters check on MCU. +* (channel range, interrupt priority, etc...) +* Arguments : chan - +* channel to check +* Return Value : SCI_SUCCESS - +* parameter check all successfully +* SCI_ERR_BAD_CHAN - +* channel number invalid for part +* SCI_ERR_INVALID_ARG - +* interrupt priority out of range +******************************************************************************/ +sci_err_t sci_mcu_param_check(uint8_t const chan) +{ + /* channel range parameter check */ + if ((SCI_CH1 != chan) && (SCI_CH5 != chan) && (SCI_CH6 != chan) && (SCI_CH12 != chan)) + { + return SCI_ERR_BAD_CHAN; + } + + /* interrupt priority configuration parameter check */ + if ((1 > SCI_CFG_ERI_TEI_PRIORITY) || (15 < SCI_CFG_ERI_TEI_PRIORITY)) + { + return SCI_ERR_INVALID_ARG; + } + + return SCI_SUCCESS; +} /* End of function sci_mcu_param_check() */ + +/***************************************************************************** +* Function Name: sci_init_register +* Description : This function initializes the register for SCI. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void sci_init_register(sci_hdl_t const hdl) +{ + /* SCI transmit enable bit and receive enable bit check & disable */ + /* WAIT_LOOP */ + while ((0 != hdl->rom->regs->SCR.BIT.TE) || (0 != hdl->rom->regs->SCR.BIT.RE)) + { + if (0 != hdl->rom->regs->SCR.BIT.TE) + { + hdl->rom->regs->SCR.BIT.TE = 0; // transmit disable + } + + if (0 != hdl->rom->regs->SCR.BIT.RE) + { + hdl->rom->regs->SCR.BIT.RE = 0; // receive disable + } + } + + /* SMR register initialize */ + hdl->rom->regs->SMR.BYTE = 0x00; + + /* SCR register initialize */ + hdl->rom->regs->SCR.BYTE = 0x00; + + /* SSR register initialize */ + if (1 == SCI_SSR_ORER) + { + SCI_SSR_ORER = 0; + } + + if (1 == SCI_SSR_PER) + { + SCI_SSR_PER = 0; + } + + if (1 == SCI_SSR_FER) + { + SCI_SSR_FER = 0; + } + + /* SCMR register initialize */ + hdl->rom->regs->SCMR.BIT.SMIF = 0; + hdl->rom->regs->SCMR.BIT.SINV = 0; + hdl->rom->regs->SCMR.BIT.SDIR = 0; + + /* SPTR register initialize */ + hdl->rom->regs->SPTR.BIT.SPB2DT = 0; + hdl->rom->regs->SPTR.BIT.SPB2IO = 0; + hdl->rom->regs->SPTR.BIT.RTADJ = 0; + hdl->rom->regs->SPTR.BIT.TTADJ = 0; + hdl->rom->regs->SPTR.BIT.RINV = 0; + hdl->rom->regs->SPTR.BIT.TINV = 0; + + /* TMGR register initialize */ + hdl->rom->regs->TMGR.BIT.RTMG = 0; + hdl->rom->regs->TMGR.BIT.TTMG = 0; + + /* BRR register initialize */ + hdl->rom->regs->BRR = 0xFF; + + /* SEMR register initialize */ + hdl->rom->regs->SEMR.BIT.BRME = 0; + hdl->rom->regs->SEMR.BIT.ABCS = 0; + hdl->rom->regs->SEMR.BIT.ABCSE = 0; + hdl->rom->regs->SEMR.BIT.NFEN = 0; + hdl->rom->regs->SEMR.BIT.BGDM = 0; + hdl->rom->regs->SEMR.BIT.RXDESEL = 0; + + /* SNFR register initialize */ + hdl->rom->regs->SNFR.BYTE = 0; + + /* SPMR register initialize */ + hdl->rom->regs->SPMR.BIT.CTSE = 0; + hdl->rom->regs->SPMR.BIT.CKPOL = 0; + hdl->rom->regs->SPMR.BIT.CKPH = 0; + + #if SCI_CFG_DATA_MATCH_INCLUDED + /* DCCR register initialize */ + hdl->rom->regs->DCCR.BIT.DCME = 0; + hdl->rom->regs->DCCR.BIT.DCMF = 0; + hdl->rom->regs->DCCR.BIT.DFER = 0; + hdl->rom->regs->DCCR.BIT.DPER = 0; + hdl->rom->regs->DCCR.BIT.IDSEL = 0; + + /* CDR register initialize */ + hdl->rom->regs->CDR.BYTE.L = 0; + + /* Set initial value of receive in 8-bit data length */ + hdl->rom->regs->SMR.BIT.CHR = 0; + hdl->rom->regs->SCMR.BIT.CHR1 = 1; + #endif /* End of SCI_CFG_DATA_MATCH_INCLUDED */ + + return; +} /* End of function sci_init_register() */ + +/***************************************************************************** +* Function Name: sci_init_bit_rate +* Description : This function determines the best possible settings for the +* baud rate registers for the specified peripheral clock speed +* and baud rate. Note that this does not guarantee a low bit +* error rate, just the best possible one. The bit rate error is +* returned in .1% increments. If the hardware cannot support +* the specified combination, a value of 1000 (100% error) is +* returned. +* +* NOTE: The transmitter and receiver (TE and RE bits in SCR) must be disabled +* prior to calling this function. +* +* The application must pause for 1 bit time after the BRR register +* is loaded before transmitting/receiving to allow time for the clock +* to settle. +* +* Arguments : hdl - +* Handle for channel (ptr to chan control block) +* NOTE: mode element must be already set +* pclk - +* Peripheral clock speed; e.g. 24000000 for 24MHz +* baud - +* Baud rate; 19200, 57600, 115200, etc. +* Return Value : bit error in .1% increments; e.g. 16 = 1.6% bit rate error +* a value of 1000 denotes 100% error; no registers set +******************************************************************************/ +int32_t sci_init_bit_rate(sci_hdl_t const hdl, + uint32_t const pclk, + uint32_t const baud) +{ + uint32_t i; + uint32_t num_divisors = 0; + uint32_t ratio; + uint32_t tmp; + baud_divisor_t const *p_baud_info = NULL; + + uint32_t divisor; + uint32_t int_M; + float float_M; + float error; + float abs_error; + + #if SCI_CFG_PARAM_CHECKING_ENABLE + if ((0 == pclk) || (0 == baud)) + { + return 1000; + } + #endif /* End of SCI_CFG_PARAM_CHECKING_ENABLE */ + + /* SELECT PROPER TABLE BASED UPON MODE */ + if (SCI_MODE_ASYNC == hdl->mode) + { + #if (SCI_CFG_ASYNC_INCLUDED) + p_baud_info = async_baud; + num_divisors = NUM_DIVISORS_ASYNC; + #endif /* End of SCI_CFG_ASYNC_INCLUDED */ + } + else + { + /* SYNC or SSPI */ + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + p_baud_info = sync_baud; + num_divisors = NUM_DIVISORS_SYNC; + #endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + } + + /* FIND DIVISOR; table has associated ABCS, BGDM, ABCSE and CKS values */ + /* BRR must be 255 or less */ + /* the "- 1" is ignored in some steps for approximations */ + /* BRR = (PCLK/(divisor * baud)) - 1 */ + /* BRR = (ratio / divisor) - 1 */ + ratio = pclk / baud; + + /* WAIT_LOOP */ + for(i = 0; i < num_divisors; i++) + { + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* ABCSE bit is not available on CH12 */ + /* Skip divisor result have ABCSE bit*/ + if (SCI_CH12 == hdl->rom->chan) + { + if(1 == p_baud_info[i].abcse) + { + continue; + } + } +#endif + } + /* Casting int16_t to uint32_t is valid. Because clock divisor is positive integer */ + if (ratio < (uint32_t)(p_baud_info[i].divisor * 256)) + { + break; + } + } + + /* RETURN IF BRR WILL BE >255 OR LESS THAN 0 */ + if (i == num_divisors) + { + return(1000); // impossible baud rate requested; return 100% error + } + + /* Casting int16_t to uint32_t is valid. Because clock divisor is a positive integer */ + divisor = (uint32_t)p_baud_info[i].divisor; + tmp = ratio / (divisor); // tmp = PCLK/(baud * divisor) = BRR+1 = N+1 + if (0 == tmp) + { + return (1000); // illegal value; return 100% error + } + + /* SET BRR, ABCS, BDGM, and CKS */ + tmp = ratio / (divisor / 2); // divide by half the divisor + + /* if odd, "round up" by ignoring -1; divide by 2 again for rest of divisor */ + hdl->rom->regs->BRR = (uint8_t)((tmp & 0x01) ? (tmp / 2) : ((tmp / 2) - 1)); + hdl->rom->regs->SEMR.BIT.ABCS = p_baud_info[i].abcs; + hdl->rom->regs->SEMR.BIT.BGDM = p_baud_info[i].bgdm; + hdl->rom->regs->SMR.BIT.CKS = p_baud_info[i].cks; + hdl->rom->regs->SEMR.BIT.ABCSE = p_baud_info[i].abcse; + + /* CALCULATE BIT RATE ERROR. + * RETURN IF ERROR LESS THAN 1% OR IF IN SYNCHRONOUS/SSPI MODE. + */ + tmp = ratio / (divisor); // tmp = PCLK/(baud * divisor) = BRR+1 = N+1 + + /* Casting uint32_t to float is valid */ + error = (((float)pclk / ((baud * divisor) * tmp)) - 1) * 100; + abs_error = (error < 0) ? (-error) : error; + + if ((abs_error <= 1.0f) || (SCI_MODE_ASYNC != hdl->mode)) + { + hdl->rom->regs->SEMR.BIT.BRME = 0; // disable MDDR + + /* Casting float to uint32_t */ + return (uint32_t)(error*10); + } + + /* CALCULATE M ASSUMING A 0% ERROR then WRITE REGISTER */ + hdl->rom->regs->BRR = (uint8_t)(tmp - 1); + + /* Casting uint32_t to float is valid */ + float_M = ((((float)baud * divisor) * 256) * tmp) / pclk; + float_M *= 2; + + /* Casting float to uint32_t */ + int_M = (uint32_t)float_M; + int_M = (int_M & 0x01) ? ((int_M / 2) + 1) : (int_M / 2); + + /* Casting uint32_t type to uint8_t type in this case is valid. Range value of m is not exceed uint8_t */ + hdl->rom->regs->MDDR = (uint8_t)int_M; // write M + hdl->rom->regs->SEMR.BIT.BRME = 1; // enable MDDR + + /* Casting uint32_t to float is valid*/ + error = (((float)(pclk) / (((divisor * tmp) * baud) * ((float)(256)/int_M))) - 1) * 100; + + /* Casting float to int32_t */ + return (int32_t)(error*10); +} /* End of function sci_init_bit_rate() */ + +/***************************************************************************** +* Function Name: sci_initialize_ints +* Description : This function sets priority, clears flags, and sets +* interrupts in both the ICU and SCI peripheral. These include +* RXI, TXI, TEI, and ERI/GROUP12 interrupts. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* priority - +* priority for interrupts +* Return Value : none +******************************************************************************/ +void sci_initialize_ints(sci_hdl_t const hdl, + uint8_t const priority) +{ + volatile bsp_int_ctrl_t group_priority; + + /* SET PRIORITY FOR INTERRUPTS */ + *hdl->rom->ipr_rxi = priority; // can set separately using Control() + *hdl->rom->ipr_txi = priority; + + group_priority.ipl = 0x00000000; + + /* Check interrupt priority */ + if (SCI_CFG_ERI_TEI_PRIORITY > IPR(ICU, GROUPBL0)) + { + /* Casting a positive integer to uint32_t is valid */ + group_priority.ipl = (uint32_t)SCI_CFG_ERI_TEI_PRIORITY; + } + + /* DISABLE ERI INTERRUPT */ + DISABLE_ERI_INT; + + /* DISABLE RXI INTERRUPT */ + DISABLE_RXI_INT; + + /* DISABLE TXI INTERRUPT */ + DISABLE_TXI_INT; + + /* DISABLE TEI INTERRUPT */ + DISABLE_TEI_INT; + + /* CLEAR INTERRUPT FLAGS */ + *hdl->rom->ir_rxi = 0; + *hdl->rom->ir_txi = 0; + DISABLE_TEI_INT; + DISABLE_ERI_INT; + + /* REGISTER GROUP INTERRUPTS WITH BSP */ + #if SCI_CFG_TEI_INCLUDED + R_BSP_InterruptWrite(hdl->rom->tei_vector, hdl->rom->tei_isr); + #endif + R_BSP_InterruptWrite(hdl->rom->eri_vector, hdl->rom->eri_isr); + + /* ENABLE GROUP INTERRUPTS */ + R_BSP_InterruptControl(hdl->rom->eri_vector, BSP_INT_CMD_GROUP_INTERRUPT_ENABLE, (void *)&group_priority); + + /* ENABLE ERI AND RXI INTERRUPTS REQUESTS */ + ENABLE_ERI_INT; + ENABLE_RXI_INT; + + /* ENABLE INTERRUPTS IN SCI PERIPHERAL */ + /* Note: Enable interrupts after xcvr or will get "extra" interrupt */ + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; // enable TE, RE, TXI, and RXI/ERI + + return; +} /* End of function sci_initialize_ints() */ + +/***************************************************************************** +* Function Name: sci_disable_ints +* Description : This function disable interrupts in both the ICU and SCI +* peripheral. These include RXI, TXI, TEI, ERI, and group +* interrupts. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void sci_disable_ints(sci_hdl_t const hdl) +{ + volatile bsp_int_ctrl_t group_priority; + + /* Disable ICU RXI interrupt */ + DISABLE_RXI_INT; + + /* Disable ICU TXI interrupt */ + DISABLE_TXI_INT; + + /* Disable ICU ERI interrupt */ + DISABLE_ERI_INT; + + /* Disable ICU TEI interrupt */ + DISABLE_TEI_INT; + + /* disable peripheral interrupts and xcvr (TE and RE) */ + hdl->rom->regs->SCR.BYTE = 0; + + /* disable group interrupts */ + group_priority.ipl = 0x00000000; + + /* Casting pointer to void* is valid */ + R_BSP_InterruptControl(hdl->rom->eri_vector, BSP_INT_CMD_GROUP_INTERRUPT_DISABLE, (void *)&group_priority); + + return; +} /* End of function sci_disable_ints() */ + + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_async_cmds +* Description : This function configures non-standard UART hardware and +* performs special software operations. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* cmd - +* command to run +* p_args - +* pointer argument(s) specific to command +* Return Value : SCI_SUCCESS - +* Command completed successfully. +* SCI_ERR_NULL_PTR - +* p_args is NULL when required for cmd +* SCI_ERR_INVALID_ARG - +* The cmd value or p_args contains an invalid value. +******************************************************************************/ +sci_err_t sci_async_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_err_t err=SCI_SUCCESS; + int32_t bit_err; + uint32_t slow_baud; + + #if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check parameters */ + if (((NULL == p_args) || (FIT_NO_PTR == p_args)) + && ((SCI_CMD_TX_Q_BYTES_FREE == cmd) || (SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ == cmd) || (SCI_CMD_COMPARE_RECEIVED_DATA == cmd))) + { + return SCI_ERR_NULL_PTR; + } + #endif /* End of SCI_CFG_PARAM_CHECKING_ENABLE */ + + switch (cmd) + { + case (SCI_CMD_EN_NOISE_CANCEL): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SEMR.BIT.NFEN = 1; /* enable noise filter */ + hdl->rom->regs->SNFR.BYTE = 0; /* clock divided by 1 (default) */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_OUTPUT_BAUD_CLK): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCR.BIT.CKE = 0x01; /* output baud clock on SCK pin */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_START_BIT_EDGE): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SEMR.BIT.RXDESEL = 1; /* detect start bit on falling edge */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + #if SCI_CFG_TEI_INCLUDED + case (SCI_CMD_EN_TEI): /* SCI_CMD_EN_TEI is obsolete command, but it exists only for compatibility with older version. */ + { + break; + } + #endif /* End of SCI_CFG_TEI_INCLUDED */ + + #if TX_DTC_DMACA_ENABLE + case (SCI_CMD_CHECK_TX_DONE): + { + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable)) + { + if (false == hdl->tx_idle) + { + err = SCI_ERR_XCVR_BUSY; + } + } + break; + } + #endif /* End of TX_DTC_DMACA_ENABLE */ + + #if RX_DTC_DMACA_ENABLE + case (SCI_CMD_CHECK_RX_DONE): + { + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + if (0 != hdl->queue[0].rx_cnt) + { + err = SCI_ERR_XCVR_BUSY; + } + } + break; + } + #endif /* End of RX_DTC_DMACA_ENABLE */ + + case (SCI_CMD_TX_Q_FLUSH): + { + #if (SCI_CFG_USE_CIRCULAR_BUFFER == 1) + R_BYTEQ_Flush(hdl->u_tx_data.que); + #else + /* Disable TXI interrupt */ + DISABLE_TXI_INT; + R_BYTEQ_Flush(hdl->u_tx_data.que); + ENABLE_TXI_INT; + + /* Re-enable interrupts */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + #endif /*End of SCI_CFG_USE_CIRCULAR_BUFFER == 1 */ + break; + } + + case (SCI_CMD_RX_Q_FLUSH): + { + #if (SCI_CFG_USE_CIRCULAR_BUFFER == 1) + R_BYTEQ_Flush(hdl->u_rx_data.que); + #else + /* Disable RXI interrupt */ + DISABLE_RXI_INT; + R_BYTEQ_Flush(hdl->u_rx_data.que); + ENABLE_RXI_INT; + #endif /*End of SCI_CFG_USE_CIRCULAR_BUFFER == 1 */ + break; + } + + case (SCI_CMD_TX_Q_BYTES_FREE): + { + /* Casting pointer void* to uint16_t* type is valid */ + R_BYTEQ_Unused(hdl->u_tx_data.que, (uint16_t *) p_args); + break; + } + + case (SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ): + { + /* Casting pointer void* type to uint16_t* type is valid */ + R_BYTEQ_Used(hdl->u_rx_data.que, (uint16_t *) p_args); + break; + } + + case (SCI_CMD_GENERATE_BREAK): + { + /* flush transmit queue */ + DISABLE_TXI_INT; + R_BYTEQ_Flush(hdl->u_tx_data.que); + + #if(TX_DTC_DMACA_ENABLE) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable)) + { + sci_fifo_ctrl_t *p_tctrl = &hdl->queue[hdl->qindex_app_rx]; + p_tctrl->tx_cnt = 0; + p_tctrl->tx_fraction = 0; + + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + if(SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + dtc_cmd_arg_t args_dtc; + args_dtc.act_src = hdl->rom->dtc_tx_act_src; + R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &args_dtc); + } + #endif /* End of (TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)*/ + + #if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + if(SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + dmaca_stat_t stat_dmaca; + R_DMACA_Control(hdl->rom->dmaca_tx_channel, DMACA_CMD_DISABLE, &stat_dmaca); + } + #endif /* End of (TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)*/ + } + #endif /* End of TX_DTC_DMACA_ENABLE*/ + + ENABLE_TXI_INT; + + /* NOTE: the following steps will abort anything being sent */ + + /* set baud rate 1.5x slower */ + slow_baud = (hdl->baud_rate << 1) / 3; + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, slow_baud); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; + } + else + { + /* transmit "0" and wait for completion */ + SCI_TDR(0); + + /* WAIT_LOOP */ + while (0 == hdl->rom->regs->SSR.BIT.TEND) + { + R_BSP_NOP(); + } + + /* restore original baud rate */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + sci_init_bit_rate(hdl, hdl->pclk_speed, hdl->baud_rate); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + break; + } + + #if SCI_CFG_DATA_MATCH_INCLUDED + case SCI_CMD_COMPARE_RECEIVED_DATA: + { + hdl->rom->regs->DCCR.BIT.DFER = 0; /* Clear Match Data Framing Error Flag */ + hdl->rom->regs->DCCR.BIT.DPER = 0; /* Clear Match Data Parity Error Flag */ + hdl->rom->regs->DCCR.BIT.DCME = 1; /* Enable Data match function */ + hdl->rom->regs->CDR.BYTE.L = *((unsigned char *)p_args); /* Comparison data */ + break; + } + #endif /* End of SCI_CFG_DATA_MATCH_INCLUDED */ + + /* Enable receive data sampling timing adjust feature*/ + case SCI_CMD_RX_SAMPLING_ENABLE: + { + hdl->rom->regs->SPTR.BIT.RTADJ = 1; + break; + } + + /* Disable receive data sampling timing adjust feature*/ + case SCI_CMD_RX_SAMPLING_DISABLE: + { + hdl->rom->regs->SPTR.BIT.RTADJ = 0; + break; + } + + /* Enable transmit signal transition timing adjust feature*/ + case SCI_CMD_TX_TRANSITION_TIMING_ENABLE: + { + hdl->rom->regs->SPTR.BIT.TTADJ = 1; + break; + } + + /* Disable transmit signal transition timing adjust feature*/ + case SCI_CMD_TX_TRANSITION_TIMING_DISABLE: + { + hdl->rom->regs->SPTR.BIT.TTADJ = 0; + break; + } + + /* Set value for receive data sampling timing adjust feature*/ + case SCI_CMD_SAMPLING_TIMING_ADJUST: + { + if ((0 == hdl->rom->regs->SEMR.BIT.ABCSE) && (0 == hdl->rom->regs->SEMR.BIT.ABCS)) + { + /* Casting pointer void* to uint8_t* type is valid */ + if ((*(uint8_t *)p_args) <= 15) + { + if (1 == hdl->rom->regs->SPTR.BIT.RTADJ) + { + /* Casting pointer void* to uint8_t* type is valid */ + hdl->rom->regs->TMGR.BIT.RTMG = *(uint8_t *)p_args; + } + } + else + { + err = SCI_ERR_INVALID_ARG; + } + } + else if ((0 == hdl->rom->regs->SEMR.BIT.ABCSE) && (1 == hdl->rom->regs->SEMR.BIT.ABCS)) + { + /* Casting pointer void* to uint8_t* type is valid */ + if (((*(uint8_t *)p_args) <= 3) || ((8 <= (*(uint8_t *)p_args)) && ((*(uint8_t *)p_args) <= 11))) + { + if (1 == hdl->rom->regs->SPTR.BIT.RTADJ) + { + /* Casting pointer void* to uint8_t* type is valid */ + hdl->rom->regs->TMGR.BIT.RTMG = *(uint8_t *)p_args; + } + } + else + { + err = SCI_ERR_INVALID_ARG; + } + } + else + { + /* Casting pointer void* to uint8_t* type is valid */ + if (((*(uint8_t *)p_args) <= 2) || ((8 <= (*(uint8_t *)p_args)) && ((*(uint8_t *)p_args) <= 10))) + { + if (1 == hdl->rom->regs->SPTR.BIT.RTADJ) + { + /* Casting pointer void* to uint8_t* type is valid */ + hdl->rom->regs->TMGR.BIT.RTMG = *(uint8_t *)p_args; + } + } + else + { + err = SCI_ERR_INVALID_ARG; + } + } + break; + } + + /*Set va transmit signal transition timing adjust feature*/ + case SCI_CMD_TRANSITION_TIMING_ADJUST: + { + if (0 == hdl->rom->regs->SEMR.BIT.ABCSE) + { + /* Casting pointer void* to uint8_t* type is valid */ + if ((*(uint8_t *)p_args) <= 15) + { + if (1 == hdl->rom->regs->SPTR.BIT.TTADJ) + { + /* Casting pointer void* to uint8_t* type is valid */ + hdl->rom->regs->TMGR.BIT.TTMG = *(uint8_t *)p_args; + } + } + else + { + err = SCI_ERR_INVALID_ARG; + } + } + else + { + /* Casting pointer void* to uint8_t* type is valid */ + if (((*(uint8_t *)p_args) <= 5) || ((8 <= (*(uint8_t *)p_args)) && ((*(uint8_t *)p_args) <= 13))) + { + if (1 == hdl->rom->regs->SPTR.BIT.TTADJ) + { + /* Casting pointer void* to uint8_t* type is valid */ + hdl->rom->regs->TMGR.BIT.TTMG = *(uint8_t *)p_args; + } + } + else + { + err = SCI_ERR_INVALID_ARG; + } + } + break; + } + + default: + { + err = SCI_ERR_INVALID_ARG; + break; + } + } + + return err; +} /* End of function sci_async_cmds() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_sync_cmds +* Description : This function performs special software operations specific +* to the SSPI and SYNC protocols. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* cmd - +* command to run +* p_args - +* pointer argument(s) specific to command +* Return Value : SCI_SUCCESS - +* Command completed successfully. +* SCI_ERR_NULL_PTR - +* p_args is NULL when required for cmd +* SCI_ERR_INVALID_ARG - +* The cmd value or p_args contains an invalid value. +* May be due to mode channel is operating in. +******************************************************************************/ +sci_err_t sci_sync_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_spi_mode_t spi_mode; + sci_cb_args_t args; + sci_err_t err = SCI_SUCCESS; + + switch (cmd) + { + case (SCI_CMD_CHECK_XFER_DONE): + { + if (false == hdl->tx_idle) + { + err = SCI_ERR_XFER_NOT_DONE; + } + break; + } + + case (SCI_CMD_XFER_LSB_FIRST): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SDIR = 0; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_XFER_MSB_FIRST): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SDIR = 1; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_INVERT_DATA): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SINV ^= 1; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_ABORT_XFER): + { + /* Disable receive interrupts in ICU and peripheral */ + DISABLE_RXI_INT; + DISABLE_ERI_INT; + + #if(TX_DTC_DMACA_ENABLE) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable)) + { + sci_fifo_ctrl_t *p_tctrl = &hdl->queue[hdl->qindex_app_rx]; + p_tctrl->tx_cnt = 0; + p_tctrl->tx_fraction = 0; + + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) && (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + // Set condition for reset TDFR to generate interrupt in next time + hdl->qindex_int_tx = 1; + dtc_cmd_arg_t args_dtc; + args_dtc.act_src = hdl->rom->dtc_tx_act_src; + R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &args_dtc); + + args_dtc.act_src = hdl->rom->dtc_rx_act_src; + R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &args_dtc); + } + #endif + + #if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + if((SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) && (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + R_DMACA_Close(hdl->rom->dmaca_tx_channel); + R_DMACA_Close(hdl->rom->dmaca_rx_channel); + } + #endif + } + #endif + + hdl->rom->regs->SCR.BYTE &= (~(SCI_SCR_REI_MASK | SCI_SCR_RE_MASK | SCI_SCR_TE_MASK)); + + hdl->tx_cnt = 0; + hdl->tx_dummy = false; + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_ABORTED; + + /* Casting pointer to void* is valid */ + hdl->callback((void *)&args); + } + + *hdl->rom->ir_rxi = 0; /* clear rxi interrupt flag */ + + DISABLE_ERI_INT; /* clear eri interrupt flag */ + ENABLE_ERI_INT; /* enable rx err interrupts in ICU */ + ENABLE_RXI_INT; /* enable receive interrupts in ICU */ + + /* Enable receive interrupt in peripheral after rcvr or will get "extra" interrupt */ + hdl->rom->regs->SCR.BYTE |= (SCI_SCR_RE_MASK | SCI_SCR_TE_MASK); + hdl->rom->regs->SCR.BYTE |= SCI_SCR_REI_MASK; + break; + } + + #if RX_DTC_DMACA_ENABLE + case (SCI_CMD_CHECK_RX_SYNC_DONE): + { + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + if (0 != hdl->queue[0].rx_cnt) + { + err = SCI_ERR_XCVR_BUSY; + } + } + break; + } + #endif + + case (SCI_CMD_CHANGE_SPI_MODE): + { + #if SCI_CFG_PARAM_CHECKING_ENABLE + if (SCI_MODE_SSPI != hdl->mode) + { + return SCI_ERR_INVALID_ARG; + } + + /* Check parameters */ + if ((NULL == p_args ) || (FIT_NO_PTR == p_args)) + { + return SCI_ERR_NULL_PTR; + } + + /* Casting pointer void* type is valid */ + spi_mode = *((sci_spi_mode_t *)p_args); + + if ((SCI_SPI_MODE_0 != spi_mode) && (SCI_SPI_MODE_1 != spi_mode) + && (SCI_SPI_MODE_2 != spi_mode) && (SCI_SPI_MODE_3 != spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + #endif + + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SPMR.BYTE &= 0x3F; /* clear previous mode */ + hdl->rom->regs->SPMR.BYTE |= (*((uint8_t *)p_args)); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + default: + { + err = SCI_ERR_INVALID_ARG; + break; + } + } + + return err; +} /* End of function sci_sync_cmds() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +/***************************************************************************** +ISRs +******************************************************************************/ + + +#if ((SCI_CFG_ASYNC_INCLUDED) || (TX_DTC_DMACA_ENABLE | RX_DTC_DMACA_ENABLE)) + +/***************************************************************************** +* sciN_txiN_isr +* Description : TXI interrupt routines for every SCI channel +******************************************************************************/ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_txi1_isr + * Description : TXI interrupt routines for SCI1 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_txi1_isr, VECT(SCI1,TXI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_txi1_isr(void) +{ +#if SCI_CFG_CH1_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch1_ctrl); +} /* End of function sci1_txi1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED  */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_txi5_isr + * Description : TXI interrupt routines for SCI5 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_txi5_isr, VECT(SCI5,TXI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_txi5_isr(void) +{ +#if SCI_CFG_CH5_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch5_ctrl); +} /* End of function sci5_txi5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED  */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_txi6_isr + * Description : TXI interrupt routines for SCI6 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_txi6_isr, VECT(SCI6,TXI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_txi6_isr(void) +{ +#if SCI_CFG_CH6_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch6_ctrl); +} /* End of function sci6_txi6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED  */ + +#if SCI_CFG_CH12_INCLUDED +/******************************************************************************* + * Function Name: sci12_txi12_isr + * Description : TXI interrupt routines for SCI12 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_txi12_isr, VECT(SCI12,TXI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_txi12_isr(void) +{ +#if SCI_CFG_CH12_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch12_ctrl); +} /* End of function sci12_txi12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED  */ + +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if SCI_CFG_TEI_INCLUDED +/***************************************************************************** +* sciN_teiN_isr +* +* Description : TEI interrupt routines for every SCI channel. +* BSP gets main group interrupt, then vectors to/calls these +* "interrupts"/callbacks. +******************************************************************************/ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_tei1_isr + * Description : TEI interrupt routines for SCI1 channel. + ******************************************************************************/ +void sci1_tei1_isr(void *cb_args) +{ +#if SCI_CFG_CH1_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch1_ctrl); +} /* End of function sci1_tei1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_tei5_isr + * Description : TEI interrupt routines for SCI5 channel. + ******************************************************************************/ +void sci5_tei5_isr(void *cb_args) +{ +#if SCI_CFG_CH5_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch5_ctrl); +} /* End of function sci5_tei5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_tei6_isr + * Description : TEI interrupt routines for SCI6 channel. + ******************************************************************************/ +void sci6_tei6_isr(void *cb_args) +{ +#if SCI_CFG_CH6_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch6_ctrl); +} /* End of function sci6_tei6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/***************************************************************************** +* Function Name: sci12_tei12_isr +* Description : TEI interrupt routines for SCI12 channel. +******************************************************************************/ +void sci12_tei12_isr(void *cb_args) +{ +#if SCI_CFG_CH12_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch12_ctrl); +} /* End of function sci12_tei12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ + +#endif /* SCI_CFG_TEI_INCLUDED */ + +/***************************************************************************** +* sciN_rxiN_isr +* Description : RXI interrupt routines for every SCI channel +******************************************************************************/ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_rxi1_isr + * Description : RXI interrupt routines for SCI1 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_rxi1_isr, VECT(SCI1,RXI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_rxi1_isr(void) +{ +#if SCI_CFG_CH1_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch1_ctrl); +} /* End of function sci1_rxi1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_rxi5_isr + * Description : RXI interrupt routines for SCI5 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_rxi5_isr, VECT(SCI5,RXI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_rxi5_isr(void) +{ +#if SCI_CFG_CH5_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch5_ctrl); +} /* End of function sci5_rxi5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_rxi6_isr + * Description : RXI interrupt routines for SCI6 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_rxi6_isr, VECT(SCI6,RXI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_rxi6_isr(void) +{ +#if SCI_CFG_CH6_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch6_ctrl); +} /* End of function sci6_rxi6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/******************************************************************************* + * Function Name: sci12_rxi12_isr + * Description : RXI interrupt routines for SCI12 channel + ******************************************************************************/ +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_rxi12_isr, VECT(SCI12,RXI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_rxi12_isr(void) +{ +#if SCI_CFG_CH12_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch12_ctrl); +} /* End of function sci12_rxi12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ + +/***************************************************************************** +* sciN_eriN_isr +* +* Description : ERI interrupt routines for every SCI channel. +* BSP gets main group interrupt, then vectors to/calls these +* "interrupts"/callbacks. +******************************************************************************/ + +#if SCI_CFG_CH1_INCLUDED +/***************************************************************************** +* Function name: sci1_eri1_isr +* Description : ERI interrupt routines for SCI1 channel. +******************************************************************************/ +void sci1_eri1_isr(void *cb_args) +{ +#if SCI_CFG_CH1_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch1_ctrl); +} /* End of function sci1_eri1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/***************************************************************************** +* Function name: sci5_eri5_isr +* Description : ERI interrupt routines for SCI5 channel. +******************************************************************************/ +void sci5_eri5_isr(void *cb_args) +{ +#if SCI_CFG_CH5_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch5_ctrl); +} /* End of function sci5_eri5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/***************************************************************************** +* Function name: sci6_eri6_isr +* Description : ERI interrupt routines for SCI6 channel. +******************************************************************************/ +void sci6_eri6_isr(void *cb_args) +{ +#if SCI_CFG_CH6_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch6_ctrl); +} /* End of function sci6_eri6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/***************************************************************************** +* Function name: sci12_eri12_isr +* Description : ERI interrupt routines for SCI12 channel. +******************************************************************************/ +void sci12_eri12_isr(void *cb_args) +{ +#if SCI_CFG_CH12_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch12_ctrl); +} /* End of function sci12_eri12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ diff --git a/drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t_data.c b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t_data.c new file mode 100644 index 00000000..168f75b1 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t_data.c @@ -0,0 +1,326 @@ +/*********************************************************************************************************************** +* Copyright (c) 2023 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx26t_data.c +* Description : Functions for using SCI on the RX26T device. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 31.03.2023 1.00 Initial Release. +* 15.03.2025 5.41 Updated disclaimer +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +#include "r_sci_rx26t_private.h" + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/* BAUD DIVISOR INFO */ + +/* Asynchronous */ +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* when abcs=0 & bgdm=0 & abcse =0, divisor = 64*pow(2,2n-1) */ +/* when abcs=1 & bgdm=0 & abcse =0 OR abcs=0 & bgdm=1 & abcse =0, divisor = 32*pow(2,2n-1) */ +/* when abcs=1 & bgdm=1 & abcse =0, divisor = 16*pow(2,2n-1) */ +/* when abcs=(1 or 0) & bgdm= (1 or 0) & abcse =1, divisor = 12*pow(2,2n-1). This case not available for SCI12 */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/* NOTE: diff than SCI async baud table, but should provide same results */ +const baud_divisor_t async_baud[NUM_DIVISORS_ASYNC]= +{ + /* divisor result, abcs, bgdm, abcse, n */ + {6, 1, 1, 1, 0}, + {8, 1, 1, 0, 0}, + {16, 0, 1, 0, 0}, + {24, 1, 1, 1, 1}, + {32, 0, 0, 0, 0}, + {64, 0, 1, 0, 1}, + {96, 1, 1, 1, 2}, + {128, 0, 0, 0, 1}, + {256, 0, 1, 0, 2}, + {384, 1, 1, 1, 3}, + {512, 0, 0, 0, 2}, + {1024, 0, 1, 0, 3}, + {2048, 0, 0, 0, 3} +}; +#endif + +/* Synchronous and Simple SPI */ +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* abcs=0, bdgm=0, divisor = 8*pow(2,2n-1) */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/* NOTE: Identical to SCI sync baud table */ +const baud_divisor_t sync_baud[NUM_DIVISORS_SYNC]= +{ + /* divisor result, abcs, bgdm, abcse, n */ + {4, 0, 0, 0, 0}, + {16, 0, 0, 0, 1}, + {64, 0, 0, 0, 2}, + {256, 0, 0, 0, 3} +}; +#endif + + +/* CHANNEL MEMORY ALLOCATIONS */ + +#if SCI_CFG_CH1_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch1_rom = {(volatile struct st_sci1 R_BSP_EVENACCESS_SFR *)&SCI1, + (volatile uint32_t R_BSP_EVENACCESS_SFR *)&SYSTEM.MSTPCRB.LONG, BIT30_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI1_TEI1, sci1_tei1_isr, + #endif + BSP_INT_SRC_BL0_SCI1_ERI1, sci1_eri1_isr, + SCI_BIT2, SCI_BIT3, + &ICU.IPR[IPR_SCI1_RXI1].BYTE, + &ICU.IPR[IPR_SCI1_TXI1].BYTE, + &ICU.IR[IR_SCI1_RXI1].BYTE, + &ICU.IR[IR_SCI1_TXI1].BYTE, + &ICU.IER[IER_SCI1_RXI1].BYTE, + &ICU.IER[IER_SCI1_TXI1].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR *)&ICU.GENBL0.LONG, + SCI_BIT4, SCI_BIT5, + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + SCI_CFG_CH1_TX_DTC_DMACA_ENABLE, + SCI_CFG_CH1_RX_DTC_DMACA_ENABLE, + 0, + 0, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + DTCE_SCI1_TXI1, + DTCE_SCI1_RXI1, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + IR_SCI1_TXI1, + IR_SCI1_RXI1, + (uint8_t)SCI_CFG_CH1_TX_DMACA_CH_NUM, + (uint8_t)SCI_CFG_CH1_RX_DMACA_CH_NUM, + #endif + /* Casting to uint8_t type is valid */ + (uint8_t)SCI_CH1 + }; + +/* channel control block */ +sci_ch_ctrl_t ch1_ctrl = {&ch1_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif /* End of SCI_CFG_CH1_INCLUDED */ + + +#if SCI_CFG_CH5_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch5_rom = {(volatile struct st_sci1 R_BSP_EVENACCESS_SFR *)&SCI5, + (volatile uint32_t R_BSP_EVENACCESS_SFR *)&SYSTEM.MSTPCRB.LONG, BIT26_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI5_TEI5, sci5_tei5_isr, + #endif + BSP_INT_SRC_BL0_SCI5_ERI5, sci5_eri5_isr, + SCI_BIT10, SCI_BIT11, + &ICU.IPR[IPR_SCI5_RXI5].BYTE, + &ICU.IPR[IPR_SCI5_TXI5].BYTE, + &ICU.IR[IR_SCI5_RXI5].BYTE, + &ICU.IR[IR_SCI5_TXI5].BYTE, + &ICU.IER[IER_SCI5_RXI5].BYTE, + &ICU.IER[IER_SCI5_TXI5].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR *)&ICU.GENBL0.LONG, + SCI_BIT4, SCI_BIT5, + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + SCI_CFG_CH5_TX_DTC_DMACA_ENABLE, + SCI_CFG_CH5_RX_DTC_DMACA_ENABLE, + 0, + 0, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + DTCE_SCI5_TXI5, + DTCE_SCI5_RXI5, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + IR_SCI5_TXI5, + IR_SCI5_RXI5, + (uint8_t)SCI_CFG_CH5_TX_DMACA_CH_NUM, + (uint8_t)SCI_CFG_CH5_RX_DMACA_CH_NUM, + #endif + /* Casting to uint8_t type is valid */ + (uint8_t)SCI_CH5 + }; + +/* channel control block */ +sci_ch_ctrl_t ch5_ctrl = {&ch5_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif /* End of SCI_CFG_CH5_INCLUDED */ + + +#if SCI_CFG_CH6_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch6_rom = {(volatile struct st_sci1 R_BSP_EVENACCESS_SFR *)&SCI6, + (volatile uint32_t R_BSP_EVENACCESS_SFR *)&SYSTEM.MSTPCRB.LONG, BIT25_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI6_TEI6, sci6_tei6_isr, + #endif + BSP_INT_SRC_BL0_SCI6_ERI6, sci6_eri6_isr, + SCI_BIT12, SCI_BIT13, + &ICU.IPR[IPR_SCI6_RXI6].BYTE, + &ICU.IPR[IPR_SCI6_TXI6].BYTE, + &ICU.IR[IR_SCI6_RXI6].BYTE, + &ICU.IR[IR_SCI6_TXI6].BYTE, + &ICU.IER[IER_SCI6_RXI6].BYTE, + &ICU.IER[IER_SCI6_TXI6].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR *)&ICU.GENBL0.LONG, + SCI_BIT6, SCI_BIT7, + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + SCI_CFG_CH6_TX_DTC_DMACA_ENABLE, + SCI_CFG_CH6_RX_DTC_DMACA_ENABLE, + 0, + 0, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + DTCE_SCI6_TXI6, + DTCE_SCI6_RXI6, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + IR_SCI6_TXI6, + IR_SCI6_RXI6, + (uint8_t)SCI_CFG_CH6_TX_DMACA_CH_NUM, + (uint8_t)SCI_CFG_CH6_RX_DMACA_CH_NUM, + #endif + /* Casting to uint8_t type is valid */ + (uint8_t)SCI_CH6 + }; + +/* channel control block */ +sci_ch_ctrl_t ch6_ctrl = {&ch6_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif /* End of SCI_CFG_CH6_INCLUDED */ + + +#if SCI_CFG_CH12_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch12_rom = {(volatile struct st_sci1 R_BSP_EVENACCESS_SFR *)&SCI12, + (volatile uint32_t R_BSP_EVENACCESS_SFR *)&SYSTEM.MSTPCRB.LONG, BIT4_MASK, + #if SCI_CFG_TEI_INCLUDED + BSP_INT_SRC_BL0_SCI12_TEI12, sci12_tei12_isr, + #endif + BSP_INT_SRC_BL0_SCI12_ERI12, sci12_eri12_isr, + SCI_BIT16, SCI_BIT17, + &ICU.IPR[IPR_SCI12_RXI12].BYTE, + &ICU.IPR[IPR_SCI12_TXI12].BYTE, + &ICU.IR[IR_SCI12_RXI12].BYTE, + &ICU.IR[IR_SCI12_TXI12].BYTE, + &ICU.IER[IER_SCI12_RXI12].BYTE, + &ICU.IER[IER_SCI12_TXI12].BYTE, + (volatile uint32_t R_BSP_EVENACCESS_SFR *)&ICU.GENBL0.LONG, + SCI_BIT4, SCI_BIT5, + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + SCI_CFG_CH12_TX_DTC_DMACA_ENABLE, + SCI_CFG_CH12_RX_DTC_DMACA_ENABLE, + 0, + 0, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + DTCE_SCI12_TXI12, + DTCE_SCI12_RXI12, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + IR_SCI12_TXI12, + IR_SCI12_RXI12, + (uint8_t)SCI_CFG_CH12_TX_DMACA_CH_NUM, + (uint8_t)SCI_CFG_CH12_RX_DMACA_CH_NUM, + #endif + /* Casting to uint8_t type is valid */ + (uint8_t)SCI_CH12 + }; + +/* channel control block */ +sci_ch_ctrl_t ch12_ctrl = {&ch12_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif /* End of SCI_CFG_CH12_INCLUDED */ + + +/* SCI HANDLE-ARRAY DECLARATION */ + +const sci_hdl_t g_handles[SCI_NUM_CH] = +{ + NULL, /* ch0 */ + +#if SCI_CFG_CH1_INCLUDED + &ch1_ctrl, +#else + NULL, +#endif + + NULL, /* ch2 */ + NULL, /* ch3 */ + NULL, /* ch4 */ + +#if SCI_CFG_CH5_INCLUDED + &ch5_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH6_INCLUDED + &ch6_ctrl, +#else + NULL, +#endif + + NULL, /* ch7 */ + NULL, /* ch8 */ + NULL, /* ch9 */ + NULL, /* ch10 */ + NULL, /* ch11 */ + +#if SCI_CFG_CH12_INCLUDED + &ch12_ctrl +#else + NULL +#endif +}; + diff --git a/drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t_private.h b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t_private.h new file mode 100644 index 00000000..9c30334a --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t_private.h @@ -0,0 +1,269 @@ +/*********************************************************************************************************************** +* Copyright (c) 2023 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx26t_private.h +* Description : Functions for using SCI on the RX26T device. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 31.03.2023 1.00 Initial Release. +* 15.03.2025 5.41 Updated disclaimer +***********************************************************************************************************************/ + +#ifndef SCI_RX26T_H +#define SCI_RX26T_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "../../r_sci_rx_private.h" + +#if (SCI_CFG_ASYNC_INCLUDED) +#include "r_byteq_if.h" +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* Mask of all active channels */ +#define SCI_CFG_CH_INCLUDED_MASK ((SCI_CFG_CH0_INCLUDED << 1) \ + | (SCI_CFG_CH5_INCLUDED << 5) \ + | (SCI_CFG_CH6_INCLUDED << 6) \ + | (SCI_CFG_CH12_INCLUDED << 12)) + +/* SCI SCR register masks */ +#define SCI_SCR_TEI_MASK (0x80U) /* transmit interrupt enable */ +#define SCI_SCR_REI_MASK (0x40U) /* receive interrupt enable */ +#define SCI_SCR_TE_MASK (0x20U) /* transmitter enable */ +#define SCI_SCR_RE_MASK (0x10U) /* receiver enable */ +#define SCI_EN_XCVR_MASK (SCI_SCR_RE_MASK | SCI_SCR_TE_MASK | SCI_SCR_REI_MASK | SCI_SCR_TEI_MASK) + +/* SCI SSR register receiver error masks */ +#define SCI_SSR_ORER_MASK (0x20U) /* overflow error */ +#define SCI_SSR_FER_MASK (0x10U) /* framing error */ +#define SCI_SSR_PER_MASK (0x08U) /* parity err */ +#define SCI_RCVR_ERR_MASK (SCI_SSR_ORER_MASK | SCI_SSR_FER_MASK | SCI_SSR_PER_MASK) +#define SCI_SSR_CLR_MASK (0xC0U) /* SSR register cleare mask (11000000b) */ + +/* Macros to enable and disable ICU interrupts */ +#define ENABLE_RXI_INT (R_BSP_BIT_SET(hdl->rom->icu_rxi, hdl->rom->rxi_bit_num)) +#define DISABLE_RXI_INT (R_BSP_BIT_CLEAR(hdl->rom->icu_rxi, hdl->rom->rxi_bit_num)) +#define ENABLE_TXI_INT (R_BSP_BIT_SET(hdl->rom->icu_txi, hdl->rom->txi_bit_num)) +#define DISABLE_TXI_INT (R_BSP_BIT_CLEAR(hdl->rom->icu_txi, hdl->rom->txi_bit_num)) + +#define ENABLE_ERI_INT (R_BSP_BIT_SET((uint8_t*)(hdl->rom->icu_grp) + (hdl->rom->eri_bit_num >> 3), hdl->rom->eri_bit_num & 7)) +#define DISABLE_ERI_INT (R_BSP_BIT_CLEAR((uint8_t*)(hdl->rom->icu_grp) + (hdl->rom->eri_bit_num >> 3), hdl->rom->eri_bit_num & 7)) +#define ENABLE_TEI_INT (R_BSP_BIT_SET((uint8_t*)(hdl->rom->icu_grp) + (hdl->rom->tei_bit_num >> 3), hdl->rom->tei_bit_num & 7)) +#define DISABLE_TEI_INT (R_BSP_BIT_CLEAR((uint8_t*)(hdl->rom->icu_grp) + (hdl->rom->tei_bit_num >> 3), hdl->rom->tei_bit_num & 7)) + +#define NUM_DIVISORS_ASYNC (13) +#define NUM_DIVISORS_SYNC (4) + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +typedef struct st_scif_fifo_ctrl +{ + uint8_t *p_tx_buf; /* user's buffer */ + uint8_t *p_rx_buf; /* user's buffer */ + uint16_t tx_cnt; /* bytes remaining to add to FIFO */ + uint16_t rx_cnt; /* bytes waiting to receive from FIFO */ +#if (TX_DTC_DMACA_ENABLE) || (RX_DTC_DMACA_ENABLE) + uint8_t *p_tx_fraction_buf; + uint8_t *p_rx_fraction_buf; + uint16_t tx_fraction; + uint16_t rx_fraction; +#endif + uint16_t total_length; /* used for DTC in txi_handler */ +} sci_fifo_ctrl_t; + +/* CHANNEL CONTROL BLOCK */ + +/* ROM INFO */ + +typedef struct st_sci_ch_rom /* SCI ROM info for channel control block */ +{ + volatile struct st_sci1 R_BSP_EVENACCESS_SFR *regs; /* base ptr to ch registers */ + volatile uint32_t R_BSP_EVENACCESS_SFR *mstp; /* ptr to mstp register */ + uint32_t stop_mask; /* mstp mask to disable ch */ +#if SCI_CFG_TEI_INCLUDED + bsp_int_src_t tei_vector; + bsp_int_cb_t tei_isr; +#endif + bsp_int_src_t eri_vector; + bsp_int_cb_t eri_isr; + uint32_t tei_bit_num; /* ICU IR and IEN bit number */ + uint32_t eri_bit_num; /* ICU IR and IEN bit number */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ipr_rxi; /* ptr to IPR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ipr_txi; /* ptr to IPR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_rxi; /* ptr to RXI IR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_txi; /* ptr to TXI IR register */ + + /* + * DO NOT use the enable/disable interrupt bits in the SCR + * register. Pending interrupts can be lost that way. + */ + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_rxi; /* ptr to ICU register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_txi; + volatile uint32_t R_BSP_EVENACCESS_SFR *icu_grp; + uint8_t rxi_bit_num; /* ICU enable/disable rxi bit number */ + uint8_t txi_bit_num; /* ICU enable/disable txi bit number */ + /* + * In case using DTC/DMAC + */ +#if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + uint8_t dtc_dmaca_tx_enable; + uint8_t dtc_dmaca_rx_enable; + uint8_t dtc_dmaca_tx_block_size; + uint8_t dtc_dmaca_rx_block_size; +#endif +#if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + dtc_activation_source_t dtc_tx_act_src; + dtc_activation_source_t dtc_rx_act_src; +#endif +#if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + dmaca_activation_source_t dmaca_tx_act_src; + dmaca_activation_source_t dmaca_rx_act_src; + uint8_t dmaca_tx_channel; + uint8_t dmaca_rx_channel; +#endif + uint8_t chan; /* Channel SCI is used*/ +} sci_ch_rom_t; + + +/* CHANNEL CONTROL BLOCK */ + +typedef struct st_sci_ch_ctrl /* SCI channel control (for handle) */ +{ + sci_ch_rom_t const *rom; /* pointer to rom info */ + sci_mode_t mode; /* operational mode */ + uint32_t baud_rate; /* baud rate */ + void (*callback)(void *p_args); /* function ptr for rcvr errs */ + union + { +#if (SCI_CFG_ASYNC_INCLUDED) + byteq_hdl_t que; /* async transmit queue handle */ +#endif + uint8_t *buf; /* sspi/sync tx buffer ptr */ + } u_tx_data; + union + { +#if (SCI_CFG_ASYNC_INCLUDED) + byteq_hdl_t que; /* async receive queue handle */ +#endif + uint8_t *buf; /* sspi/sync rx buffer ptr */ + } u_rx_data; + bool tx_idle; /* TDR is empty (async); TSR is empty (sync/sspi) */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + bool save_rx_data; /* save the data that is clocked in */ + uint16_t tx_cnt; /* number of bytes to transmit */ + uint16_t rx_cnt; /* number of bytes to receive */ + bool tx_dummy; /* transmit dummy byte, not buffer */ +#endif + uint32_t pclk_speed; /* saved peripheral clock speed for break generation */ +#if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + bool rx_idle; + uint8_t qindex_app_tx; + uint8_t qindex_int_tx; + uint8_t qindex_app_rx; + uint8_t qindex_int_rx; + sci_fifo_ctrl_t queue[2]; +#endif +} sci_ch_ctrl_t; + + +/* BAUD DIVISOR INFO */ + +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* when abcs=1, divisor = 32*pow(2,2n-1) */ +/* when abcs=0, divisor = 64*pow(2,2n-1) */ + +typedef struct st_baud_divisor +{ + int16_t divisor; // clock divisor + uint8_t abcs; // abcs value to get divisor + uint8_t bgdm; // bdgm value to get divisor + uint8_t abcse; // abcse value to get divisor + uint8_t cks; // cks value to get divisor (cks = n) +} baud_divisor_t; + + + +/***************************************************************************** +Exported global variables and functions +******************************************************************************/ +extern const sci_hdl_t g_sci_handles[]; + +#if (SCI_CFG_ASYNC_INCLUDED) +extern const baud_divisor_t async_baud[]; +#endif +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +extern const baud_divisor_t sync_baud[]; +#endif + +#if (SCI_CFG_CH1_INCLUDED) +extern const sci_ch_rom_t ch1_rom; +extern sci_ch_ctrl_t ch1_ctrl; +#endif + +#if (SCI_CFG_CH5_INCLUDED) +extern const sci_ch_rom_t ch5_rom; +extern sci_ch_ctrl_t ch5_ctrl; +#endif + +#if (SCI_CFG_CH6_INCLUDED) +extern const sci_ch_rom_t ch6_rom; +extern sci_ch_ctrl_t ch6_ctrl; +#endif + +#if (SCI_CFG_CH12_INCLUDED) +extern const sci_ch_rom_t ch12_rom; +extern sci_ch_ctrl_t ch12_ctrl; +#endif + +/***************************************************************************** +Exported global functions +******************************************************************************/ +#if SCI_CFG_TEI_INCLUDED +extern void sci1_tei1_isr (void *cb_args); +extern void sci5_tei5_isr (void *cb_args); +extern void sci6_tei6_isr (void *cb_args); +extern void sci12_tei12_isr (void *cb_args); +#endif + +extern void sci1_eri1_isr (void *cb_args); +extern void sci5_eri5_isr (void *cb_args); +extern void sci6_eri6_isr (void *cb_args); +extern void sci12_eri12_isr (void *cb_args); + +extern void sci_init_register (sci_hdl_t const hdl); + +#if (SCI_CFG_ASYNC_INCLUDED) +extern sci_err_t sci_async_cmds (sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); +#endif + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +extern sci_err_t sci_sync_cmds (sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); +#endif + +extern sci_err_t sci_mcu_param_check (uint8_t const chan); + +extern int32_t sci_init_bit_rate (sci_hdl_t const hdl, + uint32_t const pclk, + uint32_t const baud); + +extern void sci_initialize_ints (sci_hdl_t const hdl, + uint8_t const priority); + +extern void sci_disable_ints (sci_hdl_t const hdl); + +#endif /* SCI_RX26T_H */ + diff --git a/zephyr/rx/rdp_cfg/r_config/rx26t/r_bsp_config.h b/zephyr/rx/rdp_cfg/r_config/rx26t/r_bsp_config.h new file mode 100644 index 00000000..1080b9c3 --- /dev/null +++ b/zephyr/rx/rdp_cfg/r_config/rx26t/r_bsp_config.h @@ -0,0 +1,714 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : r_bsp_config_reference.h +* Device(s) : RX26T +* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included +* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h) +* is just a reference file that the user can use to make their own r_bsp_config.h file. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 26.04.2023 1.01 Modified comment. +* : 21.11.2023 1.02 Added the following macro definitions. +* - BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE +* - BSP_CFG_MEMORY_BUS1_PRIORITY +* - BSP_CFG_MEMORY_BUS2_PRIORITY +* - BSP_CFG_INTERNAL_PERIPHERAL_BUS1_PRIORITY +* - BSP_CFG_INTERNAL_PERIPHERAL_BUS2_3_PRIORITY +* - BSP_CFG_INTERNAL_PERIPHERAL_BUS4_5_PRIORITY +* - BSP_CFG_INTERNAL_PERIPHERAL_BUS6_PRIORITY +* - BSP_CFG_BOOTLOADER_PROJECT +* Modified comment. +* Deleted the BSP_CFG_ROMCODE_REG_VALUE. +* : 26.02.2025 1.03 Changed the disclaimer. +***********************************************************************************************************************/ +#include +#include +#include +#include "mcu_clocks.h" + +#ifndef R_BSP_CONFIG_REF_HEADER_FILE +#define R_BSP_CONFIG_REF_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* NOTE: + The default settings are the same as when using MCK-RX26T. + Change to the settings for the user board. +*/ + +/* Start up select + 0 = Enable BSP startup program. + 1 = Disable BSP startup program. (e.g. Using user startup program.) + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_STARTUP_DISABLE (0) + +/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such + as package and memory size. + To help parse this information, the part number will be defined using multiple macros. + R 5 F 52 6T E A D FP + | | | | | | | | | Macro Name Description + | | | | | | | | |__BSP_CFG_MCU_PART_PACKAGE = Package type, number of pins, and pin pitch + | | | | | | | |____not used = Products with wide temperature range + | | | | | | |______BSP_CFG_MCU_PART_FUNCTION = CAN 2.0/CAN FD protocol supported, + | | | | | | TSIP-Lite included/not included + | | | | | |________BSP_CFG_MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity + | | | | |___________BSP_CFG_MCU_PART_GROUP = Group name + | | | |______________BSP_CFG_MCU_PART_SERIES = Series name + | | |________________BSP_CFG_MCU_PART_MEMORY_TYPE = Type of memory (Flash, ROMless) + | |__________________not used = Renesas MCU + |____________________not used = Renesas semiconductor product. +*/ + +/* Package type. Set the macro definition based on values below: + Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch + FP = 0x0 = LFQFP/100/0.50 + FN = 0x1 = LFQFP/80/0.50 + FM = 0x8 = LFQFP/64/0.50 + FL = 0x6 = LFQFP/48/0.50 + ND = 0x5 = HWQFN/64/0.50 + NE = 0x7 = HWQFN/48/0.50 +*/ +#define BSP_CFG_MCU_PART_PACKAGE (0x0) + +/* CAN 2.0/CAN FD protocol supported, TSIP-Lite included/not included + Character(s) = Value for macro = Description + A = 0xA = Only CAN 2.0 protocol supported, without TSIP-Lite + B = 0xB = Only CAN 2.0 protocol supported, with TSIP-Lite + C = 0xC = CAN FD protocol supported, without TSIP-Lite + D = 0xD = CAN FD protocol supported, with TSIP-Lite +*/ +#define BSP_CFG_MCU_PART_FUNCTION (0xA) + +/* ROM, RAM, and Data Flash Capacity. + Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size + F = 0xF = 512KB/64KB/16KB + B = 0xB = 256KB/64KB/16KB + A = 0xA = 256KB/48KB/16KB + 9 = 0x9 = 128KB/64KB/16KB + 8 = 0x8 = 128KB/48KB/16KB +*/ +#define BSP_CFG_MCU_PART_MEMORY_SIZE (0xF) + +/* Group name. + Character(s) = Description + 6T = RX26T Group +*/ +#define BSP_CFG_MCU_PART_GROUP "RX26T" + +/* Series name. + Character(s) = Description + 52 = RX200 Series +*/ +#define BSP_CFG_MCU_PART_SERIES "RX200" + +/* Memory type. + Character(s) = Value for macro = Description + F = 0x0 = Flash memory version +*/ +#define BSP_CFG_MCU_PART_MEMORY_TYPE (0x0) + +/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack. + * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU + * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how + * much stack space to allocate since the user does not have to worry about always having enough room on the + * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not + * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used). + * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then + * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings. + * + * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored. + * 1 = Use 2 stacks. User stack and interrupt stack will both be used. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_USER_STACK_ENABLE (1) + +/* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 +/* User Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. */ +#define BSP_CFG_USTACK_BYTES (0x1000) +#endif + +/* Interrupt Stack size in bytes. + NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_ISTACK_BYTES (0x400) + +/* Heap size in bytes. + To disable the heap you must follow these steps: + 1) Set this macro (BSP_CFG_HEAP_BYTES) to 0. + 2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0. + 3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain + settings and choosing the Standard Library section. After that choose 'Contents' in e2 studio. + This will present a list of modules that can be included. Uncheck the box for stdio.h. + NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_HEAP_BYTES (0x400) + +/* Initializes C input & output library functions. + 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value. + 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_IO_LIB_ENABLE (1) + +/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions + by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */ +#define BSP_CFG_USER_CHARGET_ENABLED (0) +#define BSP_CFG_USER_CHARGET_FUNCTION my_sw_charget_function + +#define BSP_CFG_USER_CHARPUT_ENABLED (0) +#define BSP_CFG_USER_CHARPUT_FUNCTION my_sw_charput_function + +/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information + on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual. + 0 = Stay in Supervisor mode. + 1 = Switch to User mode. + NOTE: This is invalid when using Renesas RTOS with CCRX. +*/ +#define BSP_CFG_RUN_IN_USER_MODE (0) + +/* Set your desired ID code. NOTE, leave at the default (all 0xFF's) if you do not wish to use an ID code. If you set + this value and program it into the MCU then you will need to remember the ID code because the debugger will ask for + it when trying to connect. Note that the E1/E20 will ignore the ID code when programming the MCU during debugging. + If you set this value and then forget it then you can clear the ID code by connecting up in serial boot mode using + FDT. The ID Code is 16 bytes long. The macro below define the ID Code in 4-byte sections. */ +/* Lowest 4-byte section, address 0x00120050. From MSB to LSB: ID code 4, ID code 3, ID code 2, ID code 1/Control Code. + */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +/* 2nd ID Code section, address 0x00120054. From MSB to LSB: ID code 8, ID code 7, ID code 6, ID code 5. */ +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +/* 3rd ID Code section, address 0x00120058. From MSB to LSB: ID code 12, ID code 11, ID code 10, ID code 9. */ +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +/* 4th ID Code section, address 0x0012005C. From MSB to LSB: ID code 16, ID code 15, ID code 14, ID code 13. */ +#define BSP_CFG_ID_CODE_LONG_4 (0xFFFFFFFF) + +/* Select ID code protection. + 0 = ID code protection is disabled. + 1 = ID code protection is enabled. +*/ +#define BSP_CFG_ID_CODE_ENABLE (0) + +/* Select whether to enables or disables the protection of block erasure commands. + 0 = Execution of block erasure commands is permitted after a reset. (default) + 1 = Execution of block erasure commands is prohibited after a reset. + NOTE: This is invalid when ID code protection(BSP_CFG_ID_CODE_ENABLE) is enabled. + */ +#define BSP_CFG_BLOCK_ERASE_CMD_PROTECT_ENABLE (0) + +/* Select whether to enables or disables the protection of programming commands. + 0 = Execution of programming commands is permitted after a reset. (default) + 1 = Execution of programming commands is prohibited after a reset. + NOTE: This is invalid when ID code protection(BSP_CFG_ID_CODE_ENABLE) is enabled. + */ +#define BSP_CFG_PROGRAM_CMD_PROTECT_ENABLE (0) + +/* Select whether to enables or disables the protection of read commands. + 0 = Execution of read commands is permitted after a reset. (default) + 1 = Execution of read commands is prohibited after a reset. + NOTE: This is invalid when ID code protection(BSP_CFG_ID_CODE_ENABLE) is enabled. + */ +#define BSP_CFG_READ_CMD_PROTECT_ENABLE (0) + +/* Select whether to enables or disables the connection of serial programmer. + 0 = Connection of a serial programmer is prohibited after a reset. + 1 = Connection of a serial programmer is permitted after a reset. (default) +*/ +#define BSP_CFG_SERIAL_PROGRAMMER_CONECT_ENABLE (1) + +/* Select whether to oscillate the Main Clock Oscillator. + 0 = Stop Oscillating the Main Clock. + 1 = Enable oscillating the Main Clock. (default) +*/ +#define BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE (DT_NODE_HAS_STATUS(DT_NODELABEL(xtal), okay)) + +/* Select whether to oscillate the High Speed On-Chip Oscillator (HOCO). + 0 = Stop Oscillating the HOCO. (default) + 1 = Enable Oscillating the HOCO. +*/ +#define BSP_CFG_HOCO_OSCILLATE_ENABLE (DT_NODE_HAS_STATUS(DT_NODELABEL(hoco), okay)) + +/* Select whether to oscillate the Low Speed On-Chip Oscillator (LOCO). + 0 = Stop Oscillating the LOCO. (default) + 1 = Enable Oscillating the LOCO. +*/ +#define BSP_CFG_LOCO_OSCILLATE_ENABLE (DT_NODE_HAS_STATUS(DT_NODELABEL(loco), okay)) + +/* Select whether to oscillate the IWDT-Dedicated On-Chip Oscillator (IWDT). + 0 = Stop Oscillating the IWDT Clock. (default) + 1 = Enable Oscillating the IWDT Clock. +*/ +#define BSP_CFG_IWDT_CLOCK_OSCILLATE_ENABLE (DT_NODE_HAS_STATUS(DT_NODELABEL(iwdtlsclk), okay)) + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator (N/A for RX26T) + 4 = PLL Circuit +*/ +#define BSP_CFG_CLOCK_SOURCE (RX_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))) + +/* Main clock Oscillator Switching (MOSEL). + 0 = Resonator + 1 = External clock input +*/ +#define BSP_CFG_MAIN_CLOCK_SOURCE (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), mosel, 0)) + +/* Clock configuration options. + The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The + multiplier settings are used to set the clock registers in resetprg.c. If a 24MHz clock is used and the + ICLK is 120MHz, PCLKA is 120MHz, PCLKB is 60MHz, PCLKC is 120MHz, PCLKD is 60MHz, FCLK is 60MHz, CANFD Clock is 60MHz, + and then the settings would be: + + BSP_CFG_XTAL_HZ = 10000000 + BSP_CFG_PLL_DIV = 1 (no division) + BSP_CFG_PLL_MUL = 24.0 (10MHz x 24.0 = 240MHz) + BSP_CFG_ICK_DIV = 2 : System Clock (ICLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV) = 120MHz + BSP_CFG_PCKA_DIV = 2 : Peripheral Clock A (PCLKA) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKA_DIV) = 120MHz + BSP_CFG_PCKB_DIV = 4 : Peripheral Clock B (PCLKB) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 60MHz + BSP_CFG_PCKC_DIV = 2 : Peripheral Clock C (PCLKC) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKC_DIV) = 120MHz + BSP_CFG_PCKD_DIV = 4 : Peripheral Clock D (PCLKD) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 60MHz + BSP_CFG_FCK_DIV = 4 : Flash IF Clock (FCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV) = 60MHz + BSP_CFG_CFDCK_DIV = 4 : CANFD Clock (CANFDCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_CFDCK_DIV) = 60MHz +*/ + +/* Input clock frequency in Hz (XTAL or EXTAL). */ +#define BSP_CFG_XTAL_HZ (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)) + +/* The HOCO can operate at several different frequencies. Choose which one using the macro below. + Available frequency settings: + 0 = 16MHz (default) + 1 = 18MHz + 2 = 20MHz +*/ +#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 16000000 +#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 16MHz */ +#elif DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 18000000 +#define BSP_CFG_HOCO_FREQUENCY 1 /* HOCO 18MHz */ +#elif DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 20000000 +#define BSP_CFG_HOCO_FREQUENCY 2 /* HOCO 20MHz */ +#else +#error "Invalid HOCO frequency, only can be set to 16MHz, 18MHz, 20MHz, 32MHz, 48MHz" +#endif + +/* PLL clock source (PLLSRCSEL). Choose which clock source to input to the PLL circuit. + Available clock sources: + 0 = Main clock (default) + 1 = HOCO +*/ +#define BSP_CFG_PLL_SRC RX_CGC_PLL_CLK_SRC(DT_NODELABEL(pll)) + +/* PLL Input Frequency Division Ratio Select (PLIDIV). + Available divisors = /1 (no division), /2, /3 +*/ +#define BSP_CFG_PLL_DIV (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, 2)) + +/* PLL Frequency Multiplication Factor Select (STC). + Available multipliers = x10.0 to x30.0 in 0.5 increments (e.g. 10.0, 10.5, 11.0, 11.5, ..., 29.0, 29.5, 30.0) +*/ +#define BSP_CFG_PLL_MUL ((RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), mul, 15) + 1) / (2.0)) + +/* System Clock Divider (ICK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_ICK_DIV (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), div, 1)) + +/* Peripheral Module Clock A Divider (PCKA). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKA_DIV (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclka), div, 2)) + +/* Peripheral Module Clock B Divider (PCKB). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKB_DIV (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), div, 1)) + +/* Peripheral Module Clock C Divider (PCKC). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKC_DIV (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkc), div, 1)) + +/* Peripheral Module Clock D Divider (PCKD). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKD_DIV (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), div, 1)) + +/* Flash IF Clock Divider (FCK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_FCK_DIV (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), div, 1)) + +/* CANFD Clock Divider Select (CANFDCLK). + Available divisors = /2, /4, /8 +*/ +#define BSP_CFG_CFDCK_DIV (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(canfdclk), div, 1)) + +/* Main Clock Oscillator Wait Time (MOSCWTCR). + The value of MOSCWTCR register required for correspondence with the waiting time required to secure stable + oscillation by the main clock oscillator is obtained by using the maximum frequency for fLOCO in the formula below. + + BSP_CFG_MOSC_WAIT_TIME > (tMAINOSC * (fLOCO_max) + 16)/32 + (tMAINOSC: main clock oscillation stabilization time; fLOCO_max: maximum frequency for fLOCO) + + If tMAINOSC is 9.98 ms and fLOCO_max is 264 kHz (the period is 1/3.78 us), the formula gives + BSP_CFG_MOSC_WAIT_TIME > (9.98 ms * (264 kHZ) + 16)/32 = 82.83, so set the BSP_CFG_MOSC_WAIT_TIME to 83(53h). + + NOTE: The waiting time is not required when an external clock signal is input for the main clock oscillator. + Set the BSP_CFG_MOSC_WAIT_TIME to 00h. +*/ +#define BSP_CFG_MOSC_WAIT_TIME (0x53) + +/* Configure WDT and IWDT settings. + OFS0 - Option Function Select Register 0 + b31:b29 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b28 WDTRSTIRQS - WDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b27:b26 WDTRPSS - WDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b25:b24 WDTRPES - WDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b23:b20 WDTCKS - WDT Clock Frequency Division Ratio - (1=PCLKB/4, 4=PCLKB/64, 0xF=PCLKB/128, 6=PCLKB/256, + 7=PCLKB/2048, 8=PCLKB/8192) + b19:b18 WDTTOPS - WDT Timeout Period Select (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b17 WDTSTRT - WDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b16:b15 Reserved (set to 1) + b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes) + b13 Reserved (set to 1) + b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256) + b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=1024 cycles, 1=4096, 2=8192, 3=16384) + b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b0 Reserved (set to 1) + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS0_REG_VALUE (0xFFFFFFFF) + +/* Configure whether voltage detection 0 circuit and HOCO are enabled after reset. + OFS1 - Option Function Select Register 1 + b31:b9 Reserved (set to 1) + b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable) + b7:b3 Reserved When reading, these bits return the value written by the user. The write value should be 1. + b2 LVDAS - Voltage Detection 0 circuit start (1=monitoring disabled) + b1:b0 VDSEL - Voltage Detection 0 level select (2=2.83V, 3=4.22V) + NOTE: If HOCO oscillation is enabled by OFS1.HOCOEN, HOCO frequency is 16MHz. + BSP_CFG_HOCO_FREQUENCY should be default value. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS1_REG_VALUE (0xFFFFFFFF) + +/* Trusted memory is facility to prevent the reading of blocks 8 and 9 and blocks 30 and 31 (in dual mode) in + the code flash memory by third party software. This feature is disabled by default. + TMEF - TM Enable Flag Register + b31 Reserved (set to 1) + b30:b28 TMEFDB - Dual-Bank TM Enable - 000: The TM function in the address range from FFEE 0000h to + FFEE FFFFh is enabled in dual mode. + - 111: The TM function in the address range from FFEE 0000h to + FFEE FFFFh is disabled in dual mode. + b27 Reserved (set to 1) + b26:b24 TMEF - TM Enable - 000: TM function is enabled. + - 111: TM function is disabled. + b23:b0 Reserved (set to 1) + NOTE: If the dual bank function has not been incorporated in a device, + TMEFDB bits [b30:b28] are reserved area. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_TRUSTED_MODE_FUNCTION (0xFFFFFFFF) + +/* Configure FAW register is used to set the write protection flag and boot area select flag + for setting the flash access window startaddress and flash access window end address. + FAW - Flash Access Window Setting Register + b31 BTFLG - Boot Area Select Flag - 0: FFFF 8000h to FFFF BFFFh are used as the boot area + - 1: FFFF C000h to FFFF FFFFh are used as the boot area + b30:b28 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b27:b16 FAWE - Flash Access Window End Address - Flash access window end address + b15 FSPR - Access Window Protection Flag - 0: With protection (P/E disabled) + - 1: Without protection (P/E enabled) + b14:b12 Reserved - When reading, these bits return the value written by the user.The write value should be 1. + b11:b0 FAWS - Flash Access Window Start Address - Flash access window start address + NOTE: Once 0 is written to this bit, the bit can never be restored to 1. + Therefore, the access window and the BTFLG bit never be set again or the TM function + never be disabled once it has been enabled. + Exercise extra caution when handling the FSPR bit. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_FAW_REG_VALUE (0xFFFFFFFF) + +/* Select the bank mode of dual-bank function of the code flash memory. + 0 = Dual mode. + 1 = Linear mode. (default) + NOTE: If the dual bank function has been incorporated in a device, select the bank mode in this macro. + Default setting of the bank mode is linear mode. + If the dual bank function has not been incorporated in a device, this macro should be 1. +*/ +#define BSP_CFG_CODE_FLASH_BANK_MODE (1) + +/* Select the startup bank of the program when dual bank function is in dual mode. + 0 = The address range of bank 1 from FFF80000h to FFFBFFFFh and bank 0 from FFFC0000h to FFFFFFFFh. (default) + 1 = The address range of bank 1 from FFFC0000h to FFFFFFFFh and bank 0 from FFF80000h to FFFBFFFFh. + NOTE: If the dual bank function has been incorporated in a device, select the start bank in this macro. + Default setting of the start bank is bank0. + If the dual bank function has not been incorporated in a device, this macro should be 0. +*/ +#define BSP_CFG_CODE_FLASH_START_BANK (0) + +/* This macro lets other modules no if a RTOS is being used. + 0 = RTOS is not used. + 1 = FreeRTOS is used. + 2 = embOS is used.(This is not available.) + 3 = MicroC_OS is used.(This is not available.) + 4 = Renesas ITRON OS (RI600V4 or RI600PX) is used. + 5 = Azure RTOS is used. +*/ +#define BSP_CFG_RTOS_USED (0) + +/* This macro is used to select which Renesas ITRON OS. + 0 = RI600V4 is used. + 1 = RI600PX is used. +*/ +#define BSP_CFG_RENESAS_RTOS_USED (0) + +/* This macro is used to select which CMT channel used for system timer of RTOS. + * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */ +#if BSP_CFG_RTOS_USED != 0 +/* Setting value. + * 0 = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS). + * 1 = CMT channel 1 used for system timer of RTOS. + * 2 = CMT channel 2 used for system timer of RTOS. + * 3 = CMT channel 3 used for system timer of RTOS. + * Others = Invalid. + * NOTE: This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_RTOS_SYSTEM_TIMER (0) +#endif + +/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its + locking mechanisms then they can change this macro. + NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'. + 0 = Use default locking (non-RTOS) + 1 = Use user defined locking mechanism. +*/ +#define BSP_CFG_USER_LOCKING_ENABLED (0) + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef + that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be + a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions + that will handle the locking and unlocking. These functions should be defined below. + If BSP_CFG_USER_LOCKING_ENABLED is != 0: + R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index) + R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index) + NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter. + R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + NOTE:With these functions the actual address of the lock to use is passed as the parameter. + NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else, + return false. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION my_hw_locking_function +#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION my_hw_unlocking_function +#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION my_sw_locking_function +#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION my_sw_unlocking_function + +/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the + following callback definitions AND provide a call back function name for the respective callback + function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result + in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C + runtime environment by resetprg. + Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined + my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg. +*/ +#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION my_sw_warmstart_prec_function + +#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION my_sw_warmstart_postc_function + +/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users + will want to disable this for production code. The reason for this would be to save execution time and code space. + This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its + own local macro for this same purpose. By default the local macros will take the global value from here though + they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter + checking should only used when inputs are known to be good and the increase in speed or decrease in code space is + needed. + 0 = Global setting for parameter checking is disabled. + 1 = Global setting for parameter checking is enabled (Default). +*/ +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) + +/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. + Please change the value according to the supplied voltage level. + For example, when supplying 3.3 V, please set the value to 3300. + NOTE: Set values appropriate for the user system. +*/ +#define BSP_CFG_MCU_VCC_MV (5000) + +/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool. + When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0. + 0 = Disabled (default) + 1 = Smart Configurator initialization code used +*/ +#define BSP_CFG_CONFIGURATOR_SELECT (0) + +/* Version number of Smart Configurator. + This macro definition is updated by Smart Configurator. +*/ +#define BSP_CFG_CONFIGURATOR_VERSION (2140) + +/* For some BSP functions, it is necessary to ensure that, while these functions are executing, interrupts from other + FIT modules do not occur. By controlling the IPL, these functions disable interrupts that are at or below the + specified interrupt priority level. + This macro sets the IPL. Range is 0x0 - 0xF. + Please set this macro more than IPR for other FIT module interrupts. + The default value is 0xF (maximum value). + Don't change if there is no special processing with higher priority than all fit modules. +*/ +#define BSP_CFG_FIT_IPL_MAX (0xF) + +/* Software Interrupt (SWINT). + 0 = Software interrupt is not used. + 1 = Software interrupt is used. + NOTE: When this macro is set to 1, the software interrupt is initialized in bsp startup routine. +*/ +#define BSP_CFG_SWINT_UNIT1_ENABLE (0) +#define BSP_CFG_SWINT_UNIT2_ENABLE (0) + +/* Software Interrupt Task Buffer Number. + For software interrupt, this value is number of buffering user tasks. + So user can increase this value if user system would have many software interrupt tasks + and user system has enough buffer. This value requires 9 byte per task. + NOTE: This setting is common to all units. It can not be set individually. + The maximum value is 254. +*/ +#define BSP_CFG_SWINT_TASK_BUFFER_NUMBER (8) + +/* Initial value of the software interrupt priority. + For software interrupt, this value is interrupt priority. Range is 0x0 - 0xF. + NOTE: This setting is common to all units. It can not be set individually. + Please be careful that this setting is the initial value of the interrupt priority register(IPR). + It is possible to dynamically change the IPR. +*/ +#define BSP_CFG_SWINT_IPR_INITIAL_VALUE (0x1) + +/* This macro is used for serial terminal on the board selected by smart configurator. + 0 = SCI UART Terminal is disabled. + 1 = SCI UART Terminal is enabled. +*/ +#define BSP_CFG_SCI_UART_TERMINAL_ENABLE (0) + +/* This macro is channel number for serial terminal. +*/ +#define BSP_CFG_SCI_UART_TERMINAL_CHANNEL (11) + +/* This macro is bit-rate for serial terminal. +*/ +#define BSP_CFG_SCI_UART_TERMINAL_BITRATE (115200) + +/* This macro is interrupt priority for serial terminal. + 0(low) - 15(high) +*/ +#define BSP_CFG_SCI_UART_TERMINAL_INTERRUPT_PRIORITY (15) + +/* This macro is used for C++ project and updated by Smart Configurator. + 0 = This project is a C project.(Not a C++ project). + 1 = This project is a C++ project. +*/ +#define BSP_CFG_CPLUSPLUS (0) + +/* Select whether to enable initilize function for TFU (fixed-point numbers). + 0 = Initialize function for TFU is disabled. (default) + 1 = Initialize function for TFU is enabled. +*/ +#define BSP_CFG_TFU_INITIALIZE_ENABLE (0) + +/* Select the unit and format setting of the input values in fixed-point sincos operations. + 0 = Unit of turn, Q1.31 format (default) + 1 = Unit of radians, Q3.29 format +*/ +#define BSP_CFG_TFU_SINCOS_INPUT_UNIT_FORMAT (0) + +/* Select the format setting of the output values in fixed-point sincos operations. + 0 = Q1.31 (default) + 1 = Q2.30 + 2 = Q3.29 +*/ +#define BSP_CFG_TFU_SINCOS_OUTPUT_FORMAT (0) + +/* Select the output format setting of output values of atan calculations in fixed-point atanhypot_k operations. + 0 = Unit of turn, Q1.31 format (default) + 1 = Unit of radians, Q3.29 format +*/ +#define BSP_CFG_TFU_ATAN_OUTPUT_UNIT_FORMAT (0) + +/* Select whether to enable bus priority initialization. + 0 = Bus priority initialization is disabled. + 1 = Bus priority initialization is enabled. +*/ +#define BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE (0) + +/* Select the priority order for memory bus 1 (RAM). + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_MEMORY_BUS1_PRIORITY (0) + +/* Select the priority order for memory bus 2 (code flash memory). + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_MEMORY_BUS2_PRIORITY (0) + +/* Select the priority order for internal peripheral bus 1. + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_INTERNAL_PERIPHERAL_BUS1_PRIORITY (0) + +/* Select the priority order for internal peripheral buses 2 and 3. + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_INTERNAL_PERIPHERAL_BUS2_3_PRIORITY (0) + +/* Select the priority order for internal peripheral buses 4 and 5. + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_INTERNAL_PERIPHERAL_BUS4_5_PRIORITY (0) + +/* Select the priority order for internal peripheral bus 6. + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_INTERNAL_PERIPHERAL_BUS6_PRIORITY (0) + +/* Select whether it is bootloader project. + 0 = This project isn't a bootloader project. + 1 = This project is a bootloader project. + NOTE: Not normally used. Set this to "1" only in the bootloader project. +*/ +#define BSP_CFG_BOOTLOADER_PROJECT (0) + +#endif /* R_BSP_CONFIG_REF_HEADER_FILE */ +