diff --git a/drivers/rx/README b/drivers/rx/README index 8855efc7..8b7a5773 100644 --- a/drivers/rx/README +++ b/drivers/rx/README @@ -86,3 +86,8 @@ Patch List: Impacted files: drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_clocks.c drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t.c + drivers/rx/rdp/src/r_sci_rx/src/targets/rx140/r_sci_rx140.c + + * Remove unnecessary include header files + Impacted files: + drivers/rx/rdp/src/r_bsp/board/generic_rx140/r_bsp.h diff --git a/drivers/rx/rdp/src/r_bsp/board/generic_rx140/r_bsp.h b/drivers/rx/rdp/src/r_bsp/board/generic_rx140/r_bsp.h new file mode 100644 index 00000000..82163c8d --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/board/generic_rx140/r_bsp.h @@ -0,0 +1,64 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : r_bsp.h +* H/W Platform : GENERIC_RX140 +* Description : Has the header files that should be included for this platform. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First release +* : 30.11.2021 1.01 Modified the include file. +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/* Make sure that no other platforms have already been defined. Do not touch this! */ +#ifdef PLATFORM_DEFINED +#error "Error - Multiple platforms defined in platform.h!" +#else +#define PLATFORM_DEFINED +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** +INCLUDE APPROPRIATE MCU AND BOARD FILES +***********************************************************************************************************************/ +#include "r_bsp_config.h" +#include "mcu/all/r_bsp_common.h" +#include "mcu/all/r_rx_compiler.h" + +#if defined(__CCRX__) +#include "mcu/rx140/register_access/ccrx/iodefine.h" +#elif defined(__GNUC__) +#include "mcu/rx140/register_access/gnuc/iodefine.h" +#elif defined(__ICCRX__) +#include "mcu/rx140/register_access/iccrx/iodefine.h" +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ +#include "mcu/rx140/r_bsp_cpu.h" +#include "mcu/rx140/r_bsp_locking.h" +#include "mcu/rx140/mcu_clocks.h" +#include "mcu/rx140/mcu_info.h" +#include "mcu/rx140/mcu_init.h" +#include "mcu/rx140/mcu_interrupts.h" +#include "mcu/rx140/mcu_locks.h" +#include "mcu/rx140/vecttbl.h" + +#include "mcu/all/r_bsp_interrupts.h" +#include "mcu/all/r_bsp_software_interrupt.h" +#include "mcu/all/r_rx_intrinsic_functions.h" + +#ifdef __cplusplus +} +#endif + +#ifndef BSP_BOARD_GENERIC_RX140 +#define BSP_BOARD_GENERIC_RX140 + +#endif /* BSP_BOARD_GENERIC_RX140 */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_clocks.c b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_clocks.c new file mode 100644 index 00000000..7d444552 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_clocks.c @@ -0,0 +1,862 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_clocks.c +* Description : Contains clock specific routines +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First Release +* : 20.08.2021 1.01 Fixed compile switch of PLL clock settings. +* Added the Waiting for the IWDT clock oscillation stabilization in +* operating_frequency_set function. +* : 30.11.2021 1.02 Added comments for when use simulator. +* : 21.11.2023 1.03 Added compile switch of BSP_CFG_BOOTLOADER_PROJECT. +* Added the bsp_mcu_clock_reset_bootloader function. +* Renamed local variable for subclock in the clock_source_select function. +* : 26.02.2025 1.04 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_CKSEL_LOCO (0x0) +#define BSP_PRV_CKSEL_HOCO (0x1) +#define BSP_PRV_CKSEL_MAIN_OSC (0x2) +#define BSP_PRV_CKSEL_SUBCLOCK (0x3) +#define BSP_PRV_CKSEL_PLL (0x4) + +#define BSP_PRV_NORMALIZE_X10 (10) /* used to avoid floating point arithmetic */ + +/* This macro runs or stops the PLL circuit. + If the following conditions are satisfied, PLL circuit will operate. + 1. System clock source is PLL circuit. + 2. Clock output enable and clock output source is PLL circuit. + */ +#if (BSP_CFG_CLOCK_SOURCE == 4) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 4)) + #define BSP_PRV_PLL_CLK_OPERATING (1) /* PLL circuit is operating. */ +#else /* PLL is not used as clock source. */ + #define BSP_PRV_PLL_CLK_OPERATING (0) /* PLL circuit is stopped. */ +#endif + +#if BSP_CFG_BOOTLOADER_PROJECT == 1 +/* Enable the following macro definitions in the bootloader project. */ +#define BSP_PRV_SCKCR_RESET_VALUE (0x33000303) +#define BSP_PRV_SCKCR3_RESET_VALUE (0x0000) +#define BSP_PRV_MEMWAITR_RESET_VALUE (0x0000) +#define BSP_PRV_MEMWAITR_RESETTING_VALUE (0xAA00) +#define BSP_PRV_PLLCR_RESET_VALUE (0x0f00) +#define BSP_PRV_PLLCR2_RESET_VALUE (0x01) +#define BSP_PRV_MOSCCR_RESET_VALUE (0x01) +#define BSP_PRV_MOSCWTCR_RESET_VALUE (0x04) +#define BSP_PRV_MOFCR_RESET_VALUE (0x00) +#define BSP_PRV_OPCCR_RESET_VALUE (0x02) +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 1 */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +static void operating_frequency_set(void); +static void clock_source_select(void); +#if BSP_CFG_BOOTLOADER_PROJECT == 0 +/* Disable the following functions in the bootloader project. */ +static void lpt_clock_source_select(void); +#if BSP_CFG_CLKOUT_OUTPUT != 0 +/* CLKOUT initial configuration function declaration */ +static void bsp_clkout_initial_configure(void); +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +/*********************************************************************************************************************** +* Function Name: get_iclk_freq_hz +* Description : Return the current ICLK frequency in Hz. Called by R_BSP_GetIClkFreqHz(). +* The system clock source can be changed at any time via SYSTEM.SCKCR3.BIT.CKSEL, so in order to +* determine the ICLK frequency we need to first find the current system clock source and then, +* in some cases where the clock source can be configured for multiple frequencies, calculate the +* frequency at which it is currently running. +* Arguments : None +* Return Value : uint32_t - the iclk frequency in Hz +***********************************************************************************************************************/ +uint32_t get_iclk_freq_hz(void) +{ + uint32_t sys_clock_src_freq; + uint32_t pll_multiplier; + + /* Casting is valid because it matches the type to the retern value. */ + uint8_t cksel = (uint8_t)SYSTEM.SCKCR3.BIT.CKSEL; + + switch (cksel) + { + case BSP_PRV_CKSEL_LOCO: + sys_clock_src_freq = BSP_LOCO_HZ; + break; + + case BSP_PRV_CKSEL_HOCO: + sys_clock_src_freq = BSP_HOCO_HZ; + break; + + case BSP_PRV_CKSEL_MAIN_OSC: + sys_clock_src_freq = BSP_CFG_XTAL_HZ; + break; + + case BSP_PRV_CKSEL_SUBCLOCK: + sys_clock_src_freq = BSP_SUB_CLOCK_HZ; + break; + + case BSP_PRV_CKSEL_PLL: + + /* Casting is valid because it matches the type to the retern value. */ + pll_multiplier = ((((uint32_t)(SYSTEM.PLLCR.BIT.STC + 1)) * BSP_PRV_NORMALIZE_X10) / 2); + + /* Casting is valid because it matches the type to the retern value. */ + sys_clock_src_freq = ((BSP_CFG_XTAL_HZ / (((uint32_t)(1 << SYSTEM.PLLCR.BIT.PLIDIV)) * BSP_PRV_NORMALIZE_X10)) * pll_multiplier); + break; + + default: + + /* Should never arrive here. Use the Main OSC freq as a default... */ + sys_clock_src_freq = BSP_CFG_XTAL_HZ; + break; + } + + /* Finally, divide the system clock source frequency by the currently set ICLK divider to get the ICLK frequency */ + return (sys_clock_src_freq / (uint32_t)(1 << SYSTEM.SCKCR.BIT.ICK)); +} /* End of function get_iclk_freq_hz() */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +* Function name: mcu_clock_setup +* Description : Contains clock functions called at device restart. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +void mcu_clock_setup(void) +{ + /* Switch to high-speed operation */ + operating_frequency_set(); +#if BSP_CFG_BOOTLOADER_PROJECT == 0 +/* Disable the following functions in the bootloader project. */ + lpt_clock_source_select(); + +#if BSP_CFG_CLKOUT_OUTPUT != 0 + bsp_clkout_initial_configure(); +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ +} /* End of function mcu_clock_setup() */ + +/*********************************************************************************************************************** +* Function name: operating_frequency_set +* Description : Configures the clock settings for each of the device clocks +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void operating_frequency_set (void) +{ + /* Used for constructing value to write to SCKCR, and SCKCR3 registers. */ + uint32_t tmp_clock = 0; + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50F; + + /* Select the clock based upon user's choice. */ + clock_source_select(); + + /* Figure out setting for FCK bits. */ +#if BSP_CFG_FCK_DIV == 1 + /* Do nothing since FCK bits should be 0. */ +#elif BSP_CFG_FCK_DIV == 2 + tmp_clock |= 0x10000000; +#elif BSP_CFG_FCK_DIV == 4 + tmp_clock |= 0x20000000; +#elif BSP_CFG_FCK_DIV == 8 + tmp_clock |= 0x30000000; +#elif BSP_CFG_FCK_DIV == 16 + tmp_clock |= 0x40000000; +#elif BSP_CFG_FCK_DIV == 32 + tmp_clock |= 0x50000000; +#elif BSP_CFG_FCK_DIV == 64 + tmp_clock |= 0x60000000; +#else + #error "Error! Invalid setting for BSP_CFG_FCK_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for ICK bits. */ +#if BSP_CFG_ICK_DIV == 1 + /* Do nothing since ICK bits should be 0. */ +#elif BSP_CFG_ICK_DIV == 2 + tmp_clock |= 0x01000000; +#elif BSP_CFG_ICK_DIV == 4 + tmp_clock |= 0x02000000; +#elif BSP_CFG_ICK_DIV == 8 + tmp_clock |= 0x03000000; +#elif BSP_CFG_ICK_DIV == 16 + tmp_clock |= 0x04000000; +#elif BSP_CFG_ICK_DIV == 32 + tmp_clock |= 0x05000000; +#elif BSP_CFG_ICK_DIV == 64 + tmp_clock |= 0x06000000; +#else + #error "Error! Invalid setting for BSP_CFG_ICK_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKB bits. */ +#if BSP_CFG_PCKB_DIV == 1 + /* Do nothing since PCKB bits should be 0. */ +#elif BSP_CFG_PCKB_DIV == 2 + tmp_clock |= 0x00000100; +#elif BSP_CFG_PCKB_DIV == 4 + tmp_clock |= 0x00000200; +#elif BSP_CFG_PCKB_DIV == 8 + tmp_clock |= 0x00000300; +#elif BSP_CFG_PCKB_DIV == 16 + tmp_clock |= 0x00000400; +#elif BSP_CFG_PCKB_DIV == 32 + tmp_clock |= 0x00000500; +#elif BSP_CFG_PCKB_DIV == 64 + tmp_clock |= 0x00000600; +#else + #error "Error! Invalid setting for BSP_CFG_PCKB_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKD bits. */ +#if BSP_CFG_PCKD_DIV == 1 + /* Do nothing since PCKD bits should be 0. */ +#elif BSP_CFG_PCKD_DIV == 2 + tmp_clock |= 0x00000001; +#elif BSP_CFG_PCKD_DIV == 4 + tmp_clock |= 0x00000002; +#elif BSP_CFG_PCKD_DIV == 8 + tmp_clock |= 0x00000003; +#elif BSP_CFG_PCKD_DIV == 16 + tmp_clock |= 0x00000004; +#elif BSP_CFG_PCKD_DIV == 32 + tmp_clock |= 0x00000005; +#elif BSP_CFG_PCKD_DIV == 64 + tmp_clock |= 0x00000006; +#else + #error "Error! Invalid setting for BSP_CFG_PCKD_DIV in r_bsp_config.h" +#endif + + /* Set SCKCR register. */ + SYSTEM.SCKCR.LONG = tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(tmp_clock == SYSTEM.SCKCR.LONG) + { + R_BSP_NOP(); + } + + /* Choose clock source. Default for r_bsp_config.h is PLL. */ + tmp_clock = ((uint16_t)BSP_CFG_CLOCK_SOURCE) << 8; + + /* Casting is valid because it matches the type to the retern value. */ + SYSTEM.SCKCR3.WORD = (uint16_t)tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if((uint16_t)tmp_clock == SYSTEM.SCKCR3.WORD) + { + R_BSP_NOP(); + } + +#if BSP_CFG_BOOTLOADER_PROJECT == 0 +/* Disable the following functions in the bootloader project. */ +#if BSP_CFG_IWDT_CLOCK_OSCILLATE_ENABLE == 1 + /* IWDT clock is stopped after reset. Oscillate the IWDT. */ + SYSTEM.ILOCOCR.BIT.ILCSTP = 0; + + /* Wait processing for the IWDT clock oscillation stabilization (80us) */ + R_BSP_SoftwareDelay((uint32_t)80, BSP_DELAY_MICROSECS); +#endif + +#if BSP_CFG_LOCO_OSCILLATE_ENABLE == 0 + /* We can now turn LOCO off since it is not going to be used. */ + SYSTEM.LOCOCR.BYTE = 0x01; + + /* Wait for five the LOCO cycles */ + /* 5 count of LOCO : (1000000/3440000)*5 = 1.453488us + 1.45 + 2 = 3.45us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)4, BSP_DELAY_MICROSECS); +#endif +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function operating_frequency_set() */ + +/*********************************************************************************************************************** +* Function name: clock_source_select +* Description : Enables and disables clocks as chosen by the user. If a clock other than LOCO or HOCO is already +* running when this function is called then that usually means a bootloader was run beforehand and set +* up the clocks already. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void clock_source_select (void) +{ +#if BSP_CFG_BOOTLOADER_PROJECT == 0 + /* Disable the following valiable in the bootloader project. */ +#if (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) || (BSP_CFG_RTC_ENABLE == 1) + uint8_t tmp_sodrv; +#endif /* (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) || (BSP_CFG_RTC_ENABLE == 1) */ +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ + + /* Set to High-speed operating mode if ICLK is > 24MHz. */ + if (BSP_ICLK_HZ > BSP_MIDDLE_SPEED_MAX_FREQUENCY) + { + /* WAIT_LOOP */ + while(1 == SYSTEM.OPCCR.BIT.OPCMTSF) + { + /* Wait for transition to finish. */ + R_BSP_NOP(); + } + + /* set to high-speed mode */ + SYSTEM.OPCCR.BYTE = 0x00; + + /* WAIT_LOOP */ + while(1 == SYSTEM.OPCCR.BIT.OPCMTSF) + { + /* Wait for transition to finish. */ + R_BSP_NOP(); + } + } + + /* At this time the MCU is still running on the 4MHz LOCO. */ + +#if BSP_CFG_HOCO_OSCILLATE_ENABLE == 1 + /* HOCO is chosen. Start it operating if it is not already operating. */ + if (1 == SYSTEM.HOCOCR.BIT.HCSTP) + { + #if BSP_CFG_HOCO_TRIMMING_ENABLE == 1 + /* Set the frequency trimming value for the HOCO. */ + SYSTEM.HOCOTRR0.BYTE = (0x3F & BSP_CFG_HOCO_TRIMMING_REG_VALUE); + #endif + + /* HOCO is chosen. Start it operating. */ + SYSTEM.HOCOCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x00 == SYSTEM.HOCOCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } + } +#endif /* BSP_CFG_HOCO_OSCILLATE_ENABLE == 1 */ + +#if BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 1 + /* Set the oscillation source of the main clock oscillator. */ + SYSTEM.MOFCR.BIT.MOSEL = BSP_CFG_MAIN_CLOCK_SOURCE; + + /* If the main oscillator is > 10MHz then the main clock oscillator + forced oscillation control register (MOFCR) must be changed. */ + if (BSP_CFG_XTAL_HZ >= 10000000) + { + /* 10 - 20MHz. */ + SYSTEM.MOFCR.BIT.MODRV21 = 1; + } + else + { + /* 1 - 10MHz. */ + SYSTEM.MOFCR.BIT.MODRV21 = 0; + } + + /* Set the oscillation stabilization wait time of the main clock oscillator. */ +#if BSP_CFG_MAIN_CLOCK_SOURCE == 0 /* Resonator */ + SYSTEM.MOSCWTCR.BYTE = BSP_CFG_MOSC_WAIT_TIME; +#elif BSP_CFG_MAIN_CLOCK_SOURCE == 1 /* External oscillator input */ + SYSTEM.MOSCWTCR.BYTE = 0x00; +#else + #error "Error! Invalid setting for BSP_CFG_MAIN_CLOCK_SOURCE in r_bsp_config.h" +#endif + + /* Set the main clock to operating. */ + SYSTEM.MOSCCR.BYTE = 0x00; + + /* WAIT_LOOP */ + while (0 == SYSTEM.OSCOVFSR.BIT.MOOVF) + { + /* Make sure clock has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } +#else /* (BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 0) */ + /* Main clock is stopped after reset. */ +#endif /* BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 1 */ + +#if BSP_CFG_BOOTLOADER_PROJECT == 0 +/* Disable the following functions in the bootloader project. */ + /* Sub-clock setting. */ + + /* Cold start setting */ + if (0 == SYSTEM.RSTSR1.BIT.CWSF) + { + + /* SOSCCR - Sub-Clock Oscillator Control Register + b7:b1 Reserved - The write value should be 0. + b0 SOSTP - Sub-clock oscillator Stop - Sub-clock oscillator is stopped. */ + SYSTEM.SOSCCR.BYTE = 0x01; + + /* WAIT_LOOP */ + while (0x01 != SYSTEM.SOSCCR.BYTE) + { + /* wait for bit to change */ + R_BSP_NOP(); + } + +#if (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* Wait for 5 sub-clock cycles (153us): measurement result is approx. 176us */ + R_BSP_SoftwareDelay(176, BSP_DELAY_MICROSECS); /* 153us * 4.56 / 4.00 (LOCO max) */ + + /* Set the drive capacity of the sub-clock oscillator */ + #if (BSP_CFG_SOSC_DRV_CAP == 0) /* Standard CL */ + tmp_sodrv = 0x00; + #elif (BSP_CFG_SOSC_DRV_CAP == 2) /* High-drive output for the low CL */ + tmp_sodrv = 0x01; + #elif (BSP_CFG_SOSC_DRV_CAP == 3) /* Middle-drive output for the low CL */ + tmp_sodrv = 0x02; + #elif (BSP_CFG_SOSC_DRV_CAP == 4) /* Low-drive output for the low CL */ + tmp_sodrv = 0x03; + #else + #error "Error! Invalid setting for BSP_CFG_SOSC_DRV_CAP in r_bsp_config.h" + #endif + + /* Set the Sub-Clock Oscillator Drive Capacity Control. */ + SYSTEM.SOMCR.BIT.SODRV = tmp_sodrv; + + /* WAIT_LOOP */ + while (tmp_sodrv != SYSTEM.SOMCR.BIT.SODRV) + { + /* wait for bits to change */ + R_BSP_NOP(); + } +#endif + +#if BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1 + /* Operate the Sub-clock oscillator */ + SYSTEM.SOSCCR.BYTE = 0x00; + + /* WAIT_LOOP */ + while (0x00 != SYSTEM.SOSCCR.BYTE) + { + /* wait for bit to change */ + R_BSP_NOP(); + } + + /* Wait for the oscillation stabilization time of the sub-clock. */ + R_BSP_SoftwareDelay(BSP_CFG_SOSC_WAIT_TIME, BSP_DELAY_MILLISECS); +#endif + +#if (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 0) && (BSP_CFG_RTC_ENABLE == 1) + /* Wait for the oscillation stabilization time of the sub-clock. */ + R_BSP_SoftwareDelay(BSP_CFG_SOSC_WAIT_TIME, BSP_DELAY_MILLISECS); +#endif + +#if (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* Wait for six the sub-clock cycles */ + /* 6 count of sub-clock : (1000000/32768)*6=183.10546875us + In the case of LOCO frequency is 264kHz : 183.10546875/(1000000/264000)=48.33984375cycle + (48.33984375+2)*(1000000/240000)=209.7493489583333us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)210, BSP_DELAY_MICROSECS); +#endif + +#if (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) && (BSP_CFG_RTC_ENABLE == 0) + /* Stop prescaler and counter */ + /* RCR2 - RTC Control Register 2 + b7 CNTMD - Count Mode Select - The calendar count mode. + b6 HR24 - Hours Mode - The RTC operates in 24-hour mode. + b5 AADJP - Automatic Adjustment Period Select - The RADJ.ADJ[5:0] setting value is adjusted from + the count value of the prescaler every 10 seconds. + b4 AADJE - Automatic Adjustment Enable - Automatic adjustment is enabled. + b3 RTCOE - RTCOUT Output Enable - RTCOUT output enabled. + b2 ADJ30 - 30-Second Adjustment - 30-second adjustment is executed. + b1 RESET - RTC Software Reset - The prescaler and the target registers for RTC software reset are initialized. + b0 START - start - Prescaler is stopped. */ + RTC.RCR2.BYTE &= 0x7E; + + /* WAIT_LOOP */ + while (0 != RTC.RCR2.BIT.START) + { + /* Confirm that the written value can be read correctly. */ + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while (0 != RTC.RCR2.BIT.CNTMD) + { + /* Confirm that the written value can be read correctly. */ + R_BSP_NOP(); + } + + /* RTC Software Reset */ + RTC.RCR2.BIT.RESET = 1; + + /* WAIT_LOOP */ + while (0 != RTC.RCR2.BIT.RESET) + { + /* Confirm that the written value can be read correctly. + If you use simulator, the flag is not set to 0, resulting in an infinite loop. */ + R_BSP_NOP(); + } + + /* An alarm interrupt request is disabled */ + /* RCR1 - RTC Control Register 1 + b7:b4 PES - Periodic Interrupt Select - These bits specify the period for the periodic interrupt. + b3 RTCOS - RTCOUT Output Select - RTCOUT outputs 1 Hz. + b2 PIE - Periodic Interrupt Enable - A periodic interrupt request is disabled. + b1 CIE - Carry Interrupt Enable - A carry interrupt request is disabled. + b0 AIE - Alarm Interrupt Enable - An alarm interrupt request is disabled. */ + RTC.RCR1.BYTE &= 0xF8; + + /* WAIT_LOOP */ + while (0 != (0x07 & RTC.RCR1.BYTE)) + { + /* Confirm that the written value can be read correctly. */ + R_BSP_NOP(); + } +#endif /* (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) && (BSP_CFG_RTC_ENABLE == 0) */ + } + /* Warm start setting */ + else + { +#if BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 0 + /* SOSCCR - Sub-Clock Oscillator Control Register + b7:b1 Reserved - The write value should be 0. + b0 SOSTP - Sub-clock oscillator Stop - Sub-clock oscillator is stopped. */ + SYSTEM.SOSCCR.BYTE = 0x01; + + /* WAIT_LOOP */ + while (0x01 != SYSTEM.SOSCCR.BYTE) + { + /* wait for bit to change */ + R_BSP_NOP(); + } +#endif + } +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ + +#if BSP_PRV_PLL_CLK_OPERATING == 1 + /* PLL is chosen. Start it operating if it is not already. Must start main clock as well since PLL uses it. */ + + /* Set PLL Input Divisor. */ + SYSTEM.PLLCR.BIT.PLIDIV = BSP_CFG_PLL_DIV >> 1; + + /* Set PLL Multiplier. */ + SYSTEM.PLLCR.BIT.STC = (BSP_CFG_PLL_MUL * 2) - 1; + + /* Set the PLL to operating. */ + SYSTEM.PLLCR2.BYTE = 0x00; + + /* WAIT_LOOP */ + while (0 == SYSTEM.OSCOVFSR.BIT.PLOVF) + { + /* Make sure clock has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } +#endif + + /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn + it off until another clock has been enabled and is ready to use. */ +#if BSP_CFG_LOCO_OSCILLATE_ENABLE == 1 + /* LOCO is chosen. This is the default out of reset. */ +#else + /* LOCO is not chosen but it cannot be turned off yet since it is still being used. */ +#endif + + /* Set to memory wait if ICLK is > 32MHz. */ + if( BSP_ICLK_HZ > BSP_MEMORY_NO_WAIT_MAX_FREQUENCY ) + { + /* Use wait states */ + FLASH.MEMWAITR.WORD = 0xAA01; + + /* WAIT_LOOP */ + while (0x0001 != FLASH.MEMWAITR.WORD) + { + /* wait for bit to set */ + R_BSP_NOP(); + } + } +} /* End of function clock_source_select() */ + +#if BSP_CFG_BOOTLOADER_PROJECT == 0 + /* Disable the following functions in the bootloader project. */ +/*********************************************************************************************************************** +* Function name: lpt_clock_source_select +* Description : Enables clock sources for the lpt (if not already done) as chosen by the user. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void lpt_clock_source_select (void) +{ + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50F; + + /* INITIALIZE AND SELECT LPT CLOCK SOURCE */ + +#if (BSP_CFG_LPT_CLOCK_SOURCE == 0) || (BSP_CFG_LPT_CLOCK_SOURCE == 2) + /* Sub-clock or None is chosen. */ + /* sub-clock oscillator already initialized in clock_source_select() */ + +#elif (BSP_CFG_LPT_CLOCK_SOURCE == 1) + /* IWDTCLK is chosen. Start it operating. */ + SYSTEM.ILOCOCR.BYTE = 0x00; + + /* Wait processing for the IWDT clock oscillation stabilization (50us) */ + R_BSP_SoftwareDelay((uint32_t)50, BSP_DELAY_MICROSECS); + + /* Controls whether to stop the IWDT counter in a low power consumption state. + IWDTCSTPR - IWDT Count Stop Control Register + b7 SLCSTP - Sleep Mode Count Stop Control - Count stop is disabled. + b6:b1 Reserved - These bits are read as 0. Writing to these bits has no effect. */ + IWDT.IWDTCSTPR.BIT.SLCSTP = 0; +#elif (BSP_CFG_LPT_CLOCK_SOURCE == 3) + /* LOCO is chosen. */ + /* LOCO already initialized in clock_source_select() */ +#endif + + /* Enable protect bit */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function lpt_clock_source_select() */ + +#if BSP_CFG_CLKOUT_OUTPUT != 0 +/*********************************************************************************************************************** +* Function name: bsp_clkout_initial_configure +* Description : Configures the CLKOUT initial settings +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void bsp_clkout_initial_configure(void) +{ + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50B; + + /* Set the CLKOUT Output Divisor Select. */ + SYSTEM.CKOCR.BIT.CKODIV = BSP_CFG_CLKOUT_DIV; + + /* Set the CLKOUT Output Source Select. */ + SYSTEM.CKOCR.BIT.CKOSEL = BSP_CFG_CLKOUT_SOURCE; +#if BSP_CFG_CLKOUT_OUTPUT == 1 + + /* Set the CLKOUT Output Stop Control. */ + SYSTEM.CKOCR.BIT.CKOSTP = 0; +#elif BSP_CFG_CLKOUT_OUTPUT == 0 + /* do nothing */ +#else + #error "Error! Invalid setting for BSP_CFG_CLKOUT_OUTPUT in r_bsp_config.h" +#endif + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function bsp_clkout_initial_configure() */ +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ + +#if BSP_CFG_BOOTLOADER_PROJECT == 1 +/*********************************************************************************************************************** +* Function name: bsp_mcu_clock_reset_bootloader +* Description : Returns the MCU clock settings to the reset state. The system clock returns to LOCO. PLL circuit will +* stop. Main clock will stop. +* Arguments : none +* Return value : none +* Note : Enable this functions in the bootloader project. This function for bootloader only. +***********************************************************************************************************************/ +void bsp_mcu_clock_reset_bootloader (void) +{ + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA503; + + /* Is not Clock source LOCO? */ + if(BSP_PRV_SCKCR3_RESET_VALUE != SYSTEM.SCKCR3.WORD) + { + /* Reset clock source. Change to LOCO. */ + SYSTEM.SCKCR3.WORD = BSP_PRV_SCKCR3_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_SCKCR3_RESET_VALUE == SYSTEM.SCKCR3.WORD) + { + R_BSP_NOP(); + } + } + + /* Is not SCKCR reset value? */ + if(BSP_PRV_SCKCR_RESET_VALUE != SYSTEM.SCKCR.LONG) + { + /* Reset SCKCR register. */ + SYSTEM.SCKCR.LONG = BSP_PRV_SCKCR_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_SCKCR_RESET_VALUE == SYSTEM.SCKCR.LONG) + { + R_BSP_NOP(); + } + } + + /* Is not MEMWAITR reset value? */ + if(BSP_PRV_MEMWAITR_RESET_VALUE != FLASH.MEMWAITR.WORD) + { + /* Reset Memory Wait Cycle */ + FLASH.MEMWAITR.WORD = BSP_PRV_MEMWAITR_RESETTING_VALUE; + + /* WAIT_LOOP */ + while (BSP_PRV_MEMWAITR_RESET_VALUE != FLASH.MEMWAITR.WORD) + { + /* wait for bit to set */ + R_BSP_NOP(); + } + } + +#if BSP_PRV_PLL_CLK_OPERATING == 1 + /* PLL operating? */ + if(BSP_PRV_PLLCR2_RESET_VALUE != SYSTEM.PLLCR2.BYTE) + { + /* Stop PLL. */ + SYSTEM.PLLCR2.BYTE = BSP_PRV_PLLCR2_RESET_VALUE; + + /* WAIT_LOOP */ + while(1 == SYSTEM.OSCOVFSR.BIT.PLOVF) + { + /* The delay period needed is to make sure that the PLL has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } + } + + /* Is not PLLCR reset value? */ + if(BSP_PRV_PLLCR_RESET_VALUE != SYSTEM.PLLCR.WORD) + { + /* Reset PLL. */ + SYSTEM.PLLCR.WORD = BSP_PRV_PLLCR_RESET_VALUE; + } +#endif /* BSP_PRV_PLL_CLK_OPERATING == 1 */ + +#if BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 1 + /* main clock operating? */ + if(BSP_PRV_MOSCCR_RESET_VALUE != SYSTEM.MOSCCR.BYTE) + { + /* Stop the main clock. */ + SYSTEM.MOSCCR.BYTE = BSP_PRV_MOSCCR_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_MOSCCR_RESET_VALUE == SYSTEM.MOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while(1 == SYSTEM.OSCOVFSR.BIT.MOOVF) + { + /* The delay period needed is to make sure that the Main clock has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } + } + + /* Is not MOSCWTCR reset value? */ + if(BSP_PRV_MOSCWTCR_RESET_VALUE != SYSTEM.MOSCWTCR.BYTE) + { + /* Reset MOSCWTCR */ + SYSTEM.MOSCWTCR.BYTE = BSP_PRV_MOSCWTCR_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_MOSCWTCR_RESET_VALUE == SYSTEM.MOSCWTCR.BYTE) + { + R_BSP_NOP(); + } + } + + /* Is not MOFCR reset value? */ + if(BSP_PRV_MOFCR_RESET_VALUE != SYSTEM.MOFCR.BYTE) + { + /* Reset MOFCR */ + SYSTEM.MOFCR.BYTE = BSP_PRV_MOFCR_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_MOFCR_RESET_VALUE == SYSTEM.MOFCR.BYTE) + { + R_BSP_NOP(); + } + } +#endif /* BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 1 */ + + /* Initialization of other clock-related registers. */ + /* Is not OPCCR reset value? */ + if(BSP_PRV_OPCCR_RESET_VALUE != SYSTEM.OPCCR.BYTE) + { + /* WAIT_LOOP */ + while(1 == SYSTEM.OPCCR.BIT.OPCMTSF) + { + /* Wait for transition to finish. */ + R_BSP_NOP(); + } + + /* Reset OPCCR register. */ + SYSTEM.OPCCR.BYTE = BSP_PRV_OPCCR_RESET_VALUE; + + /* WAIT_LOOP */ + while(1 == SYSTEM.OPCCR.BIT.OPCMTSF) + { + /* Wait for transition to finish. */ + R_BSP_NOP(); + } + } + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function bsp_mcu_clock_reset_bootloader() */ +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 1 */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_clocks.h b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_clocks.h new file mode 100644 index 00000000..2beb8996 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_clocks.h @@ -0,0 +1,45 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_clocks.h +* Description : Contains clock specific routines. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First Release +* : 21.11.2023 1.01 Added definition of bsp_mcu_clock_reset_bootloader function. +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_CLOCKS_H +#define MCU_CLOCKS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +uint32_t get_iclk_freq_hz(void); +void mcu_clock_setup(void); + +#if BSP_CFG_BOOTLOADER_PROJECT == 1 +/* Enable the following functions in the bootloader project. */ +void bsp_mcu_clock_reset_bootloader(void); +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 1 */ + +/* End of multiple inclusion prevention macro */ +#endif + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_info.h b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_info.h new file mode 100644 index 00000000..344eadf7 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_info.h @@ -0,0 +1,195 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_info.h +* Device(s) : RX140 +* Description : Information about the MCU. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First release +* : 30.11.2021 1.01 Deleted the compile switch for BSP_CFG_MCU_PART_SERIES and BSP_CFG_MCU_PART_GROUP. +* : 22.04.2022 1.02 Added version check of smart configurator. +* : 26.02.2025 1.03 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Gets MCU configuration information. */ +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INFO +#define MCU_INFO + +#if BSP_CFG_CONFIGURATOR_VERSION < 2120 + /* The following macros are updated to invalid value by Smart configurator if you are using Smart Configurator for + RX V2.11.0 (equivalent to e2 studio 2021-10) or earlier version. + - BSP_CFG_MCU_PART_GROUP, BSP_CFG_MCU_PART_SERIES + The following macros are not updated by Smart configurator if you are using Smart Configurator for RX V2.11.0 + (equivalent to e2 studio 2021-10) or earlier version. + - BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE, BSP_CFG_HOCO_OSCILLATE_ENABLE, BSP_CFG_LOCO_OSCILLATE_ENABLE, + BSP_CFG_IWDT_CLOCK_OSCILLATE_ENABLE, BSP_CFG_CPLUSPLUS + Please update Smart configurator to Smart Configurator for RX V2.12.0 (equivalent to e2 studio 2022-01) or + later version. + */ + #error "To use this version of BSP, you need to upgrade Smart configurator. Please upgrade Smart configurator. If you don't use Smart Configurator, please change value of BSP_CFG_CONFIGURATOR_VERSION in r_bsp_config.h." +#endif + +/* MCU CPU Version */ +#define BSP_MCU_CPU_VERSION (2) + +/* CPU cycles. Known number of RXv2 CPU cycles required to execute the delay_wait() loop */ +#define CPU_CYCLES_PER_LOOP (4) + +/* MCU Series. */ +#define BSP_MCU_SERIES_RX100 (1) + +/* This macro means that this MCU is part of the RX13x collection of MCUs (i.e. RX140). */ +#define BSP_MCU_RX14_ALL (1) + +/* MCU Group name. */ +#define BSP_MCU_RX140 (1) + +/* Package. */ +#if BSP_CFG_MCU_PART_PACKAGE == 0xB + #define BSP_PACKAGE_LFQFP80 (1) + #define BSP_PACKAGE_PINS (80) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x0 + #define BSP_PACKAGE_LFQFP64 (1) + #define BSP_PACKAGE_PINS (64) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x1 + #define BSP_PACKAGE_LQFP64 (1) + #define BSP_PACKAGE_PINS (64) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x3 + #define BSP_PACKAGE_LFQFP48 (1) + #define BSP_PACKAGE_PINS (48) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x4 + #define BSP_PACKAGE_HWQFN48 (1) + #define BSP_PACKAGE_PINS (48) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x2 + #define BSP_PACKAGE_LFQFP32 (1) + #define BSP_PACKAGE_PINS (32) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x5 + #define BSP_PACKAGE_HWQFN32 (1) + #define BSP_PACKAGE_PINS (32) +#else + #error "ERROR - BSP_CFG_MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h" +#endif + +/* Memory size of your MCU. */ +#if BSP_CFG_MCU_PART_MEMORY_SIZE == 0x3 + #define BSP_ROM_SIZE_BYTES (65536) + #define BSP_RAM_SIZE_BYTES (16384) + #define BSP_DATA_FLASH_SIZE_BYTES (4096) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x5 + #define BSP_ROM_SIZE_BYTES (131072) + #define BSP_RAM_SIZE_BYTES (32768) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x6 + #define BSP_ROM_SIZE_BYTES (262144) + #define BSP_RAM_SIZE_BYTES (65536) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) +#else + #error "ERROR - BSP_CFG_MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h" +#endif + +/* These macros define clock speeds for fixed speed clocks. */ +#define BSP_LOCO_HZ (4000000) +#if ((BSP_CFG_OFS1_REG_VALUE & 0x00003000) == 0x00000000) || ((BSP_CFG_OFS1_REG_VALUE & 0x00003000) == 0x00001000) + #define BSP_HOCO_HZ (48000000) +#elif ((BSP_CFG_OFS1_REG_VALUE & 0x00003000) == 0x00002000) + #define BSP_HOCO_HZ (24000000) +#elif ((BSP_CFG_OFS1_REG_VALUE & 0x00003000) == 0x00003000) + #define BSP_HOCO_HZ (32000000) +#endif + +#define BSP_SUB_CLOCK_HZ (32768) +#define BSP_ILOCO_HZ (15000) + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit +*/ +#if BSP_CFG_CLOCK_SOURCE == 0 + #define BSP_SELECTED_CLOCK_HZ (BSP_LOCO_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 1 + #define BSP_SELECTED_CLOCK_HZ (BSP_HOCO_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 2 + #define BSP_SELECTED_CLOCK_HZ (BSP_CFG_XTAL_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 3 + #define BSP_SELECTED_CLOCK_HZ (BSP_SUB_CLOCK_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 4 + #define BSP_SELECTED_CLOCK_HZ ((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) +#else + #error "ERROR - BSP_CFG_CLOCK_SOURCE - Unknown clock source chosen in r_bsp_config.h" +#endif + +/* LPT clock speed in Hz */ +#if BSP_CFG_LPT_CLOCK_SOURCE == 0 + #define BSP_LPTSRCCLK_HZ (BSP_SUB_CLOCK_HZ) +#elif BSP_CFG_LPT_CLOCK_SOURCE == 1 + #define BSP_LPTSRCCLK_HZ (BSP_ILOCO_HZ) /* IWDTCLK typical frequency */ +#elif BSP_CFG_LPT_CLOCK_SOURCE == 2 + /* LPT none use */ +#elif BSP_CFG_LPT_CLOCK_SOURCE == 3 + #define BSP_LPTSRCCLK_HZ (BSP_LOCO_HZ/4) +#else + #error "ERROR - BSP_CFG_LPT_CLOCK_SOURCE - Unknown lpt clock source chosen in r_bsp_config.h" +#endif + +/* System clock speed in Hz. */ +#define BSP_ICLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_ICK_DIV) +/* Peripheral Module Clock B speed in Hz. */ +#define BSP_PCLKB_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKB_DIV) +/* Peripheral Module Clock D speed in Hz. */ +#define BSP_PCLKD_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKD_DIV) +/* FlashIF clock speed in Hz. */ +#define BSP_FCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_FCK_DIV) + +/* Null argument definitions. */ +#define FIT_NO_FUNC ((void (*)(void *))0x10000000) /* Reserved space on RX */ +#define FIT_NO_PTR ((void *)0x10000000) /* Reserved space on RX */ + +/* Mininum and maximum IPL levels available for this MCU. */ +#define BSP_MCU_IPL_MAX (0xF) +#define BSP_MCU_IPL_MIN (0) + +/* Maximum frequency on Middle-speed operating mode. */ +#define BSP_MIDDLE_SPEED_MAX_FREQUENCY (24000000) +/* Maximum frequency to not need memory wait. */ +#define BSP_MEMORY_NO_WAIT_MAX_FREQUENCY (32000000) + +/* MCU functions */ +#define BSP_MCU_REGISTER_WRITE_PROTECTION +#define BSP_MCU_RCPC_PRC0 +#define BSP_MCU_RCPC_PRC1 +#define BSP_MCU_RCPC_PRC2 +#define BSP_MCU_RCPC_PRC3 +#define BSP_MCU_FLOATING_POINT +#define BSP_MCU_EXCEPTION_TABLE +#define BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +#define BSP_MCU_EXCEP_UNDEFINED_INST_ISR +#define BSP_MCU_EXCEP_FLOATING_POINT_ISR +#define BSP_MCU_NON_MASKABLE_ISR +#define BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +#define BSP_MCU_BUS_ERROR_ISR + +#define BSP_MCU_NMI_EXC_NMI_PIN +#define BSP_MCU_NMI_OSC_STOP_DETECT +#define BSP_MCU_NMI_IWDT_ERROR +#define BSP_MCU_NMI_LVD1 +#define BSP_MCU_NMI_LVD2 + +#endif /* MCU_INFO */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_init.c b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_init.c new file mode 100644 index 00000000..ac632991 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_init.c @@ -0,0 +1,171 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_init.c +* Description : Performs initialization common to all MCUs in this Group +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First Release +* : 20.08.2021 1.01 Fixed the initial value of PDR register of PORTH for 80 and 64 pins. +* : 11.02.2022 1.02 Fixed the initial value of PDR register of PORTH for 80 and 64 pins. +* : 26.02.2025 1.03 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Get specifics on this MCU. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* RX MCUs come in different packages and different pin counts. For MCUs that do not have the maximum number of pins + * for their group (e.g. MCU with 100 pins when maximum is 144 pins) these 'non-existent' pins that are not bonded out + * need to be initialized to save power. The macros below define the non-existent pins on each port for smaller + * pin count MCUs. If a pin is non-existent then its value is set to a 1. These values are then ORed into the + * direction registers to set non-existent pins as outputs which can help save power. + */ +#if BSP_PACKAGE_PINS == 80 + /* Refer User's Manual: Hardware Table 18.3. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0x07) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x03) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x3C) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x08) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0xCF) + #define BSP_PRV_PORTA_NE_PIN_MASK (0x80) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x03) + #define BSP_PRV_PORTD_NE_PIN_MASK (0xF8) + #define BSP_PRV_PORTE_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORTG_NE_PIN_MASK (0x7F) + #define BSP_PRV_PORTH_NE_PIN_MASK (0x30) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0x3D) +#elif BSP_PACKAGE_PINS == 64 + /* Refer User's Manual: Hardware Table 18.4. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0xD7) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x0F) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x3F) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x18) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) + #define BSP_PRV_PORT5_NE_PIN_MASK (0xCF) + #define BSP_PRV_PORTA_NE_PIN_MASK (0xA4) + #define BSP_PRV_PORTB_NE_PIN_MASK (0x14) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x03) + #define BSP_PRV_PORTD_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTE_NE_PIN_MASK (0xC0) + #define BSP_PRV_PORTG_NE_PIN_MASK (0x7F) + #if BSP_CFG_MCU_PART_MEMORY_SIZE == 0x3 + #define BSP_PRV_PORTH_NE_PIN_MASK (0xF0) + #else + #define BSP_PRV_PORTH_NE_PIN_MASK (0x30) + #endif + #define BSP_PRV_PORTJ_NE_PIN_MASK (0x3F) +#elif BSP_PACKAGE_PINS == 48 + /* Refer User's Manual: Hardware Table 18.5. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x0F) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x3F) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x1C) + #define BSP_PRV_PORT4_NE_PIN_MASK (0x18) + #define BSP_PRV_PORT5_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTA_NE_PIN_MASK (0xA5) + #define BSP_PRV_PORTB_NE_PIN_MASK (0xD4) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x0F) + #define BSP_PRV_PORTD_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTE_NE_PIN_MASK (0xE1) + #define BSP_PRV_PORTG_NE_PIN_MASK (0x7F) + #define BSP_PRV_PORTH_NE_PIN_MASK (0xF0) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0x3F) +#elif BSP_PACKAGE_PINS == 32 + /* Refer User's Manual: Hardware Table 18.6. */ + #define BSP_PRV_PORT0_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORT1_NE_PIN_MASK (0x3F) + #define BSP_PRV_PORT2_NE_PIN_MASK (0x3F) + #define BSP_PRV_PORT3_NE_PIN_MASK (0x9C) + #define BSP_PRV_PORT4_NE_PIN_MASK (0xF8) + #define BSP_PRV_PORT5_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTA_NE_PIN_MASK (0xE5) + #define BSP_PRV_PORTB_NE_PIN_MASK (0xFE) + #define BSP_PRV_PORTC_NE_PIN_MASK (0x0F) + #define BSP_PRV_PORTD_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTE_NE_PIN_MASK (0xE1) + #define BSP_PRV_PORTG_NE_PIN_MASK (0x7F) + #define BSP_PRV_PORTH_NE_PIN_MASK (0xFF) + #define BSP_PRV_PORTJ_NE_PIN_MASK (0x3F) +#else + #error "ERROR - This package is not defined in mcu_init.c" +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_non_existent_port_init +* Description : For MCUs that do not have the 'non-existent' pins for their group (e.g. MCU with 100 pins when +* maximum is 144 pins) these 'non-existent' pins that are not bonded out need to be initialized to save +* power. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_non_existent_port_init (void) +{ + /* OR in missing pin masks from above. */ + + /* Set PORT0.PDR */ + PORT0.PDR.BYTE |= BSP_PRV_PORT0_NE_PIN_MASK; + + /* Set PORT1.PDR */ + PORT1.PDR.BYTE |= BSP_PRV_PORT1_NE_PIN_MASK; + + /* Set PORT2.PDR */ + PORT2.PDR.BYTE |= BSP_PRV_PORT2_NE_PIN_MASK; + + /* Set PORT3.PDR */ + PORT3.PDR.BYTE |= BSP_PRV_PORT3_NE_PIN_MASK; + + /* Set PORT4.PDR */ + PORT4.PDR.BYTE |= BSP_PRV_PORT4_NE_PIN_MASK; + + /* Set PORT5.PDR */ + PORT5.PDR.BYTE |= BSP_PRV_PORT5_NE_PIN_MASK; + + /* Set PORTA.PDR */ + PORTA.PDR.BYTE |= BSP_PRV_PORTA_NE_PIN_MASK; + + /* Set PORTB.PDR */ + PORTB.PDR.BYTE |= BSP_PRV_PORTB_NE_PIN_MASK; + + /* Set PORTC.PDR */ + PORTC.PDR.BYTE |= BSP_PRV_PORTC_NE_PIN_MASK; + + /* Set PORTD.PDR */ + PORTD.PDR.BYTE |= BSP_PRV_PORTD_NE_PIN_MASK; + + /* Set PORTE.PDR */ + PORTE.PDR.BYTE |= BSP_PRV_PORTE_NE_PIN_MASK; + + /* Set PORTG.PDR */ + PORTG.PDR.BYTE |= BSP_PRV_PORTG_NE_PIN_MASK; + + /* Set PORTH.PDR */ + PORTH.PDR.BYTE |= BSP_PRV_PORTH_NE_PIN_MASK; + + /* Set PORTJ.PDR */ + PORTJ.PDR.BYTE |= BSP_PRV_PORTJ_NE_PIN_MASK; +} /* End of function bsp_non_existent_port_init() */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_init.h b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_init.h new file mode 100644 index 00000000..1ee7f886 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_init.h @@ -0,0 +1,37 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_init.h +* Description : Performs initialization common to all MCUs in this Group +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First release +* : 26.02.2025 1.01 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INIT_H +#define MCU_INIT_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void bsp_non_existent_port_init(void); //r_bsp internal function. DO NOT CALL. + +#endif /* MCU_INIT_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_interrupts.c b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_interrupts.c new file mode 100644 index 00000000..5212bb59 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_interrupts.c @@ -0,0 +1,205 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.c +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First Release +* : 21.11.2023 1.01 Added timeout detection processing to bus error processing. +* Added processing to control only illegal address access detection to bus error +* processing. +* Added processing to control only timeout detection to bus error processing. +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Access to r_bsp. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Let FPSW EV, EO, EZ, EU, EX=1 (FPU exceptions enabled.) */ +#define BSP_PRV_FPU_EXCEPTIONS_ENABLE (0x00007C00) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_interrupt_enable_disable +* Description : Either enables or disables an interrupt. +* Arguments : vector - +* Which vector to enable or disable. +* enable - +* Whether to enable or disable the interrupt. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_UNSUPPORTED - +* API does not support enabling/disabling for this vector. +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable (bsp_int_src_t vector, bool enable) +{ +#ifdef __FPU + uint32_t tmp_fpsw; +#endif + bsp_int_err_t err = BSP_INT_SUCCESS; + + switch (vector) + { + case (BSP_INT_SRC_BUS_ERROR): + if (true == enable) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU*/ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + + /* Enable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 1; + + /* Enable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 1; + } + else + { + /* Disable the bus error interrupt. */ + /* Disable the interrupt in the ICU*/ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + + /* Disable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 0; + + /* Disable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 0; + } + break; + + case (BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS): + if (true == enable) + { + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU. */ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + } + + /* Enable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 1; + } + else + { + /* Disable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 0; + + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Disable the bus error interrupt in the ICU. */ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + } + } + break; + + case (BSP_INT_SRC_BUS_ERROR_TIMEOUT): + if (true == enable) + { + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU. */ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + } + + /* Enable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 1; + } + else + { + /* Disable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 0; + + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Disable the bus error interrupt in the ICU. */ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + } + } + break; + +#ifdef __FPU + case (BSP_INT_SRC_EXC_FPU): + + /* Get current FPSW. */ + tmp_fpsw = (uint32_t)R_BSP_GET_FPSW(); + + if (true == enable) + { + /* Set the FPU exception flags. */ + R_BSP_SET_FPSW(tmp_fpsw | (uint32_t)BSP_PRV_FPU_EXCEPTIONS_ENABLE); + } + else + { + /* Clear only the FPU exception flags. */ + R_BSP_SET_FPSW(tmp_fpsw & (uint32_t)~BSP_PRV_FPU_EXCEPTIONS_ENABLE); + } + break; +#endif + + case (BSP_INT_SRC_EXC_NMI_PIN): + if (true == enable) + { + /* Enable NMI pin interrupt (cannot undo!) */ + ICU.NMIER.BIT.NMIEN = 1; + } + else + { + /* NMI pin interrupts cannot be disabled after being enabled. */ + err = BSP_INT_ERR_UNSUPPORTED; + } + break; + + default: + err = BSP_INT_ERR_UNSUPPORTED; + break; + } + + return err; +} /* End of function bsp_interrupt_enable_disable() */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_interrupts.h b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_interrupts.h new file mode 100644 index 00000000..21bedcbc --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_interrupts.h @@ -0,0 +1,101 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.h +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First Release +* : 21.11.2023 1.01 Added the following enumeration constant. +* - BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS +* - BSP_INT_SRC_BUS_ERROR_TIMEOUT +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INTERRUPTS_H +#define MCU_INTERRUPTS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Available return codes. */ +typedef enum +{ + BSP_INT_SUCCESS = 0, + BSP_INT_ERR_NO_REGISTERED_CALLBACK, /* There is not a registered callback for this interrupt source */ + BSP_INT_ERR_INVALID_ARG, /* Illegal argument input */ + BSP_INT_ERR_UNSUPPORTED, /* Operation is not supported by this API */ + BSP_INT_ERR_INVALID_IPL /* Illegal IPL value input */ +} bsp_int_err_t; + +/* Available interrupts to register a callback for. */ +typedef enum +{ + BSP_INT_SRC_EXC_SUPERVISOR_INSTR = 0, /* Occurs when privileged instruction is executed in User Mode */ + BSP_INT_SRC_EXC_UNDEFINED_INSTR, /* Occurs when MCU encounters an unknown instruction */ + BSP_INT_SRC_EXC_NMI_PIN, /* NMI Pin interrupt */ + BSP_INT_SRC_EXC_FPU, /* FPU exception */ + BSP_INT_SRC_OSC_STOP_DETECT, /* Oscillation stop is detected */ + BSP_INT_SRC_IWDT_ERROR, /* IWDT underflow/refresh error has occurred */ + BSP_INT_SRC_LVD1, /* Voltage monitoring 1 interrupt */ + BSP_INT_SRC_LVD2, /* Voltage monitoring 2 interrupt */ + BSP_INT_SRC_UNDEFINED_INTERRUPT, /* Interrupt has triggered for a vector that user did not write a handler. */ + BSP_INT_SRC_BUS_ERROR, /* Bus error: illegal address access or timeout */ + BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS, /* Bus error: illegal address access. Use this when you want to set only Illegal address access detection. */ + BSP_INT_SRC_BUS_ERROR_TIMEOUT, /* Bus error: timeout. Use this when you want to set only Bus timeout detection. */ + BSP_INT_SRC_EMPTY, + BSP_INT_SRC_TOTAL_ITEMS /* DO NOT MODIFY! This is used for sizing the interrupt callback array. */ +} bsp_int_src_t; + +/* Available commands for R_BSP_InterruptControl() function. */ +typedef enum +{ + BSP_INT_CMD_CALL_CALLBACK = 0, /* Calls registered callback function if one exists */ + BSP_INT_CMD_INTERRUPT_ENABLE, /* Enables a given interrupt (Available for NMI pin and Bus Error) */ + BSP_INT_CMD_INTERRUPT_DISABLE, /* Disables a given interrupt (Available for Bus Error) */ + BSP_INT_CMD_FIT_INTERRUPT_ENABLE, /* Enables interrupt by control of IPL. */ + BSP_INT_CMD_FIT_INTERRUPT_DISABLE /* Disables interrupt by control of IPL. */ +} bsp_int_cmd_t; + +/* Type to be used for pdata argument in Control function. */ +typedef union +{ + uint32_t ipl; /* Used at the following times. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command. + - When disabling an interrupt to save that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_DISABLE command. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_ENABLE command. */ +} bsp_int_ctrl_t; + +/* Easy to use typedef for callback functions. */ +typedef void (*bsp_int_cb_t)(void *); + +/* This structure is the common one that is passed as the 'void *' argument to callback functions when an + * exception occurs. + */ +typedef struct +{ + bsp_int_src_t vector; /* Which vector caused this interrupt */ +} bsp_int_cb_args_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable(bsp_int_src_t vector, bool enable); + +#endif /* MCU_INTERRUPTS_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_locks.h b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_locks.h new file mode 100644 index 00000000..8c4fbbbc --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/mcu_locks.h @@ -0,0 +1,123 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_locks.h +* Device(s) : RX140 +* Description : This source file has 1 lock per MCU resource. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First release +* : 26.02.2025 1.01 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Gets MCU configuration information. */ +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_LOCKS_H +#define MCU_LOCKS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* This enum defines all of the available hardware locks for this MCU. If you delete an entry out of this list then you + will decrease the size of the locks array but will not be able to use that lock. For example, if your design is not + using CAN at all then you can safely remove the BSP_LOCK_CAN# entries below. */ +typedef enum +{ + BSP_LOCK_BSC = 0, + BSP_LOCK_CAC, + BSP_LOCK_CAN, + BSP_LOCK_CAN0, + BSP_LOCK_CMPB, + BSP_LOCK_CMT, + BSP_LOCK_CMT0, + BSP_LOCK_CMT1, + BSP_LOCK_CRC, + BSP_LOCK_CTSU, + BSP_LOCK_DA, + BSP_LOCK_DOC, + BSP_LOCK_DTC, + BSP_LOCK_ELC, + BSP_LOCK_FLASH, + BSP_LOCK_ICU, + BSP_LOCK_IRQ0, + BSP_LOCK_IRQ1, + BSP_LOCK_IRQ2, + BSP_LOCK_IRQ3, + BSP_LOCK_IRQ4, + BSP_LOCK_IRQ5, + BSP_LOCK_IRQ6, + BSP_LOCK_IRQ7, + BSP_LOCK_IWDT, + BSP_LOCK_LPT, + BSP_LOCK_MPC, + BSP_LOCK_MTU, + BSP_LOCK_MTU0, + BSP_LOCK_MTU1, + BSP_LOCK_MTU2, + BSP_LOCK_MTU3, + BSP_LOCK_MTU4, + BSP_LOCK_MTU5, + BSP_LOCK_POE, + BSP_LOCK_RIIC0, + BSP_LOCK_RSPI0, + BSP_LOCK_RTC, + BSP_LOCK_RTCB, + BSP_LOCK_S12AD, + BSP_LOCK_SCI0, + BSP_LOCK_SCI1, + BSP_LOCK_SCI5, + BSP_LOCK_SCI6, + BSP_LOCK_SCI8, + BSP_LOCK_SCI9, + BSP_LOCK_SCI12, + BSP_LOCK_SYSTEM, + BSP_LOCK_TEMPS, + BSP_LOCK_TMR0, + BSP_LOCK_TMR1, + BSP_LOCK_TMR2, + BSP_LOCK_TMR3, + BSP_LOCK_TMR01, + BSP_LOCK_TMR23, + BSP_LOCK_SWINT, + BSP_NUM_LOCKS //This entry is not a valid lock. It is used for sizing g_bsp_Locks[] array below. Do not touch! +} mcu_lock_t; + +typedef struct +{ + /* The actual lock. int32_t is used because this is what the xchg() instruction takes as parameters. */ + int32_t lock; + + /* Could add a ID for locking and unlocking. In this could protect against any function being able to unlock. */ +} bsp_lock_t; + +/*********************************************************************************************************************** +Error checking +***********************************************************************************************************************/ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 +#undef BSP_CFG_USER_LOCKING_TYPE +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t +#else + #if !defined(BSP_CFG_USER_LOCKING_TYPE) + #error "R_BSP ERROR - If you are using your own locking mechanism then you must define BSP_CFG_USER_LOCKING_TYPE in r_bsp_config.h." + #endif +#endif + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +extern BSP_CFG_USER_LOCKING_TYPE g_bsp_Locks[]; + +#endif /* MCU_LOCKS_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/r_bsp_cpu.h b/drivers/rx/rdp/src/r_bsp/mcu/rx140/r_bsp_cpu.h new file mode 100644 index 00000000..25d74bbf --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/r_bsp_cpu.h @@ -0,0 +1,82 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : r_bsp_cpu.h +* Description : This module implements CPU specific functions. An example is enabling/disabling interrupts. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First Release +* : 20.08.2021 1.01 Modified comment. +* : 21.11.2023 1.02 Added bsp_bus_priority_initialize function. +* : 26.02.2025 1.03 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef CPU_H +#define CPU_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* The different types of registers that can be protected. */ +typedef enum +{ + /* PRC0 + Enables writing to the registers related to the clock generation circuit: SCKCR, SCKCR3, + PLLCR, PLLCR2, MOSCCR, SOSCCR, LOCOCR, ILOCOCR, HOCOCR, LOFCR, OSTDCR, OSTDSR, CKOCR, LOCOTRR2, + ILOCOTRR, HOCOTRR0, SOMCR. */ + BSP_REG_PROTECT_CGC = 0, + + /* PRC1 + Enables writing to the registers related to operating modes, low power consumption, + the clock generation circuit, and software reset: SYSCR1, SBYCR, MSTPCRA, MSTPCRB, MSTPCRC, + MSTPCRD, OPCCR, RSTCKCR, SOPCCR, SNZCR, SNZCR2, MOFCR, MOSCWTCR, SWRR. */ + BSP_REG_PROTECT_LPC_CGC_SWR, + + /* PRC2 + Enables writing to the registers related to the LPT: LPTCR1, LPTCR2, LPTCR3, LPTPRD, LPCMR0, LPCMR1, LPWUCR. */ + BSP_REG_PROTECT_LPT, + + /* PRC3 + Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, + LVD2CR1, LVD2SR. */ + BSP_REG_PROTECT_LVD, + + /* MPC.PWPR + Enables writing to MPC's PFS registers. */ + BSP_REG_PROTECT_MPC, + + /* This entry is used for getting the number of enum items. This must be the last entry. DO NOT REMOVE THIS ENTRY!*/ + BSP_REG_PROTECT_TOTAL_ITEMS +} bsp_reg_protect_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_InterruptsDisable(void); +void R_BSP_InterruptsEnable(void); +uint32_t R_BSP_CpuInterruptLevelRead(void); +bool R_BSP_CpuInterruptLevelWrite(uint32_t level); +void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); +void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); +void R_BSP_SoftwareReset(void); + +void bsp_register_protect_open(void); //r_bsp internal function. DO NOT CALL. +void bsp_ram_initialize(void); +#if BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE == 1 +void bsp_bus_priority_initialize(void); +#endif + +#endif /* CPU_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/r_bsp_locking.h b/drivers/rx/rdp/src/r_bsp/mcu/rx140/r_bsp_locking.h new file mode 100644 index 00000000..664bb3ed --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/r_bsp_locking.h @@ -0,0 +1,55 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : r_bsp_locking.h +* Description : This implements a locking mechanism that can be used by all code. The locking is done atomically so +* common resources can be accessed safely. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First Release +* : 26.02.2025 1.01 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Lock types. */ +#include "mcu_locks.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef LOCKING_H +#define LOCKING_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +bool R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool R_BSP_HardwareLock(mcu_lock_t const hw_index); +bool R_BSP_HardwareUnlock(mcu_lock_t const hw_index); + +#if BSP_CFG_USER_LOCKING_ENABLED != 0 +/* Is user is using their own lock functions then these are the prototypes. */ +bool BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * const plock); +bool BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t const hw_index); +bool BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t const hw_index); +#endif + +#endif /* LOCKING_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/register_access/gnuc/iodefine.h b/drivers/rx/rdp/src/r_bsp/mcu/rx140/register_access/gnuc/iodefine.h new file mode 100644 index 00000000..b6afe6c4 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/register_access/gnuc/iodefine.h @@ -0,0 +1,18347 @@ +/* +* Copyright (c) 2020(2021-2025) Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/******************************************************************************* +* +* Device : RX/RX100/RX140 +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register. +* +* History : V0.40 (2020-09-04) [Hardware Manual Revision : 0.40] +* : V0.40A (2020-09-16) [Hardware Manual Revision : 0.40] +* : V0.40B (2020-10-06) [Hardware Manual Revision : 0.40] +* : V0.50 (2020-12-11) [Hardware Manual Revision : 0.50] +* : V0.50A (2020-12-16) [Hardware Manual Revision : 0.50] +* : V1.00 (2021-03-26) [Hardware Manual Revision : 1.00] +* : V1.00A (2021-05-27) [Hardware Manual Revision : 1.00] +* : V1.00B (2021-09-03) [Hardware Manual Revision : 1.00] +* : V1.00C (2021-10-12) [Hardware Manual Revision : 1.00] +* : V1.10 (2021-11-10) [Hardware Manual Revision : 1.10] +* : V1.10A (2021-12-16) [Hardware Manual Revision : 1.10] +* : V1.10B (2022-03-10) [Hardware Manual Revision : 1.10] +* : V1.10C (2022-03-29) [Hardware Manual Revision : 1.10] +* : V1.10D (2025-02-14) [Hardware Manual Revision : 1.10] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +*********************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX140 */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(MTU0,TGIA0) = 0; expands to : */ +/* ICU.IR[114].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(MTU1,TGIA1) = 2; expands to : */ +/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */ +/* ICU.IPR[121].BIT.IPR = 2; */ +/* */ +/* IPR(SCI1,ERI1) = 3; expands to : */ +/* IPR(SCI1, ) = 3; // SCI1 uses single IPR for all sources. */ +/* ICU.IPR[218].BIT.IPR = 3; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX140IODEFINE_HEADER__ +#define __RX140IODEFINE_HEADER__ + +#define IEN_BSC_BUSERR IEN0 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CAC_FERRF IEN0 +#define IEN_CAC_MENDF IEN1 +#define IEN_CAC_OVFF IEN2 +#define IEN_RSPI0_SPEI0 IEN4 +#define IEN_RSPI0_SPRI0 IEN5 +#define IEN_RSPI0_SPTI0 IEN6 +#define IEN_RSPI0_SPII0 IEN7 +#define IEN_RSCAN_COMFRXINT IEN4 +#define IEN_RSCAN_RXFINT IEN5 +#define IEN_RSCAN_TXINT IEN6 +#define IEN_RSCAN_CHERRINT IEN7 +#define IEN_RSCAN_GLERRINT IEN0 +#define IEN_DOC_DOPCF IEN1 +#define IEN_CMPB_CMPB0 IEN2 +#define IEN_CMPB_CMPB1 IEN3 +#define IEN_CTSU_CTSUWR IEN4 +#define IEN_CTSU_CTSURD IEN5 +#define IEN_CTSU_CTSUFN IEN6 +#define IEN_RTC_CUP IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ELC_ELSR8I IEN0 +#define IEN_SYSTEM_SNZI IEN1 +#define IEN_LVD_LVD1 IEN0 +#define IEN_LVD_LVD2 IEN1 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_S12AD_S12ADI0 IEN6 +#define IEN_S12AD_GBADI IEN7 +#define IEN_ELC_ELSR18I IEN2 +#define IEN_AES_AESWRI IEN7 +#define IEN_AES_AESRDI IEN0 +#define IEN_RNG_RNGRDI IEN1 +#define IEN_MTU0_TGIA0 IEN2 +#define IEN_MTU0_TGIB0 IEN3 +#define IEN_MTU0_TGIC0 IEN4 +#define IEN_MTU0_TGID0 IEN5 +#define IEN_MTU0_TCIV0 IEN6 +#define IEN_MTU0_TGIE0 IEN7 +#define IEN_MTU0_TGIF0 IEN0 +#define IEN_MTU1_TGIA1 IEN1 +#define IEN_MTU1_TGIB1 IEN2 +#define IEN_MTU1_TCIV1 IEN3 +#define IEN_MTU1_TCIU1 IEN4 +#define IEN_MTU2_TGIA2 IEN5 +#define IEN_MTU2_TGIB2 IEN6 +#define IEN_MTU2_TCIV2 IEN7 +#define IEN_MTU2_TCIU2 IEN0 +#define IEN_MTU3_TGIA3 IEN1 +#define IEN_MTU3_TGIB3 IEN2 +#define IEN_MTU3_TGIC3 IEN3 +#define IEN_MTU3_TGID3 IEN4 +#define IEN_MTU3_TCIV3 IEN5 +#define IEN_MTU4_TGIA4 IEN6 +#define IEN_MTU4_TGIB4 IEN7 +#define IEN_MTU4_TGIC4 IEN0 +#define IEN_MTU4_TGID4 IEN1 +#define IEN_MTU4_TCIV4 IEN2 +#define IEN_MTU5_TGIU5 IEN3 +#define IEN_MTU5_TGIV5 IEN4 +#define IEN_MTU5_TGIW5 IEN5 +#define IEN_POE_OEI1 IEN2 +#define IEN_POE_OEI2 IEN3 +#define IEN_TMR0_CMIA0 IEN6 +#define IEN_TMR0_CMIB0 IEN7 +#define IEN_TMR0_OVI0 IEN0 +#define IEN_TMR1_CMIA1 IEN1 +#define IEN_TMR1_CMIB1 IEN2 +#define IEN_TMR1_OVI1 IEN3 +#define IEN_TMR2_CMIA2 IEN4 +#define IEN_TMR2_CMIB2 IEN5 +#define IEN_TMR2_OVI2 IEN6 +#define IEN_TMR3_CMIA3 IEN7 +#define IEN_TMR3_CMIB3 IEN0 +#define IEN_TMR3_OVI3 IEN1 +#define IEN_SCI1_ERI1 IEN2 +#define IEN_SCI1_RXI1 IEN3 +#define IEN_SCI1_TXI1 IEN4 +#define IEN_SCI1_TEI1 IEN5 +#define IEN_SCI5_ERI5 IEN6 +#define IEN_SCI5_RXI5 IEN7 +#define IEN_SCI5_TXI5 IEN0 +#define IEN_SCI5_TEI5 IEN1 +#define IEN_SCI6_ERI6 IEN2 +#define IEN_SCI6_RXI6 IEN3 +#define IEN_SCI6_TXI6 IEN4 +#define IEN_SCI6_TEI6 IEN5 +#define IEN_SCI8_ERI8 IEN6 +#define IEN_SCI8_RXI8 IEN7 +#define IEN_SCI8_TXI8 IEN0 +#define IEN_SCI8_TEI8 IEN1 +#define IEN_SCI9_ERI9 IEN2 +#define IEN_SCI9_RXI9 IEN3 +#define IEN_SCI9_TXI9 IEN4 +#define IEN_SCI9_TEI9 IEN5 +#define IEN_SCI12_ERI12 IEN6 +#define IEN_SCI12_RXI12 IEN7 +#define IEN_SCI12_TXI12 IEN0 +#define IEN_SCI12_TEI12 IEN1 +#define IEN_SCI12_SCIX0 IEN2 +#define IEN_SCI12_SCIX1 IEN3 +#define IEN_SCI12_SCIX2 IEN4 +#define IEN_SCI12_SCIX3 IEN5 +#define IEN_RIIC0_EEI0 IEN6 +#define IEN_RIIC0_RXI0 IEN7 +#define IEN_RIIC0_TXI0 IEN0 +#define IEN_RIIC0_TEI0 IEN1 +#define IEN_LPT_LPTCMI1 IEN7 + +#define VECT_BSC_BUSERR 16 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CAC_FERRF 32 +#define VECT_CAC_MENDF 33 +#define VECT_CAC_OVFF 34 +#define VECT_RSPI0_SPEI0 44 +#define VECT_RSPI0_SPRI0 45 +#define VECT_RSPI0_SPTI0 46 +#define VECT_RSPI0_SPII0 47 +#define VECT_RSCAN_COMFRXINT 52 +#define VECT_RSCAN_RXFINT 53 +#define VECT_RSCAN_TXINT 54 +#define VECT_RSCAN_CHERRINT 55 +#define VECT_RSCAN_GLERRINT 56 +#define VECT_DOC_DOPCF 57 +#define VECT_CMPB_CMPB0 58 +#define VECT_CMPB_CMPB1 59 +#define VECT_CTSU_CTSUWR 60 +#define VECT_CTSU_CTSURD 61 +#define VECT_CTSU_CTSUFN 62 +#define VECT_RTC_CUP 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ELC_ELSR8I 80 +#define VECT_SYSTEM_SNZI 81 +#define VECT_LVD_LVD1 88 +#define VECT_LVD_LVD2 89 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_S12AD_S12ADI0 102 +#define VECT_S12AD_GBADI 103 +#define VECT_ELC_ELSR18I 106 +#define VECT_AES_AESWRI 111 +#define VECT_AES_AESRDI 112 +#define VECT_RNG_RNGRDI 113 +#define VECT_MTU0_TGIA0 114 +#define VECT_MTU0_TGIB0 115 +#define VECT_MTU0_TGIC0 116 +#define VECT_MTU0_TGID0 117 +#define VECT_MTU0_TCIV0 118 +#define VECT_MTU0_TGIE0 119 +#define VECT_MTU0_TGIF0 120 +#define VECT_MTU1_TGIA1 121 +#define VECT_MTU1_TGIB1 122 +#define VECT_MTU1_TCIV1 123 +#define VECT_MTU1_TCIU1 124 +#define VECT_MTU2_TGIA2 125 +#define VECT_MTU2_TGIB2 126 +#define VECT_MTU2_TCIV2 127 +#define VECT_MTU2_TCIU2 128 +#define VECT_MTU3_TGIA3 129 +#define VECT_MTU3_TGIB3 130 +#define VECT_MTU3_TGIC3 131 +#define VECT_MTU3_TGID3 132 +#define VECT_MTU3_TCIV3 133 +#define VECT_MTU4_TGIA4 134 +#define VECT_MTU4_TGIB4 135 +#define VECT_MTU4_TGIC4 136 +#define VECT_MTU4_TGID4 137 +#define VECT_MTU4_TCIV4 138 +#define VECT_MTU5_TGIU5 139 +#define VECT_MTU5_TGIV5 140 +#define VECT_MTU5_TGIW5 141 +#define VECT_POE_OEI1 170 +#define VECT_POE_OEI2 171 +#define VECT_TMR0_CMIA0 174 +#define VECT_TMR0_CMIB0 175 +#define VECT_TMR0_OVI0 176 +#define VECT_TMR1_CMIA1 177 +#define VECT_TMR1_CMIB1 178 +#define VECT_TMR1_OVI1 179 +#define VECT_TMR2_CMIA2 180 +#define VECT_TMR2_CMIB2 181 +#define VECT_TMR2_OVI2 182 +#define VECT_TMR3_CMIA3 183 +#define VECT_TMR3_CMIB3 184 +#define VECT_TMR3_OVI3 185 +#define VECT_SCI1_ERI1 218 +#define VECT_SCI1_RXI1 219 +#define VECT_SCI1_TXI1 220 +#define VECT_SCI1_TEI1 221 +#define VECT_SCI5_ERI5 222 +#define VECT_SCI5_RXI5 223 +#define VECT_SCI5_TXI5 224 +#define VECT_SCI5_TEI5 225 +#define VECT_SCI6_ERI6 226 +#define VECT_SCI6_RXI6 227 +#define VECT_SCI6_TXI6 228 +#define VECT_SCI6_TEI6 229 +#define VECT_SCI8_ERI8 230 +#define VECT_SCI8_RXI8 231 +#define VECT_SCI8_TXI8 232 +#define VECT_SCI8_TEI8 233 +#define VECT_SCI9_ERI9 234 +#define VECT_SCI9_RXI9 235 +#define VECT_SCI9_TXI9 236 +#define VECT_SCI9_TEI9 237 +#define VECT_SCI12_ERI12 238 +#define VECT_SCI12_RXI12 239 +#define VECT_SCI12_TXI12 240 +#define VECT_SCI12_TEI12 241 +#define VECT_SCI12_SCIX0 242 +#define VECT_SCI12_SCIX1 243 +#define VECT_SCI12_SCIX2 244 +#define VECT_SCI12_SCIX3 245 +#define VECT_RIIC0_EEI0 246 +#define VECT_RIIC0_RXI0 247 +#define VECT_RIIC0_TXI0 248 +#define VECT_RIIC0_TEI0 249 +#define VECT_LPT_LPTCMI1 255 + +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_CMPB SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_RSCAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_AES SYSTEM.MSTPCRD.BIT.MSTPD30 +#define MSTP_RNG SYSTEM.MSTPCRD.BIT.MSTPD29 +#define MSTP_CTSU SYSTEM.MSTPCRD.BIT.MSTPD10 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define BSC (*(volatile struct st_bsc *)0x81300) +#define CAC (*(volatile struct st_cac *)0x8B000) +#define CMPB (*(volatile struct st_cmpb *)0x8C580) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CRC (*(volatile struct st_crc *)0x88280) +#define CTSU (*(volatile struct st_ctsu *)0xA0700) +#define DA (*(volatile struct st_da *)0x880C0) +#define DOC (*(volatile struct st_doc *)0x8B080) +#define DTC (*(volatile struct st_dtc *)0x82400) +#define ELC (*(volatile struct st_elc *)0x8B100) +#define FLASH (*(volatile struct st_flash *)0x7FC090) +#define ICU (*(volatile struct st_icu *)0x87000) +#define IWDT (*(volatile struct st_iwdt *)0x88030) +#define LPT (*(volatile struct st_lpt *)0x800B0) +#define MPC (*(volatile struct st_mpc *)0x8C11F) +#define MTU (*(volatile struct st_mtu *)0x8860A) +#define MTU0 (*(volatile struct st_mtu0 *)0x88690) +#define MTU1 (*(volatile struct st_mtu1 *)0x88690) +#define MTU2 (*(volatile struct st_mtu2 *)0x88692) +#define MTU3 (*(volatile struct st_mtu3 *)0x88600) +#define MTU4 (*(volatile struct st_mtu4 *)0x88600) +#define MTU5 (*(volatile struct st_mtu5 *)0x88694) +#define OFSM (*(volatile struct st_ofsm *)0xFFFFFF80) +#define POE (*(volatile struct st_poe *)0x88900) +#define PORT (*(volatile struct st_port *)0x8C120) +#define PORT0 (*(volatile struct st_port0 *)0x8C000) +#define PORT1 (*(volatile struct st_port1 *)0x8C001) +#define PORT2 (*(volatile struct st_port2 *)0x8C002) +#define PORT3 (*(volatile struct st_port3 *)0x8C003) +#define PORT4 (*(volatile struct st_port4 *)0x8C004) +#define PORT5 (*(volatile struct st_port5 *)0x8C005) +#define PORTA (*(volatile struct st_porta *)0x8C00A) +#define PORTB (*(volatile struct st_portb *)0x8C00B) +#define PORTC (*(volatile struct st_portc *)0x8C00C) +#define PORTD (*(volatile struct st_portd *)0x8C00D) +#define PORTE (*(volatile struct st_porte *)0x8C00E) +#define PORTG (*(volatile struct st_portg *)0x8C010) +#define PORTH (*(volatile struct st_porth *)0x8C011) +#define PORTJ (*(volatile struct st_portj *)0x8C012) +#define RIIC0 (*(volatile struct st_riic *)0x88300) +#define RSCAN (*(volatile struct st_rscan *)0xA8322) +#define RSCAN0 (*(volatile struct st_rscan0 *)0xA8300) +#define RSPI0 (*(volatile struct st_rspi *)0x88380) +#define RTC (*(volatile struct st_rtc *)0x8C400) +#define RTCB (*(volatile struct st_rtcb *)0x8C402) +#define S12AD (*(volatile struct st_s12ad *)0x89000) +#define SCI1 (*(volatile struct st_sci1 *)0x8A020) +#define SCI5 (*(volatile struct st_sci1 *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci6 *)0x8A0C0) +#define SCI8 (*(volatile struct st_sci6 *)0x8A100) +#define SCI9 (*(volatile struct st_sci6 *)0x8A120) +#define SCI12 (*(volatile struct st_sci12 *)0x8B300) +#define SMCI1 (*(volatile struct st_smci *)0x8A020) +#define SMCI5 (*(volatile struct st_smci *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci *)0x8A0C0) +#define SMCI8 (*(volatile struct st_smci *)0x8A100) +#define SMCI9 (*(volatile struct st_smci *)0x8A120) +#define SMCI12 (*(volatile struct st_smci *)0x8B300) +#define SYSTEM (*(volatile struct st_system *)0x80000) +#define TEMPS (*(volatile struct st_temps *)0x7FC228) +#define TMR0 (*(volatile struct st_tmr0 *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 *)0x88214) + +typedef enum enum_ir { +IR_BSC_BUSERR=16,IR_FCU_FRDYI=23, +IR_ICU_SWINT=27, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CAC_FERRF=32,IR_CAC_MENDF,IR_CAC_OVFF, +IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_RSCAN_COMFRXINT=52,IR_RSCAN_RXFINT,IR_RSCAN_TXINT,IR_RSCAN_CHERRINT,IR_RSCAN_GLERRINT, +IR_DOC_DOPCF, +IR_CMPB_CMPB0,IR_CMPB_CMPB1, +IR_CTSU_CTSUWR,IR_CTSU_CTSURD,IR_CTSU_CTSUFN, +IR_RTC_CUP, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ELC_ELSR8I=80, +IR_SYSTEM_SNZI, +IR_LVD_LVD1=88,IR_LVD_LVD2, +IR_RTC_ALM=92,IR_RTC_PRD, +IR_S12AD_S12ADI0=102,IR_S12AD_GBADI, +IR_ELC_ELSR18I=106, +IR_AES_AESWRI=111,IR_AES_AESRDI, +IR_RNG_RNGRDI, +IR_MTU0_TGIA0,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1, +IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2, +IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3, +IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_POE_OEI1=170,IR_POE_OEI2, +IR_TMR0_CMIA0=174,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_SCI1_ERI1=218,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_SCI8_ERI8,IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8, +IR_SCI9_ERI9,IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9, +IR_SCI12_ERI12,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3, +IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0, +IR_LPT_LPTCMI1=255 +} enum_ir_t; + +typedef enum enum_dtce { +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0, +DTCE_RSCAN_COMFRXINT=52, +DTCE_CMPB_CMPB0=58,DTCE_CMPB_CMPB1, +DTCE_CTSU_CTSUWR,DTCE_CTSU_CTSURD, +DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI, +DTCE_ELC_ELSR18I=106, +DTCE_AES_AESWRI=111,DTCE_AES_AESRDI, +DTCE_RNG_RNGRDI, +DTCE_MTU0_TGIA0,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0, +DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1, +DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2, +DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3, +DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0, +DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1, +DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2, +DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3, +DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1, +DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6=227,DTCE_SCI6_TXI6, +DTCE_SCI8_RXI8=231,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9=235,DTCE_SCI9_TXI9, +DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12, +DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0, +DTCE_LPT_LPTCMI1=255 +} enum_dtce_t; + +typedef enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_FCU_FRDYI=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04, +IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_RSCAN_COMFRXINT=0x06,IER_RSCAN_RXFINT=0x06,IER_RSCAN_TXINT=0x06,IER_RSCAN_CHERRINT=0x06,IER_RSCAN_GLERRINT=0x07, +IER_DOC_DOPCF=0x07, +IER_CMPB_CMPB0=0x07,IER_CMPB_CMPB1=0x07, +IER_CTSU_CTSUWR=0x07,IER_CTSU_CTSURD=0x07,IER_CTSU_CTSUFN=0x07, +IER_RTC_CUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ELC_ELSR8I=0x0A, +IER_SYSTEM_SNZI=0x0A, +IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C, +IER_ELC_ELSR18I=0x0D, +IER_AES_AESWRI=0x0D,IER_AES_AESRDI=0x0E, +IER_RNG_RNGRDI=0x0E, +IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F, +IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F, +IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10, +IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10, +IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11, +IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11, +IER_POE_OEI1=0x15,IER_POE_OEI2=0x15, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16, +IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17, +IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C, +IER_SCI6_ERI6=0x1C,IER_SCI6_RXI6=0x1C,IER_SCI6_TXI6=0x1C,IER_SCI6_TEI6=0x1C, +IER_SCI8_ERI8=0x1C,IER_SCI8_RXI8=0x1C,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1D, +IER_SCI9_ERI9=0x1D,IER_SCI9_RXI9=0x1D,IER_SCI9_TXI9=0x1D,IER_SCI9_TEI9=0x1D, +IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E, +IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F, +IER_LPT_LPTCMI1=0x1F +} enum_ier_t; + +typedef enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_FCU_FRDYI=2, +IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4, +IPR_CMT1_CMI1=5, +IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34, +IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44, +IPR_RSCAN_COMFRXINT=52,IPR_RSCAN_RXFINT=53,IPR_RSCAN_TXINT=54,IPR_RSCAN_CHERRINT=55,IPR_RSCAN_GLERRINT=56, +IPR_DOC_DOPCF=57, +IPR_CMPB_CMPB0=58,IPR_CMPB_CMPB1=59, +IPR_CTSU_CTSUWR=60,IPR_CTSU_CTSURD=60,IPR_CTSU_CTSUFN=60, +IPR_RTC_CUP=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71, +IPR_ELC_ELSR8I=80, +IPR_SYSTEM_SNZI=81, +IPR_LVD_LVD1=88,IPR_LVD_LVD2=89, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103, +IPR_ELC_ELSR18I=106, +IPR_AES_AESWRI=111,IPR_AES_AESRDI=111, +IPR_RNG_RNGRDI=113, +IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118, +IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123, +IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127, +IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133, +IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138, +IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139, +IPR_POE_OEI1=170,IPR_POE_OEI2=171, +IPR_TMR0_CMIA0=174,IPR_TMR0_CMIB0=174,IPR_TMR0_OVI0=174, +IPR_TMR1_CMIA1=177,IPR_TMR1_CMIB1=177,IPR_TMR1_OVI1=177, +IPR_TMR2_CMIA2=180,IPR_TMR2_CMIB2=180,IPR_TMR2_OVI2=180, +IPR_TMR3_CMIA3=183,IPR_TMR3_CMIB3=183,IPR_TMR3_OVI3=183, +IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218, +IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222, +IPR_SCI6_ERI6=226,IPR_SCI6_RXI6=226,IPR_SCI6_TXI6=226,IPR_SCI6_TEI6=226, +IPR_SCI8_ERI8=230,IPR_SCI8_RXI8=230,IPR_SCI8_TXI8=230,IPR_SCI8_TEI8=230, +IPR_SCI9_ERI9=234,IPR_SCI9_RXI9=234,IPR_SCI9_TXI9=234,IPR_SCI9_TEI9=234, +IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245, +IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249, +IPR_LPT_LPTCMI1=255, +IPR_BSC_=0, +IPR_FCU_=2, +IPR_CMT0_=4, +IPR_CMT1_=5, +IPR_RSPI0_=44, +IPR_DOC_=57, +IPR_CTSU_=60, +IPR_SYSTEM_=81, +IPR_AES_=111, +IPR_RNG_=113, +IPR_MTU1_TGI=121, +IPR_MTU1_TCI=123, +IPR_MTU2_TGI=125, +IPR_MTU2_TCI=127, +IPR_MTU3_TGI=129, +IPR_MTU4_TGI=134, +IPR_MTU5_=139, +IPR_MTU5_TGI=139, +IPR_TMR0_=174, +IPR_TMR1_=177, +IPR_TMR2_=180, +IPR_TMR3_=183, +IPR_SCI1_=218, +IPR_SCI5_=222, +IPR_SCI6_=226, +IPR_SCI8_=230, +IPR_SCI9_=234, +IPR_LPT_=255 +} enum_ipr_t; + + +#pragma pack(4) + + +typedef struct st_bsc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char STSCLR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char STSCLR : 1; +#endif + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IGAEN : 1; + unsigned char TOEN : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TOEN : 1; + unsigned char IGAEN : 1; +#endif + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IA : 1; + unsigned char TO : 1; + unsigned char : 2; + unsigned char MST : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MST : 3; + unsigned char : 2; + unsigned char TO : 1; + unsigned char IA : 1; +#endif + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 3; + unsigned short ADDR : 13; +#else + unsigned short ADDR : 13; + unsigned short : 3; +#endif + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BPRA : 2; + unsigned short BPRO : 2; + unsigned short BPIB : 2; + unsigned short BPGB : 2; + unsigned short : 2; + unsigned short BPFB : 2; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short BPFB : 2; + unsigned short : 2; + unsigned short BPGB : 2; + unsigned short BPIB : 2; + unsigned short BPRO : 2; + unsigned short BPRA : 2; +#endif + } BIT; + } BUSPRI; +} st_bsc_t; + +typedef struct st_cac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CFME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CFME : 1; +#endif + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CACREFE : 1; + unsigned char FMCS : 3; + unsigned char TCSS : 2; + unsigned char EDGES : 2; +#else + unsigned char EDGES : 2; + unsigned char TCSS : 2; + unsigned char FMCS : 3; + unsigned char CACREFE : 1; +#endif + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RPS : 1; + unsigned char RSCS : 3; + unsigned char RCDS : 2; + unsigned char DFS : 2; +#else + unsigned char DFS : 2; + unsigned char RCDS : 2; + unsigned char RSCS : 3; + unsigned char RPS : 1; +#endif + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRIE : 1; + unsigned char MENDIE : 1; + unsigned char OVFIE : 1; + unsigned char : 1; + unsigned char FERRFCL : 1; + unsigned char MENDFCL : 1; + unsigned char OVFFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char OVFFCL : 1; + unsigned char MENDFCL : 1; + unsigned char FERRFCL : 1; + unsigned char : 1; + unsigned char OVFIE : 1; + unsigned char MENDIE : 1; + unsigned char FERRIE : 1; +#endif + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRF : 1; + unsigned char MENDF : 1; + unsigned char OVFF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char OVFF : 1; + unsigned char MENDF : 1; + unsigned char FERRF : 1; +#endif + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +} st_cac_t; + +typedef struct st_cmpb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0INI : 1; + unsigned char : 3; + unsigned char CPB1INI : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1INI : 1; + unsigned char : 3; + unsigned char CPB0INI : 1; +#endif + } BIT; + } CPBCNT1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0WCP : 1; + unsigned char : 3; + unsigned char CPB1WCP : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1WCP : 1; + unsigned char : 3; + unsigned char CPB0WCP : 1; +#endif + } BIT; + } CPBCNT2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CPB0OUT : 1; + unsigned char : 3; + unsigned char CPB1OUT : 1; +#else + unsigned char CPB1OUT : 1; + unsigned char : 3; + unsigned char CPB0OUT : 1; + unsigned char : 3; +#endif + } BIT; + } CPBFLG; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0INTEN : 1; + unsigned char CPB0INTEG : 1; + unsigned char CPB0INTPL : 1; + unsigned char : 1; + unsigned char CPB1INTEN : 1; + unsigned char CPB1INTEG : 1; + unsigned char CPB1INTPL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CPB1INTPL : 1; + unsigned char CPB1INTEG : 1; + unsigned char CPB1INTEN : 1; + unsigned char : 1; + unsigned char CPB0INTPL : 1; + unsigned char CPB0INTEG : 1; + unsigned char CPB0INTEN : 1; +#endif + } BIT; + } CPBINT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0FEN : 1; + unsigned char : 1; + unsigned char CPB0F : 2; + unsigned char CPB1FEN : 1; + unsigned char : 1; + unsigned char CPB1F : 2; +#else + unsigned char CPB1F : 2; + unsigned char : 1; + unsigned char CPB1FEN : 1; + unsigned char CPB0F : 2; + unsigned char : 1; + unsigned char CPB0FEN : 1; +#endif + } BIT; + } CPBF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPBSPDMD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CPBSPDMD : 1; +#endif + } BIT; + } CPBMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0VRF : 1; + unsigned char : 3; + unsigned char CPB1VRF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1VRF : 1; + unsigned char : 3; + unsigned char CPB0VRF : 1; +#endif + } BIT; + } CPBREF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0OE : 1; + unsigned char CPB0OP : 1; + unsigned char : 2; + unsigned char CPB1OE : 1; + unsigned char CPB1OP : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CPB1OP : 1; + unsigned char CPB1OE : 1; + unsigned char : 2; + unsigned char CPB0OP : 1; + unsigned char CPB0OE : 1; +#endif + } BIT; + } CPBOCR; +} st_cmpb_t; + +typedef struct st_cmt { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR0 : 1; + unsigned short STR1 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR1 : 1; + unsigned short STR0 : 1; +#endif + } BIT; + } CMSTR0; +} st_cmt_t; + +typedef struct st_cmt0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 4; + unsigned short CMIE : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMIE : 1; + unsigned short : 4; + unsigned short CKS : 2; +#endif + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +} st_cmt0_t; + +typedef struct st_crc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char GPS : 2; + unsigned char LMS : 1; + unsigned char : 4; + unsigned char DORCLR : 1; +#else + unsigned char DORCLR : 1; + unsigned char : 4; + unsigned char LMS : 1; + unsigned char GPS : 2; +#endif + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +} st_crc_t; + +typedef struct st_ctsu { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CTADCS : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long CTADCS : 1; +#endif + } BIT; + } CTSUADCC; + char wk0[508]; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STRT : 1; + unsigned long CAP : 1; + unsigned long SNZ : 1; + unsigned long : 1; + unsigned long INIT : 1; + unsigned long PUMPON : 1; + unsigned long TXVSEL : 2; + unsigned long PON : 1; + unsigned long CSW : 1; + unsigned long ATUNE0 : 1; + unsigned long ATUNE1 : 1; + unsigned long CLK : 2; + unsigned long MD0 : 1; + unsigned long MD1 : 1; + unsigned long : 1; + unsigned long ATUNE2 : 1; + unsigned long LOAD : 2; + unsigned long POSEL : 2; + unsigned long SDPSEL : 1; + unsigned long PCSEL : 1; + unsigned long STCLK : 6; + unsigned long DCMODE : 1; + unsigned long DCBACK : 1; +#else + unsigned long DCBACK : 1; + unsigned long DCMODE : 1; + unsigned long STCLK : 6; + unsigned long PCSEL : 1; + unsigned long SDPSEL : 1; + unsigned long POSEL : 2; + unsigned long LOAD : 2; + unsigned long ATUNE2 : 1; + unsigned long : 1; + unsigned long MD1 : 1; + unsigned long MD0 : 1; + unsigned long CLK : 2; + unsigned long ATUNE1 : 1; + unsigned long ATUNE0 : 1; + unsigned long CSW : 1; + unsigned long PON : 1; + unsigned long TXVSEL : 2; + unsigned long PUMPON : 1; + unsigned long INIT : 1; + unsigned long : 1; + unsigned long SNZ : 1; + unsigned long CAP : 1; + unsigned long STRT : 1; +#endif + } BIT; + } CTSUCRA; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PRRATIO : 4; + unsigned long PRMODE : 2; + unsigned long SOFF : 1; + unsigned long PROFF : 1; + unsigned long SST : 8; + unsigned long : 8; + unsigned long SSMOD : 3; + unsigned long : 1; + unsigned long SSCNT : 2; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long SSCNT : 2; + unsigned long : 1; + unsigned long SSMOD : 3; + unsigned long : 8; + unsigned long SST : 8; + unsigned long PROFF : 1; + unsigned long SOFF : 1; + unsigned long PRMODE : 2; + unsigned long PRRATIO : 4; +#endif + } BIT; + } CTSUCRB; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MCH0 : 6; + unsigned long : 2; + unsigned long MCH1 : 6; + unsigned long : 2; + unsigned long MCA0 : 1; + unsigned long MCA1 : 1; + unsigned long MCA2 : 1; + unsigned long MCA3 : 1; + unsigned long : 12; +#else + unsigned long : 12; + unsigned long MCA3 : 1; + unsigned long MCA2 : 1; + unsigned long MCA1 : 1; + unsigned long MCA0 : 1; + unsigned long : 2; + unsigned long MCH1 : 6; + unsigned long : 2; + unsigned long MCH0 : 6; +#endif + } BIT; + } CTSUMCH; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CHAC0 : 1; + unsigned long CHAC1 : 1; + unsigned long CHAC2 : 1; + unsigned long CHAC3 : 1; + unsigned long CHAC4 : 1; + unsigned long CHAC5 : 1; + unsigned long CHAC6 : 1; + unsigned long CHAC7 : 1; + unsigned long CHAC8 : 1; + unsigned long CHAC9 : 1; + unsigned long CHAC10 : 1; + unsigned long CHAC11 : 1; + unsigned long CHAC12 : 1; + unsigned long CHAC13 : 1; + unsigned long CHAC14 : 1; + unsigned long CHAC15 : 1; + unsigned long CHAC16 : 1; + unsigned long CHAC17 : 1; + unsigned long CHAC18 : 1; + unsigned long CHAC19 : 1; + unsigned long CHAC20 : 1; + unsigned long CHAC21 : 1; + unsigned long CHAC22 : 1; + unsigned long CHAC23 : 1; + unsigned long CHAC24 : 1; + unsigned long CHAC25 : 1; + unsigned long CHAC26 : 1; + unsigned long CHAC27 : 1; + unsigned long CHAC28 : 1; + unsigned long CHAC29 : 1; + unsigned long CHAC30 : 1; + unsigned long CHAC31 : 1; +#else + unsigned long CHAC31 : 1; + unsigned long CHAC30 : 1; + unsigned long CHAC29 : 1; + unsigned long CHAC28 : 1; + unsigned long CHAC27 : 1; + unsigned long CHAC26 : 1; + unsigned long CHAC25 : 1; + unsigned long CHAC24 : 1; + unsigned long CHAC23 : 1; + unsigned long CHAC22 : 1; + unsigned long CHAC21 : 1; + unsigned long CHAC20 : 1; + unsigned long CHAC19 : 1; + unsigned long CHAC18 : 1; + unsigned long CHAC17 : 1; + unsigned long CHAC16 : 1; + unsigned long CHAC15 : 1; + unsigned long CHAC14 : 1; + unsigned long CHAC13 : 1; + unsigned long CHAC12 : 1; + unsigned long CHAC11 : 1; + unsigned long CHAC10 : 1; + unsigned long CHAC9 : 1; + unsigned long CHAC8 : 1; + unsigned long CHAC7 : 1; + unsigned long CHAC6 : 1; + unsigned long CHAC5 : 1; + unsigned long CHAC4 : 1; + unsigned long CHAC3 : 1; + unsigned long CHAC2 : 1; + unsigned long CHAC1 : 1; + unsigned long CHAC0 : 1; +#endif + } BIT; + } CTSUCHACA; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CHAC32 : 1; + unsigned long CHAC33 : 1; + unsigned long CHAC34 : 1; + unsigned long CHAC35 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long CHAC35 : 1; + unsigned long CHAC34 : 1; + unsigned long CHAC33 : 1; + unsigned long CHAC32 : 1; +#endif + } BIT; + } CTSUCHACB; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CHTRC0 : 1; + unsigned long CHTRC1 : 1; + unsigned long CHTRC2 : 1; + unsigned long CHTRC3 : 1; + unsigned long CHTRC4 : 1; + unsigned long CHTRC5 : 1; + unsigned long CHTRC6 : 1; + unsigned long CHTRC7 : 1; + unsigned long CHTRC8 : 1; + unsigned long CHTRC9 : 1; + unsigned long CHTRC10 : 1; + unsigned long CHTRC11 : 1; + unsigned long CHTRC12 : 1; + unsigned long CHTRC13 : 1; + unsigned long CHTRC14 : 1; + unsigned long CHTRC15 : 1; + unsigned long CHTRC16 : 1; + unsigned long CHTRC17 : 1; + unsigned long CHTRC18 : 1; + unsigned long CHTRC19 : 1; + unsigned long CHTRC20 : 1; + unsigned long CHTRC21 : 1; + unsigned long CHTRC22 : 1; + unsigned long CHTRC23 : 1; + unsigned long CHTRC24 : 1; + unsigned long CHTRC25 : 1; + unsigned long CHTRC26 : 1; + unsigned long CHTRC27 : 1; + unsigned long CHTRC28 : 1; + unsigned long CHTRC29 : 1; + unsigned long CHTRC30 : 1; + unsigned long CHTRC31 : 1; +#else + unsigned long CHTRC31 : 1; + unsigned long CHTRC30 : 1; + unsigned long CHTRC29 : 1; + unsigned long CHTRC28 : 1; + unsigned long CHTRC27 : 1; + unsigned long CHTRC26 : 1; + unsigned long CHTRC25 : 1; + unsigned long CHTRC24 : 1; + unsigned long CHTRC23 : 1; + unsigned long CHTRC22 : 1; + unsigned long CHTRC21 : 1; + unsigned long CHTRC20 : 1; + unsigned long CHTRC19 : 1; + unsigned long CHTRC18 : 1; + unsigned long CHTRC17 : 1; + unsigned long CHTRC16 : 1; + unsigned long CHTRC15 : 1; + unsigned long CHTRC14 : 1; + unsigned long CHTRC13 : 1; + unsigned long CHTRC12 : 1; + unsigned long CHTRC11 : 1; + unsigned long CHTRC10 : 1; + unsigned long CHTRC9 : 1; + unsigned long CHTRC8 : 1; + unsigned long CHTRC7 : 1; + unsigned long CHTRC6 : 1; + unsigned long CHTRC5 : 1; + unsigned long CHTRC4 : 1; + unsigned long CHTRC3 : 1; + unsigned long CHTRC2 : 1; + unsigned long CHTRC1 : 1; + unsigned long CHTRC0 : 1; +#endif + } BIT; + } CTSUCHTRCA; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CHTRC32 : 1; + unsigned long CHTRC33 : 1; + unsigned long CHTRC34 : 1; + unsigned long CHTRC35 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long CHTRC35 : 1; + unsigned long CHTRC34 : 1; + unsigned long CHTRC33 : 1; + unsigned long CHTRC32 : 1; +#endif + } BIT; + } CTSUCHTRCB; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MFC : 2; + unsigned long : 3; + unsigned long ICOMPRST : 1; + unsigned long ICOMP1 : 1; + unsigned long ICOMP0 : 1; + unsigned long STC : 3; + unsigned long : 1; + unsigned long DTSR : 1; + unsigned long SCOVF : 1; + unsigned long UCOVF : 1; + unsigned long PS : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long PS : 1; + unsigned long UCOVF : 1; + unsigned long SCOVF : 1; + unsigned long DTSR : 1; + unsigned long : 1; + unsigned long STC : 3; + unsigned long ICOMP0 : 1; + unsigned long ICOMP1 : 1; + unsigned long ICOMPRST : 1; + unsigned long : 3; + unsigned long MFC : 2; +#endif + } BIT; + } CTSUSR; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SO : 10; + unsigned long SNUM : 8; + unsigned long : 2; + unsigned long SSDIV : 4; + unsigned long SDPA : 8; +#else + unsigned long SDPA : 8; + unsigned long SSDIV : 4; + unsigned long : 2; + unsigned long SNUM : 8; + unsigned long SO : 10; +#endif + } BIT; + } CTSUSO; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SC : 16; + unsigned long UC : 16; +#else + unsigned long UC : 16; + unsigned long SC : 16; +#endif + } BIT; + } CTSUSCNT; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 2; + unsigned long TSOD : 1; + unsigned long DRV : 1; + unsigned long CLKSEL : 2; + unsigned long SUCLKEN : 1; + unsigned long TSOC : 1; + unsigned long CNTRDSEL : 1; + unsigned long IOC : 1; + unsigned long : 1; + unsigned long DCOFF : 1; + unsigned long IOCSEL : 1; + unsigned long : 11; + unsigned long DACMSEL : 1; + unsigned long DACCARRY : 1; + unsigned long SUMSEL : 1; + unsigned long SUCARRY : 1; + unsigned long DACCLK : 1; + unsigned long CCOCLK : 1; + unsigned long CCOCALIB : 1; + unsigned long TXREV : 1; +#else + unsigned long TXREV : 1; + unsigned long CCOCALIB : 1; + unsigned long CCOCLK : 1; + unsigned long DACCLK : 1; + unsigned long SUCARRY : 1; + unsigned long SUMSEL : 1; + unsigned long DACCARRY : 1; + unsigned long DACMSEL : 1; + unsigned long : 11; + unsigned long IOCSEL : 1; + unsigned long DCOFF : 1; + unsigned long : 1; + unsigned long IOC : 1; + unsigned long CNTRDSEL : 1; + unsigned long TSOC : 1; + unsigned long SUCLKEN : 1; + unsigned long CLKSEL : 2; + unsigned long DRV : 1; + unsigned long TSOD : 1; + unsigned long : 2; +#endif + } BIT; + } CTSUCALIB; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SUADJ0 : 8; + unsigned long SUMULTI0 : 8; + unsigned long SUADJ1 : 8; + unsigned long SUMULTI1 : 8; +#else + unsigned long SUMULTI1 : 8; + unsigned long SUADJ1 : 8; + unsigned long SUMULTI0 : 8; + unsigned long SUADJ0 : 8; +#endif + } BIT; + } CTSUSUCLKA; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SUADJ2 : 8; + unsigned long SUMULTI2 : 8; + unsigned long SUADJ3 : 8; + unsigned long SUMULTI3 : 8; +#else + unsigned long SUMULTI3 : 8; + unsigned long SUADJ3 : 8; + unsigned long SUMULTI2 : 8; + unsigned long SUADJ2 : 8; +#endif + } BIT; + } CTSUSUCLKB; + char wk1[12]; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CCOCFEN : 1; + unsigned long : 3; + unsigned long DTCLESS : 1; + unsigned long MTUCFEN : 1; + unsigned long : 2; + unsigned long AJFEN : 1; + unsigned long : 7; + unsigned long SCACTB : 4; + unsigned long : 12; +#else + unsigned long : 12; + unsigned long SCACTB : 4; + unsigned long : 7; + unsigned long AJFEN : 1; + unsigned long : 2; + unsigned long MTUCFEN : 1; + unsigned long DTCLESS : 1; + unsigned long : 3; + unsigned long CCOCFEN : 1; +#endif + } BIT; + } CTSUOPT; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SCNTACCOEFF : 16; + unsigned long SCNTACCOUNT : 16; +#else + unsigned long SCNTACCOUNT : 16; + unsigned long SCNTACCOEFF : 16; +#endif + } BIT; + } CTSUSCNTACT; + char wk2[16]; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TLOT : 8; + unsigned long THOT : 8; + unsigned long BLINI : 1; + unsigned long : 3; + unsigned long JC : 2; + unsigned long : 2; + unsigned long AJMMAT : 4; + unsigned long AJBMAT : 4; +#else + unsigned long AJBMAT : 4; + unsigned long AJMMAT : 4; + unsigned long : 2; + unsigned long JC : 2; + unsigned long : 3; + unsigned long BLINI : 1; + unsigned long THOT : 8; + unsigned long TLOT : 8; +#endif + } BIT; + } CTSUAJCR; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long AJTHL : 16; + unsigned long AJTHH : 16; +#else + unsigned long AJTHH : 16; + unsigned long AJTHL : 16; +#endif + } BIT; + } CTSUAJTHR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long AJMMATI : 4; + unsigned long : 1; + unsigned long AJMMAR : 27; +#else + unsigned long AJMMAR : 27; + unsigned long : 1; + unsigned long AJMMATI : 4; +#endif + } BIT; + } CTSUAJMMAR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long AJBLACT : 32; +#else + unsigned long AJBLACT : 32; +#endif + } BIT; + } CTSUAJBLACT; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long AJBLAC : 16; + unsigned long AJBLAR : 16; +#else + unsigned long AJBLAR : 16; + unsigned long AJBLAC : 16; +#endif + } BIT; + } CTSUAJBLAR; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TJR0 : 1; + unsigned long TJR1 : 1; + unsigned long TJR2 : 1; + unsigned long TJR3 : 1; + unsigned long FJR : 1; + unsigned long : 3; + unsigned long SJCCR : 8; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long SJCCR : 8; + unsigned long : 3; + unsigned long FJR : 1; + unsigned long TJR3 : 1; + unsigned long TJR2 : 1; + unsigned long TJR1 : 1; + unsigned long TJR0 : 1; +#endif + } BIT; + } CTSUAJRR; + char wk3[7715380]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RTRIM : 8; + unsigned long DACTRIM : 8; + unsigned long SUADJD : 8; + unsigned long TRESULT4 : 8; +#else + unsigned long TRESULT4 : 8; + unsigned long SUADJD : 8; + unsigned long DACTRIM : 8; + unsigned long RTRIM : 8; +#endif + } BIT; + } CTSUTRIMA; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TRESULT0 : 8; + unsigned long TRESULT1 : 8; + unsigned long TRESULT2 : 8; + unsigned long TRESULT3 : 8; +#else + unsigned long TRESULT3 : 8; + unsigned long TRESULT2 : 8; + unsigned long TRESULT1 : 8; + unsigned long TRESULT0 : 8; +#endif + } BIT; + } CTSUTRIMB; +} st_ctsu_t; + +typedef struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char DAOE0 : 1; + unsigned char DAOE1 : 1; +#else + unsigned char DAOE1 : 1; + unsigned char DAOE0 : 1; + unsigned char : 6; +#endif + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DPSEL : 1; +#else + unsigned char DPSEL : 1; + unsigned char : 7; +#endif + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DAADST : 1; +#else + unsigned char DAADST : 1; + unsigned char : 7; +#endif + } BIT; + } DAADSCR; +} st_da_t; + +typedef struct st_doc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OMS : 2; + unsigned char DCSEL : 1; + unsigned char : 1; + unsigned char DOPCIE : 1; + unsigned char DOPCF : 1; + unsigned char DOPCFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char DOPCFCL : 1; + unsigned char DOPCF : 1; + unsigned char DOPCIE : 1; + unsigned char : 1; + unsigned char DCSEL : 1; + unsigned char OMS : 2; +#endif + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +} st_doc_t; + +typedef struct st_dtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char RRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char RRS : 1; + unsigned char : 4; +#endif + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHORT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHORT : 1; +#endif + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCST : 1; +#endif + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ACT : 1; +#else + unsigned short ACT : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif + } BIT; + } DTCSTS; + void *DTCIBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SQTFRL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SQTFRL : 1; +#endif + } BIT; + } DTCOR; + char wk3[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ESPSEL : 1; +#else + unsigned short ESPSEL : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif + } BIT; + } DTCSQE; + unsigned long DTCDISP; +} st_dtc_t; + +typedef struct st_elc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ELCON : 1; +#else + unsigned char ELCON : 1; + unsigned char : 7; +#endif + } BIT; + } ELCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR4; + char wk1[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR7; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR8; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR10; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR12; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR14; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR15; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR16; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR18; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR20; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR22; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR24; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR25; + char wk9[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char MTU1MD : 2; + unsigned char MTU2MD : 2; + unsigned char MTU3MD : 2; +#else + unsigned char MTU3MD : 2; + unsigned char MTU2MD : 2; + unsigned char MTU1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU4MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MTU4MD : 2; +#endif + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char CMT1MD : 2; + unsigned char LPTMD : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LPTMD : 2; + unsigned char CMT1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMR0MD : 2; + unsigned char : 2; + unsigned char TMR2MD : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char TMR2MD : 2; + unsigned char : 2; + unsigned char TMR0MD : 2; +#endif + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR1; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC1; + char wk11[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF1; + char wk12[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL1; + char wk13[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEG : 1; + unsigned char : 5; + unsigned char WE : 1; + unsigned char WI : 1; +#else + unsigned char WI : 1; + unsigned char WE : 1; + unsigned char : 5; + unsigned char SEG : 1; +#endif + } BIT; + } ELSEGR; +} st_elc_t; + +typedef struct st_flash { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DFLEN : 1; +#endif + } BIT; + } DFLCTL; + char wk0[111]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char FMS0 : 1; + unsigned char : 1; + unsigned char RPDIS : 1; + unsigned char FMS1 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char FMS1 : 1; + unsigned char RPDIS : 1; + unsigned char : 1; + unsigned char FMS0 : 1; + unsigned char : 1; +#endif + } BIT; + } FPMCR; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EXS : 1; +#endif + } BIT; + } FASR; + char wk2[3]; + unsigned short FSARL; + char wk3[6]; + unsigned short FSARH; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMD : 4; + unsigned char : 2; + unsigned char STOP : 1; + unsigned char OPST : 1; +#else + unsigned char OPST : 1; + unsigned char STOP : 1; + unsigned char : 2; + unsigned char CMD : 4; +#endif + } BIT; + } FCR; + char wk5[3]; + unsigned short FEARL; + char wk6[6]; + unsigned short FEARH; + char wk7[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FRESET : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char FRESET : 1; +#endif + } BIT; + } FRESETR; + char wk8[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ERERR : 1; + unsigned char PRGERR : 1; + unsigned char : 1; + unsigned char BCERR : 1; + unsigned char ILGLERR : 1; + unsigned char EILGLERR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char EILGLERR : 1; + unsigned char ILGLERR : 1; + unsigned char BCERR : 1; + unsigned char : 1; + unsigned char PRGERR : 1; + unsigned char ERERR : 1; +#endif + } BIT; + } FSTATR0; + char wk9[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char FRDY : 1; + unsigned char EXRDY : 1; +#else + unsigned char EXRDY : 1; + unsigned char FRDY : 1; + unsigned char : 6; +#endif + } BIT; + } FSTATR1; + char wk10[3]; + unsigned short FWB0; + char wk11[6]; + unsigned short FWB1; + char wk12[6]; + unsigned short FWB2; + char wk13[2]; + unsigned short FWB3; + char wk14[58]; + unsigned char FPR; + char wk15[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PERR : 1; +#endif + } BIT; + } FPSR; + char wk16[59]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short SASMF : 1; + unsigned short : 5; + unsigned short AWPR : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short AWPR : 1; + unsigned short : 5; + unsigned short SASMF : 1; + unsigned short : 8; +#endif + } BIT; + } FSCMR; + char wk17[6]; + unsigned short FAWSMR; + char wk18[6]; + unsigned short FAWEMR; + char wk19[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PCKA : 6; + unsigned char SAS : 2; +#else + unsigned char SAS : 2; + unsigned char PCKA : 6; +#endif + } BIT; + } FISR; + char wk20[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMD : 3; + unsigned char : 4; + unsigned char OPST : 1; +#else + unsigned char OPST : 1; + unsigned char : 4; + unsigned char CMD : 3; +#endif + } BIT; + } FEXCR; + char wk21[3]; + unsigned short FEAML; + char wk22[6]; + unsigned short FEAMH; + char wk23[358]; + unsigned long UIDR0; + unsigned long UIDR1; + unsigned long UIDR2; + unsigned long UIDR3; + char wk24[15440]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FENTRY0 : 1; + unsigned short : 6; + unsigned short FENTRYD : 1; + unsigned short FEKEY : 8; +#else + unsigned short FEKEY : 8; + unsigned short FENTRYD : 1; + unsigned short : 6; + unsigned short FENTRY0 : 1; +#endif + } BIT; + } FENTRYR; + char wk25[14]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MEMWAIT : 1; + unsigned short : 7; + unsigned short MEKEY : 8; +#else + unsigned short MEKEY : 8; + unsigned short : 7; + unsigned short MEMWAIT : 1; +#endif + } BIT; + } MEMWAITR; + char wk26[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DFLWAIT : 1; + unsigned short : 7; + unsigned short DFKEY : 8; +#else + unsigned short DFKEY : 8; + unsigned short : 7; + unsigned short DFLWAIT : 1; +#endif + } BIT; + } DFLWAITR; +} st_flash_t; + +typedef struct st_icu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IR : 1; +#endif + } BIT; + } IR[256]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCE : 1; +#endif + } BIT; + } DTCER[256]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IEN0 : 1; + unsigned char IEN1 : 1; + unsigned char IEN2 : 1; + unsigned char IEN3 : 1; + unsigned char IEN4 : 1; + unsigned char IEN5 : 1; + unsigned char IEN6 : 1; + unsigned char IEN7 : 1; +#else + unsigned char IEN7 : 1; + unsigned char IEN6 : 1; + unsigned char IEN5 : 1; + unsigned char IEN4 : 1; + unsigned char IEN3 : 1; + unsigned char IEN2 : 1; + unsigned char IEN1 : 1; + unsigned char IEN0 : 1; +#endif + } BIT; + } IER[32]; + char wk0[192]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT : 1; +#endif + } BIT; + } SWINTR; + char wk1[15]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FVCT : 8; + unsigned short : 7; + unsigned short FIEN : 1; +#else + unsigned short FIEN : 1; + unsigned short : 7; + unsigned short FVCT : 8; +#endif + } BIT; + } FIR; + char wk2[14]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IPR : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IPR : 4; +#endif + } BIT; + } IPR[256]; + char wk3[256]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRQMD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IRQMD : 2; + unsigned char : 2; +#endif + } BIT; + } IRQCR[8]; + char wk4[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN0 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN7 : 1; +#else + unsigned char FLTEN7 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN0 : 1; +#endif + } BIT; + } IRQFLTE0; + char wk5[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL0 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL7 : 2; +#else + unsigned short FCLKSEL7 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL0 : 2; +#endif + } BIT; + } IRQFLTC0; + char wk6[106]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIST : 1; + unsigned char OSTST : 1; + unsigned char : 1; + unsigned char IWDTST : 1; + unsigned char LVD1ST : 1; + unsigned char LVD2ST : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2ST : 1; + unsigned char LVD1ST : 1; + unsigned char IWDTST : 1; + unsigned char : 1; + unsigned char OSTST : 1; + unsigned char NMIST : 1; +#endif + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIEN : 1; + unsigned char OSTEN : 1; + unsigned char : 1; + unsigned char IWDTEN : 1; + unsigned char LVD1EN : 1; + unsigned char LVD2EN : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2EN : 1; + unsigned char LVD1EN : 1; + unsigned char IWDTEN : 1; + unsigned char : 1; + unsigned char OSTEN : 1; + unsigned char NMIEN : 1; +#endif + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMICLR : 1; + unsigned char OSTCLR : 1; + unsigned char : 1; + unsigned char IWDTCLR : 1; + unsigned char LVD1CLR : 1; + unsigned char LVD2CLR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2CLR : 1; + unsigned char LVD1CLR : 1; + unsigned char IWDTCLR : 1; + unsigned char : 1; + unsigned char OSTCLR : 1; + unsigned char NMICLR : 1; +#endif + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char NMIMD : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NMIMD : 1; + unsigned char : 3; +#endif + } BIT; + } NMICR; + char wk7[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFLTEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char NFLTEN : 1; +#endif + } BIT; + } NMIFLTE; + char wk8[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCLKSEL : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char NFCLKSEL : 2; +#endif + } BIT; + } NMIFLTC; +} st_icu_t; + +typedef struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char SLCSTP : 1; +#else + unsigned char SLCSTP : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTCSTPR; +} st_iwdt_t; + +typedef struct st_lpt { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTPSSEL : 3; + unsigned char LPCNTCKSEL2 : 1; + unsigned char LPCNTCKSEL : 1; + unsigned char : 1; + unsigned char LPCMRE0 : 1; + unsigned char LPCMRE1 : 1; +#else + unsigned char LPCMRE1 : 1; + unsigned char LPCMRE0 : 1; + unsigned char : 1; + unsigned char LPCNTCKSEL : 1; + unsigned char LPCNTCKSEL2 : 1; + unsigned char LPCNTPSSEL : 3; +#endif + } BIT; + } LPTCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTSTP : 1; + unsigned char : 4; + unsigned char OPOL : 1; + unsigned char OLVL : 1; + unsigned char PWME : 1; +#else + unsigned char PWME : 1; + unsigned char OLVL : 1; + unsigned char OPOL : 1; + unsigned char : 4; + unsigned char LPCNTSTP : 1; +#endif + } BIT; + } LPTCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTEN : 1; + unsigned char LPCNTRST : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LPCNTRST : 1; + unsigned char LPCNTEN : 1; +#endif + } BIT; + } LPTCR3; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LPCNTPRD : 16; +#else + unsigned short LPCNTPRD : 16; +#endif + } BIT; + } LPTPRD; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LPCMR0 : 16; +#else + unsigned short LPCMR0 : 16; +#endif + } BIT; + } LPCMR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LPCMR1 : 16; +#else + unsigned short LPCMR1 : 16; +#endif + } BIT; + } LPCMR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short LPWKUPEN : 1; +#else + unsigned short LPWKUPEN : 1; + unsigned short : 15; +#endif + } BIT; + } LPWUCR; +} st_lpt_t; + +typedef struct st_mpc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PFSWE : 1; + unsigned char B0WI : 1; +#else + unsigned char B0WI : 1; + unsigned char PFSWE : 1; + unsigned char : 6; +#endif + } BIT; + } PWPR; + char wk0[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } P03PFS; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } P05PFS; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } P07PFS; + char wk3[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P21PFS; + char wk4[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P32PFS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P34PFS; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P36PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P37PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P47PFS; + char wk7[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P55PFS; + char wk8[34]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA6PFS; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB7PFS; + char wk10[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD2PFS; + char wk11[5]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE5PFS; + char wk12[18]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PH0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PH1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PH2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PH3PFS; + char wk13[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PH6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PH7PFS; + char wk14[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PJ1PFS; + char wk15[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PJ6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PJ7PFS; +} st_mpc_t; + +typedef struct st_mtu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE3B : 1; + unsigned char OE4A : 1; + unsigned char OE4B : 1; + unsigned char OE3D : 1; + unsigned char OE4C : 1; + unsigned char OE4D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE4D : 1; + unsigned char OE4C : 1; + unsigned char OE3D : 1; + unsigned char OE4B : 1; + unsigned char OE4A : 1; + unsigned char OE3B : 1; +#endif + } BIT; + } TOER; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UF : 1; + unsigned char VF : 1; + unsigned char WF : 1; + unsigned char FB : 1; + unsigned char P : 1; + unsigned char N : 1; + unsigned char BDC : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BDC : 1; + unsigned char N : 1; + unsigned char P : 1; + unsigned char FB : 1; + unsigned char WF : 1; + unsigned char VF : 1; + unsigned char UF : 1; +#endif + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOCR2; + char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + char wk3[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCOR : 3; + unsigned char T4VEN : 1; + unsigned char T3ACOR : 3; + unsigned char T3AEN : 1; +#else + unsigned char T3AEN : 1; + unsigned char T3ACOR : 3; + unsigned char T4VEN : 1; + unsigned char T4VCOR : 3; +#endif + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCNT : 3; + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; + unsigned char T4VCNT : 3; +#endif + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif + } BIT; + } TBTER; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif + } BIT; + } TDER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOLBR; + char wk6[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char : 6; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 6; + unsigned char WRE : 1; +#endif + } BIT; + } TWCR; + char wk7[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char : 3; + unsigned char CST3 : 1; + unsigned char CST4 : 1; +#else + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char : 3; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char : 3; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; +#else + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char : 3; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif + } BIT; + } TSYR; + char wk8[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif + } BIT; + } TRWER; +} st_mtu_t; + +typedef struct st_mtu0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[111]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk1[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEE : 1; + unsigned char TGIEF : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TGIEF : 1; + unsigned char TGIEE : 1; +#endif + } BIT; + } TIER2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; +} st_mtu0_t; + +typedef struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[238]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char I1AE : 1; + unsigned char I1BE : 1; + unsigned char I2AE : 1; + unsigned char I2BE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char I2BE : 1; + unsigned char I2AE : 1; + unsigned char I1BE : 1; + unsigned char I1AE : 1; +#endif + } BIT; + } TICCR; +} st_mtu1_t; + +typedef struct st_mtu2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[365]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_mtu2_t; + +typedef struct st_mtu3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk8[90]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; +} st_mtu3_t; + +typedef struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITA3AE : 1; + unsigned short DT4BE : 1; + unsigned short UT4BE : 1; + unsigned short DT4AE : 1; + unsigned short UT4AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT4AE : 1; + unsigned short DT4AE : 1; + unsigned short UT4BE : 1; + unsigned short DT4BE : 1; + unsigned short ITA3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITB4VE : 1; +#endif + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[72]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; +} st_mtu4_t; + +typedef struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFUEN : 1; + unsigned char NFVEN : 1; + unsigned char NFWEN : 1; + unsigned char : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 1; + unsigned char NFWEN : 1; + unsigned char NFVEN : 1; + unsigned char NFUEN : 1; +#endif + } BIT; + } NFCR; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRU; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORU; + char wk3[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRV; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORV; + char wk5[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRW; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORW; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIE5W : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TGIE5U : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5W : 1; +#endif + } BIT; + } TIER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CSTW5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTU5 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CSTU5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTW5 : 1; +#endif + } BIT; + } TSTR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCLR5W : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CMPCLR5U : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5W : 1; +#endif + } BIT; + } TCNTCMPCLR; +} st_mtu5_t; + +typedef struct st_ofsm { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MDE : 3; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long MDE : 3; +#endif + } BIT; + } MDE; + char wk0[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VDSEL : 2; + unsigned long LVDAS : 1; + unsigned long FASTSTUP : 1; + unsigned long : 4; + unsigned long HOCOEN : 1; + unsigned long : 3; + unsigned long HOCOFRQ : 2; + unsigned long : 18; +#else + unsigned long : 18; + unsigned long HOCOFRQ : 2; + unsigned long : 3; + unsigned long HOCOEN : 1; + unsigned long : 4; + unsigned long FASTSTUP : 1; + unsigned long LVDAS : 1; + unsigned long VDSEL : 2; +#endif + } BIT; + } OFS1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long IWDTSTRT : 1; + unsigned long IWDTTOPS : 2; + unsigned long IWDTCKS : 4; + unsigned long IWDTRPES : 2; + unsigned long IWDTRPSS : 2; + unsigned long IWDTRSTIRQS : 1; + unsigned long : 1; + unsigned long IWDTSLCSTP : 1; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long IWDTSLCSTP : 1; + unsigned long : 1; + unsigned long IWDTRSTIRQS : 1; + unsigned long IWDTRPSS : 2; + unsigned long IWDTRPES : 2; + unsigned long IWDTCKS : 4; + unsigned long IWDTTOPS : 2; + unsigned long IWDTSTRT : 1; + unsigned long : 1; +#endif + } BIT; + } OFS0; +} st_ofsm_t; + +typedef struct st_poe { + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE0M : 2; + unsigned short POE1M : 2; + unsigned short POE2M : 2; + unsigned short POE3M : 2; + unsigned short PIE1 : 1; + unsigned short : 3; + unsigned short POE0F : 1; + unsigned short POE1F : 1; + unsigned short POE2F : 1; + unsigned short POE3F : 1; +#else + unsigned short POE3F : 1; + unsigned short POE2F : 1; + unsigned short POE1F : 1; + unsigned short POE0F : 1; + unsigned short : 3; + unsigned short PIE1 : 1; + unsigned short POE3M : 2; + unsigned short POE2M : 2; + unsigned short POE1M : 2; + unsigned short POE0M : 2; +#endif + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE1 : 1; + unsigned short OCE1 : 1; + unsigned short : 5; + unsigned short OSF1 : 1; +#else + unsigned short OSF1 : 1; + unsigned short : 5; + unsigned short OCE1 : 1; + unsigned short OIE1 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR1; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE8M : 2; + unsigned short : 6; + unsigned short PIE2 : 1; + unsigned short POE8E : 1; + unsigned short : 2; + unsigned short POE8F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE8F : 1; + unsigned short : 2; + unsigned short POE8E : 1; + unsigned short PIE2 : 1; + unsigned short : 6; + unsigned short POE8M : 2; +#endif + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CH34HIZ : 1; + unsigned char CH0HIZ : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CH0HIZ : 1; + unsigned char CH34HIZ : 1; +#endif + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PE0ZE : 1; + unsigned char PE1ZE : 1; + unsigned char PE2ZE : 1; + unsigned char PE3ZE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char PE3ZE : 1; + unsigned char PE2ZE : 1; + unsigned char PE1ZE : 1; + unsigned char PE0ZE : 1; +#endif + } BIT; + } POECR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char P3CZEA : 1; + unsigned char P2CZEA : 1; + unsigned char P1CZEA : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char P1CZEA : 1; + unsigned char P2CZEA : 1; + unsigned char P3CZEA : 1; + unsigned char : 4; +#endif + } BIT; + } POECR2; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short : 8; + unsigned short OSTSTE : 1; + unsigned short : 2; + unsigned short OSTSTF : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short OSTSTF : 1; + unsigned short : 2; + unsigned short OSTSTE : 1; + unsigned short : 8; + unsigned short : 1; +#endif + } BIT; + } ICSR3; +} st_poe_t; + +typedef struct st_port { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL0 : 1; + unsigned char PSEL1 : 1; + unsigned char : 1; + unsigned char PSEL3 : 1; + unsigned char : 1; + unsigned char PSEL5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL5 : 1; + unsigned char : 1; + unsigned char PSEL3 : 1; + unsigned char : 1; + unsigned char PSEL1 : 1; + unsigned char PSEL0 : 1; +#endif + } BIT; + } PSRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PSEL6 : 1; + unsigned char PSEL7 : 1; +#else + unsigned char PSEL7 : 1; + unsigned char PSEL6 : 1; + unsigned char : 6; +#endif + } BIT; + } PSRA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WAIT : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char WAIT : 2; +#endif + } BIT; + } PRWCNTR; +} st_port_t; + +typedef struct st_port0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PCR; +} st_port0_t; + +typedef struct st_port1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PCR; +} st_port1_t; + +typedef struct st_port2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 4; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 4; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 4; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 4; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 4; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 4; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 4; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 4; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char : 4; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 4; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_port2_t; + +typedef struct st_port3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_port3_t; + +typedef struct st_port4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_port4_t; + +typedef struct st_port5 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } PCR; +} st_port5_t; + +typedef struct st_porta { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_porta_t; + +typedef struct st_portb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_portb_t; + +typedef struct st_portc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PCR; +} st_portc_t; + +typedef struct st_portd { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[44]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + char wk4[50]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_portd_t; + +typedef struct st_porte { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + char wk4[49]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_porte_t; + +typedef struct st_portg { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 7; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 7; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 7; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 7; +#endif + } BIT; + } PMR; + char wk3[48]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } ODR1; + char wk4[46]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 7; +#endif + } BIT; + } PCR; +} st_portg_t; + +typedef struct st_porth { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +} st_porth_t; + +typedef struct st_portj { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 4; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 4; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 4; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 4; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 4; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 4; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 4; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 4; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 4; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 4; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } PCR; +} st_portj_t; + +typedef struct st_riic { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDAI : 1; + unsigned char SCLI : 1; + unsigned char SDAO : 1; + unsigned char SCLO : 1; + unsigned char SOWP : 1; + unsigned char CLO : 1; + unsigned char IICRST : 1; + unsigned char ICE : 1; +#else + unsigned char ICE : 1; + unsigned char IICRST : 1; + unsigned char CLO : 1; + unsigned char SOWP : 1; + unsigned char SCLO : 1; + unsigned char SDAO : 1; + unsigned char SCLI : 1; + unsigned char SDAI : 1; +#endif + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char ST : 1; + unsigned char RS : 1; + unsigned char SP : 1; + unsigned char : 1; + unsigned char TRS : 1; + unsigned char MST : 1; + unsigned char BBSY : 1; +#else + unsigned char BBSY : 1; + unsigned char MST : 1; + unsigned char TRS : 1; + unsigned char : 1; + unsigned char SP : 1; + unsigned char RS : 1; + unsigned char ST : 1; + unsigned char : 1; +#endif + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BC : 3; + unsigned char BCWP : 1; + unsigned char CKS : 3; + unsigned char MTWP : 1; +#else + unsigned char MTWP : 1; + unsigned char CKS : 3; + unsigned char BCWP : 1; + unsigned char BC : 3; +#endif + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOS : 1; + unsigned char TMOL : 1; + unsigned char TMOH : 1; + unsigned char : 1; + unsigned char SDDL : 3; + unsigned char DLCS : 1; +#else + unsigned char DLCS : 1; + unsigned char SDDL : 3; + unsigned char : 1; + unsigned char TMOH : 1; + unsigned char TMOL : 1; + unsigned char TMOS : 1; +#endif + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NF : 2; + unsigned char ACKBR : 1; + unsigned char ACKBT : 1; + unsigned char ACKWP : 1; + unsigned char RDRFS : 1; + unsigned char WAIT : 1; + unsigned char SMBS : 1; +#else + unsigned char SMBS : 1; + unsigned char WAIT : 1; + unsigned char RDRFS : 1; + unsigned char ACKWP : 1; + unsigned char ACKBT : 1; + unsigned char ACKBR : 1; + unsigned char NF : 2; +#endif + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOE : 1; + unsigned char MALE : 1; + unsigned char NALE : 1; + unsigned char SALE : 1; + unsigned char NACKE : 1; + unsigned char NFE : 1; + unsigned char SCLE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SCLE : 1; + unsigned char NFE : 1; + unsigned char NACKE : 1; + unsigned char SALE : 1; + unsigned char NALE : 1; + unsigned char MALE : 1; + unsigned char TMOE : 1; +#endif + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SAR0E : 1; + unsigned char SAR1E : 1; + unsigned char SAR2E : 1; + unsigned char GCAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char HOAE : 1; +#else + unsigned char HOAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char GCAE : 1; + unsigned char SAR2E : 1; + unsigned char SAR1E : 1; + unsigned char SAR0E : 1; +#endif + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOIE : 1; + unsigned char ALIE : 1; + unsigned char STIE : 1; + unsigned char SPIE : 1; + unsigned char NAKIE : 1; + unsigned char RIE : 1; + unsigned char TEIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char TEIE : 1; + unsigned char RIE : 1; + unsigned char NAKIE : 1; + unsigned char SPIE : 1; + unsigned char STIE : 1; + unsigned char ALIE : 1; + unsigned char TMOIE : 1; +#endif + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AAS0 : 1; + unsigned char AAS1 : 1; + unsigned char AAS2 : 1; + unsigned char GCA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char HOA : 1; +#else + unsigned char HOA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char GCA : 1; + unsigned char AAS2 : 1; + unsigned char AAS1 : 1; + unsigned char AAS0 : 1; +#endif + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOF : 1; + unsigned char AL : 1; + unsigned char START : 1; + unsigned char STOP : 1; + unsigned char NACKF : 1; + unsigned char RDRF : 1; + unsigned char TEND : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char TEND : 1; + unsigned char RDRF : 1; + unsigned char NACKF : 1; + unsigned char STOP : 1; + unsigned char START : 1; + unsigned char AL : 1; + unsigned char TMOF : 1; +#endif + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRL : 5; +#endif + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRH : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRH : 5; +#endif + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +} st_riic_t; + +typedef struct st_rscan { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TPRI : 1; + unsigned short DCE : 1; + unsigned short DRE : 1; + unsigned short MME : 1; + unsigned short DCS : 1; + unsigned short : 3; + unsigned short TSP : 4; + unsigned short TSSS : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short TSSS : 1; + unsigned short TSP : 4; + unsigned short : 3; + unsigned short DCS : 1; + unsigned short MME : 1; + unsigned short DRE : 1; + unsigned short DCE : 1; + unsigned short TPRI : 1; +#endif + } BIT; + } GCFGL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITRCP : 16; +#else + unsigned short ITRCP : 16; +#endif + } BIT; + } GCFGH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GMDC : 2; + unsigned short GSLPR : 1; + unsigned short : 5; + unsigned short DEIE : 1; + unsigned short MEIE : 1; + unsigned short THLEIE : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short THLEIE : 1; + unsigned short MEIE : 1; + unsigned short DEIE : 1; + unsigned short : 5; + unsigned short GSLPR : 1; + unsigned short GMDC : 2; +#endif + } BIT; + } GCTRL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSRST : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short TSRST : 1; +#endif + } BIT; + } GCTRH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GRSTSTS : 1; + unsigned short GHLTSTS : 1; + unsigned short GSLPSTS : 1; + unsigned short GRAMINIT : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short GRAMINIT : 1; + unsigned short GSLPSTS : 1; + unsigned short GHLTSTS : 1; + unsigned short GRSTSTS : 1; +#endif + } BIT; + } GSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DEF : 1; + unsigned char MES : 1; + unsigned char THLES : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char THLES : 1; + unsigned char MES : 1; + unsigned char DEF : 1; +#endif + } BIT; + } GERFLL; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TS : 16; +#else + unsigned short TS : 16; +#endif + } BIT; + } GTSC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RNC0 : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short RNC0 : 5; +#endif + } BIT; + } GAFLCFG; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short NRXMB : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short NRXMB : 5; +#endif + } BIT; + } RMNB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMNS : 16; +#else + unsigned short RMNS : 16; +#endif + } BIT; + } RMND0; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFE : 1; + unsigned short RFIE : 1; + unsigned short : 6; + unsigned short RFDC : 3; + unsigned short : 1; + unsigned short RFIM : 1; + unsigned short RFIGCV : 3; +#else + unsigned short RFIGCV : 3; + unsigned short RFIM : 1; + unsigned short : 1; + unsigned short RFDC : 3; + unsigned short : 6; + unsigned short RFIE : 1; + unsigned short RFE : 1; +#endif + } BIT; + } RFCC0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFE : 1; + unsigned short RFIE : 1; + unsigned short : 6; + unsigned short RFDC : 3; + unsigned short : 1; + unsigned short RFIM : 1; + unsigned short RFIGCV : 3; +#else + unsigned short RFIGCV : 3; + unsigned short RFIM : 1; + unsigned short : 1; + unsigned short RFDC : 3; + unsigned short : 6; + unsigned short RFIE : 1; + unsigned short RFE : 1; +#endif + } BIT; + } RFCC1; + char wk2[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFEMP : 1; + unsigned short RFFLL : 1; + unsigned short RFMLT : 1; + unsigned short RFIF : 1; + unsigned short : 4; + unsigned short RFMC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RFMC : 6; + unsigned short : 4; + unsigned short RFIF : 1; + unsigned short RFMLT : 1; + unsigned short RFFLL : 1; + unsigned short RFEMP : 1; +#endif + } BIT; + } RFSTS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFEMP : 1; + unsigned short RFFLL : 1; + unsigned short RFMLT : 1; + unsigned short RFIF : 1; + unsigned short : 4; + unsigned short RFMC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RFMC : 6; + unsigned short : 4; + unsigned short RFIF : 1; + unsigned short RFMLT : 1; + unsigned short RFFLL : 1; + unsigned short RFEMP : 1; +#endif + } BIT; + } RFSTS1; + char wk3[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFPC : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short RFPC : 8; +#endif + } BIT; + } RFPCTR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFPC : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short RFPC : 8; +#endif + } BIT; + } RFPCTR1; + char wk4[20]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RF0MLT : 1; + unsigned char RF1MLT : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char RF1MLT : 1; + unsigned char RF0MLT : 1; +#endif + } BIT; + } RFMSTS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RF0IF : 1; + unsigned char RF1IF : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char RF1IF : 1; + unsigned char RF0IF : 1; +#endif + } BIT; + } RFISTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0IF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CF0IF : 1; +#endif + } BIT; + } CFISTS; + char wk6[36]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSIF0 : 1; + unsigned short TAIF0 : 1; + unsigned short CFTIF0 : 1; + unsigned short THIF0 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short THIF0 : 1; + unsigned short CFTIF0 : 1; + unsigned short TAIF0 : 1; + unsigned short TSIF0 : 1; +#endif + } BIT; + } GTINTSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RPAGE : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RPAGE : 1; +#endif + } BIT; + } GRWCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short RTMPS : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short RTMPS : 3; + unsigned short : 8; +#endif + } BIT; + } GTSTCFG; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char RTME : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char RTME : 1; + unsigned char : 2; +#endif + } BIT; + } GTSTCTRL; + char wk7[5]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LOCK : 16; +#else + unsigned short LOCK : 16; +#endif + } BIT; + } GLOCKK; + char wk8[10]; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL0; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH0; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS0; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR0; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF00; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF20; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF30; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL1; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH1; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS1; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR1; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF01; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF21; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF31; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL2; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH2; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS2; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR2; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF02; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF12; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF22; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF32; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL3; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH3; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS3; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR3; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF03; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF13; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF23; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF33; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL4; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH4; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS4; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR4; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF04; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF14; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF24; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF34; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL5; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH5; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS5; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR5; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF05; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF15; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF25; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF35; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL6; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH6; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS6; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR6; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF06; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF16; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF26; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF36; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL7; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH7; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS7; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR7; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF07; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF17; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF27; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF37; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL8; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH8; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS8; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR8; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF08; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF18; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF28; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF38; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL9; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH9; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS9; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR9; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF09; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF19; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF29; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF39; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF010; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF110; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF210; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF310; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF011; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF111; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF211; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF311; + }; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF012; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF112; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF212; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF312; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF013; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF113; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF213; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF313; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF014; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF114; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF214; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF314; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF015; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF115; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF215; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF315; + char wk9[224]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC15; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFID : 16; +#else + unsigned short RFID : 16; +#endif + } BIT; + } RFIDL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC16; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFID : 13; + unsigned short : 1; + unsigned short RFRTR : 1; + unsigned short RFIDE : 1; +#else + unsigned short RFIDE : 1; + unsigned short RFRTR : 1; + unsigned short : 1; + unsigned short RFID : 13; +#endif + } BIT; + } RFIDH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC17; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFTS : 16; +#else + unsigned short RFTS : 16; +#endif + } BIT; + } RFTS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC18; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFPTR : 12; + unsigned short RFDLC : 4; +#else + unsigned short RFDLC : 4; + unsigned short RFPTR : 12; +#endif + } BIT; + } RFPTR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC19; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB0 : 8; + unsigned short RFDB1 : 8; +#else + unsigned short RFDB1 : 8; + unsigned short RFDB0 : 8; +#endif + } BIT; + } RFDF00; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC20; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB2 : 8; + unsigned short RFDB3 : 8; +#else + unsigned short RFDB3 : 8; + unsigned short RFDB2 : 8; +#endif + } BIT; + } RFDF10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC21; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB4 : 8; + unsigned short RFDB5 : 8; +#else + unsigned short RFDB5 : 8; + unsigned short RFDB4 : 8; +#endif + } BIT; + } RFDF20; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC22; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB6 : 8; + unsigned short RFDB7 : 8; +#else + unsigned short RFDB7 : 8; + unsigned short RFDB6 : 8; +#endif + } BIT; + } RFDF30; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC23; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFID : 16; +#else + unsigned short RFID : 16; +#endif + } BIT; + } RFIDL1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC24; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFID : 13; + unsigned short : 1; + unsigned short RFRTR : 1; + unsigned short RFIDE : 1; +#else + unsigned short RFIDE : 1; + unsigned short RFRTR : 1; + unsigned short : 1; + unsigned short RFID : 13; +#endif + } BIT; + } RFIDH1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC25; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFTS : 16; +#else + unsigned short RFTS : 16; +#endif + } BIT; + } RFTS1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC26; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFPTR : 12; + unsigned short RFDLC : 4; +#else + unsigned short RFDLC : 4; + unsigned short RFPTR : 12; +#endif + } BIT; + } RFPTR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC27; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB0 : 8; + unsigned short RFDB1 : 8; +#else + unsigned short RFDB1 : 8; + unsigned short RFDB0 : 8; +#endif + } BIT; + } RFDF01; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC28; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB2 : 8; + unsigned short RFDB3 : 8; +#else + unsigned short RFDB3 : 8; + unsigned short RFDB2 : 8; +#endif + } BIT; + } RFDF11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC29; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB4 : 8; + unsigned short RFDB5 : 8; +#else + unsigned short RFDB5 : 8; + unsigned short RFDB4 : 8; +#endif + } BIT; + } RFDF21; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC30; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB6 : 8; + unsigned short RFDB7 : 8; +#else + unsigned short RFDB7 : 8; + unsigned short RFDB6 : 8; +#endif + } BIT; + } RFDF31; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC31; + }; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC32; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC33; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC34; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC35; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC36; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC37; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC38; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC39; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC40; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC41; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC42; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC43; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC44; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC45; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC46; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC47; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC48; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC49; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC50; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC51; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC52; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC53; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC54; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC55; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC56; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC57; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC58; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC59; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC60; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC61; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC62; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC63; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC64; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC65; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC66; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC67; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC68; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC69; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC70; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC71; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC72; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC73; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC74; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC75; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC76; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC77; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC78; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC79; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC80; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC81; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC82; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC83; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC84; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC85; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC86; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC87; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC88; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC89; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC90; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC91; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC92; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC93; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC94; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC95; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC96; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC97; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC98; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC99; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC100; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC101; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC102; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC103; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC104; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC105; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC106; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC107; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC108; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC109; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC110; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC111; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC112; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC113; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC114; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC115; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC116; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC117; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC118; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC119; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC120; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC121; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC122; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC123; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC124; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC125; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC126; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC127; +} st_rscan_t; + +typedef struct st_rscan0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BRP : 10; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short BRP : 10; +#endif + } BIT; + } CFGL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSEG1 : 4; + unsigned short TSEG2 : 3; + unsigned short : 1; + unsigned short SJW : 2; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short SJW : 2; + unsigned short : 1; + unsigned short TSEG2 : 3; + unsigned short TSEG1 : 4; +#endif + } BIT; + } CFGH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CHMDC : 2; + unsigned short CSLPR : 1; + unsigned short RTBO : 1; + unsigned short : 4; + unsigned short BEIE : 1; + unsigned short EWIE : 1; + unsigned short EPIE : 1; + unsigned short BOEIE : 1; + unsigned short BORIE : 1; + unsigned short OLIE : 1; + unsigned short BLIE : 1; + unsigned short ALIE : 1; +#else + unsigned short ALIE : 1; + unsigned short BLIE : 1; + unsigned short OLIE : 1; + unsigned short BORIE : 1; + unsigned short BOEIE : 1; + unsigned short EPIE : 1; + unsigned short EWIE : 1; + unsigned short BEIE : 1; + unsigned short : 4; + unsigned short RTBO : 1; + unsigned short CSLPR : 1; + unsigned short CHMDC : 2; +#endif + } BIT; + } CTRL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TAIE : 1; + unsigned short : 4; + unsigned short BOM : 2; + unsigned short ERRD : 1; + unsigned short CTME : 1; + unsigned short CTMS : 2; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CTMS : 2; + unsigned short CTME : 1; + unsigned short ERRD : 1; + unsigned short BOM : 2; + unsigned short : 4; + unsigned short TAIE : 1; +#endif + } BIT; + } CTRH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CRSTSTS : 1; + unsigned short CHLTSTS : 1; + unsigned short CSLPSTS : 1; + unsigned short EPSTS : 1; + unsigned short BOSTS : 1; + unsigned short TRMSTS : 1; + unsigned short RECSTS : 1; + unsigned short COMSTS : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short COMSTS : 1; + unsigned short RECSTS : 1; + unsigned short TRMSTS : 1; + unsigned short BOSTS : 1; + unsigned short EPSTS : 1; + unsigned short CSLPSTS : 1; + unsigned short CHLTSTS : 1; + unsigned short CRSTSTS : 1; +#endif + } BIT; + } STSL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short REC : 8; + unsigned short TEC : 8; +#else + unsigned short TEC : 8; + unsigned short REC : 8; +#endif + } BIT; + } STSH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BEF : 1; + unsigned short EWF : 1; + unsigned short EPF : 1; + unsigned short BOEF : 1; + unsigned short BORF : 1; + unsigned short OVLF : 1; + unsigned short BLF : 1; + unsigned short ALF : 1; + unsigned short SERR : 1; + unsigned short FERR : 1; + unsigned short AERR : 1; + unsigned short CERR : 1; + unsigned short B1ERR : 1; + unsigned short B0ERR : 1; + unsigned short ADERR : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short ADERR : 1; + unsigned short B0ERR : 1; + unsigned short B1ERR : 1; + unsigned short CERR : 1; + unsigned short AERR : 1; + unsigned short FERR : 1; + unsigned short SERR : 1; + unsigned short ALF : 1; + unsigned short BLF : 1; + unsigned short OVLF : 1; + unsigned short BORF : 1; + unsigned short BOEF : 1; + unsigned short EPF : 1; + unsigned short EWF : 1; + unsigned short BEF : 1; +#endif + } BIT; + } ERFLL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CRCREG : 15; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short CRCREG : 15; +#endif + } BIT; + } ERFLH; + char wk0[64]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFE : 1; + unsigned short CFRXIE : 1; + unsigned short CFTXIE : 1; + unsigned short : 5; + unsigned short CFDC : 3; + unsigned short : 1; + unsigned short CFIM : 1; + unsigned short CFIGCV : 3; +#else + unsigned short CFIGCV : 3; + unsigned short CFIM : 1; + unsigned short : 1; + unsigned short CFDC : 3; + unsigned short : 5; + unsigned short CFTXIE : 1; + unsigned short CFRXIE : 1; + unsigned short CFE : 1; +#endif + } BIT; + } CFCCL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFM : 2; + unsigned short CFITSS : 1; + unsigned short CFITR : 1; + unsigned short CFTML : 2; + unsigned short : 2; + unsigned short CFITT : 8; +#else + unsigned short CFITT : 8; + unsigned short : 2; + unsigned short CFTML : 2; + unsigned short CFITR : 1; + unsigned short CFITSS : 1; + unsigned short CFM : 2; +#endif + } BIT; + } CFCCH0; + char wk1[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFEMP : 1; + unsigned short CFFLL : 1; + unsigned short CFMLT : 1; + unsigned short CFRXIF : 1; + unsigned short CFTXIF : 1; + unsigned short : 3; + unsigned short CFMC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short CFMC : 6; + unsigned short : 3; + unsigned short CFTXIF : 1; + unsigned short CFRXIF : 1; + unsigned short CFMLT : 1; + unsigned short CFFLL : 1; + unsigned short CFEMP : 1; +#endif + } BIT; + } CFSTS0; + char wk2[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFPC : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CFPC : 8; +#endif + } BIT; + } CFPCTR0; + char wk3[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0MLT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CF0MLT : 1; +#endif + } BIT; + } CFMSTS; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTR : 1; + unsigned char TMTAR : 1; + unsigned char TMOM : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TMOM : 1; + unsigned char TMTAR : 1; + unsigned char TMTR : 1; +#endif + } BIT; + } TMC0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTR : 1; + unsigned char TMTAR : 1; + unsigned char TMOM : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TMOM : 1; + unsigned char TMTAR : 1; + unsigned char TMTR : 1; +#endif + } BIT; + } TMC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTR : 1; + unsigned char TMTAR : 1; + unsigned char TMOM : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TMOM : 1; + unsigned char TMTAR : 1; + unsigned char TMTR : 1; +#endif + } BIT; + } TMC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTR : 1; + unsigned char TMTAR : 1; + unsigned char TMOM : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TMOM : 1; + unsigned char TMTAR : 1; + unsigned char TMTR : 1; +#endif + } BIT; + } TMC3; + char wk5[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTSTS : 1; + unsigned char TMTRF : 2; + unsigned char TMTRM : 1; + unsigned char TMTARM : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TMTARM : 1; + unsigned char TMTRM : 1; + unsigned char TMTRF : 2; + unsigned char TMTSTS : 1; +#endif + } BIT; + } TMSTS0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTSTS : 1; + unsigned char TMTRF : 2; + unsigned char TMTRM : 1; + unsigned char TMTARM : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TMTARM : 1; + unsigned char TMTRM : 1; + unsigned char TMTRF : 2; + unsigned char TMTSTS : 1; +#endif + } BIT; + } TMSTS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTSTS : 1; + unsigned char TMTRF : 2; + unsigned char TMTRM : 1; + unsigned char TMTARM : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TMTARM : 1; + unsigned char TMTRM : 1; + unsigned char TMTRF : 2; + unsigned char TMTSTS : 1; +#endif + } BIT; + } TMSTS2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTSTS : 1; + unsigned char TMTRF : 2; + unsigned char TMTRM : 1; + unsigned char TMTARM : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TMTARM : 1; + unsigned char TMTRM : 1; + unsigned char TMTRF : 2; + unsigned char TMTSTS : 1; +#endif + } BIT; + } TMSTS3; + char wk6[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMTRSTS0 : 1; + unsigned short TMTRSTS1 : 1; + unsigned short TMTRSTS2 : 1; + unsigned short TMTRSTS3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short TMTRSTS3 : 1; + unsigned short TMTRSTS2 : 1; + unsigned short TMTRSTS1 : 1; + unsigned short TMTRSTS0 : 1; +#endif + } BIT; + } TMTRSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMTCSTS0 : 1; + unsigned short TMTCSTS1 : 1; + unsigned short TMTCSTS2 : 1; + unsigned short TMTCSTS3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short TMTCSTS3 : 1; + unsigned short TMTCSTS2 : 1; + unsigned short TMTCSTS1 : 1; + unsigned short TMTCSTS0 : 1; +#endif + } BIT; + } TMTCSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMTASTS0 : 1; + unsigned short TMTASTS1 : 1; + unsigned short TMTASTS2 : 1; + unsigned short TMTASTS3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short TMTASTS3 : 1; + unsigned short TMTASTS2 : 1; + unsigned short TMTASTS1 : 1; + unsigned short TMTASTS0 : 1; +#endif + } BIT; + } TMTASTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMIE0 : 1; + unsigned short TMIE1 : 1; + unsigned short TMIE2 : 1; + unsigned short TMIE3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short TMIE3 : 1; + unsigned short TMIE2 : 1; + unsigned short TMIE1 : 1; + unsigned short TMIE0 : 1; +#endif + } BIT; + } TMIEC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short THLE : 1; + unsigned short : 7; + unsigned short THLIE : 1; + unsigned short THLIM : 1; + unsigned short THLDTE : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short THLDTE : 1; + unsigned short THLIM : 1; + unsigned short THLIE : 1; + unsigned short : 7; + unsigned short THLE : 1; +#endif + } BIT; + } THLCC0; + char wk7[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short THLEMP : 1; + unsigned short THLFLL : 1; + unsigned short THLELT : 1; + unsigned short THLIF : 1; + unsigned short : 4; + unsigned short THLMC : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short THLMC : 4; + unsigned short : 4; + unsigned short THLIF : 1; + unsigned short THLELT : 1; + unsigned short THLFLL : 1; + unsigned short THLEMP : 1; +#endif + } BIT; + } THLSTS0; + char wk8[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short THLPC : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short THLPC : 8; +#endif + } BIT; + } THLPCTR0; + char wk9[602]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFID : 16; +#else + unsigned short CFID : 16; +#endif + } BIT; + } CFIDL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFID : 13; + unsigned short THLEN : 1; + unsigned short CFRTR : 1; + unsigned short CFIDE : 1; +#else + unsigned short CFIDE : 1; + unsigned short CFRTR : 1; + unsigned short THLEN : 1; + unsigned short CFID : 13; +#endif + } BIT; + } CFIDH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFTS : 16; +#else + unsigned short CFTS : 16; +#endif + } BIT; + } CFTS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFPTR : 12; + unsigned short CFDLC : 4; +#else + unsigned short CFDLC : 4; + unsigned short CFPTR : 12; +#endif + } BIT; + } CFPTR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFDB0 : 8; + unsigned short CFDB1 : 8; +#else + unsigned short CFDB1 : 8; + unsigned short CFDB0 : 8; +#endif + } BIT; + } CFDF00; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFDB2 : 8; + unsigned short CFDB3 : 8; +#else + unsigned short CFDB3 : 8; + unsigned short CFDB2 : 8; +#endif + } BIT; + } CFDF10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFDB4 : 8; + unsigned short CFDB5 : 8; +#else + unsigned short CFDB5 : 8; + unsigned short CFDB4 : 8; +#endif + } BIT; + } CFDF20; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFDB6 : 8; + unsigned short CFDB7 : 8; +#else + unsigned short CFDB7 : 8; + unsigned short CFDB6 : 8; +#endif + } BIT; + } CFDF30; + char wk10[16]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 16; +#else + unsigned short TMID : 16; +#endif + } BIT; + } TMIDL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 13; + unsigned short THLEN : 1; + unsigned short TMRTR : 1; + unsigned short TMIDE : 1; +#else + unsigned short TMIDE : 1; + unsigned short TMRTR : 1; + unsigned short THLEN : 1; + unsigned short TMID : 13; +#endif + } BIT; + } TMIDH0; + char wk11[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMPTR : 8; + unsigned short : 4; + unsigned short TMDLC : 4; +#else + unsigned short TMDLC : 4; + unsigned short : 4; + unsigned short TMPTR : 8; +#endif + } BIT; + } TMPTR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB0 : 8; + unsigned short TMDB1 : 8; +#else + unsigned short TMDB1 : 8; + unsigned short TMDB0 : 8; +#endif + } BIT; + } TMDF00; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB2 : 8; + unsigned short TMDB3 : 8; +#else + unsigned short TMDB3 : 8; + unsigned short TMDB2 : 8; +#endif + } BIT; + } TMDF10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB4 : 8; + unsigned short TMDB5 : 8; +#else + unsigned short TMDB5 : 8; + unsigned short TMDB4 : 8; +#endif + } BIT; + } TMDF20; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB6 : 8; + unsigned short TMDB7 : 8; +#else + unsigned short TMDB7 : 8; + unsigned short TMDB6 : 8; +#endif + } BIT; + } TMDF30; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 16; +#else + unsigned short TMID : 16; +#endif + } BIT; + } TMIDL1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 13; + unsigned short THLEN : 1; + unsigned short TMRTR : 1; + unsigned short TMIDE : 1; +#else + unsigned short TMIDE : 1; + unsigned short TMRTR : 1; + unsigned short THLEN : 1; + unsigned short TMID : 13; +#endif + } BIT; + } TMIDH1; + char wk12[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMPTR : 8; + unsigned short : 4; + unsigned short TMDLC : 4; +#else + unsigned short TMDLC : 4; + unsigned short : 4; + unsigned short TMPTR : 8; +#endif + } BIT; + } TMPTR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB0 : 8; + unsigned short TMDB1 : 8; +#else + unsigned short TMDB1 : 8; + unsigned short TMDB0 : 8; +#endif + } BIT; + } TMDF01; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB2 : 8; + unsigned short TMDB3 : 8; +#else + unsigned short TMDB3 : 8; + unsigned short TMDB2 : 8; +#endif + } BIT; + } TMDF11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB4 : 8; + unsigned short TMDB5 : 8; +#else + unsigned short TMDB5 : 8; + unsigned short TMDB4 : 8; +#endif + } BIT; + } TMDF21; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB6 : 8; + unsigned short TMDB7 : 8; +#else + unsigned short TMDB7 : 8; + unsigned short TMDB6 : 8; +#endif + } BIT; + } TMDF31; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 16; +#else + unsigned short TMID : 16; +#endif + } BIT; + } TMIDL2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 13; + unsigned short THLEN : 1; + unsigned short TMRTR : 1; + unsigned short TMIDE : 1; +#else + unsigned short TMIDE : 1; + unsigned short TMRTR : 1; + unsigned short THLEN : 1; + unsigned short TMID : 13; +#endif + } BIT; + } TMIDH2; + char wk13[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMPTR : 8; + unsigned short : 4; + unsigned short TMDLC : 4; +#else + unsigned short TMDLC : 4; + unsigned short : 4; + unsigned short TMPTR : 8; +#endif + } BIT; + } TMPTR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB0 : 8; + unsigned short TMDB1 : 8; +#else + unsigned short TMDB1 : 8; + unsigned short TMDB0 : 8; +#endif + } BIT; + } TMDF02; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB2 : 8; + unsigned short TMDB3 : 8; +#else + unsigned short TMDB3 : 8; + unsigned short TMDB2 : 8; +#endif + } BIT; + } TMDF12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB4 : 8; + unsigned short TMDB5 : 8; +#else + unsigned short TMDB5 : 8; + unsigned short TMDB4 : 8; +#endif + } BIT; + } TMDF22; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB6 : 8; + unsigned short TMDB7 : 8; +#else + unsigned short TMDB7 : 8; + unsigned short TMDB6 : 8; +#endif + } BIT; + } TMDF32; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 16; +#else + unsigned short TMID : 16; +#endif + } BIT; + } TMIDL3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 13; + unsigned short THLEN : 1; + unsigned short TMRTR : 1; + unsigned short TMIDE : 1; +#else + unsigned short TMIDE : 1; + unsigned short TMRTR : 1; + unsigned short THLEN : 1; + unsigned short TMID : 13; +#endif + } BIT; + } TMIDH3; + char wk14[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMPTR : 8; + unsigned short : 4; + unsigned short TMDLC : 4; +#else + unsigned short TMDLC : 4; + unsigned short : 4; + unsigned short TMPTR : 8; +#endif + } BIT; + } TMPTR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB0 : 8; + unsigned short TMDB1 : 8; +#else + unsigned short TMDB1 : 8; + unsigned short TMDB0 : 8; +#endif + } BIT; + } TMDF03; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB2 : 8; + unsigned short TMDB3 : 8; +#else + unsigned short TMDB3 : 8; + unsigned short TMDB2 : 8; +#endif + } BIT; + } TMDF13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB4 : 8; + unsigned short TMDB5 : 8; +#else + unsigned short TMDB5 : 8; + unsigned short TMDB4 : 8; +#endif + } BIT; + } TMDF23; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB6 : 8; + unsigned short TMDB7 : 8; +#else + unsigned short TMDB7 : 8; + unsigned short TMDB6 : 8; +#endif + } BIT; + } TMDF33; + char wk15[64]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BT : 2; + unsigned short : 1; + unsigned short BN : 2; + unsigned short : 3; + unsigned short TID : 8; +#else + unsigned short TID : 8; + unsigned short : 3; + unsigned short BN : 2; + unsigned short : 1; + unsigned short BT : 2; +#endif + } BIT; + } THLACC0; +} st_rscan0_t; + +typedef struct st_rspi { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPMS : 1; + unsigned char TXMD : 1; + unsigned char MODFEN : 1; + unsigned char MSTR : 1; + unsigned char SPEIE : 1; + unsigned char SPTIE : 1; + unsigned char SPE : 1; + unsigned char SPRIE : 1; +#else + unsigned char SPRIE : 1; + unsigned char SPE : 1; + unsigned char SPTIE : 1; + unsigned char SPEIE : 1; + unsigned char MSTR : 1; + unsigned char MODFEN : 1; + unsigned char TXMD : 1; + unsigned char SPMS : 1; +#endif + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSL0P : 1; + unsigned char SSL1P : 1; + unsigned char SSL2P : 1; + unsigned char SSL3P : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char SSL3P : 1; + unsigned char SSL2P : 1; + unsigned char SSL1P : 1; + unsigned char SSL0P : 1; +#endif + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char SPLP2 : 1; + unsigned char : 2; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 2; + unsigned char SPLP2 : 1; + unsigned char SPLP : 1; +#endif + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OVRF : 1; + unsigned char IDLNF : 1; + unsigned char MODF : 1; + unsigned char PERF : 1; + unsigned char UDRF : 1; + unsigned char SPTEF : 1; + unsigned char : 1; + unsigned char SPRF : 1; +#else + unsigned char SPRF : 1; + unsigned char : 1; + unsigned char SPTEF : 1; + unsigned char UDRF : 1; + unsigned char PERF : 1; + unsigned char MODF : 1; + unsigned char IDLNF : 1; + unsigned char OVRF : 1; +#endif + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + struct { + unsigned char HH; + } BYTE; + } SPDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSLN : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPSLN : 3; +#endif + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPCP : 3; + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; + unsigned char SPCP : 3; +#endif + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPFC : 2; + unsigned char : 2; + unsigned char SPRDTD : 1; + unsigned char SPLW : 1; + unsigned char SPBYT : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPBYT : 1; + unsigned char SPLW : 1; + unsigned char SPRDTD : 1; + unsigned char : 2; + unsigned char SPFC : 2; +#endif + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPPE : 1; + unsigned char SPOE : 1; + unsigned char SPIIE : 1; + unsigned char PTE : 1; + unsigned char SCKASE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SCKASE : 1; + unsigned char PTE : 1; + unsigned char SPIIE : 1; + unsigned char SPOE : 1; + unsigned char SPPE : 1; +#endif + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD7; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BYSW : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BYSW : 1; +#endif + } BIT; + } SPDCR2; +} st_rspi_t; + +typedef struct st_rtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char F64HZ : 1; + unsigned char F32HZ : 1; + unsigned char F16HZ : 1; + unsigned char F8HZ : 1; + unsigned char F4HZ : 1; + unsigned char F2HZ : 1; + unsigned char F1HZ : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char F1HZ : 1; + unsigned char F2HZ : 1; + unsigned char F4HZ : 1; + unsigned char F8HZ : 1; + unsigned char F16HZ : 1; + unsigned char F32HZ : 1; + unsigned char F64HZ : 1; +#endif + } BIT; + } R64CNT; + char wk0[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT0; + }; + char wk1[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT1; + }; + char wk2[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT2; + }; + char wk3[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT3; + }; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRCNT; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT0AR; + }; + char wk7[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT1AR; + }; + char wk8[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT2AR; + }; + char wk9[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 4; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 4; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT3AR; + }; + char wk10[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 1; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT0AER; + }; + char wk11[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 2; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 2; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT1AER; + }; + char wk12[1]; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRAR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ENB : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ENB : 8; +#endif + } BIT; + } BCNT2AER; + }; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 7; +#endif + } BIT; + } RYRAREN; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT3AER; + }; + char wk13[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AIE : 1; + unsigned char CIE : 1; + unsigned char PIE : 1; + unsigned char RTCOS : 1; + unsigned char PES : 4; +#else + unsigned char PES : 4; + unsigned char RTCOS : 1; + unsigned char PIE : 1; + unsigned char CIE : 1; + unsigned char AIE : 1; +#endif + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char START : 1; + unsigned char RESET : 1; + unsigned char ADJ30 : 1; + unsigned char RTCOE : 1; + unsigned char AADJE : 1; + unsigned char AADJP : 1; + unsigned char HR24 : 1; + unsigned char CNTMD : 1; +#else + unsigned char CNTMD : 1; + unsigned char HR24 : 1; + unsigned char AADJP : 1; + unsigned char AADJE : 1; + unsigned char RTCOE : 1; + unsigned char ADJ30 : 1; + unsigned char RESET : 1; + unsigned char START : 1; +#endif + } BIT; + } RCR2; + char wk15[9]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADJ : 6; + unsigned char PMADJ : 2; +#else + unsigned char PMADJ : 2; + unsigned char ADJ : 6; +#endif + } BIT; + } RADJ; +} st_rtc_t; + +typedef struct st_rtcb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT0; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT3; + char wk3[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT0AR; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT1AR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT2AR; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT3AR; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT0AER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT1AER; + char wk9[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ENB : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ENB : 8; +#endif + } BIT; + } BCNT2AER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT3AER; +} st_rtcb_t; + +typedef struct st_s12ad { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short ADHSC : 1; + unsigned short : 1; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 1; + unsigned short ADHSC : 1; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA000 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA007 : 1; + unsigned short ANSA008 : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short ANSA008 : 1; + unsigned short ANSA007 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA000 : 1; +#endif + } BIT; + } ADANSA0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA100 : 1; + unsigned short ANSA101 : 1; + unsigned short ANSA102 : 1; + unsigned short ANSA103 : 1; + unsigned short ANSA104 : 1; + unsigned short ANSA105 : 1; + unsigned short : 2; + unsigned short ANSA108 : 1; + unsigned short ANSA109 : 1; + unsigned short ANSA110 : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short ANSA110 : 1; + unsigned short ANSA109 : 1; + unsigned short ANSA108 : 1; + unsigned short : 2; + unsigned short ANSA105 : 1; + unsigned short ANSA104 : 1; + unsigned short ANSA103 : 1; + unsigned short ANSA102 : 1; + unsigned short ANSA101 : 1; + unsigned short ANSA100 : 1; +#endif + } BIT; + } ADANSA1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS000 : 1; + unsigned short ADS001 : 1; + unsigned short ADS002 : 1; + unsigned short ADS003 : 1; + unsigned short ADS004 : 1; + unsigned short ADS005 : 1; + unsigned short ADS006 : 1; + unsigned short ADS007 : 1; + unsigned short ADS008 : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short ADS008 : 1; + unsigned short ADS007 : 1; + unsigned short ADS006 : 1; + unsigned short ADS005 : 1; + unsigned short ADS004 : 1; + unsigned short ADS003 : 1; + unsigned short ADS002 : 1; + unsigned short ADS001 : 1; + unsigned short ADS000 : 1; +#endif + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS100 : 1; + unsigned short ADS101 : 1; + unsigned short ADS102 : 1; + unsigned short ADS103 : 1; + unsigned short ADS104 : 1; + unsigned short ADS105 : 1; + unsigned short : 2; + unsigned short ADS108 : 1; + unsigned short ADS109 : 1; + unsigned short ADS110 : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short ADS110 : 1; + unsigned short ADS109 : 1; + unsigned short ADS108 : 1; + unsigned short : 2; + unsigned short ADS105 : 1; + unsigned short ADS104 : 1; + unsigned short ADS103 : 1; + unsigned short ADS102 : 1; + unsigned short ADS101 : 1; + unsigned short ADS100 : 1; +#endif + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 3; + unsigned char : 4; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 4; + unsigned char ADC : 3; +#endif + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 5; +#endif + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 6; + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; + unsigned short TRSB : 6; +#endif + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSSAD : 1; + unsigned short OCSAD : 1; + unsigned short : 6; + unsigned short TSSA : 1; + unsigned short OCSA : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short OCSA : 1; + unsigned short TSSA : 1; + unsigned short : 6; + unsigned short OCSAD : 1; + unsigned short TSSAD : 1; +#endif + } BIT; + } ADEXICR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB000 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB007 : 1; + unsigned short ANSB008 : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short ANSB008 : 1; + unsigned short ANSB007 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB000 : 1; +#endif + } BIT; + } ADANSB0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB100 : 1; + unsigned short ANSB101 : 1; + unsigned short ANSB102 : 1; + unsigned short ANSB103 : 1; + unsigned short ANSB104 : 1; + unsigned short ANSB105 : 1; + unsigned short : 2; + unsigned short ANSB108 : 1; + unsigned short ANSB109 : 1; + unsigned short ANSB110 : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short ANSB110 : 1; + unsigned short ANSB109 : 1; + unsigned short ANSB108 : 1; + unsigned short : 2; + unsigned short ANSB105 : 1; + unsigned short ANSB104 : 1; + unsigned short ANSB103 : 1; + unsigned short ANSB102 : 1; + unsigned short ANSB101 : 1; + unsigned short ANSB100 : 1; +#endif + } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union { + unsigned short WORD; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif + } RIGHT; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + unsigned short ADDR8; + char wk2[14]; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + unsigned short ADDR21; + char wk3[4]; + unsigned short ADDR24; + unsigned short ADDR25; + unsigned short ADDR26; + char wk4[36]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif + } BIT; + } ADDISCR; + char wk5[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELCC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char ELCC : 2; +#endif + } BIT; + } ADELCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char CCS : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CCS : 1; + unsigned char : 1; +#endif + } BIT; + } ADCCR; + char wk6[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 13; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short : 13; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif + } BIT; + } ADGSPCR; + char wk7[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HVSEL : 2; + unsigned char : 2; + unsigned char LVSEL : 1; + unsigned char : 2; + unsigned char ADSLP : 1; +#else + unsigned char ADSLP : 1; + unsigned char : 2; + unsigned char LVSEL : 1; + unsigned char : 2; + unsigned char HVSEL : 2; +#endif + } BIT; + } ADHVREFCNT; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MONCOMB : 1; + unsigned char : 3; + unsigned char MONCMPA : 1; + unsigned char MONCMPB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MONCMPB : 1; + unsigned char MONCMPA : 1; + unsigned char : 3; + unsigned char MONCOMB : 1; +#endif + } BIT; + } ADWINMON; + char wk9[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPAB : 2; + unsigned short : 7; + unsigned short CMPBE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 2; + unsigned short WCMPE : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short WCMPE : 1; + unsigned short : 2; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBE : 1; + unsigned short : 7; + unsigned short CMPAB : 2; +#endif + } BIT; + } ADCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPTSA : 1; + unsigned char CMPOCA : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPOCA : 1; + unsigned char CMPTSA : 1; +#endif + } BIT; + } ADCMPANSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPLTSA : 1; + unsigned char CMPLOCA : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPLOCA : 1; + unsigned char CMPLTSA : 1; +#endif + } BIT; + } ADCMPLER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA000 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA008 : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short CMPCHA008 : 1; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA000 : 1; +#endif + } BIT; + } ADCMPANSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA100 : 1; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA102 : 1; + unsigned short CMPCHA103 : 1; + unsigned short CMPCHA104 : 1; + unsigned short CMPCHA105 : 1; + unsigned short : 2; + unsigned short CMPCHA108 : 1; + unsigned short CMPCHA109 : 1; + unsigned short CMPCHA110 : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CMPCHA110 : 1; + unsigned short CMPCHA109 : 1; + unsigned short CMPCHA108 : 1; + unsigned short : 2; + unsigned short CMPCHA105 : 1; + unsigned short CMPCHA104 : 1; + unsigned short CMPCHA103 : 1; + unsigned short CMPCHA102 : 1; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA100 : 1; +#endif + } BIT; + } ADCMPANSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA000 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA008 : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short CMPLCHA008 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA000 : 1; +#endif + } BIT; + } ADCMPLR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA100 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA102 : 1; + unsigned short CMPLCHA103 : 1; + unsigned short CMPLCHA104 : 1; + unsigned short CMPLCHA105 : 1; + unsigned short : 2; + unsigned short CMPLCHA108 : 1; + unsigned short CMPLCHA109 : 1; + unsigned short CMPLCHA110 : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CMPLCHA110 : 1; + unsigned short CMPLCHA109 : 1; + unsigned short CMPLCHA108 : 1; + unsigned short : 2; + unsigned short CMPLCHA105 : 1; + unsigned short CMPLCHA104 : 1; + unsigned short CMPLCHA103 : 1; + unsigned short CMPLCHA102 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA100 : 1; +#endif + } BIT; + } ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA000 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA008 : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short CMPSTCHA008 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA000 : 1; +#endif + } BIT; + } ADCMPSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA100 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA102 : 1; + unsigned short CMPSTCHA103 : 1; + unsigned short CMPSTCHA104 : 1; + unsigned short CMPSTCHA105 : 1; + unsigned short : 2; + unsigned short CMPSTCHA108 : 1; + unsigned short CMPSTCHA109 : 1; + unsigned short CMPSTCHA110 : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CMPSTCHA110 : 1; + unsigned short CMPSTCHA109 : 1; + unsigned short CMPSTCHA108 : 1; + unsigned short : 2; + unsigned short CMPSTCHA105 : 1; + unsigned short CMPSTCHA104 : 1; + unsigned short CMPSTCHA103 : 1; + unsigned short CMPSTCHA102 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA100 : 1; +#endif + } BIT; + } ADCMPSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTTSA : 1; + unsigned char CMPSTOCA : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPSTOCA : 1; + unsigned char CMPSTTSA : 1; +#endif + } BIT; + } ADCMPSER; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCHB : 6; + unsigned char : 1; + unsigned char CMPLB : 1; +#else + unsigned char CMPLB : 1; + unsigned char : 1; + unsigned char CMPCHB : 6; +#endif + } BIT; + } ADCMPBNSR; + char wk11[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTB : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CMPSTB : 1; +#endif + } BIT; + } ADCMPBSR; + char wk12[3]; + unsigned short ADBUF0; + unsigned short ADBUF1; + unsigned short ADBUF2; + unsigned short ADBUF3; + unsigned short ADBUF4; + unsigned short ADBUF5; + unsigned short ADBUF6; + unsigned short ADBUF7; + unsigned short ADBUF8; + unsigned short ADBUF9; + unsigned short ADBUF10; + unsigned short ADBUF11; + unsigned short ADBUF12; + unsigned short ADBUF13; + unsigned short ADBUF14; + unsigned short ADBUF15; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BUFEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BUFEN : 1; +#endif + } BIT; + } ADBUFEN; + char wk13[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BUFPTR : 4; + unsigned char PTROVF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PTROVF : 1; + unsigned char BUFPTR : 4; +#endif + } BIT; + } ADBUFPTR; + char wk14[10]; + unsigned char ADSSTRL; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; + unsigned char ADSSTR8; +} st_s12ad_t; + +typedef struct st_sci1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char ITE : 1; + unsigned char BRME : 1; + unsigned char ABCSE : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char ABCSE : 1; + unsigned char BRME : 1; + unsigned char ITE : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCMF : 1; + unsigned char : 2; + unsigned char DPER : 1; + unsigned char DFER : 1; + unsigned char : 1; + unsigned char IDSEL : 1; + unsigned char DCME : 1; +#else + unsigned char DCME : 1; + unsigned char IDSEL : 1; + unsigned char : 1; + unsigned char DFER : 1; + unsigned char DPER : 1; + unsigned char : 2; + unsigned char DCMF : 1; +#endif + } BIT; + } DCCR; + char wk0[6]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPD : 9; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short CMPD : 9; +#endif + } BIT; + } CDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RXDMON : 1; + unsigned char SPB2DT : 1; + unsigned char SPB2IO : 1; + unsigned char : 1; + unsigned char RINV : 1; + unsigned char TINV : 1; + unsigned char RTADJ : 1; + unsigned char TTADJ : 1; +#else + unsigned char TTADJ : 1; + unsigned char RTADJ : 1; + unsigned char TINV : 1; + unsigned char RINV : 1; + unsigned char : 1; + unsigned char SPB2IO : 1; + unsigned char SPB2DT : 1; + unsigned char RXDMON : 1; +#endif + } BIT; + } SPTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RTMG : 4; + unsigned char TTMG : 4; +#else + unsigned char TTMG : 4; + unsigned char RTMG : 4; +#endif + } BIT; + } TMGR; +} st_sci1_t; + +typedef struct st_sci6 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +} st_sci6_t; + +typedef struct st_sci12 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ESME : 1; +#endif + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SFSF : 1; + unsigned char RXDSF : 1; + unsigned char BRME : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char BRME : 1; + unsigned char RXDSF : 1; + unsigned char SFSF : 1; + unsigned char : 1; +#endif + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFE : 1; + unsigned char CF0RE : 1; + unsigned char CF1DS : 2; + unsigned char PIBE : 1; + unsigned char PIBS : 3; +#else + unsigned char PIBS : 3; + unsigned char PIBE : 1; + unsigned char CF1DS : 2; + unsigned char CF0RE : 1; + unsigned char BFE : 1; +#endif + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFCS : 3; + unsigned char : 1; + unsigned char BCCS : 2; + unsigned char RTS : 2; +#else + unsigned char RTS : 2; + unsigned char BCCS : 2; + unsigned char : 1; + unsigned char DFCS : 3; +#endif + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SDST : 1; +#endif + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TXDXPS : 1; + unsigned char RXDXPS : 1; + unsigned char : 2; + unsigned char SHARPS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SHARPS : 1; + unsigned char : 2; + unsigned char RXDXPS : 1; + unsigned char TXDXPS : 1; +#endif + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDIE : 1; + unsigned char CF0MIE : 1; + unsigned char CF1MIE : 1; + unsigned char PIBDIE : 1; + unsigned char BCDIE : 1; + unsigned char AEDIE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDIE : 1; + unsigned char BCDIE : 1; + unsigned char PIBDIE : 1; + unsigned char CF1MIE : 1; + unsigned char CF0MIE : 1; + unsigned char BFDIE : 1; +#endif + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDF : 1; + unsigned char CF0MF : 1; + unsigned char CF1MF : 1; + unsigned char PIBDF : 1; + unsigned char BCDF : 1; + unsigned char AEDF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDF : 1; + unsigned char BCDF : 1; + unsigned char PIBDF : 1; + unsigned char CF1MF : 1; + unsigned char CF0MF : 1; + unsigned char BFDF : 1; +#endif + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDCL : 1; + unsigned char CF0MCL : 1; + unsigned char CF1MCL : 1; + unsigned char PIBDCL : 1; + unsigned char BCDCL : 1; + unsigned char AEDCL : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDCL : 1; + unsigned char BCDCL : 1; + unsigned char PIBDCL : 1; + unsigned char CF1MCL : 1; + unsigned char CF0MCL : 1; + unsigned char BFDCL : 1; +#endif + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0CE0 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE7 : 1; +#else + unsigned char CF0CE7 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE0 : 1; +#endif + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF1CE0 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE7 : 1; +#else + unsigned char CF1CE7 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE0 : 1; +#endif + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCST : 1; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TOMS : 2; + unsigned char : 1; + unsigned char TWRC : 1; + unsigned char TCSS : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char TCSS : 3; + unsigned char TWRC : 1; + unsigned char : 1; + unsigned char TOMS : 2; +#endif + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +} st_sci12_t; + +typedef struct st_smci { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char BCP : 2; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char BLK : 1; + unsigned char GM : 1; +#else + unsigned char GM : 1; + unsigned char BLK : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char BCP : 2; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char ERS : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char ERS : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + char wk0[7]; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +} st_smci_t; + +typedef struct st_system { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short MD : 1; +#endif + } BIT; + } MDMONR; + char wk0[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RAME : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RAME : 1; +#endif + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short SSBY : 1; +#else + unsigned short SSBY : 1; + unsigned short : 15; +#endif + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long MSTPA4 : 1; + unsigned long MSTPA5 : 1; + unsigned long : 3; + unsigned long MSTPA9 : 1; + unsigned long : 5; + unsigned long MSTPA15 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA19 : 1; + unsigned long : 8; + unsigned long MSTPA28 : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long MSTPA28 : 1; + unsigned long : 8; + unsigned long MSTPA19 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA15 : 1; + unsigned long : 5; + unsigned long MSTPA9 : 1; + unsigned long : 3; + unsigned long MSTPA5 : 1; + unsigned long MSTPA4 : 1; + unsigned long : 4; +#endif + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPB0 : 1; + unsigned long : 3; + unsigned long MSTPB4 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 2; + unsigned long MSTPB9 : 1; + unsigned long MSTPB10 : 1; + unsigned long : 6; + unsigned long MSTPB17 : 1; + unsigned long : 3; + unsigned long MSTPB21 : 1; + unsigned long : 1; + unsigned long MSTPB23 : 1; + unsigned long : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB26 : 1; + unsigned long : 3; + unsigned long MSTPB30 : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long MSTPB30 : 1; + unsigned long : 3; + unsigned long MSTPB26 : 1; + unsigned long MSTPB25 : 1; + unsigned long : 1; + unsigned long MSTPB23 : 1; + unsigned long : 1; + unsigned long MSTPB21 : 1; + unsigned long : 3; + unsigned long MSTPB17 : 1; + unsigned long : 6; + unsigned long MSTPB10 : 1; + unsigned long MSTPB9 : 1; + unsigned long : 2; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB4 : 1; + unsigned long : 3; + unsigned long MSTPB0 : 1; +#endif + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPC0 : 1; + unsigned long : 18; + unsigned long MSTPC19 : 1; + unsigned long : 6; + unsigned long MSTPC26 : 1; + unsigned long MSTPC27 : 1; + unsigned long : 3; + unsigned long DSLPE : 1; +#else + unsigned long DSLPE : 1; + unsigned long : 3; + unsigned long MSTPC27 : 1; + unsigned long MSTPC26 : 1; + unsigned long : 6; + unsigned long MSTPC19 : 1; + unsigned long : 18; + unsigned long MSTPC0 : 1; +#endif + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 10; + unsigned long MSTPD10 : 1; + unsigned long : 18; + unsigned long MSTPD29 : 1; + unsigned long MSTPD30 : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long MSTPD30 : 1; + unsigned long MSTPD29 : 1; + unsigned long : 18; + unsigned long MSTPD10 : 1; + unsigned long : 10; +#endif + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKD : 4; + unsigned long : 4; + unsigned long PCKB : 4; + unsigned long : 12; + unsigned long ICK : 4; + unsigned long FCK : 4; +#else + unsigned long FCK : 4; + unsigned long ICK : 4; + unsigned long : 12; + unsigned long PCKB : 4; + unsigned long : 4; + unsigned long PCKD : 4; +#endif + } BIT; + } SCKCR; + char wk3[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKSEL : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CKSEL : 3; + unsigned short : 8; +#endif + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PLIDIV : 2; + unsigned short : 6; + unsigned short STC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short STC : 6; + unsigned short : 6; + unsigned short PLIDIV : 2; +#endif + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PLLEN : 1; +#endif + } BIT; + } PLLCR2; + char wk4[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MOSTP : 1; +#endif + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SOSTP : 1; +#endif + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LCSTP : 1; +#endif + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ILCSTP : 1; +#endif + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HCSTP : 1; +#endif + } BIT; + } HOCOCR; + char wk5[5]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOOVF : 1; + unsigned char : 1; + unsigned char PLOVF : 1; + unsigned char HCOVF : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char HCOVF : 1; + unsigned char PLOVF : 1; + unsigned char : 1; + unsigned char MOOVF : 1; +#endif + } BIT; + } OSCOVFSR; + char wk6[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKOSEL : 4; + unsigned short CKODIV : 3; + unsigned short CKOSTP : 1; +#else + unsigned short CKOSTP : 1; + unsigned short CKODIV : 3; + unsigned short CKOSEL : 4; + unsigned short : 8; +#endif + } BIT; + } CKOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDIE : 1; + unsigned char : 6; + unsigned char OSTDE : 1; +#else + unsigned char OSTDE : 1; + unsigned char : 6; + unsigned char OSTDIE : 1; +#endif + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char OSTDF : 1; +#endif + } BIT; + } OSTDSR; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LOFXIN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LOFXIN : 1; +#endif + } BIT; + } LOFCR; + char wk8[29]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LOCOTRD2 : 8; +#else + unsigned char LOCOTRD2 : 8; +#endif + } BIT; + } LOCOTRR2; + char wk9[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILOCOTRD : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ILOCOTRD : 5; +#endif + } BIT; + } ILOCOTRR; + char wk10[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOCOTRD : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char HOCOTRD : 6; +#endif + } BIT; + } HOCOTRR0; + char wk11[26]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SODRV : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char SODRV : 2; +#endif + } BIT; + } SOMCR; + char wk12[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OPCM : 3; + unsigned char : 1; + unsigned char OPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char OPCMTSF : 1; + unsigned char : 1; + unsigned char OPCM : 3; +#endif + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RSTCKSEL : 3; + unsigned char : 4; + unsigned char RSTCKEN : 1; +#else + unsigned char RSTCKEN : 1; + unsigned char : 4; + unsigned char RSTCKSEL : 3; +#endif + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MSTS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MSTS : 5; +#endif + } BIT; + } MOSCWTCR; + char wk13[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOPCM : 1; + unsigned char : 3; + unsigned char SOPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SOPCMTSF : 1; + unsigned char : 3; + unsigned char SOPCM : 1; +#endif + } BIT; + } SOPCCR; + char wk14[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SCIERE : 1; + unsigned short : 1; + unsigned short SCIRXE : 2; + unsigned short LPTCM1E : 2; + unsigned short ADE : 2; + unsigned short CTSUFNE : 2; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short CTSUFNE : 2; + unsigned short ADE : 2; + unsigned short LPTCM1E : 2; + unsigned short SCIRXE : 2; + unsigned short : 1; + unsigned short SCIERE : 1; +#endif + } BIT; + } SNZCR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SCISNZSEL : 2; + unsigned short LPTSNZSEL : 2; + unsigned short ADCSNZSEL : 2; + unsigned short CTSUSNZSEL : 2; + unsigned short : 7; + unsigned short SNZDTCE : 1; +#else + unsigned short SNZDTCE : 1; + unsigned short : 7; + unsigned short CTSUSNZSEL : 2; + unsigned short ADCSNZSEL : 2; + unsigned short LPTSNZSEL : 2; + unsigned short SCISNZSEL : 2; +#endif + } BIT; + } SNZCR; + char wk15[16]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IWDTRF : 1; + unsigned char : 1; + unsigned char SWRF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SWRF : 1; + unsigned char : 1; + unsigned char IWDTRF : 1; +#endif + } BIT; + } RSTSR2; + char wk16[1]; + unsigned short SWRR; + char wk17[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1IDTSEL : 2; + unsigned char LVD1IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD1IRQSEL : 1; + unsigned char LVD1IDTSEL : 2; +#endif + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1DET : 1; + unsigned char LVD1MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD1MON : 1; + unsigned char LVD1DET : 1; +#endif + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2IDTSEL : 2; + unsigned char LVD2IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD2IRQSEL : 1; + unsigned char LVD2IDTSEL : 2; +#endif + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2DET : 1; + unsigned char LVD2MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD2MON : 1; + unsigned char LVD2DET : 1; +#endif + } BIT; + } LVD2SR; + char wk18[794]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PRC0 : 1; + unsigned short PRC1 : 1; + unsigned short PRC2 : 1; + unsigned short PRC3 : 1; + unsigned short : 4; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 4; + unsigned short PRC3 : 1; + unsigned short PRC2 : 1; + unsigned short PRC1 : 1; + unsigned short PRC0 : 1; +#endif + } BIT; + } PRCR; + char wk19[48784]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PORF : 1; + unsigned char LVD0RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD2RF : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char LVD2RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD0RF : 1; + unsigned char PORF : 1; +#endif + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CWSF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CWSF : 1; +#endif + } BIT; + } RSTSR1; + char wk20[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char MODRV21 : 1; + unsigned char MOSEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MOSEL : 1; + unsigned char MODRV21 : 1; + unsigned char : 5; +#endif + } BIT; + } MOFCR; + char wk21[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char EXVCCINP2 : 1; + unsigned char : 1; + unsigned char LVD1E : 1; + unsigned char LVD2E : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LVD2E : 1; + unsigned char LVD1E : 1; + unsigned char : 1; + unsigned char EXVCCINP2 : 1; + unsigned char : 3; +#endif + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1LVL : 4; + unsigned char LVD2LVL : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2LVL : 2; + unsigned char LVD1LVL : 4; +#endif + } BIT; + } LVDLVLR; + char wk22[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1RIE : 1; + unsigned char : 1; + unsigned char LVD1CMPE : 1; + unsigned char : 3; + unsigned char LVD1RI : 1; + unsigned char LVD1RN : 1; +#else + unsigned char LVD1RN : 1; + unsigned char LVD1RI : 1; + unsigned char : 3; + unsigned char LVD1CMPE : 1; + unsigned char : 1; + unsigned char LVD1RIE : 1; +#endif + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2RIE : 1; + unsigned char : 1; + unsigned char LVD2CMPE : 1; + unsigned char : 3; + unsigned char LVD2RI : 1; + unsigned char LVD2RN : 1; +#else + unsigned char LVD2RN : 1; + unsigned char LVD2RI : 1; + unsigned char : 3; + unsigned char LVD2CMPE : 1; + unsigned char : 1; + unsigned char LVD2RIE : 1; +#endif + } BIT; + } LVD2CR0; +} st_system_t; + +typedef struct st_temps { + unsigned short TSCDR; +} st_temps_t; + +typedef struct st_tmr0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif + } BIT; + } TCSTR; +} st_tmr0_t; + +typedef struct st_tmr1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; +} st_tmr1_t; + +typedef struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +} st_tmr01_t; + + +#pragma pack() + +#endif + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/vecttbl.c b/drivers/rx/rdp/src/r_bsp/mcu/rx140/vecttbl.c new file mode 100644 index 00000000..0d64c224 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/vecttbl.c @@ -0,0 +1,128 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : vecttbl.c +* Device(s) : RX140 +* Description : Definition of the exception vector table and option setting memory. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First Release +* : 21.11.2023 1.01 Deleted the BSP_CFG_ROM_CODE_PROTECT_VALUE. +* Modified comment. +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* BSP configuration. */ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +R_BSP_POR_FUNCTION(R_BSP_POWER_ON_RESET_FUNCTION); + +/*********************************************************************************************************************** +* The following array fills in the endian and option function select registers, and the exception vector table +* bytes. +***********************************************************************************************************************/ +#ifdef __BIG + #define BSP_PRV_MDE_VALUE (0xfffffff8) /* big */ +#else + #define BSP_PRV_MDE_VALUE (0xffffffff) /* little */ +#endif + +#if defined(__ICCRX__) + +#pragma public_equ = "__MDE", BSP_PRV_MDE_VALUE +#pragma public_equ = "__OFS1", BSP_CFG_OFS1_REG_VALUE +#pragma public_equ = "__OFS0", BSP_CFG_OFS0_REG_VALUE +#pragma public_equ = "__OSIS_1", BSP_CFG_ID_CODE_LONG_1 +#pragma public_equ = "__OSIS_2", BSP_CFG_ID_CODE_LONG_2 +#pragma public_equ = "__OSIS_3", BSP_CFG_ID_CODE_LONG_3 +#pragma public_equ = "__OSIS_4", BSP_CFG_ID_CODE_LONG_4 + +#endif /* defined(__ICCRX__) */ + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + /* System configurator generates the ritble.src as interrupt & exception vector tables. */ +#else /* BSP_CFG_RTOS_USED!=4 */ + +#if defined(__CCRX__) || defined(__GNUC__) +R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT void * const Except_Vectors[] = +{ + /* The Endian select register (MDE), Option function select register 1 (OFS1), and Option function select + register 0 (OFS0) are located in User ROM. */ + (void *)BSP_PRV_MDE_VALUE, /* 0xffffff80 - Endian */ + (void *)0xFFFFFFFF, /* 0xffffff84 - Reserved */ + (void *)BSP_CFG_OFS1_REG_VALUE, /* 0xffffff88 - OFS1 register defined in r_bsp_config.h */ + (void *)BSP_CFG_OFS0_REG_VALUE, /* 0xffffff8c - OFS0 register defined in r_bsp_config.h */ + (void *)0xFFFFFFFF, /* 0xffffff90 - Reserved */ + (void *)0xFFFFFFFF, /* 0xffffff94 - Reserved */ + (void *)0xFFFFFFFF, /* 0xffffff98 - Reserved */ + (void *)0xFFFFFFFF, /* 0xffffff9C - Reserved */ + + /* The memory are immediately below (0xffffffa0 through 0xffffffaf) is a special area that allows the on-chip + firmware to be protected. See the section "ID Code Protection" in the HW manual for details on how to enable + protection. Setting the four long words below to non-0xFF values will enable protection. Do this only after + carefully review the HW manual */ + + /* 0xffffffa0 through 0xffffffaf: ID Code Protection. The ID code is specified using macros in r_bsp_config.h. */ + (void *) BSP_CFG_ID_CODE_LONG_1, /* 0xffffffa0 - Control code and ID code */ + (void *) BSP_CFG_ID_CODE_LONG_2, /* 0xffffffa4 - ID code (cont.) */ + (void *) BSP_CFG_ID_CODE_LONG_3, /* 0xffffffa8 - ID code (cont.) */ + (void *) BSP_CFG_ID_CODE_LONG_4, /* 0xffffffac - ID code (cont.) */ + + /* 0xffffffb0 through 0xffffffcf: Reserved area */ + (void *) 0xFFFFFFFF, /* 0xffffffb0 - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffb4 - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffb8 - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffbc - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffc0 - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffc4 - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffc8 - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffcc - Reserved */ + + /* Exception vector table */ + (void *) excep_supervisor_inst_isr, /* 0xffffffd0 Exception(Supervisor Instruction) */ + (void *) undefined_interrupt_source_isr, /* 0xffffffd4 Reserved */ + (void *) undefined_interrupt_source_isr, /* 0xffffffd8 Reserved */ + (void *) excep_undefined_inst_isr, /* 0xffffffdc Exception(Undefined Instruction) */ + (void *) undefined_interrupt_source_isr, /* 0xffffffe0 Reserved */ + (void *) excep_floating_point_isr, /* 0xffffffe4 Exception(Floating Point) */ + (void *) undefined_interrupt_source_isr, /* 0xffffffe8 Reserved */ + (void *) undefined_interrupt_source_isr, /* 0xffffffec Reserved */ + (void *) undefined_interrupt_source_isr, /* 0xfffffff0 Reserved */ + (void *) undefined_interrupt_source_isr, /* 0xfffffff4 Reserved */ + (void *) non_maskable_isr /* 0xfffffff8 (0x80 + 0x78) NMI */ +}; +R_BSP_ATTRIB_SECTION_CHANGE_END +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +/*********************************************************************************************************************** +* The following array fills in the reset vector. +***********************************************************************************************************************/ +#if defined(__CCRX__) || defined(__GNUC__) +R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT void (* const Reset_Vector[])(void) = +{ + R_BSP_POWER_ON_RESET_FUNCTION /* 0xfffffffc RESET */ +}; +R_BSP_ATTRIB_SECTION_CHANGE_END +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +#endif/* BSP_CFG_RTOS_USED */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx140/vecttbl.h b/drivers/rx/rdp/src/r_bsp/mcu/rx140/vecttbl.h new file mode 100644 index 00000000..f3182c4e --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx140/vecttbl.h @@ -0,0 +1,36 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : vecttbl.h +* Description : Has function prototypes for exception callback functions. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First release +* : 26.02.2025 1.01 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef VECTTBL_HEADER_INC +#define VECTTBL_HEADER_INC + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* VECTTBL_HEADER_INC */ + diff --git a/drivers/rx/rdp/src/r_bsp/platform.h b/drivers/rx/rdp/src/r_bsp/platform.h index 24300028..357db390 100644 --- a/drivers/rx/rdp/src/r_bsp/platform.h +++ b/drivers/rx/rdp/src/r_bsp/platform.h @@ -233,7 +233,9 @@ DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING. //#include "./board/generic_rx13t/r_bsp.h" /* GENERIC_RX140 */ -//#include "./board/generic_rx140/r_bsp.h" +#if defined(CONFIG_SOC_SERIES_RX140) +#include "./board/generic_rx140/r_bsp.h" +#endif /* User Board - Define your own board here. */ //#include "./board/user/r_bsp.h" diff --git a/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx140/r_gpio_rx140.c b/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx140/r_gpio_rx140.c new file mode 100644 index 00000000..5eaf35bc --- /dev/null +++ b/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx140/r_gpio_rx140.c @@ -0,0 +1,124 @@ +/*********************************************************************************************************************** +* Copyright (c) 2021 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx140.c +* Description : Data for r_gpio_rx driver specific to RX140. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.04.2021 1.00 First Release +* : 15.03.2025 5.11 Updated disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" + +#if defined(BSP_MCU_RX140) + +/* Public interface header file for this package. */ +#include "r_gpio_rx_if.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* These arrays hold which pins have extra functionality. For example, not all pins have the option of enabling + * open-drain N-channel output instead of the default CMOS output. Each entry in the array corresponds to a port. + * Each bit in each entry corresponds to a pin on that port. If bit 3 of array entry [4] was set to 1 then that would + * mean that PORT 4 PIN 3 supported the feature that array represented. + * + * These arrays are only used when GPIO_CFG_PARAM_CHECKING_ENABLE is set to 1 (checking enabled). If you know that + * your code does not need to check the pins then you can set this macro to 0 and save a little execution time + * and ROM space. + * + * Note: These arrays are defined for the largest package part. For smaller packages where some pins do not exist, + * pin checking is filtered by the enumerated port_pin list for that package as defined in r_gpio_rx23e-a.h. + */ + +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) +const uint8_t g_gpio_open_drain_n_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, //PORT0 None + 0xFC, //PORT1 P12 to P17 + 0xC3, //PORT2 P20, P21, P26, P27 + 0xD7, //PORT3 P30 to P32, P34, P36, P37 + 0x00, //PORT4 None + 0x00, //PORT5 None + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0x7F, //PORTA PA0 to PA6 + 0xFF, //PORTB PB0 to PB7 + 0xFC, //PORTC PC2 to PC7 + 0x07, //PORTD PD0 to PD2 + 0x0F, //PORTE PE0 to PE3 + 0x00, //PORTF None + 0x80, //PORTG PG7 + 0x00, //PORTH None + 0x00, //PORTJ None +}; + +const uint8_t g_gpio_open_drain_p_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, //PORT0 None + 0x00, //PORT1 None + 0x00, //PORT2 None + 0x00, //PORT3 None + 0x00, //PORT4 None + 0x00, //PORT5 None + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0x00, //PORTA None + 0x00, //PORTB None + 0x00, //PORTC None + 0x00, //PORTD None + 0x02, //PORTE PE1 + 0x00, //PORTF None + 0x00, //PORTG None + 0x00, //PORTH None + 0x00, //PORTJ None +}; + +const uint8_t g_gpio_pull_up_support[GPIO_INFO_NUM_PORTS] = +{ + 0xF8, //PORT0 P03 to P07 + 0xFC, //PORT1 P12 to P17 + 0xC3, //PORT2 P20, P21, P26, P27 + 0xD7, //PORT3 P30 to P32, P34, P36, P37 + 0xFF, //PORT4 P40 to P47 + 0x30, //PORT5 P54, P55 + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0x7F, //PORTA PA0 to PA6 + 0xFF, //PORTB PB0 to PB7 + 0xFC, //PORTC PC2 to PC7 + 0x07, //PORTD PD0 to PD2 + 0x3F, //PORTE PE0 to PE5 + 0x00, //PORTF None + 0x80, //PORTG PG7 + 0x0F, //PORTH PH0 to PH3 + 0xC2, //PORTJ PJ1, PJ6, PJ7 +}; + +#endif /* GPIO_CFG_PARAM_CHECKING_ENABLE */ + +#endif /* BSP_MCU_RX140 */ + diff --git a/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx140/r_gpio_rx140.h b/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx140/r_gpio_rx140.h new file mode 100644 index 00000000..7c48cd1d --- /dev/null +++ b/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx140/r_gpio_rx140.h @@ -0,0 +1,442 @@ +/*********************************************************************************************************************** +* Copyright (c) 2021 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx140.h +* Description : Specifics for the r_gpio_rx driver for the RX140. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.04.2021 1.00 First Release +* : 11.11.2021 2.00 Added support PH6 and PH7. +* : 15.03.2025 5.11 Updated disclaimer. +***********************************************************************************************************************/ +#ifndef GPIO_RX140 +#define GPIO_RX140 + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +#if defined(BSP_MCU_RX140) /* Prevents the compiler from finding multiple definitions of constant in this file. */ + +/* Configuration for this package. */ +#include "r_gpio_rx_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* General information about number of ports and pins on this device. */ +#define GPIO_INFO_NUM_PORTS (19) + +#if (BSP_PACKAGE_PINS == 80) + #define GPIO_INFO_NUM_PINS (72) /* The number of the multiplexed pin functions with PB is not included */ +#elif (BSP_PACKAGE_PINS == 64) + #define GPIO_INFO_NUM_PINS (56) /* The number of the multiplexed pin functions with PB is not included */ +#elif (BSP_PACKAGE_PINS == 48) + #define GPIO_INFO_NUM_PINS (40) /* The number of the multiplexed pin functions with PB is not included */ +#elif (BSP_PACKAGE_PINS == 32) + #define GPIO_INFO_NUM_PINS (24) +#else + #error "r_gpio_rx does not have information about this RX140 package. Please update r_gpio_rx140.h" +#endif + +/* Base registers used for offsets on output data registers. */ +#define GPIO_PRV_BASE_ADDR_OUTPUT (((uint8_t volatile *)&PORT0.PODR.BYTE)) +/* Base registers used for offsets on input data registers. */ +#define GPIO_PRV_BASE_ADDR_INPUT (((uint8_t volatile *)&PORT0.PIDR.BYTE)) +/* Base registers used for offsets on direction registers. */ +#define GPIO_PRV_BASE_ADDR_DIRECTION (((uint8_t volatile *)&PORT0.PDR.BYTE)) +/* Base registers used for offsets on mode registers. */ +#define GPIO_PRV_BASE_ADDR_MODE (((uint8_t volatile *)&PORT0.PMR.BYTE)) +/* Base registers used for offsets on output type registers. */ +#define GPIO_PRV_BASE_ADDR_OUT_TYPE (((uint8_t volatile *)&PORT1.ODR0.BYTE) - 2) +/* Base registers used for offsets on pull-up registers. */ +#define GPIO_PRV_BASE_ADDR_PULL_UP (((uint8_t volatile *)&PORT0.PCR.BYTE)) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if (BSP_PACKAGE_PINS == 80) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_G = 0x1000, + GPIO_PORT_H = 0x1100, + GPIO_PORT_J = 0x1200, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xF8, /* Available pins: P03 to P07 */ + GPIO_PORT1_PIN_MASK = 0xFC, /* Available pins: P12 to P17 */ + GPIO_PORT2_PIN_MASK = 0xC3, /* Available pins: P20, P21, P26, P27 */ + GPIO_PORT3_PIN_MASK = 0xF7, /* Available pins: P30 to P32, P34 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x30, /* Available pins: P54, P55 */ + GPIO_PORTA_PIN_MASK = 0x7F, /* Available pins: PA0 to PA6 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFC, /* Available pins: PC2 to PC7 */ + GPIO_PORTD_PIN_MASK = 0x07, /* Available pins: PD0 to PD2 */ + GPIO_PORTE_PIN_MASK = 0x3F, /* Available pins: PE0 to PE5 */ + GPIO_PORTG_PIN_MASK = 0x80, /* Available pins: PG7 */ +#if (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 0) + /* Stop Oscillating the Sub Clock */ + GPIO_PORTH_PIN_MASK = 0xCF, /* Available pins: PH0 to PH3, PH6, PH7 */ +#else + /* Enable Oscillating the Sub Clock */ + GPIO_PORTH_PIN_MASK = 0x0F, /* Available pins: PH0 to PH3 */ +#endif + GPIO_PORTJ_PIN_MASK = 0xC2, /* Available pins: PJ1, PJ6, PJ7 */ +} gpio_pin_bit_mask_t; + +/* This enumerator has each available GPIO pin on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_4 = 0x0004, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_6 = 0x0006, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_G_PIN_7 = 0x1007, + GPIO_PORT_H_PIN_0 = 0x1100, + GPIO_PORT_H_PIN_1 = 0x1101, + GPIO_PORT_H_PIN_2 = 0x1102, + GPIO_PORT_H_PIN_3 = 0x1103, +#if (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 0) + /* Stop Oscillating the Sub Clock */ + GPIO_PORT_H_PIN_6 = 0x1106, + GPIO_PORT_H_PIN_7 = 0x1107, +#endif + GPIO_PORT_J_PIN_1 = 0x1201, + GPIO_PORT_J_PIN_6 = 0x1206, + GPIO_PORT_J_PIN_7 = 0x1207, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 64) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_G = 0x1000, + GPIO_PORT_H = 0x1100, + GPIO_PORT_J = 0x1200, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0x28, /* Available pins: P03, P05 */ + GPIO_PORT1_PIN_MASK = 0xF0, /* Available pins: P14 to P17 */ + GPIO_PORT2_PIN_MASK = 0xC0, /* Available pins: P26, P27 */ + GPIO_PORT3_PIN_MASK = 0xE7, /* Available pins: P30 to P32, P35 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x30, /* Available pins: P54, P55 */ + GPIO_PORTA_PIN_MASK = 0x5B, /* Available pins: PA0, PA1, PA3, PA4, PA6 */ + GPIO_PORTB_PIN_MASK = 0xEB, /* Available pins: PB0, PB1, PB3, PB5 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFC, /* Available pins: PC2 to PC7 */ + GPIO_PORTE_PIN_MASK = 0x3F, /* Available pins: PE0 to PE5 */ + GPIO_PORTG_PIN_MASK = 0x80, /* Available pins: PG7 */ +#if ((BSP_CFG_MCU_PART_MEMORY_SIZE != 0x3) && (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 0)) + /* ROM capacity other than 64KB and stop Oscillating the Sub Clock */ + GPIO_PORTH_PIN_MASK = 0xCF, /* Available pins: PH0 to PH3, PH6, PH7 */ +#else + /* ROM capacity of 64KB or enable Oscillating the Sub Clock */ + GPIO_PORTH_PIN_MASK = 0x0F, /* Available pins: PH0 to PH3 */ +#endif + GPIO_PORTJ_PIN_MASK = 0xC0, /* Available pins: PJ6, PJ7 */ +} gpio_pin_bit_mask_t; + +/* This enumerator has each available GPIO pin on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_G_PIN_7 = 0x1007, + GPIO_PORT_H_PIN_0 = 0x1100, + GPIO_PORT_H_PIN_1 = 0x1101, + GPIO_PORT_H_PIN_2 = 0x1102, + GPIO_PORT_H_PIN_3 = 0x1103, +#if ((BSP_CFG_MCU_PART_MEMORY_SIZE != 0x3) && (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 0)) + /* ROM capacity other than 64KB and stop Oscillating the Sub Clock */ + GPIO_PORT_H_PIN_6 = 0x1106, + GPIO_PORT_H_PIN_7 = 0x1107, +#endif + GPIO_PORT_J_PIN_6 = 0x1206, + GPIO_PORT_J_PIN_7 = 0x1207, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 48) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_G = 0x1000, + GPIO_PORT_H = 0x1100, + GPIO_PORT_J = 0x1200, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT1_PIN_MASK = 0xF0, /* Available pins: P14 to P17 */ + GPIO_PORT2_PIN_MASK = 0xC0, /* Available pins: P26, P27 */ + GPIO_PORT3_PIN_MASK = 0xE3, /* Available pins: P30, P31, P35 to P37 */ + GPIO_PORT4_PIN_MASK = 0xE7, /* Available pins: P40 to P42, P45 to P47 */ + GPIO_PORTA_PIN_MASK = 0x5A, /* Available pins: PA1, PA3, PA4, PA6 */ + GPIO_PORTB_PIN_MASK = 0x2B, /* Available pins: PB0, PB1, PB3, PB5 */ + GPIO_PORTC_PIN_MASK = 0xF0, /* Available pins: PC4 to PC7 */ + GPIO_PORTE_PIN_MASK = 0x1E, /* Available pins: PE1 to PE4 */ + GPIO_PORTG_PIN_MASK = 0x80, /* Available pins: PG7 */ + GPIO_PORTH_PIN_MASK = 0x0F, /* Available pins: PH0 to PH3 */ + GPIO_PORTJ_PIN_MASK = 0xC0, /* Available pins: PJ6, PJ7 */ +} gpio_pin_bit_mask_t; + +/* This enumerator has each available GPIO pin on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_G_PIN_7 = 0x1007, + GPIO_PORT_H_PIN_0 = 0x1100, + GPIO_PORT_H_PIN_1 = 0x1101, + GPIO_PORT_H_PIN_2 = 0x1102, + GPIO_PORT_H_PIN_3 = 0x1103, + GPIO_PORT_J_PIN_6 = 0x1206, + GPIO_PORT_J_PIN_7 = 0x1207, +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 32) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_G = 0x1000, +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT1_PIN_MASK = 0xC0, /* Available pins: P16, P17 */ + GPIO_PORT2_PIN_MASK = 0xC0, /* Available pins: P26, P27 */ + GPIO_PORT3_PIN_MASK = 0x63, /* Available pins: P30, P31, P35, P36 */ + GPIO_PORT4_PIN_MASK = 0x07, /* Available pins: P40 to P42 */ + GPIO_PORTA_PIN_MASK = 0x1A, /* Available pins: PA1, PA3, PA4 */ + GPIO_PORTB_PIN_MASK = 0x01, /* Available pins: PB0 */ + GPIO_PORTC_PIN_MASK = 0xF0, /* Available pins: PC4 to PC7 */ + GPIO_PORTE_PIN_MASK = 0x1E, /* Available pins: PE1 to PE4 */ + GPIO_PORTG_PIN_MASK = 0x80, /* Available pins: PG7 */ +} gpio_pin_bit_mask_t; + +/* This enumerator has each available GPIO pin on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_G_PIN_7 = 0x1007, + +} gpio_port_pin_t; +#endif /* BSP_PACKAGE_PINS */ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* BSP_MCU_RX140 */ +#endif /* GPIO_RX140 */ diff --git a/drivers/rx/rdp/src/r_sci_rx/src/targets/rx140/r_sci_rx140.c b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx140/r_sci_rx140.c new file mode 100644 index 00000000..6aa77ffe --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx140/r_sci_rx140.c @@ -0,0 +1,1470 @@ +/*********************************************************************************************************************** +* Copyright (c) 2021 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx140.c +* Description : Functions for using SCI on the RX140 device. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 15.04.2021 1.00 Initial Release. +* 29.12.2021 1.10 Updated condition of loop in "sci_init_bit_rate()" function +* 27.12.2022 4.60 Updated macro definition enable and disable nested interrupt for TXI, RXI, ERI, TEI. +* 16.02.2023 4.70 Fixed a bug that return wrong value in sci_init_bit_rate() function. +* 28.06.2024 5.30 Corrected the typecasting formula in sci_init_bit_rate(). +* 01.11.2024 5.40 Fixed the issue that data cannot be sent when using the SCI_CMD_TX_Q_FLUSH command +* with the R_SCI_Control() function before executing the R_SCI_Send() function. +* 15.03.2025 5.41 Updated disclaimer +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +#include "r_sci_rx140_private.h" + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions + +******************************************************************************/ + +#if SCI_CFG_CH1_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_txi1_isr, VECT(SCI1,TXI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_txi1_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_rxi1_isr, VECT(SCI1,RXI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_rxi1_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_tei1_isr, VECT(SCI1,TEI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_tei1_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_eri1_isr, VECT(SCI1,ERI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_eri1_isr(void); + +#endif + +#if SCI_CFG_CH5_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_txi5_isr, VECT(SCI5,TXI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_txi5_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_rxi5_isr, VECT(SCI5,RXI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_rxi5_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_tei5_isr, VECT(SCI5,TEI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_tei5_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_eri5_isr, VECT(SCI5,ERI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_eri5_isr(void); + +#endif + +#if SCI_CFG_CH6_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_txi6_isr, VECT(SCI6,TXI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_txi6_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_rxi6_isr, VECT(SCI6,RXI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_rxi6_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_tei6_isr, VECT(SCI6,TEI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_tei6_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_eri6_isr, VECT(SCI6,ERI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_eri6_isr(void); +#endif + +#if SCI_CFG_CH8_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_txi8_isr, VECT(SCI8,TXI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_txi8_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_rxi8_isr, VECT(SCI8,RXI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_rxi8_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_tei8_isr, VECT(SCI8,TEI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_tei8_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_eri8_isr, VECT(SCI8,ERI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_eri8_isr(void); +#endif + +#if SCI_CFG_CH9_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_txi9_isr, VECT(SCI9,TXI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_txi9_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_rxi9_isr, VECT(SCI9,RXI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_rxi9_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_tei9_isr, VECT(SCI9,TEI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_tei9_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_eri9_isr, VECT(SCI9,ERI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_eri9_isr(void); +#endif + +#if SCI_CFG_CH12_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_txi12_isr, VECT(SCI12,TXI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_txi12_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_rxi12_isr, VECT(SCI12,RXI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_rxi12_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_tei12_isr, VECT(SCI12,TEI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_tei12_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_eri12_isr, VECT(SCI12,ERI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_eri12_isr(void); + +#endif + +/***************************************************************************** +* Function Name: sci_mcu_param_check +* Description : This function parameters check on MCU. +* (channel range, interrupt priority, etc...) +* Arguments : chan - +* channel to check +* Return Value : SCI_SUCCESS - +* parameter check all successfully +* SCI_ERR_BAD_CHAN - +* channel number invalid for part +* SCI_ERR_INVALID_ARG - +* interrupt priority out of range +******************************************************************************/ +sci_err_t sci_mcu_param_check(uint8_t const chan) +{ + /* channel range parameter check */ + if ((SCI_CH1 != chan) && (SCI_CH5 != chan) + && (SCI_CH6 != chan) && (SCI_CH8 != chan) + && (SCI_CH9 != chan) && (SCI_CH12 != chan)) + { + return SCI_ERR_BAD_CHAN; + } + + return SCI_SUCCESS; +} /* End of function sci_mcu_param_check() */ + +/***************************************************************************** +* Function Name: sci_init_register +* Description : This function initializes the register for SCI. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void sci_init_register(sci_hdl_t const hdl) +{ + /* SCI transmit enable bit and receive enable bit check & disable */ + /* WAIT_LOOP */ + while ((0 != hdl->rom->regs->SCR.BIT.TE) || (0 != hdl->rom->regs->SCR.BIT.RE)) + { + if (0 != hdl->rom->regs->SCR.BIT.TE) + { + hdl->rom->regs->SCR.BIT.TE = 0; // transmit disable + } + + if (0 != hdl->rom->regs->SCR.BIT.RE) + { + hdl->rom->regs->SCR.BIT.RE = 0; // receive disable + } + } + + /* SMR register initialize */ + hdl->rom->regs->SMR.BYTE = 0x00; + + /* SCR register initialize */ + hdl->rom->regs->SCR.BYTE = 0x00; + + /* SSR register initialize */ + if (1 == SCI_SSR_ORER) + { + SCI_SSR_ORER = 0; + } + + if (1 == SCI_SSR_PER) + { + SCI_SSR_PER = 0; + } + + if (1 == SCI_SSR_FER) + { + SCI_SSR_FER = 0; + } + + /* SCMR register initialize */ + hdl->rom->regs->SCMR.BIT.SMIF = 0; + hdl->rom->regs->SCMR.BIT.SINV = 0; + hdl->rom->regs->SCMR.BIT.SDIR = 0; + + + /* SPTR register initialize */ + hdl->rom->regs->SPTR.BIT.SPB2DT = 0; + hdl->rom->regs->SPTR.BIT.SPB2IO = 0; + hdl->rom->regs->SPTR.BIT.RTADJ = 0; + hdl->rom->regs->SPTR.BIT.TTADJ = 0; + hdl->rom->regs->SPTR.BIT.RINV = 0; + hdl->rom->regs->SPTR.BIT.TINV = 0; + + /* TMGR register initialize */ + hdl->rom->regs->TMGR.BIT.RTMG = 0; + hdl->rom->regs->TMGR.BIT.TTMG = 0; + + + /* BRR register initialize */ + hdl->rom->regs->BRR = 0xFF; + + /* SEMR register initialize */ + hdl->rom->regs->SEMR.BIT.BRME = 0; + hdl->rom->regs->SEMR.BIT.ABCS = 0; + hdl->rom->regs->SEMR.BIT.ABCSE = 0; + hdl->rom->regs->SEMR.BIT.NFEN = 0; + hdl->rom->regs->SEMR.BIT.BGDM = 0; + hdl->rom->regs->SEMR.BIT.RXDESEL = 0; + + /* SNFR register initialize */ + hdl->rom->regs->SNFR.BYTE = 0; + + /* SPMR register initialize */ + hdl->rom->regs->SPMR.BIT.CTSE = 0; + hdl->rom->regs->SPMR.BIT.CKPOL = 0; + hdl->rom->regs->SPMR.BIT.CKPH = 0; + +#if SCI_CFG_DATA_MATCH_INCLUDED + /* DCCR register initialize */ + hdl->rom->regs->DCCR.BIT.DCME = 0; + hdl->rom->regs->DCCR.BIT.DCMF = 0; + hdl->rom->regs->DCCR.BIT.DFER = 0; + hdl->rom->regs->DCCR.BIT.DPER = 0; + hdl->rom->regs->DCCR.BIT.IDSEL = 0; + + /* CDR register initialize */ + hdl->rom->regs->CDR.BYTE.L = 0; + + /* Set initial value of receive in 8-bit data length */ + hdl->rom->regs->SMR.BIT.CHR = 0; + hdl->rom->regs->SCMR.BIT.CHR1 = 1; +#endif + + return; +} /* End of function sci_init_register() */ + +/***************************************************************************** +* Function Name: sci_init_bit_rate +* Description : This function determines the best possible settings for the +* baud rate registers for the specified peripheral clock speed +* and baud rate. Note that this does not guarantee a low bit +* error rate, just the best possible one. The bit rate error is +* returned in .1% increments. If the hardware cannot support +* the specified combination, a value of 1000 (100% error) is +* returned. +* +* NOTE: The transmitter and receiver (TE and RE bits in SCR) must be disabled +* prior to calling this function. +* +* The application must pause for 1 bit time after the BRR register +* is loaded before transmitting/receiving to allow time for the clock +* to settle. +* +* Arguments : hdl - +* Handle for channel (ptr to chan control block) +* NOTE: mode element must be already set +* pclk - +* Peripheral clock speed; e.g. 24000000 for 24MHz +* baud - +* Baud rate; 19200, 57600, 115200, etc. +* Return Value : bit error in .1% increments; e.g. 16 = 1.6% bit rate error +* a value of 1000 denotes 100% error; no registers set +******************************************************************************/ +int32_t sci_init_bit_rate(sci_hdl_t const hdl, + uint32_t const pclk, + uint32_t const baud) +{ + uint32_t i; + uint32_t num_divisors = 0; + uint32_t ratio; + uint32_t tmp; + baud_divisor_t const *p_baud_info = NULL; + + uint32_t divisor; + uint32_t int_M; + float float_M; + float error; + float abs_error; + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if ((0 == pclk) || (0 == baud)) + { + return 1000; + } +#endif + + /* SELECT PROPER TABLE BASED UPON MODE */ + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + p_baud_info = async_baud; + num_divisors = NUM_DIVISORS_ASYNC; +#endif + } + else + { + /* SYNC or SSPI */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + p_baud_info = sync_baud; + num_divisors = NUM_DIVISORS_SYNC; +#endif + } + + /* FIND DIVISOR; table has associated ABCS, BGDM, ABCSE and CKS values */ + /* BRR must be 255 or less */ + /* the "- 1" is ignored in some steps for approximations */ + /* BRR = (PCLK/(divisor * baud)) - 1 */ + /* BRR = (ratio / divisor) - 1 */ + ratio = pclk/baud; + + /* WAIT_LOOP */ + for(i = 0; i < num_divisors; i++) + { + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* ABCSE bit is available on CH1, CH5 */ + /* Other channels skip divisor result have ABCSE bit*/ + if ((SCI_CH1 != hdl->rom->chan) && (SCI_CH5 != hdl->rom->chan)) + { + if(1 == p_baud_info[i].abcse) + { + continue; + } + } +#endif + } + /* Casting int16_t to uint32_t is valid. Because clock divisor is positive integer */ + if (ratio < (uint32_t)(p_baud_info[i].divisor * 256)) + { + break; + } + } + + /* RETURN IF BRR WILL BE >255 OR LESS THAN 0 */ + if (i == num_divisors) + { + return(1000); // impossible baud rate requested; return 100% error + } + + /* Casting int16_t to uint32_t is valid. Because clock divisor is a positive integer */ + divisor = (uint32_t)p_baud_info[i].divisor; + tmp = ratio/(divisor); // tmp = PCLK/(baud * divisor) = BRR+1 = N+1 + if(0 == tmp) + { + return(1000); // illegal value; return 100% error + } + + /* SET BRR, ABCS, BDGM, and CKS */ + tmp = ratio / (divisor/2); // divide by half the divisor + + /* if odd, "round up" by ignoring -1; divide by 2 again for rest of divisor */ + hdl->rom->regs->BRR = (uint8_t)((tmp & 0x01) ? (tmp/2) : ((tmp/2)-1)); + hdl->rom->regs->SEMR.BIT.ABCS = p_baud_info[i].abcs; + hdl->rom->regs->SEMR.BIT.BGDM = p_baud_info[i].bgdm; + hdl->rom->regs->SMR.BIT.CKS = p_baud_info[i].cks; + hdl->rom->regs->SEMR.BIT.ABCSE= p_baud_info[i].abcse; + + /* CALCULATE BIT RATE ERROR. + * RETURN IF ERROR LESS THAN 1% OR IF IN SYNCHRONOUS/SSPI MODE. + */ + tmp = ratio/(divisor); // tmp = PCLK/(baud * divisor) = BRR+1 = N+1 + + /* Casting uint32_t to float is valid */ + error = ( ((float)pclk / ((baud * divisor) * tmp)) - 1) * 100; + abs_error = (error < 0) ? (-error) : error; + + if ((abs_error <= 1.0f) || (SCI_MODE_ASYNC != hdl->mode)) + { + hdl->rom->regs->SEMR.BIT.BRME = 0; // disable MDDR + + /* Casting float to uint32_t */ + return (uint32_t)(error*10); + } + + /* CALCULATE M ASSUMING A 0% ERROR then WRITE REGISTER */ + hdl->rom->regs->BRR = (uint8_t)(tmp-1); + + /* Casting uint32_t to float is valid */ + float_M = ((((float)baud * divisor) * 256) * tmp) / pclk; + float_M *= 2; + + /* Casting float to uint32_t */ + int_M = (uint32_t)float_M; + int_M = (int_M & 0x01) ? ((int_M/2) + 1) : (int_M/2); + + /* Casting uint32_t type to uint8_t type in this case is valid. Range value of m is not exceed uint8_t */ + hdl->rom->regs->MDDR = (uint8_t)int_M; // write M + hdl->rom->regs->SEMR.BIT.BRME = 1; // enable MDDR + + /* Casting uint32_t to float is valid*/ + error = (( (float)(pclk) / (((divisor * tmp) * baud) * ((float)(256)/int_M)) ) - 1) * 100; + + /* Casting float to int32_t */ + return (int32_t)(error*10); +} /* End of function sci_init_bit_rate() */ + +/***************************************************************************** +* Function Name: sci_initialize_ints +* Description : This function sets priority, clears flags, and sets +* interrupts in both the ICU and SCI peripheral. These include +* RXI, TXI, TEI, and ERI/GROUP12 interrupts. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* priority - +* priority for interrupts +* Return Value : none +******************************************************************************/ +void sci_initialize_ints(sci_hdl_t const hdl, + uint8_t const priority) +{ + + /* SET PRIORITY FOR INTERRUPTS */ + *hdl->rom->ipr = priority; + + /* DISABLE ERI INTERRUPT */ + DISABLE_ERI_INT; + + /* DISABLE RXI INTERRUPT */ + DISABLE_RXI_INT; + + /* DISABLE TXI INTERRUPT */ + DISABLE_TXI_INT; + + /* DISABLE TEI INTERRUPT */ + DISABLE_TEI_INT; + + /* CLEAR INTERRUPT FLAGS */ + *hdl->rom->ir_rxi = 0; + *hdl->rom->ir_txi = 0; + *hdl->rom->ir_tei = 0; + *hdl->rom->ir_eri = 0; + + /* ENABLE ERI AND RXI INTERRUPTS REQUESTS */ + ENABLE_ERI_INT; + ENABLE_RXI_INT; + + /* ENABLE INTERRUPTS IN SCI PERIPHERAL */ + /* Note: Enable interrupts after xcvr or will get "extra" interrupt */ + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; // enable TE, RE, TXI, and RXI/ERI + + return; +} /* End of function sci_initialize_ints() */ + +/***************************************************************************** +* Function Name: sci_disable_ints +* Description : This function disable interrupts in both the ICU and SCI +* peripheral. These include RXI, TXI, TEI, ERI, and group +* interrupts. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void sci_disable_ints(sci_hdl_t const hdl) +{ + /* disable ICU RXI interrupts */ + DISABLE_RXI_INT; + + /* Disable ICU TXI interrupt */ + DISABLE_TXI_INT; + + /* Disable ICU ERI interrupt */ + DISABLE_ERI_INT; + + /* Disable ICU TEI interrupt */ + DISABLE_TEI_INT; + + /* disable peripheral interrupts and xcvr (TE and RE) */ + hdl->rom->regs->SCR.BYTE = 0; + + return; +} /* End of function sci_disable_ints() */ + +/***************************************************************************** +ISRs +******************************************************************************/ + + +#if ((SCI_CFG_ASYNC_INCLUDED) || (TX_DTC_DMACA_ENABLE | RX_DTC_DMACA_ENABLE)) + +/***************************************************************************** +* sciN_txiN_isr +* Description : TXI interrupt routines for every SCI channel +******************************************************************************/ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_txi1_isr + * Description : TXI interrupt routines for SCI1 channel + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_txi1_isr(void) +{ +#if SCI_CFG_CH1_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch1_ctrl); +} /* End of function sci1_txi1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED  */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_txi5_isr + * Description : TXI interrupt routines for SCI5 channel + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_txi5_isr(void) +{ +#if SCI_CFG_CH5_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch5_ctrl); +} /* End of function sci5_txi5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED  */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_txi6_isr + * Description : TXI interrupt routines for SCI6 channel + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_txi6_isr(void) +{ +#if SCI_CFG_CH6_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch6_ctrl); +} /* End of function sci6_txi6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED  */ + +#if SCI_CFG_CH8_INCLUDED +/******************************************************************************* + * Function Name: sci8_txi8_isr + * Description : TXI interrupt routines for SCI8 channel + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_txi8_isr(void) +{ +#if SCI_CFG_CH8_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch8_ctrl); +} /* End of function sci8_txi8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED  */ + +#if SCI_CFG_CH9_INCLUDED +/******************************************************************************* + * Function Name: sci9_txi9_isr + * Description : TXI interrupt routines for SCI9 channel + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_txi9_isr(void) +{ +#if SCI_CFG_CH9_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch9_ctrl); +} /* End of function sci9_txi9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED  */ + +#if SCI_CFG_CH12_INCLUDED +/******************************************************************************* + * Function Name: sci12_txi12_isr + * Description : TXI interrupt routines for SCI12 channel + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_txi12_isr(void) +{ +#if SCI_CFG_CH12_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch12_ctrl); +} /* End of function sci12_txi12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED  */ + +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if SCI_CFG_TEI_INCLUDED +/***************************************************************************** +* sciN_teiN_isr +* +* Description : TEI interrupt routines for every SCI channel. +* BSP gets main group interrupt, then vectors to/calls these +* "interrupts"/callbacks. +******************************************************************************/ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_tei1_isr + * Description : TEI interrupt routines for SCI1 channel. + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_tei1_isr(void) +{ +#if SCI_CFG_CH1_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch1_ctrl); +} /* End of function sci1_tei1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_tei5_isr + * Description : TEI interrupt routines for SCI5 channel. + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_tei5_isr(void) +{ +#if SCI_CFG_CH5_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch5_ctrl); +} /* End of function sci5_tei5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_tei6_isr + * Description : TEI interrupt routines for SCI6 channel. + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_tei6_isr(void) +{ +#if SCI_CFG_CH6_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch6_ctrl); +} /* End of function sci6_tei6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH8_INCLUDED +/***************************************************************************** +* Function Name: sci8_tei8_isr +* Description : TEI interrupt routines for SCI8 channel. +******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_tei8_isr(void) +{ +#if SCI_CFG_CH8_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch8_ctrl); +} /* End of function sci8_tei8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED */ + + +#if SCI_CFG_CH9_INCLUDED +/***************************************************************************** +* Function name: sci9_tei9_isr +* Description : TEI interrupt routines for SCI9 channel. +******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_tei9_isr(void) +{ +#if SCI_CFG_CH9_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch9_ctrl); +} /* End of function sci9_tei9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/***************************************************************************** +* Function Name: sci12_tei12_isr +* Description : TEI interrupt routines for SCI12 channel. +******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_tei12_isr(void) +{ +#if SCI_CFG_CH12_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch12_ctrl); +} /* End of function sci12_tei12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ + +#endif /* SCI_CFG_TEI_INCLUDED */ + +/***************************************************************************** +* sciN_rxiN_isr +* Description : RXI interrupt routines for every SCI channel +******************************************************************************/ + +#if SCI_CFG_CH1_INCLUDED +/******************************************************************************* + * Function Name: sci1_rxi1_isr + * Description : RXI interrupt routines for SCI1 channel + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_rxi1_isr(void) +{ +#if SCI_CFG_CH1_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch1_ctrl); +} /* End of function sci1_rxi1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/******************************************************************************* + * Function Name: sci5_rxi5_isr + * Description : RXI interrupt routines for SCI5 channel + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_rxi5_isr(void) +{ +#if SCI_CFG_CH5_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch5_ctrl); +} /* End of function sci5_rxi5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/******************************************************************************* + * Function Name: sci6_rxi6_isr + * Description : RXI interrupt routines for SCI6 channel + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_rxi6_isr(void) +{ +#if SCI_CFG_CH6_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch6_ctrl); +} /* End of function sci6_rxi6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH8_INCLUDED +/******************************************************************************* + * Function Name: sci8_rxi8_isr + * Description : RXI interrupt routines for SCI8 channel + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_rxi8_isr(void) +{ +#if SCI_CFG_CH8_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch8_ctrl); +} /* End of function sci8_rxi8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED */ + +#if SCI_CFG_CH9_INCLUDED +/******************************************************************************* + * Function Name: sci9_rxi9_isr + * Description : RXI interrupt routines for SCI9 channel + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_rxi9_isr(void) +{ +#if SCI_CFG_CH9_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch9_ctrl); +} /* End of function sci9_rxi9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/******************************************************************************* + * Function Name: sci12_rxi12_isr + * Description : RXI interrupt routines for SCI12 channel + ******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_rxi12_isr(void) +{ +#if SCI_CFG_CH12_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch12_ctrl); +} /* End of function sci12_rxi12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ + +/***************************************************************************** +* sciN_eriN_isr +* +* Description : ERI interrupt routines for every SCI channel. +* BSP gets main group interrupt, then vectors to/calls these +* "interrupts"/callbacks. +******************************************************************************/ + +#if SCI_CFG_CH1_INCLUDED +/***************************************************************************** +* Function name: sci1_eri1_isr +* Description : ERI interrupt routines for SCI1 channel. +******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_eri1_isr(void) +{ +#if SCI_CFG_CH1_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch1_ctrl); +} /* End of function sci1_eri1_isr() */ +#endif /* End of SCI_CFG_CH1_INCLUDED */ + +#if SCI_CFG_CH5_INCLUDED +/***************************************************************************** +* Function name: sci5_eri5_isr +* Description : ERI interrupt routines for SCI5 channel. +******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_eri5_isr(void) +{ +#if SCI_CFG_CH5_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch5_ctrl); +} /* End of function sci5_eri5_isr() */ +#endif /* End of SCI_CFG_CH5_INCLUDED */ + +#if SCI_CFG_CH6_INCLUDED +/***************************************************************************** +* Function name: sci6_eri6_isr +* Description : ERI interrupt routines for SCI6 channel. +******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_eri6_isr(void) +{ +#if SCI_CFG_CH6_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch6_ctrl); +} /* End of function sci6_eri6_isr() */ +#endif /* End of SCI_CFG_CH6_INCLUDED */ + +#if SCI_CFG_CH8_INCLUDED +/***************************************************************************** +* Function name: sci8_eri8_isr +* Description : ERI interrupt routines for SCI8 channel. +******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_eri8_isr(void) +{ +#if SCI_CFG_CH8_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch8_ctrl); +} /* End of function sci8_eri8_isr() */ +#endif /* End of SCI_CFG_CH8_INCLUDED */ + +#if SCI_CFG_CH9_INCLUDED +/***************************************************************************** +* Function name: sci9_eri9_isr +* Description : ERI interrupt routines for SCI9 channel. +******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_eri9_isr(void) +{ +#if SCI_CFG_CH9_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch9_ctrl); +} /* End of function sci9_eri9_isr() */ +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED +/***************************************************************************** +* Function name: sci12_eri12_isr +* Description : ERI interrupt routines for SCI12 channel. +******************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_eri12_isr(void) +{ +#if SCI_CFG_CH12_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch12_ctrl); +} /* End of function sci12_eri12_isr() */ +#endif /* End of SCI_CFG_CH12_INCLUDED */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_async_cmds +* Description : This function configures non-standard UART hardware and +* performs special software operations. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* cmd - +* command to run +* p_args - +* pointer argument(s) specific to command +* Return Value : SCI_SUCCESS - +* Command completed successfully. +* SCI_ERR_NULL_PTR - +* p_args is NULL when required for cmd +* SCI_ERR_INVALID_ARG - +* The cmd value or p_args contains an invalid value. +******************************************************************************/ +sci_err_t sci_async_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_err_t err=SCI_SUCCESS; + int32_t bit_err; + uint32_t slow_baud; + +#if SCI_CFG_PARAM_CHECKING_ENABLE + + /* Check parameters */ + if (((NULL == p_args) || (FIT_NO_PTR == p_args)) + && ((SCI_CMD_TX_Q_BYTES_FREE == cmd) || (SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ == cmd)|| (SCI_CMD_COMPARE_RECEIVED_DATA == cmd))) + { + return SCI_ERR_NULL_PTR; + } + +#endif + + switch(cmd) + { + case (SCI_CMD_EN_NOISE_CANCEL): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SEMR.BIT.NFEN = 1; /* enable noise filter */ + hdl->rom->regs->SNFR.BYTE = 0; /* clock divided by 1 (default) */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_OUTPUT_BAUD_CLK): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCR.BIT.CKE = 0x01; /* output baud clock on SCK pin */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_START_BIT_EDGE): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SEMR.BIT.RXDESEL = 1; /* detect start bit on falling edge */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + #if SCI_CFG_TEI_INCLUDED + case (SCI_CMD_EN_TEI): /* SCI_CMD_EN_TEI is obsolete command, but it exists only for compatibility with older version. */ + { + break; + } + #endif + +#if TX_DTC_DMACA_ENABLE + case (SCI_CMD_CHECK_TX_DONE): + { + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable)) + { + if (false == hdl->tx_idle) + { + err = SCI_ERR_XCVR_BUSY; + } + } + break; + } +#endif + +#if RX_DTC_DMACA_ENABLE + case (SCI_CMD_CHECK_RX_DONE): + { + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + if (0 != hdl->queue[0].rx_cnt) + { + err = SCI_ERR_XCVR_BUSY; + } + } + break; + } +#endif + + case (SCI_CMD_TX_Q_FLUSH): + { +#if (SCI_CFG_USE_CIRCULAR_BUFFER == 1) + R_BYTEQ_Flush(hdl->u_tx_data.que); +#else + /* Disable TXI interrupt */ + DISABLE_TXI_INT; + R_BYTEQ_Flush(hdl->u_tx_data.que); + ENABLE_TXI_INT; + + /* Re-enable interrupts */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; +#endif + break; + } + + case (SCI_CMD_RX_Q_FLUSH): + { +#if (SCI_CFG_USE_CIRCULAR_BUFFER == 1) + R_BYTEQ_Flush(hdl->u_rx_data.que); +#else + /* Disable RXI interrupt */ + DISABLE_RXI_INT; + R_BYTEQ_Flush(hdl->u_rx_data.que); + ENABLE_RXI_INT; +#endif + break; + } + + case (SCI_CMD_TX_Q_BYTES_FREE): + { + /* Casting pointer void* to uint16_t* type is valid */ + R_BYTEQ_Unused(hdl->u_tx_data.que, (uint16_t *) p_args); + break; + } + + case (SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ): + { + /* Casting pointer void* type to uint16_t* type is valid */ + R_BYTEQ_Used(hdl->u_rx_data.que, (uint16_t *) p_args); + break; + } + + case (SCI_CMD_GENERATE_BREAK): + { + /* flush transmit queue */ + DISABLE_TXI_INT; + R_BYTEQ_Flush(hdl->u_tx_data.que); +#if(TX_DTC_DMACA_ENABLE) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable)) + { + sci_fifo_ctrl_t *p_tctrl = &hdl->queue[hdl->qindex_app_rx]; + p_tctrl->tx_cnt = 0; + p_tctrl->tx_fraction = 0; +#if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + if(SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + dtc_cmd_arg_t args_dtc; + args_dtc.act_src = hdl->rom->dtc_tx_act_src; + R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &args_dtc); + + } +#endif +#if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + if(SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + dmaca_stat_t stat_dmaca; + R_DMACA_Control(hdl->rom->dmaca_tx_channel, DMACA_CMD_DISABLE, &stat_dmaca); + + } +#endif +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + } +#endif + } +#endif + + ENABLE_TXI_INT; + + /* NOTE: the following steps will abort anything being sent */ + + /* set baud rate 1.5x slower */ + slow_baud = (hdl->baud_rate << 1) / 3; + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, slow_baud); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; + } + else + { + /* transmit "0" and wait for completion */ + SCI_TDR(0); + + /* WAIT_LOOP */ + while (0 == hdl->rom->regs->SSR.BIT.TEND) + { + R_BSP_NOP(); + } + + /* restore original baud rate */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + sci_init_bit_rate(hdl, hdl->pclk_speed, hdl->baud_rate); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + break; + } + + #if SCI_CFG_DATA_MATCH_INCLUDED + case SCI_CMD_COMPARE_RECEIVED_DATA: + { + hdl->rom->regs->DCCR.BIT.DFER = 0; /* Clear Match Data Framing Error Flag */ + hdl->rom->regs->DCCR.BIT.DPER = 0; /* Clear Match Data Parity Error Flag */ + hdl->rom->regs->DCCR.BIT.DCME = 1; /* Enable Data match function */ + hdl->rom->regs->CDR.BYTE.L = *((unsigned char *)p_args); /* Comparison data */ + break; + } + #endif + + /* Enable receive data sampling timing adjust feature*/ + case SCI_CMD_RX_SAMPLING_ENABLE: + { + hdl->rom->regs->SPTR.BIT.RTADJ = 1; + break; + } + + /* Disable receive data sampling timing adjust feature*/ + case SCI_CMD_RX_SAMPLING_DISABLE: + { + hdl->rom->regs->SPTR.BIT.RTADJ = 0; + break; + } + + /* Enable transmit signal transition timing adjust feature*/ + case SCI_CMD_TX_TRANSITION_TIMING_ENABLE: + { + hdl->rom->regs->SPTR.BIT.TTADJ = 1; + break; + } + + /* Disable transmit signal transition timing adjust feature*/ + case SCI_CMD_TX_TRANSITION_TIMING_DISABLE: + { + hdl->rom->regs->SPTR.BIT.TTADJ = 0; + break; + } + + /* Set value for receive data sampling timing adjust feature*/ + case SCI_CMD_SAMPLING_TIMING_ADJUST: + { + if ((0 == hdl->rom->regs->SEMR.BIT.ABCSE) && (0 == hdl->rom->regs->SEMR.BIT.ABCS)) + { + /* Casting pointer void* to uint8_t* type is valid */ + if ((*(uint8_t *)p_args) <= 15) + { + if (1 == hdl->rom->regs->SPTR.BIT.RTADJ) + { + /* Casting pointer void* to uint8_t* type is valid */ + hdl->rom->regs->TMGR.BIT.RTMG = *(uint8_t *)p_args; + } + } + else + { + err = SCI_ERR_INVALID_ARG; + } + } + else if ((0 == hdl->rom->regs->SEMR.BIT.ABCSE) && (1 == hdl->rom->regs->SEMR.BIT.ABCS)) + { + /* Casting pointer void* to uint8_t* type is valid */ + if (((*(uint8_t *)p_args) <= 3) || ((8 <= (*(uint8_t *)p_args)) && ((*(uint8_t *)p_args) <= 11))) + { + if (1 == hdl->rom->regs->SPTR.BIT.RTADJ) + { + /* Casting pointer void* to uint8_t* type is valid */ + hdl->rom->regs->TMGR.BIT.RTMG = *(uint8_t *)p_args; + } + } + else + { + err = SCI_ERR_INVALID_ARG; + } + } + else + { + /* Casting pointer void* to uint8_t* type is valid */ + if (((*(uint8_t *)p_args) <= 2) || ((8 <= (*(uint8_t *)p_args)) && ((*(uint8_t *)p_args) <= 10))) + { + if (1 == hdl->rom->regs->SPTR.BIT.RTADJ) + { + /* Casting pointer void* to uint8_t* type is valid */ + hdl->rom->regs->TMGR.BIT.RTMG = *(uint8_t *)p_args; + } + } + else + { + err = SCI_ERR_INVALID_ARG; + } + } + break; + } + /*Set va transmit signal transition timing adjust feature*/ + case SCI_CMD_TRANSITION_TIMING_ADJUST: + { + if (0 == hdl->rom->regs->SEMR.BIT.ABCSE) + { + /* Casting pointer void* to uint8_t* type is valid */ + if ((*(uint8_t *)p_args) <= 15) + { + if (1 == hdl->rom->regs->SPTR.BIT.TTADJ) + { + /* Casting pointer void* to uint8_t* type is valid */ + hdl->rom->regs->TMGR.BIT.TTMG = *(uint8_t *)p_args; + } + } + else + { + err = SCI_ERR_INVALID_ARG; + } + } + else + { + /* Casting pointer void* to uint8_t* type is valid */ + if (((*(uint8_t *)p_args) <= 5) || ((8 <= (*(uint8_t *)p_args)) && ((*(uint8_t *)p_args) <= 13))) + { + if (1 == hdl->rom->regs->SPTR.BIT.TTADJ) + { + /* Casting pointer void* to uint8_t* type is valid */ + hdl->rom->regs->TMGR.BIT.TTMG = *(uint8_t *)p_args; + } + } + else + { + err = SCI_ERR_INVALID_ARG; + } + } + + break; + } + default: + { + err = SCI_ERR_INVALID_ARG; + break; + } + } + + return err; +} /* End of function sci_async_cmds() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_sync_cmds +* Description : This function performs special software operations specific +* to the SSPI and SYNC protocols. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* cmd - +* command to run +* p_args - +* pointer argument(s) specific to command +* Return Value : SCI_SUCCESS - +* Command completed successfully. +* SCI_ERR_NULL_PTR - +* p_args is NULL when required for cmd +* SCI_ERR_INVALID_ARG - +* The cmd value or p_args contains an invalid value. +* May be due to mode channel is operating in. +******************************************************************************/ +sci_err_t sci_sync_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_spi_mode_t spi_mode; + sci_cb_args_t args; + sci_err_t err = SCI_SUCCESS; + + switch (cmd) + { + case (SCI_CMD_CHECK_XFER_DONE): + { + if (false == hdl->tx_idle) + { + err = SCI_ERR_XFER_NOT_DONE; + } + break; + } + + case (SCI_CMD_XFER_LSB_FIRST): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SDIR = 0; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_XFER_MSB_FIRST): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SDIR = 1; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_INVERT_DATA): + { + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SINV ^= 1; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + case (SCI_CMD_ABORT_XFER): + { + /* Disable receive interrupts in ICU and peripheral */ + DISABLE_RXI_INT; + DISABLE_ERI_INT; +#if(TX_DTC_DMACA_ENABLE) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable)) + { + sci_fifo_ctrl_t *p_tctrl = &hdl->queue[hdl->qindex_app_rx]; + p_tctrl->tx_cnt = 0; + p_tctrl->tx_fraction = 0; +#if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) && (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + // Set condition for reset TDFR to generate interrupt in next time + hdl->qindex_int_tx = 1; + dtc_cmd_arg_t args_dtc; + args_dtc.act_src = hdl->rom->dtc_tx_act_src; + R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &args_dtc); + + args_dtc.act_src = hdl->rom->dtc_rx_act_src; + R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &args_dtc); + } +#endif +#if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + if((SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) && (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + R_DMACA_Close(hdl->rom->dmaca_tx_channel); + R_DMACA_Close(hdl->rom->dmaca_rx_channel); + } +#endif + + } +#endif + hdl->rom->regs->SCR.BYTE &= (~(SCI_SCR_REI_MASK | SCI_SCR_RE_MASK | SCI_SCR_TE_MASK)); + + hdl->tx_cnt = 0; + hdl->tx_dummy = false; + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_ABORTED; + + /* Casting pointer to void* is valid */ + hdl->callback((void *)&args); + } + + *hdl->rom->ir_rxi = 0; /* clear rxi interrupt flag */ +#if SCI_CFG_FIFO_INCLUDED +#if(TX_DTC_DMACA_ENABLE) + if((SCI_DTC_DMACA_DISABLE != hdl->rom->dtc_dmaca_tx_enable) && (true != hdl->fifo_ctrl)) + { + *hdl->rom->ir_txi = 0; + } +#endif +#else +#if(TX_DTC_DMACA_ENABLE) + if((SCI_DTC_DMACA_DISABLE != hdl->rom->dtc_dmaca_tx_enable)) + { + *hdl->rom->ir_txi = 0; + } +#endif +#endif + *hdl->rom->ir_eri = 0; /* clear eri interrupt flag */ + + ENABLE_ERI_INT; /* enable rx err interrupts in ICU */ + ENABLE_RXI_INT; /* enable receive interrupts in ICU */ + + /* Enable receive interrupt in peripheral after rcvr or will get "extra" interrupt */ + hdl->rom->regs->SCR.BYTE |= (SCI_SCR_RE_MASK | SCI_SCR_TE_MASK); + hdl->rom->regs->SCR.BYTE |= SCI_SCR_REI_MASK; + break; + } +#if RX_DTC_DMACA_ENABLE + case (SCI_CMD_CHECK_RX_SYNC_DONE): + { + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + if (0 != hdl->queue[0].rx_cnt) + { + err = SCI_ERR_XCVR_BUSY; + } + } + break; + } +#endif + case (SCI_CMD_CHANGE_SPI_MODE): + { + #if SCI_CFG_PARAM_CHECKING_ENABLE + + if (SCI_MODE_SSPI != hdl->mode) + { + return SCI_ERR_INVALID_ARG; + } + + /* Check parameters */ + if ((NULL == p_args ) || (FIT_NO_PTR == p_args)) + { + return SCI_ERR_NULL_PTR; + } + + /* Casting pointer void* type is valid */ + spi_mode = *((sci_spi_mode_t *)p_args); + + if ((SCI_SPI_MODE_0 != spi_mode) && (SCI_SPI_MODE_1 != spi_mode) + && (SCI_SPI_MODE_2 != spi_mode) && (SCI_SPI_MODE_3 != spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + #endif + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SPMR.BYTE &= 0x3F; /* clear previous mode */ + hdl->rom->regs->SPMR.BYTE |= (*((uint8_t *)p_args)); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + } + + default: + { + err = SCI_ERR_INVALID_ARG; + break; + } + } + + return err; +} /* End of function sci_sync_cmds() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + + + diff --git a/drivers/rx/rdp/src/r_sci_rx/src/targets/rx140/r_sci_rx140_data.c b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx140/r_sci_rx140_data.c new file mode 100644 index 00000000..b8e96020 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx140/r_sci_rx140_data.c @@ -0,0 +1,406 @@ +/*********************************************************************************************************************** +* Copyright (c) 2021 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx140_data.c +* Description : Functions for using SCI on the RX140 device. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 15.04.2021 1.00 Initial Release. +* 29.12.2021 1.10 Updated ABCSE in "sync_baud" array. +* 31.03.2022 4.40 Added receive flag when using DTC/DMAC. +* 16.02.2023 4.70 Updated ABCSE in "sync_baud" array. +* 15.03.2025 5.41 Updated disclaimer +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +#include "r_sci_rx140_private.h" + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/* BAUD DIVISOR INFO */ + +/* Asynchronous */ +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* when abcs=0 & bgdm=0 & abcse =0, divisor = 64*pow(2,2n-1) */ +/* when abcs=1 & bgdm=0 & abcse =0 OR abcs=0 & bgdm=1 & abcse =0, divisor = 32*pow(2,2n-1) */ +/* when abcs=1 & bgdm=1 & abcse =0, divisor = 16*pow(2,2n-1) */ +/* when abcs=(1 or 0) & bgdm= (1 or 0) & abcse =1, divisor = 12*pow(2,2n-1). This case not available for SCI6,SCI8,SC9,SCI12 */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/* NOTE: diff than SCI async baud table, but should provide same results */ +const baud_divisor_t async_baud[NUM_DIVISORS_ASYNC]= +{ + /* divisor result, abcs, bgdm, abcse, n */ + {6, 1, 1, 1, 0}, + {8, 1, 1, 0, 0}, + {16, 0, 1, 0, 0}, + {24, 1, 1, 1, 1}, + {32, 0, 0, 0, 0}, + {64, 0, 1, 0, 1}, + {96, 1, 1, 1, 2}, + {128, 0, 0, 0, 1}, + {256, 0, 1, 0, 2}, + {384, 1, 1, 1, 3}, + {512, 0, 0, 0, 2}, + {1024, 0, 1, 0, 3}, + {2048, 0, 0, 0, 3} +}; +#endif + +/* Synchronous and Simple SPI */ +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* abcs=0, bdgm=0, divisor = 8*pow(2,2n-1) */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/* NOTE: Identical to SCI sync baud table */ +const baud_divisor_t sync_baud[NUM_DIVISORS_SYNC]= +{ + /* divisor result, abcs, bgdm, abcse, n */ + {4, 0, 0, 0, 0}, + {16, 0, 0, 0, 1}, + {64, 0, 0, 0, 2}, + {256, 0, 0, 0, 3} +}; +#endif + + +/* CHANNEL MEMORY ALLOCATIONS */ + +#if SCI_CFG_CH1_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch1_rom = {(volatile struct st_sci1 R_BSP_EVENACCESS_SFR *)&SCI1, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT30_MASK, + &ICU.IPR[IPR_SCI1_RXI1].BYTE, + &ICU.IR[IR_SCI1_RXI1].BYTE, + &ICU.IR[IR_SCI1_TXI1].BYTE, + &ICU.IR[IR_SCI1_TEI1].BYTE, + &ICU.IR[IR_SCI1_ERI1].BYTE, + &ICU.IER[IER_SCI1_RXI1].BYTE, + &ICU.IER[IER_SCI1_TXI1].BYTE, + &ICU.IER[IER_SCI1_TEI1].BYTE, + &ICU.IER[IER_SCI1_ERI1].BYTE, + SCI_BIT2, SCI_BIT3, SCI_BIT4, SCI_BIT5, + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + SCI_CFG_CH1_TX_DTC_DMACA_ENABLE, + SCI_CFG_CH1_RX_DTC_DMACA_ENABLE, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + DTCE_SCI1_TXI1, + DTCE_SCI1_RXI1, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + IR_SCI1_TXI1, + IR_SCI1_RXI1, + (uint8_t)SCI_CFG_CH1_TX_DMACA_CH_NUM, + (uint8_t)SCI_CFG_CH1_RX_DMACA_CH_NUM, + #endif + /* Casting to uint8_t type is valid */ + (uint8_t)SCI_CH1 + }; + +/* channel control block */ +sci_ch_ctrl_t ch1_ctrl = {&ch1_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif /* End of SCI_CFG_CH1_INCLUDED */ + + +#if SCI_CFG_CH5_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch5_rom = {(volatile struct st_sci1 R_BSP_EVENACCESS_SFR *)&SCI5, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT26_MASK, + &ICU.IPR[IPR_SCI5_RXI5].BYTE, + &ICU.IR[IR_SCI5_RXI5].BYTE, + &ICU.IR[IR_SCI5_TXI5].BYTE, + &ICU.IR[IR_SCI5_TEI5].BYTE, + &ICU.IR[IR_SCI5_ERI5].BYTE, + &ICU.IER[IER_SCI5_RXI5].BYTE, + &ICU.IER[IER_SCI5_TXI5].BYTE, + &ICU.IER[IER_SCI5_TEI5].BYTE, + &ICU.IER[IER_SCI5_ERI5].BYTE, + SCI_BIT6, SCI_BIT7, SCI_BIT0, SCI_BIT1, + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + SCI_CFG_CH5_TX_DTC_DMACA_ENABLE, + SCI_CFG_CH5_RX_DTC_DMACA_ENABLE, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + DTCE_SCI5_TXI5, + DTCE_SCI5_RXI5, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + IR_SCI5_TXI5, + IR_SCI5_RXI5, + (uint8_t)SCI_CFG_CH5_TX_DMACA_CH_NUM, + (uint8_t)SCI_CFG_CH5_RX_DMACA_CH_NUM, + #endif + /* Casting to uint8_t type is valid */ + (uint8_t)SCI_CH5 + }; + +/* channel control block */ +sci_ch_ctrl_t ch5_ctrl = {&ch5_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif /* End of SCI_CFG_CH5_INCLUDED */ + + +#if SCI_CFG_CH6_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch6_rom = {(volatile struct st_sci1 R_BSP_EVENACCESS_SFR *)&SCI6, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT25_MASK, + &ICU.IPR[IPR_SCI6_RXI6].BYTE, + &ICU.IR[IR_SCI6_RXI6].BYTE, + &ICU.IR[IR_SCI6_TXI6].BYTE, + &ICU.IR[IR_SCI6_TEI6].BYTE, + &ICU.IR[IR_SCI6_ERI6].BYTE, + &ICU.IER[IER_SCI6_RXI6].BYTE, + &ICU.IER[IER_SCI6_TXI6].BYTE, + &ICU.IER[IER_SCI6_TEI6].BYTE, + &ICU.IER[IER_SCI6_ERI6].BYTE, + SCI_BIT2, SCI_BIT3, SCI_BIT4, SCI_BIT5, + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + SCI_CFG_CH6_TX_DTC_DMACA_ENABLE, + SCI_CFG_CH6_RX_DTC_DMACA_ENABLE, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + DTCE_SCI6_TXI6, + DTCE_SCI6_RXI6, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + IR_SCI6_TXI6, + IR_SCI6_RXI6, + (uint8_t)SCI_CFG_CH6_TX_DMACA_CH_NUM, + (uint8_t)SCI_CFG_CH6_RX_DMACA_CH_NUM, + #endif + /* Casting to uint8_t type is valid */ + (uint8_t)SCI_CH6 + }; + +/* channel control block */ +sci_ch_ctrl_t ch6_ctrl = {&ch6_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif /* End of SCI_CFG_CH6_INCLUDED */ + + +#if SCI_CFG_CH8_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch8_rom = {(volatile struct st_sci1 R_BSP_EVENACCESS_SFR *)&SCI8, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT27_MASK, + &ICU.IPR[IPR_SCI8_RXI8].BYTE, + &ICU.IR[IR_SCI8_RXI8].BYTE, + &ICU.IR[IR_SCI8_TXI8].BYTE, + &ICU.IR[IR_SCI8_TEI8].BYTE, + &ICU.IR[IR_SCI8_ERI8].BYTE, + &ICU.IER[IER_SCI8_RXI8].BYTE, + &ICU.IER[IER_SCI8_TXI8].BYTE, + &ICU.IER[IER_SCI8_TEI8].BYTE, + &ICU.IER[IER_SCI8_ERI8].BYTE, + SCI_BIT6, SCI_BIT7, SCI_BIT0, SCI_BIT1, + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + SCI_CFG_CH8_TX_DTC_DMACA_ENABLE, + SCI_CFG_CH8_RX_DTC_DMACA_ENABLE, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + DTCE_SCI8_TXI8, + DTCE_SCI8_RXI8, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + IR_SCI8_TXI8, + IR_SCI8_RXI8, + (uint8_t)SCI_CFG_CH8_TX_DMACA_CH_NUM, + (uint8_t)SCI_CFG_CH8_RX_DMACA_CH_NUM, + #endif + /* Casting to uint8_t type is valid */ + (uint8_t)SCI_CH8 + }; + +/* channel control block */ +sci_ch_ctrl_t ch8_ctrl = {&ch8_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif /* End of SCI_CFG_CH8_INCLUDED */ + + +#if SCI_CFG_CH9_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch9_rom = {(volatile struct st_sci1 R_BSP_EVENACCESS_SFR *)&SCI9, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT26_MASK, + &ICU.IPR[IPR_SCI9_RXI9].BYTE, + &ICU.IR[IR_SCI9_RXI9].BYTE, + &ICU.IR[IR_SCI9_TXI9].BYTE, + &ICU.IR[IR_SCI9_TEI9].BYTE, + &ICU.IR[IR_SCI9_ERI9].BYTE, + &ICU.IER[IER_SCI9_RXI9].BYTE, + &ICU.IER[IER_SCI9_TXI9].BYTE, + &ICU.IER[IER_SCI9_TEI9].BYTE, + &ICU.IER[IER_SCI9_ERI9].BYTE, + SCI_BIT2, SCI_BIT3, SCI_BIT4, SCI_BIT5, + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + SCI_CFG_CH9_TX_DTC_DMACA_ENABLE, + SCI_CFG_CH9_RX_DTC_DMACA_ENABLE, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + DTCE_SCI9_TXI9, + DTCE_SCI9_RXI9, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + IR_SCI9_TXI9, + IR_SCI9_RXI9, + (uint8_t)SCI_CFG_CH9_TX_DMACA_CH_NUM, + (uint8_t)SCI_CFG_CH9_RX_DMACA_CH_NUM, + #endif + /* Casting to uint8_t type is valid */ + (uint8_t)SCI_CH9 + }; + +/* channel control block */ +sci_ch_ctrl_t ch9_ctrl = {&ch9_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif /* End of SCI_CFG_CH9_INCLUDED */ + +#if SCI_CFG_CH12_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch12_rom = {(volatile struct st_sci1 R_BSP_EVENACCESS_SFR *)&SCI12, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT4_MASK, + &ICU.IPR[IPR_SCI12_RXI12].BYTE, + &ICU.IR[IR_SCI12_RXI12].BYTE, + &ICU.IR[IR_SCI12_TXI12].BYTE, + &ICU.IR[IR_SCI12_TEI12].BYTE, + &ICU.IR[IR_SCI12_ERI12].BYTE, + &ICU.IER[IER_SCI12_RXI12].BYTE, + &ICU.IER[IER_SCI12_TXI12].BYTE, + &ICU.IER[IER_SCI12_TEI12].BYTE, + &ICU.IER[IER_SCI12_ERI12].BYTE, + SCI_BIT6, SCI_BIT7, SCI_BIT0, SCI_BIT1, + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + SCI_CFG_CH12_TX_DTC_DMACA_ENABLE, + SCI_CFG_CH12_RX_DTC_DMACA_ENABLE, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + DTCE_SCI12_TXI12, + DTCE_SCI12_RXI12, + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + IR_SCI12_TXI12, + IR_SCI12_RXI12, + (uint8_t)SCI_CFG_CH12_TX_DMACA_CH_NUM, + (uint8_t)SCI_CFG_CH12_RX_DMACA_CH_NUM, + #endif + /* Casting to uint8_t type is valid */ + (uint8_t)SCI_CH12 + }; + +/* channel control block */ +sci_ch_ctrl_t ch12_ctrl = {&ch12_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif /* End of SCI_CFG_CH12_INCLUDED */ + + +/* SCI HANDLE-ARRAY DECLARATION */ + +const sci_hdl_t g_handles[SCI_NUM_CH] = +{ + NULL, /* ch0 */ + +#if SCI_CFG_CH1_INCLUDED + &ch1_ctrl, +#else + NULL, +#endif + + NULL, /* ch2 */ + NULL, /* ch3 */ + NULL, /* ch4 */ + +#if SCI_CFG_CH5_INCLUDED + &ch5_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH6_INCLUDED + &ch6_ctrl, +#else + NULL, +#endif + NULL, +#if SCI_CFG_CH8_INCLUDED + &ch8_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH9_INCLUDED + &ch9_ctrl, +#else + NULL, +#endif + NULL, + NULL, +#if SCI_CFG_CH12_INCLUDED + &ch12_ctrl +#else + NULL +#endif +}; + diff --git a/drivers/rx/rdp/src/r_sci_rx/src/targets/rx140/r_sci_rx140_private.h b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx140/r_sci_rx140_private.h new file mode 100644 index 00000000..ca988c06 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx140/r_sci_rx140_private.h @@ -0,0 +1,269 @@ +/*********************************************************************************************************************** +* Copyright (c) 2021 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx140_private.h +* Description : Functions for using SCI on the RX140 device. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 15.04.2021 1.00 Initial Release. +* 31.03.2022 4.40 Added receive flag when using DTC/DMAC. +* 16.02.2023 4.70 Updated the macro NUM_DIVISORS_ASYNC. +* 15.03.2025 5.41 Updated disclaimer +***********************************************************************************************************************/ + +#ifndef SCI_RX140_H +#define SCI_RX140_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "../../r_sci_rx_private.h" + +#if (SCI_CFG_ASYNC_INCLUDED) +#include "r_byteq_if.h" +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* SCI channel include Check */ +#if (SCI_CFG_CH0_INCLUDED != 0) || (SCI_CFG_CH2_INCLUDED != 0) || \ + (SCI_CFG_CH3_INCLUDED != 0) || (SCI_CFG_CH4_INCLUDED != 0) || \ + (SCI_CFG_CH7_INCLUDED != 0) || (SCI_CFG_CH10_INCLUDED != 0) || \ + (SCI_CFG_CH11_INCLUDED != 0) + #error "ERROR - Unsupported channel chosen in r_sci_config.h" +#endif + +/* Mask of all active channels */ +#define SCI_CFG_CH_INCLUDED_MASK ((SCI_CFG_CH1_INCLUDED << 1) | \ + (SCI_CFG_CH5_INCLUDED << 5) | \ + (SCI_CFG_CH6_INCLUDED << 6) | \ + (SCI_CFG_CH8_INCLUDED << 8) | \ + (SCI_CFG_CH9_INCLUDED << 9) | \ + (SCI_CFG_CH12_INCLUDED << 12)) + +/* SCI SCR register masks */ +#define SCI_SCR_TEI_MASK (0x80U) /* transmit interrupt enable */ +#define SCI_SCR_REI_MASK (0x40U) /* receive interrupt enable */ +#define SCI_SCR_TE_MASK (0x20U) /* transmitter enable */ +#define SCI_SCR_RE_MASK (0x10U) /* receiver enable */ +#define SCI_EN_XCVR_MASK (SCI_SCR_RE_MASK | SCI_SCR_TE_MASK | SCI_SCR_REI_MASK | SCI_SCR_TEI_MASK) + +/* SCI SSR register receiver error masks */ +#define SCI_SSR_ORER_MASK (0x20U) /* overflow error */ +#define SCI_SSR_FER_MASK (0x10U) /* framing error */ +#define SCI_SSR_PER_MASK (0x08U) /* parity err */ +#define SCI_RCVR_ERR_MASK (SCI_SSR_ORER_MASK | SCI_SSR_FER_MASK | SCI_SSR_PER_MASK) +#define SCI_SSR_CLR_MASK (0xC0U) /* SSR register cleare mask (11000000b) */ + +/* Macros to enable and disable ICU interrupts */ +#define ENABLE_RXI_INT (R_BSP_BIT_SET(hdl->rom->icu_rxi, hdl->rom->rxi_bit_num)) +#define DISABLE_RXI_INT (R_BSP_BIT_CLEAR(hdl->rom->icu_rxi, hdl->rom->rxi_bit_num)) +#define ENABLE_TXI_INT (R_BSP_BIT_SET(hdl->rom->icu_txi, hdl->rom->txi_bit_num)) +#define DISABLE_TXI_INT (R_BSP_BIT_CLEAR(hdl->rom->icu_txi, hdl->rom->txi_bit_num)) + +#define ENABLE_ERI_INT (R_BSP_BIT_SET(hdl->rom->icu_eri, hdl->rom->eri_bit_num)) +#define DISABLE_ERI_INT (R_BSP_BIT_CLEAR(hdl->rom->icu_eri, hdl->rom->eri_bit_num)) +#define ENABLE_TEI_INT (R_BSP_BIT_SET(hdl->rom->icu_tei, hdl->rom->tei_bit_num)) +#define DISABLE_TEI_INT (R_BSP_BIT_CLEAR(hdl->rom->icu_tei, hdl->rom->tei_bit_num)) + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +typedef struct st_scif_fifo_ctrl +{ + uint8_t *p_tx_buf; /* user's buffer */ + uint8_t *p_rx_buf; /* user's buffer */ + uint16_t tx_cnt; /* bytes remaining to add to FIFO */ + uint16_t rx_cnt; /* bytes waiting to receive from FIFO */ +#if (TX_DTC_DMACA_ENABLE) || (RX_DTC_DMACA_ENABLE) + uint8_t *p_tx_fraction_buf; + uint8_t *p_rx_fraction_buf; + uint16_t tx_fraction; + uint16_t rx_fraction; +#endif + uint16_t total_length; /* used for DTC in txi_handler */ +} sci_fifo_ctrl_t; + +/* CHANNEL CONTROL BLOCK */ + +/* ROM INFO */ + +typedef struct st_sci_ch_rom /* SCI ROM info for channel control block */ +{ + volatile struct st_sci1 R_BSP_EVENACCESS_SFR *regs; /* base ptr to ch registers */ + volatile uint32_t R_BSP_EVENACCESS_SFR *mstp; /* ptr to mstp register */ + uint32_t stop_mask; /* mstp mask to disable ch */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ipr; /* ptr to IPR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_rxi; /* ptr to RXI IR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_txi; /* ptr to TXI IR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_tei; /* ptr to TEI IR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_eri; /* ptr to ERI IR register */ + + /* + * DO NOT use the enable/disable interrupt bits in the SCR + * register. Pending interrupts can be lost that way. + */ + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_rxi; /* ptr to ICU register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_txi; + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_tei; + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_eri; + uint8_t eri_bit_num; /* ICU enable/disable eri bit number */ + uint8_t rxi_bit_num; /* ICU enable/disable rxi bit number */ + uint8_t txi_bit_num; /* ICU enable/disable txi bit number */ + uint8_t tei_bit_num; /* ICU enable/disable tei bit number */ + /* + * In case using DTC/DMAC + */ +#if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + uint8_t dtc_dmaca_tx_enable; + uint8_t dtc_dmaca_rx_enable; +#endif +#if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + dtc_activation_source_t dtc_tx_act_src; + dtc_activation_source_t dtc_rx_act_src; +#endif +#if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) + dmaca_activation_source_t dmaca_tx_act_src; + dmaca_activation_source_t dmaca_rx_act_src; + uint8_t dmaca_tx_channel; + uint8_t dmaca_rx_channel; +#endif + uint8_t chan; /* Channel SCI is used*/ +} sci_ch_rom_t; + + +/* CHANNEL CONTROL BLOCK */ + +typedef struct st_sci_ch_ctrl /* SCI channel control (for handle) */ +{ + sci_ch_rom_t const *rom; /* pointer to rom info */ + sci_mode_t mode; /* operational mode */ + uint32_t baud_rate; /* baud rate */ + void (*callback)(void *p_args); /* function ptr for rcvr errs */ + union + { +#if (SCI_CFG_ASYNC_INCLUDED) + byteq_hdl_t que; /* async transmit queue handle */ +#endif + uint8_t *buf; /* sspi/sync tx buffer ptr */ + } u_tx_data; + union + { +#if (SCI_CFG_ASYNC_INCLUDED) + byteq_hdl_t que; /* async receive queue handle */ +#endif + uint8_t *buf; /* sspi/sync rx buffer ptr */ + } u_rx_data; + bool tx_idle; /* TDR is empty (async); TSR is empty (sync/sspi) */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + bool save_rx_data; /* save the data that is clocked in */ + uint16_t tx_cnt; /* number of bytes to transmit */ + uint16_t rx_cnt; /* number of bytes to receive */ + bool tx_dummy; /* transmit dummy byte, not buffer */ +#endif + uint32_t pclk_speed; /* saved peripheral clock speed for break generation */ +#if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + bool rx_idle; + uint8_t qindex_app_tx; + uint8_t qindex_int_tx; + uint8_t qindex_app_rx; + uint8_t qindex_int_rx; + sci_fifo_ctrl_t queue[2]; +#endif +} sci_ch_ctrl_t; + + +/* BAUD DIVISOR INFO */ + +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* when abcs=1, divisor = 32*pow(2,2n-1) */ +/* when abcs=0, divisor = 64*pow(2,2n-1) */ + +typedef struct st_baud_divisor +{ + int16_t divisor; // clock divisor + uint8_t abcs; // abcs value to get divisor + uint8_t bgdm; // bdgm value to get divisor + uint8_t abcse; // abcse value to get divisor + uint8_t cks; // cks value to get divisor (cks = n) +} baud_divisor_t; + +#define NUM_DIVISORS_ASYNC (13) +#define NUM_DIVISORS_SYNC (4) + + +/***************************************************************************** +Exported global variables and functions +******************************************************************************/ +#if (SCI_CFG_ASYNC_INCLUDED) +extern const baud_divisor_t async_baud[]; +#endif +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +extern const baud_divisor_t sync_baud[]; +#endif + +#if (SCI_CFG_CH1_INCLUDED) +extern const sci_ch_rom_t ch1_rom; +extern sci_ch_ctrl_t ch1_ctrl; +#endif + +#if (SCI_CFG_CH5_INCLUDED) +extern const sci_ch_rom_t ch5_rom; +extern sci_ch_ctrl_t ch5_ctrl; +#endif + +#if (SCI_CFG_CH6_INCLUDED) +extern const sci_ch_rom_t ch6_rom; +extern sci_ch_ctrl_t ch6_ctrl; +#endif + +#if (SCI_CFG_CH8_INCLUDED) +extern const sci_ch_rom_t ch8_rom; +extern sci_ch_ctrl_t ch8_ctrl; +#endif + +#if (SCI_CFG_CH9_INCLUDED) +extern const sci_ch_rom_t ch9_rom; +extern sci_ch_ctrl_t ch9_ctrl; +#endif + +#if (SCI_CFG_CH12_INCLUDED) +extern const sci_ch_rom_t ch12_rom; +extern sci_ch_ctrl_t ch12_ctrl; +#endif + +extern const sci_hdl_t g_sci_handles[]; + +extern void sci_init_register(sci_hdl_t const hdl); + +#if (SCI_CFG_ASYNC_INCLUDED) +extern sci_err_t sci_async_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); +#endif + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +extern sci_err_t sci_sync_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); +#endif + +extern sci_err_t sci_mcu_param_check(uint8_t const chan); + +extern int32_t sci_init_bit_rate(sci_hdl_t const hdl, + uint32_t const pclk, + uint32_t const baud); + +extern void sci_initialize_ints(sci_hdl_t const hdl, + uint8_t const priority); + +extern void sci_disable_ints(sci_hdl_t const hdl); + +#endif /* SCI_RX140_H */ + diff --git a/zephyr/rx/rdp_cfg/r_config/rx140/r_bsp_config.h b/zephyr/rx/rdp_cfg/r_config/rx140/r_bsp_config.h new file mode 100644 index 00000000..6ee1e1f5 --- /dev/null +++ b/zephyr/rx/rdp_cfg/r_config/rx140/r_bsp_config.h @@ -0,0 +1,652 @@ +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : r_bsp_config_reference.h +* Device(s) : RX140 +* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included +* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h) +* is just a reference file that the user can use to make their own r_bsp_config.h file. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 30.06.2021 1.00 First release +* : 30.11.2021 1.01 Added the following macro definitions. +* - BSP_CFG_CONFIGURATOR_VERSION +* - BSP_CFG_CPLUSPLUS +* Changed initial value of the following macro definitions. +* - BSP_CFG_MCU_PART_GROUP +* - BSP_CFG_MCU_PART_SERIES +* : 11.02.2022 1.02 Changed initial value of the following macro definitions. +* - BSP_CFG_MCU_PART_PACKAGE +* - BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE +* - BSP_CFG_HOCO_OSCILLATE_ENABLE +* - BSP_CFG_CLOCK_SOURCE +* - BSP_CFG_CLKOUT_SOURCE +* - BSP_CFG_SWINT_UNIT1_ENABLE +* Modified comment. +* : 22.04.2022 1.03 Modified comment. +* : 28.02.2023 1.04 Modified comment. +* : 21.11.2023 1.05 Added the following macro definitions. +* - BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE +* - BSP_CFG_MEMORY_BUS1_PRIORITY +* - BSP_CFG_MEMORY_BUS2_PRIORITY +* - BSP_CFG_INTERNAL_PERIPHERAL_BUS1_PRIORITY +* - BSP_CFG_INTERNAL_PERIPHERAL_BUS2_3_PRIORITY +* - BSP_CFG_INTERNAL_PERIPHERAL_BUS6_PRIORITY +* - BSP_CFG_BOOTLOADER_PROJECT +* Deleted the BSP_CFG_ROM_CODE_PROTECT_VALUE. +* Modified comment. +* : 27.11.2024 1.06 Changed comment of BSP_CFG_RTC_ENABLE. +* : 26.02.2025 1.07 Changed the disclaimer. +***********************************************************************************************************************/ + +#include +#include +#include +#include "mcu_clocks.h" + +#ifndef R_BSP_CONFIG_REF_HEADER_FILE +#define R_BSP_CONFIG_REF_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* NOTE: + The default settings are the same as when using RSKRX140. + Change to the settings for the user board. +*/ + +/* Start up select + 0 = Enable BSP startup program. + 1 = Disable BSP startup program. (e.g. Using user startup program.) + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_STARTUP_DISABLE (0) + +/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such + as package and memory size. + To help parse this information, the part number will be defined using multiple macros. + R 5 F 51 40 6 A D FM - - + | | | | | | | | | | | Macro Name Description + | | | | | | | | | | |_not used = Production identification code + | | | | | | | | | |____not used = Packing, Terminal material + | | | | | | | | |_______BSP_CFG_MCU_PART_PACKAGE = Package type, number of pins, and pin pitch + | | | | | | | |_________not used = Operating temperature + | | | | | | |___________BSP_CFG_MCU_PART_FUNCTION = Encryption and CAN included/not included + | | | | | |_____________BSP_CFG_MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity + | | | | |________________BSP_CFG_MCU_PART_GROUP = Group name + | | | |___________________BSP_CFG_MCU_PART_SERIES = Series name + | | |_____________________BSP_CFG_MCU_PART_MEMORY_TYPE = Type of memory (Flash) + | |_______________________not used = Renesas MCU + |_________________________not used = Renesas semiconductor product. + */ + +/* Package type. Set the macro definition based on values below: + Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch + FN = 0xB = LFQFP/80/0.50 + FM = 0x0 = LFQFP/64/0.50 + FK = 0x1 = LQFP/64/0.80 + FL = 0x3 = LFQFP/48/0.50 + NE = 0x4 = HWQFN/48/0.50 + FJ = 0x2 = LFQFP/32/0.80 + NH = 0x5 = HWQFN/32/0.50 +*/ +#define BSP_CFG_MCU_PART_PACKAGE (0xB) + +/* Whether Encryption and CAN included or not. + Character(s) = Value for macro = Description + A = 0xA = Encryption module not included + B = 0xB = Encryption module included +*/ +#define BSP_CFG_MCU_PART_FUNCTION (0xA) + +/* ROM, RAM, and Data Flash Capacity. + Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size + 6 = 0x6 = 256KB/64KB/8KB + 5 = 0x5 = 128KB/32KB/8KB + 3 = 0x3 = 64KB/16KB/4KB +*/ +#define BSP_CFG_MCU_PART_MEMORY_SIZE (0x6) + +/* Group name. + Character(s) = Description + 40 = RX140 Group +*/ +#define BSP_CFG_MCU_PART_GROUP "RX140" + +/* Series name. + Character(s) = Description + 51 = RX100 Series +*/ +#define BSP_CFG_MCU_PART_SERIES "RX100" + +/* Memory type. + Character(s) = Value for macro = Description + F = 0x0 = Flash memory version +*/ +#define BSP_CFG_MCU_PART_MEMORY_TYPE (0x0) + +/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack. + * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU + * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how + * much stack space to allocate since the user does not have to worry about always having enough room on the + * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not + * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used). + * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then + * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings. + * + * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored. + * 1 = Use 2 stacks. User stack and interrupt stack will both be used. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_USER_STACK_ENABLE (1) + +/* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 +/* User Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. */ +#define BSP_CFG_USTACK_BYTES (0x400) +#endif + +/* Interrupt Stack size in bytes. + NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_ISTACK_BYTES (0x100) + +/* Heap size in bytes. + To disable the heap you must follow these steps: + 1) Set this macro (BSP_CFG_HEAP_BYTES) to 0. + 2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0. + 3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain + settings and choosing the Standard Library section. After that choose 'Contents' in e2 studio. + This will present a list of modules that can be included. Uncheck the box for stdio.h. + NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_HEAP_BYTES (0x400) + +/* Initializes C input & output library functions. + 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value. + 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_IO_LIB_ENABLE (1) + +/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions + by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */ +#define BSP_CFG_USER_CHARGET_ENABLED (0) +#define BSP_CFG_USER_CHARGET_FUNCTION my_sw_charget_function + +#define BSP_CFG_USER_CHARPUT_ENABLED (0) +#define BSP_CFG_USER_CHARPUT_FUNCTION my_sw_charput_function + +/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information + on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual. + 0 = Stay in Supervisor mode. + 1 = Switch to User mode. + NOTE: This is invalid when using Renesas RTOS with CCRX. +*/ +#define BSP_CFG_RUN_IN_USER_MODE (0) + +/* Set your desired ID code. NOTE, leave at the default (all 0xFF's) if you do not wish to use an ID code. If you set + this value and program it into the MCU then you will need to remember the ID code because the debugger will ask for + it when trying to connect. Note that the E1/E20 will ignore the ID code when programming the MCU during debugging. + If you set this value and then forget it then you can clear the ID code by connecting up in serial boot mode using + FDT. The ID Code is 16 bytes long. The macro below define the ID Code in 4-byte sections. */ +/* Lowest 4-byte section, address 0xFFFFFFA0. From MSB to LSB: Control Code, ID code 1, ID code 2, ID code 3. */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +/* 2nd ID Code section, address 0xFFFFFFA4. From MSB to LSB: ID code 4, ID code 5, ID code 6, ID code 7. */ +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +/* 3rd ID Code section, address 0xFFFFFFA8. From MSB to LSB: ID code 8, ID code 9, ID code 10, ID code 11. */ +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +/* 4th ID Code section, address 0xFFFFFFAC. From MSB to LSB: ID code 12, ID code 13, ID code 14, ID code 15. */ +#define BSP_CFG_ID_CODE_LONG_4 (0xFFFFFFFF) + +/* Select whether to oscillate the Main Clock Oscillator. + 0 = Stop Oscillating the Main Clock. (default) + 1 = Enable oscillating the Main Clock. +*/ +#define BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE DT_NODE_HAS_STATUS(DT_NODELABEL(xtal), okay) + +/* Select whether to oscillate the Sub Clock Oscillator. + 0 = Stop Oscillating the Sub Clock. (default) + 1 = Enable Oscillating the Sub Clock. +*/ +#define BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE DT_NODE_HAS_STATUS(DT_NODELABEL(subclk), okay) + +/* Select whether to oscillate the High Speed On-Chip Oscillator (HOCO). + 0 = Stop Oscillating the HOCO. + 1 = Enable Oscillating the HOCO. (default) +*/ +#define BSP_CFG_HOCO_OSCILLATE_ENABLE DT_NODE_HAS_STATUS(DT_NODELABEL(hoco), okay) + +/* Select whether to oscillate the Low Speed On-Chip Oscillator (LOCO). + 0 = Stop Oscillating the LOCO. (default) + 1 = Enable Oscillating the LOCO. +*/ +#define BSP_CFG_LOCO_OSCILLATE_ENABLE DT_NODE_HAS_STATUS(DT_NODELABEL(loco), okay) + +/* Select whether to oscillate the IWDT-Dedicated On-Chip Oscillator (IWDT). + 0 = Stop Oscillating the IWDT Clock. (default) + 1 = Enable Oscillating the IWDT Clock. +*/ +#define BSP_CFG_IWDT_CLOCK_OSCILLATE_ENABLE DT_NODE_HAS_STATUS(DT_NODELABEL(iwdtlsclk), okay) + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit +*/ +#define BSP_CFG_CLOCK_SOURCE RX_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock))) + +/* LPT (Low Power Timer) Clock source select (LPTCR1.LPCNTCKSEL) + 0 = Sub-clock + 1 = IWDT + 2 = LPT non use + 3 = Low Speed On-Chip Oscillator (LOCO) clock divided by 4 +*/ +#define BSP_CFG_LPT_CLOCK_SOURCE RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(lptclk), lpt_clk, 2) + +/* Main clock Oscillator Switching (MOSEL). + 0 = Resonator + 1 = External clock input +*/ +#define BSP_CFG_MAIN_CLOCK_SOURCE RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), mosel, 0) + +/* Configure clock source of clock output(CLKOUT) pin (CKOSEL). + Available clock sources: + 0 = LOCO + 1 = HOCO + 2 = Main clock oscillator (default) + 3 = Sub-clock oscillator + 4 = PLL circuit + 8 = CTSU internal clock + */ +#define BSP_CFG_CLKOUT_SOURCE RX_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout))) + +/* Defines whether to use the RTC or not. + This setting will initialize the RTC related registers. + 0 = The RTC is not to be used. + 1 = The RTC is to be used. + When using RTC FIT or RTC CG, the Smart Configurator sets this to "1". Set it to "1" when using RTC. +*/ +#define BSP_CFG_RTC_ENABLE DT_NODE_HAS_STATUS(DT_NODELABEL(rtcsclk), okay) + +/* Sub-Clock Oscillator Drive Capacity Control (SODRV). + 0 = Drive capacity for standard CL. (default) + 2 = High-drive output for the low CL. + 3 = Middle-drive output for the low CL + 4 = Low-drive output for the low CL +*/ +#define BSP_CFG_SOSC_DRV_CAP RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(subclk), drive_capacity, 0) + +/* Clock configuration options. + The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The + multiplier settings are used to set the clock registers in resetprg.c. If a 8MHz clock is used and the + ICLK is 48MHz, PCLKB is 32MHz, FCLK is 48MHz, PCLKD is 48MHz then the + settings would be: + + BSP_CFG_XTAL_HZ = 8000000 + BSP_CFG_PLL_DIV = 1 (no division) + BSP_CFG_PLL_MUL = 6 (8MHz x 6 = 48MHz) + BSP_CFG_ICK_DIV = 1 : System Clock (ICLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV) = 48MHz + BSP_CFG_PCKB_DIV = 2 : Peripheral Clock B (PCLKB) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 24MHz + BSP_CFG_PCKD_DIV = 1 : Peripheral Clock D (PCLKD) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 48MHz + BSP_CFG_FCK_DIV = 1 : Flash IF Clock (FCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV) = 48MHz +*/ +/* Input clock frequency in Hz (XTAL or EXTAL). */ +#define BSP_CFG_XTAL_HZ RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0) + +/* PLL Input Frequency Divider Select (PLIDIV). + Available divisors = /1 (no division), /2, /4 +*/ +#define BSP_CFG_PLL_DIV RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, 1) + +/* PLL Frequency Multiplication Factor Select (STC). + Available multipliers = x4, x4.5, x5, x5.5, x6, x6.5, x7, x7.5, x8, x8.5, x9, x9.5, x10, x10.5, x11, x11.5, x12 +*/ +#define BSP_CFG_PLL_MUL (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), mul, 15) + 1) / 2 + +/* System Clock Divider (ICK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_ICK_DIV RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), div, 1) + +/* Peripheral Module Clock B Divider (PCKB). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKB_DIV RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), div, 1) + +/* Peripheral Module Clock D Divider (PCKD). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKD_DIV RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), div, 1) + +/* Flash IF Clock Divider (FCK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_FCK_DIV RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), div, 1) + +/* CLKOUT Output Frequency Division Ratio Select. (CKODIV) + Values + 0 = x1/1 + 1 = x1/2 + 2 = x1/4 + 3 = x1/8 (default) + 4 = x1/16 + 5 = x1/32 + 6 = x1/64 + 7 = x1/128 + */ +#define BSP_CFG_CLKOUT_DIV RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), div, 1) + +/* Configure clock output(CLKOUT) pin (CKOSTP). + Values + 0 = CLKOUT pin output stopped. (Fixed to the low level) (default) + 1 = CLKOUT pin output enabled. + */ +#define BSP_CFG_CLKOUT_OUTPUT DT_NODE_HAS_STATUS(DT_NODELABEL(clkout), okay) + + +/* Main Clock Oscillator Wait Time (MOSCWTCR). + Set these bits to select the oscillation stabilization wait time of the main clock oscillator. + Set the main clock oscillation stabilization time to longer than or equal to the stabilization + time recommended by the oscillator manufacturer. When the main clock is externally input, + set these bits to 00000b because the oscillation stabilization time is not required. + + 00000b: Wait time = 0 cycles (0 us) + 00001b: Wait time = 1024 cycles (256 us) + 00010b: Wait time = 2048 cycles (512 us) + 00011b: Wait time = 4096 cycles (1.024 ms) + 00100b: Wait time = 8192 cycles (2.048 ms) + 00101b: Wait time = 16384 cycles (4.096 ms) + 00110b: Wait time = 32768 cycles (8.192 ms) + 00111b: Wait time = 65536 cycles (16.384 ms) + 01000b: Wait time =131072 cycles (32.768 ms) + Settings other than above are prohibited. + Wait time when LOCO = 4.0 MHz (0.25 us, TYP.) +*/ +#define BSP_CFG_MOSC_WAIT_TIME RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), stabilization_time, 4) + +/* Sub-Clock Oscillator Wait Time (Use R_BSP_SoftwareDelay). + Setting delay unit is in milliseconds. +*/ +#define BSP_CFG_SOSC_WAIT_TIME RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(subclk), sub_clk_osc, 500) + +/* Select whether to initialize the HOCO trimming register. + 0 = Disable reset the HOCO trimming register in the initial setting process. + 1 = Enable reset the HOCO trimming register in the initial setting process. + Note: The trimming value is adjusted at shipment on the specified conditions and the value after a reset varies + with the chips. When re-writing the HOCO trimming register, enable this macro definition. +*/ +#define BSP_CFG_HOCO_TRIMMING_ENABLE (0) + +/* Set the frequency trimming value for the HOCO. + 0(Frequency: Low) - 63(Frequency: High) + Note: The trimming value is adjusted at shipment on the specified conditions and the value after a reset varies + with the chips. When re-writing the HOCO trimming register, set this macro definition. +*/ +#define BSP_CFG_HOCO_TRIMMING_REG_VALUE (0) + +/* Configure IWDT settings. + OFS0 - Option Function Select Register 0 + b31:b15 Reserved (set to 1) + b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes) + b13 Reserved (set to 1) + b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256) + b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048) + b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b0 Reserved (set to 1) + NOTE: When the IWDT-dedicated on-chip oscillator is used as the clock source for the low-power timer, + set the OFS0.IWDTSLCSTP + bit to 0 (counting stop is disabled) in IWDT auto-start mode operation. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS0_REG_VALUE (0xFFFFFFFF) + +#define SET_OFS1_HOCO_BITS(reg, freq) \ + ((reg) & ~(0b11 << 12)) | ((((freq) == 24000000 ? 0b10 : (freq) == 32000000 ? 0b11 : (freq) == 48000000 ? 0b01 : 0b00) << 12)) + +/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset. + OFS1 - Option Function Select Register 1 + b31:b14 Reserved (set to 1) + b13:b12 HOCOFQ - HOCO Frequency Select + 0 0: 48 MHz + 0 1: 48 MHz + 1 0: 24 MHz + 1 1: 32 MHz + b11:b9 Reserved (set to 1) + b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable) + b7:b4 Reserved (set to 1) + b3 FASTSTUP - Power-On Fast Startup Time (0=fast startup, 1=normal) + b2 LVDAS - Voltage Detection 0 Circuit Start (0=enable, 1=disable) + b1:b0 VDSEL - Voltage Detection 0 Level Select + 0 0: 3.85 V + 0 1: 2.85 V + 1 0: 2.53 V + 1 1: 1.90 V + Default value is 0xFFFFDFFF. +*/ +#define BSP_CFG_OFS1_REG_VALUE (SET_OFS1_HOCO_BITS(0xFFFFFFFF, (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(hoco), clock_frequency, 48000000)))) + +/* This macro lets other modules no if a RTOS is being used. + 0 = RTOS is not used. + 1 = FreeRTOS is used. + 2 = embOS is used.(This is not available.) + 3 = MicroC_OS is used.(This is not available.) + 4 = Renesas ITRON OS (RI600V4 or RI600PX) is used. + 5 = Azure RTOS is used. +*/ +#define BSP_CFG_RTOS_USED (0) + +/* This macro is used to select which Renesas ITRON OS. + 0 = RI600V4 is used. + 1 = RI600PX is used. +*/ +#define BSP_CFG_RENESAS_RTOS_USED (0) + +/* This macro is used to select which CMT channel used for system timer of RTOS. + * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */ +#if BSP_CFG_RTOS_USED != 0 +/* Setting value. + * 0 = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS). + * 1 = CMT channel 1 used for system timer of RTOS. + * 2 = CMT channel 2 used for system timer of RTOS. + * 3 = CMT channel 3 used for system timer of RTOS. + * Others = Invalid. + * NOTE: This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_RTOS_SYSTEM_TIMER (0) +#endif + +/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its + locking mechanisms then they can change this macro. + NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'. + 0 = Use default locking (non-RTOS) + 1 = Use user defined locking mechanism. +*/ +#define BSP_CFG_USER_LOCKING_ENABLED (0) + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef + that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be + a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions + that will handle the locking and unlocking. These functions should be defined below. + If BSP_CFG_USER_LOCKING_ENABLED is != 0: + R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index) + R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index) + NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter. + R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + NOTE:With these functions the actual address of the lock to use is passed as the parameter. + NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else, + return false. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION my_hw_locking_function +#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION my_hw_unlocking_function +#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION my_sw_locking_function +#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION my_sw_unlocking_function + +/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the + following callback definitions AND provide a call back function name for the respective callback + function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result + in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C + runtime environment by resetprg. + Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined + my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg. +*/ +#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION my_sw_warmstart_prec_function + +#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION my_sw_warmstart_postc_function + +/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users + will want to disable this for production code. The reason for this would be to save execution time and code space. + This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its + own local macro for this same purpose. By default the local macros will take the global value from here though + they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter + checking should only used when inputs are known to be good and the increase in speed or decrease in code space is + needed. + 0 = Global setting for parameter checking is disabled. + 1 = Global setting for parameter checking is enabled (Default). +*/ +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) + +/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This + macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */ +#define BSP_CFG_MCU_VCC_MV (3300) + +/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool. + When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0. + 0 = Disabled (default) + 1 = Smart Configurator initialization code used +*/ +#define BSP_CFG_CONFIGURATOR_SELECT (0) + +/* Version number of Smart Configurator. + This macro definition is updated by Smart Configurator. +*/ +#define BSP_CFG_CONFIGURATOR_VERSION (2210) + +/* For some BSP functions, it is necessary to ensure that, while these functions are executing, interrupts from other + FIT modules do not occur. By controlling the IPL, these functions disable interrupts that are at or below the + specified interrupt priority level. + This macro sets the IPL. Range is 0x0 - 0xF. + Please set this macro more than IPR for other FIT module interrupts. + The default value is 0xF (maximum value). + Don't change if there is no special processing with higher priority than all fit modules. +*/ +#define BSP_CFG_FIT_IPL_MAX (0xF) + +/* Software Interrupt (SWINT). + 0 = Software interrupt is not used. + 1 = Software interrupt is used. + NOTE: When this macro is set to 1, the software interrupt is initialized in bsp startup routine. +*/ +#define BSP_CFG_SWINT_UNIT1_ENABLE (0) + +/* Software Interrupt Task Buffer Number. + For software interrupt, this value is number of buffering user tasks. + So user can increase this value if user system would have many software interrupt tasks + and user system has enough buffer. This value requires 9 byte per task. + NOTE: This setting is common to all units. It can not be set individually. + The maximum value is 254. +*/ +#define BSP_CFG_SWINT_TASK_BUFFER_NUMBER (8) + +/* Initial value of the software interrupt priority. + For software interrupt, this value is interrupt priority. Range is 0x0 - 0xF. + NOTE: This setting is common to all units. It can not be set individually. + Please be careful that this setting is the initial value of the interrupt priority register(IPR). + It is possible to dynamically change the IPR. +*/ +#define BSP_CFG_SWINT_IPR_INITIAL_VALUE (0x1) + +/* This macro is used for serial terminal on the board selected by smart configurator. + 0 = SCI UART Terminal is disabled. + 1 = SCI UART Terminal is enabled. +*/ +#define BSP_CFG_SCI_UART_TERMINAL_ENABLE (0) + +/* This macro is channel number for serial terminal. +*/ +#define BSP_CFG_SCI_UART_TERMINAL_CHANNEL (1) + +/* This macro is bit-rate for serial terminal. +*/ +#define BSP_CFG_SCI_UART_TERMINAL_BITRATE (115200) + +/* This macro is interrupt priority for serial terminal. + 0(low) - 15(high) +*/ +#define BSP_CFG_SCI_UART_TERMINAL_INTERRUPT_PRIORITY (15) + +/* This macro is used for C++ project and updated by Smart Configurator. + 0 = This project is a C project.(Not a C++ project). + 1 = This project is a C++ project. +*/ +#define BSP_CFG_CPLUSPLUS (0) + +/* Select whether to enable bus priority initialization. + 0 = Bus priority initialization is disabled. + 1 = Bus priority initialization is enabled. +*/ +#define BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE (0) + +/* Select the priority order for memory bus 1 (RAM). + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_MEMORY_BUS1_PRIORITY (0) + +/* Select the priority order for memory bus 2 (ROM). + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_MEMORY_BUS2_PRIORITY (0) + +/* Select the priority order for internal peripheral bus 1. + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_INTERNAL_PERIPHERAL_BUS1_PRIORITY (0) + +/* Select the priority order for internal peripheral buses 2 and 3. + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_INTERNAL_PERIPHERAL_BUS2_3_PRIORITY (0) + +/* Select the priority order for internal peripheral bus 6. + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_INTERNAL_PERIPHERAL_BUS6_PRIORITY (0) + +/* Select whether it is bootloader project. + 0 = This project isn't a bootloader project. + 1 = This project is a bootloader project. + NOTE: Not normally used. Set this to "1" only in the bootloader project. +*/ +#define BSP_CFG_BOOTLOADER_PROJECT (0) + +#endif /* R_BSP_CONFIG_REF_HEADER_FILE */