diff --git a/drivers/rx/README b/drivers/rx/README index 8855efc7..4a0f1087 100644 --- a/drivers/rx/README +++ b/drivers/rx/README @@ -82,6 +82,21 @@ Patch List: Impacted files: drivers/rx/rdp/src/r_lvd_rx/src/r_lvd_rx_hw.c + * Add include stdint header in BSP of RX130 + Impacted files: + drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_clocks.h + + * Made the group interrupt handler a global variable. + Impacted files: + drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c + + * Added a new function based on R_BSP_InterruptWrite + that allows passing a user-defined argument to the registered interrupt handler. + Impacted files: + drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c + drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.h + drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.h + * Fix implicit conversion build warnings Impacted files: drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_clocks.c diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c index f985bd3a..ff336717 100644 --- a/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c @@ -58,6 +58,9 @@ Private global variables and functions ***********************************************************************************************************************/ /* This array holds callback functions. */ static void (* g_bsp_vectors[BSP_INT_SRC_TOTAL_ITEMS])(void * pdata); +#if defined(BSP_MCU_RX26T) +static void *g_bsp_contexts[BSP_INT_SRC_TOTAL_ITEMS]; +#endif static bsp_int_err_t bsp_fit_interrupts_control (bool enable, bsp_int_ctrl_t * pdata); @@ -140,6 +143,9 @@ void bsp_interrupt_open(void) { /* Casting is valid because it matches the type to the right side or argument. */ g_bsp_vectors[i] = FIT_NO_FUNC; +#if defined(BSP_MCU_RX26T) + g_bsp_contexts[i] = NULL; +#endif } #ifdef BSP_MCU_SOFTWARE_CONFIGURABLE_INTERRUPT @@ -202,6 +208,58 @@ bsp_int_err_t R_BSP_InterruptWrite(bsp_int_src_t vector, bsp_int_cb_t callback) return err; } /* End of function R_BSP_InterruptWrite() */ +#if defined(BSP_MCU_RX26T) +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptWrite_EX + ******************************************************************************************************************//** + * @brief Registers a callback function for an interrupt. + * @param[in] vector Which interrupt to register a callback for. + * @param[in] callback Pointer to function to call when interrupt occurs. + * @param[in] context Pointer to the callback function's argument. + * @retval BSP_INT_SUCCESS Successful, callback has been registered. + * @retval BSP_INT_ERR_INVALID_ARG An invalid interrupt source was specified for vector. + * @details This function registers a callback function for an interrupt. If FIT_NO_FUNC, NULL, or any other invalid + * function address is passed for the callback argument then any previously registered callbacks are unregistered. + * If one of the interrupts that is handled by this code is triggered then the interrupt handler will query this code + * to see if a valid callback function is registered. If one is found then the callback function will be called. + * If one is not found then the interrupt handler will clear the appropriate flag(s) and exit. If the user has a + * callback function registered and wishes to no longer handle the interrupt then the user should call this function + * again with FIT_NO_FUNC as the vector parameter. + * @note Use of FIT_NO_FUNC is preferred over NULL since access to the address defined by FIT_NO_FUNC will cause a + * bus error which is easy for the user to catch. NULL typically resolves to 0 which is a valid address on RX MCUs. + */ +bsp_int_err_t R_BSP_InterruptWrite_EX(bsp_int_src_t vector, bsp_int_cb_t callback, void *context) +{ + bsp_int_err_t err; + + err = BSP_INT_SUCCESS; + + /* Check for valid address. */ + if (((uint32_t)callback == (uint32_t)NULL) || ((uint32_t)callback == (uint32_t)FIT_NO_FUNC)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + g_bsp_vectors[vector] = FIT_NO_FUNC; + g_bsp_contexts[vector] = NULL; + } + else + { + if ((BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS == vector) || (BSP_INT_SRC_BUS_ERROR_TIMEOUT == vector) || + (BSP_INT_SRC_EMPTY <= vector)) + { + /* When registering a bus error callback function, specify BSP_INT_SRC_BUS_ERROR in the vector. */ + err = BSP_INT_ERR_INVALID_ARG; + } + else + { + g_bsp_vectors[vector] = callback; + g_bsp_contexts[vector] = context; + } + } + + return err; +} /* End of function R_BSP_InterruptWrite_EX() */ +#endif + /********************************************************************************************************************** * Function Name: R_BSP_InterruptRead ******************************************************************************************************************//** @@ -297,7 +355,9 @@ bsp_int_err_t R_BSP_InterruptControl(bsp_int_src_t vector, bsp_int_cmd_t cmd, vo { /* Fill in callback info. */ cb_args.vector = vector; - +#if defined(BSP_MCU_RX26T) + cb_args.p_context = g_bsp_contexts[vector]; +#endif g_bsp_vectors[vector](&cb_args); } else diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.h b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.h index 0deb2d5c..c2945a12 100644 --- a/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.h +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.h @@ -41,6 +41,9 @@ Exported global functions (to be accessed by other files) void R_BSP_InterruptRequestEnable(uint32_t vector); void R_BSP_InterruptRequestDisable(uint32_t vector); bsp_int_err_t R_BSP_InterruptWrite(bsp_int_src_t vector, bsp_int_cb_t callback); +#if defined(BSP_MCU_RX26T) +bsp_int_err_t R_BSP_InterruptWrite_EX(bsp_int_src_t vector, bsp_int_cb_t callback, void *context); +#endif bsp_int_err_t R_BSP_InterruptRead(bsp_int_src_t vector, bsp_int_cb_t * callback); bsp_int_err_t R_BSP_InterruptControl(bsp_int_src_t vector, bsp_int_cmd_t cmd, void * pdata); diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.c b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.c index 0f84106f..fcdb7f1f 100644 --- a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.c +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.c @@ -1,639 +1,634 @@ -/* -* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ -/*********************************************************************************************************************** -* File Name : mcu_interrupts.c -* Description : This module is the control of the interrupt enable. -***********************************************************************************************************************/ -/********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 28.02.2023 1.00 First Release -* : 21.11.2023 1.01 Added timeout detection processing to bus error processing. -* Added processing to control only illegal address access detection to bus error -* processing. -* Added processing to control only timeout detection to bus error processing. -* : 26.02.2025 1.02 Changed the disclaimer. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Includes , "Project Includes" -***********************************************************************************************************************/ -/* Access to r_bsp. */ -#include "platform.h" - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -/* Let FPSW EV, EO, EZ, EU, EX=1 (FPU exceptions enabled.) */ -#define BSP_PRV_FPU_EXCEPTIONS_ENABLE (0x00007C00) - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Exported global variables (to be accessed by other files) -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Private global variables and functions -***********************************************************************************************************************/ -R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl0_handler_isr, VECT(ICU,GROUPBL0)) -R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl1_handler_isr, VECT(ICU,GROUPBL1)) -R_BSP_PRAGMA_STATIC_INTERRUPT(group_bl2_handler_isr, VECT(ICU,GROUPBL2)) -R_BSP_PRAGMA_STATIC_INTERRUPT(group_al0_handler_isr, VECT(ICU,GROUPAL0)) -R_BSP_PRAGMA_STATIC_INTERRUPT(group_al1_handler_isr, VECT(ICU,GROUPAL1)) - -/*********************************************************************************************************************** -* Function Name: bsp_interrupt_enable_disable -* Description : Either enables or disables an interrupt. -* Arguments : vector - -* Which vector to enable or disable. -* enable - -* Whether to enable or disable the interrupt. -* Return Value : BSP_INT_SUCCESS - -* Interrupt enabled or disabled. -* BSP_INT_ERR_UNSUPPORTED - -* API does not support enabling/disabling for this vector. -***********************************************************************************************************************/ -bsp_int_err_t bsp_interrupt_enable_disable (bsp_int_src_t vector, bool enable) -{ -#ifdef __FPU - uint32_t tmp_fpsw; -#endif - bsp_int_err_t err = BSP_INT_SUCCESS; - - switch (vector) - { - case (BSP_INT_SRC_BUS_ERROR): - if (true == enable) - { - /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ - /* Clear any pending interrupts */ - IR(BSC,BUSERR) = 0; - - /* Make this the highest priority interrupt (adjust as necessary for your application */ - IPR(BSC,BUSERR) = 0x0F; - - /* Enable the interrupt in the ICU*/ - R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); - - /* Enable illegal address interrupt in the BSC */ - BSC.BEREN.BIT.IGAEN = 1; - - /* Enable timeout detection enable. */ - BSC.BEREN.BIT.TOEN = 1; - } - else - { - /* Disable the bus error interrupt. */ - /* Disable the interrupt in the ICU*/ - R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); - - /* Disable illegal address interrupt in the BSC */ - BSC.BEREN.BIT.IGAEN = 0; - - /* Disable timeout detection enable. */ - BSC.BEREN.BIT.TOEN = 0; - } - break; - - case (BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS): - if (true == enable) - { - /* Check the bus error monitoring status. */ - if (0 == BSC.BEREN.BYTE) - { - /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ - /* Clear any pending interrupts */ - IR(BSC,BUSERR) = 0; - - /* Make this the highest priority interrupt (adjust as necessary for your application */ - IPR(BSC,BUSERR) = 0x0F; - - /* Enable the interrupt in the ICU. */ - R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); - } - - /* Enable illegal address interrupt in the BSC */ - BSC.BEREN.BIT.IGAEN = 1; - } - else - { - /* Disable illegal address interrupt in the BSC */ - BSC.BEREN.BIT.IGAEN = 0; - - /* Check the bus error monitoring status. */ - if (0 == BSC.BEREN.BYTE) - { - /* Disable the bus error interrupt in the ICU. */ - R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); - } - } - break; - - case (BSP_INT_SRC_BUS_ERROR_TIMEOUT): - if (true == enable) - { - /* Check the bus error monitoring status. */ - if (0 == BSC.BEREN.BYTE) - { - /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ - /* Clear any pending interrupts */ - IR(BSC,BUSERR) = 0; - - /* Make this the highest priority interrupt (adjust as necessary for your application */ - IPR(BSC,BUSERR) = 0x0F; - - /* Enable the interrupt in the ICU. */ - R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); - } - - /* Enable timeout detection enable. */ - BSC.BEREN.BIT.TOEN = 1; - } - else - { - /* Disable timeout detection enable. */ - BSC.BEREN.BIT.TOEN = 0; - - /* Check the bus error monitoring status. */ - if (0 == BSC.BEREN.BYTE) - { - /* Disable the bus error interrupt in the ICU. */ - R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); - } - } - break; - -#ifdef __FPU - case (BSP_INT_SRC_EXC_FPU): - - /* Get current FPSW. */ - tmp_fpsw = (uint32_t)R_BSP_GET_FPSW(); - - if (true == enable) - { - /* Set the FPU exception flags. */ - R_BSP_SET_FPSW((tmp_fpsw | (uint32_t)BSP_PRV_FPU_EXCEPTIONS_ENABLE)); - } - else - { - /* Clear only the FPU exception flags. */ - R_BSP_SET_FPSW((tmp_fpsw & (uint32_t)~BSP_PRV_FPU_EXCEPTIONS_ENABLE)); - } - break; -#endif - - case (BSP_INT_SRC_EXC_NMI_PIN): - if (true == enable) - { - /* Enable NMI pin interrupt (cannot undo!) */ - ICU.NMIER.BIT.NMIEN = 1; - } - else - { - /* NMI pin interrupts cannot be disabled after being enabled. */ - err = BSP_INT_ERR_UNSUPPORTED; - } - break; - - default: - err = BSP_INT_ERR_UNSUPPORTED; - break; - } - - return err; -} /* End of function bsp_interrupt_enable_disable() */ - -/*********************************************************************************************************************** -* Function Name: group_bl0_handler_isr -* Description : Interrupt handler for Group BL0 interrupts. The way this code works is that for each possible interrupt -* in this group the following will be performed: -* 1) Test to see if an interrupt is requested for this source -* 2) If an interrupt is requested then the registered callback is called (if one is registered) -* NOTE: The interrupt request flag must be cleared in the peripheral. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl0_handler_isr (void) -{ - /* BL0 IS3 */ - if (1 == ICU.GRPBL0.BIT.IS3) - { - /* BSP_INT_SRC_BL0_SCI1_ERI1 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_ERI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS2 */ - if (1 == ICU.GRPBL0.BIT.IS2) - { - /* BSP_INT_SRC_BL0_SCI1_TEI1 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_TEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS11 */ - if (1 == ICU.GRPBL0.BIT.IS11) - { - /* BSP_INT_SRC_BL0_SCI5_ERI5 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_ERI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS10 */ - if (1 == ICU.GRPBL0.BIT.IS10) - { - /* BSP_INT_SRC_BL0_SCI5_TEI5 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_TEI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS13 */ - if (1 == ICU.GRPBL0.BIT.IS13) - { - /* BSP_INT_SRC_BL0_SCI6_ERI6 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_ERI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS12 */ - if (1 == ICU.GRPBL0.BIT.IS12) - { - /* BSP_INT_SRC_BL0_SCI6_TEI6 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_TEI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS17 */ - if (1 == ICU.GRPBL0.BIT.IS17) - { - /* BSP_INT_SRC_BL0_SCI12_ERI12 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_ERI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS16 */ - if (1 == ICU.GRPBL0.BIT.IS16) - { - /* BSP_INT_SRC_BL0_SCI12_TEI12 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_TEI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS118 */ - if (1 == ICU.GRPBL0.BIT.IS18) - { - /* BSP_INT_SRC_BL0_SCI12_SCIX0 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS19 */ - if (1 == ICU.GRPBL0.BIT.IS19) - { - /* BSP_INT_SRC_BL0_SCI12_SCIX1 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS20 */ - if (1 == ICU.GRPBL0.BIT.IS20) - { - /* BSP_INT_SRC_BL0_SCI12_SCIX2 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS21 */ - if (1 == ICU.GRPBL0.BIT.IS21) - { - /* BSP_INT_SRC_BL0_SCI12_SCIX3 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS26 */ - if (1 == ICU.GRPBL0.BIT.IS26) - { - /* BSP_INT_SRC_BL0_CAC_FERRI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_FERRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS27 */ - if (1 == ICU.GRPBL0.BIT.IS27) - { - /* BSP_INT_SRC_BL0_CAC_MENDI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_MENDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS28 */ - if (1 == ICU.GRPBL0.BIT.IS28) - { - /* BSP_INT_SRC_BL0_CAC_OVFI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_OVFI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL0 IS29 */ - if (1 == ICU.GRPBL0.BIT.IS29) - { - /* BSP_INT_SRC_BL0_DOC_DOPCI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL0_DOC_DOPCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } -} /* End of function group_bl0_handler_isr() */ - -/*********************************************************************************************************************** -* Function Name: group_bl1_handler_isr -* Description : Interrupt handler for Group BL1 interrupts. The way this code works is that for each possible interrupt -* in this group the following will be performed: -* 1) Test to see if an interrupt is requested for this source -* 2) If an interrupt is requested then the registered callback is called (if one is registered) -* NOTE: The interrupt request flag must be cleared in the peripheral. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl1_handler_isr (void) -{ - /* BL1 IS0 */ - if (1 == ICU.GRPBL1.BIT.IS0) - { - /* BSP_INT_SRC_BL1_POEG_POEGGAI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS1 */ - if (1 == ICU.GRPBL1.BIT.IS1) - { - /* BSP_INT_SRC_BL1_POEG_POEGGBI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS2 */ - if (1 == ICU.GRPBL1.BIT.IS2) - { - /* BSP_INT_SRC_BL1_POEG_POEGGCI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS3 */ - if (1 == ICU.GRPBL1.BIT.IS3) - { - /* BSP_INT_SRC_BL1_POEG_POEGGDI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS8 */ - if (1 == ICU.GRPBL1.BIT.IS8) - { - /* BSP_INT_SRC_BL1_POE3_OEI5 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS9 */ - if (1 == ICU.GRPBL1.BIT.IS9) - { - /* BSP_INT_SRC_BL1_POE3_OEI1 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS10 */ - if (1 == ICU.GRPBL1.BIT.IS10) - { - /* BSP_INT_SRC_BL1_POE3_OEI2 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS11 */ - if (1 == ICU.GRPBL1.BIT.IS11) - { - /* BSP_INT_SRC_BL1_POE3_OEI3 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS12 */ - if (1 == ICU.GRPBL1.BIT.IS12) - { - /* BSP_INT_SRC_BL1_POE3_OEI4 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS14 */ - if (1 == ICU.GRPBL1.BIT.IS14) - { - /* BSP_INT_SRC_BL1_RIIC0_EEI0 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_EEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS13 */ - if (1 == ICU.GRPBL1.BIT.IS13) - { - /* BSP_INT_SRC_BL1_RIIC0_TEI0 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_TEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS18 */ - if (1 == ICU.GRPBL1.BIT.IS18) - { - /* BSP_INT_SRC_BL1_S12AD2_S12CMPAI2 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD2_S12CMPAI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS19 */ - if (1 == ICU.GRPBL1.BIT.IS19) - { - /* BSP_INT_SRC_BL1_S12AD2_S12CMPBI2 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD2_S12CMPBI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS20 */ - if (1 == ICU.GRPBL1.BIT.IS20) - { - /* BSP_INT_SRC_BL1_S12AD0_S12CMPAI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS21 */ - if (1 == ICU.GRPBL1.BIT.IS21) - { - /* BSP_INT_SRC_BL1_S12AD0_S12CMPBI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS22 */ - if (1 == ICU.GRPBL1.BIT.IS22) - { - /* BSP_INT_SRC_BL1_S12AD1_S12CMPAI1 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS23 */ - if (1 == ICU.GRPBL1.BIT.IS23) - { - /* BSP_INT_SRC_BL1_S12AD1_S12CMPBI1 */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS25 */ - if (1 == ICU.GRPBL1.BIT.IS25) - { - /* BSP_INT_SRC_BL1_RSCI8_ERI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI8_ERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS24 */ - if (1 == ICU.GRPBL1.BIT.IS24) - { - /* BSP_INT_SRC_BL1_RSCI8_TEI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI8_TEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS27 */ - if (1 == ICU.GRPBL1.BIT.IS27) - { - /* BSP_INT_SRC_BL1_RSCI9_ERI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI9_ERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS26 */ - if (1 == ICU.GRPBL1.BIT.IS26) - { - /* BSP_INT_SRC_BL1_RSCI9_TEI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI9_TEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL1 IS31 */ - if (1 == ICU.GRPBL1.BIT.IS31) - { - /* BSP_INT_SRC_BL1_RSCI9_BFD */ - R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI9_BFD, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } -} /* End of function group_bl1_handler_isr() */ - -/*********************************************************************************************************************** -* Function Name: group_bl2_handler_isr -* Description : Interrupt handler for Group BL2 interrupts. The way this code works is that for each possible interrupt -* in this group the following will be performed: -* 1) Test to see if an interrupt is requested for this source -* 2) If an interrupt is requested then the registered callback is called (if one is registered) -* NOTE: The interrupt request flag must be cleared in the peripheral. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -R_BSP_ATTRIB_STATIC_INTERRUPT void group_bl2_handler_isr (void) -{ - /* BL2 IS1 */ - if (1 == ICU.GRPBL2.BIT.IS1) - { - /* BSP_INT_SRC_BL2_CANFD0_CHEI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD0_CHEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL2 IS2 */ - if (1 == ICU.GRPBL2.BIT.IS2) - { - /* BSP_INT_SRC_BL2_CANFD0_CFRI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD0_CFRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL2 IS3 */ - if (1 == ICU.GRPBL2.BIT.IS3) - { - /* BSP_INT_SRC_BL2_CANFD_GLEI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD_GLEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL2 IS4 */ - if (1 == ICU.GRPBL2.BIT.IS4) - { - /* BSP_INT_SRC_BL2_CANFD_RFRI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD_RFRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL2 IS5 */ - if (1 == ICU.GRPBL2.BIT.IS5) - { - /* BSP_INT_SRC_BL2_CANFD0_CHTI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD0_CHTI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* BL2 IS6 */ - if (1 == ICU.GRPBL2.BIT.IS6) - { - /* BSP_INT_SRC_BL2_CANFD_RMRI */ - R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD_RMRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } -} /* End of function group_bl2_handler_isr() */ - -/*********************************************************************************************************************** -* Function Name: group_al0_handler_isr -* Description : Interrupt handler for Group AL0 interrupts. The way this code works is that for each possible interrupt -* in this group the following will be performed: -* 1) Test to see if an interrupt is requested for this source -* 2) If an interrupt is requested then the registered callback is called (if one is registered) -* NOTE: The interrupt request flag must be cleared in the peripheral. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -R_BSP_ATTRIB_STATIC_INTERRUPT void group_al0_handler_isr (void) -{ - /* AL0 IS13 */ - if (1 == ICU.GRPAL0.BIT.IS13) - { - /* BSP_INT_SRC_AL0_RSCI11_ERI */ - R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSCI11_ERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* AL0 IS12 */ - if (1 == ICU.GRPAL0.BIT.IS12) - { - /* BSP_INT_SRC_AL0_RSCI11_TEI */ - R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSCI11_TEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* AL0 IS14 */ - if (1 == ICU.GRPAL0.BIT.IS14) - { - /* BSP_INT_SRC_AL0_RSCI11_BFD */ - R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSCI11_BFD, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* AL0 IS17 */ - if (1 == ICU.GRPAL0.BIT.IS17) - { - /* BSP_INT_SRC_AL0_RSPI0_SPEI0 */ - R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* AL0 IS16 */ - if (1 == ICU.GRPAL0.BIT.IS16) - { - /* BSP_INT_SRC_AL0_RSPI0_SPII0 */ - R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPII0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* AL0 IS23 */ - if (1 == ICU.GRPAL0.BIT.IS23) - { - /* BSP_INT_SRC_AL0_RSPIA0_SPEI */ - R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPIA0_SPEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } - - /* AL0 IS22 */ - if (1 == ICU.GRPAL0.BIT.IS22) - { - /* BSP_INT_SRC_AL0_RSPIA0_SPII */ - R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPIA0_SPII, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } -} /* End of function group_al0_handler_isr() */ - -/*********************************************************************************************************************** -* Function Name: group_al1_handler_isr -* Description : Interrupt handler for Group AL1 interrupts. The way this code works is that for each possible interrupt -* in this group the following will be performed: -* 1) Test to see if an interrupt is requested for this source -* 2) If an interrupt is requested then the registered callback is called (if one is registered) -* NOTE: The interrupt request flag must be cleared in the peripheral. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -R_BSP_ATTRIB_STATIC_INTERRUPT void group_al1_handler_isr (void) -{ - /* AL1 IS13 */ - if (1 == ICU.GRPAL1.BIT.IS13) - { - /* BSP_INT_SRC_AL1_RI3C0_EEI */ - R_BSP_InterruptControl(BSP_INT_SRC_AL1_RI3C0_EEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); - } -} /* End of function group_al1_handler_isr() */ - +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.c +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 21.11.2023 1.01 Added timeout detection processing to bus error processing. +* Added processing to control only illegal address access detection to bus error +* processing. +* Added processing to control only timeout detection to bus error processing. +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Access to r_bsp. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Let FPSW EV, EO, EZ, EU, EX=1 (FPU exceptions enabled.) */ +#define BSP_PRV_FPU_EXCEPTIONS_ENABLE (0x00007C00) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_interrupt_enable_disable +* Description : Either enables or disables an interrupt. +* Arguments : vector - +* Which vector to enable or disable. +* enable - +* Whether to enable or disable the interrupt. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_UNSUPPORTED - +* API does not support enabling/disabling for this vector. +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable (bsp_int_src_t vector, bool enable) +{ +#ifdef __FPU + uint32_t tmp_fpsw; +#endif + bsp_int_err_t err = BSP_INT_SUCCESS; + + switch (vector) + { + case (BSP_INT_SRC_BUS_ERROR): + if (true == enable) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU*/ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + + /* Enable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 1; + + /* Enable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 1; + } + else + { + /* Disable the bus error interrupt. */ + /* Disable the interrupt in the ICU*/ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + + /* Disable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 0; + + /* Disable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 0; + } + break; + + case (BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS): + if (true == enable) + { + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU. */ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + } + + /* Enable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 1; + } + else + { + /* Disable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 0; + + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Disable the bus error interrupt in the ICU. */ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + } + } + break; + + case (BSP_INT_SRC_BUS_ERROR_TIMEOUT): + if (true == enable) + { + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU. */ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + } + + /* Enable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 1; + } + else + { + /* Disable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 0; + + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Disable the bus error interrupt in the ICU. */ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + } + } + break; + +#ifdef __FPU + case (BSP_INT_SRC_EXC_FPU): + + /* Get current FPSW. */ + tmp_fpsw = (uint32_t)R_BSP_GET_FPSW(); + + if (true == enable) + { + /* Set the FPU exception flags. */ + R_BSP_SET_FPSW((tmp_fpsw | (uint32_t)BSP_PRV_FPU_EXCEPTIONS_ENABLE)); + } + else + { + /* Clear only the FPU exception flags. */ + R_BSP_SET_FPSW((tmp_fpsw & (uint32_t)~BSP_PRV_FPU_EXCEPTIONS_ENABLE)); + } + break; +#endif + + case (BSP_INT_SRC_EXC_NMI_PIN): + if (true == enable) + { + /* Enable NMI pin interrupt (cannot undo!) */ + ICU.NMIER.BIT.NMIEN = 1; + } + else + { + /* NMI pin interrupts cannot be disabled after being enabled. */ + err = BSP_INT_ERR_UNSUPPORTED; + } + break; + + default: + err = BSP_INT_ERR_UNSUPPORTED; + break; + } + + return err; +} /* End of function bsp_interrupt_enable_disable() */ + +/*********************************************************************************************************************** +* Function Name: group_bl0_handler_isr +* Description : Interrupt handler for Group BL0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void group_bl0_handler_isr (void) +{ + /* BL0 IS3 */ + if (1 == ICU.GRPBL0.BIT.IS3) + { + /* BSP_INT_SRC_BL0_SCI1_ERI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_ERI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS2 */ + if (1 == ICU.GRPBL0.BIT.IS2) + { + /* BSP_INT_SRC_BL0_SCI1_TEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI1_TEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS11 */ + if (1 == ICU.GRPBL0.BIT.IS11) + { + /* BSP_INT_SRC_BL0_SCI5_ERI5 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_ERI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS10 */ + if (1 == ICU.GRPBL0.BIT.IS10) + { + /* BSP_INT_SRC_BL0_SCI5_TEI5 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI5_TEI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS13 */ + if (1 == ICU.GRPBL0.BIT.IS13) + { + /* BSP_INT_SRC_BL0_SCI6_ERI6 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_ERI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS12 */ + if (1 == ICU.GRPBL0.BIT.IS12) + { + /* BSP_INT_SRC_BL0_SCI6_TEI6 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI6_TEI6, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS17 */ + if (1 == ICU.GRPBL0.BIT.IS17) + { + /* BSP_INT_SRC_BL0_SCI12_ERI12 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_ERI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS16 */ + if (1 == ICU.GRPBL0.BIT.IS16) + { + /* BSP_INT_SRC_BL0_SCI12_TEI12 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_TEI12, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS118 */ + if (1 == ICU.GRPBL0.BIT.IS18) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS19 */ + if (1 == ICU.GRPBL0.BIT.IS19) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS20 */ + if (1 == ICU.GRPBL0.BIT.IS20) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS21 */ + if (1 == ICU.GRPBL0.BIT.IS21) + { + /* BSP_INT_SRC_BL0_SCI12_SCIX3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_SCI12_SCIX3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS26 */ + if (1 == ICU.GRPBL0.BIT.IS26) + { + /* BSP_INT_SRC_BL0_CAC_FERRI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_FERRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS27 */ + if (1 == ICU.GRPBL0.BIT.IS27) + { + /* BSP_INT_SRC_BL0_CAC_MENDI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_MENDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS28 */ + if (1 == ICU.GRPBL0.BIT.IS28) + { + /* BSP_INT_SRC_BL0_CAC_OVFI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_CAC_OVFI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL0 IS29 */ + if (1 == ICU.GRPBL0.BIT.IS29) + { + /* BSP_INT_SRC_BL0_DOC_DOPCI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL0_DOC_DOPCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_bl1_handler_isr +* Description : Interrupt handler for Group BL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void group_bl1_handler_isr (void) +{ + /* BL1 IS0 */ + if (1 == ICU.GRPBL1.BIT.IS0) + { + /* BSP_INT_SRC_BL1_POEG_POEGGAI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS1 */ + if (1 == ICU.GRPBL1.BIT.IS1) + { + /* BSP_INT_SRC_BL1_POEG_POEGGBI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS2 */ + if (1 == ICU.GRPBL1.BIT.IS2) + { + /* BSP_INT_SRC_BL1_POEG_POEGGCI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGCI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS3 */ + if (1 == ICU.GRPBL1.BIT.IS3) + { + /* BSP_INT_SRC_BL1_POEG_POEGGDI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POEG_POEGGDI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS8 */ + if (1 == ICU.GRPBL1.BIT.IS8) + { + /* BSP_INT_SRC_BL1_POE3_OEI5 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI5, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS9 */ + if (1 == ICU.GRPBL1.BIT.IS9) + { + /* BSP_INT_SRC_BL1_POE3_OEI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS10 */ + if (1 == ICU.GRPBL1.BIT.IS10) + { + /* BSP_INT_SRC_BL1_POE3_OEI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS11 */ + if (1 == ICU.GRPBL1.BIT.IS11) + { + /* BSP_INT_SRC_BL1_POE3_OEI3 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI3, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS12 */ + if (1 == ICU.GRPBL1.BIT.IS12) + { + /* BSP_INT_SRC_BL1_POE3_OEI4 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_POE3_OEI4, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS14 */ + if (1 == ICU.GRPBL1.BIT.IS14) + { + /* BSP_INT_SRC_BL1_RIIC0_EEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_EEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS13 */ + if (1 == ICU.GRPBL1.BIT.IS13) + { + /* BSP_INT_SRC_BL1_RIIC0_TEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RIIC0_TEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS18 */ + if (1 == ICU.GRPBL1.BIT.IS18) + { + /* BSP_INT_SRC_BL1_S12AD2_S12CMPAI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD2_S12CMPAI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS19 */ + if (1 == ICU.GRPBL1.BIT.IS19) + { + /* BSP_INT_SRC_BL1_S12AD2_S12CMPBI2 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD2_S12CMPBI2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS20 */ + if (1 == ICU.GRPBL1.BIT.IS20) + { + /* BSP_INT_SRC_BL1_S12AD0_S12CMPAI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPAI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS21 */ + if (1 == ICU.GRPBL1.BIT.IS21) + { + /* BSP_INT_SRC_BL1_S12AD0_S12CMPBI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD0_S12CMPBI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS22 */ + if (1 == ICU.GRPBL1.BIT.IS22) + { + /* BSP_INT_SRC_BL1_S12AD1_S12CMPAI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS23 */ + if (1 == ICU.GRPBL1.BIT.IS23) + { + /* BSP_INT_SRC_BL1_S12AD1_S12CMPBI1 */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS25 */ + if (1 == ICU.GRPBL1.BIT.IS25) + { + /* BSP_INT_SRC_BL1_RSCI8_ERI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI8_ERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS24 */ + if (1 == ICU.GRPBL1.BIT.IS24) + { + /* BSP_INT_SRC_BL1_RSCI8_TEI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI8_TEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS27 */ + if (1 == ICU.GRPBL1.BIT.IS27) + { + /* BSP_INT_SRC_BL1_RSCI9_ERI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI9_ERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS26 */ + if (1 == ICU.GRPBL1.BIT.IS26) + { + /* BSP_INT_SRC_BL1_RSCI9_TEI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI9_TEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL1 IS31 */ + if (1 == ICU.GRPBL1.BIT.IS31) + { + /* BSP_INT_SRC_BL1_RSCI9_BFD */ + R_BSP_InterruptControl(BSP_INT_SRC_BL1_RSCI9_BFD, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl1_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_bl2_handler_isr +* Description : Interrupt handler for Group BL2 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void group_bl2_handler_isr (void) +{ + /* BL2 IS1 */ + if (1 == ICU.GRPBL2.BIT.IS1) + { + /* BSP_INT_SRC_BL2_CANFD0_CHEI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD0_CHEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS2 */ + if (1 == ICU.GRPBL2.BIT.IS2) + { + /* BSP_INT_SRC_BL2_CANFD0_CFRI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD0_CFRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS3 */ + if (1 == ICU.GRPBL2.BIT.IS3) + { + /* BSP_INT_SRC_BL2_CANFD_GLEI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD_GLEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS4 */ + if (1 == ICU.GRPBL2.BIT.IS4) + { + /* BSP_INT_SRC_BL2_CANFD_RFRI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD_RFRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS5 */ + if (1 == ICU.GRPBL2.BIT.IS5) + { + /* BSP_INT_SRC_BL2_CANFD0_CHTI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD0_CHTI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* BL2 IS6 */ + if (1 == ICU.GRPBL2.BIT.IS6) + { + /* BSP_INT_SRC_BL2_CANFD_RMRI */ + R_BSP_InterruptControl(BSP_INT_SRC_BL2_CANFD_RMRI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_bl2_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_al0_handler_isr +* Description : Interrupt handler for Group AL0 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void group_al0_handler_isr (void) +{ + /* AL0 IS13 */ + if (1 == ICU.GRPAL0.BIT.IS13) + { + /* BSP_INT_SRC_AL0_RSCI11_ERI */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSCI11_ERI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS12 */ + if (1 == ICU.GRPAL0.BIT.IS12) + { + /* BSP_INT_SRC_AL0_RSCI11_TEI */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSCI11_TEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS14 */ + if (1 == ICU.GRPAL0.BIT.IS14) + { + /* BSP_INT_SRC_AL0_RSCI11_BFD */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSCI11_BFD, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS17 */ + if (1 == ICU.GRPAL0.BIT.IS17) + { + /* BSP_INT_SRC_AL0_RSPI0_SPEI0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPEI0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS16 */ + if (1 == ICU.GRPAL0.BIT.IS16) + { + /* BSP_INT_SRC_AL0_RSPI0_SPII0 */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPI0_SPII0, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS23 */ + if (1 == ICU.GRPAL0.BIT.IS23) + { + /* BSP_INT_SRC_AL0_RSPIA0_SPEI */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPIA0_SPEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } + + /* AL0 IS22 */ + if (1 == ICU.GRPAL0.BIT.IS22) + { + /* BSP_INT_SRC_AL0_RSPIA0_SPII */ + R_BSP_InterruptControl(BSP_INT_SRC_AL0_RSPIA0_SPII, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_al0_handler_isr() */ + +/*********************************************************************************************************************** +* Function Name: group_al1_handler_isr +* Description : Interrupt handler for Group AL1 interrupts. The way this code works is that for each possible interrupt +* in this group the following will be performed: +* 1) Test to see if an interrupt is requested for this source +* 2) If an interrupt is requested then the registered callback is called (if one is registered) +* NOTE: The interrupt request flag must be cleared in the peripheral. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void group_al1_handler_isr (void) +{ + /* AL1 IS13 */ + if (1 == ICU.GRPAL1.BIT.IS13) + { + /* BSP_INT_SRC_AL1_RI3C0_EEI */ + R_BSP_InterruptControl(BSP_INT_SRC_AL1_RI3C0_EEI, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +} /* End of function group_al1_handler_isr() */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.h b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.h index 57923ae8..ffa3d05e 100644 --- a/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.h +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_interrupts.h @@ -1,190 +1,191 @@ -/* -* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -*/ -/*********************************************************************************************************************** -* File Name : mcu_interrupts.h -* Description : This module is the control of the interrupt enable. -***********************************************************************************************************************/ -/********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 28.02.2023 1.00 First Release -* : 21.11.2023 1.01 Added the following enumeration constant. -* - BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS -* - BSP_INT_SRC_BUS_ERROR_TIMEOUT -* : 26.02.2025 1.02 Changed the disclaimer. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -/* Multiple inclusion prevention macro */ -#ifndef MCU_INTERRUPTS_H -#define MCU_INTERRUPTS_H - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ -/* Available return codes. */ -typedef enum -{ - BSP_INT_SUCCESS = 0, - BSP_INT_ERR_NO_REGISTERED_CALLBACK, /* There is not a registered callback for this interrupt source */ - BSP_INT_ERR_INVALID_ARG, /* Illegal argument input */ - BSP_INT_ERR_UNSUPPORTED, /* Operation is not supported by this API */ - BSP_INT_ERR_GROUP_STILL_ENABLED, /* Not all group interrupts were disabled so group interrupt was not - disabled */ - BSP_INT_ERR_INVALID_IPL /* Illegal IPL value input */ -} bsp_int_err_t; - -/* Available interrupts to register a callback for. */ -typedef enum -{ - BSP_INT_SRC_EXC_SUPERVISOR_INSTR = 0, /* Occurs when privileged instruction is executed in User Mode */ - BSP_INT_SRC_EXC_UNDEFINED_INSTR, /* Occurs when MCU encounters an unknown instruction */ - BSP_INT_SRC_EXC_NMI_PIN, /* NMI Pin interrupt */ - BSP_INT_SRC_EXC_FPU, /* FPU exception */ - BSP_INT_SRC_EXC_ACCESS, /* Access exception */ - BSP_INT_SRC_OSC_STOP_DETECT, /* Oscillation stop is detected */ - BSP_INT_SRC_WDT_ERROR, /* WDT underflow/refresh error has occurred */ - BSP_INT_SRC_IWDT_ERROR, /* IWDT underflow/refresh error has occurred */ - BSP_INT_SRC_LVD1, /* Voltage monitoring 1 interrupt */ - BSP_INT_SRC_LVD2, /* Voltage monitoring 2 interrupt */ - BSP_INT_SRC_UNDEFINED_INTERRUPT, /* Interrupt has triggered for a vector that user did not write a handler. */ - BSP_INT_SRC_BUS_ERROR, /* Bus error: illegal address access or timeout */ - BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS, /* Bus error: illegal address access. Use this when you want to set only Illegal address access detection. */ - BSP_INT_SRC_BUS_ERROR_TIMEOUT, /* Bus error: timeout. Use this when you want to set only Bus timeout detection. */ - BSP_INT_SRC_RAM, /* RAM error interrupt */ - - BSP_INT_SRC_GR_INT_TOP, - - /* IE0 Group Interrupts */ - BSP_INT_SRC_GR_INT_IE0_TOP, - - /* BE0 Group Interrupts */ - BSP_INT_SRC_GR_INT_BE0_TOP, - - /* BL0 Group Interrupts. */ - BSP_INT_SRC_GR_INT_BL0_TOP, - BSP_INT_SRC_BL0_SCI1_TEI1, - BSP_INT_SRC_BL0_SCI1_ERI1, - BSP_INT_SRC_BL0_SCI5_TEI5, - BSP_INT_SRC_BL0_SCI5_ERI5, - BSP_INT_SRC_BL0_SCI6_TEI6, - BSP_INT_SRC_BL0_SCI6_ERI6, - BSP_INT_SRC_BL0_SCI12_TEI12, - BSP_INT_SRC_BL0_SCI12_ERI12, - BSP_INT_SRC_BL0_SCI12_SCIX0, - BSP_INT_SRC_BL0_SCI12_SCIX1, - BSP_INT_SRC_BL0_SCI12_SCIX2, - BSP_INT_SRC_BL0_SCI12_SCIX3, - BSP_INT_SRC_BL0_CAC_FERRI, - BSP_INT_SRC_BL0_CAC_MENDI, - BSP_INT_SRC_BL0_CAC_OVFI, - BSP_INT_SRC_BL0_DOC_DOPCI, - - /* BL1 Group Interrupts. */ - BSP_INT_SRC_GR_INT_BL1_TOP, - BSP_INT_SRC_BL1_POEG_POEGGAI, - BSP_INT_SRC_BL1_POEG_POEGGBI, - BSP_INT_SRC_BL1_POEG_POEGGCI, - BSP_INT_SRC_BL1_POEG_POEGGDI, - BSP_INT_SRC_BL1_POE3_OEI5, - BSP_INT_SRC_BL1_POE3_OEI1, - BSP_INT_SRC_BL1_POE3_OEI2, - BSP_INT_SRC_BL1_POE3_OEI3, - BSP_INT_SRC_BL1_POE3_OEI4, - BSP_INT_SRC_BL1_RIIC0_TEI0, - BSP_INT_SRC_BL1_RIIC0_EEI0, - BSP_INT_SRC_BL1_S12AD2_S12CMPAI2, - BSP_INT_SRC_BL1_S12AD2_S12CMPBI2, - BSP_INT_SRC_BL1_S12AD0_S12CMPAI, - BSP_INT_SRC_BL1_S12AD0_S12CMPBI, - BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, - BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, - BSP_INT_SRC_BL1_RSCI8_TEI, - BSP_INT_SRC_BL1_RSCI8_ERI, - BSP_INT_SRC_BL1_RSCI9_TEI, - BSP_INT_SRC_BL1_RSCI9_ERI, - BSP_INT_SRC_BL1_RSCI9_BFD, - - /* BL2 Group Interrupts. */ - BSP_INT_SRC_GR_INT_BL2_TOP, - BSP_INT_SRC_BL2_CANFD0_CHEI, - BSP_INT_SRC_BL2_CANFD0_CFRI, - BSP_INT_SRC_BL2_CANFD_GLEI, - BSP_INT_SRC_BL2_CANFD_RFRI, - BSP_INT_SRC_BL2_CANFD0_CHTI, - BSP_INT_SRC_BL2_CANFD_RMRI, - - /* AL0 Group Interrupts. */ - BSP_INT_SRC_GR_INT_AL0_TOP, - BSP_INT_SRC_AL0_RSCI11_TEI, - BSP_INT_SRC_AL0_RSCI11_ERI, - BSP_INT_SRC_AL0_RSCI11_BFD, - BSP_INT_SRC_AL0_RSPI0_SPII0, - BSP_INT_SRC_AL0_RSPI0_SPEI0, - BSP_INT_SRC_AL0_RSPIA0_SPII, - BSP_INT_SRC_AL0_RSPIA0_SPEI, - - /* AL1 Group Interrupts. */ - BSP_INT_SRC_GR_INT_AL1_TOP, - BSP_INT_SRC_AL1_RI3C0_EEI, - - BSP_INT_SRC_GR_INT_END, - BSP_INT_SRC_EMPTY, - BSP_INT_SRC_TOTAL_ITEMS /* DO NOT MODIFY! This is used for sizing the interrupt callback array. */ -} bsp_int_src_t; - -/* Available commands for R_BSP_InterruptControl() function. */ -typedef enum -{ - BSP_INT_CMD_CALL_CALLBACK = 0, /* Calls registered callback function if one exists */ - BSP_INT_CMD_INTERRUPT_ENABLE, /* Enables a given interrupt (Available for NMI pin, FPU, and Bus Error) */ - BSP_INT_CMD_INTERRUPT_DISABLE, /* Disables a given interrupt (Available for FPU, and Bus Error) */ - BSP_INT_CMD_GROUP_INTERRUPT_ENABLE, /* Enables a group interrupt when a group interrupt source is given. The - pdata argument should give the IPL to be used using the bsp_int_ctrl_t - type. If a group interrupt is enabled multiple times with different IPL - levels it will use the highest given IPL. */ - BSP_INT_CMD_GROUP_INTERRUPT_DISABLE, /* Disables a group interrupt when a group interrupt source is given. - This will only disable a group interrupt when all interrupt - sources for that group are already disabled. */ - BSP_INT_CMD_FIT_INTERRUPT_ENABLE, /* Enables interrupt by control of IPL. */ - BSP_INT_CMD_FIT_INTERRUPT_DISABLE /* Disables interrupt by control of IPL. */ -} bsp_int_cmd_t; - -/* Type to be used for pdata argument in Control function. */ -typedef union -{ - uint32_t ipl; /* Used at the following times. - - When enabling an interrupt to set that interrupt's priority level - by BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command. - - When disabling an interrupt to save that interrupt's priority level - by BSP_INT_CMD_FIT_INTERRUPT_DISABLE command. - - When enabling an interrupt to set that interrupt's priority level - by BSP_INT_CMD_FIT_INTERRUPT_ENABLE command. */ -} bsp_int_ctrl_t; - -/* Easy to use typedef for callback functions. */ -typedef void (*bsp_int_cb_t)(void *); - -/* This structure is the common one that is passed as the 'void *' argument to callback functions when an - * exception occurs. - */ -typedef struct -{ - bsp_int_src_t vector; /* Which vector caused this interrupt */ -} bsp_int_cb_args_t; - -/*********************************************************************************************************************** -Exported global variables -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Exported global functions (to be accessed by other files) -***********************************************************************************************************************/ -bsp_int_err_t bsp_interrupt_enable_disable(bsp_int_src_t vector, bool enable); - -#endif /* MCU_INTERRUPTS_H */ - +/* +* Copyright (c) 2011 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +*/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.h +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2023 1.00 First Release +* : 21.11.2023 1.01 Added the following enumeration constant. +* - BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS +* - BSP_INT_SRC_BUS_ERROR_TIMEOUT +* : 26.02.2025 1.02 Changed the disclaimer. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INTERRUPTS_H +#define MCU_INTERRUPTS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Available return codes. */ +typedef enum +{ + BSP_INT_SUCCESS = 0, + BSP_INT_ERR_NO_REGISTERED_CALLBACK, /* There is not a registered callback for this interrupt source */ + BSP_INT_ERR_INVALID_ARG, /* Illegal argument input */ + BSP_INT_ERR_UNSUPPORTED, /* Operation is not supported by this API */ + BSP_INT_ERR_GROUP_STILL_ENABLED, /* Not all group interrupts were disabled so group interrupt was not + disabled */ + BSP_INT_ERR_INVALID_IPL /* Illegal IPL value input */ +} bsp_int_err_t; + +/* Available interrupts to register a callback for. */ +typedef enum +{ + BSP_INT_SRC_EXC_SUPERVISOR_INSTR = 0, /* Occurs when privileged instruction is executed in User Mode */ + BSP_INT_SRC_EXC_UNDEFINED_INSTR, /* Occurs when MCU encounters an unknown instruction */ + BSP_INT_SRC_EXC_NMI_PIN, /* NMI Pin interrupt */ + BSP_INT_SRC_EXC_FPU, /* FPU exception */ + BSP_INT_SRC_EXC_ACCESS, /* Access exception */ + BSP_INT_SRC_OSC_STOP_DETECT, /* Oscillation stop is detected */ + BSP_INT_SRC_WDT_ERROR, /* WDT underflow/refresh error has occurred */ + BSP_INT_SRC_IWDT_ERROR, /* IWDT underflow/refresh error has occurred */ + BSP_INT_SRC_LVD1, /* Voltage monitoring 1 interrupt */ + BSP_INT_SRC_LVD2, /* Voltage monitoring 2 interrupt */ + BSP_INT_SRC_UNDEFINED_INTERRUPT, /* Interrupt has triggered for a vector that user did not write a handler. */ + BSP_INT_SRC_BUS_ERROR, /* Bus error: illegal address access or timeout */ + BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS, /* Bus error: illegal address access. Use this when you want to set only Illegal address access detection. */ + BSP_INT_SRC_BUS_ERROR_TIMEOUT, /* Bus error: timeout. Use this when you want to set only Bus timeout detection. */ + BSP_INT_SRC_RAM, /* RAM error interrupt */ + + BSP_INT_SRC_GR_INT_TOP, + + /* IE0 Group Interrupts */ + BSP_INT_SRC_GR_INT_IE0_TOP, + + /* BE0 Group Interrupts */ + BSP_INT_SRC_GR_INT_BE0_TOP, + + /* BL0 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL0_TOP, + BSP_INT_SRC_BL0_SCI1_TEI1, + BSP_INT_SRC_BL0_SCI1_ERI1, + BSP_INT_SRC_BL0_SCI5_TEI5, + BSP_INT_SRC_BL0_SCI5_ERI5, + BSP_INT_SRC_BL0_SCI6_TEI6, + BSP_INT_SRC_BL0_SCI6_ERI6, + BSP_INT_SRC_BL0_SCI12_TEI12, + BSP_INT_SRC_BL0_SCI12_ERI12, + BSP_INT_SRC_BL0_SCI12_SCIX0, + BSP_INT_SRC_BL0_SCI12_SCIX1, + BSP_INT_SRC_BL0_SCI12_SCIX2, + BSP_INT_SRC_BL0_SCI12_SCIX3, + BSP_INT_SRC_BL0_CAC_FERRI, + BSP_INT_SRC_BL0_CAC_MENDI, + BSP_INT_SRC_BL0_CAC_OVFI, + BSP_INT_SRC_BL0_DOC_DOPCI, + + /* BL1 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL1_TOP, + BSP_INT_SRC_BL1_POEG_POEGGAI, + BSP_INT_SRC_BL1_POEG_POEGGBI, + BSP_INT_SRC_BL1_POEG_POEGGCI, + BSP_INT_SRC_BL1_POEG_POEGGDI, + BSP_INT_SRC_BL1_POE3_OEI5, + BSP_INT_SRC_BL1_POE3_OEI1, + BSP_INT_SRC_BL1_POE3_OEI2, + BSP_INT_SRC_BL1_POE3_OEI3, + BSP_INT_SRC_BL1_POE3_OEI4, + BSP_INT_SRC_BL1_RIIC0_TEI0, + BSP_INT_SRC_BL1_RIIC0_EEI0, + BSP_INT_SRC_BL1_S12AD2_S12CMPAI2, + BSP_INT_SRC_BL1_S12AD2_S12CMPBI2, + BSP_INT_SRC_BL1_S12AD0_S12CMPAI, + BSP_INT_SRC_BL1_S12AD0_S12CMPBI, + BSP_INT_SRC_BL1_S12AD1_S12CMPAI1, + BSP_INT_SRC_BL1_S12AD1_S12CMPBI1, + BSP_INT_SRC_BL1_RSCI8_TEI, + BSP_INT_SRC_BL1_RSCI8_ERI, + BSP_INT_SRC_BL1_RSCI9_TEI, + BSP_INT_SRC_BL1_RSCI9_ERI, + BSP_INT_SRC_BL1_RSCI9_BFD, + + /* BL2 Group Interrupts. */ + BSP_INT_SRC_GR_INT_BL2_TOP, + BSP_INT_SRC_BL2_CANFD0_CHEI, + BSP_INT_SRC_BL2_CANFD0_CFRI, + BSP_INT_SRC_BL2_CANFD_GLEI, + BSP_INT_SRC_BL2_CANFD_RFRI, + BSP_INT_SRC_BL2_CANFD0_CHTI, + BSP_INT_SRC_BL2_CANFD_RMRI, + + /* AL0 Group Interrupts. */ + BSP_INT_SRC_GR_INT_AL0_TOP, + BSP_INT_SRC_AL0_RSCI11_TEI, + BSP_INT_SRC_AL0_RSCI11_ERI, + BSP_INT_SRC_AL0_RSCI11_BFD, + BSP_INT_SRC_AL0_RSPI0_SPII0, + BSP_INT_SRC_AL0_RSPI0_SPEI0, + BSP_INT_SRC_AL0_RSPIA0_SPII, + BSP_INT_SRC_AL0_RSPIA0_SPEI, + + /* AL1 Group Interrupts. */ + BSP_INT_SRC_GR_INT_AL1_TOP, + BSP_INT_SRC_AL1_RI3C0_EEI, + + BSP_INT_SRC_GR_INT_END, + BSP_INT_SRC_EMPTY, + BSP_INT_SRC_TOTAL_ITEMS /* DO NOT MODIFY! This is used for sizing the interrupt callback array. */ +} bsp_int_src_t; + +/* Available commands for R_BSP_InterruptControl() function. */ +typedef enum +{ + BSP_INT_CMD_CALL_CALLBACK = 0, /* Calls registered callback function if one exists */ + BSP_INT_CMD_INTERRUPT_ENABLE, /* Enables a given interrupt (Available for NMI pin, FPU, and Bus Error) */ + BSP_INT_CMD_INTERRUPT_DISABLE, /* Disables a given interrupt (Available for FPU, and Bus Error) */ + BSP_INT_CMD_GROUP_INTERRUPT_ENABLE, /* Enables a group interrupt when a group interrupt source is given. The + pdata argument should give the IPL to be used using the bsp_int_ctrl_t + type. If a group interrupt is enabled multiple times with different IPL + levels it will use the highest given IPL. */ + BSP_INT_CMD_GROUP_INTERRUPT_DISABLE, /* Disables a group interrupt when a group interrupt source is given. + This will only disable a group interrupt when all interrupt + sources for that group are already disabled. */ + BSP_INT_CMD_FIT_INTERRUPT_ENABLE, /* Enables interrupt by control of IPL. */ + BSP_INT_CMD_FIT_INTERRUPT_DISABLE /* Disables interrupt by control of IPL. */ +} bsp_int_cmd_t; + +/* Type to be used for pdata argument in Control function. */ +typedef union +{ + uint32_t ipl; /* Used at the following times. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command. + - When disabling an interrupt to save that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_DISABLE command. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_ENABLE command. */ +} bsp_int_ctrl_t; + +/* Easy to use typedef for callback functions. */ +typedef void (*bsp_int_cb_t)(void *); + +/* This structure is the common one that is passed as the 'void *' argument to callback functions when an + * exception occurs. + */ +typedef struct +{ + bsp_int_src_t vector; /* Which vector caused this interrupt */ + void *p_context; /* Pointer to the callback function's argument */ +} bsp_int_cb_args_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable(bsp_int_src_t vector, bool enable); + +#endif /* MCU_INTERRUPTS_H */ + diff --git a/zephyr/rx/rdp_cfg/r_config/r_sci_rx_config.h b/zephyr/rx/rdp_cfg/r_config/r_sci_rx_config.h index 7d2d0315..1388ebe6 100644 --- a/zephyr/rx/rdp_cfg/r_config/r_sci_rx_config.h +++ b/zephyr/rx/rdp_cfg/r_config/r_sci_rx_config.h @@ -1,371 +1,371 @@ -/*********************************************************************************************************************** -* Copyright (c) 2013 - 2025 Renesas Electronics Corporation and/or its affiliates -* -* SPDX-License-Identifier: BSD-3-Clause -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* File Name : r_sci_rx_config.h -* Description : Configures the SCI driver -************************************************************************************************************************ -* History : DD.MM.YYYY Version Description -* 25.09.2013 1.00 Initial Release -* 17.04.2014 1.20 Added comments for new RX110 support. -* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. -* 25.11.2014 1.40 Added comments for RX113 support -* 30.09.2015 1.70 Added comments for RX23T support -* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) -* 19.12.2016 1.90 Added comments for RX24U support -* 07.03.2017 2.00 Added comments for RX130-512KB support -* 28.09.2018 2.10 Added comments for RX66T support -* 01.02.2019 2.20 Added comments for RX72T, RX65N-64pin support -* Added support received data match function for RX65N -* 28.06.2019 3.10 Added comments for RX23W support -* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0- SCI11) -* Added support FIFO mode for RX72M (SCI7 - SCI11) -* 25.11.2019 3.30 Added support RX13T. -* Removed support for Generation 1 devices. -* 30.12.2019 3.40 Added support RX66N, RX72N. -* 31.03.2020 3.50 Added support RX23E-A. -* 25.08.2020 3.60 Added feature using DTC/DMAC in SCI transfer. -* Merged IrDA functionality to SCI FIT. -* 31.03.2021 3.80 Added support for RX671. -* Added support circular buffer in mode asynchronous. -* 15.04.2021 3.90 Added support for RX140. -* 31.03.2022 4.40 Added support for RX660. -* 27.12.2022 4.60 Updated macro definition enable and disable nested interrupt for TXI, RXI, ERI, TEI. -* 31.03.2023 4.80 Added support for RX26T. -* Fixed to comply with GSCE Coding Standards Rev.6.5.0. -* 29.05.2023 4.90 Added support for RX23E-B. -* 31.01.2024 5.10 Modified comments in Data Match parameters. -* 28.06.2024 5.30 Added support for RX260, RX261. -* 15.03.2025 5.41 Updated disclaimer -***********************************************************************************************************************/ -#ifndef SCI_CONFIG_H -#define SCI_CONFIG_H - -#include -#include "platform.h" - -/*********************************************************************************************************************** -Configuration Options -***********************************************************************************************************************/ - -/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */ -/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */ -/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */ -#define SCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) - -/* SPECIFY WHETHER TO INCLUDE CODE FOR DIFFERENT SCI MODES */ -/* Setting an equate to 1 includes code specific to that mode. */ -#define SCI_CFG_ASYNC_INCLUDED (CONFIG_USE_RX_RDP_SCI_UART) -#define SCI_CFG_SYNC_INCLUDED (0) -#define SCI_CFG_SSPI_INCLUDED (0) -#define SCI_CFG_IRDA_INCLUDED (0) - -/* Use circular buffer in mode asynchronous */ -/* 1=Use , 0=Unused */ -/* When SCI_CFG_USE_CIRCULAR is 1, please set BSP_CFG_RUN_IN_USER_MODE = 0 and BYTEQ_CFG_PROTECT_QUEUE = 1*/ -#define SCI_CFG_USE_CIRCULAR_BUFFER (0) - -/* SPECIFY BYTE VALUE TO TRANSMIT WHILE CLOCKING IN DATA IN SSPI MODES */ -#define SCI_CFG_DUMMY_TX_BYTE (0xFF) - -/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */ -/* - * NOTE: If using ASYNC mode, adjust BYTEQ_CFG_MAX_CTRL_BLKS in r_byteq_config.h - * to provide 2 queues per channel (static mode only). - * * = port connector RSKRX11x - * u = channel used by the USB-UART port (G1CUSB0) - * a = this channel is used only for RX130-512KB - * n = this channel is not available for RX65N-64pin. - * s = this channel is not available in simple SPI mode. - * i = this channel is available in IrDA interface. - * RX MCU supported channels - * - * CH# 110 111 113 130 140 230 231 23T 24T 24U 64M 71M 65N 66T 72T 23W 72M 13T 72N 66N 23E-A 671 660 26T 23E-B 260 261 - * --- --- --- --- --- --- --- ----- --- --- --- --- --- --- --- --- --- --- --- --- --- ----- --- --- --- ----- --- --- - * CH0 X Xa X X X X Xn X X X X X X - * CH1 X X* X* Xu X X X Xu Xu Xu X X Xs X X X X X X X Xu X X X X X X - * CH2 X X X Xu X X X X X - * CH3 X X Xs X X X X X - * CH4 X X Xn X X X X X - * CH5 X X Xi X X Xi Xu,i X X X X X X X X Xi X X X X X X X X X X X - * CH6 X X X X X X X X X Xn X X Xu X X X X X X X X X - * CH7 Xu Xu Xn X X X X X - * CH8 X Xa X X X X X X X Xu X X X X X X - * CH9 X Xa X X X X Xs X X X X X X X X - * CH10 X X X X X X - * CH11 X Xs X X X X X X X - * CH12 X X X X X X X X X Xs X X X X X X X X X X X X X X -*/ - -#define SCI_CFG_CH0_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci0), okay)) -#define SCI_CFG_CH1_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci1), okay)) -#define SCI_CFG_CH2_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci2), okay)) -#define SCI_CFG_CH3_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci3), okay)) -#define SCI_CFG_CH4_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci4), okay)) -#define SCI_CFG_CH5_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci5), okay)) -#define SCI_CFG_CH6_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci6), okay)) -#define SCI_CFG_CH7_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci7), okay)) -#define SCI_CFG_CH8_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci8), okay)) -#define SCI_CFG_CH9_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci9), okay)) -#define SCI_CFG_CH10_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci10), okay)) -#define SCI_CFG_CH11_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci11), okay)) -#define SCI_CFG_CH12_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci12), okay)) - -/* SPECIFY WHETHER TO INCLUDE CODE FOR NESTED INTERRUPT TXI */ -/* 1=included, 0=not */ -#define SCI_CFG_CH0_EN_TXI_NESTED_INT (0) -#define SCI_CFG_CH1_EN_TXI_NESTED_INT (0) -#define SCI_CFG_CH2_EN_TXI_NESTED_INT (0) -#define SCI_CFG_CH3_EN_TXI_NESTED_INT (0) -#define SCI_CFG_CH4_EN_TXI_NESTED_INT (0) -#define SCI_CFG_CH5_EN_TXI_NESTED_INT (0) -#define SCI_CFG_CH6_EN_TXI_NESTED_INT (0) -#define SCI_CFG_CH7_EN_TXI_NESTED_INT (0) -#define SCI_CFG_CH8_EN_TXI_NESTED_INT (0) -#define SCI_CFG_CH9_EN_TXI_NESTED_INT (0) -#define SCI_CFG_CH10_EN_TXI_NESTED_INT (0) -#define SCI_CFG_CH11_EN_TXI_NESTED_INT (0) -#define SCI_CFG_CH12_EN_TXI_NESTED_INT (0) - -/* SPECIFY WHETHER TO INCLUDE CODE FOR NESTED INTERRUPT RXI */ -/* 1=included, 0=not */ -#define SCI_CFG_CH0_EN_RXI_NESTED_INT (0) -#define SCI_CFG_CH1_EN_RXI_NESTED_INT (0) -#define SCI_CFG_CH2_EN_RXI_NESTED_INT (0) -#define SCI_CFG_CH3_EN_RXI_NESTED_INT (0) -#define SCI_CFG_CH4_EN_RXI_NESTED_INT (0) -#define SCI_CFG_CH5_EN_RXI_NESTED_INT (0) -#define SCI_CFG_CH6_EN_RXI_NESTED_INT (0) -#define SCI_CFG_CH7_EN_RXI_NESTED_INT (0) -#define SCI_CFG_CH8_EN_RXI_NESTED_INT (0) -#define SCI_CFG_CH9_EN_RXI_NESTED_INT (0) -#define SCI_CFG_CH10_EN_RXI_NESTED_INT (0) -#define SCI_CFG_CH11_EN_RXI_NESTED_INT (0) -#define SCI_CFG_CH12_EN_RXI_NESTED_INT (0) - -/* SPECIFY WHETHER TO INCLUDE CODE FOR NESTED INTERRUPT TEI */ -/* 1=included, 0=not */ -#define SCI_CFG_CH0_EN_TEI_NESTED_INT (0) -#define SCI_CFG_CH1_EN_TEI_NESTED_INT (0) -#define SCI_CFG_CH2_EN_TEI_NESTED_INT (0) -#define SCI_CFG_CH3_EN_TEI_NESTED_INT (0) -#define SCI_CFG_CH4_EN_TEI_NESTED_INT (0) -#define SCI_CFG_CH5_EN_TEI_NESTED_INT (0) -#define SCI_CFG_CH6_EN_TEI_NESTED_INT (0) -#define SCI_CFG_CH7_EN_TEI_NESTED_INT (0) -#define SCI_CFG_CH8_EN_TEI_NESTED_INT (0) -#define SCI_CFG_CH9_EN_TEI_NESTED_INT (0) -#define SCI_CFG_CH10_EN_TEI_NESTED_INT (0) -#define SCI_CFG_CH11_EN_TEI_NESTED_INT (0) -#define SCI_CFG_CH12_EN_TEI_NESTED_INT (0) - -/* SPECIFY WHETHER TO INCLUDE CODE FOR NESTED INTERRUPT ERI */ -/* 1=included, 0=not */ -#define SCI_CFG_CH0_EN_ERI_NESTED_INT (0) -#define SCI_CFG_CH1_EN_ERI_NESTED_INT (0) -#define SCI_CFG_CH2_EN_ERI_NESTED_INT (0) -#define SCI_CFG_CH3_EN_ERI_NESTED_INT (0) -#define SCI_CFG_CH4_EN_ERI_NESTED_INT (0) -#define SCI_CFG_CH5_EN_ERI_NESTED_INT (0) -#define SCI_CFG_CH6_EN_ERI_NESTED_INT (0) -#define SCI_CFG_CH7_EN_ERI_NESTED_INT (0) -#define SCI_CFG_CH8_EN_ERI_NESTED_INT (0) -#define SCI_CFG_CH9_EN_ERI_NESTED_INT (0) -#define SCI_CFG_CH10_EN_ERI_NESTED_INT (0) -#define SCI_CFG_CH11_EN_ERI_NESTED_INT (0) -#define SCI_CFG_CH12_EN_ERI_NESTED_INT (0) - -/* SPECIFY ASYNC MODE TX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ -#define SCI_CFG_CH0_TX_BUFSIZ (80) -#define SCI_CFG_CH1_TX_BUFSIZ (80) -#define SCI_CFG_CH2_TX_BUFSIZ (80) -#define SCI_CFG_CH3_TX_BUFSIZ (80) -#define SCI_CFG_CH4_TX_BUFSIZ (80) -#define SCI_CFG_CH5_TX_BUFSIZ (80) -#define SCI_CFG_CH6_TX_BUFSIZ (80) -#define SCI_CFG_CH7_TX_BUFSIZ (80) -#define SCI_CFG_CH8_TX_BUFSIZ (80) -#define SCI_CFG_CH9_TX_BUFSIZ (80) -#define SCI_CFG_CH10_TX_BUFSIZ (80) -#define SCI_CFG_CH11_TX_BUFSIZ (80) -#define SCI_CFG_CH12_TX_BUFSIZ (80) - -/* SPECIFY ASYNC MODE RX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ -#define SCI_CFG_CH0_RX_BUFSIZ (80) -#define SCI_CFG_CH1_RX_BUFSIZ (80) -#define SCI_CFG_CH2_RX_BUFSIZ (80) -#define SCI_CFG_CH3_RX_BUFSIZ (80) -#define SCI_CFG_CH4_RX_BUFSIZ (80) -#define SCI_CFG_CH5_RX_BUFSIZ (80) -#define SCI_CFG_CH6_RX_BUFSIZ (80) -#define SCI_CFG_CH7_RX_BUFSIZ (80) -#define SCI_CFG_CH8_RX_BUFSIZ (80) -#define SCI_CFG_CH9_RX_BUFSIZ (80) -#define SCI_CFG_CH10_RX_BUFSIZ (80) -#define SCI_CFG_CH11_RX_BUFSIZ (80) -#define SCI_CFG_CH12_RX_BUFSIZ (80) - -/* -* ENABLE TRANSMIT END INTERRUPT (ASYNCHRONOUS) -* This interrupt only occurs when the last bit of the last byte of data -* has been sent and the transmitter has become idle. The interrupt calls -* the user's callback function specified in R_SCI_Open() and passes it an -* SCI_EVT_TEI event. A typical use of this feature is to disable an external -* transceiver to save power. It would then be up to the user's code to -* re-enable the transceiver before sending again. Not including this feature -* reduces code space used by the interrupt. Note that this equate is only -* for including the TEI code. The interrupt itself must be enabled using an -* R_SCI_Control(hdl, SCI_CMD_EN_TEI, NULL) call. -*/ -#define SCI_CFG_TEI_INCLUDED (CONFIG_USE_RX_RDP_SCI_UART) /* 1=included, 0=not */ - -/* -* SET GROUPBL0 (ERI, TEI) INTERRUPT PRIORITY; RX64M/RX71M/RX65N/RX72M/RX72N/RX66N/RX671/RX660/RX26T ONLY -* SET GROUPBL1; RX65N ONLY -* SET GROUPAL0 (ERI,TEI) INTERRUPT PRIORITY; RX65N, RX72M, RX72N, RX66N ONLY -* This sets the priority level for receiver overrun, framing, and parity errors -* as well as TEI interrupts for all SCI channels. -*/ -/* (RX64M/RX71M/RX65N/RX72M/RX72N/RX66N/RX671/RX660/RX26T ONLY) 1 lowest, 15 highest */ -#define SCI_CFG_ERI_TEI_PRIORITY (3) - -/* ENABLE TX/RX FIFO; (SCIi supported MCU ONLY) 1=included, 0=not */ -#define SCI_CFG_CH7_FIFO_INCLUDED (0) -#define SCI_CFG_CH8_FIFO_INCLUDED (0) -#define SCI_CFG_CH9_FIFO_INCLUDED (0) -#define SCI_CFG_CH10_FIFO_INCLUDED (0) -#define SCI_CFG_CH11_FIFO_INCLUDED (0) - -/* SET TX FIFO THRESHOLD; (SCIi supported MCU ONLY) 0 lowest, 15 highest */ -/* TX FIFO THRESHOLD is invalid in Clock Synchronous Mode and Simple SPI Mode. */ -/* Set the same value for TX FIFO THRESHOLD and RX FIFO THRESHOLD in Clock Synchronous Mode and Simple SPI Mode. */ -#define SCI_CFG_CH7_TX_FIFO_THRESH (8) -#define SCI_CFG_CH8_TX_FIFO_THRESH (8) -#define SCI_CFG_CH9_TX_FIFO_THRESH (8) -#define SCI_CFG_CH10_TX_FIFO_THRESH (8) -#define SCI_CFG_CH11_TX_FIFO_THRESH (8) - -/* SET RX FIFO THRESHOLD; (SCIi supported MCU ONLY) 1 lowest, 15 highest */ -#define SCI_CFG_CH7_RX_FIFO_THRESH (8) -#define SCI_CFG_CH8_RX_FIFO_THRESH (8) -#define SCI_CFG_CH9_RX_FIFO_THRESH (8) -#define SCI_CFG_CH10_RX_FIFO_THRESH (8) -#define SCI_CFG_CH11_RX_FIFO_THRESH (8) - -/* ENABLE Received Data match function (SCIj supported MCU RX66T/RX72T/RX72M/RX72N/RX66N ONLY) 1=included, 0=not */ -/*(SCIi supported MCU RX65N/RX66T/RX72T/RX72M/RX72N/RX66N ONLY) 1=included, 0=not */ -/*(SCIk supported MCU RX671/RX660/RX140/RX26T/RX260/RX261 ONLY) 1=included, 0=not */ -/*(SCIm supported MCU RX671/RX660 ONLY) 1=included, 0=not */ -#define SCI_CFG_CH0_DATA_MATCH_INCLUDED (0) -#define SCI_CFG_CH1_DATA_MATCH_INCLUDED (0) -#define SCI_CFG_CH2_DATA_MATCH_INCLUDED (0) -#define SCI_CFG_CH3_DATA_MATCH_INCLUDED (0) -#define SCI_CFG_CH4_DATA_MATCH_INCLUDED (0) -#define SCI_CFG_CH5_DATA_MATCH_INCLUDED (0) -#define SCI_CFG_CH6_DATA_MATCH_INCLUDED (0) -#define SCI_CFG_CH7_DATA_MATCH_INCLUDED (0) -#define SCI_CFG_CH8_DATA_MATCH_INCLUDED (0) -#define SCI_CFG_CH9_DATA_MATCH_INCLUDED (0) -#define SCI_CFG_CH10_DATA_MATCH_INCLUDED (0) -#define SCI_CFG_CH11_DATA_MATCH_INCLUDED (0) - -/* 0=Disable, 1=DTC, 2=DMAC */ -#define SCI_CFG_CH0_TX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH1_TX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH2_TX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH3_TX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH4_TX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH5_TX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH6_TX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH7_TX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH8_TX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH9_TX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH10_TX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH11_TX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH12_TX_DTC_DMACA_ENABLE (0) - -#define SCI_CFG_CH0_RX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH1_RX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH2_RX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH3_RX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH4_RX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH5_RX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH6_RX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH7_RX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH8_RX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH9_RX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH10_RX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH11_RX_DTC_DMACA_ENABLE (0) -#define SCI_CFG_CH12_RX_DTC_DMACA_ENABLE (0) - -/* 0~7 8 channels dmac, but maximum of SCI channel is 13 channel => cost 13*2 = 26 dmac channels in case all of sci channels run simultaneously */ -#define SCI_CFG_CH0_TX_DMACA_CH_NUM (0) -#define SCI_CFG_CH1_TX_DMACA_CH_NUM (0) -#define SCI_CFG_CH2_TX_DMACA_CH_NUM (0) -#define SCI_CFG_CH3_TX_DMACA_CH_NUM (0) -#define SCI_CFG_CH4_TX_DMACA_CH_NUM (0) -#define SCI_CFG_CH5_TX_DMACA_CH_NUM (0) -#define SCI_CFG_CH6_TX_DMACA_CH_NUM (0) -#define SCI_CFG_CH7_TX_DMACA_CH_NUM (0) -#define SCI_CFG_CH8_TX_DMACA_CH_NUM (0) -#define SCI_CFG_CH9_TX_DMACA_CH_NUM (0) -#define SCI_CFG_CH10_TX_DMACA_CH_NUM (0) -#define SCI_CFG_CH11_TX_DMACA_CH_NUM (0) -#define SCI_CFG_CH12_TX_DMACA_CH_NUM (0) - -#define SCI_CFG_CH0_RX_DMACA_CH_NUM (1) -#define SCI_CFG_CH1_RX_DMACA_CH_NUM (1) -#define SCI_CFG_CH2_RX_DMACA_CH_NUM (1) -#define SCI_CFG_CH3_RX_DMACA_CH_NUM (1) -#define SCI_CFG_CH4_RX_DMACA_CH_NUM (1) -#define SCI_CFG_CH5_RX_DMACA_CH_NUM (1) -#define SCI_CFG_CH6_RX_DMACA_CH_NUM (1) -#define SCI_CFG_CH7_RX_DMACA_CH_NUM (1) -#define SCI_CFG_CH8_RX_DMACA_CH_NUM (1) -#define SCI_CFG_CH9_RX_DMACA_CH_NUM (1) -#define SCI_CFG_CH10_RX_DMACA_CH_NUM (1) -#define SCI_CFG_CH11_RX_DMACA_CH_NUM (1) -#define SCI_CFG_CH12_RX_DMACA_CH_NUM (1) - -/* Set enable/ disable transmit signal transition timing adjust feature for each channel*/ -#define SCI_CFG_CH0_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) -#define SCI_CFG_CH1_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) -#define SCI_CFG_CH2_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) -#define SCI_CFG_CH3_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) -#define SCI_CFG_CH4_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) -#define SCI_CFG_CH5_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) -#define SCI_CFG_CH6_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) -#define SCI_CFG_CH7_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) -#define SCI_CFG_CH8_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) -#define SCI_CFG_CH9_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) -#define SCI_CFG_CH10_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) -#define SCI_CFG_CH11_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) - -/* Set enable/ disable receive data sampling timing adjust feature for each channel*/ -#define SCI_CFG_CH0_RX_DATA_SAMPLING_TIMING_INCLUDED (0) -#define SCI_CFG_CH1_RX_DATA_SAMPLING_TIMING_INCLUDED (0) -#define SCI_CFG_CH2_RX_DATA_SAMPLING_TIMING_INCLUDED (0) -#define SCI_CFG_CH3_RX_DATA_SAMPLING_TIMING_INCLUDED (0) -#define SCI_CFG_CH4_RX_DATA_SAMPLING_TIMING_INCLUDED (0) -#define SCI_CFG_CH5_RX_DATA_SAMPLING_TIMING_INCLUDED (0) -#define SCI_CFG_CH6_RX_DATA_SAMPLING_TIMING_INCLUDED (0) -#define SCI_CFG_CH7_RX_DATA_SAMPLING_TIMING_INCLUDED (0) -#define SCI_CFG_CH8_RX_DATA_SAMPLING_TIMING_INCLUDED (0) -#define SCI_CFG_CH9_RX_DATA_SAMPLING_TIMING_INCLUDED (0) -#define SCI_CFG_CH10_RX_DATA_SAMPLING_TIMING_INCLUDED (0) -#define SCI_CFG_CH11_RX_DATA_SAMPLING_TIMING_INCLUDED (0) - -/* SPECIFY IRDA CHANNELS TO INCLUDE SOFTWARE (SUPPORTED MCU RX113/RX23W/RX231/RX230 ONLY) 1=included, 0=not */ -#define SCI_CFG_CH5_IRDA_INCLUDED (0) - -/* Set the non-active level of the TXD pin */ -/* 1=High , 0=Low */ -#define SCI_CFG_CH5_IRDA_IRTXD_INACTIVE_LEVEL (0) - -/* Set the non-active level of the RXD pin */ -/* 1=High , 0=Low */ -#define SCI_CFG_CH5_IRDA_IRRXD_INACTIVE_LEVEL (0) - -#endif /* SCI_CONFIG_H */ +/*********************************************************************************************************************** +* Copyright (c) 2013 - 2025 Renesas Electronics Corporation and/or its affiliates +* +* SPDX-License-Identifier: BSD-3-Clause +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_config.h +* Description : Configures the SCI driver +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.09.2013 1.00 Initial Release +* 17.04.2014 1.20 Added comments for new RX110 support. +* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. +* 25.11.2014 1.40 Added comments for RX113 support +* 30.09.2015 1.70 Added comments for RX23T support +* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) +* 19.12.2016 1.90 Added comments for RX24U support +* 07.03.2017 2.00 Added comments for RX130-512KB support +* 28.09.2018 2.10 Added comments for RX66T support +* 01.02.2019 2.20 Added comments for RX72T, RX65N-64pin support +* Added support received data match function for RX65N +* 28.06.2019 3.10 Added comments for RX23W support +* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0- SCI11) +* Added support FIFO mode for RX72M (SCI7 - SCI11) +* 25.11.2019 3.30 Added support RX13T. +* Removed support for Generation 1 devices. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +* 25.08.2020 3.60 Added feature using DTC/DMAC in SCI transfer. +* Merged IrDA functionality to SCI FIT. +* 31.03.2021 3.80 Added support for RX671. +* Added support circular buffer in mode asynchronous. +* 15.04.2021 3.90 Added support for RX140. +* 31.03.2022 4.40 Added support for RX660. +* 27.12.2022 4.60 Updated macro definition enable and disable nested interrupt for TXI, RXI, ERI, TEI. +* 31.03.2023 4.80 Added support for RX26T. +* Fixed to comply with GSCE Coding Standards Rev.6.5.0. +* 29.05.2023 4.90 Added support for RX23E-B. +* 31.01.2024 5.10 Modified comments in Data Match parameters. +* 28.06.2024 5.30 Added support for RX260, RX261. +* 15.03.2025 5.41 Updated disclaimer +***********************************************************************************************************************/ +#ifndef SCI_CONFIG_H +#define SCI_CONFIG_H + +#include +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */ +/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */ +/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */ +#define SCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR DIFFERENT SCI MODES */ +/* Setting an equate to 1 includes code specific to that mode. */ +#define SCI_CFG_ASYNC_INCLUDED (CONFIG_USE_RX_RDP_SCI_UART) +#define SCI_CFG_SYNC_INCLUDED (0) +#define SCI_CFG_SSPI_INCLUDED (0) +#define SCI_CFG_IRDA_INCLUDED (0) + +/* Use circular buffer in mode asynchronous */ +/* 1=Use , 0=Unused */ +/* When SCI_CFG_USE_CIRCULAR is 1, please set BSP_CFG_RUN_IN_USER_MODE = 0 and BYTEQ_CFG_PROTECT_QUEUE = 1*/ +#define SCI_CFG_USE_CIRCULAR_BUFFER (0) + +/* SPECIFY BYTE VALUE TO TRANSMIT WHILE CLOCKING IN DATA IN SSPI MODES */ +#define SCI_CFG_DUMMY_TX_BYTE (0xFF) + +/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */ +/* + * NOTE: If using ASYNC mode, adjust BYTEQ_CFG_MAX_CTRL_BLKS in r_byteq_config.h + * to provide 2 queues per channel (static mode only). + * * = port connector RSKRX11x + * u = channel used by the USB-UART port (G1CUSB0) + * a = this channel is used only for RX130-512KB + * n = this channel is not available for RX65N-64pin. + * s = this channel is not available in simple SPI mode. + * i = this channel is available in IrDA interface. + * RX MCU supported channels + * + * CH# 110 111 113 130 140 230 231 23T 24T 24U 64M 71M 65N 66T 72T 23W 72M 13T 72N 66N 23E-A 671 660 26T 23E-B 260 261 + * --- --- --- --- --- --- --- ----- --- --- --- --- --- --- --- --- --- --- --- --- --- ----- --- --- --- ----- --- --- + * CH0 X Xa X X X X Xn X X X X X X + * CH1 X X* X* Xu X X X Xu Xu Xu X X Xs X X X X X X X Xu X X X X X X + * CH2 X X X Xu X X X X X + * CH3 X X Xs X X X X X + * CH4 X X Xn X X X X X + * CH5 X X Xi X X Xi Xu,i X X X X X X X X Xi X X X X X X X X X X X + * CH6 X X X X X X X X X Xn X X Xu X X X X X X X X X + * CH7 Xu Xu Xn X X X X X + * CH8 X Xa X X X X X X X Xu X X X X X X + * CH9 X Xa X X X X Xs X X X X X X X X + * CH10 X X X X X X + * CH11 X Xs X X X X X X X + * CH12 X X X X X X X X X Xs X X X X X X X X X X X X X X +*/ + +#define SCI_CFG_CH0_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci0), okay)) +#define SCI_CFG_CH1_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci1), okay)) +#define SCI_CFG_CH2_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci2), okay)) +#define SCI_CFG_CH3_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci3), okay)) +#define SCI_CFG_CH4_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci4), okay)) +#define SCI_CFG_CH5_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci5), okay)) +#define SCI_CFG_CH6_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci6), okay)) +#define SCI_CFG_CH7_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci7), okay)) +#define SCI_CFG_CH8_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci8), okay)) +#define SCI_CFG_CH9_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci9), okay)) +#define SCI_CFG_CH10_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci10), okay)) +#define SCI_CFG_CH11_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci11), okay)) +#define SCI_CFG_CH12_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci12), okay)) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR NESTED INTERRUPT TXI */ +/* 1=included, 0=not */ +#define SCI_CFG_CH0_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH1_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH2_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH3_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH4_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH5_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH6_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH7_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH8_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH9_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH10_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH11_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH12_EN_TXI_NESTED_INT (0) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR NESTED INTERRUPT RXI */ +/* 1=included, 0=not */ +#define SCI_CFG_CH0_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH1_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH2_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH3_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH4_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH5_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH6_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH7_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH8_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH9_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH10_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH11_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH12_EN_RXI_NESTED_INT (0) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR NESTED INTERRUPT TEI */ +/* 1=included, 0=not */ +#define SCI_CFG_CH0_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH1_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH2_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH3_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH4_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH5_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH6_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH7_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH8_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH9_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH10_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH11_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH12_EN_TEI_NESTED_INT (0) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR NESTED INTERRUPT ERI */ +/* 1=included, 0=not */ +#define SCI_CFG_CH0_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH1_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH2_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH3_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH4_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH5_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH6_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH7_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH8_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH9_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH10_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH11_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH12_EN_ERI_NESTED_INT (0) + +/* SPECIFY ASYNC MODE TX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_TX_BUFSIZ (80) +#define SCI_CFG_CH1_TX_BUFSIZ (80) +#define SCI_CFG_CH2_TX_BUFSIZ (80) +#define SCI_CFG_CH3_TX_BUFSIZ (80) +#define SCI_CFG_CH4_TX_BUFSIZ (80) +#define SCI_CFG_CH5_TX_BUFSIZ (80) +#define SCI_CFG_CH6_TX_BUFSIZ (80) +#define SCI_CFG_CH7_TX_BUFSIZ (80) +#define SCI_CFG_CH8_TX_BUFSIZ (80) +#define SCI_CFG_CH9_TX_BUFSIZ (80) +#define SCI_CFG_CH10_TX_BUFSIZ (80) +#define SCI_CFG_CH11_TX_BUFSIZ (80) +#define SCI_CFG_CH12_TX_BUFSIZ (80) + +/* SPECIFY ASYNC MODE RX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_RX_BUFSIZ (80) +#define SCI_CFG_CH1_RX_BUFSIZ (80) +#define SCI_CFG_CH2_RX_BUFSIZ (80) +#define SCI_CFG_CH3_RX_BUFSIZ (80) +#define SCI_CFG_CH4_RX_BUFSIZ (80) +#define SCI_CFG_CH5_RX_BUFSIZ (80) +#define SCI_CFG_CH6_RX_BUFSIZ (80) +#define SCI_CFG_CH7_RX_BUFSIZ (80) +#define SCI_CFG_CH8_RX_BUFSIZ (80) +#define SCI_CFG_CH9_RX_BUFSIZ (80) +#define SCI_CFG_CH10_RX_BUFSIZ (80) +#define SCI_CFG_CH11_RX_BUFSIZ (80) +#define SCI_CFG_CH12_RX_BUFSIZ (80) + +/* +* ENABLE TRANSMIT END INTERRUPT (ASYNCHRONOUS) +* This interrupt only occurs when the last bit of the last byte of data +* has been sent and the transmitter has become idle. The interrupt calls +* the user's callback function specified in R_SCI_Open() and passes it an +* SCI_EVT_TEI event. A typical use of this feature is to disable an external +* transceiver to save power. It would then be up to the user's code to +* re-enable the transceiver before sending again. Not including this feature +* reduces code space used by the interrupt. Note that this equate is only +* for including the TEI code. The interrupt itself must be enabled using an +* R_SCI_Control(hdl, SCI_CMD_EN_TEI, NULL) call. +*/ +#define SCI_CFG_TEI_INCLUDED (CONFIG_USE_RX_RDP_SCI_UART) /* 1=included, 0=not */ + +/* +* SET GROUPBL0 (ERI, TEI) INTERRUPT PRIORITY; RX64M/RX71M/RX65N/RX72M/RX72N/RX66N/RX671/RX660/RX26T ONLY +* SET GROUPBL1; RX65N ONLY +* SET GROUPAL0 (ERI,TEI) INTERRUPT PRIORITY; RX65N, RX72M, RX72N, RX66N ONLY +* This sets the priority level for receiver overrun, framing, and parity errors +* as well as TEI interrupts for all SCI channels. +*/ +/* (RX64M/RX71M/RX65N/RX72M/RX72N/RX66N/RX671/RX660/RX26T ONLY) 1 lowest, 15 highest */ +#define SCI_CFG_ERI_TEI_PRIORITY (1) + +/* ENABLE TX/RX FIFO; (SCIi supported MCU ONLY) 1=included, 0=not */ +#define SCI_CFG_CH7_FIFO_INCLUDED (0) +#define SCI_CFG_CH8_FIFO_INCLUDED (0) +#define SCI_CFG_CH9_FIFO_INCLUDED (0) +#define SCI_CFG_CH10_FIFO_INCLUDED (0) +#define SCI_CFG_CH11_FIFO_INCLUDED (0) + +/* SET TX FIFO THRESHOLD; (SCIi supported MCU ONLY) 0 lowest, 15 highest */ +/* TX FIFO THRESHOLD is invalid in Clock Synchronous Mode and Simple SPI Mode. */ +/* Set the same value for TX FIFO THRESHOLD and RX FIFO THRESHOLD in Clock Synchronous Mode and Simple SPI Mode. */ +#define SCI_CFG_CH7_TX_FIFO_THRESH (8) +#define SCI_CFG_CH8_TX_FIFO_THRESH (8) +#define SCI_CFG_CH9_TX_FIFO_THRESH (8) +#define SCI_CFG_CH10_TX_FIFO_THRESH (8) +#define SCI_CFG_CH11_TX_FIFO_THRESH (8) + +/* SET RX FIFO THRESHOLD; (SCIi supported MCU ONLY) 1 lowest, 15 highest */ +#define SCI_CFG_CH7_RX_FIFO_THRESH (8) +#define SCI_CFG_CH8_RX_FIFO_THRESH (8) +#define SCI_CFG_CH9_RX_FIFO_THRESH (8) +#define SCI_CFG_CH10_RX_FIFO_THRESH (8) +#define SCI_CFG_CH11_RX_FIFO_THRESH (8) + +/* ENABLE Received Data match function (SCIj supported MCU RX66T/RX72T/RX72M/RX72N/RX66N ONLY) 1=included, 0=not */ +/*(SCIi supported MCU RX65N/RX66T/RX72T/RX72M/RX72N/RX66N ONLY) 1=included, 0=not */ +/*(SCIk supported MCU RX671/RX660/RX140/RX26T/RX260/RX261 ONLY) 1=included, 0=not */ +/*(SCIm supported MCU RX671/RX660 ONLY) 1=included, 0=not */ +#define SCI_CFG_CH0_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH1_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH2_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH3_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH4_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH5_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH6_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH7_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH8_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH9_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH10_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH11_DATA_MATCH_INCLUDED (0) + +/* 0=Disable, 1=DTC, 2=DMAC */ +#define SCI_CFG_CH0_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH1_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH2_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH3_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH4_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH5_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH6_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH7_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH8_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH9_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH10_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH11_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH12_TX_DTC_DMACA_ENABLE (0) + +#define SCI_CFG_CH0_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH1_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH2_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH3_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH4_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH5_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH6_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH7_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH8_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH9_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH10_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH11_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH12_RX_DTC_DMACA_ENABLE (0) + +/* 0~7 8 channels dmac, but maximum of SCI channel is 13 channel => cost 13*2 = 26 dmac channels in case all of sci channels run simultaneously */ +#define SCI_CFG_CH0_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH1_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH2_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH3_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH4_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH5_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH6_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH7_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH8_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH9_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH10_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH11_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH12_TX_DMACA_CH_NUM (0) + +#define SCI_CFG_CH0_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH1_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH2_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH3_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH4_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH5_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH6_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH7_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH8_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH9_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH10_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH11_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH12_RX_DMACA_CH_NUM (1) + +/* Set enable/ disable transmit signal transition timing adjust feature for each channel*/ +#define SCI_CFG_CH0_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH1_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH2_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH3_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH4_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH5_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH6_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH7_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH8_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH9_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH10_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH11_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) + +/* Set enable/ disable receive data sampling timing adjust feature for each channel*/ +#define SCI_CFG_CH0_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH1_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH2_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH3_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH4_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH5_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH6_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH7_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH8_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH9_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH10_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH11_RX_DATA_SAMPLING_TIMING_INCLUDED (0) + +/* SPECIFY IRDA CHANNELS TO INCLUDE SOFTWARE (SUPPORTED MCU RX113/RX23W/RX231/RX230 ONLY) 1=included, 0=not */ +#define SCI_CFG_CH5_IRDA_INCLUDED (0) + +/* Set the non-active level of the TXD pin */ +/* 1=High , 0=Low */ +#define SCI_CFG_CH5_IRDA_IRTXD_INACTIVE_LEVEL (0) + +/* Set the non-active level of the RXD pin */ +/* 1=High , 0=Low */ +#define SCI_CFG_CH5_IRDA_IRRXD_INACTIVE_LEVEL (0) + +#endif /* SCI_CONFIG_H */