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"ANTTRIGSTOP" : "ANT_TRIG_STOP" ,
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"BUFOUTREQINASYNC" : "BUFOUT_REQ_IN_ASYNC" ,
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"USBVBUSSENSE" : "USB_VBUS_SENSE" ,
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+ "SWCLKTCK" : "SWCLK" ,
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+ "SWDIOTMS" : "SWDIO" ,
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}
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# Expected offset of DBGROUTEPEN register across all of Series 2.
@@ -109,12 +111,12 @@ def __init__(self, name, offset):
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def max_signal_len (self ):
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return max (len (s .name ) for s in self .signals )
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- def set_signal_enable (self , name , bit ):
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+ def set_signal_enable (self , name , bit , offset = 0 ):
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for signal in self .signals :
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if signal .name == name :
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break
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else :
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- signal = Signal (name , self )
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+ signal = Signal (name , self , offset )
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self .signals .append (signal )
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signal .have_enable = True
@@ -132,8 +134,9 @@ def set_signal_route(self, name, offset):
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class Signal :
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- def __init__ (self , name , peripheral ):
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+ def __init__ (self , name , peripheral , offset = 0 ):
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self .peripheral = peripheral
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+ self .offset = offset
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self .name = name
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self .route = None
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self .have_enable = False
@@ -189,6 +192,18 @@ def parse_svd(peripherals, path: Path, family: str) -> None:
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reg_offset_word = (reg .address_offset - PINCTRL_GPIO_OFFSET ) // 4
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+ if reg .name .endswith ("ROUTEPEN" ):
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+ peripheral = "GPIO"
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+ if peripheral not in peripherals :
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+ peripherals [peripheral ] = Peripheral (peripheral , reg_offset_word )
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+
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+ for field in reg .fields :
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+ if field .name .endswith ("PEN" ):
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+ signal = field .name [:- 3 ]
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+ signal = SIGNAL_ALIAS .get (signal , signal )
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+ signal = SIGNAL_ALIAS .get (f"{ peripheral } ::{ signal } " , signal )
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+ peripherals [peripheral ].set_signal_enable (signal , field .bit_offset , reg_offset_word )
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+
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if reg .name .endswith ("_ROUTEEN" ):
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peripheral = reg .name [:- 8 ]
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peripheral = PERIPHERAL_ALIAS .get (peripheral , peripheral )
@@ -289,8 +304,12 @@ def write_header(path: Path, family, peripherals: dict, abuses: list) -> None:
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for port , pins in signal .pinout .items ():
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for pin in sorted (pins ):
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pad = peripheral .max_signal_len () - len (signal .name ) + 1
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- lines .append (f"#define { signal .display_name ()} _P{ chr (65 + port )} { pin } { ' ' * pad } "
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- f"SILABS_DBUS_{ signal .display_name ()} (0x{ port :x} , 0x{ pin :x} )" )
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+ if signal .route is not None :
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+ lines .append (f"#define { signal .display_name ()} _P{ chr (65 + port )} { pin } { ' ' * pad } "
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+ f"SILABS_DBUS_{ signal .display_name ()} (0x{ port :x} , 0x{ pin :x} )" )
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+ else :
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+ lines .append (f"#define { signal .display_name ()} _P{ chr (65 + port )} { pin } { ' ' * pad } "
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+ f"SILABS_FIXED_ROUTE(0x{ port :x} , 0x{ pin :x} , { signal .offset } , { signal .enable } )" )
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have_content = True
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if have_content :
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lines .append ("" )
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