wiseconnect: Get rid of PSRAM_CHIP_SELECT

PSRAM_CHIP_SELECTS contains an hardware configuration parameter. This
parameter belongs to the DT on the Zephyr side. Hence, it can't be
defined with a macro.

Fortunately, this symbol is redundant with ....spi_config_2.cs_no. So we
can replace the macro by this field.

Signed-off-by: Jérôme Pouiller <[email protected]>

Author: jerome-pouiller

wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram_handle.h

@@ -69,22 +69,16 @@ extern struct sl_psram_info_type_t PSRAM_Device;
  * @{
  */
 #if (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_52_TO_57)
-#define PSRAM_CHIP_SELECT  (CHIP_ZERO)  /**< Chip Select for GPIO Pin Set 52 to 57 */
 #define PSRAM_BASE_ADDRESS (0x0A000000) /**< Base Address for GPIO Pin Set 52 to 57 */
 #elif (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_0_TO_5)
-#define PSRAM_CHIP_SELECT  (CHIP_ZERO)  /**< Chip Select for GPIO Pin Set 0 to 5 */
 #define PSRAM_BASE_ADDRESS (0x0A000000) /**< Base Address for GPIO Pin Set 0 to 5 */
 #elif (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_51_CS_0)
-#define PSRAM_CHIP_SELECT  (CHIP_ZERO)  /**< Chip Select for GPIO Pin Set 46 to 51 with CS 0 */
 #define PSRAM_BASE_ADDRESS (0x0A000000) /**< Base Address for GPIO Pin Set 46 to 51 with CS 0 */
 #elif (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_51_CS_1)
-#define PSRAM_CHIP_SELECT  (CHIP_ONE)   /**< Chip Select for GPIO Pin Set 46 to 51 with CS 1 */
 #define PSRAM_BASE_ADDRESS (0x0B000000) /**< Base Address for GPIO Pin Set 46 to 51 with CS 1 */
 #elif (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_57_CS_0)
-#define PSRAM_CHIP_SELECT  (CHIP_ZERO)  /**< Chip Select for GPIO Pin Set 46 to 57 with CS 0 */
 #define PSRAM_BASE_ADDRESS (0x0A000000) /**< Base Address for GPIO Pin Set 46 to 57 with CS 0 */
 #elif (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_57_CS_1)
-#define PSRAM_CHIP_SELECT  (CHIP_ONE)   /**< Chip Select for GPIO Pin Set 46 to 57 with CS 1 */
 #define PSRAM_BASE_ADDRESS (0x0B000000) /**< Base Address for GPIO Pin Set 46 to 57 with CS 1 */
 #endif
 /// @} end group PSRAM_CHIP_SELECT

wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_psram.c

@@ -74,7 +74,8 @@ spi_config_t spi_psram_default_config = {
                     .extra_byte_en     = 0 },
 
   .spi_config_2 = { .auto_mode                   = EN_MANUAL_MODE,
-                    .cs_no                       = PSRAM_CHIP_SELECT,
+                    /* .cs_no will be filled with value from PSRAM_Device */
+                    .cs_no                       = 0,
                     .neg_edge_sampling           = NEG_EDGE_SAMPLING,
                     .qspi_clk_en                 = QSPI_FULL_TIME_CLK,
                     .protection                  = DNT_REM_WR_PROT,
@@ -983,6 +984,7 @@ sl_psram_return_type_t sl_si91x_psram_init()
   }
 
   /*QSPI Initialization*/
+  spi_psram_default_config.spi_config_2.cs_no = PSRAM_Device.spi_config.spi_config_2.cs_no;
 
   /*Initialize the QSPI controller to PSRAM default mode configuration*/
   RSI_QSPI_SpiInit((qspi_reg_t *)M4_QSPI_2_BASE_ADDRESS, (spi_config_t *)&spi_psram_default_config, 0, 0, 0);
@@ -1087,6 +1089,7 @@ sl_psram_return_type_t sl_si91x_psram_uninit(void)
   psram_exit_qpi_mode();
 
   PSRAMStatus.interfaceMode = SINGLE_MODE;
+  spi_psram_default_config.spi_config_2.cs_no = PSRAM_Device.spi_config.spi_config_2.cs_no;
 
   /*Initialize the QSPI controller to PSRAM default mode configuration*/
   RSI_QSPI_SpiInit((qspi_reg_t *)M4_QSPI_2_BASE_ADDRESS, (spi_config_t *)&spi_psram_default_config, 0, 0, 0);