wiseconnect: Drop orphan functions sl_si91x_trigger_sleep()

Wiseconnect has been original developed for FreeRTOS.
sl_si91x_trigger_sleep() directly relies of FreeRTOS services. This
function does not compile. However, it is never called and can be safely
removed.

Upstream-status: Pending
Signed-off-by: Jérôme Pouiller <[email protected]>

Author: jerome-pouiller

wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c

@@ -27,7 +27,6 @@
  *
  ******************************************************************************/
 
-#include "FreeRTOSConfig.h"
 #include "rsi_wisemcu_hardware_setup.h"
 #include "rsi_m4.h"
 #include "rsi_rom_egpio.h"
@@ -215,157 +214,6 @@ void sli_si91x_configure_wireless_frontend_controls(uint32_t switch_sel)
 #endif
 }
 
-/**
- * @brief	  Configure the default hardware configuration required for 'WiSeMCU' mode.
- * @param[in] sleepType - Select the retention or non-retention mode of processor; refer to 'SLEEP_TYPE_T'.
- *                        \n SLEEP_WITH_RETENTION : When used, user must configure the RAMs to be retained during sleep by using the 'RSI_PS_SetRamRetention()' function.
- * @param[in] lf_clk_mode - This parameter is used to switch the processor clock from high frequency clock to low-frequency clock. This is used in some critical power save cases.
- *                          \n '0' : ' \ref DISABLE_LF_MODE' Normal mode of operation , recommended in most applications.
- *                          \n '1' : ' \ref LF_32_KHZ_RC' Processor clock is configured to low-frequency RC clock.
- *                          \n '2' : ' \ref LF_32_KHZ_XTAL' Processor clock is configured to low-frequency XTAL clock.
- * @param[in] stack_address - Stack pointer address to be used by bootloader.
- * @param[in] jump_cb_address - Control block memory address or function address to be branched up on Wake-up
- * @param[in] vector_offset - IVT offset to be programmed by boot-loader up on Wake-up.
- * @param[in] mode - Possible parameters as follows:
- *                  \n \ref RSI_WAKEUP_FROM_FLASH_MODE  : Wakes from flash with retention. Upon wake up, control jumps to wake up handler in flash.
- *                                                        In this mode, ULPSS RAMs are used to store the stack pointer and Wake-up handler address.
- *                  \n \ref RSI_WAKEUP_WITH_OUT_RETENTION : Without retention sleep common for both FLASH/RAM based execution.
- *                                                        In this mode, ULPSS RAMs are used to store the stack pointer and control block address.
- *                                                        if stack_addr and jump_cb_addr are not valid, then 0x2404_0C00 and 0x2404_0000 are used
- *                                                        for stack and control block address respectively.
- *                  \n \ref RSI_WAKEUP_WITH_RETENTION : With retention branches to wake up handler in RAM.
- *                                                      In this mode, ULPSS RAMs are used to store the wake up handler address.
- *                  \n \ref RSI_WAKEUP_WITH_RETENTION_WO_ULPSS_RAM : In this mode, ULPSS RAMs are not used by boot-loader, instead it uses the NPSS battery flip flops.
- *                  \n \ref RSI_WAKEUP_WO_RETENTION_WO_ULPSS_RAM  : In this mode, ULPSS RAMs are not used by boot-loader, instead it uses the NPSS battery flip flops to store
- *                                                                  the stack and derives the control block address by adding 0XC00
- *                                                                  to the stack address stored in battery flops.
- * @return    Void
- */
-
-void sl_si91x_trigger_sleep(SLEEP_TYPE_T sleepType,
-                            uint8_t lf_clk_mode,
-                            uint32_t stack_address,
-                            uint32_t jump_cb_address,
-                            uint32_t vector_offset,
-                            uint32_t mode)
-{
-  // Turn on the ULPSS RAM domains and retain ULPSS RAMs
-  if ((mode != RSI_WAKEUP_WITH_RETENTION_WO_ULPSS_RAM) || (mode != RSI_WAKEUP_WO_RETENTION_WO_ULPSS_RAM)) {
-    /* Turn on ULPSS SRAM domains*/
-    RSI_PS_UlpssRamBanksPowerUp(ULPSS_2K_BANK_0 | ULPSS_2K_BANK_1 | ULPSS_2K_BANK_2 | ULPSS_2K_BANK_3);
-
-    /* Turn on ULPSS SRAM Core/Periphery domains*/
-    RSI_PS_UlpssRamBanksPeriPowerUp(ULPSS_2K_BANK_0 | ULPSS_2K_BANK_1 | ULPSS_2K_BANK_2 | ULPSS_2K_BANK_3);
-
-    if ((mode == RSI_WAKEUP_FROM_FLASH_MODE) || (mode == RSI_WAKEUP_WITH_RETENTION)
-#if defined(SLI_SI917B0) || defined(SLI_SI915)
-        || (mode == SL_SI91X_MCU_WAKEUP_PSRAM_MODE)
-#endif // SLI_SI917B0
-    ) {
-      /* Retain ULPSS RAM*/
-      RSI_PS_SetRamRetention(ULPSS_RAM_RETENTION_MODE_EN);
-    }
-  }
-
-  // Peripherals needed on Wake-up (without RAM retention) needs to be powered up before going to sleep
-  if ((mode == RSI_WAKEUP_WITH_OUT_RETENTION) || (mode == RSI_WAKEUP_WO_RETENTION_WO_ULPSS_RAM)) {
-
-    RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_M4_DEBUG_FPU);
-  }
-
-#if (SL_SI91X_TICKLESS_MODE == 0)
-
-  if ((osEventFlagsGet(si91x_events) | osEventFlagsGet(si91x_async_events))
-#ifdef SL_SI91X_SIDE_BAND_CRYPTO
-      || (osMutexGetOwner(side_band_crypto_mutex) != NULL)
-#endif
-      || (sli_si91x_host_queue_status(&cmd_queues[SI91X_COMMON_CMD].tx_queue)
-          | sli_si91x_host_queue_status(&cmd_queues[SLI_SI91X_WLAN_CMD].tx_queue)
-          | sli_si91x_host_queue_status(&cmd_queues[SLI_SI91X_NETWORK_CMD].tx_queue)
-          | sli_si91x_host_queue_status(&cmd_queues[SLI_SI91X_SOCKET_CMD].tx_queue)
-          | sli_si91x_host_queue_status(&cmd_queues[SLI_SI91X_BT_CMD].tx_queue))) {
-    return;
-  }
-  // Disabling the interrupts & clearing m4_is_active as m4 is going to sleep
-  __disable_irq();
-
-  // Indicate M4 is Inactive
-  P2P_STATUS_REG &= ~M4_is_active;
-  P2P_STATUS_REG;
-  // Adding delay to sync m4 with NWP
-  for (volatile uint8_t delay = 0; delay < 10; delay++) {
-    __ASM("NOP");
-  }
-
-  // Checking if already NWP have triggered the packet to M4
-  // RX_BUFFER_VALID will be cleared by NWP if any packet is triggered
-  if ((P2P_STATUS_REG & TA_wakeup_M4) || (P2P_STATUS_REG & M4_wakeup_TA)
-      || (!(M4SS_P2P_INTR_SET_REG & RX_BUFFER_VALID))) {
-    P2P_STATUS_REG |= M4_is_active;
-    __enable_irq();
-    return;
-  }
-
-  //Disbling systick & clearing interrupt as systick is non-maskable interrupt
-  SysTick->CTRL = DISABLE;
-  NVIC_ClearPendingIRQ(SysTick_IRQn);
-
-  //!Clear RX_BUFFER_VALID
-  M4SS_P2P_INTR_CLR_REG = RX_BUFFER_VALID;
-  M4SS_P2P_INTR_CLR_REG;
-#endif // SL_SI91X_TICKLESS_MODE  == 0
-
-#ifndef ENABLE_DEBUG_MODULE
-  RSI_PS_M4ssPeriPowerDown(M4SS_PWRGATE_ULP_M4_DEBUG_FPU);
-#endif // ENABLE_DEBUG_MODULE
-
-  /* Define 'SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION' macro if FLASH execution is needed*/
-#ifndef SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION
-  RSI_PS_M4ssPeriPowerDown(M4SS_PWRGATE_ULP_QSPI_ICACHE);
-  // Remove this if MCU is executing from Flash
-#endif //SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION
-
-  // Move M4 SOC clock to ULP reference clock before going to PowerSave
-  if (RSI_CLK_M4SocClkConfig(M4CLK, M4_ULPREFCLK, 0) != RSI_OK) {
-    printf("RSI_CLK_M4SocClkConfig failed\n");
-  }
-
-  /* Check whether M4 is using XTAL */
-  if (sli_si91x_is_xtal_in_use_by_m4() == true) {
-    /* If M4 is using XTAL then request NWP to turn OFF XTAL as M4 is going to sleep */
-    sli_si91x_raise_xtal_interrupt_to_ta(TURN_OFF_XTAL_REQUEST);
-  }
-
-  // Configure sleep parameters required by bootloader upon Wake-up
-  RSI_PS_RetentionSleepConfig(stack_address, jump_cb_address, vector_offset, mode);
-
-  // Trigger M4 to sleep
-  RSI_PS_EnterDeepSleep(sleepType, lf_clk_mode);
-
-  /* Check whether M4 is using XTAL */
-  if (sli_si91x_is_xtal_in_use_by_m4() == true) {
-    /* If M4 is using XTAL then request NWP to turn ON XTAL as M4 is going to sleep */
-    sli_si91x_raise_xtal_interrupt_to_ta(TURN_ON_XTAL_REQUEST);
-  }
-
-#if defined(SLI_SI917) || defined(SLI_SI915)
-  // Upon wake up program wireless GPIO frontend switch controls
-  if (frontend_switch_control != 0) {
-    sli_si91x_configure_wireless_frontend_controls(frontend_switch_control);
-  }
-#endif
-
-#if (SL_SI91X_TICKLESS_MODE == 0)
-  //!Indicate M4 is active and rx buffer valid
-  P2P_STATUS_REG |= M4_is_active;
-  M4SS_P2P_INTR_SET_REG = RX_BUFFER_VALID;
-  __enable_irq();
-
-  // Systick configuration upon Wake-up
-  SysTick_Config(SystemCoreClock / configTICK_RATE_HZ);
-#endif // SL_SI91X_TICKLESS_MODE  == 0
-}
-
 /**
  * @brief	  Configure the default hardware configuration required for 'WiSeMCU' mode.
  * @param[in] rams_in_use                 - RAMs to be powered functionally (the rest of the RAM banks will be power gates)