diff --git a/CMakeLists.txt b/CMakeLists.txt index e561c97..c3f690f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -40,3 +40,6 @@ endif() # STMEMSC - Hardware Abstraction Layer for ST sensor add_subdirectory_ifdef(CONFIG_HAS_STMEMSC sensor/stmemsc) + +# Add sensor common include files +zephyr_include_directories(sensor/inc) diff --git a/sensor/inc/mems_conf_shared_types.h b/sensor/inc/mems_conf_shared_types.h new file mode 100644 index 0000000..101200e --- /dev/null +++ b/sensor/inc/mems_conf_shared_types.h @@ -0,0 +1,131 @@ +/** + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#include + +/* + * This file contain the MEMS Configuration Shared Types v2.0 that are used inside + * the various algo configuration files. + */ + +#ifndef MEMS_CONF_SHARED_TYPES +#define MEMS_CONF_SHARED_TYPES + +#define MEMS_CONF_ARRAY_LEN(x) (sizeof(x) / sizeof(x[0])) + +/* + * MEMS_CONF_SHARED_TYPES format supports the following operations: + * - MEMS_CONF_OP_TYPE_TYPE_READ: read the register at the location specified + * by the "address" field ("data" field is ignored) + * - MEMS_CONF_OP_TYPE_TYPE_WRITE: write the value specified by the "data" + * field at the location specified by the "address" field + * - MEMS_CONF_OP_TYPE_TYPE_DELAY: wait the number of milliseconds specified by + * the "data" field ("address" field is ignored) + * - MEMS_CONF_OP_TYPE_TYPE_POLL_SET: poll the register at the location + * specified by the "address" field until all the bits identified by the mask + * specified by the "data" field are set to 1 + * - MEMS_CONF_OP_TYPE_TYPE_POLL_RESET: poll the register at the location + * specified by the "address" field until all the bits identified by the mask + * specified by the "data" field are reset to 0 + */ + +struct mems_conf_name_list { + const char *const *list; + uint16_t len; +}; + +enum { + MEMS_CONF_OP_TYPE_READ = 1, + MEMS_CONF_OP_TYPE_WRITE = 2, + MEMS_CONF_OP_TYPE_DELAY = 3, + MEMS_CONF_OP_TYPE_POLL_SET = 4, + MEMS_CONF_OP_TYPE_POLL_RESET = 5 +}; + +struct mems_conf_op { + uint8_t type; + uint8_t address; + uint8_t data; +}; + +struct mems_conf_op_list { + const struct mems_conf_op *list; + uint32_t len; +}; + +#endif /* MEMS_CONF_SHARED_TYPES */ + +#ifndef MEMS_CONF_METADATA_SHARED_TYPES +#define MEMS_CONF_METADATA_SHARED_TYPES + +struct mems_conf_application { + char *name; + char *version; +}; + +struct mems_conf_result { + uint8_t code; + char *label; +}; + +enum { + MEMS_CONF_OUTPUT_CORE_HW = 1, + MEMS_CONF_OUTPUT_CORE_EMB = 2, + MEMS_CONF_OUTPUT_CORE_FSM = 3, + MEMS_CONF_OUTPUT_CORE_MLC = 4, + MEMS_CONF_OUTPUT_CORE_ISPU = 5 +}; + +enum { + MEMS_CONF_OUTPUT_TYPE_UINT8_T = 1, + MEMS_CONF_OUTPUT_TYPE_INT8_T = 2, + MEMS_CONF_OUTPUT_TYPE_CHAR = 3, + MEMS_CONF_OUTPUT_TYPE_UINT16_T = 4, + MEMS_CONF_OUTPUT_TYPE_INT16_T = 5, + MEMS_CONF_OUTPUT_TYPE_UINT32_T = 6, + MEMS_CONF_OUTPUT_TYPE_INT32_T = 7, + MEMS_CONF_OUTPUT_TYPE_UINT64_T = 8, + MEMS_CONF_OUTPUT_TYPE_INT64_T = 9, + MEMS_CONF_OUTPUT_TYPE_HALF = 10, + MEMS_CONF_OUTPUT_TYPE_FLOAT = 11, + MEMS_CONF_OUTPUT_TYPE_DOUBLE = 12 +}; + +struct mems_conf_output { + char *name; + uint8_t core; + uint8_t type; + uint16_t len; + uint8_t reg_addr; + char *reg_name; + uint8_t num_results; + const struct mems_conf_result *results; +}; + +struct mems_conf_output_list { + const struct mems_conf_output *list; + uint16_t len; +}; + +struct mems_conf_mlc_identifier { + uint8_t fifo_tag; + uint16_t id; + char *label; +}; + +struct mems_conf_mlc_identifier_list { + const struct mems_conf_mlc_identifier *list; + uint16_t len; +}; + +#endif /* MEMS_CONF_METADATA_SHARED_TYPES */ diff --git a/sensor/stmemsc/CMakeLists.txt b/sensor/stmemsc/CMakeLists.txt index 54ae55a..57a98ae 100644 --- a/sensor/stmemsc/CMakeLists.txt +++ b/sensor/stmemsc/CMakeLists.txt @@ -35,6 +35,7 @@ set(stmems_pids ism330dhcx ism330dlc ism330is + ism6hg256x l3gd20h lis25ba lis2de12 diff --git a/sensor/stmemsc/README b/sensor/stmemsc/README index 3b4afb5..cd042fe 100644 --- a/sensor/stmemsc/README +++ b/sensor/stmemsc/README @@ -6,7 +6,7 @@ Origin: https://www.st.com/en/embedded-software/c-driver-mems.html Status: - version v2.9.1 + version v2.11 Purpose: ST Microelectronics standard C platform-independent drivers for MEMS @@ -49,97 +49,98 @@ Description: Driver versions in this package: - - a3g4250d_STdC v2.0.1 - - ais25ba_STdC v2.0.1 - - ais2dw12_STdC v2.0.1 - - ais2ih_STdC v2.0.1 - - ais328dq_STdC v2.0.1 - - ais3624dq_STdC v2.0.1 - - asm330lhb_STdC v2.1.0 - - asm330lhbg1_STdC v1.1.0 - - asm330lhh_STdC v3.2.0 - - asm330lhhx_STdC v2.1.0 - - asm330lhhxg1_STdC v2.0.1 - - h3lis100dl_STdC v2.0.1 - - h3lis331dl_STdC v2.0.1 - - hts221_STdC v2.1.0 - - i3g4250d_STdC v2.0.1 - - iis2dh_STdC v2.0.1 - - iis2dlpc_STdC v2.0.1 - - iis2dulpx_STdC v1.0.2 - - iis2iclx_STdC v2.0.1 - - iis2mdc_STdC v2.0.3 - - iis328dq_STdC v2.0.1 - - iis3dhhc_STdC v2.0.1 - - iis3dwb_STdC v2.0.1 - - ilps22qs_STdC v3.1.1 - - ilps28qsw_STdC v2.2.0 - - ism303dac_STdC v2.0.1 - - ism330bx_STdC v3.0.2 - - ism330dhcx_STdC v2.1.1 - - ism330dlc_STdC v2.0.2 - - ism330is_STdC v3.0.1 - - l3gd20h_STdC v2.0.1 - - lis25ba_STdC v2.0.1 - - lis2de12_STdC v2.0.1 - - lis2dh12_STdC v2.0.1 - - lis2ds12_STdC v2.0.1 - - lis2dtw12_STdC v2.0.1 - - lis2du12_STdC v2.0.1 - - lis2dux12_STdC v2.4.1 - - lis2duxs12_STdC v2.4.1 - - lis2dw12_STdC v2.0.1 - - lis2hh12_STdC v2.0.1 - - lis2mdl_STdC v2.0.1 - - lis331dlh_STdC v2.0.1 - - lis3de_STdC v2.0.1 - - lis3dh_STdC v2.0.1 - - lis3dhh_STdC v2.0.2 - - lis3mdl_STdC v2.0.1 - - lps22ch_STdC v2.0.1 - - lps22df_STdC v2.2.0 - - lps22hb_STdC v2.0.2 - - lps22hh_STdC v3.0.2 - - lps25hb_STdC v2.0.1 - - lps27hhtw_STdC v2.0.1 - - lps27hhw_STdC v2.0.1 - - lps28dfw_STdC v2.2.0 - - lps33k_STdC v2.0.1 - - lsm303agr_STdC v2.0.1 - - lsm303ah_STdC v2.0.1 - - lsm6ds3tr-c_STdC v2.0.1 - - lsm6dsl_STdC v2.0.1 - - lsm6dsm_STdC v2.0.1 - - lsm6dso16is_STdC v3.0.1 - - lsm6dso32_STdC v2.1.0 - - lsm6dso32x_STdC v2.1.0 - - lsm6dso_STdC v3.1.1 - - lsm6dsox_STdC v3.1.0 - - lsm6dsr_STdC v2.1.0 - - lsm6dsrx_STdC v2.1.0 - - lsm6dsv16b_STdC v3.0.1 - - lsm6dsv16bx_STdC v5.0.2 - - lsm6dsv16x_STdC v4.3.0 - - lsm6dsv320x_STdC v1.1.0 - - lsm6dsv32x_STdC v2.3.0 - - lsm6dsv80x_STdC v1.1.0 - - lsm6dsv_STdC v3.3.0 - - lsm9ds1_STdC v2.0.1 - - st1vafe3bx_STdC v2.1.1 - - st1vafe6ax_STdC v2.0.2 - - sths34pf80_STdC v3.0.1 - - stts22h_STdC v2.1.1 - - stts751_STdC v2.0.1 + - a3g4250d_STdC v2.2.0 + - ais25ba_STdC v2.2.0 + - ais2dw12_STdC v2.2.0 + - ais2ih_STdC v2.2.0 + - ais328dq_STdC v2.2.0 + - ais3624dq_STdC v2.2.0 + - asm330lhb_STdC v2.3.0 + - asm330lhbg1_STdC v1.3.0 + - asm330lhh_STdC v3.4.0 + - asm330lhhx_STdC v2.3.0 + - asm330lhhxg1_STdC v2.2.1 + - h3lis100dl_STdC v2.2.0 + - h3lis331dl_STdC v2.2.0 + - hts221_STdC v2.3.0 + - i3g4250d_STdC v2.2.0 + - iis2dh_STdC v2.2.0 + - iis2dlpc_STdC v2.2.0 + - iis2dulpx_STdC v2.0.0 + - iis2iclx_STdC v2.2.0 + - iis2mdc_STdC v2.2.0 + - iis328dq_STdC v2.2.0 + - iis3dhhc_STdC v2.2.0 + - iis3dwb_STdC v2.2.0 + - ilps22qs_STdC v4.0.0 + - ilps28qsw_STdC v3.0.0 + - ism303dac_STdC v2.2.0 + - ism330bx_STdC v3.2.0 + - ism330dhcx_STdC v2.4.0 + - ism330dlc_STdC v2.2.0 + - ism330is_STdC v3.2.0 + - ism6hg256x_STdC v2.0.0 + - l3gd20h_STdC v2.2.0 + - lis25ba_STdC v2.2.0 + - lis2de12_STdC v2.2.0 + - lis2dh12_STdC v2.2.0 + - lis2ds12_STdC v2.2.0 + - lis2dtw12_STdC v2.2.0 + - lis2du12_STdC v2.2.0 + - lis2dux12_STdC v3.0.0 + - lis2duxs12_STdC v3.0.0 + - lis2dw12_STdC v2.2.0 + - lis2hh12_STdC v2.2.0 + - lis2mdl_STdC v2.2.0 + - lis331dlh_STdC v2.2.0 + - lis3de_STdC v2.2.0 + - lis3dh_STdC v2.2.0 + - lis3dhh_STdC v2.2.0 + - lis3mdl_STdC v2.2.0 + - lps22ch_STdC v2.2.0 + - lps22df_STdC v2.4.0 + - lps22hb_STdC v2.2.0 + - lps22hh_STdC v3.2.0 + - lps25hb_STdC v2.2.0 + - lps27hhtw_STdC v2.2.0 + - lps27hhw_STdC v2.2.0 + - lps28dfw_STdC v3.0.0 + - lps33k_STdC v2.2.0 + - lsm303agr_STdC v2.2.0 + - lsm303ah_STdC v2.2.0 + - lsm6ds3tr-c_STdC v2.2.0 + - lsm6dsl_STdC v2.2.0 + - lsm6dsm_STdC v2.2.0 + - lsm6dso16is_STdC v3.2.0 + - lsm6dso32_STdC v2.3.0 + - lsm6dso32x_STdC v2.3.0 + - lsm6dso_STdC v3.2.1 + - lsm6dsox_STdC v3.3.0 + - lsm6dsr_STdC v2.3.0 + - lsm6dsrx_STdC v2.3.0 + - lsm6dsv16b_STdC v3.2.0 + - lsm6dsv16bx_STdC v5.2.0 + - lsm6dsv16x_STdC v5.0.0 + - lsm6dsv320x_STdC v3.0.0 + - lsm6dsv32x_STdC v3.0.0 + - lsm6dsv80x_STdC v3.0.0 + - lsm6dsv_STdC v4.0.0 + - lsm9ds1_STdC v2.2.0 + - st1vafe3bx_STdC v2.3.0 + - st1vafe6ax_STdC v2.2.0 + - sths34pf80_STdC v3.2.0 + - stts22h_STdC v2.3.0 + - stts751_STdC v2.2.0 Dependencies: None. URL: https://www.st.com/en/embedded-software/c-driver-mems.html - https://github.com/STMicroelectronics/STMems_Standard_C_drivers/tree/v2.9.1 + https://github.com/STMicroelectronics/STMems_Standard_C_drivers/tree/v2.11 commit: - 0c1759e4 (tag v2.9.1) + 7ae811c3 (tag v2.11) Maintained-by: ST Microelectronics diff --git a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c index af3100f..f833094 100644 --- a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c +++ b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -159,6 +158,7 @@ int32_t a3g4250d_data_rate_get(const stmdev_ctx_t *ctx, a3g4250d_dr_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pd) { @@ -226,6 +226,8 @@ int32_t a3g4250d_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -261,7 +263,7 @@ int32_t a3g4250d_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) /** * @brief Angular rate sensor. The value is expressed as a 16-bit word in - * two’s complement.[get] + * two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores the data read.(ptr) @@ -274,6 +276,8 @@ int32_t a3g4250d_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = a3g4250d_read_reg(ctx, A3G4250D_OUT_X_L, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -354,6 +358,7 @@ int32_t a3g4250d_self_test_get(const stmdev_ctx_t *ctx, a3g4250d_st_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.st) { @@ -418,6 +423,7 @@ int32_t a3g4250d_data_format_get(const stmdev_ctx_t *ctx, a3g4250d_ble_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.ble) { @@ -478,6 +484,8 @@ int32_t a3g4250d_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg5.boot; return ret; @@ -537,6 +545,7 @@ int32_t a3g4250d_lp_bandwidth_get(const stmdev_ctx_t *ctx, a3g4250d_bw_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } switch (ctrl_reg1.bw) { @@ -605,6 +614,7 @@ int32_t a3g4250d_hp_bandwidth_get(const stmdev_ctx_t *ctx, a3g4250d_hpcf_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpcf) { @@ -697,6 +707,7 @@ int32_t a3g4250d_hp_mode_get(const stmdev_ctx_t *ctx, a3g4250d_hpm_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpm) { @@ -766,6 +777,7 @@ int32_t a3g4250d_filter_path_get(const stmdev_ctx_t *ctx, a3g4250d_out_sel_t *va ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg5.hpen << 2) + ctrl_reg5.out_sel) { @@ -837,6 +849,7 @@ int32_t a3g4250d_filter_path_internal_get(const stmdev_ctx_t *ctx, ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg5.hpen << 2) + ctrl_reg5.int1_sel) { @@ -906,6 +919,8 @@ int32_t a3g4250d_hp_reference_value_get(const stmdev_ctx_t *ctx, ret = a3g4250d_read_reg(ctx, A3G4250D_REFERENCE, (uint8_t *)&reference, 1); + if (ret != 0) { return ret; } + *val = reference.ref; return ret; @@ -965,6 +980,7 @@ int32_t a3g4250d_spi_mode_get(const stmdev_ctx_t *ctx, a3g4250d_sim_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.sim) { @@ -1043,6 +1059,8 @@ int32_t a3g4250d_pin_int1_route_get(const stmdev_ctx_t *ctx, ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + val->i1_int1 = ctrl_reg3.i1_int1; val->i1_boot = ctrl_reg3.i1_boot; @@ -1094,6 +1112,8 @@ int32_t a3g4250d_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + val->i2_empty = ctrl_reg3.i2_empty; val->i2_orun = ctrl_reg3.i2_orun; val->i2_wtm = ctrl_reg3.i2_wtm; @@ -1144,6 +1164,7 @@ int32_t a3g4250d_pin_mode_get(const stmdev_ctx_t *ctx, ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.pp_od) { @@ -1206,6 +1227,7 @@ int32_t a3g4250d_pin_polarity_get(const stmdev_ctx_t *ctx, ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.h_lactive) { @@ -1263,6 +1285,7 @@ int32_t a3g4250d_int_notification_get(const stmdev_ctx_t *ctx, a3g4250d_lir_t *v int32_t ret; ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } switch (int1_cfg.lir) { @@ -1370,6 +1393,7 @@ int32_t a3g4250d_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } switch (int1_cfg.and_or) { @@ -1537,6 +1561,8 @@ int32_t a3g4250d_int_y_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_YL, (uint8_t *)&int1_tsh_yl, 1); + if (ret != 0) { return ret; } + *val = int1_tsh_yh.thsy; *val = *val * 256U; *val += int1_tsh_yl.thsy; @@ -1606,6 +1632,8 @@ int32_t a3g4250d_int_z_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_TSH_ZL, (uint8_t *)&int1_tsh_zl, 1); + if (ret != 0) { return ret; } + *val = int1_tsh_zh.thsz; *val = *val * 256U; *val += int1_tsh_zl.thsz; @@ -1668,6 +1696,8 @@ int32_t a3g4250d_int_on_threshold_dur_get(const stmdev_ctx_t *ctx, ret = a3g4250d_read_reg(ctx, A3G4250D_INT1_DURATION, (uint8_t *)&int1_duration, 1); + if (ret != 0) { return ret; } + *val = int1_duration.d; return ret; @@ -1726,6 +1756,8 @@ int32_t a3g4250d_fifo_enable_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg5.fifo_en; return ret; @@ -1772,6 +1804,8 @@ int32_t a3g4250d_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } + *val = fifo_ctrl_reg.wtm; return ret; @@ -1820,6 +1854,7 @@ int32_t a3g4250d_fifo_mode_get(const stmdev_ctx_t *ctx, ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl_reg.fm) { @@ -1858,6 +1893,8 @@ int32_t a3g4250d_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + if (ret != 0) { return ret; } + *val = fifo_src_reg.fss; return ret; @@ -1878,6 +1915,8 @@ int32_t a3g4250d_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + if (ret != 0) { return ret; } + *val = fifo_src_reg.empty; return ret; @@ -1898,6 +1937,8 @@ int32_t a3g4250d_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + if (ret != 0) { return ret; } + *val = fifo_src_reg.ovrn; return ret; @@ -1921,6 +1962,8 @@ int32_t a3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = a3g4250d_read_reg(ctx, A3G4250D_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + if (ret != 0) { return ret; } + *val = fifo_src_reg.wtm; return ret; @@ -1930,5 +1973,3 @@ int32_t a3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h index 37156ae..5916640 100644 --- a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h +++ b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -119,6 +118,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -745,5 +747,3 @@ int32_t a3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* A3G4250D_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.c b/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.c index 37f33e9..249ea8b 100644 --- a/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.c +++ b/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -230,12 +229,14 @@ int32_t ais25ba_bus_mode_get(const stmdev_ctx_t *ctx, bytecpy((uint8_t *)&tdm_cmax_l, ®[1]); } - val->tdm.en = ~tdm_ctrl_reg.tdm_pd; - val->tdm.clk_pol = tdm_ctrl_reg.data_valid; - val->tdm.clk_edge = tdm_ctrl_reg.delayed; - val->tdm.mapping = tdm_ctrl_reg.wclk_fq; - val->tdm.cmax = tdm_cmax_h.tdm_cmax * 256U; - val->tdm.cmax += tdm_cmax_l.tdm_cmax; + if (ret == 0) { + val->tdm.en = ~tdm_ctrl_reg.tdm_pd; + val->tdm.clk_pol = tdm_ctrl_reg.data_valid; + val->tdm.clk_edge = tdm_ctrl_reg.delayed; + val->tdm.mapping = tdm_ctrl_reg.wclk_fq; + val->tdm.cmax = tdm_cmax_h.tdm_cmax * 256U; + val->tdm.cmax += tdm_cmax_l.tdm_cmax; + } return ret; } @@ -315,6 +316,8 @@ int32_t ais25ba_mode_get(const stmdev_ctx_t *ctx, ais25ba_md_t *val) bytecpy((uint8_t *)&axes_ctrl_reg, ®[1]); } + if (ret != 0) { return ret; } + switch ((axes_ctrl_reg.odr_auto_en << 4) | (tdm_ctrl_reg.wclk_fq << 1) | ctrl_reg.pd) @@ -422,6 +425,7 @@ int32_t ais25ba_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais25ba_read_reg(ctx, AIS25BA_TEST_REG, (uint8_t *)&test_reg, 1); + if (ret != 0) { return ret; } *val = test_reg.st; return ret; @@ -436,5 +440,3 @@ int32_t ais25ba_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.h b/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.h index 1d47d56..c5047f2 100644 --- a/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.h +++ b/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -376,5 +378,3 @@ int32_t ais25ba_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /*AIS25BA_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c index d4fa4f1..50722e4 100644 --- a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c +++ b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -195,6 +194,7 @@ int32_t ais2dw12_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1); + if (ret != 0) { return ret; } switch ((ctrl1.op_mode << 2) + ctrl1.pw_mode) { @@ -293,6 +293,7 @@ int32_t ais2dw12_data_rate_get(const stmdev_ctx_t *ctx, ais2dw12_odr_t *val) if (ret == 0) { ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1); + if (ret != 0) { return ret; } switch ((ctrl3.slp_mode << 4) + ctrl1.odr) { @@ -372,6 +373,7 @@ int32_t ais2dw12_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.bdu; return ret; @@ -415,6 +417,7 @@ int32_t ais2dw12_full_scale_get(const stmdev_ctx_t *ctx, ais2dw12_fs_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.fs) { @@ -466,6 +469,7 @@ int32_t ais2dw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_STATUS, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.drdy; return ret; @@ -486,6 +490,7 @@ int32_t ais2dw12_all_sources_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_STATUS_DUP, reg, 5); + if (ret != 0) { return ret; } bytecpy((uint8_t *)&val->status_dup, ®[0]); bytecpy((uint8_t *)&val->wake_up_src, ®[1]); bytecpy((uint8_t *)&val->sixd_src, ®[3]); @@ -495,7 +500,7 @@ int32_t ais2dw12_all_sources_get(const stmdev_ctx_t *ctx, } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -514,7 +519,7 @@ int32_t ais2dw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -533,7 +538,7 @@ int32_t ais2dw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -552,7 +557,7 @@ int32_t ais2dw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -571,7 +576,7 @@ int32_t ais2dw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -590,7 +595,7 @@ int32_t ais2dw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -651,6 +656,7 @@ int32_t ais2dw12_offset_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.usr_off_w) { @@ -684,7 +690,7 @@ int32_t ais2dw12_offset_weight_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers - * together express a 16-bit word in two’s complement.[get] + * together express a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -697,6 +703,7 @@ int32_t ais2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_OUT_T_L, buff, 2); + if (ret != 0) { return ret; } *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -705,7 +712,7 @@ int32_t ais2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed as - * a 16-bit word in two’s complement.[get] + * a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -718,6 +725,7 @@ int32_t ais2dw12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_OUT_X_L, buff, 6); + if (ret != 0) { return ret; } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -797,6 +805,7 @@ int32_t ais2dw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.if_add_inc; return ret; @@ -840,6 +849,7 @@ int32_t ais2dw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.soft_reset; return ret; @@ -883,6 +893,7 @@ int32_t ais2dw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.boot; return ret; @@ -926,6 +937,7 @@ int32_t ais2dw12_self_test_get(const stmdev_ctx_t *ctx, ais2dw12_st_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.st) { @@ -989,6 +1001,7 @@ int32_t ais2dw12_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.drdy_pulsed) { @@ -1078,6 +1091,7 @@ int32_t ais2dw12_filter_path_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) &ctrl_reg7, 1); + if (ret != 0) { return ret; } switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out) { @@ -1144,6 +1158,7 @@ int32_t ais2dw12_filter_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.bw_filt) { @@ -1209,6 +1224,7 @@ int32_t ais2dw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.hp_ref_mode; return ret; @@ -1265,6 +1281,7 @@ int32_t ais2dw12_spi_mode_get(const stmdev_ctx_t *ctx, ais2dw12_sim_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.sim) { @@ -1325,6 +1342,7 @@ int32_t ais2dw12_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.i2c_disable) { @@ -1384,6 +1402,7 @@ int32_t ais2dw12_cs_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.cs_pu_disc) { @@ -1455,6 +1474,7 @@ int32_t ais2dw12_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.h_lactive) { @@ -1514,6 +1534,7 @@ int32_t ais2dw12_int_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.lir) { @@ -1572,6 +1593,7 @@ int32_t ais2dw12_pin_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.pp_od) { @@ -1767,6 +1789,7 @@ int32_t ais2dw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.int2_on_int1; return ret; @@ -1823,6 +1846,7 @@ int32_t ais2dw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.wk_ths; return ret; @@ -1866,6 +1890,7 @@ int32_t ais2dw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.wake_dur; return ret; @@ -1911,6 +1936,7 @@ int32_t ais2dw12_wkup_feed_data_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.usr_off_on_wu) { @@ -2009,6 +2035,7 @@ int32_t ais2dw12_act_mode_get(const stmdev_ctx_t *ctx, { ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); + if (ret != 0) { return ret; } switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on) { @@ -2071,6 +2098,7 @@ int32_t ais2dw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.sleep_dur; return ret; @@ -2127,6 +2155,7 @@ int32_t ais2dw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg._6d_ths; return ret; @@ -2170,6 +2199,7 @@ int32_t ais2dw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg._4d_en; return ret; @@ -2232,6 +2262,7 @@ int32_t ais2dw12_6d_feed_data_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.lpass_on6d) { @@ -2373,6 +2404,7 @@ int32_t ais2dw12_ff_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.ff_ths) { @@ -2466,6 +2498,7 @@ int32_t ais2dw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.fth; return ret; @@ -2511,6 +2544,7 @@ int32_t ais2dw12_fifo_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.fmode) { @@ -2556,6 +2590,7 @@ int32_t ais2dw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.diff; return ret; @@ -2574,6 +2609,7 @@ int32_t ais2dw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.fifo_ovr; return ret; @@ -2592,6 +2628,7 @@ int32_t ais2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } *val = reg.fifo_fth; return ret; @@ -2606,5 +2643,3 @@ int32_t ais2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h index a974be8..49a7ce8 100644 --- a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h +++ b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -127,6 +126,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -917,5 +919,3 @@ int32_t ais2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /*AIS2DW12_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c index b22b3da..87e2fe3 100644 --- a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c +++ b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -209,6 +208,7 @@ int32_t ais2ih_power_mode_get(const stmdev_ctx_t *ctx, ais2ih_mode_t *val) if (ret == 0) { ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) &ctrl6, 1); + if (ret != 0) return ret; switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) + ctrl1.lp_mode)) @@ -349,6 +349,7 @@ int32_t ais2ih_data_rate_get(const stmdev_ctx_t *ctx, ais2ih_odr_t *val) if (ret == 0) { ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) &ctrl3, 1); + if (ret != 0) return ret; switch ((ctrl3.slp_mode << 4) + ctrl1.odr) { @@ -490,6 +491,7 @@ int32_t ais2ih_full_scale_get(const stmdev_ctx_t *ctx, ais2ih_fs_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.fs) { @@ -572,7 +574,7 @@ int32_t ais2ih_all_sources_get(const stmdev_ctx_t *ctx, } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -591,7 +593,7 @@ int32_t ais2ih_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -610,7 +612,7 @@ int32_t ais2ih_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -629,7 +631,7 @@ int32_t ais2ih_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -648,7 +650,7 @@ int32_t ais2ih_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -667,7 +669,7 @@ int32_t ais2ih_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -728,6 +730,7 @@ int32_t ais2ih_offset_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.usr_off_w) { @@ -761,7 +764,7 @@ int32_t ais2ih_offset_weight_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers - * together express a 16-bit word in two’s complement.[get] + * together express a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param val buffer that stores data read @@ -774,6 +777,7 @@ int32_t ais2ih_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_OUT_T_L, buff, 2); + if (ret != 0) return ret; *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -782,7 +786,7 @@ int32_t ais2ih_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed as - * a 16-bit word in two’s complement.[get] + * a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param val buffer that stores data read @@ -795,6 +799,7 @@ int32_t ais2ih_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_OUT_X_L, buff, 6); + if (ret != 0) return ret; val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -874,6 +879,7 @@ int32_t ais2ih_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.if_add_inc; return ret; @@ -917,6 +923,7 @@ int32_t ais2ih_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.soft_reset; return ret; @@ -960,6 +967,7 @@ int32_t ais2ih_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.boot; return ret; @@ -1003,6 +1011,7 @@ int32_t ais2ih_self_test_get(const stmdev_ctx_t *ctx, ais2ih_st_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.st) { @@ -1066,6 +1075,7 @@ int32_t ais2ih_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.drdy_pulsed) { @@ -1153,6 +1163,7 @@ int32_t ais2ih_filter_path_get(const stmdev_ctx_t *ctx, ais2ih_fds_t *val) if (ret == 0) { ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) &ctrl_reg7, 1); + if (ret != 0) return ret; switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out) { @@ -1219,6 +1230,7 @@ int32_t ais2ih_filter_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL6, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.bw_filt) { @@ -1284,6 +1296,7 @@ int32_t ais2ih_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.hp_ref_mode; return ret; @@ -1400,6 +1413,7 @@ int32_t ais2ih_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.i2c_disable) { @@ -1458,6 +1472,7 @@ int32_t ais2ih_cs_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.cs_pu_disc) { @@ -1529,6 +1544,7 @@ int32_t ais2ih_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.h_lactive) { @@ -1588,6 +1604,7 @@ int32_t ais2ih_int_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.lir) { @@ -1645,6 +1662,7 @@ int32_t ais2ih_pin_mode_get(const stmdev_ctx_t *ctx, ais2ih_pp_od_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.pp_od) { @@ -1844,6 +1862,7 @@ int32_t ais2ih_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.int2_on_int1; return ret; @@ -1943,6 +1962,7 @@ int32_t ais2ih_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.wake_dur; return ret; @@ -1988,6 +2008,7 @@ int32_t ais2ih_wkup_feed_data_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.usr_off_on_wu) { @@ -2084,6 +2105,7 @@ int32_t ais2ih_act_mode_get(const stmdev_ctx_t *ctx, ais2ih_sleep_on_t *val) { ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); + if (ret != 0) return ret; switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on) { @@ -2146,6 +2168,7 @@ int32_t ais2ih_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_DUR, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.sleep_dur; return ret; @@ -2202,6 +2225,7 @@ int32_t ais2ih_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.tap_thsx; return ret; @@ -2245,6 +2269,7 @@ int32_t ais2ih_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.tap_thsy; return ret; @@ -2290,6 +2315,7 @@ int32_t ais2ih_tap_axis_priority_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Y, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.tap_prior) { @@ -2363,6 +2389,7 @@ int32_t ais2ih_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.tap_thsz; return ret; @@ -2406,6 +2433,7 @@ int32_t ais2ih_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.tap_z_en; return ret; @@ -2449,6 +2477,7 @@ int32_t ais2ih_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.tap_y_en; return ret; @@ -2492,6 +2521,7 @@ int32_t ais2ih_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_Z, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.tap_x_en; return ret; @@ -2543,6 +2573,7 @@ int32_t ais2ih_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.shock; return ret; @@ -2594,6 +2625,7 @@ int32_t ais2ih_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.quiet; return ret; @@ -2647,6 +2679,7 @@ int32_t ais2ih_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_INT_DUR, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.latency; return ret; @@ -2692,6 +2725,7 @@ int32_t ais2ih_tap_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_WAKE_UP_THS, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.single_double_tap) { @@ -2779,6 +2813,7 @@ int32_t ais2ih_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg._6d_ths; return ret; @@ -2822,6 +2857,7 @@ int32_t ais2ih_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_TAP_THS_X, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg._4d_en; return ret; @@ -2883,6 +2919,7 @@ int32_t ais2ih_6d_feed_data_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.lpass_on6d) { @@ -2975,6 +3012,7 @@ int32_t ais2ih_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { ret = ais2ih_read_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) &free_fall, 1); + if (ret != 0) return ret; *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; } @@ -3021,6 +3059,7 @@ int32_t ais2ih_ff_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_FREE_FALL, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.ff_ths) { @@ -3114,6 +3153,7 @@ int32_t ais2ih_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.fth; return ret; @@ -3157,6 +3197,7 @@ int32_t ais2ih_fifo_mode_get(const stmdev_ctx_t *ctx, ais2ih_fmode_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_CTRL, (uint8_t *) ®, 1); + if (ret != 0) return ret; switch (reg.fmode) { @@ -3202,6 +3243,7 @@ int32_t ais2ih_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_SAMPLES, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.diff; return ret; @@ -3220,6 +3262,7 @@ int32_t ais2ih_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_SAMPLES, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.fifo_ovr; return ret; @@ -3238,6 +3281,7 @@ int32_t ais2ih_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais2ih_read_reg(ctx, AIS2IH_FIFO_SAMPLES, (uint8_t *) ®, 1); + if (ret != 0) return ret; *val = reg.fifo_fth; return ret; @@ -3252,5 +3296,3 @@ int32_t ais2ih_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h index f5a7abc..0b8c742 100644 --- a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h +++ b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1050,5 +1052,3 @@ int32_t ais2ih_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /*AIS2IH_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c index 54fd6a1..417e744 100644 --- a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c +++ b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -163,6 +162,8 @@ int32_t ais328dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.xen; return ret; @@ -209,6 +210,8 @@ int32_t ais328dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.yen; return ret; @@ -255,6 +258,8 @@ int32_t ais328dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.zen; return ret; @@ -302,6 +307,7 @@ int32_t ais328dq_data_rate_get(const stmdev_ctx_t *ctx, ais328dq_dr_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm) { @@ -396,6 +402,7 @@ int32_t ais328dq_reference_mode_get(const stmdev_ctx_t *ctx, ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpm) { @@ -456,6 +463,7 @@ int32_t ais328dq_full_scale_get(const stmdev_ctx_t *ctx, ais328dq_fs_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.fs) { @@ -521,6 +529,8 @@ int32_t ais328dq_block_data_update_get(const stmdev_ctx_t *ctx, ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg4.bdu; return ret; @@ -559,6 +569,8 @@ int32_t ais328dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -578,7 +590,7 @@ int32_t ais328dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) /** * @brief Linear acceleration output register. The value is expressed - * as a 16-bit word in two’s complement.[get] + * as a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions(ptr) * @param buff buffer that stores data read @@ -591,6 +603,8 @@ int32_t ais328dq_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ais328dq_read_reg(ctx, AIS328DQ_OUT_X_L, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -671,6 +685,8 @@ int32_t ais328dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg2.boot; return ret; @@ -717,6 +733,7 @@ int32_t ais328dq_self_test_get(const stmdev_ctx_t *ctx, ais328dq_st_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.st) { @@ -783,6 +800,7 @@ int32_t ais328dq_data_format_get(const stmdev_ctx_t *ctx, ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.ble) { @@ -858,6 +876,7 @@ int32_t ais328dq_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpcf) { @@ -927,6 +946,7 @@ int32_t ais328dq_hp_path_get(const stmdev_ctx_t *ctx, ais328dq_hpen_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen) { @@ -1083,6 +1103,7 @@ int32_t ais328dq_spi_mode_get(const stmdev_ctx_t *ctx, ais328dq_sim_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.sim) { @@ -1158,6 +1179,7 @@ int32_t ais328dq_pin_int1_route_get(const stmdev_ctx_t *ctx, ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.i1_cfg) { @@ -1230,6 +1252,7 @@ int32_t ais328dq_int1_notification_get(const stmdev_ctx_t *ctx, ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.lir1) { @@ -1292,6 +1315,7 @@ int32_t ais328dq_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.i2_cfg) { @@ -1364,6 +1388,7 @@ int32_t ais328dq_int2_notification_get(const stmdev_ctx_t *ctx, ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.lir2) { @@ -1425,6 +1450,7 @@ int32_t ais328dq_pin_mode_get(const stmdev_ctx_t *ctx, ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.pp_od) { @@ -1487,6 +1513,7 @@ int32_t ais328dq_pin_polarity_get(const stmdev_ctx_t *ctx, ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.ihl) { @@ -1565,6 +1592,8 @@ int32_t ais328dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } + val->int1_xlie = int1_cfg.xlie; val->int1_xhie = int1_cfg.xhie; val->int1_ylie = int1_cfg.ylie; @@ -1616,6 +1645,7 @@ int32_t ais328dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } switch (int1_cfg.aoi) { @@ -1692,6 +1722,8 @@ int32_t ais328dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1); + if (ret != 0) { return ret; } + *val = int1_ths.ths; return ret; @@ -1738,6 +1770,8 @@ int32_t ais328dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_DURATION, (uint8_t *)&int1_duration, 1); + if (ret != 0) { return ret; } + *val = int1_duration.d; return ret; @@ -1790,6 +1824,8 @@ int32_t ais328dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } + val->int2_xlie = int2_cfg.xlie; val->int2_xhie = int2_cfg.xhie; val->int2_ylie = int2_cfg.ylie; @@ -1841,6 +1877,7 @@ int32_t ais328dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } switch (int2_cfg.aoi) { @@ -1917,6 +1954,8 @@ int32_t ais328dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1); + if (ret != 0) { return ret; } + *val = int2_ths.ths; return ret; @@ -1963,6 +2002,8 @@ int32_t ais328dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_DURATION, (uint8_t *)&int2_duration, 1); + if (ret != 0) { return ret; } + *val = int2_duration.d; return ret; @@ -2022,6 +2063,8 @@ int32_t ais328dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg5.turnon; return ret; @@ -2081,6 +2124,7 @@ int32_t ais328dq_int1_6d_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } switch ((int1_cfg.aoi << 1) + int1_cfg._6d) { @@ -2160,6 +2204,8 @@ int32_t ais328dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1); + if (ret != 0) { return ret; } + *val = int1_ths.ths; return ret; @@ -2207,6 +2253,7 @@ int32_t ais328dq_int2_6d_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } switch ((int2_cfg.aoi << 1) + int2_cfg._6d) { @@ -2287,6 +2334,8 @@ int32_t ais328dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1); + if (ret != 0) { return ret; } + *val = int2_ths.ths; return ret; @@ -2296,5 +2345,3 @@ int32_t ais328dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h index 367fe99..40b9c3f 100644 --- a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h +++ b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -831,5 +833,3 @@ int32_t ais328dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, #endif #endif /* AIS328DQ_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c index c51fd64..4b794a3 100644 --- a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c +++ b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -163,6 +162,8 @@ int32_t ais3624dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.xen; return ret; @@ -209,6 +210,8 @@ int32_t ais3624dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.yen; return ret; @@ -255,6 +258,8 @@ int32_t ais3624dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.zen; return ret; @@ -303,6 +308,7 @@ int32_t ais3624dq_data_rate_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm) { @@ -397,6 +403,7 @@ int32_t ais3624dq_reference_mode_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpm) { @@ -459,6 +466,7 @@ int32_t ais3624dq_full_scale_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.fs) { @@ -525,6 +533,8 @@ int32_t ais3624dq_block_data_update_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg4.bdu; return ret; @@ -563,6 +573,8 @@ int32_t ais3624dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais3624dq_read_reg(ctx, AIS3624DQ_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -582,7 +594,7 @@ int32_t ais3624dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) /** * @brief Linear acceleration output register. The value is expressed - * as a 16-bit word in two’s complement.[get] + * as a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions(ptr) * @param buff buffer that stores data read @@ -596,6 +608,8 @@ int32_t ais3624dq_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ais3624dq_read_reg(ctx, AIS3624DQ_OUT_X_L, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -676,6 +690,8 @@ int32_t ais3624dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg2.boot; return ret; @@ -723,6 +739,7 @@ int32_t ais3624dq_self_test_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.st) { @@ -789,6 +806,7 @@ int32_t ais3624dq_data_format_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.ble) { @@ -864,6 +882,7 @@ int32_t ais3624dq_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpcf) { @@ -934,6 +953,7 @@ int32_t ais3624dq_hp_path_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen) { @@ -1091,6 +1111,7 @@ int32_t ais3624dq_spi_mode_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.sim) { @@ -1166,6 +1187,7 @@ int32_t ais3624dq_pin_int1_route_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.i1_cfg) { @@ -1238,6 +1260,7 @@ int32_t ais3624dq_int1_notification_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.lir1) { @@ -1300,6 +1323,7 @@ int32_t ais3624dq_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.i2_cfg) { @@ -1372,6 +1396,7 @@ int32_t ais3624dq_int2_notification_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.lir2) { @@ -1434,6 +1459,7 @@ int32_t ais3624dq_pin_mode_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.pp_od) { @@ -1496,6 +1522,7 @@ int32_t ais3624dq_pin_polarity_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.ihl) { @@ -1576,6 +1603,8 @@ int32_t ais3624dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } + val->int1_xlie = int1_cfg.xlie; val->int1_xhie = int1_cfg.xhie; val->int1_ylie = int1_cfg.ylie; @@ -1629,6 +1658,7 @@ int32_t ais3624dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } switch (int1_cfg.aoi) { @@ -1707,6 +1737,8 @@ int32_t ais3624dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS, (uint8_t *)&int1_ths, 1); + if (ret != 0) { return ret; } + *val = int1_ths.ths; return ret; @@ -1753,6 +1785,8 @@ int32_t ais3624dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_DURATION, (uint8_t *)&int1_duration, 1); + if (ret != 0) { return ret; } + *val = int1_duration.d; return ret; @@ -1806,6 +1840,8 @@ int32_t ais3624dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } + val->int2_xlie = int2_cfg.xlie; val->int2_xhie = int2_cfg.xhie; val->int2_ylie = int2_cfg.ylie; @@ -1859,6 +1895,7 @@ int32_t ais3624dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } switch (int2_cfg.aoi) { @@ -1937,6 +1974,8 @@ int32_t ais3624dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS, (uint8_t *)&int2_ths, 1); + if (ret != 0) { return ret; } + *val = int2_ths.ths; return ret; @@ -1983,6 +2022,8 @@ int32_t ais3624dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_DURATION, (uint8_t *)&int2_duration, 1); + if (ret != 0) { return ret; } + *val = int2_duration.d; return ret; @@ -2042,6 +2083,8 @@ int32_t ais3624dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg5.turnon; return ret; @@ -2104,6 +2147,7 @@ int32_t ais3624dq_int1_6d_mode_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } switch ((int1_cfg.aoi << 1) + int1_cfg._6d) { @@ -2187,6 +2231,8 @@ int32_t ais3624dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS, (uint8_t *)&int1_ths, 1); + if (ret != 0) { return ret; } + *val = int1_ths.ths; return ret; @@ -2236,6 +2282,7 @@ int32_t ais3624dq_int2_6d_mode_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } switch ((int2_cfg.aoi << 1) + int2_cfg._6d) { @@ -2319,6 +2366,8 @@ int32_t ais3624dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS, (uint8_t *)&int2_ths, 1); + if (ret != 0) { return ret; } + *val = int2_ths.ths; return ret; @@ -2328,5 +2377,3 @@ int32_t ais3624dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h index 2a39de9..4ee3f61 100644 --- a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h +++ b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -821,5 +823,3 @@ int32_t ais3624dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, #endif #endif /* AIS3624DQ_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.c b/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.c index 1b9d1c8..3fdaad0 100644 --- a/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.c +++ b/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2023 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -210,6 +209,11 @@ int32_t asm330lhb_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl1_xl.fs_xl) { case ASM330LHB_2g: @@ -367,11 +371,11 @@ int32_t asm330lhb_xl_data_rate_set(const stmdev_ctx_t *ctx, mlc_enable = PROPERTY_DISABLE; if (ret == 0) { - ret = asm330lhb_mlc_get(ctx, &mlc_enable); + ret = asm330lhb_mlc_get(ctx, &mlc_enable); if (mlc_enable == PROPERTY_ENABLE) { - ret = asm330lhb_mlc_data_rate_get(ctx, &mlc_odr); + ret += asm330lhb_mlc_data_rate_get(ctx, &mlc_odr); if (ret == 0) { switch (mlc_odr) @@ -488,6 +492,11 @@ int32_t asm330lhb_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl1_xl.odr_xl) { case ASM330LHB_XL_ODR_OFF: @@ -565,6 +574,11 @@ int32_t asm330lhb_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2_g.fs_g) { case ASM330LHB_125dps: @@ -850,6 +864,11 @@ int32_t asm330lhb_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2_g.odr_g) { case ASM330LHB_GY_ODR_OFF: @@ -922,6 +941,11 @@ int32_t asm330lhb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.bdu; return ret; @@ -967,6 +991,10 @@ int32_t asm330lhb_xl_offset_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.usr_off_w) { @@ -1021,6 +1049,11 @@ int32_t asm330lhb_xl_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl6_c.xl_hm_mode) { case ASM330LHB_HIGH_PERFORMANCE_MD: @@ -1074,6 +1107,11 @@ int32_t asm330lhb_gy_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl7_g.g_hm_mode) { case ASM330LHB_GY_HIGH_PERFORMANCE: @@ -1121,35 +1159,44 @@ int32_t asm330lhb_all_sources_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, (uint8_t *)&val->status_reg, 1); } - if (ret == 0) + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + return ret; } - if (ret == 0) + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_STATUS, - (uint8_t *)&val->emb_func_status, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_STATUS, + (uint8_t *)&val->emb_func_status, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_A, - (uint8_t *)&val->fsm_status_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_A, + (uint8_t *)&val->fsm_status_a, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_B, - (uint8_t *)&val->fsm_status_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_B, + (uint8_t *)&val->fsm_status_b, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_STATUS, - (uint8_t *)&val->mlc_status, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_STATUS, + (uint8_t *)&val->mlc_status, 1); + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + goto exit; } +exit: + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } @@ -1184,6 +1231,11 @@ int32_t asm330lhb_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.xlda; return ret; @@ -1204,6 +1256,11 @@ int32_t asm330lhb_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.gda; return ret; @@ -1224,6 +1281,11 @@ int32_t asm330lhb_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.tda; return ret; @@ -1245,13 +1307,18 @@ int32_t asm330lhb_boot_device_status_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.boot_check_fail; return ret; } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1268,7 +1335,7 @@ int32_t asm330lhb_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1285,7 +1352,7 @@ int32_t asm330lhb_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1302,7 +1369,7 @@ int32_t asm330lhb_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1319,7 +1386,7 @@ int32_t asm330lhb_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1336,7 +1403,7 @@ int32_t asm330lhb_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1388,6 +1455,11 @@ int32_t asm330lhb_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7_g.usr_off_on_out; return ret; @@ -1457,6 +1529,11 @@ int32_t asm330lhb_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl10_c.timestamp_en; return ret; @@ -1478,6 +1555,11 @@ int32_t asm330lhb_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_TIMESTAMP0, buff, 4); + if (ret != 0) + { + return ret; + } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1536,6 +1618,11 @@ int32_t asm330lhb_rounding_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5_c.rounding) { case ASM330LHB_NO_ROUND: @@ -1559,7 +1646,7 @@ int32_t asm330lhb_rounding_mode_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). - * L and H registers together express a 16-bit word in two’s + * L and H registers together express a 16-bit word in two's * complement.[get] * * @param ctx Read / write interface definitions.(ptr) @@ -1573,6 +1660,11 @@ int32_t asm330lhb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_OUT_TEMP_L, buff, 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1581,7 +1673,7 @@ int32_t asm330lhb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Angular rate sensor. The value is expressed as a 16-bit - * word in two’s complement.[get] + * word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1593,6 +1685,10 @@ int32_t asm330lhb_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[6]; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_OUTX_L_G, buff, 6); + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1606,7 +1702,7 @@ int32_t asm330lhb_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed as a - * 16-bit word in two’s complement.[get] + * 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1618,6 +1714,10 @@ int32_t asm330lhb_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[6]; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_OUTX_L_A, buff, 6); + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1699,6 +1799,11 @@ int32_t asm330lhb_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); + if (ret != 0) + { + return ret; + } + *val = internal_freq_fine.freq_fine; return ret; @@ -1747,6 +1852,11 @@ int32_t asm330lhb_mem_bank_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + switch (func_cfg_access.reg_access) { case ASM330LHB_USER_BANK: @@ -1774,56 +1884,7 @@ int32_t asm330lhb_mem_bank_get(const stmdev_ctx_t *ctx, int32_t asm330lhb_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { - asm330lhb_page_rw_t page_rw; - asm330lhb_page_sel_t page_sel; - asm330lhb_page_address_t page_address; - int32_t ret; - - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); - if (ret == 0) - { - ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x02U; /* page_write enable */ - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - if (ret == 0) - { - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_VALUE, val, 1); - } - if (ret == 0) - { - ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } - return ret; + return asm330lhb_ln_pg_write(ctx, add, val, 1); } /** @@ -1850,78 +1911,92 @@ int32_t asm330lhb_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, lsb = (uint8_t)(add - (msb * 256U)); ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + + /* set page write */ + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - page_rw.page_rw = 0x02U; /* page_write enable*/ - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + page_rw.page_rw = 0x02U; /* page_write enable*/ + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1); + goto exit; } - if (ret == 0) - { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { - page_address.page_addr = lsb; - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + goto exit; } + for (i = 0; i < len; i++) { - if (ret == 0) + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_VALUE, &buf[i], 1); - if (ret == 0) + goto exit; + } + + /* Check if page wrap */ + if (lsb == 0x00U) + { + msb++; + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - /* Check if page wrap */ - if (lsb == 0x00U) - { - msb++; - ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - lsb++; + goto exit; } - if (ret == 0) + + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; // Default value + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } } - } + lsb++; - if (ret == 0) - { - page_sel.page_sel = 0; - page_sel.not_used_01 = 1; - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); } - if (ret == 0) + + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; // Default value + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_rw.page_rw = 0x00U; /* page_write disable */ - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + + /* unset page write*/ + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + goto exit; } + page_rw.page_rw = 0x00U; /* page_write disable */ + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); return ret; } @@ -1943,49 +2018,55 @@ int32_t asm330lhb_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, int32_t ret; ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); - if (ret == 0) - { - ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x01U; /* page_read enable*/ - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - if (ret == 0) + + /* set page read */ + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_VALUE, val, 2); + goto exit; } - if (ret == 0) + page_rw.page_rw = 0x01U; /* page_read enable*/ + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + + /* set page addr */ + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret += asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { - page_rw.page_rw = 0x00U; /* page_read disable */ - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + + /* read value */ + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_VALUE, val, 2); + + /* unset page read */ + ret += asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + goto exit; } + page_rw.page_rw = 0x00U; /* page_read disable */ + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } @@ -2032,6 +2113,11 @@ int32_t asm330lhb_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + switch (counter_bdr_reg1.dataready_pulsed) { case ASM330LHB_DRDY_LATCHED: @@ -2098,6 +2184,11 @@ int32_t asm330lhb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.sw_reset; return ret; @@ -2141,6 +2232,11 @@ int32_t asm330lhb_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.if_inc; return ret; @@ -2182,6 +2278,11 @@ int32_t asm330lhb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.boot; return ret; @@ -2227,6 +2328,10 @@ int32_t asm330lhb_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_xl) { @@ -2284,6 +2389,10 @@ int32_t asm330lhb_gy_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_g) { @@ -2353,6 +2462,11 @@ int32_t asm330lhb_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl1_xl.lpf2_xl_en; return ret; @@ -2396,6 +2510,11 @@ int32_t asm330lhb_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.lpf1_sel_g; return ret; @@ -2440,6 +2559,11 @@ int32_t asm330lhb_filter_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.drdy_mask; return ret; @@ -2483,6 +2607,10 @@ int32_t asm330lhb_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.ftype) { @@ -2554,6 +2682,11 @@ int32_t asm330lhb_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.low_pass_on_6d; return ret; @@ -2602,6 +2735,11 @@ int32_t asm330lhb_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) + ctrl8_xl.hpcf_xl)) { @@ -2722,6 +2860,11 @@ int32_t asm330lhb_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.fastsettl_mode_xl; return ret; @@ -2768,6 +2911,11 @@ int32_t asm330lhb_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (int_cfg0.slope_fds) { case ASM330LHB_USE_SLOPE: @@ -2824,6 +2972,10 @@ int32_t asm330lhb_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g) { @@ -2900,6 +3052,10 @@ int32_t asm330lhb_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch (pin_ctrl.sdo_pu_en) { @@ -2955,6 +3111,10 @@ int32_t asm330lhb_int1_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); + if (ret != 0) + { + return ret; + } switch (i3c_bus_avb.pd_dis_int1) { @@ -3007,6 +3167,10 @@ int32_t asm330lhb_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhb_sim_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.sim) { @@ -3061,6 +3225,10 @@ int32_t asm330lhb_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4_c.i2c_disable) { @@ -3129,11 +3297,13 @@ int32_t asm330lhb_i3c_disable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - if (ret == 0) + ret += asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); + return ret; } + switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel) { case ASM330LHB_I3C_DISABLE: @@ -3188,81 +3358,90 @@ int32_t asm330lhb_pin_int1_route_set(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhb_write_reg(ctx, ASM330LHB_MLC_INT1, - (uint8_t *)&val->mlc_int1, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhb_write_reg(ctx, ASM330LHB_MLC_INT1, + (uint8_t *)&val->mlc_int1, 1); + if (ret != 0) { - ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INT1, - (uint8_t *)&val->emb_func_int1, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INT1, + (uint8_t *)&val->emb_func_int1, 1); + if (ret != 0) { - ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT1_A, - (uint8_t *)&val->fsm_int1_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT1_A, + (uint8_t *)&val->fsm_int1_a, 1); + if (ret != 0) { - ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT1_B, - (uint8_t *)&val->fsm_int1_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT1_B, + (uint8_t *)&val->fsm_int1_b, 1); + +exit: + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } - if (ret == 0) + if ((val->emb_func_int1.int1_fsm_lc + | val->fsm_int1_a.int1_fsm1 + | val->fsm_int1_a.int1_fsm2 + | val->fsm_int1_a.int1_fsm3 + | val->fsm_int1_a.int1_fsm4 + | val->fsm_int1_a.int1_fsm5 + | val->fsm_int1_a.int1_fsm6 + | val->fsm_int1_a.int1_fsm7 + | val->fsm_int1_a.int1_fsm8 + | val->fsm_int1_b.int1_fsm9 + | val->fsm_int1_b.int1_fsm10 + | val->fsm_int1_b.int1_fsm11 + | val->fsm_int1_b.int1_fsm12 + | val->fsm_int1_b.int1_fsm13 + | val->fsm_int1_b.int1_fsm14 + | val->fsm_int1_b.int1_fsm15 + | val->fsm_int1_b.int1_fsm16 + | val->mlc_int1.int1_mlc1 + | val->mlc_int1.int1_mlc2 + | val->mlc_int1.int1_mlc3 + | val->mlc_int1.int1_mlc4 + | val->mlc_int1.int1_mlc5 + | val->mlc_int1.int1_mlc6 + | val->mlc_int1.int1_mlc7 + | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE) { - if ((val->emb_func_int1.int1_fsm_lc - | val->fsm_int1_a.int1_fsm1 - | val->fsm_int1_a.int1_fsm2 - | val->fsm_int1_a.int1_fsm3 - | val->fsm_int1_a.int1_fsm4 - | val->fsm_int1_a.int1_fsm5 - | val->fsm_int1_a.int1_fsm6 - | val->fsm_int1_a.int1_fsm7 - | val->fsm_int1_a.int1_fsm8 - | val->fsm_int1_b.int1_fsm9 - | val->fsm_int1_b.int1_fsm10 - | val->fsm_int1_b.int1_fsm11 - | val->fsm_int1_b.int1_fsm12 - | val->fsm_int1_b.int1_fsm13 - | val->fsm_int1_b.int1_fsm14 - | val->fsm_int1_b.int1_fsm15 - | val->fsm_int1_b.int1_fsm16 - | val->mlc_int1.int1_mlc1 - | val->mlc_int1.int1_mlc2 - | val->mlc_int1.int1_mlc3 - | val->mlc_int1.int1_mlc4 - | val->mlc_int1.int1_mlc5 - | val->mlc_int1.int1_mlc6 - | val->mlc_int1.int1_mlc7 - | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE) - { - val->md1_cfg.int1_emb_func = PROPERTY_ENABLE; - } - else - { - val->md1_cfg.int1_emb_func = PROPERTY_DISABLE; - } - ret = asm330lhb_write_reg(ctx, ASM330LHB_INT1_CTRL, - (uint8_t *)&val->int1_ctrl, 1); + val->md1_cfg.int1_emb_func = PROPERTY_ENABLE; } - if (ret == 0) + else { - ret = asm330lhb_write_reg(ctx, ASM330LHB_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + val->md1_cfg.int1_emb_func = PROPERTY_DISABLE; } + ret = asm330lhb_write_reg(ctx, ASM330LHB_INT1_CTRL, + (uint8_t *)&val->int1_ctrl, 1); + if (ret != 0) + { + return ret; + } + ret = asm330lhb_write_reg(ctx, ASM330LHB_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); - if (ret == 0) + ret += asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1); + return ret; } - if (ret == 0) + ret = asm330lhb_pin_int2_route_get(ctx, &pin_int2_route); + if (ret != 0) { - ret = asm330lhb_pin_int2_route_get(ctx, &pin_int2_route); + return ret; } if (ret == 0) { @@ -3315,41 +3494,48 @@ int32_t asm330lhb_pin_int1_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_INT1, - (uint8_t *)&val->mlc_int1, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_INT1, + (uint8_t *)&val->mlc_int1, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INT1, - (uint8_t *)&val->emb_func_int1, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INT1, + (uint8_t *)&val->emb_func_int1, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT1_A, - (uint8_t *)&val->fsm_int1_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT1_A, + (uint8_t *)&val->fsm_int1_a, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT1_B, - (uint8_t *)&val->fsm_int1_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT1_B, + (uint8_t *)&val->fsm_int1_b, 1); + +exit: + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } - if (ret == 0) - { - ret = asm330lhb_read_reg(ctx, ASM330LHB_INT1_CTRL, - (uint8_t *)&val->int1_ctrl, 1); - } - if (ret == 0) + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT1_CTRL, + (uint8_t *)&val->int1_ctrl, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + return ret; } + ret = asm330lhb_read_reg(ctx, ASM330LHB_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + return ret; } @@ -3369,82 +3555,86 @@ int32_t asm330lhb_pin_int2_route_set(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhb_write_reg(ctx, ASM330LHB_MLC_INT2, - (uint8_t *)&val->mlc_int2, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhb_write_reg(ctx, ASM330LHB_MLC_INT2, + (uint8_t *)&val->mlc_int2, 1); + if (ret != 0) { - ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INT2, - (uint8_t *)&val->emb_func_int2, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INT2, + (uint8_t *)&val->emb_func_int2, 1); + if (ret != 0) { - ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT2_A, - (uint8_t *)&val->fsm_int2_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT2_A, + (uint8_t *)&val->fsm_int2_a, 1); + if (ret != 0) { - ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT2_B, - (uint8_t *)&val->fsm_int2_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT2_B, + (uint8_t *)&val->fsm_int2_b, 1); + +exit: + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } - if (ret == 0) + if ((val->emb_func_int2.int2_fsm_lc + | val->fsm_int2_a.int2_fsm1 + | val->fsm_int2_a.int2_fsm2 + | val->fsm_int2_a.int2_fsm3 + | val->fsm_int2_a.int2_fsm4 + | val->fsm_int2_a.int2_fsm5 + | val->fsm_int2_a.int2_fsm6 + | val->fsm_int2_a.int2_fsm7 + | val->fsm_int2_a.int2_fsm8 + | val->fsm_int2_b.int2_fsm9 + | val->fsm_int2_b.int2_fsm10 + | val->fsm_int2_b.int2_fsm11 + | val->fsm_int2_b.int2_fsm12 + | val->fsm_int2_b.int2_fsm13 + | val->fsm_int2_b.int2_fsm14 + | val->fsm_int2_b.int2_fsm15 + | val->fsm_int2_b.int2_fsm16 + | val->mlc_int2.int2_mlc1 + | val->mlc_int2.int2_mlc2 + | val->mlc_int2.int2_mlc3 + | val->mlc_int2.int2_mlc4 + | val->mlc_int2.int2_mlc5 + | val->mlc_int2.int2_mlc6 + | val->mlc_int2.int2_mlc7 + | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE) { - if ((val->emb_func_int2.int2_fsm_lc - | val->fsm_int2_a.int2_fsm1 - | val->fsm_int2_a.int2_fsm2 - | val->fsm_int2_a.int2_fsm3 - | val->fsm_int2_a.int2_fsm4 - | val->fsm_int2_a.int2_fsm5 - | val->fsm_int2_a.int2_fsm6 - | val->fsm_int2_a.int2_fsm7 - | val->fsm_int2_a.int2_fsm8 - | val->fsm_int2_b.int2_fsm9 - | val->fsm_int2_b.int2_fsm10 - | val->fsm_int2_b.int2_fsm11 - | val->fsm_int2_b.int2_fsm12 - | val->fsm_int2_b.int2_fsm13 - | val->fsm_int2_b.int2_fsm14 - | val->fsm_int2_b.int2_fsm15 - | val->fsm_int2_b.int2_fsm16 - | val->mlc_int2.int2_mlc1 - | val->mlc_int2.int2_mlc2 - | val->mlc_int2.int2_mlc3 - | val->mlc_int2.int2_mlc4 - | val->mlc_int2.int2_mlc5 - | val->mlc_int2.int2_mlc6 - | val->mlc_int2.int2_mlc7 - | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE) - { - val->md2_cfg.int2_emb_func = PROPERTY_ENABLE; - } - else - { - val->md2_cfg.int2_emb_func = PROPERTY_DISABLE; - } - ret = asm330lhb_write_reg(ctx, ASM330LHB_INT2_CTRL, - (uint8_t *)&val->int2_ctrl, 1); + val->md2_cfg.int2_emb_func = PROPERTY_ENABLE; } - if (ret == 0) + else { - ret = asm330lhb_write_reg(ctx, ASM330LHB_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + val->md2_cfg.int2_emb_func = PROPERTY_DISABLE; } - if (ret == 0) + ret = asm330lhb_write_reg(ctx, ASM330LHB_INT2_CTRL, + (uint8_t *)&val->int2_ctrl, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1); + return ret; } - - if (ret == 0) + ret = asm330lhb_write_reg(ctx, ASM330LHB_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + ret += asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1); + if (ret != 0) { - ret = asm330lhb_pin_int1_route_get(ctx, &pin_int1_route); + return ret; } + ret = asm330lhb_pin_int1_route_get(ctx, &pin_int1_route); + if (ret == 0) { if ((val->int2_ctrl.int2_cnt_bdr @@ -3496,40 +3686,47 @@ int32_t asm330lhb_pin_int2_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_INT2, - (uint8_t *)&val->mlc_int2, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_INT2, + (uint8_t *)&val->mlc_int2, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INT2, - (uint8_t *)&val->emb_func_int2, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INT2, + (uint8_t *)&val->emb_func_int2, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT2_A, - (uint8_t *)&val->fsm_int2_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT2_A, + (uint8_t *)&val->fsm_int2_a, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT2_B, - (uint8_t *)&val->fsm_int2_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT2_B, + (uint8_t *)&val->fsm_int2_b, 1); + +exit: + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } - if (ret == 0) - { - ret = asm330lhb_read_reg(ctx, ASM330LHB_INT2_CTRL, - (uint8_t *)&val->int2_ctrl, 1); - } - if (ret == 0) + ret = asm330lhb_read_reg(ctx, ASM330LHB_INT2_CTRL, + (uint8_t *)&val->int2_ctrl, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + return ret; } + ret = asm330lhb_read_reg(ctx, ASM330LHB_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + return ret; } @@ -3569,6 +3766,10 @@ int32_t asm330lhb_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhb_pp_od_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.pp_od) { @@ -3623,6 +3824,10 @@ int32_t asm330lhb_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.h_lactive) { @@ -3675,6 +3880,11 @@ int32_t asm330lhb_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.int2_on_int1; return ret; @@ -3696,30 +3906,34 @@ int32_t asm330lhb_int_notification_set(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1); - if (ret == 0) - { - int_cfg0.lir = (uint8_t)val & 0x01U; - int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; - ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0, - (uint8_t *)&int_cfg0, 1); - } - if (ret == 0) + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + return ret; } - if (ret == 0) + int_cfg0.lir = (uint8_t)val & 0x01U; + int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; + ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + return ret; } - if (ret == 0) + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + if (ret != 0) { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + goto exit; } + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); return ret; } @@ -3740,19 +3954,22 @@ int32_t asm330lhb_int_notification_get(const stmdev_ctx_t *ctx, *val = ASM330LHB_ALL_INT_PULSED; ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1); - - if (ret == 0) + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); + return ret; } + + ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1); } - if (ret == 0) + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } + switch ((page_rw.emb_func_lir << 1) + int_cfg0.lir) { case ASM330LHB_ALL_INT_PULSED: @@ -3832,6 +4049,10 @@ int32_t asm330lhb_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } switch (wake_up_dur.wake_ths_w) { @@ -3889,6 +4110,11 @@ int32_t asm330lhb_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.wk_ths; return ret; @@ -3934,6 +4160,11 @@ int32_t asm330lhb_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.usr_off_on_wu; return ret; @@ -3978,6 +4209,11 @@ int32_t asm330lhb_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.wake_dur; return ret; @@ -4032,6 +4268,11 @@ int32_t asm330lhb_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.sleep_g; return ret; @@ -4080,7 +4321,12 @@ int32_t asm330lhb_act_pin_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1); - switch (int_cfg0. sleep_status_on_int) + if (ret != 0) + { + return ret; + } + + switch (int_cfg0.sleep_status_on_int) { case ASM330LHB_DRIVE_SLEEP_CHG_EVENT: *val = ASM330LHB_DRIVE_SLEEP_CHG_EVENT; @@ -4132,6 +4378,10 @@ int32_t asm330lhb_act_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *)&int_cfg1, 1); + if (ret != 0) + { + return ret; + } switch (int_cfg1.inact_en) { @@ -4193,6 +4443,11 @@ int32_t asm330lhb_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.sleep_dur; return ret; @@ -4252,6 +4507,10 @@ int32_t asm330lhb_6d_threshold_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D, (uint8_t *)&ths_6d, 1); + if (ret != 0) + { + return ret; + } switch (ths_6d.sixd_ths) { @@ -4313,6 +4572,11 @@ int32_t asm330lhb_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D, (uint8_t *)&ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = ths_6d.d4d_en; return ret; @@ -4370,6 +4634,10 @@ int32_t asm330lhb_ff_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -4456,12 +4724,17 @@ int32_t asm330lhb_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - - if (ret == 0) + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, - (uint8_t *)&free_fall, 1); + return ret; + } + ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, + (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; } + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; return ret; @@ -4524,11 +4797,17 @@ int32_t asm330lhb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - if (ret == 0) + if (ret != 0) + { + return ret; + } + ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL1, - (uint8_t *)&fifo_ctrl1, 1); + return ret; } + *val = fifo_ctrl2.wtm; *val = (*val * 256U) + fifo_ctrl1.wtm; return ret; @@ -4576,6 +4855,11 @@ int32_t asm330lhb_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odrchg_en; return ret; @@ -4622,6 +4906,11 @@ int32_t asm330lhb_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -4670,6 +4959,10 @@ int32_t asm330lhb_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_xl) { @@ -4753,6 +5046,10 @@ int32_t asm330lhb_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_gy) { @@ -4834,6 +5131,10 @@ int32_t asm330lhb_fifo_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.fifo_mode) { @@ -4905,6 +5206,10 @@ int32_t asm330lhb_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.odr_t_batch) { @@ -4973,6 +5278,10 @@ int32_t asm330lhb_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.dec_ts_batch) { @@ -5040,6 +5349,10 @@ int32_t asm330lhb_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } switch (counter_bdr_reg1.trig_counter_bdr) { @@ -5097,6 +5410,11 @@ int32_t asm330lhb_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + *val = counter_bdr_reg1.rst_counter_bdr; return ret; @@ -5152,10 +5470,15 @@ int32_t asm330lhb_batch_counter_threshold_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); - if (ret == 0) + if (ret != 0) + { + return ret; + } + ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + if (ret != 0) { - ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); + return ret; } *val = counter_bdr_reg1.cnt_bdr_th; @@ -5303,6 +5626,10 @@ int32_t asm330lhb_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_data_out_tag, 1); + if (ret != 0) + { + return ret; + } switch (fifo_data_out_tag.tag_sensor) { @@ -5378,6 +5705,10 @@ int32_t asm330lhb_den_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.den_mode) { @@ -5442,6 +5773,10 @@ int32_t asm330lhb_den_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_lh) { @@ -5497,6 +5832,10 @@ int32_t asm330lhb_den_enable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_xl_g) { @@ -5553,6 +5892,11 @@ int32_t asm330lhb_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_z; return ret; @@ -5595,6 +5939,11 @@ int32_t asm330lhb_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_y; return ret; @@ -5636,6 +5985,11 @@ int32_t asm330lhb_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_x; return ret; @@ -5671,8 +6025,12 @@ int32_t asm330lhb_fsm_status_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_A_MAINPAGE, (uint8_t *)&status_a, 1); - ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_B_MAINPAGE, - (uint8_t *)&status_b, 1); + ret += asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_B_MAINPAGE, + (uint8_t *)&status_b, 1); + if (ret != 0) + { + return ret; + } val->fsm1 = status_a.is_fsm1; val->fsm2 = status_a.is_fsm2; @@ -5708,10 +6066,8 @@ int32_t asm330lhb_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_OUTS1, buff, 16); } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } @@ -5739,8 +6095,8 @@ int32_t asm330lhb_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_fsm_lc; - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); return ret; } @@ -5756,6 +6112,13 @@ int32_t asm330lhb_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&page_sel, 1); page_sel.emb_func_clk_dis = val; + page_sel.not_used_01 = 1; + + if (ret == 0) + { + ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } } ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); @@ -5774,7 +6137,10 @@ int32_t asm330lhb_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1); - *val = page_sel.emb_func_clk_dis; + if (ret == 0) + { + *val = page_sel.emb_func_clk_dis; + } } ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); @@ -5808,10 +6174,8 @@ int32_t asm330lhb_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } + + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); return ret; } @@ -5840,10 +6204,9 @@ int32_t asm330lhb_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } + + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } @@ -5902,16 +6265,13 @@ int32_t asm330lhb_fsm_enable_set(const stmdev_ctx_t *ctx, { emb_func_en_b.fsm_en = PROPERTY_DISABLE; } - } - if (ret == 0) - { + ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } + + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } @@ -5939,10 +6299,8 @@ int32_t asm330lhb_fsm_enable_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_ENABLE_B, (uint8_t *)&val->fsm_enable_b, 1); } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } @@ -5968,10 +6326,7 @@ int32_t asm330lhb_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_L, buff, 2); } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); return ret; } @@ -5993,13 +6348,13 @@ int32_t asm330lhb_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; - } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); return ret; } @@ -6030,10 +6385,8 @@ int32_t asm330lhb_long_clr_set(const stmdev_ctx_t *ctx, ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } @@ -6058,10 +6411,12 @@ int32_t asm330lhb_long_clr_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } + switch (fsm_long_counter_clear.fsm_lc_clr) { case ASM330LHB_LC_NORMAL: @@ -6109,10 +6464,8 @@ int32_t asm330lhb_fsm_data_rate_set(const stmdev_ctx_t *ctx, ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } @@ -6137,10 +6490,12 @@ int32_t asm330lhb_fsm_data_rate_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + if (ret != 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } + switch (emb_func_odr_cfg_b.fsm_odr) { case ASM330LHB_ODR_FSM_12Hz5: @@ -6188,10 +6543,8 @@ int32_t asm330lhb_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } @@ -6217,8 +6570,9 @@ int32_t asm330lhb_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_init_b.fsm_init; - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } @@ -6272,8 +6626,11 @@ int32_t asm330lhb_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; } @@ -6360,8 +6717,11 @@ int32_t asm330lhb_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_START_ADD_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; } @@ -6414,10 +6774,7 @@ int32_t asm330lhb_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); return ret; } @@ -6441,9 +6798,9 @@ int32_t asm330lhb_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) } if (ret == 0) { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); *val = reg.mlc_en; } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); return ret; } @@ -6487,10 +6844,7 @@ int32_t asm330lhb_mlc_data_rate_set(const stmdev_ctx_t *ctx, ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); return ret; } @@ -6515,6 +6869,8 @@ int32_t asm330lhb_mlc_data_rate_get(const stmdev_ctx_t *ctx, ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C, (uint8_t *)®, 1); } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + if (ret == 0) { switch (reg.mlc_odr) @@ -6535,8 +6891,8 @@ int32_t asm330lhb_mlc_data_rate_get(const stmdev_ctx_t *ctx, *val = ASM330LHB_ODR_PRGS_12Hz5; break; } - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); } + return ret; } @@ -6596,7 +6952,7 @@ int32_t asm330lhb_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val) *val = emb_func_init_b.mlc_init; } - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); return ret; } @@ -6616,10 +6972,8 @@ int32_t asm330lhb_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC0_SRC, buff, 8); } - if (ret == 0) - { - ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); - } + ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); + return ret; } @@ -6633,4 +6987,3 @@ int32_t asm330lhb_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.h b/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.h index 4ef8b5d..f56e2c3 100644 --- a/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.h +++ b/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2023 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -2696,4 +2698,3 @@ int32_t asm330lhb_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val #endif /* ASM330LHB_REGS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.c b/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.c index 9aa4442..c0cd635 100644 --- a/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.c +++ b/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2023 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -210,6 +209,11 @@ int32_t asm330lhbg1_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl1_xl.fs_xl) { case ASM330LHBG1_2g: @@ -367,11 +371,11 @@ int32_t asm330lhbg1_xl_data_rate_set(const stmdev_ctx_t *ctx, mlc_enable = PROPERTY_DISABLE; if (ret == 0) { - ret = asm330lhbg1_mlc_get(ctx, &mlc_enable); + ret = asm330lhbg1_mlc_get(ctx, &mlc_enable); if (mlc_enable == PROPERTY_ENABLE) { - ret = asm330lhbg1_mlc_data_rate_get(ctx, &mlc_odr); + ret += asm330lhbg1_mlc_data_rate_get(ctx, &mlc_odr); if (ret == 0) { switch (mlc_odr) @@ -488,6 +492,11 @@ int32_t asm330lhbg1_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl1_xl.odr_xl) { case ASM330LHBG1_XL_ODR_OFF: @@ -565,6 +574,11 @@ int32_t asm330lhbg1_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2_g.fs_g) { case ASM330LHBG1_125dps: @@ -850,6 +864,11 @@ int32_t asm330lhbg1_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2_g.odr_g) { case ASM330LHBG1_GY_ODR_OFF: @@ -922,6 +941,11 @@ int32_t asm330lhbg1_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.bdu; return ret; @@ -967,6 +991,10 @@ int32_t asm330lhbg1_xl_offset_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.usr_off_w) { @@ -1021,6 +1049,11 @@ int32_t asm330lhbg1_xl_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl6_c.xl_hm_mode) { case ASM330LHBG1_HIGH_PERFORMANCE_MD: @@ -1074,6 +1107,11 @@ int32_t asm330lhbg1_gy_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl7_g.g_hm_mode) { case ASM330LHBG1_GY_HIGH_PERFORMANCE: @@ -1121,35 +1159,44 @@ int32_t asm330lhbg1_all_sources_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_STATUS_REG, (uint8_t *)&val->status_reg, 1); } - if (ret == 0) + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + return ret; } - if (ret == 0) + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_STATUS, - (uint8_t *)&val->emb_func_status, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_STATUS, + (uint8_t *)&val->emb_func_status, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_STATUS_A, - (uint8_t *)&val->fsm_status_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_STATUS_A, + (uint8_t *)&val->fsm_status_a, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_STATUS_B, - (uint8_t *)&val->fsm_status_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_STATUS_B, + (uint8_t *)&val->fsm_status_b, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MLC_STATUS, - (uint8_t *)&val->mlc_status, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MLC_STATUS, + (uint8_t *)&val->mlc_status, 1); + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + goto exit; } +exit: + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } @@ -1184,6 +1231,11 @@ int32_t asm330lhbg1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.xlda; return ret; @@ -1204,6 +1256,11 @@ int32_t asm330lhbg1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.gda; return ret; @@ -1224,6 +1281,11 @@ int32_t asm330lhbg1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *v ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.tda; return ret; @@ -1245,13 +1307,18 @@ int32_t asm330lhbg1_boot_device_status_get(const stmdev_ctx_t *ctx, uint8_t *val ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.boot_check_fail; return ret; } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1268,7 +1335,7 @@ int32_t asm330lhbg1_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1285,7 +1352,7 @@ int32_t asm330lhbg1_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1302,7 +1369,7 @@ int32_t asm330lhbg1_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1319,7 +1386,7 @@ int32_t asm330lhbg1_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1336,7 +1403,7 @@ int32_t asm330lhbg1_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1388,6 +1455,11 @@ int32_t asm330lhbg1_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7_g.usr_off_on_out; return ret; @@ -1457,6 +1529,11 @@ int32_t asm330lhbg1_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl10_c.timestamp_en; return ret; @@ -1478,6 +1555,11 @@ int32_t asm330lhbg1_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_TIMESTAMP0, buff, 4); + if (ret != 0) + { + return ret; + } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1536,6 +1618,11 @@ int32_t asm330lhbg1_rounding_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5_c.rounding) { case ASM330LHBG1_NO_ROUND: @@ -1559,7 +1646,7 @@ int32_t asm330lhbg1_rounding_mode_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). - * L and H registers together express a 16-bit word in two’s + * L and H registers together express a 16-bit word in two's * complement.[get] * * @param ctx Read / write interface definitions.(ptr) @@ -1573,6 +1660,11 @@ int32_t asm330lhbg1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_OUT_TEMP_L, buff, 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1581,7 +1673,7 @@ int32_t asm330lhbg1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Angular rate sensor. The value is expressed as a 16-bit - * word in two’s complement.[get] + * word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1593,6 +1685,10 @@ int32_t asm330lhbg1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[6]; int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_OUTX_L_G, buff, 6); + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1606,7 +1702,7 @@ int32_t asm330lhbg1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed as a - * 16-bit word in two’s complement.[get] + * 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1618,6 +1714,10 @@ int32_t asm330lhbg1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[6]; int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_OUTX_L_A, buff, 6); + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1699,6 +1799,11 @@ int32_t asm330lhbg1_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); + if (ret != 0) + { + return ret; + } + *val = internal_freq_fine.freq_fine; return ret; @@ -1747,6 +1852,11 @@ int32_t asm330lhbg1_mem_bank_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + switch (func_cfg_access.reg_access) { case ASM330LHBG1_USER_BANK: @@ -1774,56 +1884,7 @@ int32_t asm330lhbg1_mem_bank_get(const stmdev_ctx_t *ctx, int32_t asm330lhbg1_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { - asm330lhbg1_page_rw_t page_rw; - asm330lhbg1_page_sel_t page_sel; - asm330lhbg1_page_address_t page_address; - int32_t ret; - - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); - if (ret == 0) - { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x02U; /* page_write enable */ - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - if (ret == 0) - { - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_VALUE, val, 1); - } - if (ret == 0) - { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } - return ret; + return asm330lhbg1_ln_pg_write(ctx, add, val, 1); } /** @@ -1850,78 +1911,92 @@ int32_t asm330lhbg1_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, lsb = (uint8_t)(add - (msb * 256U)); ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + + /* set page write */ + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - page_rw.page_rw = 0x02U; /* page_write enable*/ - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + page_rw.page_rw = 0x02U; /* page_write enable*/ + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, (uint8_t *)&page_sel, 1); + goto exit; } - if (ret == 0) - { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { - page_address.page_addr = lsb; - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + goto exit; } + for (i = 0; i < len; i++) { - if (ret == 0) + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_VALUE, &buf[i], 1); - if (ret == 0) + goto exit; + } + + /* Check if page wrap */ + if (lsb == 0x00U) + { + msb++; + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - /* Check if page wrap */ - if (lsb == 0x00U) - { - msb++; - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - lsb++; + goto exit; } - if (ret == 0) + + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; // Default value + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } } - } + lsb++; - if (ret == 0) - { - page_sel.page_sel = 0; - page_sel.not_used_01 = 1; - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); } - if (ret == 0) + + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; // Default value + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_rw.page_rw = 0x00U; /* page_write disable */ - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + + /* unset page write*/ + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + goto exit; } + page_rw.page_rw = 0x00U; /* page_write disable */ + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); return ret; } @@ -1943,49 +2018,55 @@ int32_t asm330lhbg1_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, int32_t ret; ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); - if (ret == 0) - { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x01U; /* page_read enable*/ - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - if (ret == 0) + + /* set page read */ + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_VALUE, val, 2); + goto exit; } - if (ret == 0) + page_rw.page_rw = 0x01U; /* page_read enable*/ + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + + /* set page addr */ + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret += asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { - page_rw.page_rw = 0x00U; /* page_read disable */ - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + + /* read value */ + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_VALUE, val, 2); + + /* unset page read */ + ret += asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + goto exit; } + page_rw.page_rw = 0x00U; /* page_read disable */ + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } @@ -2032,6 +2113,11 @@ int32_t asm330lhbg1_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + switch (counter_bdr_reg1.dataready_pulsed) { case ASM330LHBG1_DRDY_LATCHED: @@ -2098,6 +2184,11 @@ int32_t asm330lhbg1_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.sw_reset; return ret; @@ -2141,6 +2232,11 @@ int32_t asm330lhbg1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.if_inc; return ret; @@ -2182,6 +2278,11 @@ int32_t asm330lhbg1_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.boot; return ret; @@ -2227,6 +2328,10 @@ int32_t asm330lhbg1_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_xl) { @@ -2284,6 +2389,10 @@ int32_t asm330lhbg1_gy_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_g) { @@ -2353,6 +2462,11 @@ int32_t asm330lhbg1_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl1_xl.lpf2_xl_en; return ret; @@ -2396,6 +2510,11 @@ int32_t asm330lhbg1_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.lpf1_sel_g; return ret; @@ -2440,6 +2559,11 @@ int32_t asm330lhbg1_filter_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.drdy_mask; return ret; @@ -2483,6 +2607,10 @@ int32_t asm330lhbg1_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.ftype) { @@ -2554,6 +2682,11 @@ int32_t asm330lhbg1_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.low_pass_on_6d; return ret; @@ -2602,6 +2735,11 @@ int32_t asm330lhbg1_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) + ctrl8_xl.hpcf_xl)) { @@ -2722,6 +2860,11 @@ int32_t asm330lhbg1_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.fastsettl_mode_xl; return ret; @@ -2768,6 +2911,11 @@ int32_t asm330lhbg1_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (int_cfg0.slope_fds) { case ASM330LHBG1_USE_SLOPE: @@ -2824,6 +2972,10 @@ int32_t asm330lhbg1_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g) { @@ -2900,6 +3052,10 @@ int32_t asm330lhbg1_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch (pin_ctrl.sdo_pu_en) { @@ -2955,6 +3111,10 @@ int32_t asm330lhbg1_int1_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); + if (ret != 0) + { + return ret; + } switch (i3c_bus_avb.pd_dis_int1) { @@ -3007,6 +3167,10 @@ int32_t asm330lhbg1_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhbg1_sim_t *val int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.sim) { @@ -3061,6 +3225,10 @@ int32_t asm330lhbg1_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4_c.i2c_disable) { @@ -3129,11 +3297,13 @@ int32_t asm330lhbg1_i3c_disable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - if (ret == 0) + ret += asm330lhbg1_read_reg(ctx, ASM330LHBG1_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); + return ret; } + switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel) { case ASM330LHBG1_I3C_DISABLE: @@ -3188,81 +3358,90 @@ int32_t asm330lhbg1_pin_int1_route_set(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MLC_INT1, - (uint8_t *)&val->mlc_int1, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MLC_INT1, + (uint8_t *)&val->mlc_int1, 1); + if (ret != 0) { - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_INT1, - (uint8_t *)&val->emb_func_int1, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_INT1, + (uint8_t *)&val->emb_func_int1, 1); + if (ret != 0) { - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_INT1_A, - (uint8_t *)&val->fsm_int1_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_INT1_A, + (uint8_t *)&val->fsm_int1_a, 1); + if (ret != 0) { - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_INT1_B, - (uint8_t *)&val->fsm_int1_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_INT1_B, + (uint8_t *)&val->fsm_int1_b, 1); + +exit: + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } - if (ret == 0) + if ((val->emb_func_int1.int1_fsm_lc + | val->fsm_int1_a.int1_fsm1 + | val->fsm_int1_a.int1_fsm2 + | val->fsm_int1_a.int1_fsm3 + | val->fsm_int1_a.int1_fsm4 + | val->fsm_int1_a.int1_fsm5 + | val->fsm_int1_a.int1_fsm6 + | val->fsm_int1_a.int1_fsm7 + | val->fsm_int1_a.int1_fsm8 + | val->fsm_int1_b.int1_fsm9 + | val->fsm_int1_b.int1_fsm10 + | val->fsm_int1_b.int1_fsm11 + | val->fsm_int1_b.int1_fsm12 + | val->fsm_int1_b.int1_fsm13 + | val->fsm_int1_b.int1_fsm14 + | val->fsm_int1_b.int1_fsm15 + | val->fsm_int1_b.int1_fsm16 + | val->mlc_int1.int1_mlc1 + | val->mlc_int1.int1_mlc2 + | val->mlc_int1.int1_mlc3 + | val->mlc_int1.int1_mlc4 + | val->mlc_int1.int1_mlc5 + | val->mlc_int1.int1_mlc6 + | val->mlc_int1.int1_mlc7 + | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE) { - if ((val->emb_func_int1.int1_fsm_lc - | val->fsm_int1_a.int1_fsm1 - | val->fsm_int1_a.int1_fsm2 - | val->fsm_int1_a.int1_fsm3 - | val->fsm_int1_a.int1_fsm4 - | val->fsm_int1_a.int1_fsm5 - | val->fsm_int1_a.int1_fsm6 - | val->fsm_int1_a.int1_fsm7 - | val->fsm_int1_a.int1_fsm8 - | val->fsm_int1_b.int1_fsm9 - | val->fsm_int1_b.int1_fsm10 - | val->fsm_int1_b.int1_fsm11 - | val->fsm_int1_b.int1_fsm12 - | val->fsm_int1_b.int1_fsm13 - | val->fsm_int1_b.int1_fsm14 - | val->fsm_int1_b.int1_fsm15 - | val->fsm_int1_b.int1_fsm16 - | val->mlc_int1.int1_mlc1 - | val->mlc_int1.int1_mlc2 - | val->mlc_int1.int1_mlc3 - | val->mlc_int1.int1_mlc4 - | val->mlc_int1.int1_mlc5 - | val->mlc_int1.int1_mlc6 - | val->mlc_int1.int1_mlc7 - | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE) - { - val->md1_cfg.int1_emb_func = PROPERTY_ENABLE; - } - else - { - val->md1_cfg.int1_emb_func = PROPERTY_DISABLE; - } - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT1_CTRL, - (uint8_t *)&val->int1_ctrl, 1); + val->md1_cfg.int1_emb_func = PROPERTY_ENABLE; } - if (ret == 0) + else { - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + val->md1_cfg.int1_emb_func = PROPERTY_DISABLE; } + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT1_CTRL, + (uint8_t *)&val->int1_ctrl, 1); + if (ret != 0) + { + return ret; + } + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); - if (ret == 0) + ret += asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *) &int_cfg1, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *) &int_cfg1, 1); + return ret; } - if (ret == 0) + ret = asm330lhbg1_pin_int2_route_get(ctx, &pin_int2_route); + if (ret != 0) { - ret = asm330lhbg1_pin_int2_route_get(ctx, &pin_int2_route); + return ret; } if (ret == 0) { @@ -3315,41 +3494,48 @@ int32_t asm330lhbg1_pin_int1_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MLC_INT1, - (uint8_t *)&val->mlc_int1, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MLC_INT1, + (uint8_t *)&val->mlc_int1, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_INT1, - (uint8_t *)&val->emb_func_int1, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_INT1, + (uint8_t *)&val->emb_func_int1, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_INT1_A, - (uint8_t *)&val->fsm_int1_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_INT1_A, + (uint8_t *)&val->fsm_int1_a, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_INT1_B, - (uint8_t *)&val->fsm_int1_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_INT1_B, + (uint8_t *)&val->fsm_int1_b, 1); + +exit: + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } - if (ret == 0) - { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT1_CTRL, - (uint8_t *)&val->int1_ctrl, 1); - } - if (ret == 0) + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT1_CTRL, + (uint8_t *)&val->int1_ctrl, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + return ret; } + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + return ret; } @@ -3369,82 +3555,86 @@ int32_t asm330lhbg1_pin_int2_route_set(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MLC_INT2, - (uint8_t *)&val->mlc_int2, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MLC_INT2, + (uint8_t *)&val->mlc_int2, 1); + if (ret != 0) { - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_INT2, - (uint8_t *)&val->emb_func_int2, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_INT2, + (uint8_t *)&val->emb_func_int2, 1); + if (ret != 0) { - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_INT2_A, - (uint8_t *)&val->fsm_int2_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_INT2_A, + (uint8_t *)&val->fsm_int2_a, 1); + if (ret != 0) { - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_INT2_B, - (uint8_t *)&val->fsm_int2_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_INT2_B, + (uint8_t *)&val->fsm_int2_b, 1); + +exit: + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } - if (ret == 0) + if ((val->emb_func_int2.int2_fsm_lc + | val->fsm_int2_a.int2_fsm1 + | val->fsm_int2_a.int2_fsm2 + | val->fsm_int2_a.int2_fsm3 + | val->fsm_int2_a.int2_fsm4 + | val->fsm_int2_a.int2_fsm5 + | val->fsm_int2_a.int2_fsm6 + | val->fsm_int2_a.int2_fsm7 + | val->fsm_int2_a.int2_fsm8 + | val->fsm_int2_b.int2_fsm9 + | val->fsm_int2_b.int2_fsm10 + | val->fsm_int2_b.int2_fsm11 + | val->fsm_int2_b.int2_fsm12 + | val->fsm_int2_b.int2_fsm13 + | val->fsm_int2_b.int2_fsm14 + | val->fsm_int2_b.int2_fsm15 + | val->fsm_int2_b.int2_fsm16 + | val->mlc_int2.int2_mlc1 + | val->mlc_int2.int2_mlc2 + | val->mlc_int2.int2_mlc3 + | val->mlc_int2.int2_mlc4 + | val->mlc_int2.int2_mlc5 + | val->mlc_int2.int2_mlc6 + | val->mlc_int2.int2_mlc7 + | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE) { - if ((val->emb_func_int2.int2_fsm_lc - | val->fsm_int2_a.int2_fsm1 - | val->fsm_int2_a.int2_fsm2 - | val->fsm_int2_a.int2_fsm3 - | val->fsm_int2_a.int2_fsm4 - | val->fsm_int2_a.int2_fsm5 - | val->fsm_int2_a.int2_fsm6 - | val->fsm_int2_a.int2_fsm7 - | val->fsm_int2_a.int2_fsm8 - | val->fsm_int2_b.int2_fsm9 - | val->fsm_int2_b.int2_fsm10 - | val->fsm_int2_b.int2_fsm11 - | val->fsm_int2_b.int2_fsm12 - | val->fsm_int2_b.int2_fsm13 - | val->fsm_int2_b.int2_fsm14 - | val->fsm_int2_b.int2_fsm15 - | val->fsm_int2_b.int2_fsm16 - | val->mlc_int2.int2_mlc1 - | val->mlc_int2.int2_mlc2 - | val->mlc_int2.int2_mlc3 - | val->mlc_int2.int2_mlc4 - | val->mlc_int2.int2_mlc5 - | val->mlc_int2.int2_mlc6 - | val->mlc_int2.int2_mlc7 - | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE) - { - val->md2_cfg.int2_emb_func = PROPERTY_ENABLE; - } - else - { - val->md2_cfg.int2_emb_func = PROPERTY_DISABLE; - } - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT2_CTRL, - (uint8_t *)&val->int2_ctrl, 1); + val->md2_cfg.int2_emb_func = PROPERTY_ENABLE; } - if (ret == 0) + else { - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + val->md2_cfg.int2_emb_func = PROPERTY_DISABLE; } - if (ret == 0) + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT2_CTRL, + (uint8_t *)&val->int2_ctrl, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *) &int_cfg1, 1); + return ret; } - - if (ret == 0) + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + ret += asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *) &int_cfg1, 1); + if (ret != 0) { - ret = asm330lhbg1_pin_int1_route_get(ctx, &pin_int1_route); + return ret; } + ret = asm330lhbg1_pin_int1_route_get(ctx, &pin_int1_route); + if (ret == 0) { if ((val->int2_ctrl.int2_cnt_bdr @@ -3496,40 +3686,47 @@ int32_t asm330lhbg1_pin_int2_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MLC_INT2, - (uint8_t *)&val->mlc_int2, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MLC_INT2, + (uint8_t *)&val->mlc_int2, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_INT2, - (uint8_t *)&val->emb_func_int2, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_INT2, + (uint8_t *)&val->emb_func_int2, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_INT2_A, - (uint8_t *)&val->fsm_int2_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_INT2_A, + (uint8_t *)&val->fsm_int2_a, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_INT2_B, - (uint8_t *)&val->fsm_int2_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_INT2_B, + (uint8_t *)&val->fsm_int2_b, 1); + +exit: + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } - if (ret == 0) - { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT2_CTRL, - (uint8_t *)&val->int2_ctrl, 1); - } - if (ret == 0) + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT2_CTRL, + (uint8_t *)&val->int2_ctrl, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + return ret; } + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + return ret; } @@ -3569,6 +3766,10 @@ int32_t asm330lhbg1_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhbg1_pp_od_t *v int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.pp_od) { @@ -3623,6 +3824,10 @@ int32_t asm330lhbg1_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.h_lactive) { @@ -3675,6 +3880,11 @@ int32_t asm330lhbg1_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.int2_on_int1; return ret; @@ -3696,30 +3906,34 @@ int32_t asm330lhbg1_int_notification_set(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); - if (ret == 0) - { - int_cfg0.lir = (uint8_t)val & 0x01U; - int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT_CFG0, - (uint8_t *)&int_cfg0, 1); - } - if (ret == 0) + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + return ret; } - if (ret == 0) + int_cfg0.lir = (uint8_t)val & 0x01U; + int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + return ret; } - if (ret == 0) + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret != 0) { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + goto exit; } + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); return ret; } @@ -3740,19 +3954,22 @@ int32_t asm330lhbg1_int_notification_get(const stmdev_ctx_t *ctx, *val = ASM330LHBG1_ALL_INT_PULSED; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); - - if (ret == 0) + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + return ret; } + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); if (ret == 0) { ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); } - if (ret == 0) + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } + switch ((page_rw.emb_func_lir << 1) + int_cfg0.lir) { case ASM330LHBG1_ALL_INT_PULSED: @@ -3832,6 +4049,10 @@ int32_t asm330lhbg1_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } switch (wake_up_dur.wake_ths_w) { @@ -3889,6 +4110,11 @@ int32_t asm330lhbg1_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.wk_ths; return ret; @@ -3934,6 +4160,11 @@ int32_t asm330lhbg1_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.usr_off_on_wu; return ret; @@ -3978,6 +4209,11 @@ int32_t asm330lhbg1_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.wake_dur; return ret; @@ -4032,6 +4268,11 @@ int32_t asm330lhbg1_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.sleep_g; return ret; @@ -4080,7 +4321,12 @@ int32_t asm330lhbg1_act_pin_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); - switch (int_cfg0. sleep_status_on_int) + if (ret != 0) + { + return ret; + } + + switch (int_cfg0.sleep_status_on_int) { case ASM330LHBG1_DRIVE_SLEEP_CHG_EVENT: *val = ASM330LHBG1_DRIVE_SLEEP_CHG_EVENT; @@ -4132,6 +4378,10 @@ int32_t asm330lhbg1_act_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *)&int_cfg1, 1); + if (ret != 0) + { + return ret; + } switch (int_cfg1.inact_en) { @@ -4193,6 +4443,11 @@ int32_t asm330lhbg1_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.sleep_dur; return ret; @@ -4252,6 +4507,10 @@ int32_t asm330lhbg1_6d_threshold_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_THS_6D, (uint8_t *)&ths_6d, 1); + if (ret != 0) + { + return ret; + } switch (ths_6d.sixd_ths) { @@ -4313,6 +4572,11 @@ int32_t asm330lhbg1_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_THS_6D, (uint8_t *)&ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = ths_6d.d4d_en; return ret; @@ -4370,6 +4634,10 @@ int32_t asm330lhbg1_ff_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -4456,12 +4724,17 @@ int32_t asm330lhbg1_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - - if (ret == 0) + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FREE_FALL, - (uint8_t *)&free_fall, 1); + return ret; + } + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FREE_FALL, + (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; } + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; return ret; @@ -4524,11 +4797,17 @@ int32_t asm330lhbg1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - if (ret == 0) + if (ret != 0) + { + return ret; + } + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL1, - (uint8_t *)&fifo_ctrl1, 1); + return ret; } + *val = fifo_ctrl2.wtm; *val = (*val * 256U) + fifo_ctrl1.wtm; return ret; @@ -4576,6 +4855,11 @@ int32_t asm330lhbg1_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odrchg_en; return ret; @@ -4622,6 +4906,11 @@ int32_t asm330lhbg1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -4670,6 +4959,10 @@ int32_t asm330lhbg1_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_xl) { @@ -4753,6 +5046,10 @@ int32_t asm330lhbg1_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_gy) { @@ -4834,6 +5131,10 @@ int32_t asm330lhbg1_fifo_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.fifo_mode) { @@ -4905,6 +5206,10 @@ int32_t asm330lhbg1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.odr_t_batch) { @@ -4973,6 +5278,10 @@ int32_t asm330lhbg1_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.dec_ts_batch) { @@ -5040,6 +5349,10 @@ int32_t asm330lhbg1_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } switch (counter_bdr_reg1.trig_counter_bdr) { @@ -5097,6 +5410,11 @@ int32_t asm330lhbg1_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + *val = counter_bdr_reg1.rst_counter_bdr; return ret; @@ -5152,10 +5470,15 @@ int32_t asm330lhbg1_batch_counter_threshold_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); - if (ret == 0) + if (ret != 0) + { + return ret; + } + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + if (ret != 0) { - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); + return ret; } *val = counter_bdr_reg1.cnt_bdr_th; @@ -5303,6 +5626,10 @@ int32_t asm330lhbg1_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_data_out_tag, 1); + if (ret != 0) + { + return ret; + } switch (fifo_data_out_tag.tag_sensor) { @@ -5378,6 +5705,10 @@ int32_t asm330lhbg1_den_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.den_mode) { @@ -5442,6 +5773,10 @@ int32_t asm330lhbg1_den_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_lh) { @@ -5497,6 +5832,10 @@ int32_t asm330lhbg1_den_enable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_xl_g) { @@ -5553,6 +5892,11 @@ int32_t asm330lhbg1_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_z; return ret; @@ -5595,6 +5939,11 @@ int32_t asm330lhbg1_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_y; return ret; @@ -5636,6 +5985,11 @@ int32_t asm330lhbg1_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_x; return ret; @@ -5671,8 +6025,12 @@ int32_t asm330lhbg1_fsm_status_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_STATUS_A_MAINPAGE, (uint8_t *)&status_a, 1); - ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_STATUS_B_MAINPAGE, - (uint8_t *)&status_b, 1); + ret += asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_STATUS_B_MAINPAGE, + (uint8_t *)&status_b, 1); + if (ret != 0) + { + return ret; + } val->fsm1 = status_a.is_fsm1; val->fsm2 = status_a.is_fsm2; @@ -5708,10 +6066,8 @@ int32_t asm330lhbg1_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_OUTS1, buff, 16); } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } @@ -5739,8 +6095,8 @@ int32_t asm330lhbg1_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_fsm_lc; - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); return ret; } @@ -5756,6 +6112,13 @@ int32_t asm330lhbg1_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&page_sel, 1); page_sel.emb_func_clk_dis = val; + page_sel.not_used_01 = 1; + + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } } ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); @@ -5774,7 +6137,10 @@ int32_t asm330lhbg1_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, (uint8_t *)&page_sel, 1); - *val = page_sel.emb_func_clk_dis; + if (ret == 0) + { + *val = page_sel.emb_func_clk_dis; + } } ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); @@ -5808,10 +6174,8 @@ int32_t asm330lhbg1_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } + + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); return ret; } @@ -5840,10 +6204,9 @@ int32_t asm330lhbg1_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } + + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } @@ -5902,16 +6265,13 @@ int32_t asm330lhbg1_fsm_enable_set(const stmdev_ctx_t *ctx, { emb_func_en_b.fsm_en = PROPERTY_DISABLE; } - } - if (ret == 0) - { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } + + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } @@ -5939,10 +6299,8 @@ int32_t asm330lhbg1_fsm_enable_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_ENABLE_B, (uint8_t *)&val->fsm_enable_b, 1); } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } @@ -5968,10 +6326,7 @@ int32_t asm330lhbg1_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_LONG_COUNTER_L, buff, 2); } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); return ret; } @@ -5993,13 +6348,13 @@ int32_t asm330lhbg1_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_LONG_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; - } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); return ret; } @@ -6030,10 +6385,8 @@ int32_t asm330lhbg1_long_clr_set(const stmdev_ctx_t *ctx, ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_LONG_COUNTER_CLEAR, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } @@ -6058,10 +6411,12 @@ int32_t asm330lhbg1_long_clr_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_LONG_COUNTER_CLEAR, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } + switch (fsm_long_counter_clear.fsm_lc_clr) { case ASM330LHBG1_LC_NORMAL: @@ -6109,10 +6464,8 @@ int32_t asm330lhbg1_fsm_data_rate_set(const stmdev_ctx_t *ctx, ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_ODR_CFG_B, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } @@ -6137,10 +6490,12 @@ int32_t asm330lhbg1_fsm_data_rate_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_ODR_CFG_B, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + if (ret != 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } + switch (emb_func_odr_cfg_b.fsm_odr) { case ASM330LHBG1_ODR_FSM_12Hz5: @@ -6188,10 +6543,8 @@ int32_t asm330lhbg1_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } @@ -6217,8 +6570,9 @@ int32_t asm330lhbg1_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_init_b.fsm_init; - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } @@ -6272,8 +6626,11 @@ int32_t asm330lhbg1_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *va { ret = asm330lhbg1_ln_pg_read_byte(ctx, ASM330LHBG1_FSM_LC_TIMEOUT_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; } @@ -6360,8 +6717,11 @@ int32_t asm330lhbg1_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val if (ret == 0) { ret = asm330lhbg1_ln_pg_read_byte(ctx, ASM330LHBG1_FSM_START_ADD_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; } @@ -6414,10 +6774,7 @@ int32_t asm330lhbg1_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); return ret; } @@ -6441,9 +6798,9 @@ int32_t asm330lhbg1_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) } if (ret == 0) { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); *val = reg.mlc_en; } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); return ret; } @@ -6487,10 +6844,7 @@ int32_t asm330lhbg1_mlc_data_rate_set(const stmdev_ctx_t *ctx, ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_ODR_CFG_C, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); return ret; } @@ -6515,6 +6869,8 @@ int32_t asm330lhbg1_mlc_data_rate_get(const stmdev_ctx_t *ctx, ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_ODR_CFG_C, (uint8_t *)®, 1); } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + if (ret == 0) { switch (reg.mlc_odr) @@ -6535,8 +6891,8 @@ int32_t asm330lhbg1_mlc_data_rate_get(const stmdev_ctx_t *ctx, *val = ASM330LHBG1_ODR_PRGS_12Hz5; break; } - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); } + return ret; } @@ -6596,7 +6952,7 @@ int32_t asm330lhbg1_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val) *val = emb_func_init_b.mlc_init; } - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); return ret; } @@ -6616,10 +6972,8 @@ int32_t asm330lhbg1_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MLC0_SRC, buff, 8); } - if (ret == 0) - { - ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); - } + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + return ret; } @@ -6633,4 +6987,3 @@ int32_t asm330lhbg1_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.h b/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.h index af1dca8..66b9f35 100644 --- a/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.h +++ b/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2023 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -2696,4 +2698,3 @@ int32_t asm330lhbg1_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *v #endif /* ASM330LHBG1_REGS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c index 1bef2d4..abe0a90 100644 --- a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c +++ b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2023 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -210,6 +209,11 @@ int32_t asm330lhh_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl1_xl.fs_xl) { case ASM330LHH_2g: @@ -274,6 +278,11 @@ int32_t asm330lhh_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl1_xl.odr_xl) { case ASM330LHH_XL_ODR_OFF: @@ -354,6 +363,11 @@ int32_t asm330lhh_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2_g.fs_g) { case ASM330LHH_125dps: @@ -423,6 +437,11 @@ int32_t asm330lhh_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2_g.odr_g) { case ASM330LHH_GY_ODR_OFF: @@ -501,6 +520,11 @@ int32_t asm330lhh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.bdu; return ret; @@ -546,6 +570,10 @@ int32_t asm330lhh_xl_offset_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.usr_off_w) { @@ -629,6 +657,11 @@ int32_t asm330lhh_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhh_read_reg(ctx, ASM330LHH_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.xlda; return ret; @@ -649,6 +682,11 @@ int32_t asm330lhh_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhh_read_reg(ctx, ASM330LHH_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.gda; return ret; @@ -669,13 +707,18 @@ int32_t asm330lhh_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val ret = asm330lhh_read_reg(ctx, ASM330LHH_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.tda; return ret; } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -692,7 +735,7 @@ int32_t asm330lhh_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -709,7 +752,7 @@ int32_t asm330lhh_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -726,7 +769,7 @@ int32_t asm330lhh_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -743,7 +786,7 @@ int32_t asm330lhh_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -760,7 +803,7 @@ int32_t asm330lhh_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -812,6 +855,11 @@ int32_t asm330lhh_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7_g.usr_off_on_out; return ret; @@ -881,6 +929,11 @@ int32_t asm330lhh_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl10_c.timestamp_en; return ret; @@ -902,6 +955,11 @@ int32_t asm330lhh_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_TIMESTAMP0, buff, 4); + if (ret != 0) + { + return ret; + } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -960,6 +1018,11 @@ int32_t asm330lhh_rounding_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5_c.rounding) { case ASM330LHH_NO_ROUND: @@ -983,7 +1046,7 @@ int32_t asm330lhh_rounding_mode_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). - * L and H registers together express a 16-bit word in two’s + * L and H registers together express a 16-bit word in two's * complement.[get] * * @param ctx Read / write interface definitions.(ptr) @@ -997,6 +1060,11 @@ int32_t asm330lhh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_OUT_TEMP_L, buff, 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1005,7 +1073,7 @@ int32_t asm330lhh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Angular rate sensor. The value is expressed as a 16-bit - * word in two’s complement.[get] + * word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1017,6 +1085,10 @@ int32_t asm330lhh_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[6]; int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_OUTX_L_G, buff, 6); + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1030,7 +1102,7 @@ int32_t asm330lhh_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed as a - * 16-bit word in two’s complement.[get] + * 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1042,6 +1114,10 @@ int32_t asm330lhh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[6]; int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_OUTX_L_A, buff, 6); + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1121,6 +1197,11 @@ int32_t asm330lhh_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.device_conf; return ret; @@ -1169,6 +1250,11 @@ int32_t asm330lhh_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhh_read_reg(ctx, ASM330LHH_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); + if (ret != 0) + { + return ret; + } + *val = internal_freq_fine.freq_fine; return ret; @@ -1217,6 +1303,11 @@ int32_t asm330lhh_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + switch (counter_bdr_reg1.dataready_pulsed) { case ASM330LHH_DRDY_LATCHED: @@ -1283,6 +1374,11 @@ int32_t asm330lhh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.sw_reset; return ret; @@ -1326,6 +1422,11 @@ int32_t asm330lhh_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.if_inc; return ret; @@ -1367,6 +1468,11 @@ int32_t asm330lhh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.boot; return ret; @@ -1412,6 +1518,10 @@ int32_t asm330lhh_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_xl) { @@ -1469,6 +1579,10 @@ int32_t asm330lhh_gy_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_g) { @@ -1538,6 +1652,11 @@ int32_t asm330lhh_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl1_xl.lpf2_xl_en; return ret; @@ -1581,6 +1700,11 @@ int32_t asm330lhh_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.lpf1_sel_g; return ret; @@ -1625,6 +1749,11 @@ int32_t asm330lhh_filter_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.drdy_mask; return ret; @@ -1668,6 +1797,10 @@ int32_t asm330lhh_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.ftype) { @@ -1739,6 +1872,11 @@ int32_t asm330lhh_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.low_pass_on_6d; return ret; @@ -1787,6 +1925,11 @@ int32_t asm330lhh_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) + ctrl8_xl.hpcf_xl)) { @@ -1907,6 +2050,11 @@ int32_t asm330lhh_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.fastsettl_mode_xl; return ret; @@ -1953,6 +2101,11 @@ int32_t asm330lhh_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (int_cfg0.slope_fds) { case ASM330LHH_USE_SLOPE: @@ -2009,6 +2162,10 @@ int32_t asm330lhh_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g) { @@ -2085,6 +2242,10 @@ int32_t asm330lhh_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch (pin_ctrl.sdo_pu_en) { @@ -2137,6 +2298,10 @@ int32_t asm330lhh_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhh_sim_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.sim) { @@ -2191,6 +2356,10 @@ int32_t asm330lhh_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4_c.i2c_disable) { @@ -2237,9 +2406,10 @@ int32_t asm330lhh_pin_int1_route_set(const stmdev_ctx_t *ctx, ret = asm330lhh_write_reg(ctx, ASM330LHH_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); - if (ret == 0) + ret += asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG1, (uint8_t *) &int_cfg1, 1); + if (ret != 0) { - ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG1, (uint8_t *) &int_cfg1, 1); + return ret; } if (ret == 0) @@ -2283,11 +2453,13 @@ int32_t asm330lhh_pin_int1_route_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_INT1_CTRL, (uint8_t *)&val->int1_ctrl, 1); - if (ret == 0) + if (ret != 0) { - ret = asm330lhh_read_reg(ctx, ASM330LHH_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + return ret; } + ret = asm330lhh_read_reg(ctx, ASM330LHH_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + return ret; } @@ -2308,19 +2480,18 @@ int32_t asm330lhh_pin_int2_route_set(const stmdev_ctx_t *ctx, ret = asm330lhh_write_reg(ctx, ASM330LHH_INT2_CTRL, (uint8_t *)&val->int2_ctrl, 1); - if (ret == 0) + if (ret != 0) { - ret = asm330lhh_write_reg(ctx, ASM330LHH_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + return ret; } - if (ret == 0) + ret = asm330lhh_write_reg(ctx, ASM330LHH_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + ret += asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG1, (uint8_t *) &int_cfg1, 1); + if (ret != 0) { - ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG1, (uint8_t *) &int_cfg1, 1); + return ret; } - if (ret == 0) - { - ret = asm330lhh_pin_int1_route_get(ctx, &pin_int1_route); - } + ret = asm330lhh_pin_int1_route_get(ctx, &pin_int1_route); if (ret == 0) { @@ -2374,10 +2545,12 @@ int32_t asm330lhh_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_INT2_CTRL, (uint8_t *)&val->int2_ctrl, 1); - if (ret == 0) + if (ret != 0) { - ret = asm330lhh_read_reg(ctx, ASM330LHH_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + return ret; } + ret = asm330lhh_read_reg(ctx, ASM330LHH_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + return ret; } @@ -2417,6 +2590,10 @@ int32_t asm330lhh_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhh_pp_od_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.pp_od) { @@ -2471,6 +2648,10 @@ int32_t asm330lhh_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.h_lactive) { @@ -2523,6 +2704,11 @@ int32_t asm330lhh_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.int2_on_int1; return ret; @@ -2543,12 +2729,17 @@ int32_t asm330lhh_int_notification_set(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0, (uint8_t *)&int_cfg0, 1); - if (ret == 0) + if (ret != 0) { - int_cfg0.lir = (uint8_t)val & 0x01U; - int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; - ret = asm330lhh_write_reg(ctx, ASM330LHH_INT_CFG0, - (uint8_t *)&int_cfg0, 1); + return ret; + } + int_cfg0.lir = (uint8_t)val & 0x01U; + int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; + ret = asm330lhh_write_reg(ctx, ASM330LHH_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + if (ret != 0) + { + return ret; } return ret; } @@ -2569,6 +2760,10 @@ int32_t asm330lhh_int_notification_get(const stmdev_ctx_t *ctx, *val = ASM330LHH_ALL_INT_PULSED; ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret != 0) + { + return ret; + } switch ((int_cfg0.lir << 1) + int_cfg0.int_clr_on_read) { @@ -2649,6 +2844,10 @@ int32_t asm330lhh_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } switch (wake_up_dur.wake_ths_w) { @@ -2706,6 +2905,11 @@ int32_t asm330lhh_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.wk_ths; return ret; @@ -2751,6 +2955,11 @@ int32_t asm330lhh_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.usr_off_on_wu; return ret; @@ -2795,6 +3004,11 @@ int32_t asm330lhh_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.wake_dur; return ret; @@ -2849,6 +3063,11 @@ int32_t asm330lhh_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.sleep_g; return ret; @@ -2897,7 +3116,12 @@ int32_t asm330lhh_act_pin_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG0, (uint8_t *)&int_cfg0, 1); - switch (int_cfg0. sleep_status_on_int) + if (ret != 0) + { + return ret; + } + + switch (int_cfg0.sleep_status_on_int) { case ASM330LHH_DRIVE_SLEEP_CHG_EVENT: *val = ASM330LHH_DRIVE_SLEEP_CHG_EVENT; @@ -2949,6 +3173,10 @@ int32_t asm330lhh_act_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_INT_CFG1, (uint8_t *)&int_cfg1, 1); + if (ret != 0) + { + return ret; + } switch (int_cfg1.inact_en) { @@ -3010,6 +3238,11 @@ int32_t asm330lhh_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.sleep_dur; return ret; @@ -3069,6 +3302,10 @@ int32_t asm330lhh_6d_threshold_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_THS_6D, (uint8_t *)&ths_6d, 1); + if (ret != 0) + { + return ret; + } switch (ths_6d.sixd_ths) { @@ -3130,6 +3367,11 @@ int32_t asm330lhh_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhh_read_reg(ctx, ASM330LHH_THS_6D, (uint8_t *)&ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = ths_6d.d4d_en; return ret; @@ -3187,6 +3429,10 @@ int32_t asm330lhh_ff_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -3273,12 +3519,17 @@ int32_t asm330lhh_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhh_read_reg(ctx, ASM330LHH_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - - if (ret == 0) + if (ret != 0) { - ret = asm330lhh_read_reg(ctx, ASM330LHH_FREE_FALL, - (uint8_t *)&free_fall, 1); + return ret; + } + ret = asm330lhh_read_reg(ctx, ASM330LHH_FREE_FALL, + (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; } + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; return ret; @@ -3341,11 +3592,17 @@ int32_t asm330lhh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - if (ret == 0) + if (ret != 0) { - ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL1, - (uint8_t *)&fifo_ctrl1, 1); + return ret; } + ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.wtm; *val = (*val * 256U) + fifo_ctrl1.wtm; return ret; @@ -3393,6 +3650,11 @@ int32_t asm330lhh_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odrchg_en; return ret; @@ -3439,6 +3701,11 @@ int32_t asm330lhh_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -3487,6 +3754,10 @@ int32_t asm330lhh_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_xl) { @@ -3573,6 +3844,10 @@ int32_t asm330lhh_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_gy) { @@ -3660,6 +3935,10 @@ int32_t asm330lhh_fifo_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.fifo_mode) { @@ -3731,6 +4010,10 @@ int32_t asm330lhh_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.odr_t_batch) { @@ -3799,6 +4082,10 @@ int32_t asm330lhh_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.dec_ts_batch) { @@ -3866,6 +4153,10 @@ int32_t asm330lhh_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } switch (counter_bdr_reg1.trig_counter_bdr) { @@ -3923,6 +4214,11 @@ int32_t asm330lhh_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + *val = counter_bdr_reg1.rst_counter_bdr; return ret; @@ -3978,10 +4274,15 @@ int32_t asm330lhh_batch_counter_threshold_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); - if (ret == 0) + if (ret != 0) { - ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); + return ret; + } + ret = asm330lhh_read_reg(ctx, ASM330LHH_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + if (ret != 0) + { + return ret; } *val = counter_bdr_reg1.cnt_bdr_th; @@ -4129,6 +4430,10 @@ int32_t asm330lhh_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ret = asm330lhh_read_reg(ctx, ASM330LHH_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_data_out_tag, 1); + if (ret != 0) + { + return ret; + } switch (fifo_data_out_tag.tag_sensor) { @@ -4204,6 +4509,10 @@ int32_t asm330lhh_den_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.den_mode) { @@ -4268,6 +4577,10 @@ int32_t asm330lhh_den_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_lh) { @@ -4323,6 +4636,10 @@ int32_t asm330lhh_den_enable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_xl_g) { @@ -4379,6 +4696,11 @@ int32_t asm330lhh_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_z; return ret; @@ -4421,6 +4743,11 @@ int32_t asm330lhh_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_y; return ret; @@ -4462,6 +4789,11 @@ int32_t asm330lhh_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhh_read_reg(ctx, ASM330LHH_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_x; return ret; @@ -4477,4 +4809,3 @@ int32_t asm330lhh_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h index abf7000..f85900f 100644 --- a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h +++ b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2023 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1500,4 +1502,3 @@ int32_t asm330lhh_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif /* ASM330LHH_REGS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.c b/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.c index 6af1411..fd13090 100644 --- a/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.c +++ b/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2023 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -210,6 +209,11 @@ int32_t asm330lhhx_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl1_xl.fs_xl) { case ASM330LHHX_2g: @@ -367,11 +371,11 @@ int32_t asm330lhhx_xl_data_rate_set(const stmdev_ctx_t *ctx, mlc_enable = PROPERTY_DISABLE; if (ret == 0) { - ret = asm330lhhx_mlc_get(ctx, &mlc_enable); + ret = asm330lhhx_mlc_get(ctx, &mlc_enable); if (mlc_enable == PROPERTY_ENABLE) { - ret = asm330lhhx_mlc_data_rate_get(ctx, &mlc_odr); + ret += asm330lhhx_mlc_data_rate_get(ctx, &mlc_odr); if (ret == 0) { switch (mlc_odr) @@ -488,6 +492,11 @@ int32_t asm330lhhx_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl1_xl.odr_xl) { case ASM330LHHX_XL_ODR_OFF: @@ -571,6 +580,11 @@ int32_t asm330lhhx_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2_g.fs_g) { case ASM330LHHX_125dps: @@ -856,6 +870,11 @@ int32_t asm330lhhx_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2_g.odr_g) { case ASM330LHHX_GY_ODR_OFF: @@ -934,6 +953,11 @@ int32_t asm330lhhx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.bdu; return ret; @@ -979,6 +1003,10 @@ int32_t asm330lhhx_xl_offset_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.usr_off_w) { @@ -1033,6 +1061,11 @@ int32_t asm330lhhx_xl_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl6_c.xl_hm_mode) { case ASM330LHHX_HIGH_PERFORMANCE_MD: @@ -1086,6 +1119,11 @@ int32_t asm330lhhx_gy_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl7_g.g_hm_mode) { case ASM330LHHX_GY_HIGH_PERFORMANCE: @@ -1133,35 +1171,44 @@ int32_t asm330lhhx_all_sources_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_STATUS_REG, (uint8_t *)&val->status_reg, 1); } - if (ret == 0) + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); + return ret; } - if (ret == 0) + ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_STATUS, - (uint8_t *)&val->emb_func_status, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_STATUS, + (uint8_t *)&val->emb_func_status, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_A, - (uint8_t *)&val->fsm_status_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_A, + (uint8_t *)&val->fsm_status_a, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_B, - (uint8_t *)&val->fsm_status_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_B, + (uint8_t *)&val->fsm_status_b, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MLC_STATUS, - (uint8_t *)&val->mlc_status, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MLC_STATUS, + (uint8_t *)&val->mlc_status, 1); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + goto exit; } +exit: + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -1196,6 +1243,11 @@ int32_t asm330lhhx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhx_read_reg(ctx, ASM330LHHX_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.xlda; return ret; @@ -1216,6 +1268,11 @@ int32_t asm330lhhx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhx_read_reg(ctx, ASM330LHHX_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.gda; return ret; @@ -1236,13 +1293,18 @@ int32_t asm330lhhx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *va ret = asm330lhhx_read_reg(ctx, ASM330LHHX_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.tda; return ret; } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1259,7 +1321,7 @@ int32_t asm330lhhx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1276,7 +1338,7 @@ int32_t asm330lhhx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1293,7 +1355,7 @@ int32_t asm330lhhx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1310,7 +1372,7 @@ int32_t asm330lhhx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1327,7 +1389,7 @@ int32_t asm330lhhx_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1379,6 +1441,11 @@ int32_t asm330lhhx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7_g.usr_off_on_out; return ret; @@ -1448,6 +1515,11 @@ int32_t asm330lhhx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl10_c.timestamp_en; return ret; @@ -1469,6 +1541,11 @@ int32_t asm330lhhx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_TIMESTAMP0, buff, 4); + if (ret != 0) + { + return ret; + } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1527,6 +1604,11 @@ int32_t asm330lhhx_rounding_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5_c.rounding) { case ASM330LHHX_NO_ROUND: @@ -1550,7 +1632,7 @@ int32_t asm330lhhx_rounding_mode_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). - * L and H registers together express a 16-bit word in two’s + * L and H registers together express a 16-bit word in two's * complement.[get] * * @param ctx Read / write interface definitions.(ptr) @@ -1564,6 +1646,11 @@ int32_t asm330lhhx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_OUT_TEMP_L, buff, 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1572,7 +1659,7 @@ int32_t asm330lhhx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Angular rate sensor. The value is expressed as a 16-bit - * word in two’s complement.[get] + * word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1584,6 +1671,10 @@ int32_t asm330lhhx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[6]; int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_OUTX_L_G, buff, 6); + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1597,7 +1688,7 @@ int32_t asm330lhhx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed as a - * 16-bit word in two’s complement.[get] + * 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1609,6 +1700,10 @@ int32_t asm330lhhx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[6]; int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_OUTX_L_A, buff, 6); + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1690,6 +1785,11 @@ int32_t asm330lhhx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); + if (ret != 0) + { + return ret; + } + *val = internal_freq_fine.freq_fine; return ret; @@ -1738,6 +1838,11 @@ int32_t asm330lhhx_mem_bank_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + switch (func_cfg_access.reg_access) { case ASM330LHHX_USER_BANK: @@ -1768,56 +1873,7 @@ int32_t asm330lhhx_mem_bank_get(const stmdev_ctx_t *ctx, int32_t asm330lhhx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { - asm330lhhx_page_rw_t page_rw; - asm330lhhx_page_sel_t page_sel; - asm330lhhx_page_address_t page_address; - int32_t ret; - - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); - if (ret == 0) - { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x02U; /* page_write enable */ - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL, (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - if (ret == 0) - { - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_VALUE, val, 1); - } - if (ret == 0) - { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } - return ret; + return asm330lhhx_ln_pg_write(ctx, add, val, 1); } /** @@ -1844,78 +1900,92 @@ int32_t asm330lhhx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, lsb = (uint8_t)(add - (msb * 256U)); ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); - if (ret == 0) - { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) + if (ret != 0) { - page_rw.page_rw = 0x02U; /* page_write enable*/ - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + + /* set page write */ + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL, (uint8_t *)&page_sel, 1); + goto exit; } - if (ret == 0) + page_rw.page_rw = 0x02U; /* page_write enable*/ + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { - page_address.page_addr = lsb; - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + goto exit; } + for (i = 0; i < len; i++) { - if (ret == 0) + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_VALUE, &buf[i], 1); - if (ret == 0) + goto exit; + } + + /* Check if page wrap */ + if (lsb == 0x00U) + { + msb++; + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - /* Check if page wrap */ - if (lsb == 0x00U) - { - msb++; - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - lsb++; + goto exit; } - if (ret == 0) + + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; // Default value + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } } - } + lsb++; - if (ret == 0) - { - page_sel.page_sel = 0; - page_sel.not_used_01 = 1; - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); } - if (ret == 0) + + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; // Default value + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_rw.page_rw = 0x00U; /* page_write disable */ - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + + /* unset page write*/ + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + goto exit; } + page_rw.page_rw = 0x00U; /* page_write disable */ + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -1937,49 +2007,55 @@ int32_t asm330lhhx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, int32_t ret; ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x01U; /* page_read enable*/ - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL, (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + goto exit; } - if (ret == 0) + + /* set page read */ + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_VALUE, val, 2); + goto exit; } - if (ret == 0) + page_rw.page_rw = 0x01U; /* page_read enable*/ + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + + /* set page addr */ + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret += asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { - page_rw.page_rw = 0x00U; /* page_read disable */ - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + + /* read value */ + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_VALUE, val, 2); + + /* unset page read */ + ret += asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + goto exit; } + page_rw.page_rw = 0x00U; /* page_read disable */ + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -2026,6 +2102,11 @@ int32_t asm330lhhx_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + switch (counter_bdr_reg1.dataready_pulsed) { case ASM330LHHX_DRDY_LATCHED: @@ -2092,6 +2173,11 @@ int32_t asm330lhhx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.sw_reset; return ret; @@ -2135,6 +2221,11 @@ int32_t asm330lhhx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.if_inc; return ret; @@ -2176,6 +2267,11 @@ int32_t asm330lhhx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.boot; return ret; @@ -2221,6 +2317,10 @@ int32_t asm330lhhx_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_xl) { @@ -2278,6 +2378,10 @@ int32_t asm330lhhx_gy_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_g) { @@ -2347,6 +2451,11 @@ int32_t asm330lhhx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl1_xl.lpf2_xl_en; return ret; @@ -2390,6 +2499,11 @@ int32_t asm330lhhx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.lpf1_sel_g; return ret; @@ -2434,6 +2548,11 @@ int32_t asm330lhhx_filter_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.drdy_mask; return ret; @@ -2477,6 +2596,10 @@ int32_t asm330lhhx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.ftype) { @@ -2548,6 +2671,11 @@ int32_t asm330lhhx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.low_pass_on_6d; return ret; @@ -2596,6 +2724,11 @@ int32_t asm330lhhx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) + ctrl8_xl.hpcf_xl)) { @@ -2716,6 +2849,11 @@ int32_t asm330lhhx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.fastsettl_mode_xl; return ret; @@ -2762,6 +2900,11 @@ int32_t asm330lhhx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (int_cfg0.slope_fds) { case ASM330LHHX_USE_SLOPE: @@ -2818,6 +2961,10 @@ int32_t asm330lhhx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g) { @@ -2894,6 +3041,10 @@ int32_t asm330lhhx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch (pin_ctrl.sdo_pu_en) { @@ -2949,6 +3100,10 @@ int32_t asm330lhhx_int1_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); + if (ret != 0) + { + return ret; + } switch (i3c_bus_avb.pd_dis_int1) { @@ -3001,6 +3156,10 @@ int32_t asm330lhhx_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_sim_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.sim) { @@ -3055,6 +3214,10 @@ int32_t asm330lhhx_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4_c.i2c_disable) { @@ -3123,11 +3286,13 @@ int32_t asm330lhhx_i3c_disable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - if (ret == 0) + ret += asm330lhhx_read_reg(ctx, ASM330LHHX_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); + return ret; } + switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel) { case ASM330LHHX_I3C_DISABLE: @@ -3182,81 +3347,90 @@ int32_t asm330lhhx_pin_int1_route_set(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MLC_INT1, - (uint8_t *)&val->mlc_int1, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MLC_INT1, + (uint8_t *)&val->mlc_int1, 1); + if (ret != 0) { - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_INT1, - (uint8_t *)&val->emb_func_int1, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_INT1, + (uint8_t *)&val->emb_func_int1, 1); + if (ret != 0) { - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_INT1_A, - (uint8_t *)&val->fsm_int1_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_INT1_A, + (uint8_t *)&val->fsm_int1_a, 1); + if (ret != 0) { - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_INT1_B, - (uint8_t *)&val->fsm_int1_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_INT1_B, + (uint8_t *)&val->fsm_int1_b, 1); + +exit: + ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } - if (ret == 0) + if ((val->emb_func_int1.int1_fsm_lc + | val->fsm_int1_a.int1_fsm1 + | val->fsm_int1_a.int1_fsm2 + | val->fsm_int1_a.int1_fsm3 + | val->fsm_int1_a.int1_fsm4 + | val->fsm_int1_a.int1_fsm5 + | val->fsm_int1_a.int1_fsm6 + | val->fsm_int1_a.int1_fsm7 + | val->fsm_int1_a.int1_fsm8 + | val->fsm_int1_b.int1_fsm9 + | val->fsm_int1_b.int1_fsm10 + | val->fsm_int1_b.int1_fsm11 + | val->fsm_int1_b.int1_fsm12 + | val->fsm_int1_b.int1_fsm13 + | val->fsm_int1_b.int1_fsm14 + | val->fsm_int1_b.int1_fsm15 + | val->fsm_int1_b.int1_fsm16 + | val->mlc_int1.int1_mlc1 + | val->mlc_int1.int1_mlc2 + | val->mlc_int1.int1_mlc3 + | val->mlc_int1.int1_mlc4 + | val->mlc_int1.int1_mlc5 + | val->mlc_int1.int1_mlc6 + | val->mlc_int1.int1_mlc7 + | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE) { - if ((val->emb_func_int1.int1_fsm_lc - | val->fsm_int1_a.int1_fsm1 - | val->fsm_int1_a.int1_fsm2 - | val->fsm_int1_a.int1_fsm3 - | val->fsm_int1_a.int1_fsm4 - | val->fsm_int1_a.int1_fsm5 - | val->fsm_int1_a.int1_fsm6 - | val->fsm_int1_a.int1_fsm7 - | val->fsm_int1_a.int1_fsm8 - | val->fsm_int1_b.int1_fsm9 - | val->fsm_int1_b.int1_fsm10 - | val->fsm_int1_b.int1_fsm11 - | val->fsm_int1_b.int1_fsm12 - | val->fsm_int1_b.int1_fsm13 - | val->fsm_int1_b.int1_fsm14 - | val->fsm_int1_b.int1_fsm15 - | val->fsm_int1_b.int1_fsm16 - | val->mlc_int1.int1_mlc1 - | val->mlc_int1.int1_mlc2 - | val->mlc_int1.int1_mlc3 - | val->mlc_int1.int1_mlc4 - | val->mlc_int1.int1_mlc5 - | val->mlc_int1.int1_mlc6 - | val->mlc_int1.int1_mlc7 - | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE) - { - val->md1_cfg.int1_emb_func = PROPERTY_ENABLE; - } - else - { - val->md1_cfg.int1_emb_func = PROPERTY_DISABLE; - } - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT1_CTRL, - (uint8_t *)&val->int1_ctrl, 1); + val->md1_cfg.int1_emb_func = PROPERTY_ENABLE; } - if (ret == 0) + else { - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + val->md1_cfg.int1_emb_func = PROPERTY_DISABLE; } + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT1_CTRL, + (uint8_t *)&val->int1_ctrl, 1); + if (ret != 0) + { + return ret; + } + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); - if (ret == 0) + ret += asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG1, (uint8_t *) &int_cfg1, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG1, (uint8_t *) &int_cfg1, 1); + return ret; } - if (ret == 0) + ret = asm330lhhx_pin_int2_route_get(ctx, &pin_int2_route); + if (ret != 0) { - ret = asm330lhhx_pin_int2_route_get(ctx, &pin_int2_route); + return ret; } if (ret == 0) { @@ -3310,41 +3484,48 @@ int32_t asm330lhhx_pin_int1_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MLC_INT1, - (uint8_t *)&val->mlc_int1, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MLC_INT1, + (uint8_t *)&val->mlc_int1, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_INT1, - (uint8_t *)&val->emb_func_int1, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_INT1, + (uint8_t *)&val->emb_func_int1, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_INT1_A, - (uint8_t *)&val->fsm_int1_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_INT1_A, + (uint8_t *)&val->fsm_int1_a, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_INT1_B, - (uint8_t *)&val->fsm_int1_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_INT1_B, + (uint8_t *)&val->fsm_int1_b, 1); + +exit: + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } - if (ret == 0) - { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT1_CTRL, - (uint8_t *)&val->int1_ctrl, 1); - } - if (ret == 0) + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT1_CTRL, + (uint8_t *)&val->int1_ctrl, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + return ret; } + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + return ret; } @@ -3364,82 +3545,86 @@ int32_t asm330lhhx_pin_int2_route_set(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MLC_INT2, - (uint8_t *)&val->mlc_int2, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MLC_INT2, + (uint8_t *)&val->mlc_int2, 1); + if (ret != 0) { - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_INT2, - (uint8_t *)&val->emb_func_int2, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_INT2, + (uint8_t *)&val->emb_func_int2, 1); + if (ret != 0) { - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_INT2_A, - (uint8_t *)&val->fsm_int2_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_INT2_A, + (uint8_t *)&val->fsm_int2_a, 1); + if (ret != 0) { - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_INT2_B, - (uint8_t *)&val->fsm_int2_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_INT2_B, + (uint8_t *)&val->fsm_int2_b, 1); + +exit: + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } - if (ret == 0) + if ((val->emb_func_int2.int2_fsm_lc + | val->fsm_int2_a.int2_fsm1 + | val->fsm_int2_a.int2_fsm2 + | val->fsm_int2_a.int2_fsm3 + | val->fsm_int2_a.int2_fsm4 + | val->fsm_int2_a.int2_fsm5 + | val->fsm_int2_a.int2_fsm6 + | val->fsm_int2_a.int2_fsm7 + | val->fsm_int2_a.int2_fsm8 + | val->fsm_int2_b.int2_fsm9 + | val->fsm_int2_b.int2_fsm10 + | val->fsm_int2_b.int2_fsm11 + | val->fsm_int2_b.int2_fsm12 + | val->fsm_int2_b.int2_fsm13 + | val->fsm_int2_b.int2_fsm14 + | val->fsm_int2_b.int2_fsm15 + | val->fsm_int2_b.int2_fsm16 + | val->mlc_int2.int2_mlc1 + | val->mlc_int2.int2_mlc2 + | val->mlc_int2.int2_mlc3 + | val->mlc_int2.int2_mlc4 + | val->mlc_int2.int2_mlc5 + | val->mlc_int2.int2_mlc6 + | val->mlc_int2.int2_mlc7 + | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE) { - if ((val->emb_func_int2.int2_fsm_lc - | val->fsm_int2_a.int2_fsm1 - | val->fsm_int2_a.int2_fsm2 - | val->fsm_int2_a.int2_fsm3 - | val->fsm_int2_a.int2_fsm4 - | val->fsm_int2_a.int2_fsm5 - | val->fsm_int2_a.int2_fsm6 - | val->fsm_int2_a.int2_fsm7 - | val->fsm_int2_a.int2_fsm8 - | val->fsm_int2_b.int2_fsm9 - | val->fsm_int2_b.int2_fsm10 - | val->fsm_int2_b.int2_fsm11 - | val->fsm_int2_b.int2_fsm12 - | val->fsm_int2_b.int2_fsm13 - | val->fsm_int2_b.int2_fsm14 - | val->fsm_int2_b.int2_fsm15 - | val->fsm_int2_b.int2_fsm16 - | val->mlc_int2.int2_mlc1 - | val->mlc_int2.int2_mlc2 - | val->mlc_int2.int2_mlc3 - | val->mlc_int2.int2_mlc4 - | val->mlc_int2.int2_mlc5 - | val->mlc_int2.int2_mlc6 - | val->mlc_int2.int2_mlc7 - | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE) - { - val->md2_cfg.int2_emb_func = PROPERTY_ENABLE; - } - else - { - val->md2_cfg.int2_emb_func = PROPERTY_DISABLE; - } - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT2_CTRL, - (uint8_t *)&val->int2_ctrl, 1); + val->md2_cfg.int2_emb_func = PROPERTY_ENABLE; } - if (ret == 0) + else { - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + val->md2_cfg.int2_emb_func = PROPERTY_DISABLE; } - if (ret == 0) + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT2_CTRL, + (uint8_t *)&val->int2_ctrl, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG1, (uint8_t *) &int_cfg1, 1); + return ret; } - - if (ret == 0) + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + ret += asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG1, (uint8_t *) &int_cfg1, 1); + if (ret != 0) { - ret = asm330lhhx_pin_int1_route_get(ctx, &pin_int1_route); + return ret; } + ret = asm330lhhx_pin_int1_route_get(ctx, &pin_int1_route); + if (ret == 0) { if ((val->int2_ctrl.int2_cnt_bdr @@ -3491,40 +3676,47 @@ int32_t asm330lhhx_pin_int2_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); - if (ret == 0) + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MLC_INT2, - (uint8_t *)&val->mlc_int2, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MLC_INT2, + (uint8_t *)&val->mlc_int2, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_INT2, - (uint8_t *)&val->emb_func_int2, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_INT2, + (uint8_t *)&val->emb_func_int2, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_INT2_A, - (uint8_t *)&val->fsm_int2_a, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_INT2_A, + (uint8_t *)&val->fsm_int2_a, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_INT2_B, - (uint8_t *)&val->fsm_int2_b, 1); + goto exit; } - if (ret == 0) + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_INT2_B, + (uint8_t *)&val->fsm_int2_b, 1); + +exit: + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } - if (ret == 0) - { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT2_CTRL, - (uint8_t *)&val->int2_ctrl, 1); - } - if (ret == 0) + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT2_CTRL, + (uint8_t *)&val->int2_ctrl, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + return ret; } + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + return ret; } @@ -3564,6 +3756,10 @@ int32_t asm330lhhx_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_pp_od_t *val int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.pp_od) { @@ -3618,6 +3814,10 @@ int32_t asm330lhhx_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.h_lactive) { @@ -3670,6 +3870,11 @@ int32_t asm330lhhx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.int2_on_int1; return ret; @@ -3691,30 +3896,34 @@ int32_t asm330lhhx_int_notification_set(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG0, (uint8_t *)&int_cfg0, 1); - if (ret == 0) - { - int_cfg0.lir = (uint8_t)val & 0x01U; - int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT_CFG0, - (uint8_t *)&int_cfg0, 1); - } - if (ret == 0) + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); + return ret; } - if (ret == 0) + int_cfg0.lir = (uint8_t)val & 0x01U; + int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + return ret; } - if (ret == 0) + ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); + if (ret != 0) { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + goto exit; } + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -3735,19 +3944,22 @@ int32_t asm330lhhx_int_notification_get(const stmdev_ctx_t *ctx, *val = ASM330LHHX_ALL_INT_PULSED; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG0, (uint8_t *)&int_cfg0, 1); - - if (ret == 0) + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); + return ret; } + + ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); if (ret == 0) { ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1); } - if (ret == 0) + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } + switch ((page_rw.emb_func_lir << 1) + int_cfg0.lir) { case ASM330LHHX_ALL_INT_PULSED: @@ -3827,6 +4039,10 @@ int32_t asm330lhhx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } switch (wake_up_dur.wake_ths_w) { @@ -3884,6 +4100,11 @@ int32_t asm330lhhx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.wk_ths; return ret; @@ -3929,6 +4150,11 @@ int32_t asm330lhhx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.usr_off_on_wu; return ret; @@ -3973,6 +4199,11 @@ int32_t asm330lhhx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.wake_dur; return ret; @@ -4027,6 +4258,11 @@ int32_t asm330lhhx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.sleep_g; return ret; @@ -4075,7 +4311,12 @@ int32_t asm330lhhx_act_pin_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG0, (uint8_t *)&int_cfg0, 1); - switch (int_cfg0. sleep_status_on_int) + if (ret != 0) + { + return ret; + } + + switch (int_cfg0.sleep_status_on_int) { case ASM330LHHX_DRIVE_SLEEP_CHG_EVENT: *val = ASM330LHHX_DRIVE_SLEEP_CHG_EVENT; @@ -4127,6 +4368,10 @@ int32_t asm330lhhx_act_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG1, (uint8_t *)&int_cfg1, 1); + if (ret != 0) + { + return ret; + } switch (int_cfg1.inact_en) { @@ -4188,6 +4433,11 @@ int32_t asm330lhhx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.sleep_dur; return ret; @@ -4247,6 +4497,10 @@ int32_t asm330lhhx_6d_threshold_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_THS_6D, (uint8_t *)&ths_6d, 1); + if (ret != 0) + { + return ret; + } switch (ths_6d.sixd_ths) { @@ -4308,6 +4562,11 @@ int32_t asm330lhhx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhx_read_reg(ctx, ASM330LHHX_THS_6D, (uint8_t *)&ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = ths_6d.d4d_en; return ret; @@ -4365,6 +4624,10 @@ int32_t asm330lhhx_ff_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -4451,12 +4714,17 @@ int32_t asm330lhhx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - - if (ret == 0) + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FREE_FALL, - (uint8_t *)&free_fall, 1); + return ret; } + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FREE_FALL, + (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; return ret; @@ -4519,11 +4787,17 @@ int32_t asm330lhhx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - if (ret == 0) + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL1, - (uint8_t *)&fifo_ctrl1, 1); + return ret; } + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.wtm; *val = (*val * 256U) + fifo_ctrl1.wtm; return ret; @@ -4571,6 +4845,11 @@ int32_t asm330lhhx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odrchg_en; return ret; @@ -4617,6 +4896,11 @@ int32_t asm330lhhx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -4665,6 +4949,10 @@ int32_t asm330lhhx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_xl) { @@ -4754,6 +5042,10 @@ int32_t asm330lhhx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_gy) { @@ -4841,6 +5133,10 @@ int32_t asm330lhhx_fifo_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.fifo_mode) { @@ -4912,6 +5208,10 @@ int32_t asm330lhhx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.odr_t_batch) { @@ -4980,6 +5280,10 @@ int32_t asm330lhhx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.dec_ts_batch) { @@ -5047,6 +5351,10 @@ int32_t asm330lhhx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } switch (counter_bdr_reg1.trig_counter_bdr) { @@ -5104,6 +5412,11 @@ int32_t asm330lhhx_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + *val = counter_bdr_reg1.rst_counter_bdr; return ret; @@ -5159,10 +5472,15 @@ int32_t asm330lhhx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); - if (ret == 0) + if (ret != 0) + { + return ret; + } + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + if (ret != 0) { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); + return ret; } *val = counter_bdr_reg1.cnt_bdr_th; @@ -5310,6 +5628,10 @@ int32_t asm330lhhx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_data_out_tag, 1); + if (ret != 0) + { + return ret; + } switch (fifo_data_out_tag.tag_sensor) { @@ -5364,22 +5686,24 @@ int32_t asm330lhhx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK); - - if (ret == 0) - { - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV0_CONFIG, - (uint8_t *)&slv0_config, 1); - } - if (ret == 0) + if (ret != 0) { - slv0_config. batch_ext_sens_0_en = (uint8_t)val; - ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV0_CONFIG, - (uint8_t *)&slv0_config, 1); + goto exit; } - if (ret == 0) + + ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + goto exit; } + slv0_config.batch_ext_sens_0_en = (uint8_t)val; + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + +exit: + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -5406,9 +5730,10 @@ int32_t asm330lhhx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) } if (ret == 0) { - *val = slv0_config. batch_ext_sens_0_en; - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + *val = slv0_config.batch_ext_sens_0_en; } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -5438,10 +5763,9 @@ int32_t asm330lhhx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -5467,10 +5791,8 @@ int32_t asm330lhhx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)&slv1_config, 1); *val = slv1_config. batch_ext_sens_1_en; } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -5501,10 +5823,8 @@ int32_t asm330lhhx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV2_CONFIG, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -5531,8 +5851,8 @@ int32_t asm330lhhx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = slv2_config. batch_ext_sens_2_en; - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -5562,10 +5882,8 @@ int32_t asm330lhhx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -5589,12 +5907,12 @@ int32_t asm330lhhx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); - *val = slv3_config. batch_ext_sens_3_en; } if (ret == 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + *val = slv3_config. batch_ext_sens_3_en; } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -5648,6 +5966,10 @@ int32_t asm330lhhx_den_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.den_mode) { @@ -5712,6 +6034,10 @@ int32_t asm330lhhx_den_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_lh) { @@ -5767,6 +6093,10 @@ int32_t asm330lhhx_den_enable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_xl_g) { @@ -5823,6 +6153,11 @@ int32_t asm330lhhx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_z; return ret; @@ -5865,6 +6200,11 @@ int32_t asm330lhhx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_y; return ret; @@ -5906,6 +6246,11 @@ int32_t asm330lhhx_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_x; return ret; @@ -5961,12 +6306,15 @@ int32_t asm330lhhx_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SENSITIVITY_L, &buff[0]); - if (ret == 0) + ret += asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SENSITIVITY_H, &buff[1]); + if (ret != 0) { - ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SENSITIVITY_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + return ret; } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + return ret; } @@ -6063,12 +6411,15 @@ int32_t asm330lhhx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) i++; ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_OFFZ_H, &buff[i]); } - val[0] = (int16_t)buff[1]; - val[0] = (val[0] * 256) + (int16_t)buff[0]; - val[1] = (int16_t)buff[3]; - val[1] = (val[1] * 256) + (int16_t)buff[2]; - val[2] = (int16_t)buff[5]; - val[2] = (val[2] * 256) + (int16_t)buff[4]; + if (ret == 0) + { + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + } return ret; } @@ -6242,18 +6593,21 @@ int32_t asm330lhhx_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_ZZ_H, &buff[i]); } - val[0] = buff[1]; - val[0] = (val[0] * 256U) + buff[0]; - val[1] = buff[3]; - val[1] = (val[1] * 256U) + buff[2]; - val[2] = buff[5]; - val[2] = (val[2] * 256U) + buff[4]; - val[3] = buff[7]; - val[3] = (val[3] * 256U) + buff[6]; - val[4] = buff[9]; - val[4] = (val[4] * 256U) + buff[8]; - val[5] = buff[11]; - val[6] = (val[5] * 256U) + buff[10]; + if (ret == 0) + { + val[0] = buff[1]; + val[0] = (val[0] * 256U) + buff[0]; + val[1] = buff[3]; + val[1] = (val[1] * 256U) + buff[2]; + val[2] = buff[5]; + val[2] = (val[2] * 256U) + buff[4]; + val[3] = buff[7]; + val[3] = (val[3] * 256U) + buff[6]; + val[4] = buff[9]; + val[4] = (val[4] * 256U) + buff[8]; + val[5] = buff[11]; + val[6] = (val[5] * 256U) + buff[10]; + } return ret; } @@ -6301,6 +6655,10 @@ int32_t asm330lhhx_mag_z_orient_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_CFG_A, (uint8_t *)&mag_cfg_a); + if (ret != 0) + { + return ret; + } switch (mag_cfg_a.mag_z_axis) { @@ -6373,6 +6731,10 @@ int32_t asm330lhhx_mag_y_orient_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_CFG_A, (uint8_t *)&mag_cfg_a); + if (ret != 0) + { + return ret; + } switch (mag_cfg_a.mag_y_axis) { @@ -6444,6 +6806,10 @@ int32_t asm330lhhx_mag_x_orient_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_CFG_B, (uint8_t *)&mag_cfg_b); + if (ret != 0) + { + return ret; + } switch (mag_cfg_b.mag_x_axis) { @@ -6502,8 +6868,12 @@ int32_t asm330lhhx_fsm_status_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_A_MAINPAGE, (uint8_t *)&status_a, 1); - ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_B_MAINPAGE, - (uint8_t *)&status_b, 1); + ret += asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_B_MAINPAGE, + (uint8_t *)&status_b, 1); + if (ret != 0) + { + return ret; + } val->fsm1 = status_a.is_fsm1; val->fsm2 = status_a.is_fsm2; @@ -6539,10 +6909,8 @@ int32_t asm330lhhx_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_OUTS1, buff, 16); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -6570,8 +6938,8 @@ int32_t asm330lhhx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_fsm_lc; - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -6587,6 +6955,13 @@ int32_t asm330lhhx_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&page_sel, 1); page_sel.emb_func_clk_dis = val; + page_sel.not_used_01 = 1; + + if (ret == 0) + { + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } } ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); @@ -6605,7 +6980,10 @@ int32_t asm330lhhx_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL, (uint8_t *)&page_sel, 1); - *val = page_sel.emb_func_clk_dis; + if (ret == 0) + { + *val = page_sel.emb_func_clk_dis; + } } ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); @@ -6639,10 +7017,8 @@ int32_t asm330lhhx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -6671,10 +7047,9 @@ int32_t asm330lhhx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -6733,16 +7108,13 @@ int32_t asm330lhhx_fsm_enable_set(const stmdev_ctx_t *ctx, { emb_func_en_b.fsm_en = PROPERTY_DISABLE; } - } - if (ret == 0) - { + ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -6770,10 +7142,8 @@ int32_t asm330lhhx_fsm_enable_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_ENABLE_B, (uint8_t *)&val->fsm_enable_b, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -6799,10 +7169,7 @@ int32_t asm330lhhx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_LONG_COUNTER_L, buff, 2); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -6824,13 +7191,13 @@ int32_t asm330lhhx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_LONG_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; - } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -6861,10 +7228,8 @@ int32_t asm330lhhx_long_clr_set(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_LONG_COUNTER_CLEAR, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -6889,10 +7254,12 @@ int32_t asm330lhhx_long_clr_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_LONG_COUNTER_CLEAR, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } + switch (fsm_long_counter_clear.fsm_lc_clr) { case ASM330LHHX_LC_NORMAL: @@ -6940,10 +7307,8 @@ int32_t asm330lhhx_fsm_data_rate_set(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_ODR_CFG_B, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -6968,10 +7333,12 @@ int32_t asm330lhhx_fsm_data_rate_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_ODR_CFG_B, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } + switch (emb_func_odr_cfg_b.fsm_odr) { case ASM330LHHX_ODR_FSM_12Hz5: @@ -7019,10 +7386,8 @@ int32_t asm330lhhx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -7048,8 +7413,9 @@ int32_t asm330lhhx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_init_b.fsm_init; - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -7103,8 +7469,11 @@ int32_t asm330lhhx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val { ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_FSM_LC_TIMEOUT_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; } @@ -7191,8 +7560,11 @@ int32_t asm330lhhx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_FSM_START_ADD_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; } @@ -7245,10 +7617,7 @@ int32_t asm330lhhx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -7272,9 +7641,9 @@ int32_t asm330lhhx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) } if (ret == 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); *val = reg.mlc_en; } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -7318,10 +7687,7 @@ int32_t asm330lhhx_mlc_data_rate_set(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_ODR_CFG_C, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -7346,6 +7712,8 @@ int32_t asm330lhhx_mlc_data_rate_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_ODR_CFG_C, (uint8_t *)®, 1); } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret == 0) { switch (reg.mlc_odr) @@ -7366,8 +7734,8 @@ int32_t asm330lhhx_mlc_data_rate_get(const stmdev_ctx_t *ctx, *val = ASM330LHHX_ODR_PRGS_12Hz5; break; } - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); } + return ret; } @@ -7427,7 +7795,7 @@ int32_t asm330lhhx_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val) *val = emb_func_init_b.mlc_init; } - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -7447,10 +7815,8 @@ int32_t asm330lhhx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MLC0_SRC, buff, 8); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -7498,8 +7864,11 @@ int32_t asm330lhhx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *va { ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MLC_MAG_SENSITIVITY_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; } @@ -7536,10 +7905,9 @@ int32_t asm330lhhx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, { ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SENSOR_HUB_1, (uint8_t *)val, 18); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -7570,10 +7938,9 @@ int32_t asm330lhhx_sh_slave_connected_set(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -7598,27 +7965,29 @@ int32_t asm330lhhx_sh_slave_connected_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG, (uint8_t *)&master_config, 1); } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret == 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } - switch (master_config.aux_sens_on) - { - case ASM330LHHX_SLV_0: - *val = ASM330LHHX_SLV_0; - break; - case ASM330LHHX_SLV_0_1: - *val = ASM330LHHX_SLV_0_1; - break; - case ASM330LHHX_SLV_0_1_2: - *val = ASM330LHHX_SLV_0_1_2; - break; - case ASM330LHHX_SLV_0_1_2_3: - *val = ASM330LHHX_SLV_0_1_2_3; - break; - default: - *val = ASM330LHHX_SLV_0; - break; + switch (master_config.aux_sens_on) + { + case ASM330LHHX_SLV_0: + *val = ASM330LHHX_SLV_0; + break; + case ASM330LHHX_SLV_0_1: + *val = ASM330LHHX_SLV_0_1; + break; + case ASM330LHHX_SLV_0_1_2: + *val = ASM330LHHX_SLV_0_1_2; + break; + case ASM330LHHX_SLV_0_1_2_3: + *val = ASM330LHHX_SLV_0_1_2_3; + break; + default: + *val = ASM330LHHX_SLV_0; + break; + } } return ret; } @@ -7649,10 +8018,7 @@ int32_t asm330lhhx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); return ret; } @@ -7679,8 +8045,10 @@ int32_t asm330lhhx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = master_config.master_on; - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -7711,10 +8079,9 @@ int32_t asm330lhhx_sh_pin_mode_set(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -7738,10 +8105,13 @@ int32_t asm330lhhx_sh_pin_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } + switch (master_config.shub_pu_en) { case ASM330LHHX_EXT_PULL_UP: @@ -7783,10 +8153,9 @@ int32_t asm330lhhx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -7813,8 +8182,10 @@ int32_t asm330lhhx_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = master_config.pass_through_mode; - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -7845,10 +8216,9 @@ int32_t asm330lhhx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -7873,10 +8243,13 @@ int32_t asm330lhhx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } + switch (master_config.start_config) { case ASM330LHHX_EXT_ON_INT2_PIN: @@ -7920,10 +8293,9 @@ int32_t asm330lhhx_sh_write_mode_set(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -7949,10 +8321,13 @@ int32_t asm330lhhx_sh_write_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } + switch (master_config.write_once) { case ASM330LHHX_EACH_SH_CYCLE: @@ -7999,10 +8374,9 @@ int32_t asm330lhhx_sh_reset_set(const stmdev_ctx_t *ctx) ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -8025,12 +8399,14 @@ int32_t asm330lhhx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG, (uint8_t *)&master_config, 1); - *val = master_config.rst_master_regs; } if (ret == 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + *val = master_config.rst_master_regs; } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -8061,10 +8437,9 @@ int32_t asm330lhhx_sh_data_rate_set(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -8089,10 +8464,13 @@ int32_t asm330lhhx_sh_data_rate_get(const stmdev_ctx_t *ctx, ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); } - if (ret == 0) + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + if (ret != 0) { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } + switch (slv0_config.shub_odr) { case ASM330LHHX_SH_ODR_104Hz: @@ -8150,10 +8528,9 @@ int32_t asm330lhhx_sh_cfg_write(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_DATAWRITE_SLV0, (uint8_t *) & (val->slv0_data), 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -8200,10 +8577,9 @@ int32_t asm330lhhx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -8248,10 +8624,9 @@ int32_t asm330lhhx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -8298,10 +8673,9 @@ int32_t asm330lhhx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV2_CONFIG, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -8348,10 +8722,9 @@ int32_t asm330lhhx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -8374,10 +8747,9 @@ int32_t asm330lhhx_sh_status_get(const stmdev_ctx_t *ctx, { ret = asm330lhhx_read_reg(ctx, ASM330LHHX_STATUS_MASTER, (uint8_t *)val, 1); } - if (ret == 0) - { - ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); - } + + ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK); + return ret; } @@ -8391,4 +8763,3 @@ int32_t asm330lhhx_sh_status_get(const stmdev_ctx_t *ctx, * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.h b/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.h index 5dc295a..f023da7 100644 --- a/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.h +++ b/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2023 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -3557,4 +3559,3 @@ int32_t asm330lhhx_sh_status_get(const stmdev_ctx_t *ctx, #endif /* ASM330LHHX_REGS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.c b/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.c index c8ab86f..3096326 100644 --- a/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.c +++ b/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -204,6 +203,8 @@ int32_t asm330lhhxg1_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl1_xl.fs_xl) { case ASM330LHHXG1_2g: @@ -361,11 +362,11 @@ int32_t asm330lhhxg1_xl_data_rate_set(const stmdev_ctx_t *ctx, mlc_enable = PROPERTY_DISABLE; if (ret == 0) { - ret = asm330lhhxg1_mlc_get(ctx, &mlc_enable); + ret = asm330lhhxg1_mlc_get(ctx, &mlc_enable); if (mlc_enable == PROPERTY_ENABLE) { - ret = asm330lhhxg1_mlc_data_rate_get(ctx, &mlc_odr); + ret += asm330lhhxg1_mlc_data_rate_get(ctx, &mlc_odr); if (ret == 0) { switch (mlc_odr) @@ -482,6 +483,8 @@ int32_t asm330lhhxg1_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl1_xl.odr_xl) { case ASM330LHHXG1_XL_ODR_OFF: @@ -565,6 +568,8 @@ int32_t asm330lhhxg1_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) { return ret; } + switch (ctrl2_g.fs_g) { case ASM330LHHXG1_125dps: @@ -728,11 +733,11 @@ int32_t asm330lhhxg1_gy_data_rate_set(const stmdev_ctx_t *ctx, mlc_enable = PROPERTY_DISABLE; if (ret == 0) { - ret = asm330lhhxg1_mlc_get(ctx, &mlc_enable); + ret = asm330lhhxg1_mlc_get(ctx, &mlc_enable); if (mlc_enable == PROPERTY_ENABLE) { - ret = asm330lhhxg1_mlc_data_rate_get(ctx, &mlc_odr); + ret += asm330lhhxg1_mlc_data_rate_get(ctx, &mlc_odr); if (ret == 0) { switch (mlc_odr) @@ -850,6 +855,8 @@ int32_t asm330lhhxg1_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) { return ret; } + switch (ctrl2_g.odr_g) { case ASM330LHHXG1_GY_ODR_OFF: @@ -928,6 +935,8 @@ int32_t asm330lhhxg1_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + *val = ctrl3_c.bdu; return ret; @@ -973,6 +982,7 @@ int32_t asm330lhhxg1_xl_offset_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } switch (ctrl6_c.usr_off_w) { @@ -1027,6 +1037,8 @@ int32_t asm330lhhxg1_xl_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } + switch (ctrl6_c.xl_hm_mode) { case ASM330LHHXG1_HIGH_PERFORMANCE_MD: @@ -1080,6 +1092,8 @@ int32_t asm330lhhxg1_gy_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) { return ret; } + switch (ctrl7_g.g_hm_mode) { case ASM330LHHXG1_GY_HIGH_PERFORMANCE: @@ -1151,10 +1165,7 @@ int32_t asm330lhhxg1_all_sources_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MLC_STATUS, (uint8_t *)&val->mlc_status, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); return ret; } @@ -1190,6 +1201,8 @@ int32_t asm330lhhxg1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *va ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.xlda; return ret; @@ -1210,6 +1223,8 @@ int32_t asm330lhhxg1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *va ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.gda; return ret; @@ -1230,13 +1245,15 @@ int32_t asm330lhhxg1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t * ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.tda; return ret; } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1253,7 +1270,7 @@ int32_t asm330lhhxg1_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1270,7 +1287,7 @@ int32_t asm330lhhxg1_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1287,7 +1304,7 @@ int32_t asm330lhhxg1_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1304,7 +1321,7 @@ int32_t asm330lhhxg1_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1321,7 +1338,7 @@ int32_t asm330lhhxg1_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1373,6 +1390,8 @@ int32_t asm330lhhxg1_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) { return ret; } + *val = ctrl7_g.usr_off_on_out; return ret; @@ -1442,6 +1461,8 @@ int32_t asm330lhhxg1_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) { return ret; } + *val = ctrl10_c.timestamp_en; return ret; @@ -1463,6 +1484,8 @@ int32_t asm330lhhxg1_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_TIMESTAMP0, buff, 4); + if (ret != 0) { return ret; } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1521,6 +1544,8 @@ int32_t asm330lhhxg1_rounding_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.rounding) { case ASM330LHHXG1_NO_ROUND: @@ -1544,7 +1569,7 @@ int32_t asm330lhhxg1_rounding_mode_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). - * L and H registers together express a 16-bit word in two’s + * L and H registers together express a 16-bit word in two's * complement.[get] * * @param ctx Read / write interface definitions.(ptr) @@ -1558,6 +1583,8 @@ int32_t asm330lhhxg1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_OUT_TEMP_L, buff, 2); + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1566,7 +1593,7 @@ int32_t asm330lhhxg1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Angular rate sensor. The value is expressed as a 16-bit - * word in two’s complement.[get] + * word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1578,6 +1605,7 @@ int32_t asm330lhhxg1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[6]; int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_OUTX_L_G, buff, 6); + if (ret != 0) { return ret; } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1591,7 +1619,7 @@ int32_t asm330lhhxg1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed as a - * 16-bit word in two’s complement.[get] + * 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1603,6 +1631,7 @@ int32_t asm330lhhxg1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[6]; int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_OUTX_L_A, buff, 6); + if (ret != 0) { return ret; } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1684,6 +1713,8 @@ int32_t asm330lhhxg1_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); + if (ret != 0) { return ret; } + *val = internal_freq_fine.freq_fine; return ret; @@ -1732,6 +1763,8 @@ int32_t asm330lhhxg1_mem_bank_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) { return ret; } + switch (func_cfg_access.reg_access) { case ASM330LHHXG1_USER_BANK: @@ -1768,49 +1801,43 @@ int32_t asm330lhhxg1_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, int32_t ret; ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x02U; /* page_write enable */ - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_VALUE, val, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + if (ret != 0) { goto exit; } + + /* set page write */ + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x02U; /* page_write enable */ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + + /* select page */ + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + + /* set page addr */ + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { goto exit; } + + /* write */ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_VALUE, val, 1); + if (ret != 0) { goto exit; } + + /* unset page write */ + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x00; /* page_write disable */ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -1838,78 +1865,66 @@ int32_t asm330lhhxg1_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, lsb = (uint8_t)(add - (msb * 256U)); ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x02U; /* page_write enable*/ - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_address.page_addr = lsb; - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } + if (ret != 0) { goto exit; } + + /* set page write */ + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x02U; /* page_write enable*/ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + + /* select page */ + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; // Default value + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + + /* set page addr */ + page_address.page_addr = lsb; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { goto exit; } + for (i = 0; i < len; i++) { - if (ret == 0) + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { goto exit; } + + lsb++; + /* Check if page wrap */ + if (lsb == 0x00U) { - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_VALUE, &buf[i], 1); - if (ret == 0) - { - /* Check if page wrap */ - if (lsb == 0x00U) - { - msb++; - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - lsb++; - } - if (ret == 0) - { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } + msb++; + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } } } - if (ret == 0) - { - page_sel.page_sel = 0; - page_sel.not_used_01 = 1; - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x00U; /* page_write disable */ - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + + /* unset page write */ + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x00U; /* page_write disable */ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -1931,49 +1946,43 @@ int32_t asm330lhhxg1_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, int32_t ret; ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x01U; /* page_read enable*/ - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_VALUE, val, 2); - } - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x00U; /* page_read disable */ - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + if (ret != 0) { goto exit; } + + /* set page write */ + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x01U; /* page_read enable */ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + + /* select page */ + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + + /* set page addr */ + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { goto exit; } + + /* read page value */ + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_VALUE, val, 1); + if (ret != 0) { goto exit; } + + /* unset page write */ + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x00U; /* page_read disable */ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -2020,6 +2029,8 @@ int32_t asm330lhhxg1_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) { goto exit; } + switch (counter_bdr_reg1.dataready_pulsed) { case ASM330LHHXG1_DRDY_LATCHED: @@ -2032,6 +2043,8 @@ int32_t asm330lhhxg1_data_ready_mode_get(const stmdev_ctx_t *ctx, *val = ASM330LHHXG1_DRDY_LATCHED; break; } + +exit: return ret; } @@ -2086,8 +2099,11 @@ int32_t asm330lhhxg1_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { goto exit; } + *val = ctrl3_c.sw_reset; +exit: return ret; } @@ -2129,8 +2145,11 @@ int32_t asm330lhhxg1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { goto exit; } + *val = ctrl3_c.if_inc; +exit: return ret; } @@ -2170,8 +2189,11 @@ int32_t asm330lhhxg1_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { goto exit; } + *val = ctrl3_c.boot; +exit: return ret; } @@ -2215,6 +2237,7 @@ int32_t asm330lhhxg1_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { goto exit; } switch (ctrl5_c.st_xl) { @@ -2231,6 +2254,8 @@ int32_t asm330lhhxg1_xl_self_test_get(const stmdev_ctx_t *ctx, *val = ASM330LHHXG1_XL_ST_DISABLE; break; } + +exit: return ret; } @@ -2272,6 +2297,7 @@ int32_t asm330lhhxg1_gy_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { goto exit; } switch (ctrl5_c.st_g) { @@ -2288,6 +2314,8 @@ int32_t asm330lhhxg1_gy_self_test_get(const stmdev_ctx_t *ctx, *val = ASM330LHHXG1_GY_ST_DISABLE; break; } + +exit: return ret; } @@ -2341,8 +2369,11 @@ int32_t asm330lhhxg1_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { goto exit; } + *val = ctrl1_xl.lpf2_xl_en; +exit: return ret; } @@ -2384,8 +2415,11 @@ int32_t asm330lhhxg1_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { goto exit; } + *val = ctrl4_c.lpf1_sel_g; +exit: return ret; } @@ -2428,8 +2462,11 @@ int32_t asm330lhhxg1_filter_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { goto exit; } + *val = ctrl4_c.drdy_mask; +exit: return ret; } @@ -2471,6 +2508,7 @@ int32_t asm330lhhxg1_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { goto exit; } switch (ctrl6_c.ftype) { @@ -2502,6 +2540,8 @@ int32_t asm330lhhxg1_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, *val = ASM330LHHXG1_ULTRA_LIGHT; break; } + +exit: return ret; } @@ -2542,8 +2582,11 @@ int32_t asm330lhhxg1_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { goto exit; } + *val = ctrl8_xl.low_pass_on_6d; +exit: return ret; } @@ -2590,6 +2633,8 @@ int32_t asm330lhhxg1_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { goto exit; } + switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) + ctrl8_xl.hpcf_xl)) { @@ -2666,6 +2711,8 @@ int32_t asm330lhhxg1_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, *val = ASM330LHHXG1_HP_PATH_DISABLE_ON_OUT; break; } + +exit: return ret; } @@ -2710,8 +2757,11 @@ int32_t asm330lhhxg1_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { goto exit; } + *val = ctrl8_xl.fastsettl_mode_xl; +exit: return ret; } @@ -2756,6 +2806,8 @@ int32_t asm330lhhxg1_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret != 0) { goto exit; } + switch (int_cfg0.slope_fds) { case ASM330LHHXG1_USE_SLOPE: @@ -2768,6 +2820,8 @@ int32_t asm330lhhxg1_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, *val = ASM330LHHXG1_USE_SLOPE; break; } + +exit: return ret; } @@ -2812,6 +2866,7 @@ int32_t asm330lhhxg1_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) { goto exit; } switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g) { @@ -2834,6 +2889,8 @@ int32_t asm330lhhxg1_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, *val = ASM330LHHXG1_HP_FILTER_NONE; break; } + +exit: return ret; } @@ -2888,6 +2945,7 @@ int32_t asm330lhhxg1_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) { goto exit; } switch (pin_ctrl.sdo_pu_en) { @@ -2901,6 +2959,8 @@ int32_t asm330lhhxg1_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, *val = ASM330LHHXG1_PULL_UP_DISC; break; } + +exit: return ret; } @@ -2943,6 +3003,7 @@ int32_t asm330lhhxg1_int1_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); + if (ret != 0) { goto exit; } switch (i3c_bus_avb.pd_dis_int1) { @@ -2956,6 +3017,8 @@ int32_t asm330lhhxg1_int1_mode_get(const stmdev_ctx_t *ctx, *val = ASM330LHHXG1_PULL_DOWN_CONNECT; break; } + +exit: return ret; } @@ -2995,6 +3058,7 @@ int32_t asm330lhhxg1_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhhxg1_sim_t *v int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { goto exit; } switch (ctrl3_c.sim) { @@ -3008,6 +3072,8 @@ int32_t asm330lhhxg1_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhhxg1_sim_t *v *val = ASM330LHHXG1_SPI_4_WIRE; break; } + +exit: return ret; } @@ -3049,6 +3115,7 @@ int32_t asm330lhhxg1_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { goto exit; } switch (ctrl4_c.i2c_disable) { @@ -3062,6 +3129,8 @@ int32_t asm330lhhxg1_i2c_interface_get(const stmdev_ctx_t *ctx, *val = ASM330LHHXG1_I2C_ENABLE; break; } + +exit: return ret; } @@ -3117,11 +3186,10 @@ int32_t asm330lhhxg1_i3c_disable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); - } + ret += asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + if (ret != 0) { goto exit; } + switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel) { case ASM330LHHXG1_I3C_DISABLE: @@ -3143,6 +3211,8 @@ int32_t asm330lhhxg1_i3c_disable_get(const stmdev_ctx_t *ctx, *val = ASM330LHHXG1_I3C_DISABLE; break; } + +exit: return ret; } @@ -3196,10 +3266,7 @@ int32_t asm330lhhxg1_pin_int1_route_set(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_INT1_B, (uint8_t *)&val->fsm_int1_b, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); if (ret == 0) { @@ -3323,10 +3390,9 @@ int32_t asm330lhhxg1_pin_int1_route_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_INT1_B, (uint8_t *)&val->fsm_int1_b, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + if (ret == 0) { @@ -3377,10 +3443,7 @@ int32_t asm330lhhxg1_pin_int2_route_set(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_INT2_B, (uint8_t *)&val->fsm_int2_b, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); if (ret == 0) { @@ -3504,10 +3567,9 @@ int32_t asm330lhhxg1_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_INT2_B, (uint8_t *)&val->fsm_int2_b, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + if (ret == 0) { @@ -3557,6 +3619,7 @@ int32_t asm330lhhxg1_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhhxg1_pp_od_t int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } switch (ctrl3_c.pp_od) { @@ -3611,6 +3674,7 @@ int32_t asm330lhhxg1_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } switch (ctrl3_c.h_lactive) { @@ -3663,6 +3727,8 @@ int32_t asm330lhhxg1_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { return ret; } + *val = ctrl4_c.int2_on_int1; return ret; @@ -3694,20 +3760,20 @@ int32_t asm330lhhxg1_int_notification_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); } - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + return ret; } @@ -3732,15 +3798,17 @@ int32_t asm330lhhxg1_int_notification_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); } - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + if (ret != 0) { return ret; } + switch ((page_rw.emb_func_lir << 1) + int_cfg0.lir) { case ASM330LHHXG1_ALL_INT_PULSED: @@ -3820,6 +3888,7 @@ int32_t asm330lhhxg1_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) { return ret; } switch (wake_up_dur.wake_ths_w) { @@ -3877,6 +3946,8 @@ int32_t asm330lhhxg1_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) { return ret; } + *val = wake_up_ths.wk_ths; return ret; @@ -3922,6 +3993,8 @@ int32_t asm330lhhxg1_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) { return ret; } + *val = wake_up_ths.usr_off_on_wu; return ret; @@ -3966,6 +4039,8 @@ int32_t asm330lhhxg1_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) { return ret; } + *val = wake_up_dur.wake_dur; return ret; @@ -4020,6 +4095,8 @@ int32_t asm330lhhxg1_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { return ret; } + *val = ctrl4_c.sleep_g; return ret; @@ -4068,6 +4145,8 @@ int32_t asm330lhhxg1_act_pin_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret != 0) { return ret; } + switch (int_cfg0. sleep_status_on_int) { case ASM330LHHXG1_DRIVE_SLEEP_CHG_EVENT: @@ -4120,6 +4199,7 @@ int32_t asm330lhhxg1_act_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *)&int_cfg1, 1); + if (ret != 0) { return ret; } switch (int_cfg1.inact_en) { @@ -4181,6 +4261,8 @@ int32_t asm330lhhxg1_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) { return ret; } + *val = wake_up_dur.sleep_dur; return ret; @@ -4240,6 +4322,7 @@ int32_t asm330lhhxg1_6d_threshold_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_THS_6D, (uint8_t *)&ths_6d, 1); + if (ret != 0) { return ret; } switch (ths_6d.sixd_ths) { @@ -4301,6 +4384,8 @@ int32_t asm330lhhxg1_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_THS_6D, (uint8_t *)&ths_6d, 1); + if (ret != 0) { return ret; } + *val = ths_6d.d4d_en; return ret; @@ -4358,6 +4443,7 @@ int32_t asm330lhhxg1_ff_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) { return ret; } switch (free_fall.ff_ths) { @@ -4445,11 +4531,10 @@ int32_t asm330lhhxg1_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FREE_FALL, - (uint8_t *)&free_fall, 1); - } + ret += asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FREE_FALL, + (uint8_t *)&free_fall, 1); + + if (ret != 0) { return ret; } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; return ret; @@ -4516,11 +4601,11 @@ int32_t asm330lhhxg1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL1, - (uint8_t *)&fifo_ctrl1, 1); - } + ret += asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl2.wtm; *val = (*val * 256U) + fifo_ctrl1.wtm; return ret; @@ -4568,6 +4653,8 @@ int32_t asm330lhhxg1_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) { return ret; } + *val = fifo_ctrl2.odrchg_en; return ret; @@ -4614,6 +4701,8 @@ int32_t asm330lhhxg1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) { return ret; } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -4662,6 +4751,7 @@ int32_t asm330lhhxg1_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl3.bdr_xl) { @@ -4751,6 +4841,7 @@ int32_t asm330lhhxg1_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl3.bdr_gy) { @@ -4838,6 +4929,7 @@ int32_t asm330lhhxg1_fifo_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl4.fifo_mode) { @@ -4909,6 +5001,7 @@ int32_t asm330lhhxg1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl4.odr_t_batch) { @@ -4977,6 +5070,7 @@ int32_t asm330lhhxg1_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl4.dec_ts_batch) { @@ -5044,6 +5138,7 @@ int32_t asm330lhhxg1_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) { return ret; } switch (counter_bdr_reg1.trig_counter_bdr) { @@ -5101,6 +5196,8 @@ int32_t asm330lhhxg1_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) { return ret; } + *val = counter_bdr_reg1.rst_counter_bdr; return ret; @@ -5156,11 +5253,9 @@ int32_t asm330lhhxg1_batch_counter_threshold_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); - } + ret += asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + if (ret != 0) { return ret; } *val = counter_bdr_reg1.cnt_bdr_th; *val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th; @@ -5183,14 +5278,12 @@ int32_t asm330lhhxg1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); - if (ret == 0) - { - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); + ret += asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + if (ret != 0) { return ret; } - *val = fifo_status2.diff_fifo; - *val = (*val * 256U) + fifo_status1.diff_fifo; - } + *val = fifo_status2.diff_fifo; + *val = (*val * 256U) + fifo_status1.diff_fifo; return ret; } @@ -5225,6 +5318,8 @@ int32_t asm330lhhxg1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); + if (ret != 0) { return ret; } + *val = fifo_status2.fifo_full_ia; return ret; @@ -5246,6 +5341,8 @@ int32_t asm330lhhxg1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); + if (ret != 0) { return ret; } + *val = fifo_status2. fifo_ovr_ia; return ret; @@ -5266,6 +5363,8 @@ int32_t asm330lhhxg1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); + if (ret != 0) { return ret; } + *val = fifo_status2.fifo_wtm_ia; return ret; @@ -5287,6 +5386,7 @@ int32_t asm330lhhxg1_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_data_out_tag, 1); + if (ret != 0) { return ret; } switch (fifo_data_out_tag.tag_sensor) { @@ -5353,10 +5453,9 @@ int32_t asm330lhhxg1_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -5384,8 +5483,10 @@ int32_t asm330lhhxg1_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = slv0_config. batch_ext_sens_0_en; - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -5415,10 +5516,9 @@ int32_t asm330lhhxg1_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -5442,14 +5542,16 @@ int32_t asm330lhhxg1_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); - *val = slv1_config. batch_ext_sens_1_en; - } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + if (ret == 0) + { + *val = slv1_config. batch_ext_sens_1_en; + } } - return ret; -} + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + return ret; +} /** * @brief Enable FIFO batching data of third slave.[set] @@ -5478,10 +5580,9 @@ int32_t asm330lhhxg1_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV2_CONFIG, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -5508,8 +5609,10 @@ int32_t asm330lhhxg1_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = slv2_config. batch_ext_sens_2_en; - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -5539,10 +5642,9 @@ int32_t asm330lhhxg1_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -5566,12 +5668,15 @@ int32_t asm330lhhxg1_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); - *val = slv3_config. batch_ext_sens_3_en; - } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + if (ret == 0) + { + *val = slv3_config. batch_ext_sens_3_en; + } } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -5625,6 +5730,7 @@ int32_t asm330lhhxg1_den_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } switch (ctrl6_c.den_mode) { @@ -5689,6 +5795,7 @@ int32_t asm330lhhxg1_den_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) { return ret; } switch (ctrl9_xl.den_lh) { @@ -5744,6 +5851,7 @@ int32_t asm330lhhxg1_den_enable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) { return ret; } switch (ctrl9_xl.den_xl_g) { @@ -5800,6 +5908,8 @@ int32_t asm330lhhxg1_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_z; return ret; @@ -5842,6 +5952,8 @@ int32_t asm330lhhxg1_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_y; return ret; @@ -5883,6 +5995,8 @@ int32_t asm330lhhxg1_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_x; return ret; @@ -5941,8 +6055,12 @@ int32_t asm330lhhxg1_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SENSITIVITY_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; } @@ -6219,6 +6337,8 @@ int32_t asm330lhhxg1_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_ZZ_H, &buff[i]); } + if (ret != 0) { return ret; } + val[0] = buff[1]; val[0] = (val[0] * 256U) + buff[0]; val[1] = buff[3]; @@ -6278,6 +6398,7 @@ int32_t asm330lhhxg1_mag_z_orient_get(const stmdev_ctx_t *ctx, int32_t ret; ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_A, (uint8_t *)&mag_cfg_a); + if (ret != 0) { return ret; } switch (mag_cfg_a.mag_z_axis) { @@ -6350,6 +6471,7 @@ int32_t asm330lhhxg1_mag_y_orient_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_A, (uint8_t *)&mag_cfg_a); + if (ret != 0) { return ret; } switch (mag_cfg_a.mag_y_axis) { @@ -6421,6 +6543,7 @@ int32_t asm330lhhxg1_mag_x_orient_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_B, (uint8_t *)&mag_cfg_b); + if (ret != 0) { return ret; } switch (mag_cfg_b.mag_x_axis) { @@ -6479,8 +6602,9 @@ int32_t asm330lhhxg1_fsm_status_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_STATUS_A_MAINPAGE, (uint8_t *)&status_a, 1); - ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_STATUS_B_MAINPAGE, + ret += asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_STATUS_B_MAINPAGE, (uint8_t *)&status_b, 1); + if (ret != 0) { return ret; } val->fsm1 = status_a.is_fsm1; val->fsm2 = status_a.is_fsm2; @@ -6516,10 +6640,9 @@ int32_t asm330lhhxg1_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_OUTS1, buff, 16); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -6547,8 +6670,10 @@ int32_t asm330lhhxg1_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_fsm_lc; - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -6563,7 +6688,14 @@ int32_t asm330lhhxg1_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1); - page_sel.emb_func_clk_dis = val; + if (ret == 0) + { + page_sel.emb_func_clk_dis = val; + page_sel.not_used_01 = 1; // Default value + + ret += asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } } ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); @@ -6582,7 +6714,10 @@ int32_t asm330lhhxg1_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1); - *val = page_sel.emb_func_clk_dis; + if (ret == 0) + { + *val = page_sel.emb_func_clk_dis; + } } ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); @@ -6616,10 +6751,9 @@ int32_t asm330lhhxg1_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -6645,13 +6779,10 @@ int32_t asm330lhhxg1_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_en_b.fsm_en; - ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -6716,10 +6847,9 @@ int32_t asm330lhhxg1_fsm_enable_set(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -6747,10 +6877,9 @@ int32_t asm330lhhxg1_fsm_enable_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_ENABLE_B, (uint8_t *)&val->fsm_enable_b, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -6776,10 +6905,9 @@ int32_t asm330lhhxg1_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_L, buff, 2); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -6801,13 +6929,16 @@ int32_t asm330lhhxg1_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; - } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -6838,10 +6969,9 @@ int32_t asm330lhhxg1_long_clr_set(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_CLEAR, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -6866,10 +6996,10 @@ int32_t asm330lhhxg1_long_clr_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_CLEAR, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + if (ret != 0) { return ret; } + switch (fsm_long_counter_clear.fsm_lc_clr) { case ASM330LHHXG1_LC_NORMAL: @@ -6917,10 +7047,9 @@ int32_t asm330lhhxg1_fsm_data_rate_set(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_B, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -6945,10 +7074,10 @@ int32_t asm330lhhxg1_fsm_data_rate_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_B, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + if (ret != 0) { return ret; } + switch (emb_func_odr_cfg_b.fsm_odr) { case ASM330LHHXG1_ODR_FSM_12Hz5: @@ -6996,10 +7125,9 @@ int32_t asm330lhhxg1_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7025,8 +7153,10 @@ int32_t asm330lhhxg1_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_init_b.fsm_init; - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7080,8 +7210,12 @@ int32_t asm330lhhxg1_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *v { ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_FSM_LC_TIMEOUT_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; } @@ -7168,8 +7302,11 @@ int32_t asm330lhhxg1_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *va if (ret == 0) { ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_FSM_START_ADD_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; } @@ -7222,10 +7359,9 @@ int32_t asm330lhhxg1_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7249,9 +7385,11 @@ int32_t asm330lhhxg1_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) } if (ret == 0) { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); *val = reg.mlc_en; } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7295,10 +7433,8 @@ int32_t asm330lhhxg1_mlc_data_rate_set(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_C, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); return ret; } @@ -7343,8 +7479,10 @@ int32_t asm330lhhxg1_mlc_data_rate_get(const stmdev_ctx_t *ctx, *val = ASM330LHHXG1_ODR_PRGS_12Hz5; break; } - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7404,7 +7542,7 @@ int32_t asm330lhhxg1_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val) *val = emb_func_init_b.mlc_init; } - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); return ret; } @@ -7424,10 +7562,9 @@ int32_t asm330lhhxg1_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MLC0_SRC, buff, 8); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7475,8 +7612,11 @@ int32_t asm330lhhxg1_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t * { ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MLC_MAG_SENSITIVITY_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; } @@ -7513,10 +7653,9 @@ int32_t asm330lhhxg1_sh_read_data_raw_get(const stmdev_ctx_t *ctx, { ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SENSOR_HUB_1, (uint8_t *)val, 18); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7547,10 +7686,9 @@ int32_t asm330lhhxg1_sh_slave_connected_set(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7575,10 +7713,11 @@ int32_t asm330lhhxg1_sh_slave_connected_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + if (ret != 0) { return ret; } + switch (master_config.aux_sens_on) { case ASM330LHHXG1_SLV_0: @@ -7626,10 +7765,9 @@ int32_t asm330lhhxg1_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7656,8 +7794,10 @@ int32_t asm330lhhxg1_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = master_config.master_on; - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7688,10 +7828,9 @@ int32_t asm330lhhxg1_sh_pin_mode_set(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7715,10 +7854,10 @@ int32_t asm330lhhxg1_sh_pin_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + if (ret != 0) { return ret; } + switch (master_config.shub_pu_en) { case ASM330LHHXG1_EXT_PULL_UP: @@ -7760,10 +7899,9 @@ int32_t asm330lhhxg1_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7790,8 +7928,10 @@ int32_t asm330lhhxg1_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = master_config.pass_through_mode; - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7822,10 +7962,9 @@ int32_t asm330lhhxg1_sh_syncro_mode_set(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7850,10 +7989,10 @@ int32_t asm330lhhxg1_sh_syncro_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + if (ret != 0) { return ret; } + switch (master_config.start_config) { case ASM330LHHXG1_EXT_ON_INT2_PIN: @@ -7897,10 +8036,8 @@ int32_t asm330lhhxg1_sh_write_mode_set(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -7926,10 +8063,10 @@ int32_t asm330lhhxg1_sh_write_mode_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + if (ret != 0) { return ret; } + switch (master_config.write_once) { case ASM330LHHXG1_EACH_SH_CYCLE: @@ -7976,10 +8113,9 @@ int32_t asm330lhhxg1_sh_reset_set(const stmdev_ctx_t *ctx) ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -8002,12 +8138,14 @@ int32_t asm330lhhxg1_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, (uint8_t *)&master_config, 1); - *val = master_config.rst_master_regs; } if (ret == 0) { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + *val = master_config.rst_master_regs; } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -8038,10 +8176,9 @@ int32_t asm330lhhxg1_sh_data_rate_set(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -8066,10 +8203,11 @@ int32_t asm330lhhxg1_sh_data_rate_get(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + if (ret != 0) { return ret; } + switch (slv0_config.shub_odr) { case ASM330LHHXG1_SH_ODR_104Hz: @@ -8127,10 +8265,9 @@ int32_t asm330lhhxg1_sh_cfg_write(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_DATAWRITE_SLV0, (uint8_t *) & (val->slv0_data), 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -8177,10 +8314,9 @@ int32_t asm330lhhxg1_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -8225,10 +8361,9 @@ int32_t asm330lhhxg1_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -8275,10 +8410,9 @@ int32_t asm330lhhxg1_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV2_CONFIG, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -8325,10 +8459,9 @@ int32_t asm330lhhxg1_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -8351,10 +8484,9 @@ int32_t asm330lhhxg1_sh_status_get(const stmdev_ctx_t *ctx, { ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_MASTER, (uint8_t *)val, 1); } - if (ret == 0) - { - ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); - } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + return ret; } @@ -8367,5 +8499,3 @@ int32_t asm330lhhxg1_sh_status_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.h b/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.h index e2c1bb1..c959028 100644 --- a/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.h +++ b/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -3551,5 +3553,3 @@ int32_t asm330lhhxg1_sh_status_get(const stmdev_ctx_t *ctx, #endif #endif /* ASM330LHHXG1_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c index 12080cd..42e3ce8 100644 --- a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c +++ b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -153,7 +152,10 @@ int32_t h3lis100dl_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - *val = ctrl_reg1.xen; + if (ret == 0) + { + *val = ctrl_reg1.xen; + } return ret; } @@ -199,7 +201,10 @@ int32_t h3lis100dl_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - *val = ctrl_reg1.yen; + if (ret == 0) + { + *val = ctrl_reg1.yen; + } return ret; } @@ -245,7 +250,10 @@ int32_t h3lis100dl_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - *val = ctrl_reg1.zen; + if (ret == 0) + { + *val = ctrl_reg1.zen; + } return ret; } @@ -294,6 +302,7 @@ int32_t h3lis100dl_data_rate_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm) { @@ -384,6 +393,7 @@ int32_t h3lis100dl_reference_mode_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpm) { @@ -437,6 +447,8 @@ int32_t h3lis100dl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -469,8 +481,14 @@ int32_t h3lis100dl_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = h3lis100dl_read_reg(ctx, H3LIS100DL_OUT_X, (uint8_t *)&val[0], 1); - ret = h3lis100dl_read_reg(ctx, H3LIS100DL_OUT_Y, (uint8_t *)&val[1], 1); - ret = h3lis100dl_read_reg(ctx, H3LIS100DL_OUT_Z, (uint8_t *)&val[2], 1); + if (ret == 0) + { + ret = h3lis100dl_read_reg(ctx, H3LIS100DL_OUT_Y, (uint8_t *)&val[1], 1); + } + if (ret == 0) + { + ret = h3lis100dl_read_reg(ctx, H3LIS100DL_OUT_Z, (uint8_t *)&val[2], 1); + } return ret; } @@ -545,7 +563,10 @@ int32_t h3lis100dl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.boot; + if (ret == 0) + { + *val = ctrl_reg2.boot; + } return ret; } @@ -606,6 +627,7 @@ int32_t h3lis100dl_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpcf) { @@ -677,6 +699,7 @@ int32_t h3lis100dl_hp_path_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen) { @@ -835,6 +858,7 @@ int32_t h3lis100dl_spi_mode_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.sim) { @@ -910,6 +934,7 @@ int32_t h3lis100dl_pin_int1_route_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.i1_cfg) { @@ -982,6 +1007,7 @@ int32_t h3lis100dl_int1_notification_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.lir1) { @@ -1044,6 +1070,7 @@ int32_t h3lis100dl_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.i2_cfg) { @@ -1116,6 +1143,7 @@ int32_t h3lis100dl_int2_notification_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.lir2) { @@ -1178,6 +1206,7 @@ int32_t h3lis100dl_pin_mode_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.pp_od) { @@ -1240,6 +1269,7 @@ int32_t h3lis100dl_pin_polarity_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.ihl) { @@ -1320,6 +1350,8 @@ int32_t h3lis100dl_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } + val->int1_xlie = int1_cfg.xlie; val->int1_xhie = int1_cfg.xhie; val->int1_ylie = int1_cfg.ylie; @@ -1373,6 +1405,7 @@ int32_t h3lis100dl_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } switch (int1_cfg.aoi) { @@ -1451,6 +1484,8 @@ int32_t h3lis100dl_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_THS, (uint8_t *)&int1_ths, 1); + if (ret != 0) { return ret; } + *val = int1_ths.ths; return ret; @@ -1497,6 +1532,8 @@ int32_t h3lis100dl_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_DURATION, (uint8_t *)&int1_duration, 1); + if (ret != 0) { return ret; } + *val = int1_duration.d; return ret; @@ -1550,6 +1587,8 @@ int32_t h3lis100dl_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } + val->int2_xlie = int2_cfg.xlie; val->int2_xhie = int2_cfg.xhie; val->int2_ylie = int2_cfg.ylie; @@ -1603,6 +1642,7 @@ int32_t h3lis100dl_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } switch (int2_cfg.aoi) { @@ -1681,6 +1721,8 @@ int32_t h3lis100dl_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_THS, (uint8_t *)&int2_ths, 1); + if (ret != 0) { return ret; } + *val = int2_ths.ths; return ret; @@ -1727,6 +1769,8 @@ int32_t h3lis100dl_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_DURATION, (uint8_t *)&int2_duration, 1); + if (ret != 0) { return ret; } + *val = int2_duration.d; return ret; @@ -1786,6 +1830,8 @@ int32_t h3lis100dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg5.turnon; return ret; @@ -1800,5 +1846,3 @@ int32_t h3lis100dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h index 1ea5e20..aa837a9 100644 --- a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h +++ b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -732,5 +734,3 @@ int32_t h3lis100dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* H3LIS100DL_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c index 4217c96..dfea5b2 100644 --- a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c +++ b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -163,7 +162,10 @@ int32_t h3lis331dl_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - *val = ctrl_reg1.xen; + if (ret == 0) + { + *val = ctrl_reg1.xen; + } return ret; } @@ -209,7 +211,10 @@ int32_t h3lis331dl_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - *val = ctrl_reg1.yen; + if (ret == 0) + { + *val = ctrl_reg1.yen; + } return ret; } @@ -255,7 +260,10 @@ int32_t h3lis331dl_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - *val = ctrl_reg1.zen; + if (ret == 0) + { + *val = ctrl_reg1.zen; + } return ret; } @@ -304,6 +312,7 @@ int32_t h3lis331dl_data_rate_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm) { @@ -398,6 +407,7 @@ int32_t h3lis331dl_reference_mode_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpm) { @@ -460,6 +470,7 @@ int32_t h3lis331dl_full_scale_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.fs) { @@ -526,6 +537,8 @@ int32_t h3lis331dl_block_data_update_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg4.bdu; return ret; @@ -566,6 +579,8 @@ int32_t h3lis331dl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -585,7 +600,7 @@ int32_t h3lis331dl_flag_data_ready_get(const stmdev_ctx_t *ctx, /** * @brief Linear acceleration output register. The value is expressed - * as a 16-bit word in two’s complement.[get] + * as a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions(ptr) * @param buff buffer that stores data read @@ -599,6 +614,8 @@ int32_t h3lis331dl_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = h3lis331dl_read_reg(ctx, H3LIS331DL_OUT_X_L, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -679,6 +696,8 @@ int32_t h3lis331dl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg2.boot; return ret; @@ -727,6 +746,7 @@ int32_t h3lis331dl_data_format_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.ble) { @@ -802,6 +822,7 @@ int32_t h3lis331dl_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpcf) { @@ -873,6 +894,7 @@ int32_t h3lis331dl_hp_path_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen) { @@ -1031,6 +1053,7 @@ int32_t h3lis331dl_spi_mode_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.sim) { @@ -1106,6 +1129,7 @@ int32_t h3lis331dl_pin_int1_route_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.i1_cfg) { @@ -1178,6 +1202,7 @@ int32_t h3lis331dl_int1_notification_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.lir1) { @@ -1240,6 +1265,7 @@ int32_t h3lis331dl_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.i2_cfg) { @@ -1312,6 +1338,7 @@ int32_t h3lis331dl_int2_notification_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.lir2) { @@ -1374,6 +1401,7 @@ int32_t h3lis331dl_pin_mode_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.pp_od) { @@ -1436,6 +1464,7 @@ int32_t h3lis331dl_pin_polarity_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.ihl) { @@ -1516,6 +1545,8 @@ int32_t h3lis331dl_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } + val->int1_xlie = int1_cfg.xlie; val->int1_xhie = int1_cfg.xhie; val->int1_ylie = int1_cfg.ylie; @@ -1569,6 +1600,7 @@ int32_t h3lis331dl_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } switch (int1_cfg.aoi) { @@ -1647,6 +1679,8 @@ int32_t h3lis331dl_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_THS, (uint8_t *)&int1_ths, 1); + if (ret != 0) { return ret; } + *val = int1_ths.ths; return ret; @@ -1693,6 +1727,8 @@ int32_t h3lis331dl_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_DURATION, (uint8_t *)&int1_duration, 1); + if (ret != 0) { return ret; } + *val = int1_duration.d; return ret; @@ -1746,6 +1782,8 @@ int32_t h3lis331dl_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } + val->int2_xlie = int2_cfg.xlie; val->int2_xhie = int2_cfg.xhie; val->int2_ylie = int2_cfg.ylie; @@ -1799,6 +1837,7 @@ int32_t h3lis331dl_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } switch (int2_cfg.aoi) { @@ -1877,6 +1916,8 @@ int32_t h3lis331dl_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_THS, (uint8_t *)&int2_ths, 1); + if (ret != 0) { return ret; } + *val = int2_ths.ths; return ret; @@ -1923,6 +1964,8 @@ int32_t h3lis331dl_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_DURATION, (uint8_t *)&int2_duration, 1); + if (ret != 0) { return ret; } + *val = int2_duration.d; return ret; @@ -1982,6 +2025,8 @@ int32_t h3lis331dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg5.turnon; return ret; @@ -1991,5 +2036,3 @@ int32_t h3lis331dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h index 5b73ee6..4ea44e7 100644 --- a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h +++ b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -769,5 +771,3 @@ int32_t h3lis331dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* H3LIS331DL_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c index 579a868..e942b20 100644 --- a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c +++ b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -136,6 +135,7 @@ int32_t hts221_humidity_avg_get(const stmdev_ctx_t *ctx, hts221_avgh_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_AV_CONF, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.avgh) { @@ -219,6 +219,7 @@ int32_t hts221_temperature_avg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = hts221_read_reg(ctx, HTS221_AV_CONF, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.avgh) { @@ -300,6 +301,7 @@ int32_t hts221_data_rate_get(const stmdev_ctx_t *ctx, hts221_odr_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.odr) { @@ -365,7 +367,10 @@ int32_t hts221_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t *) ®, 1); - *val = reg.bdu; + if (ret == 0) + { + *val = reg.bdu; + } return ret; } @@ -408,7 +413,10 @@ int32_t hts221_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t *) ®, 1); - *val = reg.one_shot; + if (ret == 0) + { + *val = reg.one_shot; + } return ret; } @@ -427,7 +435,10 @@ int32_t hts221_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_STATUS_REG, (uint8_t *) ®, 1); - *val = reg.t_da; + if (ret == 0) + { + *val = reg.t_da; + } return ret; } @@ -446,7 +457,10 @@ int32_t hts221_hum_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_STATUS_REG, (uint8_t *) ®, 1); - *val = reg.h_da; + if (ret == 0) + { + *val = reg.h_da; + } return ret; } @@ -465,8 +479,11 @@ int32_t hts221_humidity_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_HUMIDITY_OUT_L, buff, 2); - *val = (int16_t)buff[1]; - *val = (*val * 256) + (int16_t)buff[0]; + if (ret == 0) + { + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + } return ret; } @@ -485,8 +502,11 @@ int32_t hts221_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_TEMP_OUT_L, buff, 2); - *val = (int16_t)buff[1]; - *val = (*val * 256) + (int16_t)buff[0]; + if (ret == 0) + { + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + } return ret; } @@ -558,7 +578,10 @@ int32_t hts221_power_on_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_CTRL_REG1, (uint8_t *) ®, 1); - *val = reg.pd; + if (ret == 0) + { + *val = reg.pd; + } return ret; } @@ -601,7 +624,10 @@ int32_t hts221_heater_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t *) ®, 1); - *val = reg.heater; + if (ret == 0) + { + *val = reg.heater; + } return ret; } @@ -644,7 +670,10 @@ int32_t hts221_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_CTRL_REG2, (uint8_t *) ®, 1); - *val = reg.boot; + if (ret == 0) + { + *val = reg.boot; + } return ret; } @@ -716,7 +745,10 @@ int32_t hts221_drdy_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t *) ®, 1); - *val = reg.drdy; + if (ret == 0) + { + *val = reg.drdy; + } return ret; } @@ -758,6 +790,7 @@ int32_t hts221_pin_mode_get(const stmdev_ctx_t *ctx, hts221_pp_od_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.pp_od) { @@ -817,6 +850,7 @@ int32_t hts221_int_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = hts221_read_reg(ctx, HTS221_CTRL_REG3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.drdy_h_l) { @@ -863,7 +897,10 @@ int32_t hts221_hum_rh_point_0_get(const stmdev_ctx_t *ctx, float_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_H0_RH_X2, &coeff, 1); - *val = (float_t)coeff / 2.0f; + if (ret == 0) + { + *val = (float_t)coeff / 2.0f; + } return ret; } @@ -882,7 +919,10 @@ int32_t hts221_hum_rh_point_1_get(const stmdev_ctx_t *ctx, float_t *val) int32_t ret; ret = hts221_read_reg(ctx, HTS221_H1_RH_X2, &coeff, 1); - *val = (float_t)coeff / 2.0f; + if (ret == 0) + { + *val = (float_t)coeff / 2.0f; + } return ret; } @@ -908,7 +948,10 @@ int32_t hts221_temp_deg_point_0_get(const stmdev_ctx_t *ctx, float_t *val) { ret = hts221_read_reg(ctx, HTS221_T1_T0_MSB, (uint8_t *) ®, 1); coeff_h = reg.t0_msb; - *val = (((float_t)coeff_h * 256.0f) + (float_t)coeff_l) / 8.0f; + if (ret == 0) + { + *val = (((float_t)coeff_h * 256.0f) + (float_t)coeff_l) / 8.0f; + } } return ret; @@ -935,7 +978,10 @@ int32_t hts221_temp_deg_point_1_get(const stmdev_ctx_t *ctx, float_t *val) { ret = hts221_read_reg(ctx, HTS221_T1_T0_MSB, (uint8_t *) ®, 1); coeff_h = reg.t1_msb; - *val = (((float_t)coeff_h * 256.0f) + (float_t)coeff_l) / 8.0f; + if (ret == 0) + { + *val = (((float_t)coeff_h * 256.0f) + (float_t)coeff_l) / 8.0f; + } } return ret; @@ -957,7 +1003,10 @@ int32_t hts221_hum_adc_point_0_get(const stmdev_ctx_t *ctx, float_t *val) ret = hts221_read_reg(ctx, HTS221_H0_T0_OUT_L, coeff_p, 2); coeff = ((int16_t)coeff_p[1] * 256) + (int16_t)coeff_p[0]; - *val = (float_t)coeff * 1.0f; + if (ret == 0) + { + *val = (float_t)coeff * 1.0f; + } return ret; } @@ -978,7 +1027,10 @@ int32_t hts221_hum_adc_point_1_get(const stmdev_ctx_t *ctx, float_t *val) ret = hts221_read_reg(ctx, HTS221_H1_T0_OUT_L, coeff_p, 2); coeff = ((int16_t)coeff_p[1] * 256) + (int16_t)coeff_p[0]; - *val = (float_t)coeff * 1.0f; + if (ret == 0) + { + *val = (float_t)coeff * 1.0f; + } return ret; } @@ -999,7 +1051,10 @@ int32_t hts221_temp_adc_point_0_get(const stmdev_ctx_t *ctx, float_t *val) ret = hts221_read_reg(ctx, HTS221_T0_OUT_L, coeff_p, 2); coeff = ((int16_t)coeff_p[1] * 256) + (int16_t)coeff_p[0]; - *val = (float_t)coeff * 1.0f; + if (ret == 0) + { + *val = (float_t)coeff * 1.0f; + } return ret; } @@ -1020,7 +1075,10 @@ int32_t hts221_temp_adc_point_1_get(const stmdev_ctx_t *ctx, float_t *val) ret = hts221_read_reg(ctx, HTS221_T1_OUT_L, coeff_p, 2); coeff = ((int16_t)coeff_p[1] * 256) + (int16_t)coeff_p[0]; - *val = (float_t)coeff * 1.0f; + if (ret == 0) + { + *val = (float_t)coeff * 1.0f; + } return ret; } @@ -1029,5 +1087,3 @@ int32_t hts221_temp_adc_point_1_get(const stmdev_ctx_t *ctx, float_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h index b4624b2..ea3fe56 100644 --- a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h +++ b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -404,5 +406,3 @@ int32_t hts221_temp_adc_point_1_get(const stmdev_ctx_t *ctx, float_t *val); #endif #endif /*HTS221_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c index 1d8903a..5dbaa03 100644 --- a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c +++ b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -159,6 +158,7 @@ int32_t i3g4250d_data_rate_get(const stmdev_ctx_t *ctx, i3g4250d_dr_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pd) { @@ -235,6 +235,7 @@ int32_t i3g4250d_full_scale_get(const stmdev_ctx_t *ctx, i3g4250d_fs_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.fs) { @@ -291,6 +292,8 @@ int32_t i3g4250d_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -326,7 +329,7 @@ int32_t i3g4250d_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) /** * @brief Angular rate sensor. The value is expressed as a 16-bit word in - * two’s complement.[get] + * two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores the data read.(ptr) @@ -339,6 +342,8 @@ int32_t i3g4250d_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = i3g4250d_read_reg(ctx, I3G4250D_OUT_X_L, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -419,6 +424,7 @@ int32_t i3g4250d_self_test_get(const stmdev_ctx_t *ctx, i3g4250d_st_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.st) { @@ -485,6 +491,7 @@ int32_t i3g4250d_data_format_get(const stmdev_ctx_t *ctx, ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.ble) { @@ -545,6 +552,8 @@ int32_t i3g4250d_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg5.boot; return ret; @@ -606,6 +615,7 @@ int32_t i3g4250d_lp_bandwidth_get(const stmdev_ctx_t *ctx, ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } switch (ctrl_reg1.bw) { @@ -676,6 +686,7 @@ int32_t i3g4250d_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpcf) { @@ -768,6 +779,7 @@ int32_t i3g4250d_hp_mode_get(const stmdev_ctx_t *ctx, i3g4250d_hpm_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpm) { @@ -839,6 +851,7 @@ int32_t i3g4250d_filter_path_get(const stmdev_ctx_t *ctx, ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg5.hpen << 2) + ctrl_reg5.out_sel) { @@ -910,6 +923,7 @@ int32_t i3g4250d_filter_path_internal_get(const stmdev_ctx_t *ctx, ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg5.hpen << 2) + ctrl_reg5.int1_sel) { @@ -980,6 +994,8 @@ int32_t i3g4250d_hp_reference_value_get(const stmdev_ctx_t *ctx, ret = i3g4250d_read_reg(ctx, I3G4250D_REFERENCE, (uint8_t *)&reference, 1); + if (ret != 0) { return ret; } + *val = reference.ref; return ret; @@ -1039,6 +1055,7 @@ int32_t i3g4250d_spi_mode_get(const stmdev_ctx_t *ctx, i3g4250d_sim_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.sim) { @@ -1116,6 +1133,8 @@ int32_t i3g4250d_pin_int1_route_get(const stmdev_ctx_t *ctx, ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + val->i1_int1 = ctrl_reg3.i1_int1; val->i1_boot = ctrl_reg3.i1_boot; @@ -1167,6 +1186,8 @@ int32_t i3g4250d_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + val->i2_empty = ctrl_reg3.i2_empty; val->i2_orun = ctrl_reg3.i2_orun; val->i2_wtm = ctrl_reg3.i2_wtm; @@ -1217,6 +1238,7 @@ int32_t i3g4250d_pin_mode_get(const stmdev_ctx_t *ctx, ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.pp_od) { @@ -1279,6 +1301,7 @@ int32_t i3g4250d_pin_polarity_get(const stmdev_ctx_t *ctx, ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.h_lactive) { @@ -1338,6 +1361,7 @@ int32_t i3g4250d_int_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } switch (int1_cfg.lir) { @@ -1445,6 +1469,7 @@ int32_t i3g4250d_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } switch (int1_cfg.and_or) { @@ -1543,6 +1568,8 @@ int32_t i3g4250d_int_x_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_XL, (uint8_t *)&int1_tsh_xl, 1); + if (ret != 0) { return ret; } + *val = int1_tsh_xh.thsx; *val = *val * 256U; *val += int1_tsh_xl.thsx; @@ -1612,6 +1639,8 @@ int32_t i3g4250d_int_y_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_YL, (uint8_t *)&int1_tsh_yl, 1); + if (ret != 0) { return ret; } + *val = int1_tsh_yh.thsy; *val = *val * 256U; *val += int1_tsh_yl.thsy; @@ -1681,6 +1710,8 @@ int32_t i3g4250d_int_z_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_ZL, (uint8_t *)&int1_tsh_zl, 1); + if (ret != 0) { return ret; } + *val = int1_tsh_zh.thsz; *val = *val * 256U; *val += int1_tsh_zl.thsz; @@ -1743,6 +1774,8 @@ int32_t i3g4250d_int_on_threshold_dur_get(const stmdev_ctx_t *ctx, ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_DURATION, (uint8_t *)&int1_duration, 1); + if (ret != 0) { return ret; } + *val = int1_duration.d; return ret; @@ -1801,6 +1834,8 @@ int32_t i3g4250d_fifo_enable_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg5.fifo_en; return ret; @@ -1847,6 +1882,8 @@ int32_t i3g4250d_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } + *val = fifo_ctrl_reg.wtm; return ret; @@ -1895,6 +1932,7 @@ int32_t i3g4250d_fifo_mode_get(const stmdev_ctx_t *ctx, ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl_reg.fm) { @@ -1933,6 +1971,8 @@ int32_t i3g4250d_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + if (ret != 0) { return ret; } + *val = fifo_src_reg.fss; return ret; @@ -1953,6 +1993,8 @@ int32_t i3g4250d_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + if (ret != 0) { return ret; } + *val = fifo_src_reg.empty; return ret; @@ -1973,6 +2015,8 @@ int32_t i3g4250d_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + if (ret != 0) { return ret; } + *val = fifo_src_reg.ovrn; return ret; @@ -1996,6 +2040,8 @@ int32_t i3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + if (ret != 0) { return ret; } + *val = fifo_src_reg.wtm; return ret; @@ -2005,5 +2051,3 @@ int32_t i3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h index de13137..dea9ccd 100644 --- a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h +++ b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -120,6 +119,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -778,5 +780,3 @@ int32_t i3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* I3G4250D_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c index a7519d7..629479d 100644 --- a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c +++ b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -211,7 +210,10 @@ int32_t iis2dh_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG_AUX, (uint8_t *)&status_reg_aux, 1); - *val = status_reg_aux.tda; + if (ret == 0) + { + *val = status_reg_aux.tda; + } return ret; } @@ -230,7 +232,10 @@ int32_t iis2dh_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG_AUX, (uint8_t *)&status_reg_aux, 1); - *val = status_reg_aux.tor; + if (ret == 0) + { + *val = status_reg_aux.tor; + } return ret; } @@ -248,8 +253,11 @@ int32_t iis2dh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_OUT_TEMP_L, buff, 2); - *val = (int16_t)buff[1]; - *val = (*val * 256) + (int16_t)buff[0]; + if (ret == 0) + { + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + } return ret; } @@ -296,6 +304,7 @@ int32_t iis2dh_temperature_meas_get(const stmdev_ctx_t *ctx, ret = iis2dh_read_reg(ctx, IIS2DH_TEMP_CFG_REG, (uint8_t *)&temp_cfg_reg, 1); + if (ret != 0) { return ret; } switch (temp_cfg_reg.temp_en) { @@ -385,11 +394,13 @@ int32_t iis2dh_operating_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - if (ret == 0) { ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + } + if (ret == 0) + { if (ctrl_reg1.lpen == PROPERTY_ENABLE) { *val = IIS2DH_LP_8bit; @@ -447,6 +458,7 @@ int32_t iis2dh_data_rate_get(const stmdev_ctx_t *ctx, iis2dh_odr_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } switch (ctrl_reg1.odr) { @@ -540,6 +552,8 @@ int32_t iis2dh_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg2.fds; return ret; @@ -597,6 +611,7 @@ int32_t iis2dh_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpcf) { @@ -663,6 +678,7 @@ int32_t iis2dh_high_pass_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpm) { @@ -728,6 +744,7 @@ int32_t iis2dh_full_scale_get(const stmdev_ctx_t *ctx, iis2dh_fs_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.fs) { @@ -793,6 +810,8 @@ int32_t iis2dh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg4.bdu; return ret; @@ -847,6 +866,8 @@ int32_t iis2dh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -865,6 +886,8 @@ int32_t iis2dh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.zyxor; return ret; @@ -883,6 +906,8 @@ int32_t iis2dh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_OUT_X_L, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -958,6 +983,7 @@ int32_t iis2dh_self_test_get(const stmdev_ctx_t *ctx, iis2dh_st_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.st) { @@ -1019,6 +1045,7 @@ int32_t iis2dh_data_format_get(const stmdev_ctx_t *ctx, iis2dh_ble_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.ble) { @@ -1076,6 +1103,8 @@ int32_t iis2dh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.boot; return ret; @@ -1222,6 +1251,8 @@ int32_t iis2dh_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)int1_ths.ths; return ret; @@ -1270,6 +1301,8 @@ int32_t iis2dh_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dh_read_reg(ctx, IIS2DH_INT1_DURATION, (uint8_t *)&int1_duration, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)int1_duration.d; return ret; @@ -1382,6 +1415,8 @@ int32_t iis2dh_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)int2_ths.ths; return ret; @@ -1430,6 +1465,8 @@ int32_t iis2dh_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dh_read_reg(ctx, IIS2DH_INT2_DURATION, (uint8_t *)&int2_duration, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)int2_duration.d; return ret; @@ -1487,6 +1524,7 @@ int32_t iis2dh_high_pass_int_conf_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hp) { @@ -1606,6 +1644,8 @@ int32_t iis2dh_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.d4d_int2; return ret; @@ -1655,6 +1695,7 @@ int32_t iis2dh_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } switch (ctrl_reg5.lir_int2) { @@ -1714,6 +1755,8 @@ int32_t iis2dh_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.d4d_int1; return ret; @@ -1761,6 +1804,7 @@ int32_t iis2dh_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } switch (ctrl_reg5.lir_int1) { @@ -1866,6 +1910,8 @@ int32_t iis2dh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.fifo_en; return ret; @@ -1912,6 +1958,8 @@ int32_t iis2dh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_ctrl_reg.fth; return ret; @@ -1960,6 +2008,7 @@ int32_t iis2dh_fifo_trigger_event_get(const stmdev_ctx_t *ctx, ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl_reg.tr) { @@ -2020,6 +2069,7 @@ int32_t iis2dh_fifo_mode_get(const stmdev_ctx_t *ctx, iis2dh_fm_t *val) ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl_reg.fm) { @@ -2079,6 +2129,8 @@ int32_t iis2dh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.fss; return ret; @@ -2098,6 +2150,8 @@ int32_t iis2dh_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.empty; return ret; @@ -2117,6 +2171,8 @@ int32_t iis2dh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.ovrn_fifo; return ret; @@ -2136,6 +2192,8 @@ int32_t iis2dh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.wtm; return ret; @@ -2245,6 +2303,8 @@ int32_t iis2dh_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_THS, (uint8_t *)&click_ths, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)click_ths.ths; return ret; @@ -2292,6 +2352,8 @@ int32_t iis2dh_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t *)&time_limit, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)time_limit.tli; return ret; @@ -2344,6 +2406,8 @@ int32_t iis2dh_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LATENCY, (uint8_t *)&time_latency, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)time_latency.tla; return ret; @@ -2396,6 +2460,8 @@ int32_t iis2dh_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dh_read_reg(ctx, IIS2DH_TIME_WINDOW, (uint8_t *)&time_window, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)time_window.tw; return ret; @@ -2456,6 +2522,8 @@ int32_t iis2dh_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_ACT_THS, (uint8_t *)&act_ths, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)act_ths.acth; return ret; @@ -2501,6 +2569,8 @@ int32_t iis2dh_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)act_dur.actd; return ret; @@ -2557,6 +2627,7 @@ int32_t iis2dh_spi_mode_get(const stmdev_ctx_t *ctx, iis2dh_sim_t *val) int32_t ret; ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.sim) { @@ -2580,5 +2651,3 @@ int32_t iis2dh_spi_mode_get(const stmdev_ctx_t *ctx, iis2dh_sim_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h index 87d51e8..8dd1701 100644 --- a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h +++ b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1026,5 +1028,3 @@ int32_t iis2dh_spi_mode_get(const stmdev_ctx_t *ctx, iis2dh_sim_t *val); #endif #endif /* IIS2DH_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c index c2360bd..ec180ad 100644 --- a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c +++ b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -96,42 +95,42 @@ int32_t __weak iis2dlpc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, float_t iis2dlpc_from_fs2_to_mg(int16_t lsb) { - return ((float_t)lsb) * 0.061f; + return ((float_t)lsb) * 0.244f; } float_t iis2dlpc_from_fs4_to_mg(int16_t lsb) { - return ((float_t)lsb) * 0.122f; + return ((float_t)lsb) * 0.488f; } float_t iis2dlpc_from_fs8_to_mg(int16_t lsb) { - return ((float_t)lsb) * 0.244f; + return ((float_t)lsb) * 0.976f; } float_t iis2dlpc_from_fs16_to_mg(int16_t lsb) { - return ((float_t)lsb) * 0.488f; + return ((float_t)lsb) * 1.952f; } float_t iis2dlpc_from_fs2_lp1_to_mg(int16_t lsb) { - return ((float_t)lsb) * 0.061f; + return ((float_t)lsb) * 0.976f; } float_t iis2dlpc_from_fs4_lp1_to_mg(int16_t lsb) { - return ((float_t)lsb) * 0.122f; + return ((float_t)lsb) * 1.952f; } float_t iis2dlpc_from_fs8_lp1_to_mg(int16_t lsb) { - return ((float_t)lsb) * 0.244f; + return ((float_t)lsb) * 3.904f; } float_t iis2dlpc_from_fs16_lp1_to_mg(int16_t lsb) { - return ((float_t)lsb) * 0.488f; + return ((float_t)lsb) * 7.808f; } float_t iis2dlpc_from_lsb_to_celsius(int16_t lsb) @@ -213,11 +212,12 @@ int32_t iis2dlpc_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1); + if (ret == 0) { + ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1); + } if (ret == 0) { - ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1); - switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) + ctrl1.lp_mode)) { @@ -358,11 +358,13 @@ int32_t iis2dlpc_data_rate_get(const stmdev_ctx_t *ctx, iis2dlpc_odr_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL1, (uint8_t *) &ctrl1, 1); - if (ret == 0) { ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) &ctrl3, 1); + } + if (ret == 0) + { switch ((ctrl3.slp_mode << 4) + ctrl1.odr) { case IIS2DLPC_XL_ODR_OFF: @@ -461,7 +463,10 @@ int32_t iis2dlpc_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1); - *val = reg.bdu; + if (ret == 0) + { + *val = reg.bdu; + } return ret; } @@ -563,7 +568,10 @@ int32_t iis2dlpc_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_STATUS, (uint8_t *) ®, 1); - *val = reg.drdy; + if (ret == 0) + { + *val = reg.drdy; + } return ret; } @@ -587,7 +595,7 @@ int32_t iis2dlpc_all_sources_get(const stmdev_ctx_t *ctx, } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -606,7 +614,7 @@ int32_t iis2dlpc_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -625,7 +633,7 @@ int32_t iis2dlpc_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -644,7 +652,7 @@ int32_t iis2dlpc_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -663,7 +671,7 @@ int32_t iis2dlpc_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -682,7 +690,7 @@ int32_t iis2dlpc_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -744,19 +752,22 @@ int32_t iis2dlpc_offset_weight_get(const stmdev_ctx_t *ctx, ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1); - switch (reg.usr_off_w) + if (ret == 0) { - case IIS2DLPC_LSb_977ug: - *val = IIS2DLPC_LSb_977ug; - break; + switch (reg.usr_off_w) + { + case IIS2DLPC_LSb_977ug: + *val = IIS2DLPC_LSb_977ug; + break; - case IIS2DLPC_LSb_15mg6: - *val = IIS2DLPC_LSb_15mg6; - break; + case IIS2DLPC_LSb_15mg6: + *val = IIS2DLPC_LSb_15mg6; + break; - default: - *val = IIS2DLPC_LSb_977ug; - break; + default: + *val = IIS2DLPC_LSb_977ug; + break; + } } return ret; @@ -776,7 +787,7 @@ int32_t iis2dlpc_offset_weight_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers - * together express a 16-bit word in two’s complement.[get] + * together express a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -789,15 +800,18 @@ int32_t iis2dlpc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_OUT_T_L, buff, 2); - *val = (int16_t)buff[1]; - *val = (*val * 256) + (int16_t)buff[0]; + if (ret == 0) + { + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + } return ret; } /** * @brief Linear acceleration output register. The value is expressed as - * a 16-bit word in two’s complement.[get] + * a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -810,6 +824,8 @@ int32_t iis2dlpc_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_OUT_X_L, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -889,6 +905,8 @@ int32_t iis2dlpc_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.if_add_inc; return ret; @@ -898,11 +916,10 @@ int32_t iis2dlpc_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) * @brief Software reset. Restore the default values in user registers.[set] * * @param ctx read / write interface definitions - * @param val change the values of soft_reset in reg CTRL2 * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_reset_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_reset_set(const stmdev_ctx_t *ctx) { iis2dlpc_ctrl2_t reg; int32_t ret; @@ -911,7 +928,7 @@ int32_t iis2dlpc_reset_set(const stmdev_ctx_t *ctx, uint8_t val) if (ret == 0) { - reg.soft_reset = val; + reg.soft_reset = PROPERTY_ENABLE; ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1); } @@ -932,6 +949,8 @@ int32_t iis2dlpc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.soft_reset; return ret; @@ -941,11 +960,10 @@ int32_t iis2dlpc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) * @brief Reboot memory content. Reload the calibration parameters.[set] * * @param ctx read / write interface definitions - * @param val change the values of boot in reg CTRL2 * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_boot_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_boot_set(const stmdev_ctx_t *ctx) { iis2dlpc_ctrl2_t reg; int32_t ret; @@ -954,7 +972,7 @@ int32_t iis2dlpc_boot_set(const stmdev_ctx_t *ctx, uint8_t val) if (ret == 0) { - reg.boot = val; + reg.boot = PROPERTY_ENABLE; ret = iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1); } @@ -975,6 +993,8 @@ int32_t iis2dlpc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.boot; return ret; @@ -1018,6 +1038,7 @@ int32_t iis2dlpc_self_test_get(const stmdev_ctx_t *ctx, iis2dlpc_st_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.st) { @@ -1081,6 +1102,7 @@ int32_t iis2dlpc_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.drdy_pulsed) { @@ -1171,11 +1193,13 @@ int32_t iis2dlpc_filter_path_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) &ctrl6, 1); - if (ret == 0) { ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) &ctrl_reg7, 1); + } + if (ret == 0) + { switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out) { case IIS2DLPC_LPF_ON_OUT: @@ -1241,6 +1265,7 @@ int32_t iis2dlpc_filter_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL6, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.bw_filt) { @@ -1306,6 +1331,8 @@ int32_t iis2dlpc_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.hp_ref_mode; return ret; @@ -1362,6 +1389,7 @@ int32_t iis2dlpc_spi_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_sim_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.sim) { @@ -1422,6 +1450,7 @@ int32_t iis2dlpc_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.i2c_disable) { @@ -1481,6 +1510,7 @@ int32_t iis2dlpc_cs_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.cs_pu_disc) { @@ -1552,6 +1582,7 @@ int32_t iis2dlpc_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.h_lactive) { @@ -1611,6 +1642,7 @@ int32_t iis2dlpc_int_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.lir) { @@ -1669,6 +1701,7 @@ int32_t iis2dlpc_pin_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.pp_od) { @@ -1713,6 +1746,7 @@ int32_t iis2dlpc_pin_int1_route_set(const stmdev_ctx_t *ctx, if (ret == 0) { + // `interrupts_enable` is set to ENABLE when at least one of the int1/int2 events is active if ((ctrl5_int2_pad_ctrl.int2_sleep_state | ctrl5_int2_pad_ctrl.int2_sleep_chg | val->int1_tap @@ -1790,6 +1824,7 @@ int32_t iis2dlpc_pin_int2_route_set(const stmdev_ctx_t *ctx, if (ret == 0) { + // `interrupts_enable` is set to ENABLE when at least one of the int1/int2 events is active if ((val->int2_sleep_state | val->int2_sleep_chg | ctrl4_int1_pad.int1_tap @@ -1879,6 +1914,8 @@ int32_t iis2dlpc_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.int2_on_int1; return ret; @@ -1935,6 +1972,8 @@ int32_t iis2dlpc_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.wk_ths; return ret; @@ -1978,6 +2017,8 @@ int32_t iis2dlpc_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.wake_dur; return ret; @@ -2023,6 +2064,7 @@ int32_t iis2dlpc_wkup_feed_data_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.usr_off_on_wu) { @@ -2115,12 +2157,13 @@ int32_t iis2dlpc_act_mode_get(const stmdev_ctx_t *ctx, ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) &wake_up_ths, 1); - if (ret == 0) { ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); - + } + if (ret == 0) + { switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on) { case IIS2DLPC_NO_DETECTION: @@ -2182,7 +2225,10 @@ int32_t iis2dlpc_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) ®, 1); - *val = reg.sleep_dur; + if (ret == 0) + { + *val = reg.sleep_dur; + } return ret; } @@ -2238,7 +2284,10 @@ int32_t iis2dlpc_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1); - *val = reg.tap_thsx; + if (ret == 0) + { + *val = reg.tap_thsx; + } return ret; } @@ -2281,7 +2330,10 @@ int32_t iis2dlpc_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1); - *val = reg.tap_thsy; + if (ret == 0) + { + *val = reg.tap_thsy; + } return ret; } @@ -2326,6 +2378,7 @@ int32_t iis2dlpc_tap_axis_priority_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Y, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.tap_prior) { @@ -2399,6 +2452,8 @@ int32_t iis2dlpc_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.tap_thsz; return ret; @@ -2444,6 +2499,8 @@ int32_t iis2dlpc_tap_detection_on_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.tap_z_en; return ret; @@ -2489,6 +2546,8 @@ int32_t iis2dlpc_tap_detection_on_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.tap_y_en; return ret; @@ -2534,6 +2593,8 @@ int32_t iis2dlpc_tap_detection_on_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_Z, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.tap_x_en; return ret; @@ -2585,6 +2646,8 @@ int32_t iis2dlpc_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.shock; return ret; @@ -2636,6 +2699,8 @@ int32_t iis2dlpc_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.quiet; return ret; @@ -2689,6 +2754,8 @@ int32_t iis2dlpc_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_INT_DUR, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.latency; return ret; @@ -2734,6 +2801,7 @@ int32_t iis2dlpc_tap_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_THS, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.single_double_tap) { @@ -2822,6 +2890,8 @@ int32_t iis2dlpc_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg._6d_ths; return ret; @@ -2865,6 +2935,8 @@ int32_t iis2dlpc_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_TAP_THS_X, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg._4d_en; return ret; @@ -2927,6 +2999,7 @@ int32_t iis2dlpc_6d_feed_data_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_CTRL7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.lpass_on6d) { @@ -3017,11 +3090,13 @@ int32_t iis2dlpc_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dlpc_read_reg(ctx, IIS2DLPC_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); - if (ret == 0) { ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL, (uint8_t *) &free_fall, 1); + } + if (ret == 0) + { *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; } @@ -3068,6 +3143,7 @@ int32_t iis2dlpc_ff_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FREE_FALL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.ff_ths) { @@ -3161,6 +3237,8 @@ int32_t iis2dlpc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.fth; return ret; @@ -3206,6 +3284,7 @@ int32_t iis2dlpc_fifo_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.fmode) { @@ -3251,6 +3330,8 @@ int32_t iis2dlpc_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.diff; return ret; @@ -3269,6 +3350,8 @@ int32_t iis2dlpc_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.fifo_ovr; return ret; @@ -3287,6 +3370,8 @@ int32_t iis2dlpc_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dlpc_read_reg(ctx, IIS2DLPC_FIFO_SAMPLES, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.fifo_fth; return ret; @@ -3295,5 +3380,3 @@ int32_t iis2dlpc_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h index f67c669..c1cba00 100644 --- a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h +++ b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -790,10 +792,10 @@ int32_t iis2dlpc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); int32_t iis2dlpc_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t iis2dlpc_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_reset_set(const stmdev_ctx_t *ctx); int32_t iis2dlpc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_boot_set(const stmdev_ctx_t *ctx); int32_t iis2dlpc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1072,5 +1074,3 @@ int32_t iis2dlpc_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /*IIS2DLPC_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis2dulpx_STdC/driver/iis2dulpx_reg.c b/sensor/stmemsc/iis2dulpx_STdC/driver/iis2dulpx_reg.c index 5364a88..28eb15c 100644 --- a/sensor/stmemsc/iis2dulpx_STdC/driver/iis2dulpx_reg.c +++ b/sensor/stmemsc/iis2dulpx_STdC/driver/iis2dulpx_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -166,6 +165,10 @@ int32_t iis2dulpx_init_set(const stmdev_ctx_t *ctx, iis2dulpx_init_t val) ret += iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL1, (uint8_t *)&ctrl1, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (val) { case IIS2DULPX_BOOT: @@ -278,9 +281,12 @@ int32_t iis2dulpx_status_get(const stmdev_ctx_t *ctx, iis2dulpx_status_t *val) ret += iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL1, (uint8_t *)&ctrl1, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL4, (uint8_t *)&ctrl4, 1); - val->sw_reset = ctrl1.sw_reset; - val->boot = ctrl4.boot; - val->drdy = status_register.drdy; + if (ret == 0) + { + val->sw_reset = ctrl1.sw_reset; + val->boot = ctrl4.boot; + val->drdy = status_register.drdy; + } return ret; } @@ -295,16 +301,17 @@ int32_t iis2dulpx_status_get(const stmdev_ctx_t *ctx, iis2dulpx_status_t *val) */ int32_t iis2dulpx_embedded_status_get(const stmdev_ctx_t *ctx, iis2dulpx_embedded_status_t *val) { - iis2dulpx_emb_func_status_t status; + iis2dulpx_emb_func_status_mainpage_t status; int32_t ret; - ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); - ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_STATUS, (uint8_t *)&status, 1); - ret += iis2dulpx_mem_bank_set(ctx, IIS2DULPX_MAIN_MEM_BANK); + ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_STATUS_MAINPAGE, (uint8_t *)&status, 1); - val->is_step_det = status.is_step_det; - val->is_tilt = status.is_tilt; - val->is_sigmot = status.is_sigmot; + if (ret == 0) + { + val->is_step_det = status.is_step_det; + val->is_tilt = status.is_tilt; + val->is_sigmot = status.is_sigmot; + } return ret; } @@ -348,6 +355,11 @@ int32_t iis2dulpx_data_ready_mode_get(const stmdev_ctx_t *ctx, iis2dulpx_data_re ret = iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl1.drdy_pulsed)) { case 0x0: @@ -380,6 +392,10 @@ int32_t iis2dulpx_mode_set(const stmdev_ctx_t *ctx, const iis2dulpx_md_t *val) int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } ctrl5.odr = (uint8_t)val->odr & 0xFU; ctrl5.fs = (uint8_t)val->fs; @@ -469,11 +485,6 @@ int32_t iis2dulpx_mode_set(const stmdev_ctx_t *ctx, const iis2dulpx_md_t *val) break; } - if (ret != 0) - { - return ret; - } - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL3, (uint8_t *)&ctrl3, 1); ctrl3.hp_en = (((uint8_t)val->odr & 0x30U) == 0x10U) ? 1U : 0U; @@ -504,6 +515,11 @@ int32_t iis2dulpx_mode_get(const stmdev_ctx_t *ctx, iis2dulpx_md_t *val) ret = iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL5, (uint8_t *)&ctrl5, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5.odr) { case 0x00: @@ -632,7 +648,10 @@ int32_t iis2dulpx_t_ah_qvar_dis_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_SELF_TEST, (uint8_t *)&temp, 1); - *val = temp.t_ah_qvar_dis; + if (ret == 0) + { + *val = temp.t_ah_qvar_dis; + } return ret; } @@ -699,7 +718,10 @@ int32_t iis2dulpx_disable_hard_reset_from_cs_set(const stmdev_ctx_t *ctx, uint8_ ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); fifo_ctrl.dis_hard_rst_cs = (val == 1) ? PROPERTY_ENABLE : PROPERTY_DISABLE; - ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret == 0) + { + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + } return ret; } @@ -717,7 +739,10 @@ int32_t iis2dulpx_disable_hard_reset_from_cs_get(const stmdev_ctx_t *ctx, uint8_ int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - *val = fifo_ctrl.dis_hard_rst_cs; + if (ret == 0) + { + *val = fifo_ctrl.dis_hard_rst_cs; + } return ret; } @@ -765,6 +790,11 @@ int32_t iis2dulpx_all_sources_get(const stmdev_ctx_t *ctx, iis2dulpx_all_sources ret += iis2dulpx_read_reg(ctx, IIS2DULPX_WAKE_UP_SRC, (uint8_t *)&wu_src, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_TAP_SRC, (uint8_t *)&tap_src, 1); + if (ret != 0) + { + return ret; + } + val->six_d = sixd_src.d6d_ia; val->six_d_xl = sixd_src.xl; val->six_d_xh = sixd_src.xh; @@ -808,6 +838,11 @@ int32_t iis2dulpx_xl_data_get(const stmdev_ctx_t *ctx, const iis2dulpx_md_t *md, ret = iis2dulpx_read_reg(ctx, IIS2DULPX_OUT_X_L, buff, 6); + if (ret != 0) + { + return ret; + } + /* acceleration conversion */ j = 0U; for (i = 0U; i < 3U; i++) @@ -855,6 +890,11 @@ int32_t iis2dulpx_outt_data_get(const stmdev_ctx_t *ctx, ret = iis2dulpx_read_reg(ctx, IIS2DULPX_OUT_T_AH_QVAR_L, buff, 2); + if (ret != 0) + { + return ret; + } + data->heat.raw = (int16_t)buff[1U]; data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[0]; /* temperature conversion */ @@ -881,6 +921,11 @@ int32_t iis2dulpx_ah_qvar_data_get(const stmdev_ctx_t *ctx, /* Read and discard also OUT_Z_H reg to clear drdy */ ret = iis2dulpx_read_reg(ctx, IIS2DULPX_OUT_T_AH_QVAR_L - 1, buff, 3); + if (ret != 0) + { + return ret; + } + data->raw = (int16_t)buff[2U]; data->raw = (data->raw * 256) + (int16_t) buff[1U]; @@ -904,6 +949,10 @@ int32_t iis2dulpx_self_test_sign_set(const stmdev_ctx_t *ctx, iis2dulpx_xl_self_ ret = iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL3, (uint8_t *)&ctrl3, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1); + if (ret != 0) + { + return ret; + } switch (val) { @@ -1013,13 +1062,19 @@ int32_t iis2dulpx_i3c_configure_set(const stmdev_ctx_t *ctx, const iis2dulpx_i3c * @param val configuration params * @retval interface status (MANDATORY: return 0 -> no Error) * - */int32_t iis2dulpx_i3c_configure_get(const stmdev_ctx_t *ctx, iis2dulpx_i3c_cfg_t *val) + */ +int32_t iis2dulpx_i3c_configure_get(const stmdev_ctx_t *ctx, iis2dulpx_i3c_cfg_t *val) { iis2dulpx_i3c_if_ctrl_t i3c_cfg; int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1); + if (ret != 0) + { + return ret; + } + val->drstdaa_en = i3c_cfg.dis_drstdaa; val->asf_on = i3c_cfg.asf_on; @@ -1084,6 +1139,10 @@ int32_t iis2dulpx_mem_bank_get(const stmdev_ctx_t *ctx, iis2dulpx_mem_bank_t *va int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } switch ((func_cfg_access.emb_func_reg_access)) { @@ -1134,12 +1193,20 @@ int32_t iis2dulpx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* page write */ ret = iis2dulpx_read_reg(ctx, IIS2DULPX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_ENABLE; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_PAGE_RW, (uint8_t *)&page_rw, 1); /* set page num */ ret += iis2dulpx_read_reg(ctx, IIS2DULPX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += iis2dulpx_write_reg(ctx, IIS2DULPX_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -1159,6 +1226,10 @@ int32_t iis2dulpx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t { msb++; ret += iis2dulpx_read_reg(ctx, IIS2DULPX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += iis2dulpx_write_reg(ctx, IIS2DULPX_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -1175,6 +1246,10 @@ int32_t iis2dulpx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t ret += iis2dulpx_write_reg(ctx, IIS2DULPX_PAGE_SEL, (uint8_t *)&page_sel, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -1217,6 +1292,10 @@ int32_t iis2dulpx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* page read */ ret = iis2dulpx_read_reg(ctx, IIS2DULPX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -1227,6 +1306,10 @@ int32_t iis2dulpx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* set page num */ ret = iis2dulpx_read_reg(ctx, IIS2DULPX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += iis2dulpx_write_reg(ctx, IIS2DULPX_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -1252,6 +1335,10 @@ int32_t iis2dulpx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* set page */ ret += iis2dulpx_read_reg(ctx, IIS2DULPX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += iis2dulpx_write_reg(ctx, IIS2DULPX_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -1268,6 +1355,10 @@ int32_t iis2dulpx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t ret += iis2dulpx_write_reg(ctx, IIS2DULPX_PAGE_SEL, (uint8_t *)&page_sel, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -1304,8 +1395,11 @@ int32_t iis2dulpx_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EXT_CLK_CFG, (uint8_t *)&clk, 1); - clk.ext_clk_en = val; - ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EXT_CLK_CFG, (uint8_t *)&clk, 1); + if (ret == 0) + { + clk.ext_clk_en = val; + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EXT_CLK_CFG, (uint8_t *)&clk, 1); + } return ret; } @@ -1324,7 +1418,10 @@ int32_t iis2dulpx_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EXT_CLK_CFG, (uint8_t *)&clk, 1); - *val = clk.ext_clk_en; + if (ret == 0) + { + *val = clk.ext_clk_en; + } return ret; } @@ -1374,12 +1471,15 @@ int32_t iis2dulpx_pin_conf_get(const stmdev_ctx_t *ctx, iis2dulpx_pin_conf_t *va ret = iis2dulpx_read_reg(ctx, IIS2DULPX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); - val->cs_pull_up = ~pin_ctrl.cs_pu_dis; - val->int1_pull_down = ~pin_ctrl.pd_dis_int1; - val->int2_pull_down = ~pin_ctrl.pd_dis_int2; - val->sda_pull_up = pin_ctrl.sda_pu_en; - val->sdo_pull_up = pin_ctrl.sdo_pu_en; - val->int1_int2_push_pull = ~pin_ctrl.pp_od; + if (ret == 0) + { + val->cs_pull_up = ~pin_ctrl.cs_pu_dis; + val->int1_pull_down = ~pin_ctrl.pd_dis_int1; + val->int2_pull_down = ~pin_ctrl.pd_dis_int2; + val->sda_pull_up = pin_ctrl.sda_pu_en; + val->sdo_pull_up = pin_ctrl.sdo_pu_en; + val->int1_int2_push_pull = ~pin_ctrl.pp_od; + } return ret; } @@ -1423,6 +1523,11 @@ int32_t iis2dulpx_int_pin_polarity_get(const stmdev_ctx_t *ctx, iis2dulpx_int_pi ret = iis2dulpx_read_reg(ctx, IIS2DULPX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + switch ((pin_ctrl.h_lactive)) { case 0x0: @@ -1478,6 +1583,10 @@ int32_t iis2dulpx_spi_mode_get(const stmdev_ctx_t *ctx, iis2dulpx_spi_mode *val) int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch ((pin_ctrl.sim)) { @@ -1732,8 +1841,8 @@ int32_t iis2dulpx_pin_int2_route_get(const stmdev_ctx_t *ctx, iis2dulpx_pin_int_ iis2dulpx_md2_cfg_t md2_cfg; int32_t ret; - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL2, (uint8_t *)&ctrl3, 1); - ret += iis2dulpx_read_reg(ctx, IIS2DULPX_MD1_CFG, (uint8_t *)&md2_cfg, 1); + ret = iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL3, (uint8_t *)&ctrl3, 1); + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_MD2_CFG, (uint8_t *)&md2_cfg, 1); if (ret == 0) { @@ -1927,19 +2036,22 @@ int32_t iis2dulpx_embedded_int_cfg_set(const stmdev_ctx_t *ctx, iis2dulpx_embedd { ret = iis2dulpx_read_reg(ctx, IIS2DULPX_PAGE_RW, (uint8_t *)&page_rw, 1); - switch (val) + if (ret == 0) { - case IIS2DULPX_EMBEDDED_INT_LEVEL: - page_rw.emb_func_lir = 0; - break; + switch (val) + { + case IIS2DULPX_EMBEDDED_INT_LEVEL: + page_rw.emb_func_lir = 0; + break; - case IIS2DULPX_EMBEDDED_INT_LATCHED: - default: - page_rw.emb_func_lir = 1; - break; - } + case IIS2DULPX_EMBEDDED_INT_LATCHED: + default: + page_rw.emb_func_lir = 1; + break; + } - ret += iis2dulpx_write_reg(ctx, IIS2DULPX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_PAGE_RW, (uint8_t *)&page_rw, 1); + } } ret += iis2dulpx_mem_bank_set(ctx, IIS2DULPX_MAIN_MEM_BANK); @@ -1966,13 +2078,16 @@ int32_t iis2dulpx_embedded_int_cfg_get(const stmdev_ctx_t *ctx, { ret = iis2dulpx_read_reg(ctx, IIS2DULPX_PAGE_RW, (uint8_t *)&page_rw, 1); - if (page_rw.emb_func_lir == 0U) - { - *val = IIS2DULPX_EMBEDDED_INT_LEVEL; - } - else + if (ret == 0) { - *val = IIS2DULPX_EMBEDDED_INT_LATCHED; + if (page_rw.emb_func_lir == 0U) + { + *val = IIS2DULPX_EMBEDDED_INT_LEVEL; + } + else + { + *val = IIS2DULPX_EMBEDDED_INT_LATCHED; + } } } @@ -2006,12 +2121,10 @@ int32_t iis2dulpx_fifo_mode_set(const stmdev_ctx_t *ctx, iis2dulpx_fifo_mode_t v iis2dulpx_ctrl4_t ctrl4; iis2dulpx_fifo_ctrl_t fifo_ctrl; iis2dulpx_fifo_wtm_t fifo_wtm; - iis2dulpx_fifo_batch_dec_t fifo_batch; int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL4, (uint8_t *)&ctrl4, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - ret += iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); if (ret == 0) @@ -2033,23 +2146,11 @@ int32_t iis2dulpx_fifo_mode_set(const stmdev_ctx_t *ctx, iis2dulpx_fifo_mode_t v /* Set xl_only_fifo */ fifo_wtm.xl_only_fifo = val.xl_only; - /* set batching info */ - fifo_batch.dec_ts_batch = (uint8_t)val.batch.dec_ts; - fifo_batch.bdr_xl = (uint8_t)val.batch.bdr_xl; - fifo_ctrl.cfg_chg_en = val.cfg_change_in_fifo; - /* set watermark */ - if (val.watermark > 0U) - { - fifo_ctrl.stop_on_fth = (val.fifo_event == IIS2DULPX_FIFO_EV_WTM) ? 1 : 0; - fifo_wtm.fth = val.watermark; - } - - ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); - ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); - ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); ret += iis2dulpx_write_reg(ctx, IIS2DULPX_CTRL4, (uint8_t *)&ctrl4, 1); + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); } return ret; @@ -2068,12 +2169,10 @@ int32_t iis2dulpx_fifo_mode_get(const stmdev_ctx_t *ctx, iis2dulpx_fifo_mode_t * iis2dulpx_ctrl4_t ctrl4; iis2dulpx_fifo_ctrl_t fifo_ctrl; iis2dulpx_fifo_wtm_t fifo_wtm; - iis2dulpx_fifo_batch_dec_t fifo_batch; int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL4, (uint8_t *)&ctrl4, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - ret += iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); if (ret == 0) @@ -2095,12 +2194,155 @@ int32_t iis2dulpx_fifo_mode_get(const stmdev_ctx_t *ctx, iis2dulpx_fifo_mode_t * /* Get xl_only_fifo */ val->xl_only = fifo_wtm.xl_only_fifo; - /* get batching info */ - val->batch.dec_ts = (iis2dulpx_dec_ts_t)fifo_batch.dec_ts_batch; - val->batch.bdr_xl = (iis2dulpx_bdr_xl_t)fifo_batch.bdr_xl; + } + + return ret; +} + +/** + * @brief FIFO watermark threshold.[set] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold, maximum value is 127. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t iis2dulpx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + iis2dulpx_fifo_wtm_t fifo_wtm; + int32_t ret; + + ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + + if (ret == 0) + { + fifo_wtm.fth = val; + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark threshold.[get] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold, maximum value is 127. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t iis2dulpx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + iis2dulpx_fifo_wtm_t fifo_wtm; + int32_t ret; + + ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + + if (ret == 0) + { + *val = fifo_wtm.fth; + } + + return ret; +} + + +/** + * @brief FIFO batch.[set] + * + * @param ctx read / write interface definitions + * @param val Select value for bdr_xl: BDR_XL_ODR, BDR_XL_ODR_DIV_2, BDR_XL_ODR_DIV_4, BDR_XL_ODR_DIV_8, + * BDR_XL_ODR_DIV_16, BDR_XL_ODR_DIV_32, BDR_XL_ODR_DIV_64, BDR_XL_ODR_OFF; + * and dec_ts: DEC_TS_OFF, DEC_TS_1, DEC_TS_8, DEC_TS_32 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t iis2dulpx_fifo_batch_set(const stmdev_ctx_t *ctx, iis2dulpx_fifo_batch_t val) +{ + iis2dulpx_fifo_batch_dec_t fifo_batch; + int32_t ret; + + ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + + if (ret == 0) + { + fifo_batch.dec_ts_batch = (uint8_t)val.dec_ts; + fifo_batch.bdr_xl = (uint8_t)val.bdr_xl; + + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + } + + return ret; +} + +/** + * @brief FIFO batch.[get] + * + * @param ctx read / write interface definitions + * @param val Select value for bdr_xl: BDR_XL_ODR, BDR_XL_ODR_DIV_2, BDR_XL_ODR_DIV_4, BDR_XL_ODR_DIV_8, + * BDR_XL_ODR_DIV_16, BDR_XL_ODR_DIV_32, BDR_XL_ODR_DIV_64, BDR_XL_ODR_OFF; + * and dec_ts: DEC_TS_OFF, DEC_TS_1, DEC_TS_8, DEC_TS_32 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t iis2dulpx_fifo_batch_get(const stmdev_ctx_t *ctx, iis2dulpx_fifo_batch_t *val) +{ + iis2dulpx_fifo_batch_dec_t fifo_batch; + int32_t ret; + + ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + + if (ret == 0) + { + val->dec_ts = fifo_batch.dec_ts_batch; + val->bdr_xl = fifo_batch.bdr_xl; + } + + return ret; +} + +/** + * @brief FIFO stop on wtm.[set] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable stop on wtm functionality. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t iis2dulpx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, iis2dulpx_fifo_event_t val) +{ + iis2dulpx_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - /* get watermark */ - val->watermark = fifo_wtm.fth; + if (ret == 0) + { + fifo_ctrl.stop_on_fth = (val == IIS2DULPX_FIFO_EV_WTM) ? 1 : 0; + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + } + + return ret; +} + +/** + * @brief FIFO stop on wtm.[get] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable stop on wtm functionality. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t iis2dulpx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, iis2dulpx_fifo_event_t *val) +{ + iis2dulpx_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + + if (ret == 0) + { + *val = (fifo_ctrl.stop_on_fth == 1) ? IIS2DULPX_FIFO_EV_WTM : IIS2DULPX_FIFO_EV_FULL; } return ret; @@ -2121,7 +2363,10 @@ int32_t iis2dulpx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_STATUS2, &buff, 1); - *val = buff; + if (ret == 0) + { + *val = buff; + } return ret; } @@ -2133,7 +2378,10 @@ int32_t iis2dulpx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); - *val = fifo_status1.fifo_wtm_ia; + if (ret == 0) + { + *val = fifo_status1.fifo_wtm_ia; + } return ret; } @@ -2145,7 +2393,10 @@ int32_t iis2dulpx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, iis2dulpx_fifo_se ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); - *val = (iis2dulpx_fifo_sensor_tag_t) fifo_tag.tag_sensor; + if (ret == 0) + { + *val = (iis2dulpx_fifo_sensor_tag_t) fifo_tag.tag_sensor; + } return ret; } @@ -2168,6 +2419,10 @@ int32_t iis2dulpx_fifo_data_get(const stmdev_ctx_t *ctx, const iis2dulpx_md_t *m int32_t ret, i; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); + if (ret != 0) + { + return ret; + } data->tag = fifo_tag.tag_sensor; switch (fifo_tag.tag_sensor) @@ -2176,6 +2431,10 @@ int32_t iis2dulpx_fifo_data_get(const stmdev_ctx_t *ctx, const iis2dulpx_md_t *m case IIS2DULPX_XL_ONLY_2X_TAG_2ND: /* A FIFO sample consists of 2X 8-bits 3-axis XL at ODR/2 */ ret = iis2dulpx_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } for (i = 0; i < 3; i++) { data->xl[0].raw[i] = (int16_t)fifo_raw[i] * 256; @@ -2185,6 +2444,10 @@ int32_t iis2dulpx_fifo_data_get(const stmdev_ctx_t *ctx, const iis2dulpx_md_t *m case IIS2DULPX_XL_AND_QVAR: case IIS2DULPX_XL_TEMP_TAG: ret = iis2dulpx_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } if (fmd->xl_only == 0x0U) { /* A FIFO sample consists of 12-bits 3-axis XL + T at ODR*/ @@ -2216,6 +2479,10 @@ int32_t iis2dulpx_fifo_data_get(const stmdev_ctx_t *ctx, const iis2dulpx_md_t *m break; case IIS2DULPX_TIMESTAMP_TAG: ret = iis2dulpx_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } data->cfg_chg.cfg_change = fifo_raw[0] >> 7; data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU; @@ -2234,6 +2501,10 @@ int32_t iis2dulpx_fifo_data_get(const stmdev_ctx_t *ctx, const iis2dulpx_md_t *m case IIS2DULPX_STEP_COUNTER_TAG: ret = iis2dulpx_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } data->pedo.steps = fifo_raw[1]; data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0]; @@ -2324,6 +2595,10 @@ int32_t iis2dulpx_ah_qvar_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_AH_QVAR_CFG, (uint8_t *)&ah_qvar_cfg, 1); + if (ret != 0) + { + return ret; + } switch (ah_qvar_cfg.ah_qvar_gain) { @@ -2410,19 +2685,23 @@ int32_t iis2dulpx_stpcnt_mode_set(const stmdev_ctx_t *ctx, iis2dulpx_stpcnt_mode ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); - if ((val.false_step_rej == PROPERTY_ENABLE) - && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) + if (ret == 0) { - emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; - } + if ((val.false_step_rej == PROPERTY_ENABLE) + && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) + { + emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + } - emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo; - ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); + emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo; + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); - emb_func_en_a.pedo_en = val.step_counter_enable; - ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.pedo_en = val.step_counter_enable; + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } ret += iis2dulpx_mem_bank_set(ctx, IIS2DULPX_MAIN_MEM_BANK); + ret += iis2dulpx_ln_pg_read(ctx, IIS2DULPX_EMB_ADV_PG_0 + IIS2DULPX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); @@ -2447,17 +2726,24 @@ int32_t iis2dulpx_stpcnt_mode_set(const stmdev_ctx_t *ctx, iis2dulpx_stpcnt_mode int32_t iis2dulpx_stpcnt_mode_get(const stmdev_ctx_t *ctx, iis2dulpx_stpcnt_mode_t *val) { iis2dulpx_emb_func_en_a_t emb_func_en_a; + iis2dulpx_emb_func_fifo_en_t emb_func_fifo_en; iis2dulpx_pedo_cmd_reg_t pedo_cmd_reg; int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); ret += iis2dulpx_mem_bank_set(ctx, IIS2DULPX_MAIN_MEM_BANK); ret += iis2dulpx_ln_pg_read(ctx, IIS2DULPX_EMB_ADV_PG_0 + IIS2DULPX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); - val->false_step_rej = pedo_cmd_reg.fp_rejection_en; - val->step_counter_enable = emb_func_en_a.pedo_en; + + if (ret == 0) + { + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + val->step_counter_in_fifo = emb_func_fifo_en.step_counter_fifo_en; + } return ret; } @@ -2479,8 +2765,11 @@ int32_t iis2dulpx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) ret += iis2dulpx_read_reg(ctx, IIS2DULPX_STEP_COUNTER_L, &buff[0], 2); ret += iis2dulpx_mem_bank_set(ctx, IIS2DULPX_MAIN_MEM_BANK); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -2499,9 +2788,9 @@ int32_t iis2dulpx_stpcnt_rst_step_set(const stmdev_ctx_t *ctx) int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); + ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); emb_func_src.pedo_rst_step = 1; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); } @@ -2546,7 +2835,10 @@ int32_t iis2dulpx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dulpx_ln_pg_read(ctx, IIS2DULPX_EMB_ADV_PG_0 + IIS2DULPX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); - *val = pedo_deb_steps_conf.deb_step; + if (ret == 0) + { + *val = pedo_deb_steps_conf.deb_step; + } return ret; } @@ -2588,8 +2880,11 @@ int32_t iis2dulpx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = iis2dulpx_ln_pg_read(ctx, IIS2DULPX_EMB_ADV_PG_0 + IIS2DULPX_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -2608,6 +2903,10 @@ int32_t iis2dulpx_smart_power_set(const stmdev_ctx_t *ctx, iis2dulpx_smart_power int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } ctrl1.smart_power_en = val.enable; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_CTRL1, (uint8_t *)&ctrl1, 1); @@ -2639,12 +2938,16 @@ int32_t iis2dulpx_smart_power_get(const stmdev_ctx_t *ctx, iis2dulpx_smart_power int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_CTRL1, (uint8_t *)&ctrl1, 1); - val->enable = ctrl1.smart_power_en; ret += iis2dulpx_ln_pg_read(ctx, IIS2DULPX_EMB_ADV_PG_0 + IIS2DULPX_SMART_POWER_CTRL, (uint8_t *)&smart_power_ctrl, 1); - val->window = smart_power_ctrl.smart_power_ctrl_win; - val->duration = smart_power_ctrl.smart_power_ctrl_dur; + + if (ret == 0) + { + val->enable = ctrl1.smart_power_en; + val->window = smart_power_ctrl.smart_power_ctrl_win; + val->duration = smart_power_ctrl.smart_power_ctrl_dur; + } return ret; } @@ -2674,9 +2977,9 @@ int32_t iis2dulpx_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); emb_func_en_a.tilt_en = val; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } @@ -2700,9 +3003,9 @@ int32_t iis2dulpx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); *val = emb_func_en_a.tilt_en; } @@ -2736,9 +3039,9 @@ int32_t iis2dulpx_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); emb_func_en_a.sign_motion_en = val; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } @@ -2762,9 +3065,9 @@ int32_t iis2dulpx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); *val = emb_func_en_a.sign_motion_en; } @@ -2807,9 +3110,9 @@ int32_t iis2dulpx_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val) ret = iis2dulpx_write_reg(ctx, IIS2DULPX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); } + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_FREE_FALL, (uint8_t *)&free_fall, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FREE_FALL, (uint8_t *)&free_fall, 1); free_fall.ff_dur = val & 0x1FU; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FREE_FALL, (uint8_t *)&free_fall, 1); } @@ -2834,7 +3137,10 @@ int32_t iis2dulpx_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2dulpx_read_reg(ctx, IIS2DULPX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_FREE_FALL, (uint8_t *)&free_fall, 1); - *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur; + if (ret == 0) + { + *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur; + } return ret; } @@ -2853,8 +3159,11 @@ int32_t iis2dulpx_ff_thresholds_set(const stmdev_ctx_t *ctx, iis2dulpx_ff_thresh int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FREE_FALL, (uint8_t *)&free_fall, 1); - free_fall.ff_ths = ((uint8_t)val & 0x7U); - ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = ((uint8_t)val & 0x7U); + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FREE_FALL, (uint8_t *)&free_fall, 1); + } return ret; } @@ -2874,6 +3183,11 @@ int32_t iis2dulpx_ff_thresholds_get(const stmdev_ctx_t *ctx, iis2dulpx_ff_thresh ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } + switch (free_fall.ff_ths) { case 0x0: @@ -2966,6 +3280,10 @@ int32_t iis2dulpx_sixd_config_get(const stmdev_ctx_t *ctx, iis2dulpx_sixd_config int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_SIXD, (uint8_t *)&sixd, 1); + if (ret != 0) + { + return ret; + } val->mode = (iis2dulpx_mode_t)sixd.d4d_en; @@ -3273,7 +3591,10 @@ int32_t iis2dulpx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); - *val = int_cfg.timestamp_en; + if (ret == 0) + { + *val = int_cfg.timestamp_en; + } return ret; } @@ -3294,6 +3615,10 @@ int32_t iis2dulpx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = iis2dulpx_read_reg(ctx, IIS2DULPX_TIMESTAMP0, buff, 4); + if (ret != 0) + { + return ret; + } *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -3331,12 +3656,10 @@ int32_t iis2dulpx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); - + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_STATUS, + (uint8_t *)&emb_func_status, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_STATUS, - (uint8_t *)&emb_func_status, 1); - *val = emb_func_status.is_fsm_lc; } @@ -3359,12 +3682,10 @@ int32_t iis2dulpx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) iis2dulpx_emb_func_en_b_t emb_func_en_b; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); - + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - emb_func_en_b.fsm_en = (uint8_t)val; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, @@ -3390,16 +3711,11 @@ int32_t iis2dulpx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) iis2dulpx_emb_func_en_b_t emb_func_en_b; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); - + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - *val = emb_func_en_b.fsm_en; - - ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); } ret += iis2dulpx_mem_bank_set(ctx, IIS2DULPX_MAIN_MEM_BANK); @@ -3429,11 +3745,10 @@ int32_t iis2dulpx_fsm_enable_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_enable, 1); } + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - if ((val->fsm_enable.fsm1_en | val->fsm_enable.fsm2_en | val->fsm_enable.fsm3_en | @@ -3594,12 +3909,10 @@ int32_t iis2dulpx_fsm_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); - + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_FSM_ODR, + (uint8_t *)&fsm_odr_reg, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_FSM_ODR, - (uint8_t *)&fsm_odr_reg, 1); - fsm_odr_reg.fsm_odr = (uint8_t)val; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_FSM_ODR, (uint8_t *)&fsm_odr_reg, 1); @@ -3628,6 +3941,11 @@ int32_t iis2dulpx_fsm_data_rate_get(const stmdev_ctx_t *ctx, ret += iis2dulpx_read_reg(ctx, IIS2DULPX_FSM_ODR, (uint8_t *)&fsm_odr_reg, 1); ret += iis2dulpx_mem_bank_set(ctx, IIS2DULPX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (fsm_odr_reg.fsm_odr) { case 0: @@ -3680,12 +3998,11 @@ int32_t iis2dulpx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); - emb_func_init_b.fsm_init = (uint8_t)val; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_INIT_B, @@ -3711,12 +4028,10 @@ int32_t iis2dulpx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); - + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); - *val = emb_func_init_b.fsm_init; } @@ -3739,10 +4054,9 @@ int32_t iis2dulpx_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); - + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); fifo_reg.fsm_fifo_en = val; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); } @@ -3766,10 +4080,9 @@ int32_t iis2dulpx_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); - + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); *val = fifo_reg.fsm_fifo_en; } @@ -3820,8 +4133,11 @@ int32_t iis2dulpx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dulpx_ln_pg_read(ctx, IIS2DULPX_FSM_LC_TIMEOUT_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -3898,8 +4214,11 @@ int32_t iis2dulpx_fsm_start_address_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dulpx_ln_pg_read(ctx, IIS2DULPX_FSM_START_ADD_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -3939,27 +4258,30 @@ int32_t iis2dulpx_mlc_set(const stmdev_ctx_t *ctx, iis2dulpx_mlc_mode_t val) ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - switch (val) + if (ret == 0) { - case IIS2DULPX_MLC_OFF: - emb_en_a.mlc_before_fsm_en = 0; - emb_en_b.mlc_en = 0; - break; - case IIS2DULPX_MLC_ON: - emb_en_a.mlc_before_fsm_en = 0; - emb_en_b.mlc_en = 1; - break; - case IIS2DULPX_MLC_ON_BEFORE_FSM: - emb_en_a.mlc_before_fsm_en = 1; - emb_en_b.mlc_en = 0; - break; - default: - /* do nothing */ - break; - } + switch (val) + { + case IIS2DULPX_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case IIS2DULPX_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case IIS2DULPX_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + /* do nothing */ + break; + } - ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); - ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } } ret += iis2dulpx_mem_bank_set(ctx, IIS2DULPX_MAIN_MEM_BANK); @@ -3989,21 +4311,24 @@ int32_t iis2dulpx_mlc_get(const stmdev_ctx_t *ctx, iis2dulpx_mlc_mode_t *val) ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) - { - *val = IIS2DULPX_MLC_OFF; - } - else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) - { - *val = IIS2DULPX_MLC_ON; - } - else if (emb_en_a.mlc_before_fsm_en == 1U) - { - *val = IIS2DULPX_MLC_ON_BEFORE_FSM; - } - else + if (ret == 0) { - /* Do nothing */ + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = IIS2DULPX_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = IIS2DULPX_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = IIS2DULPX_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } } } @@ -4064,10 +4389,10 @@ int32_t iis2dulpx_mlc_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_MLC_ODR, (uint8_t *)®, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_MLC_ODR, (uint8_t *)®, 1); reg.mlc_odr = (uint8_t)val; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_MLC_ODR, (uint8_t *)®, 1); } @@ -4095,10 +4420,10 @@ int32_t iis2dulpx_mlc_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_MLC_ODR, (uint8_t *)®, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_MLC_ODR, (uint8_t *)®, 1); switch (reg.mlc_odr) { @@ -4147,10 +4472,9 @@ int32_t iis2dulpx_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); - + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); fifo_reg.mlc_fifo_en = val; ret += iis2dulpx_write_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); } @@ -4174,10 +4498,10 @@ int32_t iis2dulpx_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2dulpx_mem_bank_set(ctx, IIS2DULPX_EMBED_FUNC_MEM_BANK); + ret += iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); if (ret == 0) { - ret = iis2dulpx_read_reg(ctx, IIS2DULPX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); *val = fifo_reg.mlc_fifo_en; } @@ -4190,5 +4514,3 @@ int32_t iis2dulpx_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis2dulpx_STdC/driver/iis2dulpx_reg.h b/sensor/stmemsc/iis2dulpx_STdC/driver/iis2dulpx_reg.h index 18790a5..daeec80 100644 --- a/sensor/stmemsc/iis2dulpx_STdC/driver/iis2dulpx_reg.h +++ b/sensor/stmemsc/iis2dulpx_STdC/driver/iis2dulpx_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -2115,7 +2117,6 @@ typedef struct uint8_t sw_reset : 1; /* Restoring configuration registers */ uint8_t boot : 1; /* Restoring calibration parameters */ uint8_t drdy : 1; /* Accelerometer data ready */ - uint8_t power_down : 1; /* Monitors power-down. */ } iis2dulpx_status_t; int32_t iis2dulpx_status_get(const stmdev_ctx_t *ctx, iis2dulpx_status_t *val); @@ -2194,7 +2195,6 @@ int32_t iis2dulpx_trigger_sw(const stmdev_ctx_t *ctx, const iis2dulpx_md_t *md); typedef struct { uint8_t drdy : 1; - uint8_t timestamp : 1; uint8_t free_fall : 1; uint8_t wake_up : 1; uint8_t wake_up_z : 1; @@ -2212,11 +2212,6 @@ typedef struct uint8_t six_d_zh : 1; uint8_t sleep_change : 1; uint8_t sleep_state : 1; - uint8_t tilt : 1; - uint8_t fifo_bdr : 1; - uint8_t fifo_full : 1; - uint8_t fifo_ovr : 1; - uint8_t fifo_th : 1; } iis2dulpx_all_sources_t; int32_t iis2dulpx_all_sources_get(const stmdev_ctx_t *ctx, iis2dulpx_all_sources_t *val); @@ -2437,18 +2432,26 @@ typedef struct iis2dulpx_operation_t operation; iis2dulpx_store_t store; uint8_t xl_only : 1; /* only XL samples (16-bit) are stored in FIFO */ - uint8_t watermark : 7; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ uint8_t cfg_change_in_fifo : 1; - iis2dulpx_fifo_event_t fifo_event : 1; /* 0: FIFO watermark, 1: FIFO full */ - struct - { - iis2dulpx_dec_ts_t dec_ts; /* decimation for timestamp batching*/ - iis2dulpx_bdr_xl_t bdr_xl; /* accelerometer batch data rate*/ - } batch; } iis2dulpx_fifo_mode_t; int32_t iis2dulpx_fifo_mode_set(const stmdev_ctx_t *ctx, iis2dulpx_fifo_mode_t val); int32_t iis2dulpx_fifo_mode_get(const stmdev_ctx_t *ctx, iis2dulpx_fifo_mode_t *val); +int32_t iis2dulpx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dulpx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + iis2dulpx_dec_ts_t dec_ts; /* decimation for timestamp batching*/ + iis2dulpx_bdr_xl_t bdr_xl; /* accelerometer batch data rate*/ +} iis2dulpx_fifo_batch_t; + +int32_t iis2dulpx_fifo_batch_set(const stmdev_ctx_t *ctx, iis2dulpx_fifo_batch_t val); +int32_t iis2dulpx_fifo_batch_get(const stmdev_ctx_t *ctx, iis2dulpx_fifo_batch_t *val); + +int32_t iis2dulpx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, iis2dulpx_fifo_event_t val); +int32_t iis2dulpx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, iis2dulpx_fifo_event_t *val); + int32_t iis2dulpx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); int32_t iis2dulpx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); @@ -2639,10 +2642,10 @@ typedef enum typedef enum { - IIS2DULPX_ODR_NO_CHANGE = 0, /* no odr change during inactivity state */ - IIS2DULPX_ODR_1_6_HZ = 1, /* set odr to 1.6Hz during inactivity state */ - IIS2DULPX_ODR_3_HZ = 1, /* set odr to 3Hz during inactivity state */ - IIS2DULPX_ODR_25_HZ = 1, /* set odr to 25Hz during inactivity state */ + IIS2DULPX_ODR_NO_CHANGE = 0x0, /* no odr change during inactivity state */ + IIS2DULPX_ODR_1_6_HZ = 0x1, /* set odr to 1.6Hz during inactivity state */ + IIS2DULPX_ODR_3_HZ = 0x2, /* set odr to 3Hz during inactivity state */ + IIS2DULPX_ODR_25_HZ = 0x3, /* set odr to 25Hz during inactivity state */ } iis2dulpx_inact_odr_t; typedef struct @@ -2784,5 +2787,3 @@ int32_t iis2dulpx_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* IIS2DULPX_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c index 8f664bc..a9abe53 100644 --- a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c +++ b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -178,6 +177,7 @@ int32_t iis2iclx_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } switch (ctrl1_xl.fs_xl) { @@ -493,10 +493,7 @@ int32_t iis2iclx_xl_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_odr_cfg_c, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); } if (ret == 0) @@ -529,6 +526,7 @@ int32_t iis2iclx_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } switch (ctrl1_xl.odr_xl) { @@ -611,6 +609,8 @@ int32_t iis2iclx_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + *val = ctrl3_c.bdu; return ret; @@ -658,6 +658,7 @@ int32_t iis2iclx_xl_offset_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } switch (ctrl6_c.usr_off_w) { @@ -722,29 +723,26 @@ int32_t iis2iclx_all_sources_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_STATUS, - (uint8_t *)&val->emb_func_status, 1); - } + if (ret == 0) + { + ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_STATUS, + (uint8_t *)&val->emb_func_status, 1); + } - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_STATUS_A, - (uint8_t *)&val->fsm_status_a, 1); - } + if (ret == 0) + { + ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_STATUS_A, + (uint8_t *)&val->fsm_status_a, 1); + } - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_STATUS_B, - (uint8_t *)&val->fsm_status_b, 1); - } + if (ret == 0) + { + ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_STATUS_B, + (uint8_t *)&val->fsm_status_b, 1); + } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); } return ret; @@ -784,6 +782,8 @@ int32_t iis2iclx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.xlda; return ret; @@ -805,13 +805,15 @@ int32_t iis2iclx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.tda; return ret; } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -830,7 +832,7 @@ int32_t iis2iclx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -849,7 +851,7 @@ int32_t iis2iclx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -868,7 +870,7 @@ int32_t iis2iclx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -924,6 +926,8 @@ int32_t iis2iclx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL7_XL, (uint8_t *)&ctrl7_xl, 1); + if (ret != 0) { return ret; } + *val = ctrl7_xl.usr_off_on_out; return ret; @@ -981,6 +985,8 @@ int32_t iis2iclx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) { return ret; } + *val = ctrl10_c.timestamp_en; return ret; @@ -1002,6 +1008,8 @@ int32_t iis2iclx_timestamp_raw_get(const stmdev_ctx_t *ctx, int32_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_TIMESTAMP0, buff, 4); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1024,7 +1032,7 @@ int32_t iis2iclx_timestamp_raw_get(const stmdev_ctx_t *ctx, int32_t *val) /** * @brief Temperature data output register (r). - * L and H registers together express a 16-bit word in two’s + * L and H registers together express a 16-bit word in two's * complement.[get] * * @param ctx Read / write interface definitions.(ptr) @@ -1038,6 +1046,8 @@ int32_t iis2iclx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_OUT_TEMP_L, buff, 2); + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1046,7 +1056,7 @@ int32_t iis2iclx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed as a - * 16-bit word in two’s complement.[get] + * 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read @@ -1059,6 +1069,8 @@ int32_t iis2iclx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_OUTX_L_A, buff, 4); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1134,6 +1146,8 @@ int32_t iis2iclx_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) { return ret; } + *val = ctrl9_xl.device_conf; return ret; @@ -1184,6 +1198,8 @@ int32_t iis2iclx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2iclx_read_reg(ctx, IIS2ICLX_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); + if (ret != 0) { return ret; } + *val = internal_freq_fine.freq_fine; return ret; @@ -1234,6 +1250,7 @@ int32_t iis2iclx_mem_bank_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) { return ret; } switch (func_cfg_access.reg_access) { @@ -1269,66 +1286,7 @@ int32_t iis2iclx_mem_bank_get(const stmdev_ctx_t *ctx, int32_t iis2iclx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { - iis2iclx_page_rw_t page_rw; - iis2iclx_page_sel_t page_sel; - iis2iclx_page_address_t page_address; - int32_t ret; - - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x02U; /* page_write enable */ - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add >> 8) & 0x0FU); - page_sel.not_used_01 = 1; - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add & 0xFFU); - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - - if (ret == 0) - { - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_VALUE, val, 1); - } - - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } - - return ret; + return iis2iclx_ln_pg_write(ctx, add, val, 1); } /** @@ -1353,91 +1311,67 @@ int32_t iis2iclx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, uint8_t i ; msb = (uint8_t)((add >> 8) & 0x0FU); lsb = (uint8_t)(add & 0xFFU); - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.page_rw = 0x02U; /* page_write enable*/ - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - page_address.page_addr = lsb; - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } + ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK); + if (ret != 0) { return ret; } + + /* set page write */ + ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x02U; /* page_write enable*/ + ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; // Default value + ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + + /* set page addr */ + page_address.page_addr = lsb; + ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { goto exit; } for (i = 0; i < len; i++) { - if (ret == 0) - { - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_VALUE, &buf[i], 1); + ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - /* Check if page wrap */ - if (lsb == 0x00U) - { - msb++; - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } + lsb++; - lsb++; - } + /* Check if page wrap */ + if (lsb == 0x00U) + { + msb++; + ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; // Default value + ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } } } - if (ret == 0) - { - page_sel.page_sel = 0; - page_sel.not_used_01 = 1; - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; // Default value + ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL, + (uint8_t *)&page_sel, 1); - if (ret == 0) - { - page_rw.page_rw = 0x00U; /* page_write disable */ - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } + /* unset page write */ + ret += iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x00U; /* page_write disable */ + ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } +exit: + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -1460,58 +1394,41 @@ int32_t iis2iclx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, int32_t ret; ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK); + if (ret != 0) { return ret; } + + /* set page read */ + ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x01U; /* page_read enable*/ + ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + page_sel.page_sel = (uint8_t)((add >> 8) & 0x0FU); + page_sel.not_used_01 = 1; // Default value + ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + + /* set page addr */ + page_address.page_addr = (uint8_t)(add & 0x00FFU); + ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { goto exit; } + + /* read value */ + ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_VALUE, val, 2); + if (ret != 0) { goto exit; } + + /* unset page read */ + ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x00U; /* page_read disable */ + ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x01U; /* page_read enable*/ - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add >> 8) & 0x0FU); - page_sel.not_used_01 = 1; - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add & 0x00FFU); - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_VALUE, val, 2); - } - - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x00U; /* page_read disable */ - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } +exit: + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -1561,6 +1478,7 @@ int32_t iis2iclx_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) { return ret; } switch (counter_bdr_reg1.dataready_pulsed) { @@ -1635,6 +1553,8 @@ int32_t iis2iclx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + *val = ctrl3_c.sw_reset; return ret; @@ -1680,6 +1600,8 @@ int32_t iis2iclx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + *val = ctrl3_c.if_inc; return ret; @@ -1723,6 +1645,8 @@ int32_t iis2iclx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + *val = ctrl3_c.boot; return ret; @@ -1770,6 +1694,7 @@ int32_t iis2iclx_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } switch (ctrl5_c.st_xl) { @@ -1845,6 +1770,8 @@ int32_t iis2iclx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + *val = ctrl1_xl.lpf2_xl_en; return ret; @@ -1892,6 +1819,8 @@ int32_t iis2iclx_filter_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { return ret; } + *val = ctrl4_c.drdy_mask; return ret; @@ -1942,6 +1871,7 @@ int32_t iis2iclx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { return ret; } switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) + @@ -2090,6 +2020,8 @@ int32_t iis2iclx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { return ret; } + *val = ctrl8_xl.fastsettl_mode_xl; return ret; @@ -2138,6 +2070,7 @@ int32_t iis2iclx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) { return ret; } switch (tap_cfg0.slope_fds) { @@ -2210,6 +2143,7 @@ int32_t iis2iclx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) { return ret; } switch (pin_ctrl.sdo_pu_en) { @@ -2267,6 +2201,7 @@ int32_t iis2iclx_spi_mode_get(const stmdev_ctx_t *ctx, iis2iclx_sim_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } switch (ctrl3_c.sim) { @@ -2326,6 +2261,7 @@ int32_t iis2iclx_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { return ret; } switch (ctrl4_c.i2c_disable) { @@ -2400,10 +2336,7 @@ int32_t iis2iclx_pin_int1_route_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int1_b, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); if (ret == 0) { @@ -2541,10 +2474,7 @@ int32_t iis2iclx_pin_int1_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int1_b, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); if (ret == 0) { @@ -2603,10 +2533,7 @@ int32_t iis2iclx_pin_int2_route_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int2_b, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); if (ret == 0) { @@ -2743,10 +2670,7 @@ int32_t iis2iclx_pin_int2_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int2_b, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); if (ret == 0) { @@ -2802,6 +2726,7 @@ int32_t iis2iclx_pin_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } switch (ctrl3_c.pp_od) { @@ -2861,6 +2786,7 @@ int32_t iis2iclx_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } switch (ctrl3_c.h_lactive) { @@ -2918,6 +2844,8 @@ int32_t iis2iclx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { return ret; } + *val = ctrl4_c.int2_on_int1; return ret; @@ -2951,22 +2879,19 @@ int32_t iis2iclx_int_notification_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); + } - if (ret == 0) - { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); + } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); } return ret; @@ -2993,18 +2918,17 @@ int32_t iis2iclx_int_notification_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1); + } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); } + if (ret != 0) { return ret; } + switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir) { case IIS2ICLX_ALL_INT_PULSED: @@ -3091,6 +3015,7 @@ int32_t iis2iclx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) { return ret; } switch (wake_up_dur.wake_ths_w) { @@ -3153,6 +3078,8 @@ int32_t iis2iclx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) { return ret; } + *val = wake_up_ths.wk_ths; return ret; @@ -3201,6 +3128,8 @@ int32_t iis2iclx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) { return ret; } + *val = wake_up_ths.usr_off_on_wu; return ret; @@ -3247,6 +3176,8 @@ int32_t iis2iclx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) { return ret; } + *val = wake_up_dur.wake_dur; return ret; @@ -3310,6 +3241,7 @@ int32_t iis2iclx_act_pin_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) { return ret; } switch (tap_cfg0. sleep_status_on_int) { @@ -3370,6 +3302,8 @@ int32_t iis2iclx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) { return ret; } + *val = wake_up_dur.sleep_dur; return ret; @@ -3429,6 +3363,8 @@ int32_t iis2iclx_tap_detection_on_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) { return ret; } + *val = tap_cfg0.tap_y_en; return ret; @@ -3475,6 +3411,8 @@ int32_t iis2iclx_tap_detection_on_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) { return ret; } + *val = tap_cfg0.tap_x_en; return ret; @@ -3519,6 +3457,8 @@ int32_t iis2iclx_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) { return ret; } + *val = tap_cfg1.tap_ths_x; return ret; @@ -3564,6 +3504,7 @@ int32_t iis2iclx_tap_axis_priority_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) { return ret; } switch (tap_cfg1.tap_priority) { @@ -3622,6 +3563,8 @@ int32_t iis2iclx_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + if (ret != 0) { return ret; } + *val = tap_cfg2.tap_ths_y; return ret; @@ -3674,6 +3617,8 @@ int32_t iis2iclx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1); + if (ret != 0) { return ret; } + *val = int_dur2.shock; return ret; @@ -3726,6 +3671,8 @@ int32_t iis2iclx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1); + if (ret != 0) { return ret; } + *val = int_dur2.quiet; return ret; @@ -3780,6 +3727,8 @@ int32_t iis2iclx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1); + if (ret != 0) { return ret; } + *val = int_dur2.dur; return ret; @@ -3828,6 +3777,7 @@ int32_t iis2iclx_tap_mode_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) { return ret; } switch (wake_up_ths.single_double_tap) { @@ -3910,12 +3860,11 @@ int32_t iis2iclx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL1, - (uint8_t *)&fifo_ctrl1, 1); - } + ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) { return ret; } *val = fifo_ctrl2.wtm; *val = *val << 8; @@ -3967,6 +3916,8 @@ int32_t iis2iclx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) { return ret; } + *val = fifo_ctrl2.odrchg_en; return ret; @@ -4015,6 +3966,8 @@ int32_t iis2iclx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) { return ret; } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -4065,6 +4018,7 @@ int32_t iis2iclx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl3.bdr_xl) { @@ -4155,6 +4109,7 @@ int32_t iis2iclx_fifo_mode_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl4.fifo_mode) { @@ -4235,6 +4190,7 @@ int32_t iis2iclx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl4.odr_t_batch) { @@ -4310,6 +4266,7 @@ int32_t iis2iclx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl4.odr_ts_batch) { @@ -4381,6 +4338,8 @@ int32_t iis2iclx_rst_batch_counter_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) { return ret; } + *val = counter_bdr_reg1.rst_counter_bdr; return ret; @@ -4440,12 +4399,11 @@ int32_t iis2iclx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); - } + ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + if (ret != 0) { return ret; } *val = counter_bdr_reg1.cnt_bdr_th; *val = *val << 8; @@ -4470,15 +4428,15 @@ int32_t iis2iclx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); - *val = fifo_status2.diff_fifo; - *val = *val << 8; - *val += fifo_status1.diff_fifo; - } + ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + if (ret != 0) { return ret; } + + *val = fifo_status2.diff_fifo; + *val = *val << 8; + *val += fifo_status1.diff_fifo; return ret; } @@ -4516,6 +4474,8 @@ int32_t iis2iclx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); + if (ret != 0) { return ret; } + *val = fifo_status2.fifo_full_ia; return ret; @@ -4537,6 +4497,8 @@ int32_t iis2iclx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); + if (ret != 0) { return ret; } + *val = fifo_status2. fifo_ovr_ia; return ret; @@ -4557,6 +4519,8 @@ int32_t iis2iclx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); + if (ret != 0) { return ret; } + *val = fifo_status2.fifo_wtm_ia; return ret; @@ -4578,6 +4542,7 @@ int32_t iis2iclx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_data_out_tag, 1); + if (ret != 0) { return ret; } switch (fifo_data_out_tag.tag_sensor) { @@ -4653,10 +4618,7 @@ int32_t iis2iclx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -4686,9 +4648,10 @@ int32_t iis2iclx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = slv0_config. batch_ext_sens_0_en; - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + return ret; } @@ -4721,10 +4684,7 @@ int32_t iis2iclx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -4752,10 +4712,7 @@ int32_t iis2iclx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) *val = slv1_config. batch_ext_sens_1_en; } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -4789,10 +4746,7 @@ int32_t iis2iclx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -4822,9 +4776,10 @@ int32_t iis2iclx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = slv2_config. batch_ext_sens_2_en; - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + return ret; } @@ -4857,10 +4812,7 @@ int32_t iis2iclx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -4885,14 +4837,14 @@ int32_t iis2iclx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); - *val = slv3_config. batch_ext_sens_3_en; } - if (ret == 0) { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + *val = slv3_config. batch_ext_sens_3_en; } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + return ret; } @@ -4963,11 +4915,9 @@ int32_t iis2iclx_den_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + ret += iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - } + if (ret != 0) { return ret; } switch ((ctrl9_xl.den_en << 4) + ctrl6_c.den_mode) { @@ -5040,6 +4990,7 @@ int32_t iis2iclx_den_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) { return ret; } switch (ctrl9_xl.den_lh) { @@ -5098,6 +5049,8 @@ int32_t iis2iclx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_y; return ret; @@ -5141,6 +5094,8 @@ int32_t iis2iclx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_x; return ret; @@ -5182,10 +5137,11 @@ int32_t iis2iclx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_status, 1); } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + if (ret == 0) { *val = emb_func_status.is_fsm_lc; - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); } return ret; @@ -5219,10 +5175,7 @@ int32_t iis2iclx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -5251,14 +5204,9 @@ int32_t iis2iclx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_en_b.fsm_en; - ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -5331,10 +5279,7 @@ int32_t iis2iclx_fsm_enable_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -5366,10 +5311,7 @@ int32_t iis2iclx_fsm_enable_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_enable_b, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -5397,10 +5339,7 @@ int32_t iis2iclx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_LONG_COUNTER_L, buff, 2); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -5424,15 +5363,15 @@ int32_t iis2iclx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_LONG_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; } - if (ret == 0) { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + return ret; } @@ -5466,10 +5405,7 @@ int32_t iis2iclx_long_clr_set(const stmdev_ctx_t *ctx, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -5496,10 +5432,9 @@ int32_t iis2iclx_long_clr_get(const stmdev_ctx_t *ctx, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + + if (ret != 0) { return ret; } switch (fsm_long_counter_clear.fsm_lc_clr) { @@ -5544,10 +5479,7 @@ int32_t iis2iclx_fsm_out_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_outs1, 16); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -5583,10 +5515,7 @@ int32_t iis2iclx_fsm_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -5613,10 +5542,9 @@ int32_t iis2iclx_fsm_data_rate_get(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + + if (ret != 0) { return ret; } switch (emb_func_odr_cfg_b.fsm_odr) { @@ -5672,10 +5600,7 @@ int32_t iis2iclx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_init_b, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -5704,9 +5629,10 @@ int32_t iis2iclx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_init_b.fsm_init; - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + return ret; } @@ -5765,8 +5691,12 @@ int32_t iis2iclx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, { ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -5865,8 +5795,12 @@ int32_t iis2iclx_fsm_start_address_get(const stmdev_ctx_t *ctx, { ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_START_ADD_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -5925,10 +5859,7 @@ int32_t iis2iclx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) } } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -5955,10 +5886,11 @@ int32_t iis2iclx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); *val = reg.mlc_en; } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + return ret; } @@ -6005,10 +5937,7 @@ int32_t iis2iclx_mlc_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6035,6 +5964,8 @@ int32_t iis2iclx_mlc_data_rate_get(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + if (ret == 0) { switch (reg.mlc_odr) @@ -6059,8 +5990,6 @@ int32_t iis2iclx_mlc_data_rate_get(const stmdev_ctx_t *ctx, *val = IIS2ICLX_ODR_PRGS_12Hz5; break; } - - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); } return ret; @@ -6084,10 +6013,7 @@ int32_t iis2iclx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) ret = iis2iclx_read_reg(ctx, IIS2ICLX_MLC0_SRC, buff, 8); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6132,10 +6058,7 @@ int32_t iis2iclx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_SENSOR_HUB_1, (uint8_t *)val, len); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); exit: return ret; @@ -6170,10 +6093,7 @@ int32_t iis2iclx_sh_slave_connected_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6200,10 +6120,9 @@ int32_t iis2iclx_sh_slave_connected_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + + if (ret != 0) { return ret; } switch (master_config.aux_sens_on) { @@ -6259,10 +6178,7 @@ int32_t iis2iclx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6291,9 +6207,10 @@ int32_t iis2iclx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = master_config.master_on; - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + return ret; } @@ -6326,10 +6243,7 @@ int32_t iis2iclx_sh_pin_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6356,10 +6270,9 @@ int32_t iis2iclx_sh_pin_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + + if (ret != 0) { return ret; } switch (master_config.shub_pu_en) { @@ -6407,10 +6320,7 @@ int32_t iis2iclx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6439,9 +6349,10 @@ int32_t iis2iclx_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = master_config.pass_through_mode; - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + return ret; } @@ -6474,10 +6385,7 @@ int32_t iis2iclx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6504,10 +6412,9 @@ int32_t iis2iclx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + + if (ret != 0) { return ret; } switch (master_config.start_config) { @@ -6557,10 +6464,7 @@ int32_t iis2iclx_sh_write_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6588,10 +6492,9 @@ int32_t iis2iclx_sh_write_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + + if (ret != 0) { return ret; } switch (master_config.write_once) { @@ -6645,10 +6548,7 @@ int32_t iis2iclx_sh_reset_set(const stmdev_ctx_t *ctx) (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6672,14 +6572,15 @@ int32_t iis2iclx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG, (uint8_t *)&master_config, 1); - *val = master_config.rst_master_regs; } if (ret == 0) { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + *val = master_config.rst_master_regs; } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + return ret; } @@ -6712,10 +6613,7 @@ int32_t iis2iclx_sh_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6742,10 +6640,9 @@ int32_t iis2iclx_sh_data_rate_get(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); + + if (ret != 0) { return ret; } switch (slv0_config.shub_odr) { @@ -6812,10 +6709,7 @@ int32_t iis2iclx_sh_cfg_write(const stmdev_ctx_t *ctx, (uint8_t *) & (val->slv0_data), 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6868,10 +6762,7 @@ int32_t iis2iclx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6922,10 +6813,7 @@ int32_t iis2iclx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -6977,10 +6865,7 @@ int32_t iis2iclx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -7032,10 +6917,7 @@ int32_t iis2iclx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -7060,10 +6942,7 @@ int32_t iis2iclx_sh_status_get(const stmdev_ctx_t *ctx, ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_MASTER, (uint8_t *)val, 1); } - if (ret == 0) - { - ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); - } + ret += iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); return ret; } @@ -7117,11 +6996,9 @@ int32_t iis2iclx_bus_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + ret += iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - if (ret == 0) - { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - } + if (ret != 0) { return ret; } switch ((ctrl3_c.sim << 1) | ctrl4_c.i2c_disable) { @@ -7154,5 +7031,3 @@ int32_t iis2iclx_bus_mode_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h index 81f167f..6297846 100644 --- a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h +++ b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -3265,5 +3267,3 @@ int32_t iis2iclx_bus_mode_get(const stmdev_ctx_t *ctx, #endif #endif /* IIS2ICLX_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c index 18b2038..eea0b2c 100644 --- a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c +++ b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -170,6 +169,8 @@ int32_t iis2mdc_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_OFFSET_X_REG_L, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -220,6 +221,7 @@ int32_t iis2mdc_operating_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.md) { @@ -281,6 +283,7 @@ int32_t iis2mdc_data_rate_get(const stmdev_ctx_t *ctx, iis2mdc_odr_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.odr) { @@ -346,6 +349,7 @@ int32_t iis2mdc_power_mode_get(const stmdev_ctx_t *ctx, iis2mdc_lp_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.lp) { @@ -403,6 +407,8 @@ int32_t iis2mdc_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.comp_temp_en; return ret; @@ -448,6 +454,7 @@ int32_t iis2mdc_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.lpf) { @@ -508,6 +515,7 @@ int32_t iis2mdc_set_rst_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.set_rst) { @@ -578,6 +586,8 @@ int32_t iis2mdc_off_canc_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.off_canc_one_shot; return ret; @@ -621,6 +631,8 @@ int32_t iis2mdc_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.bdu; return ret; @@ -640,6 +652,8 @@ int32_t iis2mdc_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_STATUS_REG, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.zyxda; return ret; @@ -659,6 +673,8 @@ int32_t iis2mdc_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_STATUS_REG, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.zyxor; return ret; @@ -678,6 +694,8 @@ int32_t iis2mdc_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_OUTX_L_REG, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -702,6 +720,8 @@ int32_t iis2mdc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_TEMP_OUT_L_REG, buff, 2); + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -776,6 +796,8 @@ int32_t iis2mdc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.soft_rst; return ret; @@ -819,6 +841,8 @@ int32_t iis2mdc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_A, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.reboot; return ret; @@ -862,6 +886,8 @@ int32_t iis2mdc_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.self_test; return ret; @@ -905,6 +931,7 @@ int32_t iis2mdc_data_format_get(const stmdev_ctx_t *ctx, iis2mdc_ble_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.ble) { @@ -999,6 +1026,7 @@ int32_t iis2mdc_offset_int_conf_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_B, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.int_on_dataoff) { @@ -1056,6 +1084,8 @@ int32_t iis2mdc_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.drdy_on_pin; return ret; @@ -1099,6 +1129,8 @@ int32_t iis2mdc_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + *val = reg.int_on_pin; return ret; @@ -1196,6 +1228,8 @@ int32_t iis2mdc_int_gen_threshold_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_INT_THS_L_REG, buff, 2); + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1255,6 +1289,7 @@ int32_t iis2mdc_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis2mdc_read_reg(ctx, IIS2MDC_CFG_REG_C, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.i2c_dis) { @@ -1278,5 +1313,3 @@ int32_t iis2mdc_i2c_interface_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h index 930b441..0302a6d 100644 --- a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h +++ b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -465,5 +467,3 @@ int32_t iis2mdc_i2c_interface_get(const stmdev_ctx_t *ctx, #endif #endif /* IIS2MDC_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c index 006d268..f49ea98 100644 --- a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c +++ b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -163,6 +162,8 @@ int32_t iis328dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.xen; return ret; @@ -209,6 +210,8 @@ int32_t iis328dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.yen; return ret; @@ -255,6 +258,8 @@ int32_t iis328dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.zen; return ret; @@ -302,6 +307,7 @@ int32_t iis328dq_data_rate_get(const stmdev_ctx_t *ctx, iis328dq_dr_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm) { @@ -396,6 +402,7 @@ int32_t iis328dq_reference_mode_get(const stmdev_ctx_t *ctx, ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpm) { @@ -456,6 +463,7 @@ int32_t iis328dq_full_scale_get(const stmdev_ctx_t *ctx, iis328dq_fs_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.fs) { @@ -521,6 +529,8 @@ int32_t iis328dq_block_data_update_get(const stmdev_ctx_t *ctx, ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg4.bdu; return ret; @@ -559,6 +569,8 @@ int32_t iis328dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -578,7 +590,7 @@ int32_t iis328dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) /** * @brief Linear acceleration output register. The value is expressed - * as a 16-bit word in two’s complement.[get] + * as a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions(ptr) * @param buff buffer that stores data read @@ -591,6 +603,8 @@ int32_t iis328dq_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis328dq_read_reg(ctx, IIS328DQ_OUT_X_L, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -671,6 +685,8 @@ int32_t iis328dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg2.boot; return ret; @@ -717,6 +733,7 @@ int32_t iis328dq_self_test_get(const stmdev_ctx_t *ctx, iis328dq_st_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.st) { @@ -783,6 +800,7 @@ int32_t iis328dq_data_format_get(const stmdev_ctx_t *ctx, ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.ble) { @@ -858,6 +876,7 @@ int32_t iis328dq_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2.hpcf) { @@ -927,6 +946,7 @@ int32_t iis328dq_hp_path_get(const stmdev_ctx_t *ctx, iis328dq_hpen_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen) { @@ -1083,6 +1103,7 @@ int32_t iis328dq_spi_mode_get(const stmdev_ctx_t *ctx, iis328dq_sim_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.sim) { @@ -1158,6 +1179,7 @@ int32_t iis328dq_pin_int1_route_get(const stmdev_ctx_t *ctx, ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.i1_cfg) { @@ -1230,6 +1252,7 @@ int32_t iis328dq_int1_notification_get(const stmdev_ctx_t *ctx, ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.lir1) { @@ -1292,6 +1315,7 @@ int32_t iis328dq_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.i2_cfg) { @@ -1364,6 +1388,7 @@ int32_t iis328dq_int2_notification_get(const stmdev_ctx_t *ctx, ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.lir2) { @@ -1425,6 +1450,7 @@ int32_t iis328dq_pin_mode_get(const stmdev_ctx_t *ctx, ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.pp_od) { @@ -1487,6 +1513,7 @@ int32_t iis328dq_pin_polarity_get(const stmdev_ctx_t *ctx, ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3.ihl) { @@ -1565,6 +1592,8 @@ int32_t iis328dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } + val->int1_xlie = int1_cfg.xlie; val->int1_xhie = int1_cfg.xhie; val->int1_ylie = int1_cfg.ylie; @@ -1616,6 +1645,7 @@ int32_t iis328dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } switch (int1_cfg.aoi) { @@ -1692,6 +1722,8 @@ int32_t iis328dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1); + if (ret != 0) { return ret; } + *val = int1_ths.ths; return ret; @@ -1738,6 +1770,8 @@ int32_t iis328dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_DURATION, (uint8_t *)&int1_duration, 1); + if (ret != 0) { return ret; } + *val = int1_duration.d; return ret; @@ -1790,6 +1824,8 @@ int32_t iis328dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } + val->int2_xlie = int2_cfg.xlie; val->int2_xhie = int2_cfg.xhie; val->int2_ylie = int2_cfg.ylie; @@ -1841,6 +1877,7 @@ int32_t iis328dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } switch (int2_cfg.aoi) { @@ -1917,6 +1954,8 @@ int32_t iis328dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1); + if (ret != 0) { return ret; } + *val = int2_ths.ths; return ret; @@ -1963,6 +2002,8 @@ int32_t iis328dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_DURATION, (uint8_t *)&int2_duration, 1); + if (ret != 0) { return ret; } + *val = int2_duration.d; return ret; @@ -2022,6 +2063,8 @@ int32_t iis328dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg5.turnon; return ret; @@ -2081,6 +2124,7 @@ int32_t iis328dq_int1_6d_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } switch ((int1_cfg.aoi << 1) + int1_cfg._6d) { @@ -2160,6 +2204,8 @@ int32_t iis328dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1); + if (ret != 0) { return ret; } + *val = int1_ths.ths; return ret; @@ -2207,6 +2253,7 @@ int32_t iis328dq_int2_6d_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } switch ((int2_cfg.aoi << 1) + int2_cfg._6d) { @@ -2287,6 +2334,8 @@ int32_t iis328dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1); + if (ret != 0) { return ret; } + *val = int2_ths.ths; return ret; @@ -2296,5 +2345,3 @@ int32_t iis328dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h index 4a4645d..c50cd76 100644 --- a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h +++ b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -808,5 +810,3 @@ int32_t iis328dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, #endif #endif /* IIS328DQ_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c index c1937f6..bfa063c 100644 --- a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c +++ b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -159,6 +158,8 @@ int32_t iis3dhhc_block_data_update_get(const stmdev_ctx_t *ctx, ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.bdu; return ret; @@ -207,6 +208,7 @@ int32_t iis3dhhc_data_rate_get(const stmdev_ctx_t *ctx, ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } switch (ctrl_reg1.norm_mod_en) { @@ -267,6 +269,8 @@ int32_t iis3dhhc_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg4.off_tcomp_en; return ret; @@ -286,6 +290,8 @@ int32_t iis3dhhc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis3dhhc_read_reg(ctx, IIS3DHHC_OUT_TEMP_L, buff, 2); + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -306,6 +312,8 @@ int32_t iis3dhhc_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = iis3dhhc_read_reg(ctx, IIS3DHHC_OUT_X_L_XL, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -330,6 +338,8 @@ int32_t iis3dhhc_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis3dhhc_read_reg(ctx, IIS3DHHC_STATUS, (uint8_t *)&status, 1); + if (ret != 0) { return ret; } + *val = status.zyxda; return ret; @@ -349,6 +359,8 @@ int32_t iis3dhhc_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis3dhhc_read_reg(ctx, IIS3DHHC_STATUS, (uint8_t *)&status, 1); + if (ret != 0) { return ret; } + *val = status.zyxor; return ret; @@ -424,6 +436,8 @@ int32_t iis3dhhc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.sw_reset; return ret; @@ -470,6 +484,8 @@ int32_t iis3dhhc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.boot; return ret; @@ -516,6 +532,7 @@ int32_t iis3dhhc_self_test_get(const stmdev_ctx_t *ctx, iis3dhhc_st_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.st) { @@ -582,6 +599,7 @@ int32_t iis3dhhc_filter_config_get(const stmdev_ctx_t *ctx, ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.dsp) { @@ -681,6 +699,7 @@ int32_t iis3dhhc_drdy_notification_mode_get(const stmdev_ctx_t *ctx, ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } switch (ctrl_reg1.drdy_pulse) { @@ -745,6 +764,7 @@ int32_t iis3dhhc_int1_mode_get(const stmdev_ctx_t *ctx, ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) { return ret; } switch (int1_ctrl.int1_ext) { @@ -807,6 +827,8 @@ int32_t iis3dhhc_fifo_threshold_on_int1_get(const stmdev_ctx_t *ctx, ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) { return ret; } + *val = int1_ctrl.int1_fth; return ret; @@ -854,6 +876,8 @@ int32_t iis3dhhc_fifo_full_on_int1_get(const stmdev_ctx_t *ctx, ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) { return ret; } + *val = int1_ctrl.int1_fss5; return ret; @@ -900,6 +924,8 @@ int32_t iis3dhhc_fifo_ovr_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) { return ret; } + *val = int1_ctrl.int1_ovr; return ret; @@ -946,6 +972,8 @@ int32_t iis3dhhc_boot_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) { return ret; } + *val = int1_ctrl.int1_boot; return ret; @@ -992,6 +1020,8 @@ int32_t iis3dhhc_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) { return ret; } + *val = int1_ctrl.int1_drdy; return ret; @@ -1040,6 +1070,8 @@ int32_t iis3dhhc_fifo_threshold_on_int2_get(const stmdev_ctx_t *ctx, ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) { return ret; } + *val = int2_ctrl.int2_fth; return ret; @@ -1087,6 +1119,8 @@ int32_t iis3dhhc_fifo_full_on_int2_get(const stmdev_ctx_t *ctx, ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) { return ret; } + *val = int2_ctrl.int2_fss5; return ret; @@ -1133,6 +1167,8 @@ int32_t iis3dhhc_fifo_ovr_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) { return ret; } + *val = int2_ctrl.int2_ovr; return ret; @@ -1179,6 +1215,8 @@ int32_t iis3dhhc_boot_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) { return ret; } + *val = int2_ctrl.int2_boot; return ret; @@ -1225,6 +1263,8 @@ int32_t iis3dhhc_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) { return ret; } + *val = int2_ctrl.int2_drdy; return ret; @@ -1272,6 +1312,7 @@ int32_t iis3dhhc_pin_mode_get(const stmdev_ctx_t *ctx, ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch (ctrl_reg4.pp_od) { @@ -1353,6 +1394,8 @@ int32_t iis3dhhc_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg4.fifo_en; return ret; @@ -1406,6 +1449,8 @@ int32_t iis3dhhc_fifo_block_spi_hs_get(const stmdev_ctx_t *ctx, ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg5.fifo_spi_hs_on; return ret; @@ -1452,6 +1497,8 @@ int32_t iis3dhhc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret != 0) { return ret; } + *val = fifo_ctrl.fth; return ret; @@ -1500,6 +1547,7 @@ int32_t iis3dhhc_fifo_mode_get(const stmdev_ctx_t *ctx, ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl.fmode) { @@ -1563,6 +1611,8 @@ int32_t iis3dhhc_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t *)&fifo_src, 1); + if (ret != 0) { return ret; } + *val = fifo_src.fss; return ret; @@ -1582,6 +1632,8 @@ int32_t iis3dhhc_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t *)&fifo_src, 1); + if (ret != 0) { return ret; } + *val = fifo_src.ovrn; return ret; @@ -1601,6 +1653,8 @@ int32_t iis3dhhc_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = iis3dhhc_read_reg(ctx, IIS3DHHC_FIFO_SRC, (uint8_t *)&fifo_src, 1); + if (ret != 0) { return ret; } + *val = fifo_src.fth; return ret; @@ -1662,6 +1716,8 @@ int32_t iis3dhhc_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = iis3dhhc_read_reg(ctx, IIS3DHHC_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + *val = ctrl_reg1.if_add_inc; return ret; @@ -1676,5 +1732,3 @@ int32_t iis3dhhc_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h index 8219a5e..f4ef317 100644 --- a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h +++ b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -573,5 +575,3 @@ int32_t iis3dhhc_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* IIS3DHHC_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c index a56aa68..a2cfe86 100644 --- a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c +++ b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -189,6 +188,7 @@ int32_t iis3dwb_xl_full_scale_get(const stmdev_ctx_t *ctx, iis3dwb_ctrl1_xl_t ctrl1_xl; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } switch (ctrl1_xl.fs_xl) { @@ -255,6 +255,7 @@ int32_t iis3dwb_xl_data_rate_get(const stmdev_ctx_t *ctx, iis3dwb_ctrl1_xl_t ctrl1_xl; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } switch (ctrl1_xl.xl_en) { @@ -310,6 +311,8 @@ int32_t iis3dwb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) iis3dwb_ctrl3_c_t ctrl3_c; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + *val = ctrl3_c.bdu; return ret; @@ -355,6 +358,7 @@ int32_t iis3dwb_xl_offset_weight_get(const stmdev_ctx_t *ctx, iis3dwb_ctrl6_c_t ctrl6_c; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } switch (ctrl6_c.usr_off_w) { @@ -533,6 +537,8 @@ int32_t iis3dwb_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.xlda; return ret; @@ -553,6 +559,8 @@ int32_t iis3dwb_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.tda; return ret; @@ -596,13 +604,15 @@ int32_t iis3dwb_usr_offset_block_get(const stmdev_ctx_t *ctx, uint8_t *val) iis3dwb_ctrl7_c_t ctrl7_c; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL7_C, (uint8_t *)&ctrl7_c, 1); + if (ret != 0) { return ret; } + *val = ctrl7_c.usr_off_on_out; return ret; } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -619,7 +629,7 @@ int32_t iis3dwb_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -636,7 +646,7 @@ int32_t iis3dwb_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -653,7 +663,7 @@ int32_t iis3dwb_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -670,7 +680,7 @@ int32_t iis3dwb_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -687,7 +697,7 @@ int32_t iis3dwb_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -766,6 +776,8 @@ int32_t iis3dwb_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) iis3dwb_ctrl10_c_t ctrl10_c; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) { return ret; } + *val = ctrl10_c.timestamp_en; return ret; @@ -786,6 +798,8 @@ int32_t iis3dwb_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) uint8_t buff[4]; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_TIMESTAMP0, buff, 4); + if (ret != 0) { return ret; } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -844,6 +858,7 @@ int32_t iis3dwb_rounding_mode_get(const stmdev_ctx_t *ctx, iis3dwb_ctrl5_c_t ctrl5_c; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } switch (ctrl5_c.rounding) { @@ -865,7 +880,7 @@ int32_t iis3dwb_rounding_mode_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). - * L and H registers together express a 16-bit word in two’s + * L and H registers together express a 16-bit word in two's * complement.[get] * * @param ctx Read / write interface definitions.(ptr) @@ -878,6 +893,8 @@ int32_t iis3dwb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[2]; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_OUT_TEMP_L, buff, 2); + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -886,7 +903,7 @@ int32_t iis3dwb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed as a - * 16-bit word in two’s complement.[get] + * 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param val Buffer that stores data read @@ -898,6 +915,8 @@ int32_t iis3dwb_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[6]; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_OUTX_L_A, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -959,6 +978,7 @@ int32_t iis3dwb_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_data_out_tag, 1); + if (ret != 0) { return ret; } switch (fifo_data_out_tag.tag_sensor) { @@ -1037,6 +1057,8 @@ int32_t iis3dwb_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); + if (ret != 0) { return ret; } + *val = internal_freq_fine.freq_fine; return ret; @@ -1085,6 +1107,7 @@ int32_t iis3dwb_data_ready_mode_get(const stmdev_ctx_t *ctx, const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) { return ret; } switch (counter_bdr_reg1.dataready_pulsed) { @@ -1155,6 +1178,8 @@ int32_t iis3dwb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) iis3dwb_ctrl3_c_t ctrl3_c; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + *val = ctrl3_c.sw_reset; return ret; @@ -1198,6 +1223,8 @@ int32_t iis3dwb_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) iis3dwb_ctrl3_c_t ctrl3_c; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + *val = ctrl3_c.if_inc; return ret; @@ -1239,6 +1266,8 @@ int32_t iis3dwb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) iis3dwb_ctrl3_c_t ctrl3_c; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + *val = ctrl3_c.boot; return ret; @@ -1284,6 +1313,7 @@ int32_t iis3dwb_xl_self_test_get(const stmdev_ctx_t *ctx, iis3dwb_ctrl5_c_t ctrl5_c; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } switch (ctrl5_c.st_xl) { @@ -1361,6 +1391,8 @@ int32_t iis3dwb_filter_settling_mask_get(const stmdev_ctx_t *ctx, { iis3dwb_ctrl4_c_t ctrl4_c; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { return ret; } + *val = ctrl4_c.drdy_mask; return ret; @@ -1546,6 +1578,8 @@ int32_t iis3dwb_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) iis3dwb_ctrl8_xl_t ctrl8_xl; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { return ret; } + *val = ctrl8_xl.fastsettl_mode_xl; return ret; @@ -1592,6 +1626,7 @@ int32_t iis3dwb_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, iis3dwb_slope_en_t int_cfg0; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&int_cfg0, 1); + if (ret != 0) { return ret; } switch (int_cfg0.slope_fds) { @@ -1662,6 +1697,7 @@ int32_t iis3dwb_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, iis3dwb_pin_ctrl_t pin_ctrl; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) { return ret; } switch (pin_ctrl.sdo_pu_en) { @@ -1717,6 +1753,7 @@ int32_t iis3dwb_spi_mode_get(const stmdev_ctx_t *ctx, iis3dwb_sim_t *val) iis3dwb_ctrl3_c_t ctrl3_c; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } switch (ctrl3_c.sim) { @@ -1774,6 +1811,7 @@ int32_t iis3dwb_i2c_interface_get(const stmdev_ctx_t *ctx, iis3dwb_ctrl4_c_t ctrl4_c; const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { return ret; } switch (ctrl4_c.i2c_disable) { @@ -2030,6 +2068,7 @@ int32_t iis3dwb_pin_mode_get(const stmdev_ctx_t *ctx, iis3dwb_pp_od_t *val) iis3dwb_ctrl3_c_t ctrl3_c; int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } switch (ctrl3_c.pp_od) { @@ -2087,6 +2126,7 @@ int32_t iis3dwb_pin_polarity_get(const stmdev_ctx_t *ctx, iis3dwb_ctrl3_c_t ctrl3_c; int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } switch (ctrl3_c.h_lactive) { @@ -2142,6 +2182,8 @@ int32_t iis3dwb_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) iis3dwb_ctrl4_c_t ctrl4_c; int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { return ret; } + *val = ctrl4_c.int2_on_int1; return ret; @@ -2185,6 +2227,7 @@ int32_t iis3dwb_int_notification_get(const stmdev_ctx_t *ctx, iis3dwb_slope_en_t slope_en; int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_SLOPE_EN, (uint8_t *)&slope_en, 1); + if (ret != 0) { return ret; } switch (slope_en.lir) { @@ -2262,6 +2305,7 @@ int32_t iis3dwb_wkup_ths_weight_get(const stmdev_ctx_t *ctx, int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) { return ret; } switch (wake_up_dur.wake_ths_w) { @@ -2337,6 +2381,8 @@ int32_t iis3dwb_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) { return ret; } + *val = wake_up_ths.wk_ths; return ret; @@ -2383,6 +2429,8 @@ int32_t iis3dwb_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) { return ret; } + *val = wake_up_ths.usr_off_on_wu; return ret; @@ -2427,6 +2475,8 @@ int32_t iis3dwb_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) { return ret; } + *val = wake_up_dur.wake_dur; return ret; @@ -2484,6 +2534,8 @@ int32_t iis3dwb_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) { return ret; } + *val = wake_up_dur.sleep_dur; return ret; @@ -2556,6 +2608,7 @@ int32_t iis3dwb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) { return ret; } *val = fifo_ctrl2.wtm; *val = *val << 8; @@ -2605,6 +2658,8 @@ int32_t iis3dwb_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) { return ret; } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -2653,6 +2708,7 @@ int32_t iis3dwb_fifo_xl_batch_get(const stmdev_ctx_t *ctx, int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl3.bdr_xl) { @@ -2713,6 +2769,7 @@ int32_t iis3dwb_fifo_mode_get(const stmdev_ctx_t *ctx, int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl4.fifo_mode) { @@ -2791,6 +2848,7 @@ int32_t iis3dwb_fifo_temp_batch_get(const stmdev_ctx_t *ctx, int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl4.odr_t_batch) { @@ -2856,6 +2914,7 @@ int32_t iis3dwb_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } switch (fifo_ctrl4.odr_ts_batch) { @@ -2924,6 +2983,8 @@ int32_t iis3dwb_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) { return ret; } + *val = counter_bdr_reg1.rst_counter_bdr; return ret; @@ -3011,15 +3072,15 @@ int32_t iis3dwb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); - *val = fifo_status2.diff_fifo; - *val = *val << 8; - *val += fifo_status1.diff_fifo; - } + ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + if (ret != 0) { return ret; } + + *val = fifo_status2.diff_fifo; + *val = *val << 8; + *val += fifo_status1.diff_fifo; return ret; } @@ -3056,5 +3117,3 @@ int32_t iis3dwb_fifo_status_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h index f46bf04..1f1f4f3 100644 --- a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h +++ b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1168,5 +1170,3 @@ int32_t iis3dwb_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, #endif #endif /* IIS3DWB_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.c b/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.c index cb68aae..6ae06e9 100644 --- a/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.c +++ b/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.c @@ -6,18 +6,18 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ #include "ilps22qs_reg.h" +#include /** * @defgroup ILPS22QS @@ -224,6 +224,10 @@ int32_t ilps22qs_bus_mode_get(const stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) { ret = ilps22qs_read_reg(ctx, ILPS22QS_I3C_IF_CTRL, (uint8_t *)&i3c_if_ctrl, 1); + if (ret != 0) + { + return ret; + } switch (if_ctrl.i2c_i3c_dis << 1) { @@ -399,6 +403,10 @@ int32_t ilps22qs_status_get(const stmdev_ctx_t *ctx, ilps22qs_stat_t *val) ret = ilps22qs_read_reg(ctx, ILPS22QS_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); } + if (ret != 0) + { + return ret; + } val->sw_reset = ctrl_reg2.swreset; val->boot = int_source.boot_on; val->drdy_pres = status.p_da; @@ -451,6 +459,10 @@ int32_t ilps22qs_pin_conf_get(const stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val) ret = ilps22qs_read_reg(ctx, ILPS22QS_IF_CTRL, (uint8_t *)&if_ctrl, 1); + if (ret != 0) + { + return ret; + } val->sda_pull_up = if_ctrl.sda_pu_en; val->cs_pull_up = ~if_ctrl.cs_pu_dis; @@ -485,6 +497,10 @@ int32_t ilps22qs_all_sources_get(const stmdev_ctx_t *ctx, (uint8_t *)&fifo_status2, 1); } + if (ret != 0) + { + return ret; + } val->drdy_pres = status.p_da; val->drdy_temp = status.t_da; val->over_pres = int_source.ph; @@ -762,6 +778,11 @@ int32_t ilps22qs_ah_qvar_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ilps22qs_read_reg(ctx, ILPS22QS_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl_reg3.ah_qvar_en; return ret; @@ -783,6 +804,10 @@ int32_t ilps22qs_data_get(const stmdev_ctx_t *ctx, ilps22qs_md_t *md, int32_t ret; ret = ilps22qs_read_reg(ctx, ILPS22QS_PRESS_OUT_XL, buff, 5); + if (ret != 0) + { + return ret; + } /* pressure conversion */ data->pressure.raw = (int32_t)buff[2]; @@ -856,6 +881,11 @@ int32_t ilps22qs_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) uint8_t reg[3]; ret = ilps22qs_read_reg(ctx, ILPS22QS_PRESS_OUT_XL, reg, 3); + if (ret != 0) + { + return ret; + } + *buff = reg[2]; *buff = (*buff * 256U) + reg[1]; *buff = (*buff * 256U) + reg[0]; @@ -878,6 +908,11 @@ int32_t ilps22qs_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) uint8_t reg[2]; ret = ilps22qs_read_reg(ctx, ILPS22QS_TEMP_OUT_L, reg, 2); + if (ret != 0) + { + return ret; + } + *buff = (int16_t)reg[1]; *buff = (*buff * 256) + (int16_t)reg[0]; @@ -900,6 +935,10 @@ int32_t ilps22qs_ah_qvar_data_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ilps22qs_read_reg(ctx, ILPS22QS_PRESS_OUT_XL, buff, 3); + if (ret != 0) + { + return ret; + } /* QVAR conversion */ data->raw = (int32_t)buff[2]; @@ -930,41 +969,22 @@ int32_t ilps22qs_ah_qvar_data_get(const stmdev_ctx_t *ctx, * @brief FIFO operation mode selection.[set] * * @param ctx communication interface handler.(ptr) - * @param val set the FIFO operation mode.(ptr) + * @param val set the FIFO operation mode. * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_fifo_mode_set(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val) +int32_t ilps22qs_fifo_mode_set(const stmdev_ctx_t *ctx, ilps22qs_operation_t val) { ilps22qs_fifo_ctrl_t fifo_ctrl; - ilps22qs_fifo_wtm_t fifo_wtm; - uint8_t reg[2]; int32_t ret; - ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_CTRL, reg, 2); + ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); if (ret == 0) { - bytecpy((uint8_t *)&fifo_ctrl, ®[0]); - bytecpy((uint8_t *)&fifo_wtm, ®[1]); - - fifo_ctrl.f_mode = (uint8_t)val->operation & 0x03U; - fifo_ctrl.trig_modes = ((uint8_t)val->operation & 0x04U) >> 2; - - if (val->watermark != 0x00U) - { - fifo_ctrl.stop_on_wtm = PROPERTY_ENABLE; - } - else - { - fifo_ctrl.stop_on_wtm = PROPERTY_DISABLE; - } + fifo_ctrl.f_mode = (uint8_t)val & 0x03U; + fifo_ctrl.trig_modes = ((uint8_t)val & 0x04U) >> 2; - fifo_wtm.wtm = val->watermark; - - bytecpy(®[0], (uint8_t *)&fifo_ctrl); - bytecpy(®[1], (uint8_t *)&fifo_wtm); - - ret = ilps22qs_write_reg(ctx, ILPS22QS_FIFO_CTRL, reg, 2); + ret = ilps22qs_write_reg(ctx, ILPS22QS_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); } return ret; } @@ -977,48 +997,137 @@ int32_t ilps22qs_fifo_mode_set(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_fifo_mode_get(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val) +int32_t ilps22qs_fifo_mode_get(const stmdev_ctx_t *ctx, ilps22qs_operation_t *val) { ilps22qs_fifo_ctrl_t fifo_ctrl; - ilps22qs_fifo_wtm_t fifo_wtm; - uint8_t reg[2]; int32_t ret; - ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_CTRL, reg, 2); - - bytecpy((uint8_t *)&fifo_ctrl, ®[0]); - bytecpy((uint8_t *)&fifo_wtm, ®[1]); + ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret != 0) + { + return ret; + } switch ((fifo_ctrl.trig_modes << 2) | fifo_ctrl.f_mode) { case ILPS22QS_BYPASS: - val->operation = ILPS22QS_BYPASS; + *val = ILPS22QS_BYPASS; break; case ILPS22QS_FIFO: - val->operation = ILPS22QS_FIFO; + *val = ILPS22QS_FIFO; break; case ILPS22QS_STREAM: - val->operation = ILPS22QS_STREAM; + *val = ILPS22QS_STREAM; break; case ILPS22QS_STREAM_TO_FIFO: - val->operation = ILPS22QS_STREAM_TO_FIFO; + *val = ILPS22QS_STREAM_TO_FIFO; break; case ILPS22QS_BYPASS_TO_STREAM: - val->operation = ILPS22QS_BYPASS_TO_STREAM; + *val = ILPS22QS_BYPASS_TO_STREAM; break; case ILPS22QS_BYPASS_TO_FIFO: - val->operation = ILPS22QS_BYPASS_TO_FIFO; + *val = ILPS22QS_BYPASS_TO_FIFO; break; default: - val->operation = ILPS22QS_BYPASS; + *val = ILPS22QS_BYPASS; break; } - val->watermark = fifo_wtm.wtm; return ret; } +/** + * @brief FIFO watermark selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val watermark value (0 disable; max 128) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps22qs_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ilps22qs_fifo_wtm_t fifo_wtm; + int32_t ret; + + assert(val < 128); + + ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + if (ret == 0) + { + fifo_wtm.wtm = val & 0x7F; + + ret = ilps22qs_write_reg(ctx, ILPS22QS_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + } + return ret; +} + +/** + * @brief FIFO watermark selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val watermark value (0 disable; max 128) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps22qs_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ilps22qs_fifo_wtm_t fifo_wtm; + int32_t ret; + + ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + if (ret == 0) + { + *val = fifo_wtm.wtm; + } + return ret; +} + +/** + * @brief FIFO stop_on_wtm selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val set the stop_on_wtm mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps22qs_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, ilps22qs_fifo_event_t *val) +{ + ilps22qs_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret == 0) + { + fifo_ctrl.stop_on_wtm = (val == ILPS22QS_FIFO_EV_WTM) ? 1 : 0; + + ret = ilps22qs_write_reg(ctx, ILPS22QS_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + } + return ret; +} + +/** + * @brief FIFO stop_on_wtm selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val get the stop_on_wtm mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps22qs_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, ilps22qs_fifo_event_t *val) +{ + ilps22qs_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret == 0) + { + *val = (fifo_ctrl.stop_on_wtm == 1) ? ILPS22QS_FIFO_EV_WTM : ILPS22QS_FIFO_EV_FULL; + } + return ret; +} + + /** * @brief Get the number of samples stored in FIFO.[get] * @@ -1034,6 +1143,10 @@ int32_t ilps22qs_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + if (ret != 0) + { + return ret; + } *val = fifo_status1.fss; @@ -1059,7 +1172,11 @@ int32_t ilps22qs_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, for (i = 0U; i < samp; i++) { - ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_DATA_OUT_PRESS_XL, fifo_data, 3); + ret += ilps22qs_read_reg(ctx, ILPS22QS_FIFO_DATA_OUT_PRESS_XL, fifo_data, 3); + if (ret != 0) + { + return ret; + } data[i].raw = (int32_t)fifo_data[2]; data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[1]; data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[0]; @@ -1165,6 +1282,10 @@ int32_t ilps22qs_interrupt_mode_get(const stmdev_ctx_t *ctx, ret += ilps22qs_read_reg(ctx, ILPS22QS_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + if (ret != 0) + { + return ret; + } val->int_latched = interrupt_cfg.lir; @@ -1258,6 +1379,10 @@ int32_t ilps22qs_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ilps22qs_read_reg(ctx, ILPS22QS_INTERRUPT_CFG, reg, 3); + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&interrupt_cfg, ®[0]); bytecpy((uint8_t *)&ths_p_l, ®[1]); @@ -1329,6 +1454,10 @@ int32_t ilps22qs_reference_mode_get(const stmdev_ctx_t *ctx, ilps22qs_ref_md_t * ret = ilps22qs_read_reg(ctx, ILPS22QS_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + if (ret != 0) + { + return ret; + } switch ((interrupt_cfg.reset_az << 1) | interrupt_cfg.autorefp) @@ -1384,6 +1513,10 @@ int32_t ilps22qs_opc_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ilps22qs_read_reg(ctx, ILPS22QS_RPDS_L, reg, 2); + if (ret != 0) + { + return ret; + } *val = (int16_t)reg[1]; *val = *val * 256 + (int16_t)reg[0]; @@ -1401,4 +1534,3 @@ int32_t ilps22qs_opc_get(const stmdev_ctx_t *ctx, int16_t *val) * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.h b/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.h index 688f9c3..3a0b443 100644 --- a/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.h +++ b/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -647,13 +649,21 @@ typedef enum ILPS22QS_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ } ilps22qs_operation_t; -typedef struct + +int32_t ilps22qs_fifo_mode_set(const stmdev_ctx_t *ctx, ilps22qs_operation_t val); +int32_t ilps22qs_fifo_mode_get(const stmdev_ctx_t *ctx, ilps22qs_operation_t *val); + +int32_t ilps22qs_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ilps22qs_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { - ilps22qs_operation_t operation; - uint8_t watermark : 7; /* (0 disable) max 128.*/ -} ilps22qs_fifo_md_t; -int32_t ilps22qs_fifo_mode_set(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val); -int32_t ilps22qs_fifo_mode_get(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val); + ILPS22QS_FIFO_EV_WTM = 0x0, + ILPS22QS_FIFO_EV_FULL = 0x1, +} ilps22qs_fifo_event_t; + +int32_t ilps22qs_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, ilps22qs_fifo_event_t *val); +int32_t ilps22qs_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, ilps22qs_fifo_event_t *val); int32_t ilps22qs_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val); @@ -721,4 +731,3 @@ int32_t ilps22qs_opc_get(const stmdev_ctx_t *ctx, int16_t *val); #endif /* ILPS22QS_REGS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.c b/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.c index 211d2a5..8b26682 100644 --- a/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.c +++ b/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.c @@ -6,18 +6,18 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ #include "ilps28qsw_reg.h" +#include /** * @defgroup ILPS28QSW @@ -96,7 +96,7 @@ int32_t __weak ilps28qsw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t * @brief Section collect all the utility functions needed by APIs. * @{ * - */ +*/ static void bytecpy(uint8_t *target, uint8_t *source) { @@ -165,6 +165,11 @@ int32_t ilps28qsw_id_get(const stmdev_ctx_t *ctx, ilps28qsw_id_t *val) int32_t ret; ret = ilps28qsw_read_reg(ctx, ILPS28QSW_WHO_AM_I, ®, 1); + if (ret != 0) + { + return ret; + } + val->whoami = reg; return ret; @@ -329,6 +334,12 @@ int32_t ilps28qsw_status_get(const stmdev_ctx_t *ctx, ilps28qsw_stat_t *val) ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); } + + if (ret != 0) + { + return ret; + } + val->sw_reset = ctrl_reg2.swreset; val->boot = int_source.boot_on; val->drdy_pres = status.p_da; @@ -379,6 +390,10 @@ int32_t ilps28qsw_pin_conf_get(const stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *va int32_t ret; ret = ilps28qsw_read_reg(ctx, ILPS28QSW_IF_CTRL, (uint8_t *)&if_ctrl, 1); + if (ret != 0) + { + return ret; + } val->sda_pull_up = if_ctrl.sda_pu_en; return ret; @@ -401,15 +416,21 @@ int32_t ilps28qsw_all_sources_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ilps28qsw_read_reg(ctx, ILPS28QSW_STATUS, (uint8_t *)&status, 1); - if (ret == 0) + if (ret != 0) { - ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INT_SOURCE, - (uint8_t *)&int_source, 1); + return ret; } - if (ret == 0) + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INT_SOURCE, + (uint8_t *)&int_source, 1); + if (ret != 0) { - ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); + return ret; + } + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + if (ret != 0) + { + return ret; } val->drdy_pres = status.p_da; @@ -521,6 +542,10 @@ int32_t ilps28qsw_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_md_t *val) int32_t ret; ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG1, reg, 3); + if (ret != 0) + { + return ret; + } if (ret == 0) { @@ -690,6 +715,11 @@ int32_t ilps28qsw_ah_qvar_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl_reg3.ah_qvar_en; return ret; @@ -711,6 +741,10 @@ int32_t ilps28qsw_data_get(const stmdev_ctx_t *ctx, ilps28qsw_md_t *md, int32_t ret; ret = ilps28qsw_read_reg(ctx, ILPS28QSW_PRESS_OUT_XL, buff, 5); + if (ret != 0) + { + return ret; + } /* pressure conversion */ data->pressure.raw = (int32_t)buff[2]; @@ -783,6 +817,11 @@ int32_t ilps28qsw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) uint8_t reg[3]; ret = ilps28qsw_read_reg(ctx, ILPS28QSW_PRESS_OUT_XL, reg, 3); + if (ret != 0) + { + return ret; + } + *buff = reg[2]; *buff = (*buff * 256U) + reg[1]; *buff = (*buff * 256U) + reg[0]; @@ -805,6 +844,11 @@ int32_t ilps28qsw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) uint8_t reg[2]; ret = ilps28qsw_read_reg(ctx, ILPS28QSW_TEMP_OUT_L, reg, 2); + if (ret != 0) + { + return ret; + } + *buff = (int16_t)reg[1]; *buff = (*buff * 256) + (int16_t)reg[0]; @@ -827,6 +871,10 @@ int32_t ilps28qsw_ah_qvar_data_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ilps28qsw_read_reg(ctx, ILPS28QSW_PRESS_OUT_XL, buff, 3); + if (ret != 0) + { + return ret; + } /* QVAR conversion */ data->raw = (int32_t)buff[2]; @@ -857,41 +905,22 @@ int32_t ilps28qsw_ah_qvar_data_get(const stmdev_ctx_t *ctx, * @brief FIFO operation mode selection.[set] * * @param ctx communication interface handler.(ptr) - * @param val set the FIFO operation mode.(ptr) + * @param val set the FIFO operation mode. * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_fifo_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val) +int32_t ilps28qsw_fifo_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_operation_t val) { ilps28qsw_fifo_ctrl_t fifo_ctrl; - ilps28qsw_fifo_wtm_t fifo_wtm; - uint8_t reg[2]; int32_t ret; - ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, reg, 2); + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); if (ret == 0) { - bytecpy((uint8_t *)&fifo_ctrl, ®[0]); - bytecpy((uint8_t *)&fifo_wtm, ®[1]); - - fifo_ctrl.f_mode = (uint8_t)val->operation & 0x03U; - fifo_ctrl.trig_modes = ((uint8_t)val->operation & 0x04U) >> 2; + fifo_ctrl.f_mode = (uint8_t)val & 0x03U; + fifo_ctrl.trig_modes = ((uint8_t)val & 0x04U) >> 2; - if (val->watermark != 0x00U) - { - fifo_ctrl.stop_on_wtm = PROPERTY_ENABLE; - } - else - { - fifo_ctrl.stop_on_wtm = PROPERTY_DISABLE; - } - - fifo_wtm.wtm = val->watermark; - - bytecpy(®[0], (uint8_t *)&fifo_ctrl); - bytecpy(®[1], (uint8_t *)&fifo_wtm); - - ret = ilps28qsw_write_reg(ctx, ILPS28QSW_FIFO_CTRL, reg, 2); + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); } return ret; } @@ -904,45 +933,132 @@ int32_t ilps28qsw_fifo_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *va * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_fifo_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val) +int32_t ilps28qsw_fifo_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_operation_t *val) { ilps28qsw_fifo_ctrl_t fifo_ctrl; - ilps28qsw_fifo_wtm_t fifo_wtm; - uint8_t reg[2]; int32_t ret; - ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, reg, 2); - - bytecpy((uint8_t *)&fifo_ctrl, ®[0]); - bytecpy((uint8_t *)&fifo_wtm, ®[1]); + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret != 0) + { + return ret; + } switch ((fifo_ctrl.trig_modes << 2) | fifo_ctrl.f_mode) { case ILPS28QSW_BYPASS: - val->operation = ILPS28QSW_BYPASS; + *val = ILPS28QSW_BYPASS; break; case ILPS28QSW_FIFO: - val->operation = ILPS28QSW_FIFO; + *val = ILPS28QSW_FIFO; break; case ILPS28QSW_STREAM: - val->operation = ILPS28QSW_STREAM; + *val = ILPS28QSW_STREAM; break; case ILPS28QSW_STREAM_TO_FIFO: - val->operation = ILPS28QSW_STREAM_TO_FIFO; + *val = ILPS28QSW_STREAM_TO_FIFO; break; case ILPS28QSW_BYPASS_TO_STREAM: - val->operation = ILPS28QSW_BYPASS_TO_STREAM; + *val = ILPS28QSW_BYPASS_TO_STREAM; break; case ILPS28QSW_BYPASS_TO_FIFO: - val->operation = ILPS28QSW_BYPASS_TO_FIFO; + *val = ILPS28QSW_BYPASS_TO_FIFO; break; default: - val->operation = ILPS28QSW_BYPASS; + *val = ILPS28QSW_BYPASS; break; } - val->watermark = fifo_wtm.wtm; + return ret; +} +/** + * @brief FIFO watermark selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val watermark value (0 disable; max 128) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ilps28qsw_fifo_wtm_t fifo_wtm; + int32_t ret; + + assert(val < 128); + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + if (ret == 0) + { + fifo_wtm.wtm = val & 0x7F; + + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + } + return ret; +} + +/** + * @brief FIFO watermark selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val watermark value (0 disable; max 128) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ilps28qsw_fifo_wtm_t fifo_wtm; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + if (ret == 0) + { + *val = fifo_wtm.wtm; + } + return ret; +} + +/** + * @brief FIFO stop_on_wtm selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val set the stop_on_wtm mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, ilps28qsw_fifo_event_t val) +{ + ilps28qsw_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret == 0) + { + fifo_ctrl.stop_on_wtm = (val == ILPS28QSW_FIFO_EV_WTM) ? 1 : 0; + + ret = ilps28qsw_write_reg(ctx, ILPS28QSW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + } + return ret; +} + +/** + * @brief FIFO stop_on_wtm selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val set the stop_on_wtm mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, ilps28qsw_fifo_event_t *val) +{ + ilps28qsw_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret == 0) + { + *val = (fifo_ctrl.stop_on_wtm == 1) ? ILPS28QSW_FIFO_EV_WTM : ILPS28QSW_FIFO_EV_FULL; + } return ret; } @@ -962,6 +1078,10 @@ int32_t ilps28qsw_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + if (ret != 0) + { + return ret; + } *val = fifo_status1.fss; @@ -989,6 +1109,11 @@ int32_t ilps28qsw_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, for (i = 0U; i < samp; i++) { ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_DATA_OUT_PRESS_XL, fifo_data, 3); + if (ret != 0) + { + return ret; + } + data[i].raw = (int32_t)fifo_data[2]; data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[1]; data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[0]; @@ -1169,6 +1294,10 @@ int32_t ilps28qsw_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, reg, 3); + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&interrupt_cfg, ®[0]); bytecpy((uint8_t *)&ths_p_l, ®[1]); @@ -1240,6 +1369,10 @@ int32_t ilps28qsw_reference_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_ref_md_t ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + if (ret != 0) + { + return ret; + } switch ((interrupt_cfg.reset_az << 1) | interrupt_cfg.autorefp) @@ -1273,6 +1406,10 @@ int32_t ilps28qsw_refp_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ilps28qsw_read_reg(ctx, ILPS28QSW_REF_P_L, reg, 2); + if (ret != 0) + { + return ret; + } *val = (int16_t)reg[1]; *val = *val * 256 + (int16_t)reg[0]; @@ -1315,6 +1452,10 @@ int32_t ilps28qsw_opc_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ilps28qsw_read_reg(ctx, ILPS28QSW_RPDS_L, reg, 2); + if (ret != 0) + { + return ret; + } *val = (int16_t)reg[1]; *val = *val * 256 + (int16_t)reg[0]; @@ -1332,5 +1473,3 @@ int32_t ilps28qsw_opc_get(const stmdev_ctx_t *ctx, int16_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.h b/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.h index 9a6308d..cf4f417 100644 --- a/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.h +++ b/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -645,13 +647,20 @@ typedef enum ILPS28QSW_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ } ilps28qsw_operation_t; -typedef struct +int32_t ilps28qsw_fifo_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_operation_t val); +int32_t ilps28qsw_fifo_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_operation_t *val); + +int32_t ilps28qsw_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ilps28qsw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { - ilps28qsw_operation_t operation; - uint8_t watermark : 7; /* (0 disable) max 128.*/ -} ilps28qsw_fifo_md_t; -int32_t ilps28qsw_fifo_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val); -int32_t ilps28qsw_fifo_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val); + ILPS28QSW_FIFO_EV_WTM = 0x0, + ILPS28QSW_FIFO_EV_FULL = 0x1, +} ilps28qsw_fifo_event_t; + +int32_t ilps28qsw_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, ilps28qsw_fifo_event_t val); +int32_t ilps28qsw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, ilps28qsw_fifo_event_t *val); int32_t ilps28qsw_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val); @@ -673,7 +682,6 @@ int32_t ilps28qsw_interrupt_mode_set(const stmdev_ctx_t *ctx, int32_t ilps28qsw_interrupt_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_int_mode_t *val); -int32_t ilps28qsw_ah_qvar_disable(const stmdev_ctx_t *ctx); int32_t ilps28qsw_ah_qvar_en_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t ilps28qsw_ah_qvar_en_get(const stmdev_ctx_t *ctx, uint8_t *val); @@ -722,5 +730,3 @@ int32_t ilps28qsw_opc_get(const stmdev_ctx_t *ctx, int16_t *val); #endif #endif /* ILPS28QSW_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c index ccbd7a5..7b17764 100644 --- a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c +++ b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -232,7 +231,10 @@ int32_t ism303dac_xl_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1); - *val = ctrl1_a.bdu; + if (ret == 0) + { + *val = ctrl1_a.bdu; + } return ret; } @@ -280,7 +282,10 @@ int32_t ism303dac_mg_block_data_update_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); - *val = cfg_reg_c_m.bdu; + if (ret == 0) + { + *val = cfg_reg_c_m.bdu; + } return ret; } @@ -328,6 +333,10 @@ int32_t ism303dac_mg_data_format_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + if (ret != 0) + { + return ret; + } switch (cfg_reg_c_m.ble) { @@ -388,6 +397,11 @@ int32_t ism303dac_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl1_a.fs) { case ISM303DAC_XL_2g: @@ -456,6 +470,11 @@ int32_t ism303dac_xl_data_rate_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL1_A, (uint8_t *)&ctrl1_a, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl1_a.hf_odr << 4) + ctrl1_a.odr) { case ISM303DAC_XL_ODR_OFF: @@ -594,7 +613,10 @@ int32_t ism303dac_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_A, (uint8_t *)&status_a, 1); - *val = status_a.drdy; + if (ret == 0) + { + *val = status_a.drdy; + } return ret; } @@ -614,7 +636,10 @@ int32_t ism303dac_mg_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_REG_M, (uint8_t *)&status_reg_m, 1); - *val = status_reg_m.zyxda; + if (ret == 0) + { + *val = status_reg_m.zyxda; + } return ret; } @@ -634,7 +659,10 @@ int32_t ism303dac_mg_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_STATUS_REG_M, (uint8_t *)&status_reg_m, 1); - *val = status_reg_m.zyxor; + if (ret == 0) + { + *val = status_reg_m.zyxor; + } return ret; } @@ -642,7 +670,7 @@ int32_t ism303dac_mg_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) /** * @brief These registers comprise a 3 group of 16-bit number and represent * hard-iron offset in order to compensate environmental effects. - * Data format is the same of output data raw: two’s complement with + * Data format is the same of output data raw: two's complement with * 1LSb = 1.5mG. These values act on the magnetic output data value * in order to delete the environmental offset.[set] * @@ -670,7 +698,7 @@ int32_t ism303dac_mg_user_offset_set(const stmdev_ctx_t *ctx, uint16_t *val) /** * @brief These registers comprise a 3 group of 16-bit number and represent * hard-iron offset in order to compensate environmental effects. - * Data format is the same of output data raw: two’s complement with + * Data format is the same of output data raw: two's complement with * 1LSb = 1.5mG. These values act on the magnetic output data value * in order to delete the environmental offset.[get] * @@ -685,6 +713,10 @@ int32_t ism303dac_mg_user_offset_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_OFFSET_X_REG_L_M, buff, 6); + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -738,6 +770,10 @@ int32_t ism303dac_mg_operating_mode_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + if (ret != 0) + { + return ret; + } switch (cfg_reg_a_m.md) { @@ -804,6 +840,10 @@ int32_t ism303dac_mg_data_rate_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + if (ret != 0) + { + return ret; + } switch (cfg_reg_a_m.odr) { @@ -874,6 +914,10 @@ int32_t ism303dac_mg_power_mode_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + if (ret != 0) + { + return ret; + } switch (cfg_reg_a_m.lp) { @@ -936,7 +980,10 @@ int32_t ism303dac_mg_offset_temp_comp_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); - *val = cfg_reg_a_m.comp_temp_en; + if (ret == 0) + { + *val = cfg_reg_a_m.comp_temp_en; + } return ret; } @@ -984,6 +1031,10 @@ int32_t ism303dac_mg_set_rst_mode_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M, (uint8_t *)&cfg_reg_b_m, 1); + if (ret != 0) + { + return ret; + } switch (cfg_reg_b_m.set_rst) { @@ -1056,7 +1107,10 @@ int32_t ism303dac_mg_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M, (uint8_t *)&cfg_reg_b_m, 1); - *val = cfg_reg_b_m.off_canc_one_shot; + if (ret == 0) + { + *val = cfg_reg_b_m.off_canc_one_shot; + } return ret; } @@ -1093,7 +1147,7 @@ int32_t ism303dac_acceleration_module_raw_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers together - * express a 16-bit word in two’s complement.[get] + * express a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions.(ptr) * @param buff buffer that stores data read @@ -1112,7 +1166,7 @@ int32_t ism303dac_xl_temperature_raw_get(const stmdev_ctx_t *ctx, /** * @brief Linear acceleration output register. The value is expressed as a - * 16-bit word in two’s complement.[get] + * 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions.(ptr) * @param buff buffer that stores data read @@ -1126,6 +1180,11 @@ int32_t ism303dac_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_OUT_X_L_A, buff, 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1150,6 +1209,11 @@ int32_t ism303dac_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_OUTX_L_REG_M, buff, 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1248,7 +1312,10 @@ int32_t ism303dac_xl_auto_increment_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1); - *val = ctrl2_a.if_add_inc; + if (ret == 0) + { + *val = ctrl2_a.if_add_inc; + } return ret; } @@ -1292,7 +1359,10 @@ int32_t ism303dac_xl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1); - *val = ctrl2_a.soft_reset; + if (ret == 0) + { + *val = ctrl2_a.soft_reset; + } return ret; } @@ -1338,7 +1408,10 @@ int32_t ism303dac_mg_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); - *val = cfg_reg_a_m.soft_rst; + if (ret == 0) + { + *val = cfg_reg_a_m.soft_rst; + } return ret; } @@ -1381,7 +1454,10 @@ int32_t ism303dac_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1); - *val = ctrl2_a.boot; + if (ret == 0) + { + *val = ctrl2_a.boot; + } return ret; } @@ -1427,7 +1503,10 @@ int32_t ism303dac_mg_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); - *val = cfg_reg_a_m.reboot; + if (ret == 0) + { + *val = cfg_reg_a_m.reboot; + } return ret; } @@ -1472,6 +1551,10 @@ int32_t ism303dac_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_a.st) { @@ -1536,7 +1619,10 @@ int32_t ism303dac_mg_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); - *val = cfg_reg_c_m.self_test; + if (ret == 0) + { + *val = cfg_reg_c_m.self_test; + } return ret; } @@ -1581,6 +1667,10 @@ int32_t ism303dac_xl_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_a.drdy_pulsed) { @@ -1653,6 +1743,10 @@ int32_t ism303dac_xl_hp_path_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2_a.fds_slope) { @@ -1715,6 +1809,10 @@ int32_t ism303dac_mg_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M, (uint8_t *)&cfg_reg_b_m, 1); + if (ret != 0) + { + return ret; + } switch (cfg_reg_b_m.lpf) { @@ -1787,6 +1885,10 @@ int32_t ism303dac_xl_spi_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2_a.sim) { @@ -1846,6 +1948,10 @@ int32_t ism303dac_xl_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL2_A, (uint8_t *)&ctrl2_a, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2_a.i2c_disable) { @@ -1908,6 +2014,10 @@ int32_t ism303dac_mg_i2c_interface_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + if (ret != 0) + { + return ret; + } switch (cfg_reg_c_m.i2c_dis) { @@ -1971,6 +2081,10 @@ int32_t ism303dac_xl_cs_mode_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A, (uint8_t *)&fifo_ctrl_a, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl_a.if_cs_pu_dis) { @@ -2043,6 +2157,10 @@ int32_t ism303dac_xl_pin_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_a.pp_od) { @@ -2102,6 +2220,10 @@ int32_t ism303dac_xl_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_a.h_lactive) { @@ -2161,6 +2283,10 @@ int32_t ism303dac_xl_int_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_a.lir) { @@ -2354,7 +2480,10 @@ int32_t ism303dac_xl_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL5_A, (uint8_t *)&ctrl5_a, 1); - *val = ctrl5_a.int2_on_int1; + if (ret == 0) + { + *val = ctrl5_a.int2_on_int1; + } return ret; } @@ -2400,7 +2529,10 @@ int32_t ism303dac_mg_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); - *val = cfg_reg_c_m.int_mag; + if (ret == 0) + { + *val = cfg_reg_c_m.int_mag; + } return ret; } @@ -2446,7 +2578,10 @@ int32_t ism303dac_mg_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); - *val = cfg_reg_c_m.int_mag_pin; + if (ret == 0) + { + *val = cfg_reg_c_m.int_mag_pin; + } return ret; } @@ -2510,7 +2645,7 @@ int32_t ism303dac_mg_int_gen_source_get(const stmdev_ctx_t *ctx, /** * @brief User-defined threshold value for xl interrupt event on generator. - * Data format is the same of output data raw: two’s complement with + * Data format is the same of output data raw: two's complement with * 1LSb = 1.5mG.[set] * * @param ctx read / write interface definitions.(ptr) @@ -2533,7 +2668,7 @@ int32_t ism303dac_mg_int_gen_threshold_set(const stmdev_ctx_t *ctx, /** * @brief User-defined threshold value for xl interrupt event on generator. - * Data format is the same of output data raw: two’s complement with + * Data format is the same of output data raw: two's complement with * 1LSb = 1.5mG.[get] * * @param ctx read / write interface definitions.(ptr) @@ -2548,8 +2683,11 @@ int32_t ism303dac_mg_int_gen_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_INT_THS_L_REG_M, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -2624,6 +2762,10 @@ int32_t ism303dac_mg_offset_int_conf_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_CFG_REG_B_M, (uint8_t *)&cfg_reg_b_m, 1); + if (ret != 0) + { + return ret; + } switch (cfg_reg_b_m.int_on_dataoff) { @@ -2686,7 +2828,10 @@ int32_t ism303dac_xl_wkup_threshold_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A, (uint8_t *)&wake_up_ths_a, 1); - *val = wake_up_ths_a.wu_ths; + if (ret == 0) + { + *val = wake_up_ths_a.wu_ths; + } return ret; } @@ -2732,7 +2877,10 @@ int32_t ism303dac_xl_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A, (uint8_t *)&wake_up_dur_a, 1); - *val = wake_up_dur_a.wu_dur; + if (ret == 0) + { + *val = wake_up_dur_a.wu_dur; + } return ret; } @@ -2791,7 +2939,10 @@ int32_t ism303dac_xl_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A, (uint8_t *)&wake_up_ths_a, 1); - *val = wake_up_ths_a.sleep_on; + if (ret == 0) + { + *val = wake_up_ths_a.sleep_on; + } return ret; } @@ -2838,7 +2989,10 @@ int32_t ism303dac_xl_act_sleep_dur_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_DUR_A, (uint8_t *)&wake_up_dur_a, 1); - *val = wake_up_dur_a.sleep_dur; + if (ret == 0) + { + *val = wake_up_dur_a.sleep_dur; + } return ret; } @@ -2896,7 +3050,10 @@ int32_t ism303dac_xl_tap_detection_on_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1); - *val = ctrl3_a.tap_z_en; + if (ret == 0) + { + *val = ctrl3_a.tap_z_en; + } return ret; } @@ -2941,7 +3098,10 @@ int32_t ism303dac_xl_tap_detection_on_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1); - *val = ctrl3_a.tap_y_en; + if (ret == 0) + { + *val = ctrl3_a.tap_y_en; + } return ret; } @@ -2986,7 +3146,10 @@ int32_t ism303dac_xl_tap_detection_on_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism303dac_read_reg(ctx, ISM303DAC_CTRL3_A, (uint8_t *)&ctrl3_a, 1); - *val = ctrl3_a.tap_x_en; + if (ret == 0) + { + *val = ctrl3_a.tap_x_en; + } return ret; } @@ -3033,7 +3196,10 @@ int32_t ism303dac_xl_tap_threshold_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A, (uint8_t *)&tap_6d_ths_a, 1); - *val = tap_6d_ths_a.tap_ths; + if (ret == 0) + { + *val = tap_6d_ths_a.tap_ths; + } return ret; } @@ -3087,7 +3253,10 @@ int32_t ism303dac_xl_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A, (uint8_t *)&int_dur_a, 1); - *val = int_dur_a.shock; + if (ret == 0) + { + *val = int_dur_a.shock; + } return ret; } @@ -3141,7 +3310,10 @@ int32_t ism303dac_xl_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A, (uint8_t *)&int_dur_a, 1); - *val = int_dur_a.quiet; + if (ret == 0) + { + *val = int_dur_a.quiet; + } return ret; } @@ -3197,7 +3369,10 @@ int32_t ism303dac_xl_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_INT_DUR_A, (uint8_t *)&int_dur_a, 1); - *val = int_dur_a.lat; + if (ret == 0) + { + *val = int_dur_a.lat; + } return ret; } @@ -3245,6 +3420,10 @@ int32_t ism303dac_xl_tap_mode_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_WAKE_UP_THS_A, (uint8_t *)&wake_up_ths_a, 1); + if (ret != 0) + { + return ret; + } switch (wake_up_ths_a.single_double_tap) { @@ -3338,6 +3517,10 @@ int32_t ism303dac_xl_6d_threshold_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A, (uint8_t *)&tap_6d_ths_a, 1); + if (ret != 0) + { + return ret; + } switch (tap_6d_ths_a._6d_ths) { @@ -3406,7 +3589,10 @@ int32_t ism303dac_xl_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_TAP_6D_THS_A, (uint8_t *)&tap_6d_ths_a, 1); - *val = tap_6d_ths_a._4d_en; + if (ret == 0) + { + *val = tap_6d_ths_a._4d_en; + } return ret; } @@ -3505,7 +3691,10 @@ int32_t ism303dac_xl_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)&free_fall_a, 1); } - *val = (wake_up_dur_a.ff_dur << 5) + free_fall_a.ff_dur; + if (ret == 0) + { + *val = (wake_up_dur_a.ff_dur << 5) + free_fall_a.ff_dur; + } return ret; } @@ -3551,7 +3740,10 @@ int32_t ism303dac_xl_ff_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_FREE_FALL_A, (uint8_t *)&free_fall_a, 1); - *val = free_fall_a.ff_ths; + if (ret == 0) + { + *val = free_fall_a.ff_ths; + } return ret; } @@ -3613,7 +3805,10 @@ int32_t ism303dac_xl_fifo_xl_module_batch_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A, (uint8_t *)&fifo_ctrl_a, 1); - *val = fifo_ctrl_a.module_to_fifo; + if (ret == 0) + { + *val = fifo_ctrl_a.module_to_fifo; + } return ret; } @@ -3661,6 +3856,10 @@ int32_t ism303dac_xl_fifo_mode_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_CTRL_A, (uint8_t *)&fifo_ctrl_a, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl_a.fmode) { @@ -3744,7 +3943,10 @@ int32_t ism303dac_xl_fifo_full_flag_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A, (uint8_t *)&fifo_src_a, 1); - *val = fifo_src_a.diff; + if (ret == 0) + { + *val = fifo_src_a.diff; + } return ret; } @@ -3765,7 +3967,10 @@ int32_t ism303dac_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A, (uint8_t *)&fifo_src_a, 1); - *val = fifo_src_a.fifo_ovr; + if (ret == 0) + { + *val = fifo_src_a.fifo_ovr; + } return ret; } @@ -3786,7 +3991,10 @@ int32_t ism303dac_xl_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SRC_A, (uint8_t *)&fifo_src_a, 1); - *val = fifo_src_a.fth; + if (ret == 0) + { + *val = fifo_src_a.fth; + } return ret; } @@ -3813,6 +4021,10 @@ int32_t ism303dac_xl_fifo_data_level_get(const stmdev_ctx_t *ctx, { ret = ism303dac_read_reg(ctx, ISM303DAC_FIFO_SAMPLES_A, (uint8_t *)&fifo_samples_a, 1); + } + + if (ret == 0) + { *val = fifo_src_a.diff; *val = *val << 7; *val += fifo_samples_a.diff; @@ -3893,7 +4105,10 @@ int32_t ism303dac_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism303dac_read_reg(ctx, ISM303DAC_FUNC_CTRL_A, (uint8_t *)&func_ctrl_a, 1); - *val = func_ctrl_a.module_on; + if (ret == 0) + { + *val = func_ctrl_a.module_on; + } return ret; } @@ -3907,5 +4122,3 @@ int32_t ism303dac_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h index a73300c..0f74a71 100644 --- a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h +++ b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1269,5 +1271,3 @@ int32_t ism303dac_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* ISM303DAC_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.c b/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.c index 051ca16..731d84c 100644 --- a/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.c +++ b/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -215,23 +214,19 @@ int32_t ism330bx_reset_set(const stmdev_ctx_t *ctx, ism330bx_reset_t val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + return ret; } - ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; - ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; - func_cfg_access.sw_por = (uint8_t)val & 0x01U; + ctrl3.boot = (val == ISM330BX_RESTORE_CAL_PARAM) ? 1 : 0; + ctrl3.sw_reset = (val == ISM330BX_RESTORE_CTRL_REGS) ? 1 : 0; + func_cfg_access.sw_por = (val == ISM330BX_GLOBAL_RST) ? 1 : 0; - if (ret == 0) - { - ret = ism330bx_write_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); - } - if (ret == 0) - { - ret = ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - } + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); + ret += ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); return ret; } @@ -251,9 +246,11 @@ int32_t ism330bx_reset_get(const stmdev_ctx_t *ctx, ism330bx_reset_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + return ret; } switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) @@ -318,6 +315,10 @@ int32_t ism330bx_mem_bank_get(const stmdev_ctx_t *ctx, ism330bx_mem_bank_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } switch (func_cfg_access.emb_func_reg_access) { @@ -350,6 +351,11 @@ int32_t ism330bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_WHO_AM_I, (uint8_t *)&who_am_i, 1); + if (ret != 0) + { + return ret; + } + *val = who_am_i.id; return ret; @@ -394,6 +400,10 @@ int32_t ism330bx_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1.odr_xl) { @@ -490,6 +500,10 @@ int32_t ism330bx_xl_mode_get(const stmdev_ctx_t *ctx, ism330bx_xl_mode_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1.op_mode_xl) { @@ -560,6 +574,10 @@ int32_t ism330bx_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2.odr_g) { @@ -651,6 +669,11 @@ int32_t ism330bx_gy_mode_get(const stmdev_ctx_t *ctx, ism330bx_gy_mode_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2.op_mode_g) { case ISM330BX_GY_HIGH_PERFORMANCE_MD: @@ -709,6 +732,11 @@ int32_t ism330bx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.if_inc; @@ -753,6 +781,11 @@ int32_t ism330bx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.bdu; return ret; @@ -798,6 +831,10 @@ int32_t ism330bx_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4.drdy_pulsed) { @@ -856,6 +893,10 @@ int32_t ism330bx_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6.fs_g) { @@ -930,6 +971,10 @@ int32_t ism330bx_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } switch (ctrl8.fs_xl) { @@ -990,6 +1035,11 @@ int32_t ism330bx_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8.xl_dualc_en; return ret; @@ -1036,6 +1086,10 @@ int32_t ism330bx_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } //switch (ctrl10.xl_st_offset) switch (ctrl10.st_xl) @@ -1099,6 +1153,10 @@ int32_t ism330bx_gy_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } switch (ctrl10.st_g) { @@ -1158,6 +1216,12 @@ int32_t ism330bx_all_sources_get(const stmdev_ctx_t *ctx, { ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_STATUS1, (uint8_t *)&buff, 4); } + + if (ret != 0) + { + return ret; + } + bytecpy((uint8_t *)&fifo_status2, &buff[1]); bytecpy((uint8_t *)&all_int_src, &buff[2]); bytecpy((uint8_t *)&status_reg, &buff[3]); @@ -1245,19 +1309,25 @@ int32_t ism330bx_all_sources_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, + 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); } - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, - 1); - } - if (ret == 0) + + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + return ret; } - ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); - val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; val->step_count_inc = emb_func_src.stepcounter_bit_set; @@ -1276,6 +1346,11 @@ int32_t ism330bx_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_STATUS_REG, (uint8_t *)&status, 1); + if (ret != 0) + { + return ret; + } + val->drdy_xl = status.xlda; val->drdy_gy = status.gda; val->drdy_temp = status.tda; @@ -1298,6 +1373,11 @@ int32_t ism330bx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_OUT_TEMP_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1318,6 +1398,11 @@ int32_t ism330bx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_OUTX_L_G, &buff[0], 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1342,6 +1427,11 @@ int32_t ism330bx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_OUTZ_L_A, &buff[0], 6); + if (ret != 0) + { + return ret; + } + val[2] = (int16_t)buff[1]; val[2] = (val[2] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1366,6 +1456,11 @@ int32_t ism330bx_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_UI_OUTZ_L_A_DUALC, &buff[0], 6); + if (ret != 0) + { + return ret; + } + val[2] = (int16_t)buff[1]; val[2] = (val[2] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1390,6 +1485,11 @@ int32_t ism330bx_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_AH_QVAR_OUT_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1410,6 +1510,11 @@ int32_t ism330bx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + if (ret != 0) + { + return ret; + } + *val = (int8_t)internal_freq.freq_fine; return ret; @@ -1454,6 +1559,11 @@ int32_t ism330bx_tdm_xl_axis_get(const stmdev_ctx_t *ctx, ism330bx_tdm_xl_axis_t int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + if (ret != 0) + { + return ret; + } + val->x = tdm_cfg1.tdm_xl_x_en; val->y = tdm_cfg1.tdm_xl_y_en; val->z = tdm_cfg1.tdm_xl_z_en; @@ -1484,57 +1594,95 @@ int32_t ism330bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, lsb = (uint8_t)address & 0xFFU; ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } /* set page write */ - ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_ENABLE; - ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); /* select page */ ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } /* set page addr */ page_address.page_addr = lsb; ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_ADDRESS, (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } for (i = 0; ((i < len) && (ret == 0)); i++) { - ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_VALUE, &buf[i], 1); + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) + { + goto exit; + } lsb++; /* Check if page wrap */ if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) { msb++; - ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used0 = 1; // Default value - ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + goto exit; } } } page_sel.page_sel = 0; page_sel.not_used0 = 1;// Default value - ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) + { + goto exit; + } /* unset page write */ - ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; - ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); +exit: ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); return ret; @@ -1563,57 +1711,95 @@ int32_t ism330bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, lsb = (uint8_t)address & 0xFFU; ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } /* set page write */ - ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; - ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); /* select page */ ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value - ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) + { + goto exit; + } /* set page addr */ page_address.page_addr = lsb; - ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } for (i = 0; ((i < len) && (ret == 0)); i++) { - ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_VALUE, &buf[i], 1); + ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) + { + goto exit; + } lsb++; /* Check if page wrap */ if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) { msb++; - ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used0 = 1; // Default value - ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + goto exit; } } } page_sel.page_sel = 0; page_sel.not_used0 = 1;// Default value - ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) + { + goto exit; + } /* unset page write */ - ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; - ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); +exit: ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); return ret; @@ -1669,6 +1855,11 @@ int32_t ism330bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + *val = functions_enable.timestamp_en; return ret; @@ -1688,6 +1879,11 @@ int32_t ism330bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TIMESTAMP0, &buff[0], 4); + if (ret != 0) + { + return ret; + } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1749,6 +1945,11 @@ int32_t ism330bx_filt_anti_spike_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.asf_ctrl) { case ISM330BX_AUTO: @@ -1834,13 +2035,12 @@ int32_t ism330bx_filt_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); - } - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + return ret; } val->drdy = ctrl4.drdy_mask; @@ -1890,6 +2090,10 @@ int32_t ism330bx_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6.lpf1_g_bw) { @@ -1970,6 +2174,11 @@ int32_t ism330bx_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7.lpf1_g_en; return ret; @@ -1991,10 +2200,7 @@ int32_t ism330bx_filt_ah_qvar_conf_set(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); - } + ret += ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); ctrl8.ah_qvar_hpf = val.hpf; ctrl9.ah_qvar_lpf = val.lpf; @@ -2027,9 +2233,11 @@ int32_t ism330bx_filt_ah_qvar_conf_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + return ret; } val->lpf = ctrl9.ah_qvar_lpf; @@ -2077,6 +2285,11 @@ int32_t ism330bx_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl8.hp_lpf2_xl_bw) { case ISM330BX_XL_ULTRA_LIGHT: @@ -2155,6 +2368,11 @@ int32_t ism330bx_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.lpf2_xl_en; return ret; @@ -2197,6 +2415,11 @@ int32_t ism330bx_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.hp_slope_xl_en; return ret; @@ -2239,6 +2462,11 @@ int32_t ism330bx_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.xl_fastsettl_mode; return ret; @@ -2283,6 +2511,11 @@ int32_t ism330bx_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl9.hp_ref_mode_xl) { case ISM330BX_HP_MD_NORMAL: @@ -2316,9 +2549,11 @@ int32_t ism330bx_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + return ret; } tap_cfg0.slope_fds = (uint8_t)val & 0x01U; @@ -2354,9 +2589,11 @@ int32_t ism330bx_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + return ret; } switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) @@ -2418,6 +2655,11 @@ int32_t ism330bx_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.hw_func_mask_xl_settl; return ret; @@ -2463,6 +2705,11 @@ int32_t ism330bx_filt_sixd_feed_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg0.low_pass_on_6d) { case ISM330BX_SIXD_FEED_ODR_DIV_2: @@ -2530,6 +2777,11 @@ int32_t ism330bx_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.sdo_pu_en; return ret; @@ -2574,6 +2826,11 @@ int32_t ism330bx_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.i2c_i3c_disable) { case ISM330BX_I2C_I3C_ENABLE: @@ -2628,6 +2885,11 @@ int32_t ism330bx_spi_mode_get(const stmdev_ctx_t *ctx, ism330bx_spi_mode_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.sim) { case ISM330BX_SPI_4_WIRE: @@ -2682,6 +2944,11 @@ int32_t ism330bx_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.sda_pu_en; return ret; @@ -2726,6 +2993,11 @@ int32_t ism330bx_i3c_ibi_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5.bus_act_sel) { case ISM330BX_IBI_2us: @@ -2802,6 +3074,11 @@ int32_t ism330bx_int_pin_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.pp_od) { case ISM330BX_PUSH_PULL: @@ -2858,6 +3135,11 @@ int32_t ism330bx_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.h_lactive) { case ISM330BX_ACTIVE_HIGH: @@ -3141,11 +3423,12 @@ int32_t ism330bx_pin_int1_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; + ret += ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); } + if (ret == 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; val->timestamp = md2_cfg.int2_timestamp; } } @@ -3153,71 +3436,73 @@ int32_t ism330bx_pin_int1_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - val->sleep_status = inactivity_dur.sleep_status_on_int; + ret += ism330bx_read_reg(ctx, ISM330BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_MD1_CFG, (uint8_t *)&md1_cfg, 1); } if (ret == 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - val->drdy_xl = int1_ctrl.int1_drdy_xl; - val->drdy_gy = int1_ctrl.int1_drdy_g; - val->fifo_th = int1_ctrl.int1_fifo_th; - val->fifo_ovr = int1_ctrl.int1_fifo_ovr; - val->fifo_full = int1_ctrl.int1_fifo_full; - val->fifo_bdr = int1_ctrl.int1_cnt_bdr; - } + val->sleep_status = inactivity_dur.sleep_status_on_int; + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_gy = int1_ctrl.int1_drdy_g; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->fifo_bdr = int1_ctrl.int1_cnt_bdr; - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_MD1_CFG, (uint8_t *)&md1_cfg, 1); - val->six_d = md1_cfg.int1_6d; - val->double_tap = md1_cfg.int1_double_tap; - val->free_fall = md1_cfg.int1_ff; - val->wake_up = md1_cfg.int1_wu; - val->single_tap = md1_cfg.int1_single_tap; + val->six_d = md1_cfg.int1_6d; + val->double_tap = md1_cfg.int1_double_tap; + val->free_fall = md1_cfg.int1_ff; + val->wake_up = md1_cfg.int1_wu; + val->single_tap = md1_cfg.int1_single_tap; val->sleep_change = md1_cfg.int1_sleep_change; } if (ret == 0) { ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_FSM_INT1, (uint8_t *)&fsm_int1, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_MLC_INT1, (uint8_t *)&mlc_int1, 1); + } + + if (ret == 0) + { + val->step_detector = emb_func_int1.int1_step_detector; + val->tilt = emb_func_int1.int1_tilt; + val->sig_mot = emb_func_int1.int1_sig_mot; + val->fsm_lc = emb_func_int1.int1_fsm_lc; + + val->fsm1 = fsm_int1.int1_fsm1; + val->fsm2 = fsm_int1.int1_fsm2; + val->fsm3 = fsm_int1.int1_fsm3; + val->fsm4 = fsm_int1.int1_fsm4; + val->fsm5 = fsm_int1.int1_fsm5; + val->fsm6 = fsm_int1.int1_fsm6; + val->fsm7 = fsm_int1.int1_fsm7; + val->fsm8 = fsm_int1.int1_fsm8; + + val->mlc1 = mlc_int1.int1_mlc1; + val->mlc2 = mlc_int1.int1_mlc2; + val->mlc3 = mlc_int1.int1_mlc3; + val->mlc4 = mlc_int1.int1_mlc4; + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); } + if (ret == 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); - val->step_detector = emb_func_int1.int1_step_detector; - val->tilt = emb_func_int1.int1_tilt; - val->sig_mot = emb_func_int1.int1_sig_mot; - val->fsm_lc = emb_func_int1.int1_fsm_lc; - } - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_FSM_INT1, (uint8_t *)&fsm_int1, 1); - val->fsm1 = fsm_int1.int1_fsm1; - val->fsm2 = fsm_int1.int1_fsm2; - val->fsm3 = fsm_int1.int1_fsm3; - val->fsm4 = fsm_int1.int1_fsm4; - val->fsm5 = fsm_int1.int1_fsm5; - val->fsm6 = fsm_int1.int1_fsm6; - val->fsm7 = fsm_int1.int1_fsm7; - val->fsm8 = fsm_int1.int1_fsm8; - } - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_MLC_INT1, (uint8_t *)&mlc_int1, 1); - val->mlc1 = mlc_int1.int1_mlc1; - val->mlc2 = mlc_int1.int1_mlc2; - val->mlc3 = mlc_int1.int1_mlc3; - val->mlc4 = mlc_int1.int1_mlc4; + ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); } - ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); - if (ret == 0) { - ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); val->step_count_overflow = pedo_cmd_reg.carry_count_en; } @@ -3254,14 +3539,8 @@ int32_t ism330bx_pin_int2_route_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); - } - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); - } - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); } if (ret == 0) @@ -3340,6 +3619,10 @@ int32_t ism330bx_pin_int2_route_set(const stmdev_ctx_t *ctx, { ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); ctrl7.int2_drdy_ah_qvar = val.drdy_ah_qvar; + } + + if (ret == 0) + { ret += ism330bx_write_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); } @@ -3466,70 +3749,67 @@ int32_t ism330bx_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + if (ctrl4.int2_on_int1 == PROPERTY_DISABLE) { - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; - } - if (ret == 0) + ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); - val->timestamp = md2_cfg.int2_timestamp; + return ret; } + + val->timestamp = md2_cfg.int2_timestamp; + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; } - if (ret == 0) + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - val->sleep_status = inactivity_dur.sleep_status_on_int; + return ret; } + val->sleep_status = inactivity_dur.sleep_status_on_int; - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->drdy_xl = int2_ctrl.int2_drdy_xl; - val->drdy_gy = int2_ctrl.int2_drdy_g; - val->fifo_th = int2_ctrl.int2_fifo_th; - val->fifo_ovr = int2_ctrl.int2_fifo_ovr; - val->fifo_full = int2_ctrl.int2_fifo_full; - val->fifo_bdr = int2_ctrl.int2_cnt_bdr; - } + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_gy = int2_ctrl.int2_drdy_g; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->fifo_bdr = int2_ctrl.int2_cnt_bdr; - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); - val->drdy_ah_qvar = ctrl7.int2_drdy_ah_qvar; - } + val->six_d = md2_cfg.int2_6d; + val->double_tap = md2_cfg.int2_double_tap; + val->free_fall = md2_cfg.int2_ff; + val->wake_up = md2_cfg.int2_wu; + val->single_tap = md2_cfg.int2_single_tap; + val->sleep_change = md2_cfg.int2_sleep_change; - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); - val->six_d = md2_cfg.int2_6d; - val->double_tap = md2_cfg.int2_double_tap; - val->free_fall = md2_cfg.int2_ff; - val->wake_up = md2_cfg.int2_wu; - val->single_tap = md2_cfg.int2_single_tap; - val->sleep_change = md2_cfg.int2_sleep_change; - } + val->drdy_ah_qvar = ctrl7.int2_drdy_ah_qvar; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); if (ret == 0) { - ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); } + if (ret == 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); val->step_detector = emb_func_int2.int2_step_detector; val->tilt = emb_func_int2.int2_tilt; val->sig_mot = emb_func_int2.int2_sig_mot; val->fsm_lc = emb_func_int2.int2_fsm_lc; - } - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + val->fsm1 = fsm_int2.int2_fsm1; val->fsm2 = fsm_int2.int2_fsm2; val->fsm3 = fsm_int2.int2_fsm3; @@ -3538,10 +3818,7 @@ int32_t ism330bx_pin_int2_route_get(const stmdev_ctx_t *ctx, val->fsm6 = fsm_int2.int2_fsm6; val->fsm7 = fsm_int2.int2_fsm7; val->fsm8 = fsm_int2.int2_fsm8; - } - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + val->mlc1 = mlc_int2.int2_mlc1; val->mlc2 = mlc_int2.int2_mlc2; val->mlc3 = mlc_int2.int2_mlc3; @@ -3553,6 +3830,10 @@ int32_t ism330bx_pin_int2_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + if (ret == 0) + { val->step_count_overflow = pedo_cmd_reg.carry_count_en; } @@ -3596,6 +3877,11 @@ int32_t ism330bx_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl5.int_en_i3c; return ret; @@ -3626,19 +3912,20 @@ int32_t ism330bx_int_notification_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); - } - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } - ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + } return ret; } @@ -3662,14 +3949,20 @@ int32_t ism330bx_int_notification_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); } - if (ret == 0) + + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + return ret; } - ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); - switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir) { case ISM330BX_ALL_INT_PULSED: @@ -3745,6 +4038,11 @@ int32_t ism330bx_act_mode_get(const stmdev_ctx_t *ctx, ism330bx_act_mode_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + switch (functions_enable.inact_en) { case ISM330BX_XL_AND_GY_NOT_AFFECTED: @@ -3809,6 +4107,11 @@ int32_t ism330bx_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret != 0) + { + return ret; + } + switch (inactivity_dur.inact_dur) { case ISM330BX_SLEEP_TO_ACT_AT_1ST_SAMPLE: @@ -3873,6 +4176,11 @@ int32_t ism330bx_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret != 0) + { + return ret; + } + switch (inactivity_dur.xl_inact_odr) { case ISM330BX_1Hz875: @@ -3916,14 +4224,12 @@ int32_t ism330bx_act_thresholds_set(const stmdev_ctx_t *ctx, float_t tmp; ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); - } + ret += ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); - if (ret == 0) + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + return ret; } if ((val.wk_ths_mg < (uint32_t)(7.8125f * 63.0f)) @@ -4035,13 +4341,12 @@ int32_t ism330bx_act_thresholds_get(const stmdev_ctx_t *ctx, float_t tmp; ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); - } - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + return ret; } switch (inactivity_dur.wu_inact_ths_w) @@ -4138,6 +4443,11 @@ int32_t ism330bx_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + val->shock = wake_up_dur.wake_dur; val->quiet = wake_up_dur.sleep_dur; @@ -4198,6 +4508,11 @@ int32_t ism330bx_tap_detection_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + val->tap_x_en = tap_cfg0.tap_x_en; val->tap_y_en = tap_cfg0.tap_y_en; val->tap_z_en = tap_cfg0.tap_z_en; @@ -4222,13 +4537,11 @@ int32_t ism330bx_tap_thresholds_set(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); - } - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + return ret; } tap_cfg1.tap_ths_z = val.z; @@ -4268,13 +4581,11 @@ int32_t ism330bx_tap_thresholds_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); - } - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + return ret; } val->z = tap_cfg1.tap_ths_z; @@ -4323,6 +4634,11 @@ int32_t ism330bx_tap_axis_priority_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg1.tap_priority) { case ISM330BX_XYZ : @@ -4398,6 +4714,11 @@ int32_t ism330bx_tap_time_windows_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret != 0) + { + return ret; + } + val->shock = tap_dur.shock; val->quiet = tap_dur.quiet; val->tap_gap = tap_dur.dur; @@ -4442,6 +4763,11 @@ int32_t ism330bx_tap_mode_get(const stmdev_ctx_t *ctx, ism330bx_tap_mode_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + switch (wake_up_ths.single_double_tap) { case ISM330BX_ONLY_SINGLE: @@ -4511,6 +4837,11 @@ int32_t ism330bx_6d_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + switch (tap_ths_6d.sixd_ths) { case ISM330BX_DEG_80: @@ -4598,9 +4929,10 @@ int32_t ism330bx_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1); + return ret; } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -4647,6 +4979,10 @@ int32_t ism330bx_ff_thresholds_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -4739,6 +5075,11 @@ int32_t ism330bx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl1.wtm; return ret; @@ -4781,6 +5122,11 @@ int32_t ism330bx_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *va int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; return ret; @@ -4825,6 +5171,10 @@ int32_t ism330bx_fifo_compress_algo_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl2.uncompr_rate) { @@ -4890,6 +5240,11 @@ int32_t ism330bx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odr_chg_en; return ret; @@ -4921,18 +5276,19 @@ int32_t ism330bx_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); - } - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); - } - if (ret == 0) - { - emb_func_en_b.fifo_compr_en = val; - ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); - } - ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fifo_compr_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + } return ret; } @@ -4952,6 +5308,10 @@ int32_t ism330bx_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } *val = fifo_ctrl2.fifo_compr_rt_en; @@ -4995,6 +5355,11 @@ int32_t ism330bx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -5039,6 +5404,11 @@ int32_t ism330bx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl3.bdr_xl) { case ISM330BX_XL_NOT_BATCHED: @@ -5135,6 +5505,11 @@ int32_t ism330bx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl3.bdr_gy) { case ISM330BX_GY_NOT_BATCHED: @@ -5231,6 +5606,11 @@ int32_t ism330bx_fifo_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.fifo_mode) { case ISM330BX_BYPASS_MODE: @@ -5307,6 +5687,11 @@ int32_t ism330bx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.odr_t_batch) { case ISM330BX_TEMP_NOT_BATCHED: @@ -5371,6 +5756,11 @@ int32_t ism330bx_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.dec_ts_batch) { case ISM330BX_TMSTMP_NOT_BATCHED: @@ -5439,6 +5829,11 @@ int32_t ism330bx_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = (uint16_t)buff[0] & 0x3U; *val = (*val * 256U) + (uint16_t)buff[1]; @@ -5482,6 +5877,11 @@ int32_t ism330bx_fifo_batch_ah_qvar_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + *val = counter_bdr_reg1.ah_qvar_batch_en; return ret; @@ -5527,6 +5927,11 @@ int32_t ism330bx_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + switch (counter_bdr_reg1.trig_counter_bdr) { case ISM330BX_XL_BATCH_EVENT: @@ -5562,6 +5967,10 @@ int32_t ism330bx_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; @@ -5592,7 +6001,10 @@ int32_t ism330bx_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + if (ret == 0) + { val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; @@ -5619,6 +6031,11 @@ int32_t ism330bx_fifo_status_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + if (ret != 0) + { + return ret; + } + bytecpy((uint8_t *)&status, &buff[1]); val->fifo_bdr = status.counter_bdr_ia; @@ -5648,6 +6065,11 @@ int32_t ism330bx_fifo_out_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_DATA_OUT_TAG, buff, 7); + if (ret != 0) + { + return ret; + } + bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); switch (fifo_data_out_tag.tag_sensor) @@ -5810,7 +6232,10 @@ int32_t ism330bx_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); } - *val = emb_func_fifo_en_a.step_counter_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_a.step_counter_fifo_en; + } ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); @@ -5867,7 +6292,10 @@ int32_t ism330bx_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); } - *val = emb_func_fifo_en_a.mlc_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_a.mlc_fifo_en; + } ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); @@ -5923,7 +6351,10 @@ int32_t ism330bx_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); } - *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + } ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); @@ -5962,10 +6393,7 @@ int32_t ism330bx_stpcnt_mode_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - } - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } if ((val.false_step_rej == PROPERTY_ENABLE) && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == @@ -6021,8 +6449,12 @@ int32_t ism330bx_stpcnt_mode_get(const stmdev_ctx_t *ctx, { ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); } - val->false_step_rej = pedo_cmd_reg.fp_rejection_en; - val->step_counter_enable = emb_func_en_a.pedo_en; + + if (ret == 0) + { + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + } return ret; } @@ -6048,8 +6480,11 @@ int32_t ism330bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -6103,7 +6538,10 @@ int32_t ism330bx_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); } - *val = emb_func_src.pedo_rst_step; + if (ret == 0) + { + *val = emb_func_src.pedo_rst_step; + } ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); @@ -6150,7 +6588,10 @@ int32_t ism330bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); - *val = pedo_deb_steps_conf.deb_step; + if (ret == 0) + { + *val = pedo_deb_steps_conf.deb_step; + } return ret; } @@ -6190,8 +6631,12 @@ int32_t ism330bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_SC_DELTAT_L, &buff[0], 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -6257,7 +6702,10 @@ int32_t ism330bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } - *val = emb_func_en_a.sign_motion_en; + if (ret == 0) + { + *val = emb_func_en_a.sign_motion_en; + } ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); @@ -6325,7 +6773,10 @@ int32_t ism330bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } - *val = emb_func_en_a.tilt_en; + if (ret == 0) + { + *val = emb_func_en_a.tilt_en; + } ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); @@ -6361,6 +6812,9 @@ int32_t ism330bx_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val) if (ret == 0) { ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { emb_func_en_a.sflp_game_en = val; ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); @@ -6388,6 +6842,9 @@ int32_t ism330bx_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { *val = emb_func_en_a.sflp_game_en; } @@ -6414,6 +6871,9 @@ int32_t ism330bx_sflp_data_rate_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330bx_read_reg(ctx, ISM330BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + } + if (ret == 0) + { sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; ret += ism330bx_write_reg(ctx, ISM330BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); @@ -6439,9 +6899,17 @@ int32_t ism330bx_sflp_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); - ret += ism330bx_read_reg(ctx, ISM330BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + } ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (sflp_odr.sflp_game_odr) { case ISM330BX_SFLP_15Hz: @@ -6707,6 +7175,12 @@ int32_t ism330bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, ret += ism330bx_read_reg(ctx, ISM330BX_CTRL1, conf_saved, 2); ret += ism330bx_xl_mode_set(ctx, ISM330BX_XL_HIGH_PERFORMANCE_MD); ret += ism330bx_gy_mode_set(ctx, ISM330BX_GY_HIGH_PERFORMANCE_MD); + + if (ret != 0) + { + return ret; + } + if ((conf_saved[0] & 0x0FU) == ISM330BX_XL_ODR_OFF) { ret += ism330bx_xl_data_rate_set(ctx, ISM330BX_XL_ODR_AT_120Hz); @@ -6714,29 +7188,59 @@ int32_t ism330bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, /* disable algos */ ret += ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); - ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, emb_func_en_saved, - 2); - ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, reg_zero, 2); - do + + if (ret == 0) { - ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EXEC_STATUS, - (uint8_t *)&emb_func_sts, 1); - } while (emb_func_sts.emb_func_endop != 1); + ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + } + if (ret == 0) + { + ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, reg_zero, 2); + } + if (ret == 0) + { + do + { + ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + } ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + // enable gbias setting ret += ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } ctrl10.emb_func_debug = 1; ret += ism330bx_write_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } /* enable algos */ ret += ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); - emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */ - ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, emb_func_en_saved, - 2); + if (ret == 0) + { + emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */ + ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + } ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); ret += ism330bx_xl_full_scale_get(ctx, &xl_fs); + if (ret != 0) + { + return ret; + } /* Read XL data */ do @@ -6744,11 +7248,20 @@ int32_t ism330bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, ret += ism330bx_flag_data_ready_get(ctx, &drdy); } while (drdy.drdy_xl != 1); ret += ism330bx_acceleration_raw_get(ctx, xl_data); + if (ret != 0) + { + return ret; + } /* force sflp initialization */ master_config = 0x40; ret += ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, &master_config, 1); + if (ret != 0) + { + return ret; + } + for (i = 0; i < 3; i++) { j = 0; @@ -6769,23 +7282,38 @@ int32_t ism330bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, master_config = 0x00; ret += ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, &master_config, 1); + if (ret != 0) + { + return ret; + } // wait end_op (and at least 30 us) ctx->mdelay(1); ret += ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); - do + if (ret == 0) { - ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EXEC_STATUS, - (uint8_t *)&emb_func_sts, 1); - } while (emb_func_sts.emb_func_endop != 1); + do + { + ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + } ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); /* write gbias in embedded advanced features registers */ ret += ism330bx_ln_pg_write(ctx, ISM330BX_SFLP_GAME_GBIASX_L, (uint8_t *)gbias_hf, 6); + if (ret != 0) + { + return ret; + } /* reload previous sensor configuration */ ret += ism330bx_write_reg(ctx, ISM330BX_CTRL1, conf_saved, 2); + if (ret != 0) + { + return ret; + } // disable gbias setting ctrl10.emb_func_debug = 0; @@ -6863,6 +7391,11 @@ int32_t ism330bx_fsm_permission_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + switch (func_cfg_access.fsm_wr_ctrl_en) { case ISM330BX_PROTECT_CTRL_REGS: @@ -6895,6 +7428,11 @@ int32_t ism330bx_fsm_permission_status(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL_STATUS, (uint8_t *)&status, 1); + if (ret != 0) + { + return ret; + } + *val = (status.fsm_wr_ctrl_status == 0) ? ISM330BX_STD_IF_CONTROL : ISM330BX_FSM_CONTROL; return ret; @@ -6975,6 +7513,11 @@ int32_t ism330bx_fsm_mode_get(const stmdev_ctx_t *ctx, ism330bx_fsm_mode_t *val) ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + val->fsm1_en = fsm_enable.fsm1_en; val->fsm2_en = fsm_enable.fsm2_en; val->fsm3_en = fsm_enable.fsm3_en; @@ -7035,6 +7578,11 @@ int32_t ism330bx_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7117,6 +7665,11 @@ int32_t ism330bx_fsm_data_rate_get(const stmdev_ctx_t *ctx, ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (fsm_odr.fsm_odr) { case ISM330BX_FSM_15Hz: @@ -7188,6 +7741,11 @@ int32_t ism330bx_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val int32_t ret; ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_LC_TIMEOUT_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7231,6 +7789,11 @@ int32_t ism330bx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *va int32_t ret; ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + if (ret != 0) + { + return ret; + } + *val = fsm_programs.fsm_n_prog; @@ -7271,6 +7834,11 @@ int32_t ism330bx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_START_ADD_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7311,26 +7879,29 @@ int32_t ism330bx_mlc_set(const stmdev_ctx_t *ctx, ism330bx_mlc_mode_t val) ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - switch (val) + if (ret == 0) { - case ISM330BX_MLC_OFF: - emb_en_a.mlc_before_fsm_en = 0; - emb_en_b.mlc_en = 0; - break; - case ISM330BX_MLC_ON: - emb_en_a.mlc_before_fsm_en = 0; - emb_en_b.mlc_en = 1; - break; - case ISM330BX_MLC_ON_BEFORE_FSM: - emb_en_a.mlc_before_fsm_en = 1; - emb_en_b.mlc_en = 0; - break; - default: - break; - } + switch (val) + { + case ISM330BX_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case ISM330BX_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case ISM330BX_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + break; + } - ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); - ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } } ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); @@ -7359,21 +7930,24 @@ int32_t ism330bx_mlc_get(const stmdev_ctx_t *ctx, ism330bx_mlc_mode_t *val) ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) - { - *val = ISM330BX_MLC_OFF; - } - else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) - { - *val = ISM330BX_MLC_ON; - } - else if (emb_en_a.mlc_before_fsm_en == 1U) - { - *val = ISM330BX_MLC_ON_BEFORE_FSM; - } - else + if (ret == 0) { - /* Do nothing */ + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = ISM330BX_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = ISM330BX_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = ISM330BX_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } } } @@ -7435,6 +8009,11 @@ int32_t ism330bx_mlc_data_rate_get(const stmdev_ctx_t *ctx, ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (mlc_odr.mlc_odr) { case ISM330BX_MLC_15Hz: @@ -7534,6 +8113,12 @@ int32_t ism330bx_mlc_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val int32_t ret; ret = ism330bx_ln_pg_read(ctx, ISM330BX_MLC_QVAR_SENSITIVITY_L, &buff[0], 2); + + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7590,6 +8175,11 @@ int32_t ism330bx_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.usr_off_on_out; return ret; @@ -7614,20 +8204,15 @@ int32_t ism330bx_xl_offset_mg_set(const stmdev_ctx_t *ctx, float_t tmp; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); - } - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); - } - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + return ret; } - if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) && (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f))) @@ -7703,17 +8288,13 @@ int32_t ism330bx_xl_offset_mg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); - } - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); - } - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + return ret; } if (ctrl9.usr_off_w == PROPERTY_DISABLE) @@ -7763,10 +8344,7 @@ int32_t ism330bx_ah_qvar_mode_set(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); - if (ret == 0) - { - ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); - } + ret += ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); if (ret == 0) { @@ -7808,9 +8386,11 @@ int32_t ism330bx_ah_qvar_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); - if (ret == 0) + ret += ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret != 0) { - ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + return ret; } val->ah_qvar1_en = ctrl7.ah_qvar1_en; @@ -7859,6 +8439,11 @@ int32_t ism330bx_ah_qvar_zin_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl7.ah_qvar_c_zin) { case ISM330BX_2400MOhm: @@ -7924,6 +8509,11 @@ int32_t ism330bx_fsm_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val int32_t ret; ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_QVAR_SENSITIVITY_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7982,6 +8572,11 @@ int32_t ism330bx_i3c_reset_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + switch (pin_ctrl.ibhr_por_en) { case ISM330BX_SW_RST_DYN_ADDRESS_RST: @@ -8049,6 +8644,11 @@ int32_t ism330bx_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.tdm_wclk_pu_dis; return ret; @@ -8091,6 +8691,11 @@ int32_t ism330bx_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.tdm_out_pu_en; return ret; @@ -8136,6 +8741,11 @@ int32_t ism330bx_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch ((tdm_cfg0.tdm_wclk_bclk_sel << 2) + tdm_cfg0.tdm_wclk) { case ISM330BX_WCLK_16kHZ_BCLK_2048kHz: @@ -8190,6 +8800,11 @@ int32_t ism330bx_tdm_slot_get(const stmdev_ctx_t *ctx, ism330bx_tdm_slot_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (tdm_cfg0.tdm_slot_sel) { case ISM330BX_SLOT_012: @@ -8246,6 +8861,11 @@ int32_t ism330bx_tdm_bclk_edge_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (tdm_cfg0.tdm_bclk_edge_sel) { case ISM330BX_BCLK_RISING: @@ -8300,6 +8920,11 @@ int32_t ism330bx_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tdm_cfg0.tdm_delayed_cfg; return ret; @@ -8345,6 +8970,11 @@ int32_t ism330bx_tdm_axis_order_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + if (ret != 0) + { + return ret; + } + switch (tdm_cfg1.tdm_axes_ord_sel) { case ISM330BX_TDM_ORDER_ZYX: @@ -8405,6 +9035,11 @@ int32_t ism330bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + if (ret != 0) + { + return ret; + } + switch (tdm_cfg2.tdm_fs_xl) { case ISM330BX_TDM_2g: @@ -8436,4 +9071,3 @@ int32_t ism330bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.h b/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.h index 0a63cdf..ce5d8ad 100644 --- a/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.h +++ b/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -3734,5 +3736,3 @@ int32_t ism330bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, #endif #endif /*ISM330BX_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c index 3772a7a..feedd5e 100644 --- a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c +++ b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -73,7 +72,7 @@ int32_t __weak ism330dhcx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, * */ int32_t __weak ism330dhcx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, - const uint8_t *data, + uint8_t *data, uint16_t len) { int32_t ret; @@ -88,26 +87,6 @@ int32_t __weak ism330dhcx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, return ret; } -/** - * @} - * - */ - -/** - * @defgroup LIS2DU12_Private_functions - * @brief Section collect all the utility functions needed by APIs. - * @{ - * - */ - -static void bytecpy(uint8_t *target, uint8_t *source) -{ - if ((target != NULL) && (source != NULL)) - { - *target = *source; - } -} - /** * @} * @@ -234,6 +213,10 @@ int32_t ism330dhcx_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1_xl.fs_xl) { @@ -407,7 +390,7 @@ int32_t ism330dhcx_xl_data_rate_set(const stmdev_ctx_t *ctx, if (mlc_enable == PROPERTY_ENABLE) { - ret = ism330dhcx_mlc_data_rate_get(ctx, &mlc_odr); + ret += ism330dhcx_mlc_data_rate_get(ctx, &mlc_odr); if (ret == 0) { @@ -534,6 +517,10 @@ int32_t ism330dhcx_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1_xl.odr_xl) { @@ -634,6 +621,10 @@ int32_t ism330dhcx_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2_g.fs_g) { @@ -815,7 +806,7 @@ int32_t ism330dhcx_gy_data_rate_set(const stmdev_ctx_t *ctx, if (mlc_enable == PROPERTY_ENABLE) { - ret = ism330dhcx_mlc_data_rate_get(ctx, &mlc_odr); + ret += ism330dhcx_mlc_data_rate_get(ctx, &mlc_odr); if (ret == 0) { @@ -942,6 +933,10 @@ int32_t ism330dhcx_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2_g.odr_g) { @@ -1038,6 +1033,11 @@ int32_t ism330dhcx_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.bdu; return ret; @@ -1086,6 +1086,10 @@ int32_t ism330dhcx_xl_offset_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.usr_off_w) { @@ -1146,6 +1150,10 @@ int32_t ism330dhcx_xl_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.xl_hm_mode) { @@ -1206,6 +1214,10 @@ int32_t ism330dhcx_gy_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl7_g.g_hm_mode) { @@ -1231,6 +1243,7 @@ int32_t ism330dhcx_gy_power_mode_get(const stmdev_ctx_t *ctx, * @param ctx Read / write interface definitions.(ptr) * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC; * TAP_SRC; D6D_SRC; STATUS_REG; + * MLC_STATUS_MAINPAGE; * EMB_FUNC_STATUS; FSM_STATUS_A/B * @retval Interface status (MANDATORY: return 0 -> no Error). * @@ -1269,9 +1282,17 @@ int32_t ism330dhcx_all_sources_get(const stmdev_ctx_t *ctx, if (ret == 0) { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK); + ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MLC_STATUS_MAINPAGE, + (uint8_t *)&val->mlc_status, 1); + } + + if (ret != 0) + { + return ret; } + ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK); + if (ret == 0) { ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_STATUS, @@ -1290,10 +1311,7 @@ int32_t ism330dhcx_all_sources_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_status_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -1332,6 +1350,11 @@ int32_t ism330dhcx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.xlda; return ret; @@ -1353,6 +1376,11 @@ int32_t ism330dhcx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.gda; return ret; @@ -1374,6 +1402,11 @@ int32_t ism330dhcx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.tda; return ret; @@ -1540,6 +1573,11 @@ int32_t ism330dhcx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7_g.usr_off_on_out; return ret; @@ -1612,6 +1650,11 @@ int32_t ism330dhcx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl10_c.timestamp_en; return ret; @@ -1633,6 +1676,11 @@ int32_t ism330dhcx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TIMESTAMP0, buff, 4); + if (ret != 0) + { + return ret; + } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1696,6 +1744,10 @@ int32_t ism330dhcx_rounding_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.rounding) { @@ -1740,6 +1792,11 @@ int32_t ism330dhcx_temperature_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_OUT_TEMP_L, buff, 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1762,6 +1819,11 @@ int32_t ism330dhcx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_OUTX_L_G, buff, 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1788,6 +1850,11 @@ int32_t ism330dhcx_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_OUTX_L_A, buff, 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1838,10 +1905,7 @@ int32_t ism330dhcx_number_of_steps_get(const stmdev_ctx_t *ctx, *val = (*val * 256U) + buff[0]; } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -1873,10 +1937,7 @@ int32_t ism330dhcx_steps_reset(const stmdev_ctx_t *ctx) (uint8_t *)&emb_func_src, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -1934,6 +1995,11 @@ int32_t ism330dhcx_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.device_conf; return ret; @@ -1941,7 +2007,7 @@ int32_t ism330dhcx_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) /** * @brief Difference in percentage of the effective ODR (and timestamp rate) - * with respect to the typical.[set] + * with respect to the typical.[get] * Step: 0.15%. 8-bit format, 2's complement. * * @param ctx Read / write interface definitions.(ptr) @@ -1949,42 +2015,19 @@ int32_t ism330dhcx_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) { ism330dhcx_internal_freq_fine_t internal_freq_fine; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); - - if (ret == 0) + if (ret != 0) { - internal_freq_fine.freq_fine = (uint8_t)val; - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_INTERNAL_FREQ_FINE, - (uint8_t *)&internal_freq_fine, 1); + return ret; } - return ret; -} - -/** - * @brief Difference in percentage of the effective ODR (and timestamp rate) - * with respect to the typical.[get] - * Step: 0.15%. 8-bit format, 2's complement. - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t ism330dhcx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) -{ - ism330dhcx_internal_freq_fine_t internal_freq_fine; - int32_t ret; - - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INTERNAL_FREQ_FINE, - (uint8_t *)&internal_freq_fine, 1); - *val = internal_freq_fine.freq_fine; + *val = (int8_t)internal_freq_fine.freq_fine; return ret; } @@ -2034,6 +2077,10 @@ int32_t ism330dhcx_mem_bank_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } switch (func_cfg_access.reg_access) { @@ -2069,71 +2116,7 @@ int32_t ism330dhcx_mem_bank_get(const stmdev_ctx_t *ctx, int32_t ism330dhcx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { - ism330dhcx_page_rw_t page_rw; - ism330dhcx_page_sel_t page_sel; - ism330dhcx_page_address_t page_address; - int32_t ret; - - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x02U; /* page_write enable */ - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - - if (ret == 0) - { - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_VALUE, val, 1); - } - - if (ret == 0) - { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } - - return ret; + return ism330dhcx_ln_pg_write(ctx, add, val, 1); } /** @@ -2157,98 +2140,105 @@ int32_t ism330dhcx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, int32_t ret; uint8_t i ; - msb = (uint8_t)((add / 256U) & 0x0FU); + msb = (uint8_t)((add >> 8) & 0x0FU); lsb = (uint8_t)(add - (msb * 256U)); - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK); - if (ret == 0) + ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK); + if (ret != 0) { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); + return ret; } - if (ret == 0) + /* set page write */ + ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, + (uint8_t *)&page_rw, 1); + if (ret != 0) { - page_rw.page_rw = 0x02U; /* page_write enable*/ - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } + page_rw.page_rw = 0x02U; /* page_write enable*/ + ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, + (uint8_t *)&page_rw, 1); - if (ret == 0) + /* select page */ + ret += ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - if (ret == 0) + /* set page addr */ + page_address.page_addr = lsb; + ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { - page_address.page_addr = lsb; - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + goto exit; } for (i = 0; i < len; i++) { - if (ret == 0) + ret += ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_VALUE, &buf[i], 1); + goto exit; + } - if (ret == 0) - { - /* Check if page wrap */ - if (lsb == 0x00U) - { - msb++; - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } + lsb++; - lsb++; + /* Check if page wrap */ + if (lsb == 0x00U) + { + msb++; + ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; // Default value + ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } } } - if (ret == 0) - { - page_sel.page_sel = 0; - page_sel.not_used_01 = 1; - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - - if (ret == 0) + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; // Default value + ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + /* unset page write */ + ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, + (uint8_t *)&page_rw, 1); + if (ret != 0) { - page_rw.page_rw = 0x00U; /* page_write disable */ - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } + page_rw.page_rw = 0x00U; /* page_write disable */ + ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, + (uint8_t *)&page_rw, 1); - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } +exit: + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -2271,63 +2261,67 @@ int32_t ism330dhcx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, int32_t ret; ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) + if (ret != 0) { - page_rw.page_rw = 0x01U; /* page_read enable*/ - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); + return ret; } - if (ret == 0) + /* set page write */ + ret += ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, + (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } + page_rw.page_rw = 0x01U; /* page_read enable*/ + ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, + (uint8_t *)&page_rw, 1); - if (ret == 0) + /* select page */ + ret += ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - - if (ret == 0) + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; // Default value + ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + goto exit; } - if (ret == 0) + /* set page addr */ + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_VALUE, val, 2); + goto exit; } - if (ret == 0) + /* read value */ + ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_VALUE, val, 2); + if (ret != 0) { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + /* unset page read */ + ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, + (uint8_t *)&page_rw, 1); + if (ret != 0) { - page_rw.page_rw = 0x00U; /* page_read disable */ - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } + page_rw.page_rw = 0x00U; /* page_read disable */ + ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, + (uint8_t *)&page_rw, 1); - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } +exit: + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -2377,6 +2371,10 @@ int32_t ism330dhcx_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } switch (counter_bdr_reg1.dataready_pulsed) { @@ -2454,6 +2452,11 @@ int32_t ism330dhcx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.sw_reset; return ret; @@ -2502,6 +2505,11 @@ int32_t ism330dhcx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.if_inc; return ret; @@ -2548,6 +2556,11 @@ int32_t ism330dhcx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.boot; return ret; @@ -2598,6 +2611,10 @@ int32_t ism330dhcx_xl_self_test_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_xl) { @@ -2664,6 +2681,10 @@ int32_t ism330dhcx_gy_self_test_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_g) { @@ -2741,6 +2762,11 @@ int32_t ism330dhcx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl1_xl.lpf2_xl_en; return ret; @@ -2789,6 +2815,11 @@ int32_t ism330dhcx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.lpf1_sel_g; return ret; @@ -2837,6 +2868,11 @@ int32_t ism330dhcx_drdy_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.drdy_mask; return ret; @@ -2885,6 +2921,10 @@ int32_t ism330dhcx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.ftype) { @@ -2969,6 +3009,11 @@ int32_t ism330dhcx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.low_pass_on_6d; return ret; @@ -3021,6 +3066,10 @@ int32_t ism330dhcx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) + @@ -3173,6 +3222,11 @@ int32_t ism330dhcx_xl_fast_settling_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.fastsettl_mode_xl; return ret; @@ -3187,8 +3241,8 @@ int32_t ism330dhcx_xl_fast_settling_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_hp_slope_filter_set(const stmdev_ctx_t *ctx, - ism330dhcx_slope_fds_t val) +int32_t ism330dhcx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, + ism330dhcx_slope_fds_t val) { ism330dhcx_tap_cfg0_t tap_cfg0; int32_t ret; @@ -3215,14 +3269,18 @@ int32_t ism330dhcx_xl_hp_slope_filter_set(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_hp_slope_filter_get(const stmdev_ctx_t *ctx, - ism330dhcx_slope_fds_t *val) +int32_t ism330dhcx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, + ism330dhcx_slope_fds_t *val) { ism330dhcx_tap_cfg0_t tap_cfg0; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } switch (tap_cfg0.slope_fds) { @@ -3251,8 +3309,8 @@ int32_t ism330dhcx_xl_hp_slope_filter_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_hp_filter_set(const stmdev_ctx_t *ctx, - ism330dhcx_hpm_g_t val) +int32_t ism330dhcx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, + ism330dhcx_hpm_g_t val) { ism330dhcx_ctrl7_g_t ctrl7_g; int32_t ret; @@ -3280,14 +3338,18 @@ int32_t ism330dhcx_gy_hp_filter_set(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_hp_filter_get(const stmdev_ctx_t *ctx, - ism330dhcx_hpm_g_t *val) +int32_t ism330dhcx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, + ism330dhcx_hpm_g_t *val) { ism330dhcx_ctrl7_g_t ctrl7_g; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g) { @@ -3377,6 +3439,10 @@ int32_t ism330dhcx_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch (pin_ctrl.ois_pu_dis) { @@ -3440,6 +3506,10 @@ int32_t ism330dhcx_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl7_g.ois_on) { @@ -3494,6 +3564,11 @@ int32_t ism330dhcx_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_SPIAUX, (uint8_t *)&status_spiaux, 1); + if (ret != 0) + { + return ret; + } + *val = status_spiaux.xlda; return ret; @@ -3515,6 +3590,11 @@ int32_t ism330dhcx_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_SPIAUX, (uint8_t *)&status_spiaux, 1); + if (ret != 0) + { + return ret; + } + *val = status_spiaux.gda; return ret; @@ -3536,6 +3616,11 @@ int32_t ism330dhcx_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_STATUS_SPIAUX, (uint8_t *)&status_spiaux, 1); + if (ret != 0) + { + return ret; + } + *val = status_spiaux.gyro_settling; return ret; @@ -3586,6 +3671,10 @@ int32_t ism330dhcx_aux_xl_self_test_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t *)&int_ois, 1); + if (ret != 0) + { + return ret; + } switch (int_ois.st_xl_ois) { @@ -3652,6 +3741,10 @@ int32_t ism330dhcx_aux_den_polarity_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t *)&int_ois, 1); + if (ret != 0) + { + return ret; + } switch (int_ois.den_lh_ois) { @@ -3730,10 +3823,12 @@ int32_t ism330dhcx_aux_den_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t *)&int_ois, 1); - if (ret == 0) + ret += ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS, + (uint8_t *)&ctrl1_ois, 1); + + if (ret != 0) { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); + return ret; } switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) @@ -3803,6 +3898,11 @@ int32_t ism330dhcx_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_OIS, (uint8_t *)&int_ois, 1); + if (ret != 0) + { + return ret; + } + *val = int_ois.int2_drdy_ois; return ret; @@ -3863,6 +3963,10 @@ int32_t ism330dhcx_aux_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2)) { @@ -3930,6 +4034,10 @@ int32_t ism330dhcx_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl1_ois.fs_125_ois << 2) + ctrl1_ois.fs_g_ois) { @@ -4004,6 +4112,10 @@ int32_t ism330dhcx_aux_spi_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1_ois.sim_ois) { @@ -4031,8 +4143,8 @@ int32_t ism330dhcx_aux_spi_mode_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_lp1_filter_set(const stmdev_ctx_t *ctx, - ism330dhcx_ftype_ois_t val) +int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + ism330dhcx_ftype_ois_t val) { ism330dhcx_ctrl2_ois_t ctrl2_ois; int32_t ret; @@ -4058,14 +4170,18 @@ int32_t ism330dhcx_aux_gy_lp1_filter_set(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_lp1_filter_get(const stmdev_ctx_t *ctx, - ism330dhcx_ftype_ois_t *val) +int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + ism330dhcx_ftype_ois_t *val) { ism330dhcx_ctrl2_ois_t ctrl2_ois; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2_ois.ftype_ois) { @@ -4101,8 +4217,8 @@ int32_t ism330dhcx_aux_gy_lp1_filter_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_hp_filter_set(const stmdev_ctx_t *ctx, - ism330dhcx_hpm_ois_t val) +int32_t ism330dhcx_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, + ism330dhcx_hpm_ois_t val) { ism330dhcx_ctrl2_ois_t ctrl2_ois; int32_t ret; @@ -4129,14 +4245,18 @@ int32_t ism330dhcx_aux_gy_hp_filter_set(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_hp_filter_get(const stmdev_ctx_t *ctx, - ism330dhcx_hpm_ois_t *val) +int32_t ism330dhcx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, + ism330dhcx_hpm_ois_t *val) { ism330dhcx_ctrl2_ois_t ctrl2_ois; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois) { @@ -4215,6 +4335,10 @@ int32_t ism330dhcx_aux_gy_clamp_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_ois.st_ois_clampdis) { @@ -4277,6 +4401,10 @@ int32_t ism330dhcx_aux_gy_self_test_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_ois.st_ois) { @@ -4343,6 +4471,10 @@ int32_t ism330dhcx_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_ois.filter_xl_conf_ois) { @@ -4429,6 +4561,10 @@ int32_t ism330dhcx_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_ois.fs_xl_ois) { @@ -4512,6 +4648,10 @@ int32_t ism330dhcx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch (pin_ctrl.sdo_pu_en) { @@ -4574,6 +4714,10 @@ int32_t ism330dhcx_spi_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.sim) { @@ -4636,6 +4780,10 @@ int32_t ism330dhcx_i2c_interface_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4_c.i2c_disable) { @@ -4709,10 +4857,7 @@ int32_t ism330dhcx_pin_int1_route_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int1_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); if (ret == 0) { @@ -4841,10 +4986,7 @@ int32_t ism330dhcx_pin_int1_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int1_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); if (ret == 0) { @@ -4902,10 +5044,7 @@ int32_t ism330dhcx_pin_int2_route_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int2_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); if (ret == 0) { @@ -5032,10 +5171,7 @@ int32_t ism330dhcx_pin_int2_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int2_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); if (ret == 0) { @@ -5095,6 +5231,10 @@ int32_t ism330dhcx_pin_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.pp_od) { @@ -5157,6 +5297,10 @@ int32_t ism330dhcx_pin_polarity_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.h_lactive) { @@ -5217,6 +5361,11 @@ int32_t ism330dhcx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.int2_on_int1; return ret; @@ -5251,24 +5400,21 @@ int32_t ism330dhcx_int_notification_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, + (uint8_t *)&page_rw, 1); + } - if (ret == 0) - { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = ism330dhcx_write_reg(ctx, ISM330DHCX_PAGE_RW, + (uint8_t *)&page_rw, 1); + } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } return ret; @@ -5296,17 +5442,19 @@ int32_t ism330dhcx_int_notification_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, - (uint8_t *)&page_rw, 1); + if (ret == 0) + { + ret = ism330dhcx_read_reg(ctx, ISM330DHCX_PAGE_RW, + (uint8_t *)&page_rw, 1); + } + + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } - if (ret == 0) + if (ret != 0) { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir) @@ -5395,6 +5543,10 @@ int32_t ism330dhcx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } switch (wake_up_dur.wake_ths_w) { @@ -5457,6 +5609,11 @@ int32_t ism330dhcx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.wk_ths; return ret; @@ -5470,7 +5627,8 @@ int32_t ism330dhcx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_usr_off_on_wu_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, + uint8_t val) { ism330dhcx_wake_up_ths_t wake_up_ths; int32_t ret; @@ -5496,13 +5654,19 @@ int32_t ism330dhcx_xl_usr_off_on_wu_set(const stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_usr_off_on_wu_get(const stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, + uint8_t *val) { ism330dhcx_wake_up_ths_t wake_up_ths; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.usr_off_on_wu; return ret; @@ -5549,6 +5713,11 @@ int32_t ism330dhcx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.wake_dur; return ret; @@ -5608,6 +5777,11 @@ int32_t ism330dhcx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.sleep_g; return ret; @@ -5623,8 +5797,8 @@ int32_t ism330dhcx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_slp_status_route_set(const stmdev_ctx_t *ctx, - ism330dhcx_sleep_status_on_int_t val) +int32_t ism330dhcx_act_pin_notification_set(const stmdev_ctx_t *ctx, + ism330dhcx_sleep_status_on_int_t val) { ism330dhcx_tap_cfg0_t tap_cfg0; int32_t ret; @@ -5652,14 +5826,18 @@ int32_t ism330dhcx_slp_status_route_set(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_slp_status_route_get(const stmdev_ctx_t *ctx, - ism330dhcx_sleep_status_on_int_t *val) +int32_t ism330dhcx_act_pin_notification_get(const stmdev_ctx_t *ctx, + ism330dhcx_sleep_status_on_int_t *val) { ism330dhcx_tap_cfg0_t tap_cfg0; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } switch (tap_cfg0. sleep_status_on_int) { @@ -5722,6 +5900,11 @@ int32_t ism330dhcx_act_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg2.inact_en) { @@ -5790,6 +5973,11 @@ int32_t ism330dhcx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.sleep_dur; return ret; @@ -5816,7 +6004,8 @@ int32_t ism330dhcx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_detect_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_tap_detection_on_z_set(const stmdev_ctx_t *ctx, + uint8_t val) { ism330dhcx_tap_cfg0_t tap_cfg0; int32_t ret; @@ -5842,13 +6031,19 @@ int32_t ism330dhcx_tap_detect_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_detect_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_tap_detection_on_z_get(const stmdev_ctx_t *ctx, + uint8_t *val) { ism330dhcx_tap_cfg0_t tap_cfg0; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.tap_z_en; return ret; @@ -5862,7 +6057,8 @@ int32_t ism330dhcx_tap_detect_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_detect_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_tap_detection_on_y_set(const stmdev_ctx_t *ctx, + uint8_t val) { ism330dhcx_tap_cfg0_t tap_cfg0; int32_t ret; @@ -5888,13 +6084,19 @@ int32_t ism330dhcx_tap_detect_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_detect_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_tap_detection_on_y_get(const stmdev_ctx_t *ctx, + uint8_t *val) { ism330dhcx_tap_cfg0_t tap_cfg0; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.tap_y_en; return ret; @@ -5908,7 +6110,8 @@ int32_t ism330dhcx_tap_detect_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_detect_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_tap_detection_on_x_set(const stmdev_ctx_t *ctx, + uint8_t val) { ism330dhcx_tap_cfg0_t tap_cfg0; int32_t ret; @@ -5934,13 +6137,19 @@ int32_t ism330dhcx_tap_detect_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_detect_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_tap_detection_on_x_get(const stmdev_ctx_t *ctx, + uint8_t *val) { ism330dhcx_tap_cfg0_t tap_cfg0; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.tap_x_en; return ret; @@ -5988,6 +6197,11 @@ int32_t ism330dhcx_tap_threshold_x_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg1.tap_ths_x; return ret; @@ -6036,6 +6250,10 @@ int32_t ism330dhcx_tap_axis_priority_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) + { + return ret; + } switch (tap_cfg1.tap_priority) { @@ -6113,6 +6331,11 @@ int32_t ism330dhcx_tap_threshold_y_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg2.tap_ths_y; return ret; @@ -6160,6 +6383,11 @@ int32_t ism330dhcx_tap_threshold_z_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = tap_ths_6d.tap_ths_z; return ret; @@ -6214,6 +6442,11 @@ int32_t ism330dhcx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2, (uint8_t *)&int_dur2, 1); + if (ret != 0) + { + return ret; + } + *val = int_dur2.shock; return ret; @@ -6268,6 +6501,11 @@ int32_t ism330dhcx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2, (uint8_t *)&int_dur2, 1); + if (ret != 0) + { + return ret; + } + *val = int_dur2.quiet; return ret; @@ -6324,6 +6562,11 @@ int32_t ism330dhcx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_INT_DUR2, (uint8_t *)&int_dur2, 1); + if (ret != 0) + { + return ret; + } + *val = int_dur2.dur; return ret; @@ -6372,6 +6615,10 @@ int32_t ism330dhcx_tap_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } switch (wake_up_ths.single_double_tap) { @@ -6447,6 +6694,10 @@ int32_t ism330dhcx_6d_threshold_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } switch (tap_ths_6d.sixd_ths) { @@ -6515,6 +6766,11 @@ int32_t ism330dhcx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = tap_ths_6d.d4d_en; return ret; @@ -6576,6 +6832,10 @@ int32_t ism330dhcx_ff_threshold_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -6681,6 +6941,10 @@ int32_t ism330dhcx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FREE_FALL, (uint8_t *)&free_fall, 1); } + if (ret != 0) + { + return ret; + } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -6747,6 +7011,11 @@ int32_t ism330dhcx_fifo_watermark_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); ret += ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.wtm; *val = (*val * 256U) + fifo_ctrl1.wtm;; @@ -6761,7 +7030,8 @@ int32_t ism330dhcx_fifo_watermark_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_compr_init_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_compression_algo_init_set(const stmdev_ctx_t *ctx, + uint8_t val) { ism330dhcx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -6781,10 +7051,7 @@ int32_t ism330dhcx_fifo_compr_init_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_init_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -6798,7 +7065,8 @@ int32_t ism330dhcx_fifo_compr_init_set(const stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_compr_init_get(const stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_compression_algo_init_get(const stmdev_ctx_t *ctx, + uint8_t *val) { ism330dhcx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -6814,9 +7082,10 @@ int32_t ism330dhcx_fifo_compr_init_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_init_b.fifo_compr_init; - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -6850,10 +7119,7 @@ int32_t ism330dhcx_compression_algo_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); if (ret == 0) { @@ -6892,6 +7158,10 @@ int32_t ism330dhcx_compression_algo_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } switch ((fifo_ctrl2.fifo_compr_rt_en << 2) + fifo_ctrl2.uncoptr_rate) @@ -6932,7 +7202,8 @@ int32_t ism330dhcx_compression_algo_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_odr_chg_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val) { ism330dhcx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -6958,13 +7229,19 @@ int32_t ism330dhcx_fifo_odr_chg_batch_set(const stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_odr_chg_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val) { ism330dhcx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odrchg_en; return ret; @@ -6978,7 +7255,8 @@ int32_t ism330dhcx_fifo_odr_chg_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_compr_rt_en_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_compression_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val) { ism330dhcx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -7004,13 +7282,19 @@ int32_t ism330dhcx_fifo_compr_rt_en_set(const stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_compr_rt_en_get(const stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_compression_algo_real_time_get(const stmdev_ctx_t *ctx, + uint8_t *val) { ism330dhcx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.fifo_compr_rt_en; return ret; @@ -7061,6 +7345,11 @@ int32_t ism330dhcx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -7111,6 +7400,10 @@ int32_t ism330dhcx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_xl) { @@ -7215,6 +7508,10 @@ int32_t ism330dhcx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_gy) { @@ -7317,6 +7614,10 @@ int32_t ism330dhcx_fifo_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.fifo_mode) { @@ -7397,6 +7698,10 @@ int32_t ism330dhcx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.odr_t_batch) { @@ -7434,8 +7739,8 @@ int32_t ism330dhcx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_ts_dec_set(const stmdev_ctx_t *ctx, - ism330dhcx_odr_ts_batch_t val) +int32_t ism330dhcx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, + ism330dhcx_odr_ts_batch_t val) { ism330dhcx_fifo_ctrl4_t fifo_ctrl4; int32_t ret; @@ -7464,14 +7769,18 @@ int32_t ism330dhcx_fifo_ts_dec_set(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_ts_dec_get(const stmdev_ctx_t *ctx, - ism330dhcx_odr_ts_batch_t *val) +int32_t ism330dhcx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, + ism330dhcx_odr_ts_batch_t *val) { ism330dhcx_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.odr_ts_batch) { @@ -7509,8 +7818,8 @@ int32_t ism330dhcx_fifo_ts_dec_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_trig_cnt_bdr_set(const stmdev_ctx_t *ctx, - ism330dhcx_trig_counter_bdr_t val) +int32_t ism330dhcx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, + ism330dhcx_trig_counter_bdr_t val) { ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; @@ -7538,14 +7847,18 @@ int32_t ism330dhcx_fifo_trig_cnt_bdr_set(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_trig_cnt_bdr_get(const stmdev_ctx_t *ctx, - ism330dhcx_trig_counter_bdr_t *val) +int32_t ism330dhcx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, + ism330dhcx_trig_counter_bdr_t *val) { ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } switch (counter_bdr_reg1.trig_counter_bdr) { @@ -7610,6 +7923,11 @@ int32_t ism330dhcx_rst_batch_counter_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + *val = counter_bdr_reg1.rst_counter_bdr; return ret; @@ -7624,7 +7942,8 @@ int32_t ism330dhcx_rst_batch_counter_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_batch_counter_th_set(const stmdev_ctx_t *ctx, uint16_t val) +int32_t ism330dhcx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val) { ism330dhcx_counter_bdr_reg2_t counter_bdr_reg1; ism330dhcx_counter_bdr_reg2_t counter_bdr_reg2; @@ -7660,7 +7979,8 @@ int32_t ism330dhcx_batch_counter_th_set(const stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_batch_counter_th_get(const stmdev_ctx_t *ctx, uint16_t *val) +int32_t ism330dhcx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val) { ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1; ism330dhcx_counter_bdr_reg2_t counter_bdr_reg2; @@ -7669,10 +7989,12 @@ int32_t ism330dhcx_batch_counter_th_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); - if (ret == 0) + ret += ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + + if (ret != 0) { - ret = ism330dhcx_read_reg(ctx, ISM330DHCX_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); + return ret; } *val = counter_bdr_reg1.cnt_bdr_th; @@ -7693,18 +8015,16 @@ int32_t ism330dhcx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t reg[2]; - ism330dhcx_fifo_status1_t fifo_status1; - ism330dhcx_fifo_status2_t fifo_status2; + ism330dhcx_fifo_status1_t *fifo_status1 = (ism330dhcx_fifo_status1_t *)®[0]; + ism330dhcx_fifo_status2_t *fifo_status2 = (ism330dhcx_fifo_status2_t *)®[1]; int32_t ret; /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS1, (uint8_t *)reg, 2); if (ret == 0) { - bytecpy((uint8_t *)&fifo_status1, ®[0]); - bytecpy((uint8_t *)&fifo_status2, ®[1]); - *val = fifo_status2.diff_fifo; - *val = (*val * 256U) + fifo_status1.diff_fifo; + *val = fifo_status2->diff_fifo; + *val = (*val * 256U) + fifo_status1->diff_fifo; } return ret; @@ -7722,15 +8042,14 @@ int32_t ism330dhcx_fifo_status_get(const stmdev_ctx_t *ctx, ism330dhcx_fifo_status2_t *val) { uint8_t reg[2]; - ism330dhcx_fifo_status2_t fifo_status2; + ism330dhcx_fifo_status2_t *fifo_status2 = (ism330dhcx_fifo_status2_t *)®[1]; int32_t ret; /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS1, (uint8_t *)reg, 2); if (ret == 0) { - bytecpy((uint8_t *)&fifo_status2, ®[1]); - *val = fifo_status2; + *val = *fifo_status2; } return ret; @@ -7747,15 +8066,14 @@ int32_t ism330dhcx_fifo_status_get(const stmdev_ctx_t *ctx, int32_t ism330dhcx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { uint8_t reg[2]; - ism330dhcx_fifo_status2_t fifo_status2; + ism330dhcx_fifo_status2_t *fifo_status2 = (ism330dhcx_fifo_status2_t *)®[1]; int32_t ret; /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS1, (uint8_t *)reg, 2); if (ret == 0) { - bytecpy((uint8_t *)&fifo_status2, ®[1]); - *val = fifo_status2.fifo_full_ia; + *val = fifo_status2->fifo_full_ia; } return ret; @@ -7773,15 +8091,14 @@ int32_t ism330dhcx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ism330dhcx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { uint8_t reg[2]; - ism330dhcx_fifo_status2_t fifo_status2; + ism330dhcx_fifo_status2_t *fifo_status2 = (ism330dhcx_fifo_status2_t *)®[1]; int32_t ret; /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS1, (uint8_t *)reg, 2); if (ret == 0) { - bytecpy((uint8_t *)&fifo_status2, ®[1]); - *val = fifo_status2.fifo_ovr_ia; + *val = fifo_status2->fifo_ovr_ia; } return ret; @@ -7798,15 +8115,14 @@ int32_t ism330dhcx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ism330dhcx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { uint8_t reg[2]; - ism330dhcx_fifo_status2_t fifo_status2; + ism330dhcx_fifo_status2_t *fifo_status2 = (ism330dhcx_fifo_status2_t *)®[1]; int32_t ret; /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */ ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_STATUS1, (uint8_t *)reg, 2); if (ret == 0) { - bytecpy((uint8_t *)&fifo_status2, ®[1]); - *val = fifo_status2.fifo_wtm_ia; + *val = fifo_status2->fifo_wtm_ia; } return ret; @@ -7828,6 +8144,10 @@ int32_t ism330dhcx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_data_out_tag, 1); + if (ret != 0) + { + return ret; + } switch (fifo_data_out_tag.tag_sensor) { @@ -7903,18 +8223,6 @@ int32_t ism330dhcx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, *val = ISM330DHCX_STEP_CPUNTER_TAG; break; - case ISM330DHCX_GAME_ROTATION_TAG: - *val = ISM330DHCX_GAME_ROTATION_TAG; - break; - - case ISM330DHCX_GEOMAG_ROTATION_TAG: - *val = ISM330DHCX_GEOMAG_ROTATION_TAG; - break; - - case ISM330DHCX_ROTATION_TAG: - *val = ISM330DHCX_ROTATION_TAG; - break; - case ISM330DHCX_SENSORHUB_NACK_TAG: *val = ISM330DHCX_SENSORHUB_NACK_TAG; break; @@ -7956,10 +8264,7 @@ int32_t ism330dhcx_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_fifo_cfg, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -7988,10 +8293,7 @@ int32_t ism330dhcx_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, *val = emb_func_fifo_cfg.pedo_fifo_en; } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -8025,10 +8327,7 @@ int32_t ism330dhcx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -8059,9 +8358,10 @@ int32_t ism330dhcx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = slv0_config. batch_ext_sens_0_en; - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -8095,10 +8395,7 @@ int32_t ism330dhcx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -8124,14 +8421,15 @@ int32_t ism330dhcx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, { ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); - *val = slv1_config. batch_ext_sens_1_en; } if (ret == 0) { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + *val = slv1_config. batch_ext_sens_1_en; } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -8165,10 +8463,7 @@ int32_t ism330dhcx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -8199,9 +8494,10 @@ int32_t ism330dhcx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = slv2_config. batch_ext_sens_2_en; - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -8235,10 +8531,7 @@ int32_t ism330dhcx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -8264,14 +8557,15 @@ int32_t ism330dhcx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, { ret = ism330dhcx_read_reg(ctx, ISM330DHCX_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); - *val = slv3_config. batch_ext_sens_3_en; } if (ret == 0) { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + *val = slv3_config. batch_ext_sens_3_en; } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -8331,6 +8625,10 @@ int32_t ism330dhcx_den_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.den_mode) { @@ -8405,6 +8703,10 @@ int32_t ism330dhcx_den_polarity_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_lh) { @@ -8467,6 +8769,10 @@ int32_t ism330dhcx_den_enable_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_xl_g) { @@ -8532,6 +8838,11 @@ int32_t ism330dhcx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_z; return ret; @@ -8579,6 +8890,11 @@ int32_t ism330dhcx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_y; return ret; @@ -8602,7 +8918,7 @@ int32_t ism330dhcx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) if (ret == 0) { - ctrl9_xl.den_x = (uint8_t)val; + ctrl9_xl.den_z = (uint8_t)val; ret = ism330dhcx_write_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); } @@ -8626,7 +8942,12 @@ int32_t ism330dhcx_den_mark_axis_z_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_read_reg(ctx, ISM330DHCX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - *val = ctrl9_xl.den_x; + if (ret != 0) + { + return ret; + } + + *val = ctrl9_xl.den_z; return ret; } @@ -8671,10 +8992,7 @@ int32_t ism330dhcx_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_a, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -8698,14 +9016,15 @@ int32_t ism330dhcx_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = ism330dhcx_read_reg(ctx, ISM330DHCX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - *val = emb_func_en_a.pedo_en; } if (ret == 0) { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + *val = emb_func_en_a.pedo_en; } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -8732,10 +9051,7 @@ int32_t ism330dhcx_pedo_step_detect_get(const stmdev_ctx_t *ctx, *val = emb_func_status.is_step_det; } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -8748,7 +9064,8 @@ int32_t ism330dhcx_pedo_step_detect_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pedo_deb_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ism330dhcx_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, + uint8_t *buff) { int32_t ret; @@ -8766,7 +9083,8 @@ int32_t ism330dhcx_pedo_deb_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pedo_deb_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ism330dhcx_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, + uint8_t *buff) { int32_t ret; @@ -8825,8 +9143,11 @@ int32_t ism330dhcx_pedo_steps_period_get(const stmdev_ctx_t *ctx, { ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_SC_DELTAT_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -8877,6 +9198,10 @@ int32_t ism330dhcx_pedo_int_mode_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg); + if (ret != 0) + { + return ret; + } switch (pedo_cmd_reg.carry_count_en) { @@ -8937,10 +9262,7 @@ int32_t ism330dhcx_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_a, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -8969,9 +9291,10 @@ int32_t ism330dhcx_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_en_a.sign_motion_en; - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -9000,9 +9323,10 @@ int32_t ism330dhcx_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_sigmot; - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -9047,10 +9371,7 @@ int32_t ism330dhcx_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_a, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -9079,9 +9400,10 @@ int32_t ism330dhcx_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_en_a.tilt_en; - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -9110,9 +9432,10 @@ int32_t ism330dhcx_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_tilt; - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -9174,14 +9497,16 @@ int32_t ism330dhcx_mag_sensitivity_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SENSITIVITY_L, &buff[0]); - if (ret == 0) + ret += ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SENSITIVITY_H, + &buff[1]); + if (ret != 0) { - ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_SENSITIVITY_H, - &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + return ret; } + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + return ret; } @@ -9286,7 +9611,10 @@ int32_t ism330dhcx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { i++; ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_OFFZ_H, &buff[i]); + } + if (ret == 0) + { val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -9513,18 +9841,21 @@ int32_t ism330dhcx_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) &buff[i]); } - val[0] = buff[1]; - val[0] = (val[0] * 256U) + buff[0]; - val[1] = buff[3]; - val[1] = (val[1] * 256U) + buff[2]; - val[2] = buff[5]; - val[2] = (val[2] * 256U) + buff[4]; - val[3] = buff[7]; - val[3] = (val[3] * 256U) + buff[6]; - val[4] = buff[9]; - val[4] = (val[4] * 256U) + buff[8]; - val[5] = buff[11]; - val[6] = (val[5] * 256U) + buff[10]; + if (ret == 0) + { + val[0] = buff[1]; + val[0] = (val[0] * 256U) + buff[0]; + val[1] = buff[3]; + val[1] = (val[1] * 256U) + buff[2]; + val[2] = buff[5]; + val[2] = (val[2] * 256U) + buff[4]; + val[3] = buff[7]; + val[3] = (val[3] * 256U) + buff[6]; + val[4] = buff[9]; + val[4] = (val[4] * 256U) + buff[8]; + val[5] = buff[11]; + val[6] = (val[5] * 256U) + buff[10]; + } return ret; } @@ -9574,6 +9905,10 @@ int32_t ism330dhcx_mag_z_orient_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_A, (uint8_t *)&mag_cfg_a); + if (ret != 0) + { + return ret; + } switch (mag_cfg_a.mag_z_axis) { @@ -9655,6 +9990,10 @@ int32_t ism330dhcx_mag_y_orient_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_A, (uint8_t *)&mag_cfg_a); + if (ret != 0) + { + return ret; + } switch (mag_cfg_a.mag_y_axis) { @@ -9735,6 +10074,10 @@ int32_t ism330dhcx_mag_x_orient_get(const stmdev_ctx_t *ctx, ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MAG_CFG_B, (uint8_t *)&mag_cfg_b); + if (ret != 0) + { + return ret; + } switch (mag_cfg_b.mag_x_axis) { @@ -9809,9 +10152,10 @@ int32_t ism330dhcx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_fsm_lc; - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -9843,10 +10187,7 @@ int32_t ism330dhcx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -9879,10 +10220,7 @@ int32_t ism330dhcx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -9955,10 +10293,7 @@ int32_t ism330dhcx_fsm_enable_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -9990,10 +10325,7 @@ int32_t ism330dhcx_fsm_enable_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_enable_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10022,10 +10354,7 @@ int32_t ism330dhcx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) 2); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10050,14 +10379,14 @@ int32_t ism330dhcx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FSM_LONG_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10092,10 +10421,7 @@ int32_t ism330dhcx_long_clr_set(const stmdev_ctx_t *ctx, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10122,9 +10448,11 @@ int32_t ism330dhcx_long_clr_get(const stmdev_ctx_t *ctx, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + + if (ret != 0) { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } switch (fsm_long_counter_clear.fsm_lc_clr) @@ -10170,10 +10498,7 @@ int32_t ism330dhcx_fsm_out_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_outs1, 16); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10209,10 +10534,7 @@ int32_t ism330dhcx_fsm_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10239,9 +10561,11 @@ int32_t ism330dhcx_fsm_data_rate_get(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + + if (ret != 0) { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } switch (emb_func_odr_cfg_b.fsm_odr) @@ -10298,10 +10622,7 @@ int32_t ism330dhcx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_init_b, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10330,9 +10651,10 @@ int32_t ism330dhcx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_init_b.fsm_init; - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -10347,7 +10669,8 @@ int32_t ism330dhcx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_lc_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) +int32_t ism330dhcx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, + uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -10377,7 +10700,8 @@ int32_t ism330dhcx_fsm_lc_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_lc_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) +int32_t ism330dhcx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, + uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -10389,8 +10713,11 @@ int32_t ism330dhcx_fsm_lc_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_LC_TIMEOUT_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -10404,19 +10731,13 @@ int32_t ism330dhcx_fsm_lc_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ism330dhcx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, + uint8_t *buff) { int32_t ret; ret = ism330dhcx_ln_pg_write_byte(ctx, ISM330DHCX_FSM_PROGRAMS, buff); - if (ret == 0) - { - ret = ism330dhcx_ln_pg_write_byte(ctx, - ISM330DHCX_FSM_PROGRAMS + 0x01U, - buff); - } - return ret; } @@ -10428,7 +10749,8 @@ int32_t ism330dhcx_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ism330dhcx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, + uint8_t *buff) { int32_t ret; @@ -10488,8 +10810,11 @@ int32_t ism330dhcx_fsm_start_address_get(const stmdev_ctx_t *ctx, { ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_FSM_START_ADD_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -10550,10 +10875,7 @@ int32_t ism330dhcx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) } } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10581,10 +10903,11 @@ int32_t ism330dhcx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - *val = reg.mlc_en; + *val = reg.mlc_en; } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -10631,10 +10954,7 @@ int32_t ism330dhcx_mlc_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10686,9 +11006,10 @@ int32_t ism330dhcx_mlc_data_rate_get(const stmdev_ctx_t *ctx, break; } - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -10710,10 +11031,7 @@ int32_t ism330dhcx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) ret = ism330dhcx_read_reg(ctx, ISM330DHCX_MLC0_SRC, buff, 8); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10767,8 +11085,11 @@ int32_t ism330dhcx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, { ret = ism330dhcx_ln_pg_read_byte(ctx, ISM330DHCX_MLC_MAG_SENSITIVITY_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -10795,8 +11116,7 @@ int32_t ism330dhcx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, - ism330dhcx_emb_sh_read_t *val, +int32_t ism330dhcx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len) { int32_t ret; @@ -10809,10 +11129,7 @@ int32_t ism330dhcx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, (uint8_t *)val, len); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10846,10 +11163,7 @@ int32_t ism330dhcx_sh_slave_connected_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10876,9 +11190,11 @@ int32_t ism330dhcx_sh_slave_connected_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + + if (ret != 0) { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } switch (master_config.aux_sens_on) @@ -10935,10 +11251,7 @@ int32_t ism330dhcx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -10967,9 +11280,10 @@ int32_t ism330dhcx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = master_config.master_on; - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -11002,10 +11316,7 @@ int32_t ism330dhcx_sh_pin_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11032,9 +11343,11 @@ int32_t ism330dhcx_sh_pin_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + + if (ret != 0) { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } switch (master_config.shub_pu_en) @@ -11083,10 +11396,7 @@ int32_t ism330dhcx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11116,9 +11426,10 @@ int32_t ism330dhcx_sh_pass_through_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = master_config.pass_through_mode; - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } @@ -11151,10 +11462,7 @@ int32_t ism330dhcx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11181,9 +11489,11 @@ int32_t ism330dhcx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + + if (ret != 0) { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } switch (master_config.start_config) @@ -11234,10 +11544,7 @@ int32_t ism330dhcx_sh_write_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11265,10 +11572,7 @@ int32_t ism330dhcx_sh_write_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); switch (master_config.write_once) { @@ -11322,10 +11626,7 @@ int32_t ism330dhcx_sh_reset_set(const stmdev_ctx_t *ctx) (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11352,10 +11653,7 @@ int32_t ism330dhcx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) *val = master_config.rst_master_regs; } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11389,10 +11687,7 @@ int32_t ism330dhcx_sh_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11419,9 +11714,11 @@ int32_t ism330dhcx_sh_data_rate_get(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + + if (ret != 0) { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); + return ret; } switch (slv0_config.shub_odr) @@ -11489,10 +11786,7 @@ int32_t ism330dhcx_sh_cfg_write(const stmdev_ctx_t *ctx, (uint8_t *) & (val->slv0_data), 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11544,10 +11838,7 @@ int32_t ism330dhcx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11599,10 +11890,7 @@ int32_t ism330dhcx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11654,10 +11942,7 @@ int32_t ism330dhcx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11709,10 +11994,7 @@ int32_t ism330dhcx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11738,10 +12020,7 @@ int32_t ism330dhcx_sh_status_get(const stmdev_ctx_t *ctx, (uint8_t *)val, 1); } - if (ret == 0) - { - ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); - } + ret += ism330dhcx_mem_bank_set(ctx, ISM330DHCX_USER_BANK); return ret; } @@ -11756,4 +12035,3 @@ int32_t ism330dhcx_sh_status_get(const stmdev_ctx_t *ctx, * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h index 487602c..2e75c39 100644 --- a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h +++ b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -131,11 +133,6 @@ typedef struct #endif /* MEMS_SHARED_TYPES */ -/** - * @} - * - */ - /** @defgroup ISM330DHCX Infos * @{ * @@ -2683,7 +2680,7 @@ int32_t ism330dhcx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); int32_t ism330dhcx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, - const uint8_t *data, + uint8_t *data, uint16_t len); float_t ism330dhcx_from_fs2g_to_mg(int16_t lsb); @@ -2874,11 +2871,12 @@ int32_t ism330dhcx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); int32_t ism330dhcx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *val); + int32_t ism330dhcx_device_conf_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t ism330dhcx_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); int32_t ism330dhcx_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); @@ -3014,10 +3012,10 @@ typedef enum ISM330DHCX_USE_SLOPE = 0, ISM330DHCX_USE_HPF = 1, } ism330dhcx_slope_fds_t; -int32_t ism330dhcx_xl_hp_slope_filter_set(const stmdev_ctx_t *ctx, - ism330dhcx_slope_fds_t val); -int32_t ism330dhcx_xl_hp_slope_filter_get(const stmdev_ctx_t *ctx, - ism330dhcx_slope_fds_t *val); +int32_t ism330dhcx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, + ism330dhcx_slope_fds_t val); +int32_t ism330dhcx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, + ism330dhcx_slope_fds_t *val); typedef enum { @@ -3027,10 +3025,10 @@ typedef enum ISM330DHCX_HP_FILTER_260mHz = 0x82, ISM330DHCX_HP_FILTER_1Hz04 = 0x83, } ism330dhcx_hpm_g_t; -int32_t ism330dhcx_gy_hp_filter_set(const stmdev_ctx_t *ctx, - ism330dhcx_hpm_g_t val); -int32_t ism330dhcx_gy_hp_filter_get(const stmdev_ctx_t *ctx, - ism330dhcx_hpm_g_t *val); +int32_t ism330dhcx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, + ism330dhcx_hpm_g_t val); +int32_t ism330dhcx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, + ism330dhcx_hpm_g_t *val); typedef enum { @@ -3140,10 +3138,10 @@ typedef enum ISM330DHCX_172Hz70 = 2, ISM330DHCX_937Hz91 = 3, } ism330dhcx_ftype_ois_t; -int32_t ism330dhcx_aux_gy_lp1_filter_set(const stmdev_ctx_t *ctx, - ism330dhcx_ftype_ois_t val); -int32_t ism330dhcx_aux_gy_lp1_filter_get(const stmdev_ctx_t *ctx, - ism330dhcx_ftype_ois_t *val); +int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + ism330dhcx_ftype_ois_t val); +int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + ism330dhcx_ftype_ois_t *val); typedef enum { @@ -3153,10 +3151,10 @@ typedef enum ISM330DHCX_AUX_HP_Hz260 = 0x12, ISM330DHCX_AUX_HP_1Hz040 = 0x13, } ism330dhcx_hpm_ois_t; -int32_t ism330dhcx_aux_gy_hp_filter_set(const stmdev_ctx_t *ctx, - ism330dhcx_hpm_ois_t val); -int32_t ism330dhcx_aux_gy_hp_filter_get(const stmdev_ctx_t *ctx, - ism330dhcx_hpm_ois_t *val); +int32_t ism330dhcx_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, + ism330dhcx_hpm_ois_t val); +int32_t ism330dhcx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, + ism330dhcx_hpm_ois_t *val); typedef enum { @@ -3314,8 +3312,10 @@ int32_t ism330dhcx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t ism330dhcx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_xl_usr_off_on_wu_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_xl_usr_off_on_wu_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism330dhcx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, + uint8_t *val); int32_t ism330dhcx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t ism330dhcx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); @@ -3328,10 +3328,10 @@ typedef enum ISM330DHCX_DRIVE_SLEEP_CHG_EVENT = 0, ISM330DHCX_DRIVE_SLEEP_STATUS = 1, } ism330dhcx_sleep_status_on_int_t; -int32_t ism330dhcx_slp_status_route_set(const stmdev_ctx_t *ctx, - ism330dhcx_sleep_status_on_int_t val); -int32_t ism330dhcx_slp_status_route_get(const stmdev_ctx_t *ctx, - ism330dhcx_sleep_status_on_int_t *val); +int32_t ism330dhcx_act_pin_notification_set(const stmdev_ctx_t *ctx, + ism330dhcx_sleep_status_on_int_t val); +int32_t ism330dhcx_act_pin_notification_get(const stmdev_ctx_t *ctx, + ism330dhcx_sleep_status_on_int_t *val); typedef enum { @@ -3348,14 +3348,20 @@ int32_t ism330dhcx_act_mode_get(const stmdev_ctx_t *ctx, int32_t ism330dhcx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t ism330dhcx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_tap_detect_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tap_detect_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_tap_detection_on_z_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism330dhcx_tap_detection_on_z_get(const stmdev_ctx_t *ctx, + uint8_t *val); -int32_t ism330dhcx_tap_detect_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tap_detect_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_tap_detection_on_y_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism330dhcx_tap_detection_on_y_get(const stmdev_ctx_t *ctx, + uint8_t *val); -int32_t ism330dhcx_tap_detect_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tap_detect_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_tap_detection_on_x_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism330dhcx_tap_detection_on_x_get(const stmdev_ctx_t *ctx, + uint8_t *val); int32_t ism330dhcx_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); @@ -3444,8 +3450,10 @@ int32_t ism330dhcx_fifo_watermark_set(const stmdev_ctx_t *ctx, int32_t ism330dhcx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism330dhcx_fifo_compr_init_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_fifo_compr_init_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_compression_algo_init_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism330dhcx_compression_algo_init_get(const stmdev_ctx_t *ctx, + uint8_t *val); typedef enum { @@ -3460,11 +3468,15 @@ int32_t ism330dhcx_compression_algo_set(const stmdev_ctx_t *ctx, int32_t ism330dhcx_compression_algo_get(const stmdev_ctx_t *ctx, ism330dhcx_uncoptr_rate_t *val); -int32_t ism330dhcx_fifo_odr_chg_batch_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_fifo_odr_chg_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val); -int32_t ism330dhcx_fifo_compr_rt_en_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_fifo_compr_rt_en_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_compression_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism330dhcx_compression_algo_real_time_get(const stmdev_ctx_t *ctx, + uint8_t *val); int32_t ism330dhcx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); @@ -3544,28 +3556,30 @@ typedef enum ISM330DHCX_DEC_8 = 2, ISM330DHCX_DEC_32 = 3, } ism330dhcx_odr_ts_batch_t; -int32_t ism330dhcx_fifo_ts_dec_set(const stmdev_ctx_t *ctx, - ism330dhcx_odr_ts_batch_t val); -int32_t ism330dhcx_fifo_ts_dec_get(const stmdev_ctx_t *ctx, - ism330dhcx_odr_ts_batch_t *val); +int32_t ism330dhcx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, + ism330dhcx_odr_ts_batch_t val); +int32_t ism330dhcx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, + ism330dhcx_odr_ts_batch_t *val); typedef enum { ISM330DHCX_XL_BATCH_EVENT = 0, ISM330DHCX_GYRO_BATCH_EVENT = 1, } ism330dhcx_trig_counter_bdr_t; -int32_t ism330dhcx_fifo_trig_cnt_bdr_set(const stmdev_ctx_t *ctx, - ism330dhcx_trig_counter_bdr_t val); -int32_t ism330dhcx_fifo_trig_cnt_bdr_get(const stmdev_ctx_t *ctx, - ism330dhcx_trig_counter_bdr_t *val); +int32_t ism330dhcx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, + ism330dhcx_trig_counter_bdr_t val); +int32_t ism330dhcx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, + ism330dhcx_trig_counter_bdr_t *val); int32_t ism330dhcx_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t ism330dhcx_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_batch_counter_th_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t ism330dhcx_batch_counter_th_get(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t ism330dhcx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t ism330dhcx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val); int32_t ism330dhcx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); @@ -3600,9 +3614,6 @@ typedef enum ISM330DHCX_SENSORHUB_SLAVE2_TAG, ISM330DHCX_SENSORHUB_SLAVE3_TAG, ISM330DHCX_STEP_CPUNTER_TAG, - ISM330DHCX_GAME_ROTATION_TAG, - ISM330DHCX_GEOMAG_ROTATION_TAG, - ISM330DHCX_ROTATION_TAG, ISM330DHCX_SENSORHUB_NACK_TAG = 0x19, } ism330dhcx_fifo_tag_t; int32_t ism330dhcx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, @@ -3688,8 +3699,10 @@ int32_t ism330dhcx_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); int32_t ism330dhcx_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_pedo_deb_steps_set(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_pedo_deb_steps_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, + uint8_t *val); +int32_t ism330dhcx_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, + uint8_t *val); int32_t ism330dhcx_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val); @@ -3840,11 +3853,15 @@ int32_t ism330dhcx_fsm_data_rate_get(const stmdev_ctx_t *ctx, int32_t ism330dhcx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t ism330dhcx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_fsm_lc_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t ism330dhcx_fsm_lc_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t ism330dhcx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t ism330dhcx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, + uint16_t *val); -int32_t ism330dhcx_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, + uint8_t *val); +int32_t ism330dhcx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, + uint8_t *val); int32_t ism330dhcx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); @@ -3873,29 +3890,7 @@ int32_t ism330dhcx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); int32_t ism330dhcx_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); int32_t ism330dhcx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -typedef struct -{ - ism330dhcx_sensor_hub_1_t sh_byte_1; - ism330dhcx_sensor_hub_2_t sh_byte_2; - ism330dhcx_sensor_hub_3_t sh_byte_3; - ism330dhcx_sensor_hub_4_t sh_byte_4; - ism330dhcx_sensor_hub_5_t sh_byte_5; - ism330dhcx_sensor_hub_6_t sh_byte_6; - ism330dhcx_sensor_hub_7_t sh_byte_7; - ism330dhcx_sensor_hub_8_t sh_byte_8; - ism330dhcx_sensor_hub_9_t sh_byte_9; - ism330dhcx_sensor_hub_10_t sh_byte_10; - ism330dhcx_sensor_hub_11_t sh_byte_11; - ism330dhcx_sensor_hub_12_t sh_byte_12; - ism330dhcx_sensor_hub_13_t sh_byte_13; - ism330dhcx_sensor_hub_14_t sh_byte_14; - ism330dhcx_sensor_hub_15_t sh_byte_15; - ism330dhcx_sensor_hub_16_t sh_byte_16; - ism330dhcx_sensor_hub_17_t sh_byte_17; - ism330dhcx_sensor_hub_18_t sh_byte_18; -} ism330dhcx_emb_sh_read_t; -int32_t ism330dhcx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, - ism330dhcx_emb_sh_read_t *val, +int32_t ism330dhcx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len); typedef enum @@ -4001,4 +3996,3 @@ int32_t ism330dhcx_sh_status_get(const stmdev_ctx_t *ctx, #endif /* ISM330DHCX_REGS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c index 82ea4cd..3f5d055 100644 --- a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c +++ b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -204,6 +203,10 @@ int32_t ism330dlc_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1_xl.fs_xl) { @@ -272,6 +275,10 @@ int32_t ism330dlc_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1_xl.odr_xl) { @@ -370,6 +377,11 @@ int32_t ism330dlc_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2_g.fs_g) { case ISM330DLC_250dps: @@ -439,6 +451,11 @@ int32_t ism330dlc_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2_g.odr_g) { case ISM330DLC_GY_ODR_OFF: @@ -531,7 +548,10 @@ int32_t ism330dlc_block_data_update_get(const stmdev_ctx_t *ctx, ism330dlc_ctrl3_c_t ctrl3_c; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - *val = ctrl3_c.bdu; + if (ret == 0) + { + *val = ctrl3_c.bdu; + } return ret; } @@ -576,6 +596,10 @@ int32_t ism330dlc_xl_offset_weight_get(const stmdev_ctx_t *ctx, ism330dlc_ctrl6_c_t ctrl6_c; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.usr_off_w) { @@ -633,6 +657,10 @@ int32_t ism330dlc_xl_power_mode_get(const stmdev_ctx_t *ctx, ism330dlc_ctrl6_c_t ctrl6_c; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.xl_hm_mode) { @@ -694,6 +722,10 @@ int32_t ism330dlc_rounding_on_status_get(const stmdev_ctx_t *ctx, ism330dlc_ctrl7_g_t ctrl7_g; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl7_g.rounding_status) { @@ -751,6 +783,10 @@ int32_t ism330dlc_gy_power_mode_get(const stmdev_ctx_t *ctx, ism330dlc_ctrl7_g_t ctrl7_g; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl7_g.g_hm_mode) { @@ -855,7 +891,10 @@ int32_t ism330dlc_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG, (uint8_t *)&status_reg, 1); - *val = status_reg.xlda; + if (ret == 0) + { + *val = status_reg.xlda; + } return ret; } @@ -875,7 +914,10 @@ int32_t ism330dlc_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG, (uint8_t *)&status_reg, 1); - *val = status_reg.gda; + if (ret == 0) + { + *val = status_reg.gda; + } return ret; } @@ -895,13 +937,16 @@ int32_t ism330dlc_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_REG, (uint8_t *)&status_reg, 1); - *val = status_reg.tda; + if (ret == 0) + { + *val = status_reg.tda; + } return ret; } /** - * @brief Accelerometer axis user offset correction expressed in two’s + * @brief Accelerometer axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C. * The value must be in the range [-127 127].[set] * @@ -919,7 +964,7 @@ int32_t ism330dlc_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer axis user offset correction xpressed in two’s + * @brief Accelerometer axis user offset correction xpressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C. * The value must be in the range [-127 127].[get] * @@ -995,7 +1040,10 @@ int32_t ism330dlc_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - *val = ctrl10_c.timer_en; + if (ret == 0) + { + *val = ctrl10_c.timer_en; + } return ret; } @@ -1051,6 +1099,10 @@ int32_t ism330dlc_timestamp_res_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } switch (wake_up_dur.timer_hr) { @@ -1122,6 +1174,10 @@ int32_t ism330dlc_rounding_mode_get(const stmdev_ctx_t *ctx, ism330dlc_ctrl5_c_t ctrl5_c; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.rounding) { @@ -1167,7 +1223,7 @@ int32_t ism330dlc_rounding_mode_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers together - * express a 16-bit word in two’s complement.[get] + * express a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -1179,15 +1235,18 @@ int32_t ism330dlc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[2]; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_OUT_TEMP_L, buff, 2); - *val = (int16_t)buff[1]; - *val = (*val * 256) + (int16_t)buff[0]; + if (ret == 0) + { + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + } return ret; } /** * @brief Angular rate sensor. The value is expressed as a 16-bit word in - * two’s complement.[get] + * two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -1200,6 +1259,11 @@ int32_t ism330dlc_angular_rate_raw_get(const stmdev_ctx_t *ctx, uint8_t buff[6]; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_OUTX_L_G, buff, 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1212,7 +1276,7 @@ int32_t ism330dlc_angular_rate_raw_get(const stmdev_ctx_t *ctx, /** * @brief Linear acceleration output register. The value is expressed - * as a 16-bit word in two’s complement.[get] + * as a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -1225,6 +1289,11 @@ int32_t ism330dlc_acceleration_raw_get(const stmdev_ctx_t *ctx, uint8_t buff[6]; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_OUTX_L_XL, buff, 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1249,6 +1318,11 @@ int32_t ism330dlc_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, uint8_t buff[6]; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_OUT_MAG_RAW_X_L, buff, 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1333,6 +1407,10 @@ int32_t ism330dlc_mem_bank_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } switch (func_cfg_access.func_cfg_en) { @@ -1389,6 +1467,10 @@ int32_t ism330dlc_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_DRDY_PULSE_CFG, (uint8_t *)&drdy_pulse_cfg_g, 1); + if (ret != 0) + { + return ret; + } switch (drdy_pulse_cfg_g.drdy_pulsed) { @@ -1460,7 +1542,10 @@ int32_t ism330dlc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ism330dlc_ctrl3_c_t ctrl3_c; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - *val = ctrl3_c.sw_reset; + if (ret == 0) + { + *val = ctrl3_c.sw_reset; + } return ret; } @@ -1503,6 +1588,10 @@ int32_t ism330dlc_data_format_get(const stmdev_ctx_t *ctx, ism330dlc_ctrl3_c_t ctrl3_c; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.ble) { @@ -1560,7 +1649,10 @@ int32_t ism330dlc_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) ism330dlc_ctrl3_c_t ctrl3_c; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - *val = ctrl3_c.if_inc; + if (ret == 0) + { + *val = ctrl3_c.if_inc; + } return ret; } @@ -1601,7 +1693,10 @@ int32_t ism330dlc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ism330dlc_ctrl3_c_t ctrl3_c; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - *val = ctrl3_c.boot; + if (ret == 0) + { + *val = ctrl3_c.boot; + } return ret; } @@ -1645,6 +1740,11 @@ int32_t ism330dlc_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5_c.st_xl) { case ISM330DLC_XL_ST_DISABLE: @@ -1706,6 +1806,11 @@ int32_t ism330dlc_gy_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5_c.st_g) { case ISM330DLC_GY_ST_DISABLE: @@ -1781,7 +1886,11 @@ int32_t ism330dlc_filter_settling_mask_get(const stmdev_ctx_t *ctx, ism330dlc_ctrl4_c_t ctrl4_c; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - *val = ctrl4_c.drdy_mask; + + if (ret == 0) + { + *val = ctrl4_c.drdy_mask; + } return ret; } @@ -1827,6 +1936,11 @@ int32_t ism330dlc_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg.slope_fds) { case ISM330DLC_USE_SLOPE: @@ -1901,6 +2015,10 @@ int32_t ism330dlc_xl_filter_analog_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1_xl.bw0_xl) { @@ -2006,6 +2124,11 @@ int32_t ism330dlc_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl1_xl.lpf1_bw_sel) { case ISM330DLC_XL_LP1_ODR_DIV_2: @@ -2166,7 +2289,10 @@ int32_t ism330dlc_xl_reference_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); - *val = ctrl8_xl.hp_ref_mode; + if (ret == 0) + { + *val = ctrl8_xl.hp_ref_mode; + } return ret; } @@ -2215,6 +2341,11 @@ int32_t ism330dlc_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + if (ctrl8_xl.hp_slope_xl_en == 0x00U) { *val = ISM330DLC_XL_HP_NA; @@ -2334,6 +2465,11 @@ int32_t ism330dlc_xl_ui_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl1_xl.lpf1_bw_sel) { case ISM330DLC_XL_UI_LP1_ODR_DIV_2: @@ -2389,7 +2525,10 @@ int32_t ism330dlc_xl_ui_slope_get(const stmdev_ctx_t *ctx, uint8_t *val) ism330dlc_ctrl8_xl_t reg; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t *)®, 1); - *val = reg.hp_slope_xl_en; + if (ret == 0) + { + *val = reg.hp_slope_xl_en; + } return ret; } @@ -2458,6 +2597,10 @@ int32_t ism330dlc_xl_aux_lp_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_ctrl3_ois_t reg; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1); + if (ret != 0) + { + return ret; + } switch (reg.filter_xl_conf_ois) { @@ -2576,6 +2719,11 @@ int32_t ism330dlc_gy_band_pass_get(const stmdev_ctx_t *ctx, { ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) + (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype) { @@ -2689,7 +2837,10 @@ int32_t ism330dlc_gy_ui_high_pass_get(const stmdev_ctx_t *ctx, uint8_t *val) ism330dlc_ctrl7_g_t reg; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL7_G, (uint8_t *)®, 1); - *val = reg.hp_en_g; + if (ret == 0) + { + *val = reg.hp_en_g; + } return ret; } @@ -2754,6 +2905,11 @@ int32_t ism330dlc_gy_aux_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL2_OIS, (uint8_t *)®, 1); + if (ret != 0) + { + return ret; + } + switch ((reg.hp_en_ois << 7) + (reg.hpm_ois << 4) + reg.ftype_ois) { @@ -2843,7 +2999,10 @@ int32_t ism330dlc_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX, (uint8_t *)®, 1); - *val = reg.xlda; + if (ret == 0) + { + *val = reg.xlda; + } return ret; } @@ -2863,7 +3022,10 @@ int32_t ism330dlc_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX, (uint8_t *)®, 1); - *val = reg.gda; + if (ret == 0) + { + *val = reg.gda; + } return ret; } @@ -2883,7 +3045,10 @@ int32_t ism330dlc_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_STATUS_SPIAUX, (uint8_t *)®, 1); - *val = reg.gyro_settling; + if (ret == 0) + { + *val = reg.gyro_settling; + } return ret; } @@ -2949,6 +3114,11 @@ int32_t ism330dlc_aux_den_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&ctrl1_ois, 1); } + if (ret != 0) + { + return ret; + } + switch ((ctrl1_ois.lvl1_ois << 1) | int_ois.lvl2_ois) { case ISM330DLC_AUX_DEN_DISABLE: @@ -3010,7 +3180,10 @@ int32_t ism330dlc_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, ism330dlc_int_ois_t reg; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_OIS, (uint8_t *)®, 1); - *val = reg.int2_drdy_ois; + if (ret == 0) + { + *val = reg.int2_drdy_ois; + } return ret; } @@ -3069,6 +3242,11 @@ int32_t ism330dlc_aux_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1); + if (ret != 0) + { + return ret; + } + switch ((reg.mode4_en << 1) + reg.ois_en_spi2) { case ISM330DLC_AUX_DISABLE: @@ -3130,6 +3308,11 @@ int32_t ism330dlc_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1); + if (ret != 0) + { + return ret; + } + switch (reg.fs_g_ois) { case ISM330DLC_250dps_AUX: @@ -3199,6 +3382,11 @@ int32_t ism330dlc_aux_spi_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1); + if (ret != 0) + { + return ret; + } + switch (reg.sim_ois) { case ISM330DLC_AUX_SPI_4_WIRE: @@ -3256,6 +3444,11 @@ int32_t ism330dlc_aux_data_format_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL1_OIS, (uint8_t *)®, 1); + if (ret != 0) + { + return ret; + } + switch (reg.ble_ois) { case ISM330DLC_AUX_LSB_AT_LOW_ADD: @@ -3319,6 +3512,11 @@ int32_t ism330dlc_aux_gy_clamp_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1); + if (ret != 0) + { + return ret; + } + switch (reg.st_ois_clampdis) { case ISM330DLC_ENABLE_CLAMP: @@ -3376,6 +3574,11 @@ int32_t ism330dlc_aux_gy_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1); + if (ret != 0) + { + return ret; + } + switch (reg.st_ois) { case ISM330DLC_AUX_GY_DISABLE: @@ -3437,6 +3640,11 @@ int32_t ism330dlc_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1); + if (ret != 0) + { + return ret; + } + switch (reg.fs_xl_ois) { case ISM330DLC_AUX_2g: @@ -3502,6 +3710,11 @@ int32_t ism330dlc_aux_den_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_OIS, (uint8_t *)®, 1); + if (ret != 0) + { + return ret; + } + switch (reg.den_lh_ois) { case ISM330DLC_AUX_DEN_ACTIVE_LOW: @@ -3571,6 +3784,11 @@ int32_t ism330dlc_spi_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl3_c.sim) { case ISM330DLC_SPI_4_WIRE: @@ -3628,6 +3846,11 @@ int32_t ism330dlc_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl4_c.i2c_disable) { case ISM330DLC_I2C_ENABLE: @@ -3820,7 +4043,10 @@ int32_t ism330dlc_pin_int1_route_get(const stmdev_ctx_t *ctx, val->den_drdy_int1 = ctrl4_c.den_drdy_int1; ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG, (uint8_t *)&master_config, 1); - val->den_drdy_int1 = master_config.drdy_on_int1; + if (ret == 0) + { + val->den_drdy_int1 = master_config.drdy_on_int1; + } } } } @@ -4013,6 +4239,11 @@ int32_t ism330dlc_pin_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl3_c.pp_od) { case ISM330DLC_PUSH_PULL: @@ -4070,6 +4301,11 @@ int32_t ism330dlc_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl3_c.h_lactive) { case ISM330DLC_ACTIVE_HIGH: @@ -4124,7 +4360,10 @@ int32_t ism330dlc_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) ism330dlc_ctrl4_c_t ctrl4_c; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - *val = ctrl4_c.int2_on_int1; + if (ret == 0) + { + *val = ctrl4_c.int2_on_int1; + } return ret; } @@ -4168,6 +4407,11 @@ int32_t ism330dlc_int_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg.lir) { case ISM330DLC_INT_PULSED: @@ -4238,7 +4482,10 @@ int32_t ism330dlc_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); - *val = wake_up_ths.wk_ths; + if (ret == 0) + { + *val = wake_up_ths.wk_ths; + } return ret; } @@ -4282,7 +4529,10 @@ int32_t ism330dlc_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - *val = wake_up_dur.wake_dur; + if (ret == 0) + { + *val = wake_up_dur.wake_dur; + } return ret; } @@ -4336,7 +4586,10 @@ int32_t ism330dlc_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ism330dlc_ctrl4_c_t ctrl4_c; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - *val = ctrl4_c.sleep; + if (ret == 0) + { + *val = ctrl4_c.sleep; + } return ret; } @@ -4380,6 +4633,11 @@ int32_t ism330dlc_act_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg.inact_en) { case ISM330DLC_PROPERTY_DISABLE: @@ -4445,7 +4703,10 @@ int32_t ism330dlc_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - *val = wake_up_dur.sleep_dur; + if (ret == 0) + { + *val = wake_up_dur.sleep_dur; + } return ret; } @@ -4517,7 +4778,10 @@ int32_t ism330dlc_tap_detection_on_z_get(const stmdev_ctx_t *ctx, ism330dlc_tap_cfg_t tap_cfg; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1); - *val = tap_cfg.tap_z_en; + if (ret == 0) + { + *val = tap_cfg.tap_z_en; + } return ret; } @@ -4560,7 +4824,10 @@ int32_t ism330dlc_tap_detection_on_y_get(const stmdev_ctx_t *ctx, ism330dlc_tap_cfg_t tap_cfg; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1); - *val = tap_cfg.tap_y_en; + if (ret == 0) + { + *val = tap_cfg.tap_y_en; + } return ret; } @@ -4603,7 +4870,10 @@ int32_t ism330dlc_tap_detection_on_x_get(const stmdev_ctx_t *ctx, ism330dlc_tap_cfg_t tap_cfg; int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_CFG, (uint8_t *)&tap_cfg, 1); - *val = tap_cfg.tap_x_en; + if (ret == 0) + { + *val = tap_cfg.tap_x_en; + } return ret; } @@ -4647,7 +4917,10 @@ int32_t ism330dlc_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); - *val = tap_ths_6d.tap_ths; + if (ret == 0) + { + *val = tap_ths_6d.tap_ths; + } return ret; } @@ -4701,7 +4974,10 @@ int32_t ism330dlc_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2, (uint8_t *)&int_dur2, 1); - *val = int_dur2.shock; + if (ret == 0) + { + *val = int_dur2.shock; + } return ret; } @@ -4755,7 +5031,10 @@ int32_t ism330dlc_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2, (uint8_t *)&int_dur2, 1); - *val = int_dur2.quiet; + if (ret == 0) + { + *val = int_dur2.quiet; + } return ret; } @@ -4811,7 +5090,10 @@ int32_t ism330dlc_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_INT_DUR2, (uint8_t *)&int_dur2, 1); - *val = int_dur2.dur; + if (ret == 0) + { + *val = int_dur2.dur; + } return ret; } @@ -4858,6 +5140,11 @@ int32_t ism330dlc_tap_mode_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + switch (wake_up_ths.single_double_tap) { case ISM330DLC_ONLY_SINGLE: @@ -4931,6 +5218,11 @@ int32_t ism330dlc_6d_feed_data_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl8_xl.low_pass_on_6d) { case ISM330DLC_ODR_DIV_2_FEED: @@ -4991,6 +5283,11 @@ int32_t ism330dlc_6d_threshold_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + switch (tap_ths_6d.sixd_ths) { case ISM330DLC_DEG_80: @@ -5056,7 +5353,10 @@ int32_t ism330dlc_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); - *val = tap_ths_6d.d4d_en; + if (ret == 0) + { + *val = tap_ths_6d.d4d_en; + } return ret; } @@ -5135,7 +5435,10 @@ int32_t ism330dlc_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)&free_fall, 1); } - *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + if (ret == 0) + { + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + } return ret; } @@ -5182,6 +5485,11 @@ int32_t ism330dlc_ff_threshold_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } + switch (free_fall.ff_ths) { case ISM330DLC_FF_TSH_156mg: @@ -5292,8 +5600,11 @@ int32_t ism330dlc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) (uint8_t *)&fifo_ctrl2, 1); } - *val = fifo_ctrl2.fth; - *val = (*val * 256U) + fifo_ctrl1.fth; + if (ret == 0) + { + *val = fifo_ctrl2.fth; + *val = (*val * 256U) + fifo_ctrl1.fth; + } return ret; } @@ -5321,8 +5632,12 @@ int32_t ism330dlc_fifo_data_level_get(const stmdev_ctx_t *ctx, { ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); - *val = fifo_status2.diff_fifo; - *val = (*val * 256U) + fifo_status1.diff_fifo; + + if (ret == 0) + { + *val = fifo_status2.diff_fifo; + *val = (*val * 256U) + fifo_status1.diff_fifo; + } } return ret; @@ -5342,7 +5657,10 @@ int32_t ism330dlc_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); - *val = fifo_status2.waterm; + if (ret == 0) + { + *val = fifo_status2.waterm; + } return ret; } @@ -5368,8 +5686,11 @@ int32_t ism330dlc_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val) { ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_STATUS4, (uint8_t *)&fifo_status4, 1); - *val = fifo_status4.fifo_pattern; - *val = (*val * 256U) + fifo_status3.fifo_pattern; + if (ret == 0) + { + *val = fifo_status4.fifo_pattern; + *val = (*val * 256U) + fifo_status3.fifo_pattern; + } } return ret; @@ -5414,7 +5735,10 @@ int32_t ism330dlc_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - *val = fifo_ctrl2.fifo_temp_en; + if (ret == 0) + { + *val = fifo_ctrl2.fifo_temp_en; + } return ret; } @@ -5490,6 +5814,11 @@ int32_t ism330dlc_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl3.dec_fifo_xl) { case ISM330DLC_FIFO_XL_DISABLE: @@ -5576,6 +5905,11 @@ int32_t ism330dlc_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl3.dec_fifo_gyro) { case ISM330DLC_FIFO_GY_DISABLE: @@ -5662,6 +5996,11 @@ int32_t ism330dlc_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.dec_ds3_fifo) { case ISM330DLC_FIFO_DS3_DISABLE: @@ -5748,6 +6087,11 @@ int32_t ism330dlc_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.dec_ds4_fifo) { case ISM330DLC_FIFO_DS4_DISABLE: @@ -5831,7 +6175,10 @@ int32_t ism330dlc_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); - *val = fifo_ctrl4.only_high_data; + if (ret == 0) + { + *val = fifo_ctrl4.only_high_data; + } return ret; } @@ -5878,7 +6225,10 @@ int32_t ism330dlc_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); - *val = fifo_ctrl4.stop_on_fth; + if (ret == 0) + { + *val = fifo_ctrl4.stop_on_fth; + } return ret; } @@ -5925,6 +6275,11 @@ int32_t ism330dlc_fifo_mode_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL5, (uint8_t *)&fifo_ctrl5, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl5.fifo_mode) { case ISM330DLC_BYPASS_MODE: @@ -5997,6 +6352,11 @@ int32_t ism330dlc_fifo_data_rate_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_FIFO_CTRL5, (uint8_t *)&fifo_ctrl5, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl5.odr_fifo) { case ISM330DLC_FIFO_DISABLE: @@ -6103,6 +6463,11 @@ int32_t ism330dlc_den_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5_c.den_lh) { case ISM330DLC_DEN_ACT_LOW: @@ -6160,6 +6525,11 @@ int32_t ism330dlc_den_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl6_c.den_mode) { case ISM330DLC_DEN_DISABLE: @@ -6249,6 +6619,11 @@ int32_t ism330dlc_den_enable_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g) { case ISM330DLC_STAMP_IN_GY_DATA: @@ -6311,7 +6686,10 @@ int32_t ism330dlc_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - *val = ctrl9_xl.den_z; + if (ret == 0) + { + *val = ctrl9_xl.den_z; + } return ret; } @@ -6355,7 +6733,10 @@ int32_t ism330dlc_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - *val = ctrl9_xl.den_y; + if (ret == 0) + { + *val = ctrl9_xl.den_y; + } return ret; } @@ -6399,7 +6780,10 @@ int32_t ism330dlc_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - *val = ctrl9_xl.den_x; + if (ret == 0) + { + *val = ctrl9_xl.den_x; + } return ret; } @@ -6456,7 +6840,10 @@ int32_t ism330dlc_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - *val = ctrl9_xl.soft_en; + if (ret == 0) + { + *val = ctrl9_xl.soft_en; + } return ret; } @@ -6518,7 +6905,10 @@ int32_t ism330dlc_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG, (uint8_t *)&master_config, 1); - *val = master_config.iron_en; + if (ret == 0) + { + *val = master_config.iron_en; + } return ret; } @@ -6541,13 +6931,10 @@ int32_t ism330dlc_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330dlc_write_reg(ctx, ISM330DLC_MAG_SI_XX, buff, 9); - - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -6569,19 +6956,16 @@ int32_t ism330dlc_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = ism330dlc_read_reg(ctx, ISM330DLC_MAG_SI_XX, buff, 9); - - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } /** * @brief Offset for hard-iron compensation register (r/w). The value is - * expressed as a 16-bit word in two’s complement.[set] + * expressed as a 16-bit word in two's complement.[set] * * @param ctx Read / write interface definitions * @param buff Buffer that contains data to write @@ -6603,19 +6987,16 @@ int32_t ism330dlc_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) buff[5] = (uint8_t)((uint16_t)val[2] / 256U); buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U)); ret = ism330dlc_write_reg(ctx, ISM330DLC_MAG_OFFX_L, buff, 6); - - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } /** * @brief Offset for hard-iron compensation register(r/w). - * The value is expressed as a 16-bit word in two’s complement.[get] + * The value is expressed as a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -6631,19 +7012,20 @@ int32_t ism330dlc_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) if (ret == 0) { ret = ism330dlc_read_reg(ctx, ISM330DLC_MAG_OFFX_L, buff, 6); - val[0] = (int16_t)buff[1]; - val[0] = (val[0] * 256) + (int16_t)buff[0]; - val[1] = (int16_t)buff[3]; - val[1] = (val[1] * 256) + (int16_t)buff[2]; - val[2] = (int16_t)buff[5]; - val[2] = (val[2] * 256) + (int16_t)buff[4]; if (ret == 0) { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -6703,7 +7085,10 @@ int32_t ism330dlc_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSOR_SYNC_TIME_FRAME, (uint8_t *)&sensor_sync_time_frame, 1); - *val = sensor_sync_time_frame.tph; + if (ret == 0) + { + *val = sensor_sync_time_frame.tph; + } return ret; } @@ -6750,6 +7135,11 @@ int32_t ism330dlc_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_SENSOR_SYNC_RES_RATIO, (uint8_t *)&sensor_sync_res_ratio, 1); + if (ret != 0) + { + return ret; + } + switch (sensor_sync_res_ratio.rr) { case ISM330DLC_RES_RATIO_2_11: @@ -6815,7 +7205,10 @@ int32_t ism330dlc_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG, (uint8_t *)&master_config, 1); - *val = master_config.master_on; + if (ret == 0) + { + *val = master_config.master_on; + } return ret; } @@ -6859,7 +7252,10 @@ int32_t ism330dlc_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG, (uint8_t *)&master_config, 1); - *val = master_config.pass_through_mode; + if (ret == 0) + { + *val = master_config.pass_through_mode; + } return ret; } @@ -6906,6 +7302,11 @@ int32_t ism330dlc_sh_pin_mode_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) + { + return ret; + } + switch (master_config.pull_up_en) { case ISM330DLC_EXT_PULL_UP: @@ -6966,6 +7367,11 @@ int32_t ism330dlc_sh_syncro_mode_get(const stmdev_ctx_t *ctx, ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) + { + return ret; + } + switch (master_config.start_config) { case ISM330DLC_XL_GY_DRDY: @@ -7023,7 +7429,10 @@ int32_t ism330dlc_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CONFIG, (uint8_t *)&master_config, 1); - *val = master_config.drdy_on_int1; + if (ret == 0) + { + *val = master_config.drdy_on_int1; + } return ret; } @@ -7094,7 +7503,10 @@ int32_t ism330dlc_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_MASTER_CMD_CODE, (uint8_t *)&master_cmd_code, 1); - *val = master_cmd_code.master_cmd_code; + if (ret == 0) + { + *val = master_cmd_code.master_cmd_code; + } return ret; } @@ -7142,7 +7554,10 @@ int32_t ism330dlc_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_SENS_SYNC_SPI_ERROR_CODE, (uint8_t *)&sens_sync_spi_error_code, 1); - *val = sens_sync_spi_error_code.error_code; + if (ret == 0) + { + *val = sens_sync_spi_error_code.error_code; + } return ret; } @@ -7172,14 +7587,11 @@ int32_t ism330dlc_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, slave0_config.aux_sens_on = (uint8_t) val; ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); - - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7228,10 +7640,11 @@ int32_t ism330dlc_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, break; } - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7269,15 +7682,12 @@ int32_t ism330dlc_sh_cfg_write(const stmdev_ctx_t *ctx, { ret = ism330dlc_write_reg(ctx, ISM330DLC_DATAWRITE_SRC_MODE_SUB_SLV0, &(val->slv0_data), 1); - - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7322,16 +7732,13 @@ int32_t ism330dlc_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, { ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); - - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } } } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7376,16 +7783,13 @@ int32_t ism330dlc_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, { ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); - - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } } } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7430,16 +7834,13 @@ int32_t ism330dlc_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, slave2_config.slave2_numop = val->slv_len; ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE2_CONFIG, (uint8_t *)&slave2_config, 1); - - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } } } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7484,16 +7885,13 @@ int32_t ism330dlc_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, slave3_config.slave3_numop = val->slv_len; ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE3_CONFIG, (uint8_t *)&slave3_config, 1); - - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } } } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7524,13 +7922,11 @@ int32_t ism330dlc_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7579,11 +7975,11 @@ int32_t ism330dlc_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, *val = ISM330DLC_SL0_NO_DEC; break; } - - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7615,14 +8011,11 @@ int32_t ism330dlc_sh_write_mode_set(const stmdev_ctx_t *ctx, { ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); - - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } } + ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7665,11 +8058,11 @@ int32_t ism330dlc_sh_write_mode_get(const stmdev_ctx_t *ctx, *val = ISM330DLC_EACH_SH_CYCLE; break; } - - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7699,14 +8092,11 @@ int32_t ism330dlc_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, slave1_config.slave1_rate = (uint8_t) val; ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); - - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7754,11 +8144,11 @@ int32_t ism330dlc_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, *val = ISM330DLC_SL1_NO_DEC; break; } - - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7788,14 +8178,11 @@ int32_t ism330dlc_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, slave2_config.slave2_rate = (uint8_t) val; ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE2_CONFIG, (uint8_t *)&slave2_config, 1); - - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7844,11 +8231,11 @@ int32_t ism330dlc_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, *val = ISM330DLC_SL2_NO_DEC; break; } - - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7879,13 +8266,11 @@ int32_t ism330dlc_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, ret = ism330dlc_write_reg(ctx, ISM330DLC_SLAVE3_CONFIG, (uint8_t *)&slave3_config, 1); - if (ret == 0) - { - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); - } } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } @@ -7934,12 +8319,10 @@ int32_t ism330dlc_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, *val = ISM330DLC_SL3_NO_DEC; break; } - - ret = ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); } } + ret += ism330dlc_mem_bank_set(ctx, ISM330DLC_USER_BANK); + return ret; } - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h index 8368a9b..071546e 100644 --- a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h +++ b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -2811,5 +2813,3 @@ int32_t ism330dlc_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, #endif #endif /* ISM330DLC_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.c b/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.c index 7e9e137..87b658c 100644 --- a/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.c +++ b/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -202,7 +201,11 @@ int32_t ism330is_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330is_read_reg(ctx, ISM330IS_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); - *val = internal_freq_fine.freq_fine; + + if (ret == 0) + { + *val = internal_freq_fine.freq_fine; + } return ret; } @@ -243,6 +246,11 @@ int32_t ism330is_mem_bank_get(const stmdev_ctx_t *ctx, ism330is_mem_bank_t *val) ret = ism330is_read_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + if (func_cfg_access.shub_reg_access == 1U) { *val = ISM330IS_SENSOR_HUB_MEM_BANK; @@ -300,6 +308,11 @@ int32_t ism330is_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1); + if (ret != 0) + { + return ret; + } + switch ((drdy_pulsed_reg.drdy_pulsed)) { case ISM330IS_DRDY_LATCHED: @@ -403,6 +416,12 @@ int32_t ism330is_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.boot; return ret; @@ -447,6 +466,11 @@ int32_t ism330is_xl_hm_mode_get(const stmdev_ctx_t *ctx, ism330is_hm_mode_t *val ret = ism330is_read_reg(ctx, ISM330IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl6_c.xl_hm_mode)) { case ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED: @@ -505,6 +529,11 @@ int32_t ism330is_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl1_xl.fs_xl)) { case ISM330IS_2g: @@ -582,6 +611,11 @@ int32_t ism330is_xl_data_rate_get(const stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); ret += ism330is_read_reg(ctx, ISM330IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl6_c.xl_hm_mode << 4) | (ctrl1_xl.odr_xl)) { case ISM330IS_XL_ODR_OFF: @@ -719,6 +753,11 @@ int32_t ism330is_gy_hm_mode_get(const stmdev_ctx_t *ctx, ism330is_hm_mode_t *val ret = ism330is_read_reg(ctx, ISM330IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl7_g.g_hm_mode)) { case ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED: @@ -778,6 +817,11 @@ int32_t ism330is_gy_full_scale_get(const stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl2_g.fs_125 << 4) | (ctrl2_g.fs_g)) { case ISM330IS_125dps: @@ -859,6 +903,11 @@ int32_t ism330is_gy_data_rate_get(const stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); ret += ism330is_read_reg(ctx, ISM330IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl7_g.g_hm_mode << 4) | (ctrl2_g.odr_g)) { case ISM330IS_GY_ODR_OFF: @@ -992,6 +1041,11 @@ int32_t ism330is_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.if_inc; return ret; @@ -1036,6 +1090,11 @@ int32_t ism330is_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.bdu; return ret; @@ -1080,6 +1139,11 @@ int32_t ism330is_sleep_get(const stmdev_ctx_t *ctx, ism330is_sleep_t *val) ret = ism330is_read_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl4_c.sleep_g)) { case ISM330IS_SLEEP_G_ENABLE: @@ -1138,6 +1202,11 @@ int32_t ism330is_xl_self_test_get(const stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl5_c.st_xl)) { case ISM330IS_XL_ST_DISABLE: @@ -1200,6 +1269,11 @@ int32_t ism330is_gy_self_test_get(const stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl5_c.st_g)) { case ISM330IS_GY_ST_DISABLE: @@ -1266,6 +1340,11 @@ int32_t ism330is_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330is_read_reg(ctx, ISM330IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.sdo_pu_en; return ret; @@ -1310,6 +1389,11 @@ int32_t ism330is_spi_mode_get(const stmdev_ctx_t *ctx, ism330is_spi_mode_t *val) ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl3_c.sim)) { case ISM330IS_SPI_4_WIRE: @@ -1366,6 +1450,11 @@ int32_t ism330is_ui_i2c_mode_get(const stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t ret = ism330is_read_reg(ctx, ISM330IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl4_c.i2c_disable)) { case ISM330IS_I2C_ENABLE: @@ -1433,6 +1522,11 @@ int32_t ism330is_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330is_read_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl10_c.timestamp_en; return ret; @@ -1453,6 +1547,11 @@ int32_t ism330is_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) ret = ism330is_read_reg(ctx, ISM330IS_TIMESTAMP0, &buff[0], 4); + if (ret != 0) + { + return ret; + } + *val = (uint32_t)buff[3]; *val = (*val * 256U) + (uint32_t)buff[2]; *val = (*val * 256U) + (uint32_t)buff[1]; @@ -1547,6 +1646,12 @@ int32_t ism330is_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) + { + return ret; + } + *val = status_reg.xlda; return ret; @@ -1567,6 +1672,12 @@ int32_t ism330is_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) + { + return ret; + } + *val = status_reg.gda; return ret; @@ -1587,6 +1698,12 @@ int32_t ism330is_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) + { + return ret; + } + *val = status_reg.tda; return ret; @@ -1606,6 +1723,12 @@ int32_t ism330is_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ism330is_read_reg(ctx, ISM330IS_OUT_TEMP_L, &buff[0], 2); + + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1626,6 +1749,12 @@ int32_t ism330is_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ism330is_read_reg(ctx, ISM330IS_OUTX_L_G, buff, 6); + + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1650,6 +1779,12 @@ int32_t ism330is_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = ism330is_read_reg(ctx, ISM330IS_OUTX_L_A, buff, 6); + + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1845,6 +1980,11 @@ int32_t ism330is_int_pin_mode_get(const stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl3_c.pp_od)) { case ISM330IS_PUSH_PULL: @@ -1903,6 +2043,11 @@ int32_t ism330is_pin_polarity_get(const stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl3_c.h_lactive)) { case ISM330IS_ACTIVE_HIGH: @@ -1947,7 +2092,10 @@ int32_t ism330is_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); - ret += ism330is_read_reg(ctx, ISM330IS_SENSOR_HUB_1, val, len); + if (ret == 0) + { + ret += ism330is_read_reg(ctx, ISM330IS_SENSOR_HUB_1, val, len); + } ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); return ret; @@ -2075,13 +2223,12 @@ int32_t ism330is_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) + + if (ret == 0) { - return ret; + *val = master_config.master_on; } - *val = master_config.master_on; - ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); return ret; @@ -2132,14 +2279,13 @@ int32_t ism330is_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) + + if (ret == 0) { - return ret; + *val = master_config.shub_pu_en; } - *val = master_config.shub_pu_en; - - ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); return ret; } @@ -2188,8 +2334,10 @@ int32_t ism330is_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - - *val = master_config.pass_through_mode; + if (ret == 0) + { + *val = master_config.pass_through_mode; + } ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); return ret; @@ -2379,13 +2527,12 @@ int32_t ism330is_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) + + if (ret == 0) { - return ret; + *val = master_config.rst_master_regs; } - *val = master_config.rst_master_regs; - ret = ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); return ret; @@ -2411,7 +2558,7 @@ int32_t ism330is_sh_cfg_write(const stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } reg.slave0_add = val->slv0_add; @@ -2537,7 +2684,7 @@ int32_t ism330is_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } slv_add.slave0_add = val->slv_add; @@ -2641,6 +2788,11 @@ int32_t ism330is_ispu_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = ism330is_read_reg(ctx, ISM330IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + *val = func_cfg_access.sw_reset_ispu; @@ -2672,6 +2824,11 @@ int32_t ism330is_ispu_clock_get(const stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl10_c.ispu_clk_sel) { default: @@ -2731,6 +2888,11 @@ int32_t ism330is_ispu_data_rate_get(const stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl9_c.ispu_rate)) { case ISM330IS_ISPU_ODR_OFF: @@ -2823,6 +2985,11 @@ int32_t ism330is_ispu_bdu_get(const stmdev_ctx_t *ctx, ism330is_ispu_bdu_t *val) ret = ism330is_read_reg(ctx, ISM330IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl9_c.ispu_rate)) { case ISM330IS_ISPU_BDU_OFF: @@ -2863,6 +3030,11 @@ int32_t ism330is_ia_ispu_get(const stmdev_ctx_t *ctx, uint32_t *val) ret = ism330is_read_reg(ctx, ISM330IS_ISPU_INT_STATUS0_MAINPAGE, &buff[0], 4); + if (ret != 0) + { + return ret; + } + *val = (uint32_t)buff[3]; *val = (*val * 256U) + (uint32_t)buff[2]; *val = (*val * 256U) + (uint32_t)buff[1]; @@ -2940,7 +3112,7 @@ int32_t ism330is_ispu_boot_set(const stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); @@ -2976,7 +3148,7 @@ int32_t ism330is_ispu_boot_get(const stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret += ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); @@ -3014,7 +3186,7 @@ int32_t ism330is_ispu_int_latched_set(const stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret += ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); @@ -3087,13 +3259,11 @@ int32_t ism330is_ispu_get_boot_status(const stmdev_ctx_t *ctx, int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); - if (ret != 0) + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_STATUS, (uint8_t *)&ispu_boot_status, 1); + if (ret == 0) { - return ret; + *val = (ism330is_ispu_boot_end_t)ispu_boot_status.boot_end; } - - ret = ism330is_read_reg(ctx, ISM330IS_ISPU_STATUS, (uint8_t *)&ispu_boot_status, 1); - *val = (ism330is_ispu_boot_end_t)ispu_boot_status.boot_end; ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); return ret; @@ -3140,14 +3310,26 @@ int32_t ism330is_ispu_write_memory(const stmdev_ctx_t *ctx, { /* disable ISPU clock */ ret = ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); + if (ret != 0) + { + goto exit; + } clk_dis = ispu_cfg.clk_dis; ispu_cfg.clk_dis = 1; - ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); + ret = ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); + if (ret != 0) + { + goto exit; + } /* select memory to be written */ ispu_mem_sel.read_mem_en = 0; ispu_mem_sel.mem_sel = (uint8_t)mem_sel; - ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1); + ret = ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1); + if (ret != 0) + { + goto exit; + } if (mem_sel == ISM330IS_ISPU_PROGRAM_RAM_MEMORY) { @@ -3185,12 +3367,21 @@ int32_t ism330is_ispu_write_memory(const stmdev_ctx_t *ctx, ret += ism330is_ispu_sel_memory_addr(ctx, mem_addr); ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_DATA, &mem_data[0], len); } + if (ret != 0) + { + goto exit; + } /* set ISPU clock back to previous value */ ispu_cfg.clk_dis = clk_dis; ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); + if (ret != 0) + { + goto exit; + } } +exit: ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); return ret; @@ -3222,27 +3413,52 @@ int32_t ism330is_ispu_read_memory(const stmdev_ctx_t *ctx, { /* disable ISPU clock */ ret = ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); + if (ret != 0) + { + goto exit; + } clk_dis = ispu_cfg.clk_dis; ispu_cfg.clk_dis = 1; ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); + if (ret != 0) + { + goto exit; + } /* select memory to be read */ ispu_mem_sel.read_mem_en = 1; ispu_mem_sel.mem_sel = (uint8_t)mem_sel; ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1); + if (ret != 0) + { + goto exit; + } /* select memory address */ ret += ism330is_ispu_sel_memory_addr(ctx, mem_addr); + if (ret != 0) + { + goto exit; + } /* read data */ ret += ism330is_read_reg(ctx, ISM330IS_ISPU_MEM_DATA, &dummy, 1); + if (ret != 0) + { + goto exit; + } ret += ism330is_read_reg(ctx, ISM330IS_ISPU_MEM_DATA, &mem_data[0], len); + if (ret != 0) + { + goto exit; + } /* set ISPU clock back to previous value */ ispu_cfg.clk_dis = clk_dis; ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); } +exit: ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); return ret; @@ -3293,10 +3509,11 @@ int32_t ism330is_ispu_read_flags(const stmdev_ctx_t *ctx, uint16_t *data) int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); + + /* read the flags */ + ret += ism330is_read_reg(ctx, ISM330IS_ISPU_S2IF_FLAG_L, buff, 2); if (ret == 0) { - /* read the flags */ - ret += ism330is_read_reg(ctx, ISM330IS_ISPU_S2IF_FLAG_L, buff, 2); data[0] = (uint16_t)buff[1]; data[0] = (data[0] * 256U) + (uint16_t)buff[0]; } @@ -3323,9 +3540,10 @@ int32_t ism330is_ispu_clear_flags(const stmdev_ctx_t *ctx) if (ret == 0) { ret += ism330is_write_reg(ctx, ISM330IS_ISPU_S2IF_FLAG_H, &data, 1); - ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); } + ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); + return ret; } @@ -3374,10 +3592,13 @@ int32_t ism330is_ispu_int1_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val) /* read int1_ctrl reg */ ret += ism330is_read_reg(ctx, ISM330IS_ISPU_INT1_CTRL0, &buff[0], 4); - *val = (uint32_t)buff[3]; - *val = (*val * 256U) + (uint32_t)buff[2]; - *val = (*val * 256U) + (uint32_t)buff[1]; - *val = (*val * 256U) + (uint32_t)buff[0]; + if (ret == 0) + { + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } } ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); @@ -3446,10 +3667,13 @@ int32_t ism330is_ispu_int2_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val) /* read int2_ctrl reg */ ret += ism330is_read_reg(ctx, ISM330IS_ISPU_INT2_CTRL0, &buff[0], 4); - *val = (uint32_t)buff[3]; - *val = (*val * 256U) + (uint32_t)buff[2]; - *val = (*val * 256U) + (uint32_t)buff[1]; - *val = (*val * 256U) + (uint32_t)buff[0]; + if (ret == 0) + { + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } } ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); @@ -3518,10 +3742,13 @@ int32_t ism330is_ispu_int_status_get(const stmdev_ctx_t *ctx, uint32_t *val) /* read int2_ctrl reg */ ret += ism330is_read_reg(ctx, ISM330IS_ISPU_INT_STATUS0, &buff[0], 4); - *val = (uint32_t)buff[3]; - *val = (*val * 256U) + (uint32_t)buff[2]; - *val = (*val * 256U) + (uint32_t)buff[1]; - *val = (*val * 256U) + (uint32_t)buff[0]; + if (ret == 0) + { + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } } ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); @@ -3548,10 +3775,13 @@ int32_t ism330is_ispu_algo_get(const stmdev_ctx_t *ctx, uint32_t *val) /* read int2_ctrl reg */ ret += ism330is_read_reg(ctx, ISM330IS_ISPU_ALGO0, &buff[0], 4); - *val = (uint32_t)buff[3]; - *val = (*val * 256U) + (uint32_t)buff[2]; - *val = (*val * 256U) + (uint32_t)buff[1]; - *val = (*val * 256U) + (uint32_t)buff[0]; + if (ret == 0) + { + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } } ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); diff --git a/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.h b/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.h index 0762763..91a54d0 100644 --- a/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.h +++ b/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -2803,5 +2805,3 @@ int32_t ism330is_ispu_algo_set(const stmdev_ctx_t *ctx, uint32_t val); #endif #endif /*ISM330IS_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism6hg256x_STdC/driver/ism6hg256x_reg.c b/sensor/stmemsc/ism6hg256x_STdC/driver/ism6hg256x_reg.c new file mode 100644 index 0000000..3e6b05c --- /dev/null +++ b/sensor/stmemsc/ism6hg256x_STdC/driver/ism6hg256x_reg.c @@ -0,0 +1,12201 @@ +/** + ****************************************************************************** + * @file ism6hg256x_reg.c + * @author Sensors Software Solution Team + * @brief ISM6HG256X driver file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#include "ism6hg256x_reg.h" + +/** + * @defgroup ISM6HG256X + * @brief This file provides a set of functions needed to drive the + * ism6hg256x enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup Interfaces functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to read. + * @param data buffer for data read.(ptr) + * @param len number of consecutive register to read. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak ism6hg256x_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) + { + return -1; + } + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to write. + * @param data the buffer contains data to be written.(ptr) + * @param len number of consecutive register to write. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak ism6hg256x_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) + { + return -1; + } + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Private functions + * @brief Section collect all the utility functions needed by APIs. + * @{ + * + */ + +static void bytecpy(uint8_t *target, uint8_t *source) +{ + if ((target != NULL) && (source != NULL)) + { + *target = *source; + } +} + +/** + * @} + * + */ + +/** + * @defgroup Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ +float_t ism6hg256x_from_sflp_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t ism6hg256x_from_fs2_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t ism6hg256x_from_fs4_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.122f; +} + +float_t ism6hg256x_from_fs8_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.244f; +} + +float_t ism6hg256x_from_fs16_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.488f; +} + +float_t ism6hg256x_from_fs32_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.976f; +} + +float_t ism6hg256x_from_fs64_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 1.952f; +} + +float_t ism6hg256x_from_fs128_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 3.904f; +} + +float_t ism6hg256x_from_fs256_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 10.417f; +} + +float_t ism6hg256x_from_fs125_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 4.375f; +} +float_t ism6hg256x_from_fs250_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 8.750f; +} + +float_t ism6hg256x_from_fs500_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 17.50f; +} + +float_t ism6hg256x_from_fs1000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 35.0f; +} + +float_t ism6hg256x_from_fs2000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 70.0f; +} + +float_t ism6hg256x_from_fs4000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 140.0f; +} + +float_t ism6hg256x_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +uint64_t ism6hg256x_from_lsb_to_nsec(uint32_t lsb) +{ + return ((uint64_t)lsb * 21700); +} + +float_t ism6hg256x_from_lsb_to_mv(int16_t lsb) +{ + return ((float_t)lsb) / 78.0f; +} + +float_t ism6hg256x_from_gbias_lsb_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 4.375f; +} + +float_t ism6hg256x_from_gravity_lsb_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +static float_t npy_half_to_float(uint16_t h); +float_t ism6hg256x_from_quaternion_lsb_to_float(uint16_t lsb) +{ + return npy_half_to_float(lsb); +} + +static uint32_t npy_halfbits_to_floatbits(uint16_t h); +/** + * @brief Convert from 16-bit to 32-bit float number + * + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +uint32_t ism6hg256x_from_f16_to_f32(uint16_t val) +{ + return npy_halfbits_to_floatbits(val); +} + +/** + * @} + * + */ + +/** + * @defgroup Accelerometer user offset correction + * @brief This section groups all the functions concerning the + * usage of Accelerometer user offset correction + * @{ + * + */ + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_ctrl9_t ctrl9; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.usr_off_on_out = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_ctrl9_t ctrl9; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.usr_off_on_out; + + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_offset_mg_set(const stmdev_ctx_t *ctx, + ism6hg256x_xl_offset_mg_t val) +{ + ism6hg256x_z_ofs_usr_t z_ofs_usr; + ism6hg256x_y_ofs_usr_t y_ofs_usr; + ism6hg256x_x_ofs_usr_t x_ofs_usr; + ism6hg256x_ctrl9_t ctrl9; + int32_t ret; + float_t tmp; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + if (ret != 0) + { + return ret; + } + + + if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && + (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) && + (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f))) + { + ctrl9.usr_off_w = 0; + + tmp = val.z_mg / 0.0078125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.0078125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.0078125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) && + (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) && + (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f))) + { + ctrl9.usr_off_w = 1; + + tmp = val.z_mg / 0.125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else // out of limit + { + ctrl9.usr_off_w = 1; + z_ofs_usr.z_ofs_usr = 0xFFU; + y_ofs_usr.y_ofs_usr = 0xFFU; + x_ofs_usr.x_ofs_usr = 0xFFU; + } + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_offset_mg_get(const stmdev_ctx_t *ctx, + ism6hg256x_xl_offset_mg_t *val) +{ + ism6hg256x_z_ofs_usr_t z_ofs_usr; + ism6hg256x_y_ofs_usr_t y_ofs_usr; + ism6hg256x_x_ofs_usr_t x_ofs_usr; + ism6hg256x_ctrl9_t ctrl9; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + if (ret != 0) + { + return ret; + } + + if (ctrl9.usr_off_w == PROPERTY_DISABLE) + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f); + } + else + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f); + } + + return ret; +} + +/** + * @brief HG Accelerometer user offset correction values in mg.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_hg_xl_offset_mg_set(const stmdev_ctx_t *ctx, + ism6hg256x_xl_offset_mg_t val) +{ + ism6hg256x_hg_z_ofs_usr_t z_ofs_usr; + ism6hg256x_hg_y_ofs_usr_t y_ofs_usr; + ism6hg256x_hg_x_ofs_usr_t x_ofs_usr; + ism6hg256x_ctrl1_xl_hg_t ctrl1_xl_hg; + int32_t ret; + float_t tmp; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL1_XL_HG, (uint8_t *)&ctrl1_xl_hg, 1); + if (ret != 0) + { + return ret; + } + + if ((val.x_mg < (0.25f * 127.0f)) && (val.x_mg > (0.25f * -127.0f)) && + (val.y_mg < (0.25f * 127.0f)) && (val.y_mg > (0.25f * -127.0f)) && + (val.z_mg < (0.25f * 127.0f)) && (val.z_mg > (0.25f * -127.0f))) + { + ctrl1_xl_hg.hg_usr_off_on_out = 1; + + tmp = val.z_mg / 0.25f; + z_ofs_usr.xl_hg_z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.25f; + y_ofs_usr.xl_hg_y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.25f; + x_ofs_usr.xl_hg_x_ofs_usr = (uint8_t)tmp; + } + else // out of limit + { + ctrl1_xl_hg.hg_usr_off_on_out = 0; + z_ofs_usr.xl_hg_z_ofs_usr = 0xFFU; + y_ofs_usr.xl_hg_y_ofs_usr = 0xFFU; + x_ofs_usr.xl_hg_x_ofs_usr = 0xFFU; + } + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_XL_HG_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_XL_HG_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_XL_HG_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL1_XL_HG, (uint8_t *)&ctrl1_xl_hg, 1); + + return ret; +} + +/** + * @brief HG Accelerometer user offset correction values in mg.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_hg_xl_offset_mg_get(const stmdev_ctx_t *ctx, + ism6hg256x_xl_offset_mg_t *val) +{ + ism6hg256x_hg_z_ofs_usr_t z_ofs_usr; + ism6hg256x_hg_y_ofs_usr_t y_ofs_usr; + ism6hg256x_hg_x_ofs_usr_t x_ofs_usr; + ism6hg256x_ctrl1_xl_hg_t ctrl1_xl_hg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL1_XL_HG, (uint8_t *)&ctrl1_xl_hg, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_XL_HG_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_XL_HG_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_XL_HG_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + if (ret != 0) + { + return ret; + } + + if (ctrl1_xl_hg.hg_usr_off_on_out == PROPERTY_DISABLE) + { + val->z_mg = 0.0f; + val->y_mg = 0.0f; + val->x_mg = 0.0f; + } + else + { + val->z_mg = ((float_t)z_ofs_usr.xl_hg_z_ofs_usr * 0.25f); + val->y_mg = ((float_t)y_ofs_usr.xl_hg_y_ofs_usr * 0.25f); + val->x_mg = ((float_t)x_ofs_usr.xl_hg_x_ofs_usr * 0.25f); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @brief Reset of the device.[set] + * + * @param ctx read / write interface definitions + * @param val Reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_reset_set(const stmdev_ctx_t *ctx, ism6hg256x_reset_t val) +{ + ism6hg256x_func_cfg_access_t func_cfg_access; + ism6hg256x_ctrl3_t ctrl3; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL3, (uint8_t *)&ctrl3, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + + ctrl3.boot = (val == ISM6HG256X_RESTORE_CAL_PARAM) ? 1 : 0; + ctrl3.sw_reset = (val == ISM6HG256X_RESTORE_CTRL_REGS) ? 1 : 0; + func_cfg_access.sw_por = (val == ISM6HG256X_GLOBAL_RST) ? 1 : 0; + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL3, (uint8_t *)&ctrl3, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + return ret; +} + +/** + * @brief Global reset of the device.[get] + * + * @param ctx read / write interface definitions + * @param val Global reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_reset_get(const stmdev_ctx_t *ctx, ism6hg256x_reset_t *val) +{ + ism6hg256x_func_cfg_access_t func_cfg_access; + ism6hg256x_ctrl3_t ctrl3; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL3, (uint8_t *)&ctrl3, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + + switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) + { + case ISM6HG256X_READY: + *val = ISM6HG256X_READY; + break; + + case ISM6HG256X_GLOBAL_RST: + *val = ISM6HG256X_GLOBAL_RST; + break; + + case ISM6HG256X_RESTORE_CAL_PARAM: + *val = ISM6HG256X_RESTORE_CAL_PARAM; + break; + + case ISM6HG256X_RESTORE_CTRL_REGS: + *val = ISM6HG256X_RESTORE_CTRL_REGS; + break; + + default: + *val = ISM6HG256X_GLOBAL_RST; + break; + } + + return ret; +} + +/** + * @brief Change memory bank.[set] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_mem_bank_set(const stmdev_ctx_t *ctx, ism6hg256x_mem_bank_t val) +{ + ism6hg256x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + + func_cfg_access.shub_reg_access = ((uint8_t)val & 0x02U) >> 1; + func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + return ret; +} + +/** + * @brief Change memory bank.[get] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_mem_bank_get(const stmdev_ctx_t *ctx, ism6hg256x_mem_bank_t *val) +{ + ism6hg256x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + + switch ((func_cfg_access.shub_reg_access << 1) + func_cfg_access.emb_func_reg_access) + { + case ISM6HG256X_MAIN_MEM_BANK: + *val = ISM6HG256X_MAIN_MEM_BANK; + break; + + case ISM6HG256X_EMBED_FUNC_MEM_BANK: + *val = ISM6HG256X_EMBED_FUNC_MEM_BANK; + break; + + case ISM6HG256X_SENSOR_HUB_MEM_BANK: + *val = ISM6HG256X_SENSOR_HUB_MEM_BANK; + break; + + default: + *val = ISM6HG256X_MAIN_MEM_BANK; + break; + } + + return ret; +} + +/** + * @brief Device ID.[get] + * + * @param ctx read / write interface definitions + * @param val Device ID. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_WHO_AM_I, val, 1); + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val ism6hg256x_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_data_rate_t val) +{ + ism6hg256x_ctrl1_t ctrl1; + ism6hg256x_haodr_cfg_t haodr; + uint8_t sel; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } + + ctrl1.odr_xl = (uint8_t)val & 0x0Fu; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } + + sel = ((uint8_t)val >> 4) & 0xFU; + if (sel != 0U) + { + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } + haodr.haodr_sel = sel; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_HAODR_CFG, (uint8_t *)&haodr, 1); + } + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val ism6hg256x_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_data_rate_t *val) +{ + ism6hg256x_ctrl1_t ctrl1; + ism6hg256x_haodr_cfg_t haodr; + uint8_t sel; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL1, (uint8_t *)&ctrl1, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } + + sel = haodr.haodr_sel; + + switch (ctrl1.odr_xl) + { + case ISM6HG256X_ODR_OFF: + *val = ISM6HG256X_ODR_OFF; + break; + + case ISM6HG256X_ODR_AT_1Hz875: + *val = ISM6HG256X_ODR_AT_1Hz875; + break; + + case ISM6HG256X_ODR_AT_7Hz5: + *val = ISM6HG256X_ODR_AT_7Hz5; + break; + + case ISM6HG256X_ODR_AT_15Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_15Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_15Hz625; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_12Hz5; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_13Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_30Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_30Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_31Hz25; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_25Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_26Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_60Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_60Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_62Hz5; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_50Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_52Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_120Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_120Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_125Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_100Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_104Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_240Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_240Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_250Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_200Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_208Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_480Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_480Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_500Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_400Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_417Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_960Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_960Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_1000Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_800Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_833Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_1920Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_1920Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_2000Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_1600Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_1667Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_3840Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_3840Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_4000Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_3200Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_3333Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_7680Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_7680Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_8000Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_6400Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_6667Hz; + break; + } + break; + + default: + *val = ISM6HG256X_ODR_OFF; + break; + } + + return ret; +} + +/** + * @brief HG Accelerometer output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val ism6hg256x_hg_xl_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_hg_xl_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_hg_xl_data_rate_t val, + uint8_t reg_out_en) +{ + ism6hg256x_ctrl1_xl_hg_t ctrl1_xl_hg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL1_XL_HG, (uint8_t *)&ctrl1_xl_hg, 1); + if (ret != 0) + { + return ret; + } + + ctrl1_xl_hg.odr_xl_hg = (uint8_t)val & 0x07U; + ctrl1_xl_hg.xl_hg_regout_en = reg_out_en & 0x1U; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL1_XL_HG, (uint8_t *)&ctrl1_xl_hg, 1); + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val ism6hg256x_hg_xl_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_hg_xl_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_hg_xl_data_rate_t *val, + uint8_t *reg_out_en) +{ + ism6hg256x_ctrl1_xl_hg_t ctrl1_xl_hg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL1_XL_HG, (uint8_t *)&ctrl1_xl_hg, 1); + if (ret != 0) + { + return ret; + } + + *reg_out_en = ctrl1_xl_hg.xl_hg_regout_en; + + switch (ctrl1_xl_hg.odr_xl_hg) + { + case ISM6HG256X_HG_XL_ODR_OFF: + *val = ISM6HG256X_HG_XL_ODR_OFF; + break; + + case ISM6HG256X_HG_XL_ODR_AT_480Hz: + *val = ISM6HG256X_HG_XL_ODR_AT_480Hz; + break; + + case ISM6HG256X_HG_XL_ODR_AT_960Hz: + *val = ISM6HG256X_HG_XL_ODR_AT_960Hz; + break; + + case ISM6HG256X_HG_XL_ODR_AT_1920Hz: + *val = ISM6HG256X_HG_XL_ODR_AT_1920Hz; + break; + + case ISM6HG256X_HG_XL_ODR_AT_3840Hz: + *val = ISM6HG256X_HG_XL_ODR_AT_3840Hz; + break; + + case ISM6HG256X_HG_XL_ODR_AT_7680Hz: + *val = ISM6HG256X_HG_XL_ODR_AT_7680Hz; + break; + + default: + *val = ISM6HG256X_HG_XL_ODR_OFF; + break; + } + + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_xl_mode_t val) +{ + ism6hg256x_ctrl1_t ctrl1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.op_mode_xl = (uint8_t)val & 0x07U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_xl_mode_t *val) +{ + ism6hg256x_ctrl1_t ctrl1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl1.op_mode_xl) + { + case ISM6HG256X_XL_HIGH_PERFORMANCE_MD: + *val = ISM6HG256X_XL_HIGH_PERFORMANCE_MD; + break; + + case ISM6HG256X_XL_HIGH_ACCURACY_ODR_MD: + *val = ISM6HG256X_XL_HIGH_ACCURACY_ODR_MD; + break; + + case ISM6HG256X_XL_ODR_TRIGGERED_MD: + *val = ISM6HG256X_XL_ODR_TRIGGERED_MD; + break; + + case ISM6HG256X_XL_LOW_POWER_2_AVG_MD: + *val = ISM6HG256X_XL_LOW_POWER_2_AVG_MD; + break; + + case ISM6HG256X_XL_LOW_POWER_4_AVG_MD: + *val = ISM6HG256X_XL_LOW_POWER_4_AVG_MD; + break; + + case ISM6HG256X_XL_LOW_POWER_8_AVG_MD: + *val = ISM6HG256X_XL_LOW_POWER_8_AVG_MD; + break; + + case ISM6HG256X_XL_NORMAL_MD: + *val = ISM6HG256X_XL_NORMAL_MD; + break; + + default: + *val = ISM6HG256X_XL_HIGH_PERFORMANCE_MD; + break; + } + + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val ism6hg256x_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_gy_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_data_rate_t val) +{ + ism6hg256x_ctrl2_t ctrl2; + ism6hg256x_haodr_cfg_t haodr; + uint8_t sel; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } + ctrl2.odr_g = (uint8_t)val & 0x0Fu; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } + + sel = ((uint8_t)val >> 4) & 0xFU; + if (sel != 0U) + { + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } + haodr.haodr_sel = sel; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_HAODR_CFG, (uint8_t *)&haodr, 1); + } + + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val ism6hg256x_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_gy_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_data_rate_t *val) +{ + ism6hg256x_ctrl2_t ctrl2; + ism6hg256x_haodr_cfg_t haodr; + uint8_t sel; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL2, (uint8_t *)&ctrl2, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } + + sel = haodr.haodr_sel; + + switch (ctrl2.odr_g) + { + case ISM6HG256X_ODR_OFF: + *val = ISM6HG256X_ODR_OFF; + break; + + case ISM6HG256X_ODR_AT_1Hz875: + *val = ISM6HG256X_ODR_AT_1Hz875; + break; + + case ISM6HG256X_ODR_AT_7Hz5: + *val = ISM6HG256X_ODR_AT_7Hz5; + break; + + case ISM6HG256X_ODR_AT_15Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_15Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_15Hz625; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_12Hz5; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_13Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_30Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_30Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_31Hz25; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_25Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_26Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_60Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_60Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_62Hz5; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_50Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_52Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_120Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_120Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_125Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_100Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_104Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_240Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_240Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_250Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_200Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_208Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_480Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_480Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_500Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_400Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_417Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_960Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_960Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_1000Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_800Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_833Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_1920Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_1920Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_2000Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_1600Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_1667Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_3840Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_3840Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_4000Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_3200Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_3333Hz; + break; + } + break; + + case ISM6HG256X_ODR_AT_7680Hz: + switch (sel) + { + default: + case 0: + *val = ISM6HG256X_ODR_AT_7680Hz; + break; + case 1: + *val = ISM6HG256X_ODR_HA01_AT_8000Hz; + break; + case 2: + *val = ISM6HG256X_ODR_HA02_AT_6400Hz; + break; + case 3: + *val = ISM6HG256X_ODR_HA03_AT_6667Hz; + break; + } + break; + + default: + *val = ISM6HG256X_ODR_OFF; + break; + } + + + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_gy_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_gy_mode_t val) +{ + ism6hg256x_ctrl2_t ctrl2; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret == 0) + { + ctrl2.op_mode_g = (uint8_t)val & 0x07U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_gy_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_gy_mode_t *val) +{ + ism6hg256x_ctrl2_t ctrl2; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl2.op_mode_g) + { + case ISM6HG256X_GY_HIGH_PERFORMANCE_MD: + *val = ISM6HG256X_GY_HIGH_PERFORMANCE_MD; + break; + + case ISM6HG256X_GY_HIGH_ACCURACY_ODR_MD: + *val = ISM6HG256X_GY_HIGH_ACCURACY_ODR_MD; + break; + + case ISM6HG256X_GY_ODR_TRIGGERED_MD: + *val = ISM6HG256X_GY_ODR_TRIGGERED_MD; + break; + + case ISM6HG256X_GY_SLEEP_MD: + *val = ISM6HG256X_GY_SLEEP_MD; + break; + + case ISM6HG256X_GY_LOW_POWER_MD: + *val = ISM6HG256X_GY_LOW_POWER_MD; + break; + + default: + *val = ISM6HG256X_GY_HIGH_PERFORMANCE_MD; + break; + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_ctrl3_t ctrl3; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ctrl3.if_inc = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_ctrl3_t ctrl3; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + + *val = ctrl3.if_inc; + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_ctrl3_t ctrl3; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret == 0) + { + ctrl3.bdu = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_ctrl3_t ctrl3; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + + *val = ctrl3.bdu; + + return ret; +} + +/** + * @brief Configure ODR trigger. [set] + * + * @param ctx read / write interface definitions + * @param val number of data in the reference period. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_odr_trig_cfg_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_odr_trig_cfg_t odr_trig; + int32_t ret; + + if (val >= 1U && val <= 3U) + { + return -1; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + + if (ret == 0) + { + odr_trig.odr_trig_nodr = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + } + + return ret; +} + +/** + * @brief Configure ODR trigger. [get] + * + * @param ctx read / write interface definitions + * @param val number of data in the reference period. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_odr_trig_cfg_t odr_trig; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + if (ret != 0) + { + return ret; + } + *val = odr_trig.odr_trig_nodr; + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[set] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_data_ready_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_data_ready_mode_t val) +{ + ism6hg256x_ctrl4_t ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_pulsed = (uint8_t)val & 0x1U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[get] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_data_ready_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_data_ready_mode_t *val) +{ + ism6hg256x_ctrl4_t ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl4.drdy_pulsed) + { + case ISM6HG256X_DRDY_LATCHED: + *val = ISM6HG256X_DRDY_LATCHED; + break; + + case ISM6HG256X_DRDY_PULSED: + *val = ISM6HG256X_DRDY_PULSED; + break; + + default: + *val = ISM6HG256X_DRDY_LATCHED; + break; + } + + return ret; +} + +/** + * @brief Enables interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val enable/disable, latched/pulsed + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_interrupt_enable_set(const stmdev_ctx_t *ctx, + ism6hg256x_interrupt_mode_t val) +{ + ism6hg256x_tap_cfg0_t cfg; + ism6hg256x_functions_enable_t func; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + if (ret != 0) + { + return ret; + } + + func.interrupts_enable = val.enable; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&cfg, 1); + if (ret != 0) + { + return ret; + } + + cfg.lir = val.lir; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&cfg, 1); + + return ret; +} + +/** + * @brief Enables latched interrupt mode.[get] + * + * @param ctx read / write interface definitions + * @param val enable/disable, latched/pulsed + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_interrupt_enable_get(const stmdev_ctx_t *ctx, + ism6hg256x_interrupt_mode_t *val) +{ + ism6hg256x_tap_cfg0_t cfg; + ism6hg256x_functions_enable_t func; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&cfg, 1); + if (ret != 0) + { + return ret; + } + + val->enable = func.interrupts_enable; + val->lir = cfg.lir; + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_gy_full_scale_set(const stmdev_ctx_t *ctx, + ism6hg256x_gy_full_scale_t val) +{ + ism6hg256x_ctrl6_t ctrl6; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL6, (uint8_t *)&ctrl6, 1); + + if (ret == 0) + { + ctrl6.fs_g = (uint8_t)val & 0xfu; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_gy_full_scale_get(const stmdev_ctx_t *ctx, + ism6hg256x_gy_full_scale_t *val) +{ + ism6hg256x_ctrl6_t ctrl6; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl6.fs_g) + { + case ISM6HG256X_250dps: + *val = ISM6HG256X_250dps; + break; + + case ISM6HG256X_500dps: + *val = ISM6HG256X_500dps; + break; + + case ISM6HG256X_1000dps: + *val = ISM6HG256X_1000dps; + break; + + case ISM6HG256X_2000dps: + *val = ISM6HG256X_2000dps; + break; + + case ISM6HG256X_4000dps: + *val = ISM6HG256X_4000dps; + break; + + default: + *val = ISM6HG256X_250dps; + break; + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_full_scale_set(const stmdev_ctx_t *ctx, + ism6hg256x_xl_full_scale_t val) +{ + ism6hg256x_ctrl8_t ctrl8; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.fs_xl = (uint8_t)val & 0x3U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_full_scale_get(const stmdev_ctx_t *ctx, + ism6hg256x_xl_full_scale_t *val) +{ + ism6hg256x_ctrl8_t ctrl8; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl8.fs_xl) + { + case ISM6HG256X_2g: + *val = ISM6HG256X_2g; + break; + + case ISM6HG256X_4g: + *val = ISM6HG256X_4g; + break; + + case ISM6HG256X_8g: + *val = ISM6HG256X_8g; + break; + + case ISM6HG256X_16g: + *val = ISM6HG256X_16g; + break; + + default: + *val = ISM6HG256X_2g; + break; + } + + return ret; +} + +/** + * @brief Accelerometer HG full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val ism6hg256x_hg_xl_full_scale_t + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_hg_xl_full_scale_set(const stmdev_ctx_t *ctx, + ism6hg256x_hg_xl_full_scale_t val) +{ + ism6hg256x_ctrl1_xl_hg_t ctrl1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL1_XL_HG, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.fs_xl_hg = (uint8_t)val & 0x7U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL1_XL_HG, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer HG full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val ism6hg256x_hg_xl_full_scale_t + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_hg_xl_full_scale_get(const stmdev_ctx_t *ctx, + ism6hg256x_hg_xl_full_scale_t *val) +{ + ism6hg256x_ctrl1_xl_hg_t ctrl1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL1_XL_HG, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl1.fs_xl_hg) + { + case ISM6HG256X_32g: + *val = ISM6HG256X_32g; + break; + + case ISM6HG256X_64g: + *val = ISM6HG256X_64g; + break; + + case ISM6HG256X_128g: + *val = ISM6HG256X_128g; + break; + + case ISM6HG256X_256g: + *val = ISM6HG256X_256g; + break; + + default: + *val = ISM6HG256X_32g; + break; + } + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val ST_DISABLE, ST_POSITIVE, ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_self_test_set(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t val) +{ + ism6hg256x_ctrl10_t ctrl10; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_xl = (uint8_t)val & 0x3U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val ST_DISABLE, ST_POSITIVE, ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_self_test_get(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t *val) +{ + ism6hg256x_ctrl10_t ctrl10; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl10.st_xl) + { + case ISM6HG256X_ST_DISABLE: + *val = ISM6HG256X_ST_DISABLE; + break; + + case ISM6HG256X_ST_POSITIVE: + *val = ISM6HG256X_ST_POSITIVE; + break; + + case ISM6HG256X_ST_NEGATIVE: + *val = ISM6HG256X_ST_NEGATIVE; + break; + + default: + *val = ISM6HG256X_ST_DISABLE; + break; + } + + return ret; +} + +/** + * @brief Gyroscope self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val ST_DISABLE, ST_POSITIVE, ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_gy_self_test_set(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t val) +{ + ism6hg256x_ctrl10_t ctrl10; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_g = (uint8_t)val & 0x3U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Gyroscope self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val ST_DISABLE, ST_POSITIVE, ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_gy_self_test_get(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t *val) +{ + ism6hg256x_ctrl10_t ctrl10; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl10.st_g) + { + case ISM6HG256X_ST_DISABLE: + *val = ISM6HG256X_ST_DISABLE; + break; + + case ISM6HG256X_ST_POSITIVE: + *val = ISM6HG256X_ST_POSITIVE; + break; + + case ISM6HG256X_ST_NEGATIVE: + *val = ISM6HG256X_ST_NEGATIVE; + break; + + default: + *val = ISM6HG256X_ST_DISABLE; + break; + } + + return ret; +} + +/** + * @brief HG XL self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val ST_DISABLE, ST_POSITIVE, ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_hg_xl_self_test_set(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t val) +{ + ism6hg256x_ctrl2_xl_hg_t ctrl2_xl_hg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL2_XL_HG, (uint8_t *)&ctrl2_xl_hg, 1); + + if (ret == 0) + { + ctrl2_xl_hg.xl_hg_st = (uint8_t)val & 0x3U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL2_XL_HG, (uint8_t *)&ctrl2_xl_hg, 1); + } + + return ret; +} + +/** + * @brief HG XL self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val ST_DISABLE, ST_POSITIVE, ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_hg_xl_self_test_get(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t *val) +{ + ism6hg256x_ctrl2_xl_hg_t ctrl2_xl_hg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL2_XL_HG, (uint8_t *)&ctrl2_xl_hg, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl2_xl_hg.xl_hg_st) + { + case ISM6HG256X_ST_DISABLE: + *val = ISM6HG256X_ST_DISABLE; + break; + + case ISM6HG256X_ST_POSITIVE: + *val = ISM6HG256X_ST_POSITIVE; + break; + + case ISM6HG256X_ST_NEGATIVE: + *val = ISM6HG256X_ST_NEGATIVE; + break; + + default: + *val = ISM6HG256X_ST_DISABLE; + break; + } + + return ret; +} + +/** + * @brief IF2 Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val ST_DISABLE, ST_POSITIVE, ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_xl_self_test_set(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t val) +{ + ism6hg256x_if2_int_ois_t if2_int_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF2_INT_OIS, (uint8_t *)&if2_int_ois, 1); + + if (ret == 0) + { + if2_int_ois.st_xl_ois = ((uint8_t)val & 0x3U); + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_IF2_INT_OIS, (uint8_t *)&if2_int_ois, 1); + } + + return ret; +} + +/** + * @brief IF2 Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val ST_DISABLE, ST_POSITIVE, ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_xl_self_test_get(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t *val) +{ + ism6hg256x_if2_int_ois_t if2_int_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF2_INT_OIS, (uint8_t *)&if2_int_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (if2_int_ois.st_xl_ois) + { + case ISM6HG256X_ST_DISABLE: + *val = ISM6HG256X_ST_DISABLE; + break; + + case ISM6HG256X_ST_POSITIVE: + *val = ISM6HG256X_ST_POSITIVE; + break; + + case ISM6HG256X_ST_NEGATIVE: + *val = ISM6HG256X_ST_NEGATIVE; + break; + + default: + *val = ISM6HG256X_ST_DISABLE; + break; + } + + return ret; +} + +/** + * @brief IF2 Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, ISM6HG256X_OIS_GY_ST_CLAMP_POS, ISM6HG256X_OIS_GY_ST_CLAMP_NEG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_gy_self_test_set(const stmdev_ctx_t *ctx, + ism6hg256x_ois_gy_self_test_t val) +{ + ism6hg256x_if2_int_ois_t if2_int_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF2_INT_OIS, (uint8_t *)&if2_int_ois, 1); + + if (ret == 0) + { + if2_int_ois.st_g_ois = ((uint8_t)val & 0x3U); + if2_int_ois.st_ois_clampdis = ((uint8_t)val & 0x04U) >> 2; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_IF2_INT_OIS, (uint8_t *)&if2_int_ois, 1); + } + + return ret; +} + +/** + * @brief IF2 Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, ISM6HG256X_OIS_GY_ST_CLAMP_POS, ISM6HG256X_OIS_GY_ST_CLAMP_NEG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_gy_self_test_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_gy_self_test_t *val) +{ + ism6hg256x_if2_int_ois_t if2_int_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF2_INT_OIS, (uint8_t *)&if2_int_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (if2_int_ois.st_g_ois) + { + case ISM6HG256X_OIS_GY_ST_DISABLE: + *val = ISM6HG256X_OIS_GY_ST_DISABLE; + break; + + case ISM6HG256X_OIS_GY_ST_POSITIVE: + *val = (if2_int_ois.st_ois_clampdis == 1U) ? ISM6HG256X_OIS_GY_ST_CLAMP_POS : + ISM6HG256X_OIS_GY_ST_POSITIVE; + break; + + case ISM6HG256X_OIS_GY_ST_NEGATIVE: + *val = (if2_int_ois.st_ois_clampdis == 1U) ? ISM6HG256X_OIS_GY_ST_CLAMP_NEG : + ISM6HG256X_OIS_GY_ST_NEGATIVE; + break; + + default: + *val = ISM6HG256X_OIS_GY_ST_DISABLE; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup High-g + * @brief This section groups all the functions that manage + * High-g + * @{ + * + */ + +/** + * @brief High-g event configuration.[set] + * + * @param ctx read / write interface definitions + * @param val ism6hg256x_hg_wake_up_cfg_t structure + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_hg_wake_up_cfg_set(const stmdev_ctx_t *ctx, + ism6hg256x_hg_wake_up_cfg_t val) +{ + ism6hg256x_hg_functions_enable_t hg_func; + ism6hg256x_hg_wake_up_ths_t hg_wake_up_ths; + uint8_t reg[2]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_HG_FUNCTIONS_ENABLE, (uint8_t *)&hg_func, 1); + if (ret != 0) + { + return ret; + } + + hg_func.hg_shock_dur = val.hg_shock_dur; + hg_wake_up_ths.hg_wk_ths = val.hg_wakeup_ths; + + bytecpy(®[0], (uint8_t *)&hg_func); + bytecpy(®[1], (uint8_t *)&hg_wake_up_ths); + + return ism6hg256x_write_reg(ctx, ISM6HG256X_HG_FUNCTIONS_ENABLE, reg, 2); +} + +/** + * @brief High-g event configuration.[get] + * + * @param ctx read / write interface definitions + * @param val ism6hg256x_hg_wake_up_cfg_t structure + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_hg_wake_up_cfg_get(const stmdev_ctx_t *ctx, + ism6hg256x_hg_wake_up_cfg_t *val) +{ + ism6hg256x_hg_functions_enable_t hg_func; + ism6hg256x_hg_wake_up_ths_t hg_wake_up_ths; + uint8_t buff[2]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_HG_FUNCTIONS_ENABLE, (uint8_t *)buff, 2); + if (ret != 0) + { + return ret; + } + + bytecpy((uint8_t *)&hg_func, &buff[0]); + bytecpy((uint8_t *)&hg_wake_up_ths, &buff[1]); + + val->hg_shock_dur = hg_func.hg_shock_dur; + val->hg_wakeup_ths = hg_wake_up_ths.hg_wk_ths; + + return ret; +} + +/** + * @brief High-g wake-up interrupt configuration[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val ism6hg256x_hg_wu_interrupt_cfg_t. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_hg_wu_interrupt_cfg_set(const stmdev_ctx_t *ctx, + ism6hg256x_hg_wu_interrupt_cfg_t val) +{ + ism6hg256x_hg_functions_enable_t hg_func; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_HG_FUNCTIONS_ENABLE, (uint8_t *)&hg_func, 1); + if (ret != 0) + { + return ret; + } + + hg_func.hg_interrupts_enable = val.hg_interrupts_enable; + hg_func.hg_wu_change_int_sel = val.hg_wakeup_int_sel; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_HG_FUNCTIONS_ENABLE, (uint8_t *)&hg_func, 1); + + return ret; +} + +/** + * @brief High-g wake-up interrupt configuration[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val ism6hg256x_hg_wu_interrupt_cfg_t. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_hg_wu_interrupt_cfg_get(const stmdev_ctx_t *ctx, + ism6hg256x_hg_wu_interrupt_cfg_t *val) +{ + ism6hg256x_hg_functions_enable_t hg_func; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_HG_FUNCTIONS_ENABLE, (uint8_t *)&hg_func, 1); + if (ret != 0) + { + return ret; + } + + val->hg_interrupts_enable = hg_func.hg_interrupts_enable; + val->hg_wakeup_int_sel = hg_func.hg_wu_change_int_sel; + + return ret; +} + +/** + * @brief Emable/disable user offset data correction driving to hg embedded functions[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val 0: disable, 1: enable + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_hg_emb_usr_off_correction_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_emb_func_cfg_t emb_func_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + + if (ret == 0) + { + emb_func_cfg.hg_usr_off_on_emb_func = (uint8_t)val & 0x1U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + return ret; +} + +/** + * @brief Emable/disable user offset data correction driving to hg embedded functions[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val 0: disable, 1: enable + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_hg_emb_usr_off_correction_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_emb_func_cfg_t emb_func_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } + + *val = emb_func_cfg.hg_usr_off_on_emb_func; + + return ret; +} + +/** + * @brief Emable/disable user offset data correction driving to hg wake-up[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val 0: disable, 1: enable + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_hg_wu_usr_off_correction_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_ctrl2_xl_hg_t ctrl2_xl_hg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL2_XL_HG, (uint8_t *)&ctrl2_xl_hg, 1); + + if (ret == 0) + { + ctrl2_xl_hg.hg_usr_off_on_wu = (uint8_t)val & 0x1U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL2_XL_HG, (uint8_t *)&ctrl2_xl_hg, 1); + } + + return ret; +} + +/** + * @brief Emable/disable user offset data correction driving to hg wake-up[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val 0: disable, 1: enable + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_hg_wu_usr_off_correction_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_ctrl2_xl_hg_t ctrl2_xl_hg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL2_XL_HG, (uint8_t *)&ctrl2_xl_hg, 1); + if (ret != 0) + { + return ret; + } + + *val = ctrl2_xl_hg.hg_usr_off_on_wu; + + return ret; +} + +/** + * @brief High-g event handling[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val High-g event. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_hg_event_get(const stmdev_ctx_t *ctx, ism6hg256x_hg_event_t *val) +{ + ism6hg256x_all_int_src_t int_src; + ism6hg256x_hg_wake_up_src_t wup_src; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_ALL_INT_SRC, (uint8_t *)&int_src, 1); + if (ret != 0) + { + return ret; + } + + val->hg_event = int_src.hg_ia; + + /* no High-g event */ + if (int_src.hg_ia != 0) + { + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_HG_WAKE_UP_SRC, (uint8_t *)&wup_src, 1); + if (ret != 0) + { + return ret; + } + + val->hg_wakeup_z = wup_src.hg_z_wu; + val->hg_wakeup_y = wup_src.hg_y_wu; + val->hg_wakeup_x = wup_src.hg_x_wu; + val->hg_wakeup = wup_src.hg_wu_ia; + val->hg_wakeup_chg = wup_src.hg_wu_change_ia; + val->hg_shock = wup_src.hg_shock_state; + val->hg_shock_change = wup_src.hg_shock_change_ia; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup interrupt_pins + * @brief This section groups all the functions that manage + * interrupt pins + * @{ + * + */ + +/** + * @brief Select the signals that need to be routed on int1 pad.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int1 pin. + * (xl/g drdy, fifo, 6d/tap/wu/ff/sleep_change/cnt_bdr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_pin_int1_route_set(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val) +{ + ism6hg256x_int1_ctrl_t int1_ctrl; + ism6hg256x_md1_cfg_t md1_cfg; + int32_t ret; + + /* not available on INT1 */ + if (val->drdy_temp == 1) + { + return -1; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) + { + return ret; + } + + int1_ctrl.int1_drdy_xl = val->drdy_xl; + int1_ctrl.int1_drdy_g = val->drdy_g; + int1_ctrl.int1_fifo_th = val->fifo_th; + int1_ctrl.int1_fifo_ovr = val->fifo_ovr; + int1_ctrl.int1_fifo_full = val->fifo_full; + int1_ctrl.int1_cnt_bdr = val->cnt_bdr; + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + if (ret != 0) + { + return ret; + } + + md1_cfg.int1_shub = val->shub; + md1_cfg.int1_6d = val->sixd; + md1_cfg.int1_single_tap = val->single_tap; + md1_cfg.int1_double_tap = val->double_tap; + md1_cfg.int1_wu = val->wakeup; + md1_cfg.int1_ff = val->freefall; + md1_cfg.int1_sleep_change = val->sleep_change; + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + return ret; +} + +/** + * @brief Report the signals that are routed on int1 pad.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals that are routed on int1 pin.(ptr) + * (xl/g drdy, fifo, 6d/tap/wu/ff/sleep_change/cnt_bdr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_pin_int1_route_get(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val) +{ + ism6hg256x_int1_ctrl_t int1_ctrl; + ism6hg256x_md1_cfg_t md1_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) + { + return ret; + } + + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_g = int1_ctrl.int1_drdy_g; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->cnt_bdr = int1_ctrl.int1_cnt_bdr; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + if (ret != 0) + { + return ret; + } + + val->shub = md1_cfg.int1_shub; + val->sixd = md1_cfg.int1_6d; + val->single_tap = md1_cfg.int1_single_tap; + val->double_tap = md1_cfg.int1_double_tap; + val->wakeup = md1_cfg.int1_wu; + val->freefall = md1_cfg.int1_ff; + val->sleep_change = md1_cfg.int1_sleep_change; + + return ret; +} + +/** + * @brief Select the signals that need to be routed on int2 pad.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int1 pin. + * (xl/g drdy, fifo, 6d/tap/wu/ff/sleep_change/cnt_bdr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_pin_int2_route_set(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val) +{ + ism6hg256x_int2_ctrl_t int2_ctrl; + ism6hg256x_ctrl4_t ctrl4; + ism6hg256x_md2_cfg_t md2_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) + { + return ret; + } + + int2_ctrl.int2_drdy_xl = val->drdy_xl; + int2_ctrl.int2_drdy_g = val->drdy_g; + int2_ctrl.int2_fifo_th = val->fifo_th; + int2_ctrl.int2_fifo_ovr = val->fifo_ovr; + int2_ctrl.int2_fifo_full = val->fifo_full; + int2_ctrl.int2_cnt_bdr = val->cnt_bdr; + int2_ctrl.int2_drdy_g_eis = val->drdy_g_eis; + int2_ctrl.int2_emb_func_endop = val->emb_func_endop; + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + ctrl4.int2_drdy_temp = val->drdy_temp; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) + { + return ret; + } + + md2_cfg.int2_timestamp = val->timestamp; + md2_cfg.int2_6d = val->sixd; + md2_cfg.int2_single_tap = val->single_tap; + md2_cfg.int2_double_tap = val->double_tap; + md2_cfg.int2_wu = val->wakeup; + md2_cfg.int2_ff = val->freefall; + md2_cfg.int2_sleep_change = val->sleep_change; + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + + return ret; +} + +/** + * @brief Report the signals that are routed on int2 pad.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals that are routed on int1 pin.(ptr) + * (xl/g drdy, fifo, 6d/tap/wu/ff/sleep_change/cnt_bdr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_pin_int2_route_get(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val) +{ + ism6hg256x_int2_ctrl_t int2_ctrl; + ism6hg256x_ctrl4_t ctrl4; + ism6hg256x_md2_cfg_t md2_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) + { + return ret; + } + + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_g = int2_ctrl.int2_drdy_g; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->cnt_bdr = int2_ctrl.int2_cnt_bdr; + val->drdy_g_eis = int2_ctrl.int2_drdy_g_eis; + val->emb_func_endop = int2_ctrl.int2_emb_func_endop; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + + val->drdy_temp = ctrl4.int2_drdy_temp; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) + { + return ret; + } + + val->timestamp = md2_cfg.int2_timestamp; + val->sixd = md2_cfg.int2_6d; + val->single_tap = md2_cfg.int2_single_tap; + val->double_tap = md2_cfg.int2_double_tap; + val->wakeup = md2_cfg.int2_wu; + val->freefall = md2_cfg.int2_ff; + val->sleep_change = md2_cfg.int2_sleep_change; + + return ret; +} + +/** + * @brief Select the signals that need to be routed on int1 pad.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int1 pin. + * (HG events only) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_pin_int1_route_hg_set(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val) +{ + ism6hg256x_ctrl7_t ctrl7; + ism6hg256x_hg_functions_enable_t hg_func; + ism6hg256x_inactivity_ths_t reg_shock; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + + ctrl7.int1_drdy_xl_hg = val->drdy_hg_xl; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_HG_FUNCTIONS_ENABLE, (uint8_t *)&hg_func, 1); + if (ret != 0) + { + return ret; + } + + hg_func.int1_hg_wu = val->hg_wakeup; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_HG_FUNCTIONS_ENABLE, (uint8_t *)&hg_func, 1); + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INACTIVITY_THS, (uint8_t *)®_shock, 1); + if (ret != 0) + { + return ret; + } + + reg_shock.int1_hg_shock_change = val->hg_shock_change; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_INACTIVITY_THS, (uint8_t *)®_shock, 1); + + return ret; +} + +/** + * @brief Report the signals that are routed on int1 pad.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals that are routed on int1 pin.(ptr) + * (HG events only) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_pin_int1_route_hg_get(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val) +{ + ism6hg256x_ctrl7_t ctrl7; + ism6hg256x_hg_functions_enable_t hg_func; + ism6hg256x_inactivity_ths_t reg_shock; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + + val->drdy_hg_xl = ctrl7.int1_drdy_xl_hg; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_HG_FUNCTIONS_ENABLE, (uint8_t *)&hg_func, 1); + if (ret != 0) + { + return ret; + } + + val->hg_wakeup = hg_func.int1_hg_wu; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INACTIVITY_THS, (uint8_t *)®_shock, 1); + if (ret != 0) + { + return ret; + } + + val->hg_shock_change = reg_shock.int1_hg_shock_change; + + return ret; +} + +/** + * @brief Select the signals that need to be routed on int2 pad.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int2 pin. + * (HG events only) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_pin_int2_route_hg_set(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val) +{ + ism6hg256x_ctrl7_t ctrl7; + ism6hg256x_hg_functions_enable_t hg_func; + ism6hg256x_inactivity_ths_t reg_shock; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + + ctrl7.int2_drdy_xl_hg = val->drdy_hg_xl; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL7, (uint8_t *)&ctrl7, 1); + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_HG_FUNCTIONS_ENABLE, (uint8_t *)&hg_func, 1); + if (ret != 0) + { + return ret; + } + + hg_func.int2_hg_wu = val->hg_wakeup; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_HG_FUNCTIONS_ENABLE, (uint8_t *)&hg_func, 1); + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INACTIVITY_THS, (uint8_t *)®_shock, 1); + if (ret != 0) + { + return ret; + } + + reg_shock.int2_hg_shock_change = val->hg_shock_change; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_INACTIVITY_THS, (uint8_t *)®_shock, 1); + + return ret; +} + +/** + * @brief Report the signals that are routed on int2 pad.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals that are routed on int2 pin.(ptr) + * (HG events only) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_pin_int2_route_hg_get(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val) +{ + ism6hg256x_ctrl7_t ctrl7; + ism6hg256x_hg_functions_enable_t hg_func; + ism6hg256x_inactivity_ths_t reg_shock; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + + val->drdy_hg_xl = ctrl7.int2_drdy_xl_hg; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_HG_FUNCTIONS_ENABLE, (uint8_t *)&hg_func, 1); + if (ret != 0) + { + return ret; + } + + val->hg_wakeup = hg_func.int2_hg_wu; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INACTIVITY_THS, (uint8_t *)®_shock, 1); + if (ret != 0) + { + return ret; + } + + val->hg_shock_change = reg_shock.int2_hg_shock_change; + + return ret; +} + +/** + * @brief Select the signals that need to be routed on int1 pad.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int1 pin. + * (embedded events) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_pin_int1_route_embedded_set(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val) +{ + ism6hg256x_md1_cfg_t md1_cfg; + ism6hg256x_emb_func_int1_t emb_func_int1; + ism6hg256x_fsm_int1_t fsm_int1; + ism6hg256x_mlc_int1_t mlc_int1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + if (ret != 0) + { + return ret; + } + + md1_cfg.int1_emb_func = 1; + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + if (ret != 0) + { + return ret; + } + + /* Embedded Functions */ + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + if (ret != 0) + { + goto exit; + } + + emb_func_int1.int1_step_detector = val->step_detector; + emb_func_int1.int1_tilt = val->tilt; + emb_func_int1.int1_sig_mot = val->sig_mot; + + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + if (ret != 0) + { + goto exit; + } + + /* FSM */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_FSM_INT1, (uint8_t *)&fsm_int1, 1); + if (ret != 0) + { + goto exit; + } + + fsm_int1.int1_fsm1 = val->fsm1; + fsm_int1.int1_fsm2 = val->fsm2; + fsm_int1.int1_fsm3 = val->fsm3; + fsm_int1.int1_fsm4 = val->fsm4; + fsm_int1.int1_fsm5 = val->fsm5; + fsm_int1.int1_fsm6 = val->fsm6; + fsm_int1.int1_fsm7 = val->fsm7; + fsm_int1.int1_fsm8 = val->fsm8; + + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_FSM_INT1, (uint8_t *)&fsm_int1, 1); + if (ret != 0) + { + goto exit; + } + + /* MLC */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_MLC_INT1, (uint8_t *)&mlc_int1, 1); + if (ret != 0) + { + goto exit; + } + + mlc_int1.int1_mlc1 = val->mlc1; + mlc_int1.int1_mlc2 = val->mlc2; + mlc_int1.int1_mlc3 = val->mlc3; + mlc_int1.int1_mlc4 = val->mlc4; + mlc_int1.int1_mlc5 = val->mlc5; + mlc_int1.int1_mlc6 = val->mlc6; + mlc_int1.int1_mlc7 = val->mlc7; + mlc_int1.int1_mlc8 = val->mlc8; + + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_MLC_INT1, (uint8_t *)&mlc_int1, 1); + if (ret != 0) + { + goto exit; + } + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Report the signals that are routed on int1 pad.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int1 pin. + * (embedded events) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_pin_int1_route_embedded_get(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val) +{ + ism6hg256x_emb_func_int1_t emb_func_int1; + ism6hg256x_fsm_int1_t fsm_int1; + ism6hg256x_mlc_int1_t mlc_int1; + int32_t ret; + + /* Embedded Functions */ + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + if (ret != 0) + { + goto exit; + } + + val->step_detector = emb_func_int1.int1_step_detector; + val->sig_mot = emb_func_int1.int1_sig_mot; + val->tilt = emb_func_int1.int1_tilt; + + /* FSM */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_FSM_INT1, (uint8_t *)&fsm_int1, 1); + if (ret != 0) + { + goto exit; + } + + val->fsm1 = fsm_int1.int1_fsm1; + val->fsm2 = fsm_int1.int1_fsm2; + val->fsm3 = fsm_int1.int1_fsm3; + val->fsm4 = fsm_int1.int1_fsm4; + val->fsm5 = fsm_int1.int1_fsm5; + val->fsm6 = fsm_int1.int1_fsm6; + val->fsm7 = fsm_int1.int1_fsm7; + val->fsm8 = fsm_int1.int1_fsm8; + + /* MLC */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_MLC_INT1, (uint8_t *)&mlc_int1, 1); + if (ret != 0) + { + goto exit; + } + + val->mlc1 = mlc_int1.int1_mlc1; + val->mlc2 = mlc_int1.int1_mlc2; + val->mlc3 = mlc_int1.int1_mlc3; + val->mlc4 = mlc_int1.int1_mlc4; + val->mlc5 = mlc_int1.int1_mlc5; + val->mlc6 = mlc_int1.int1_mlc6; + val->mlc7 = mlc_int1.int1_mlc7; + val->mlc8 = mlc_int1.int1_mlc8; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Select the signals that need to be routed on int2 pad[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int2 pin. + * (embedded events) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_pin_int2_route_embedded_set(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val) +{ + ism6hg256x_md2_cfg_t md2_cfg; + ism6hg256x_emb_func_int2_t emb_func_int2; + ism6hg256x_fsm_int2_t fsm_int2; + ism6hg256x_mlc_int2_t mlc_int2; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) + { + return ret; + } + + md2_cfg.int2_emb_func = 1; + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) + { + return ret; + } + + /* Embedded Functions */ + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + if (ret != 0) + { + goto exit; + } + + emb_func_int2.int2_step_detector = val->step_detector; + emb_func_int2.int2_tilt = val->tilt; + emb_func_int2.int2_sig_mot = val->sig_mot; + + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + if (ret != 0) + { + goto exit; + } + + /* FSM */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_FSM_INT2, (uint8_t *)&fsm_int2, 1); + if (ret != 0) + { + goto exit; + } + + fsm_int2.int2_fsm1 = val->fsm1; + fsm_int2.int2_fsm2 = val->fsm2; + fsm_int2.int2_fsm3 = val->fsm3; + fsm_int2.int2_fsm4 = val->fsm4; + fsm_int2.int2_fsm5 = val->fsm5; + fsm_int2.int2_fsm6 = val->fsm6; + fsm_int2.int2_fsm7 = val->fsm7; + fsm_int2.int2_fsm8 = val->fsm8; + + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_FSM_INT2, (uint8_t *)&fsm_int2, 1); + if (ret != 0) + { + goto exit; + } + + /* MLC */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_MLC_INT2, (uint8_t *)&mlc_int2, 1); + if (ret != 0) + { + goto exit; + } + + mlc_int2.int2_mlc1 = val->mlc1; + mlc_int2.int2_mlc2 = val->mlc2; + mlc_int2.int2_mlc3 = val->mlc3; + mlc_int2.int2_mlc4 = val->mlc4; + mlc_int2.int2_mlc5 = val->mlc5; + mlc_int2.int2_mlc6 = val->mlc6; + mlc_int2.int2_mlc7 = val->mlc7; + mlc_int2.int2_mlc8 = val->mlc8; + + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_MLC_INT2, (uint8_t *)&mlc_int2, 1); + if (ret != 0) + { + goto exit; + } + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Report the signals that are routed on int2 pad.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int2 pin. + * (embedded events) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t ism6hg256x_pin_int2_route_embedded_get(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val) +{ + ism6hg256x_emb_func_int2_t emb_func_int2; + ism6hg256x_fsm_int2_t fsm_int2; + ism6hg256x_mlc_int2_t mlc_int2; + int32_t ret; + + /* Embedded Functions */ + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + if (ret != 0) + { + goto exit; + } + + val->step_detector = emb_func_int2.int2_step_detector; + val->sig_mot = emb_func_int2.int2_sig_mot; + val->tilt = emb_func_int2.int2_tilt; + + /* FSM */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_FSM_INT2, (uint8_t *)&fsm_int2, 1); + if (ret != 0) + { + goto exit; + } + + val->fsm1 = fsm_int2.int2_fsm1; + val->fsm2 = fsm_int2.int2_fsm2; + val->fsm3 = fsm_int2.int2_fsm3; + val->fsm4 = fsm_int2.int2_fsm4; + val->fsm5 = fsm_int2.int2_fsm5; + val->fsm6 = fsm_int2.int2_fsm6; + val->fsm7 = fsm_int2.int2_fsm7; + val->fsm8 = fsm_int2.int2_fsm8; + + /* MLC */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_MLC_INT2, (uint8_t *)&mlc_int2, 1); + if (ret != 0) + { + goto exit; + } + + val->mlc1 = mlc_int2.int2_mlc1; + val->mlc2 = mlc_int2.int2_mlc2; + val->mlc3 = mlc_int2.int2_mlc3; + val->mlc4 = mlc_int2.int2_mlc4; + val->mlc5 = mlc_int2.int2_mlc5; + val->mlc6 = mlc_int2.int2_mlc6; + val->mlc7 = mlc_int2.int2_mlc7; + val->mlc8 = mlc_int2.int2_mlc8; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @brief Get the status of all the interrupt sources.[get] + * + * @param ctx read / write interface definitions + * @param val Get the status of all the interrupt sources. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_all_sources_get(const stmdev_ctx_t *ctx, + ism6hg256x_all_sources_t *val) +{ + ism6hg256x_emb_func_status_mainpage_t emb_func_status_mainpage; + ism6hg256x_emb_func_exec_status_t emb_func_exec_status; + ism6hg256x_fsm_status_mainpage_t fsm_status_mainpage; + ism6hg256x_mlc_status_mainpage_t mlc_status_mainpage; + ism6hg256x_functions_enable_t functions_enable; + ism6hg256x_emb_func_src_t emb_func_src; + ism6hg256x_fifo_status2_t fifo_status2; + ism6hg256x_all_int_src_t all_int_src; + ism6hg256x_wake_up_src_t wake_up_src; + ism6hg256x_status_reg_t status_reg; + ism6hg256x_d6d_src_t d6d_src; + ism6hg256x_tap_src_t tap_src; + ism6hg256x_ui_status_reg_ois_t status_reg_ois; + ism6hg256x_status_controller_t status_shub; + uint8_t buff[8]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + + functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_STATUS1, (uint8_t *)&buff, 4); + if (ret != 0) + { + return ret; + } + + bytecpy((uint8_t *)&fifo_status2, &buff[1]); + bytecpy((uint8_t *)&all_int_src, &buff[2]); + bytecpy((uint8_t *)&status_reg, &buff[3]); + + val->fifo_ovr = fifo_status2.fifo_ovr_ia; + val->fifo_bdr = fifo_status2.counter_bdr_ia; + val->fifo_full = fifo_status2.fifo_full_ia; + val->fifo_th = fifo_status2.fifo_wtm_ia; + + val->hg = all_int_src.hg_ia; + val->free_fall = all_int_src.ff_ia; + val->wake_up = all_int_src.wu_ia; + val->six_d = all_int_src.d6d_ia; + + val->drdy_xl = status_reg.xlda; + val->drdy_gy = status_reg.gda; + val->drdy_temp = status_reg.tda; + val->drdy_xlhgda = status_reg.xlhgda; + val->drdy_eis = status_reg.gda_eis; + val->drdy_ois = status_reg.ois_drdy; + val->timestamp = status_reg.timestamp_endcount; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + + functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_STATUS_REG_OIS, (uint8_t *)&buff, 8); + if (ret != 0) + { + return ret; + } + + bytecpy((uint8_t *)&status_reg_ois, &buff[0]); + bytecpy((uint8_t *)&wake_up_src, &buff[1]); + bytecpy((uint8_t *)&tap_src, &buff[2]); + bytecpy((uint8_t *)&d6d_src, &buff[3]); + bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[5]); + bytecpy((uint8_t *)&fsm_status_mainpage, &buff[6]); + bytecpy((uint8_t *)&mlc_status_mainpage, &buff[7]); + + val->gy_settling = status_reg_ois.gyro_settling; + val->sleep_change = wake_up_src.sleep_change_ia; + val->wake_up_x = wake_up_src.x_wu; + val->wake_up_y = wake_up_src.y_wu; + val->wake_up_z = wake_up_src.z_wu; + val->sleep_state = wake_up_src.sleep_state; + + val->tap_x = tap_src.x_tap; + val->tap_y = tap_src.y_tap; + val->tap_z = tap_src.z_tap; + val->tap_sign = tap_src.tap_sign; + val->double_tap = tap_src.double_tap; + val->single_tap = tap_src.single_tap; + + val->six_d_zl = d6d_src.zl; + val->six_d_zh = d6d_src.zh; + val->six_d_yl = d6d_src.yl; + val->six_d_yh = d6d_src.yh; + val->six_d_xl = d6d_src.xl; + val->six_d_xh = d6d_src.xh; + + val->step_detector = emb_func_status_mainpage.is_step_det; + val->tilt = emb_func_status_mainpage.is_tilt; + val->sig_mot = emb_func_status_mainpage.is_sigmot; + val->fsm_lc = emb_func_status_mainpage.is_fsm_lc; + + val->fsm1 = fsm_status_mainpage.is_fsm1; + val->fsm2 = fsm_status_mainpage.is_fsm2; + val->fsm3 = fsm_status_mainpage.is_fsm3; + val->fsm4 = fsm_status_mainpage.is_fsm4; + val->fsm5 = fsm_status_mainpage.is_fsm5; + val->fsm6 = fsm_status_mainpage.is_fsm6; + val->fsm7 = fsm_status_mainpage.is_fsm7; + val->fsm8 = fsm_status_mainpage.is_fsm8; + + val->mlc1 = mlc_status_mainpage.is_mlc1; + val->mlc2 = mlc_status_mainpage.is_mlc2; + val->mlc3 = mlc_status_mainpage.is_mlc3; + val->mlc4 = mlc_status_mainpage.is_mlc4; + val->mlc5 = mlc_status_mainpage.is_mlc5; + val->mlc6 = mlc_status_mainpage.is_mlc6; + val->mlc7 = mlc_status_mainpage.is_mlc7; + val->mlc8 = mlc_status_mainpage.is_mlc8; + + + /* embedded func */ + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, + 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; + val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; + val->step_count_inc = emb_func_src.stepcounter_bit_set; + val->step_count_overflow = emb_func_src.step_overflow; + val->step_on_delta_time = emb_func_src.step_count_delta_ia; + + val->step_detector = emb_func_src.step_detected; + + /* sensor hub */ + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_STATUS_CONTROLLER_MAINPAGE, (uint8_t *)&status_shub, 1); + if (ret != 0) + { + return ret; + } + + val->sh_endop = status_shub.sens_hub_endop; + val->sh_wr_once = status_shub.wr_once_done; + val->sh_target3_nack = status_shub.target3_nack; + val->sh_target2_nack = status_shub.target2_nack; + val->sh_target1_nack = status_shub.target1_nack; + val->sh_target0_nack = status_shub.target0_nack; + + return ret; +} + +int32_t ism6hg256x_flag_data_ready_get(const stmdev_ctx_t *ctx, + ism6hg256x_data_ready_t *val) +{ + ism6hg256x_status_reg_t status; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_STATUS_REG, (uint8_t *)&status, 1); + if (ret != 0) + { + return ret; + } + + val->drdy_hgxl = status.xlhgda; + val->drdy_xl = status.xlda; + val->drdy_gy = status.gda; + val->drdy_temp = status.tda; + + return ret; +} + +/** + * @brief Mask status bit reset[set] + * + * @param ctx read / write interface definitions + * @param val Mask to prevent status bit being reset + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_INT_ACK_MASK, &val, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Mask status bit reset[get] + * + * @param ctx read / write interface definitions + * @param val Mask to prevent status bit being reset + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_INT_ACK_MASK, val, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Temperature data output register[get] + * + * @param ctx read / write interface definitions + * @param val Temperature data output register + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_OUT_TEMP_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_OUTX_L_G, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val OIS Angular rate sensor (thru IF2). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF2_OUTX_L_G_OIS, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (*val * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (*val * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (*val * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Angular rate sensor for OIS gyro or the EIS gyro channel.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor for OIS gyro or the EIS gyro channel. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_eis_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_OUTX_L_G_OIS_EIS, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (*val * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (*val * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (*val * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_OUTX_L_A, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor for hg channel mode.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor or High-G channel mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_hg_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_OUTX_L_A_OIS_HG, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor for OIS channel mode.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor or OIS channel mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_OUTX_L_A_OIS_HG, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief SFLP gbias.[get] + * + * @param ctx read / write interface definitions + * @param val SFLP gbias raw array. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sflp_gbias_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_SFLP_GBIASX_L, &buff[0], 6); + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief SFLP gravity.[get] + * + * @param ctx read / write interface definitions + * @param val SFLP gravity raw array. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sflp_gravity_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_SFLP_GRAVX_L, &buff[0], 6); + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief SFLP raw quaternions.[get] + * + * @param ctx read / write interface definitions + * @param val pointer to SFLP quaternions raw array. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sflp_quaternion_raw_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[8]; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_SFLP_QUATW_L, &buff[0], 8); + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + val[0] = (uint16_t)buff[1]; + val[0] = (val[0] * 256) + (uint16_t)buff[0]; + val[1] = (uint16_t)buff[3]; + val[1] = (val[1] * 256) + (uint16_t)buff[2]; + val[2] = (uint16_t)buff[5]; + val[2] = (val[2] * 256) + (uint16_t)buff[4]; + val[3] = (uint16_t)buff[7]; + val[3] = (val[3] * 256) + (uint16_t)buff[6]; + + return ret; +} + +/** + * @brief SFLP quaternions.[get] + * + * @param ctx read / write interface definitions + * @param val pointer to SFLP quaternions raw array. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sflp_quaternion_get(const stmdev_ctx_t *ctx, ism6hg256x_quaternion_t *quat) +{ + uint16_t val[4]; + int32_t ret; + + ret = ism6hg256x_sflp_quaternion_raw_get(ctx, val); + if (ret != 0) + { + return ret; + } + + quat->quat_w = ism6hg256x_from_quaternion_lsb_to_float(val[0]); + quat->quat_x = ism6hg256x_from_quaternion_lsb_to_float(val[1]); + quat->quat_y = ism6hg256x_from_quaternion_lsb_to_float(val[2]); + quat->quat_z = ism6hg256x_from_quaternion_lsb_to_float(val[3]); + + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get] + * + * @param ctx read / write interface definitions + * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) +{ + ism6hg256x_internal_freq_t internal_freq; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + if (ret != 0) + { + return ret; + } + + *val = (int8_t)internal_freq.freq_fine; + + return ret; +} + +/** + * @defgroup Common + * @brief This section groups common useful functions. + * @{/ + * + */ + +/** + * @brief Disable Embedded functions.[set] + * + * @param ctx read / write interface definitions + * @param val 1 (disable) or 0 (enable) embedded functions + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_disable_embedded_function_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_emb_func_cfg_t emb_func_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } + + emb_func_cfg.emb_func_disable = val & 0x1U; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + + return ret; +} + +/** + * @brief Disable Embedded functions.[get] + * + * @param ctx read / write interface definitions + * @param val 1 (disable) or 0 (enable) embedded functions + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_disable_embedded_function_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_emb_func_cfg_t emb_func_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } + + *val = emb_func_cfg.emb_func_disable; + + return ret; +} + +/** + * @brief Enable/Disable embedded function sensor conversion.[set] + * + * @param ctx read / write interface definitions + * @param val 0 (disable) or 1 (enable) embedded functions sensor conversion + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_emb_func_conv_set(const stmdev_ctx_t *ctx, ism6hg256x_emb_func_conv_t val) +{ + ism6hg256x_emb_func_sensor_conv_en_t conv_reg; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_SENSOR_CONV_EN, (uint8_t *)&conv_reg, 1); + if (ret != 0) + { + goto exit; + } + conv_reg.xl_hg_conv_en = val.xl_hg_conv_en; + conv_reg.gyro_conv_en = val.gyro_conv_en; + conv_reg.temp_conv_en = val.temp_conv_en; + conv_reg.ext_sensor_conv_en = val.ext_sensor_conv_en; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_SENSOR_CONV_EN, (uint8_t *)&conv_reg, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable/Disable embedded function sensor conversion.[get] + * + * @param ctx read / write interface definitions + * @param val 0 (disable) or 1 (enable) embedded functions sensor conversion + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_emb_func_conv_get(const stmdev_ctx_t *ctx, ism6hg256x_emb_func_conv_t *val) +{ + ism6hg256x_emb_func_sensor_conv_en_t conv_reg; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_SENSOR_CONV_EN, (uint8_t *)&conv_reg, 1); + if (ret != 0) + { + goto exit; + } + val->xl_hg_conv_en = conv_reg.xl_hg_conv_en; + val->gyro_conv_en = conv_reg.gyro_conv_en; + val->temp_conv_en = conv_reg.temp_conv_en; + val->ext_sensor_conv_en = conv_reg.ext_sensor_conv_en; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Write buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + ism6hg256x_page_address_t page_address; + ism6hg256x_page_sel_t page_sel; + ism6hg256x_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + /* set page write */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + + /* set page addr */ + page_address.page_addr = lsb; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_VALUE, &buf[i], 1); + if (ret != 0) + { + goto exit; + } + + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + + /* unset page write */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Read buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, + uint8_t len) +{ + ism6hg256x_page_address_t page_address; + ism6hg256x_page_sel_t page_sel; + ism6hg256x_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + /* set page write */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } + page_rw.page_read = PROPERTY_ENABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } + + /* select page */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + + /* set page addr */ + page_address.page_addr = lsb; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_PAGE_VALUE, &buf[i], 1); + if (ret != 0) + { + goto exit; + } + + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + + /* unset page write */ + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable debug mode for embedded functions [set] + * + * @param ctx read / write interface definitions + * @param val 0, 1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_emb_function_dbg_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_ctrl10_t ctrl10; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.emb_func_debug = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Enable debug mode for embedded functions [get] + * + * @param ctx read / write interface definitions + * @param val 0, 1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_emb_function_dbg_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_ctrl10_t ctrl10; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } + + *val = ctrl10.emb_func_debug; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Data ENable (DEN) + * @brief This section groups all the functions concerning + * DEN functionality. + * @{ + * + */ + +/** + * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[set] + * + * @param ctx read / write interface definitions + * @param val DEN_ACT_LOW, DEN_ACT_HIGH, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_den_polarity_set(const stmdev_ctx_t *ctx, + ism6hg256x_den_polarity_t val) +{ + ism6hg256x_ctrl4_t ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.int2_in_lh = (uint8_t)val & 0x1U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[get] + * + * @param ctx read / write interface definitions + * @param val DEN_ACT_LOW, DEN_ACT_HIGH, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_den_polarity_get(const stmdev_ctx_t *ctx, + ism6hg256x_den_polarity_t *val) +{ + ism6hg256x_ctrl4_t ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl4.int2_in_lh) + { + case ISM6HG256X_DEN_ACT_LOW: + *val = ISM6HG256X_DEN_ACT_LOW; + break; + + case ISM6HG256X_DEN_ACT_HIGH: + *val = ISM6HG256X_DEN_ACT_HIGH; + break; + + default: + *val = ISM6HG256X_DEN_ACT_LOW; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Electronic Image Stabilization (EIS) + * @brief Electronic Image Stabilization (EIS) + * @{/ + * + */ + +/** + * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[set] + * + * @param ctx read / write interface definitions + * @param val 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_eis_gy_full_scale_set(const stmdev_ctx_t *ctx, + ism6hg256x_eis_gy_full_scale_t val) +{ + ism6hg256x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.fs_g_eis = (uint8_t)val & 0x7U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[get] + * + * @param ctx read / write interface definitions + * @param val 250dps, 500dps, 1000dps, 2000dps, 4000dps + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_eis_gy_full_scale_get(const stmdev_ctx_t *ctx, + ism6hg256x_eis_gy_full_scale_t *val) +{ + ism6hg256x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl_eis.fs_g_eis) + { + case 1: + *val = ISM6HG256X_EIS_250dps; + break; + + case 2: + *val = ISM6HG256X_EIS_500dps; + break; + + case 3: + *val = ISM6HG256X_EIS_1000dps; + break; + + case 4: + *val = ISM6HG256X_EIS_2000dps; + break; + + case 5: + *val = ISM6HG256X_EIS_4000dps; + break; + + default: + *val = ISM6HG256X_EIS_250dps; + break; + } + return ret; +} + +/** + * @brief Enables routing of gyroscope EIS outputs on IF2 (OIS interface). The gyroscope data on IF2 (OIS interface) cannot be read from User Interface (UI).[set] + * + * @param ctx read / write interface definitions + * @param val Enables routing of gyroscope EIS outputs on IF2 (OIS interface). The gyroscope data on IF2 (OIS interface) cannot be read from User Interface (UI). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_eis_gy_on_if2_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.g_eis_on_g_ois_out_reg = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Enables routing of gyroscope EIS outputs on IF2 (OIS interface). The gyroscope data on IF2 (OIS interface) cannot be read from User Interface (UI).[get] + * + * @param ctx read / write interface definitions + * @param val Enables routing of gyroscope EIS outputs on IF2 (OIS interface). The gyroscope data on IF2 (OIS interface) cannot be read from User Interface (UI). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_eis_gy_on_if2_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + if (ret != 0) + { + return ret; + } + + *val = ctrl_eis.g_eis_on_g_ois_out_reg; + + return ret; +} + +/** + * @brief Enables and selects the ODR of the gyroscope EIS channel.[set] + * + * @param ctx read / write interface definitions + * @param val EIS_1920Hz, EIS_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_gy_eis_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_gy_eis_data_rate_t val) +{ + ism6hg256x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.odr_g_eis = (uint8_t)val & 0x03U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Enables and selects the ODR of the gyroscope EIS channel.[get] + * + * @param ctx read / write interface definitions + * @param val EIS_1920Hz, EIS_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_gy_eis_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_gy_eis_data_rate_t *val) +{ + ism6hg256x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl_eis.odr_g_eis) + { + case ISM6HG256X_EIS_ODR_OFF: + *val = ISM6HG256X_EIS_ODR_OFF; + break; + + case ISM6HG256X_EIS_1920Hz: + *val = ISM6HG256X_EIS_1920Hz; + break; + + case ISM6HG256X_EIS_960Hz: + *val = ISM6HG256X_EIS_960Hz; + break; + + default: + *val = ISM6HG256X_EIS_1920Hz; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO + * @brief This section group all the functions concerning the FIFO usage + * @{ + * + */ + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + + if (ret == 0) + { + fifo_ctrl1.wtm = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) + { + return ret; + } + + *val = fifo_ctrl1.wtm; + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[set] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_compress_algo_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_compress_algo_t val) +{ + ism6hg256x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[get] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_compress_algo_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_compress_algo_t *val) +{ + ism6hg256x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + + switch (fifo_ctrl2.uncompr_rate) + { + case ISM6HG256X_CMP_DISABLE: + *val = ISM6HG256X_CMP_DISABLE; + break; + + case ISM6HG256X_CMP_8_TO_1: + *val = ISM6HG256X_CMP_8_TO_1; + break; + + case ISM6HG256X_CMP_16_TO_1: + *val = ISM6HG256X_CMP_16_TO_1; + break; + + case ISM6HG256X_CMP_32_TO_1: + *val = ISM6HG256X_CMP_32_TO_1; + break; + + default: + *val = ISM6HG256X_CMP_DISABLE; + break; + } + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.odr_chg_en = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + ism6hg256x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + + *val = fifo_ctrl2.odr_chg_en; + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[set] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val) +{ + ism6hg256x_emb_func_en_b_t emb_func_en_b; + ism6hg256x_fifo_ctrl2_t fifo_ctrl2; + + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + fifo_ctrl2.fifo_compr_rt_en = val; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + if (ret != 0) + { + goto exit; + } + emb_func_en_b.fifo_compr_en = val; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[get] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + ism6hg256x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + + *val = fifo_ctrl2.fifo_compr_rt_en; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[set] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, ism6hg256x_fifo_event_t val) +{ + ism6hg256x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.stop_on_wtm = (val == ISM6HG256X_FIFO_EV_WTM) ? 1 : 0; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[get] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, ism6hg256x_fifo_event_t *val) +{ + ism6hg256x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + + *val = (fifo_ctrl2.stop_on_wtm == 1) ? ISM6HG256X_FIFO_EV_WTM : ISM6HG256X_FIFO_EV_FULL; + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set] + * + * @param ctx read / write interface definitions + * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_xl_batch_t val) +{ + ism6hg256x_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFu; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get] + * + * @param ctx read / write interface definitions + * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_xl_batch_t *val) +{ + ism6hg256x_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + + switch (fifo_ctrl3.bdr_xl) + { + case ISM6HG256X_XL_NOT_BATCHED: + *val = ISM6HG256X_XL_NOT_BATCHED; + break; + + case ISM6HG256X_XL_BATCHED_AT_1Hz875: + *val = ISM6HG256X_XL_BATCHED_AT_1Hz875; + break; + + case ISM6HG256X_XL_BATCHED_AT_7Hz5: + *val = ISM6HG256X_XL_BATCHED_AT_7Hz5; + break; + + case ISM6HG256X_XL_BATCHED_AT_15Hz: + *val = ISM6HG256X_XL_BATCHED_AT_15Hz; + break; + + case ISM6HG256X_XL_BATCHED_AT_30Hz: + *val = ISM6HG256X_XL_BATCHED_AT_30Hz; + break; + + case ISM6HG256X_XL_BATCHED_AT_60Hz: + *val = ISM6HG256X_XL_BATCHED_AT_60Hz; + break; + + case ISM6HG256X_XL_BATCHED_AT_120Hz: + *val = ISM6HG256X_XL_BATCHED_AT_120Hz; + break; + + case ISM6HG256X_XL_BATCHED_AT_240Hz: + *val = ISM6HG256X_XL_BATCHED_AT_240Hz; + break; + + case ISM6HG256X_XL_BATCHED_AT_480Hz: + *val = ISM6HG256X_XL_BATCHED_AT_480Hz; + break; + + case ISM6HG256X_XL_BATCHED_AT_960Hz: + *val = ISM6HG256X_XL_BATCHED_AT_960Hz; + break; + + case ISM6HG256X_XL_BATCHED_AT_1920Hz: + *val = ISM6HG256X_XL_BATCHED_AT_1920Hz; + break; + + case ISM6HG256X_XL_BATCHED_AT_3840Hz: + *val = ISM6HG256X_XL_BATCHED_AT_3840Hz; + break; + + case ISM6HG256X_XL_BATCHED_AT_7680Hz: + *val = ISM6HG256X_XL_BATCHED_AT_7680Hz; + break; + + default: + *val = ISM6HG256X_XL_NOT_BATCHED; + break; + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set] + * + * @param ctx read / write interface definitions + * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_gy_batch_t val) +{ + ism6hg256x_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_gy = (uint8_t)val & 0x0Fu; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get] + * + * @param ctx read / write interface definitions + * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_gy_batch_t *val) +{ + ism6hg256x_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + + switch (fifo_ctrl3.bdr_gy) + { + case ISM6HG256X_GY_NOT_BATCHED: + *val = ISM6HG256X_GY_NOT_BATCHED; + break; + + case ISM6HG256X_GY_BATCHED_AT_1Hz875: + *val = ISM6HG256X_GY_BATCHED_AT_1Hz875; + break; + + case ISM6HG256X_GY_BATCHED_AT_7Hz5: + *val = ISM6HG256X_GY_BATCHED_AT_7Hz5; + break; + + case ISM6HG256X_GY_BATCHED_AT_15Hz: + *val = ISM6HG256X_GY_BATCHED_AT_15Hz; + break; + + case ISM6HG256X_GY_BATCHED_AT_30Hz: + *val = ISM6HG256X_GY_BATCHED_AT_30Hz; + break; + + case ISM6HG256X_GY_BATCHED_AT_60Hz: + *val = ISM6HG256X_GY_BATCHED_AT_60Hz; + break; + + case ISM6HG256X_GY_BATCHED_AT_120Hz: + *val = ISM6HG256X_GY_BATCHED_AT_120Hz; + break; + + case ISM6HG256X_GY_BATCHED_AT_240Hz: + *val = ISM6HG256X_GY_BATCHED_AT_240Hz; + break; + + case ISM6HG256X_GY_BATCHED_AT_480Hz: + *val = ISM6HG256X_GY_BATCHED_AT_480Hz; + break; + + case ISM6HG256X_GY_BATCHED_AT_960Hz: + *val = ISM6HG256X_GY_BATCHED_AT_960Hz; + break; + + case ISM6HG256X_GY_BATCHED_AT_1920Hz: + *val = ISM6HG256X_GY_BATCHED_AT_1920Hz; + break; + + case ISM6HG256X_GY_BATCHED_AT_3840Hz: + *val = ISM6HG256X_GY_BATCHED_AT_3840Hz; + break; + + case ISM6HG256X_GY_BATCHED_AT_7680Hz: + *val = ISM6HG256X_GY_BATCHED_AT_7680Hz; + break; + + default: + *val = ISM6HG256X_GY_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Enable FIFO Batch for hg XL data.[set] + * + * @param ctx read / write interface definitions + * @param val 0 (disable) / 1 (enabled) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_hg_xl_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_counter_bdr_reg1_t cbdr_reg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_COUNTER_BDR_REG1, (uint8_t *)&cbdr_reg, 1); + if (ret == 0) + { + cbdr_reg.xl_hg_batch_en = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_COUNTER_BDR_REG1, (uint8_t *)&cbdr_reg, 1); + } + + return ret; +} + +/** + * @brief Enable FIFO Batch for hg XL data.[get] + * + * @param ctx read / write interface definitions + * @param val 0 (disable) / 1 (enabled) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_hg_xl_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_counter_bdr_reg1_t cbdr_reg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_COUNTER_BDR_REG1, (uint8_t *)&cbdr_reg, 1); + if (ret != 0) + { + return ret; + } + + *val = cbdr_reg.xl_hg_batch_en; + + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_fifo_mode_t val) +{ + ism6hg256x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_fifo_mode_t *val) +{ + ism6hg256x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + + switch (fifo_ctrl4.fifo_mode) + { + case ISM6HG256X_BYPASS_MODE: + *val = ISM6HG256X_BYPASS_MODE; + break; + + case ISM6HG256X_FIFO_MODE: + *val = ISM6HG256X_FIFO_MODE; + break; + + case ISM6HG256X_STREAM_WTM_TO_FULL_MODE: + *val = ISM6HG256X_STREAM_WTM_TO_FULL_MODE; + break; + + case ISM6HG256X_STREAM_TO_FIFO_MODE: + *val = ISM6HG256X_STREAM_TO_FIFO_MODE; + break; + + case ISM6HG256X_BYPASS_TO_STREAM_MODE: + *val = ISM6HG256X_BYPASS_TO_STREAM_MODE; + break; + + case ISM6HG256X_STREAM_MODE: + *val = ISM6HG256X_STREAM_MODE; + break; + + case ISM6HG256X_BYPASS_TO_FIFO_MODE: + *val = ISM6HG256X_BYPASS_TO_FIFO_MODE; + break; + + default: + *val = ISM6HG256X_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief Enables FIFO batching of EIS gyroscope output values.[set] + * + * @param ctx read / write interface definitions + * @param val Enables FIFO batching of EIS gyroscope output values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_gy_eis_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.g_eis_fifo_en = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Enables FIFO batching of EIS gyroscope output values.[get] + * + * @param ctx read / write interface definitions + * @param val Enables FIFO batching of EIS gyroscope output values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + + *val = fifo_ctrl4.g_eis_fifo_en; + + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_temp_batch_t val) +{ + ism6hg256x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_temp_batch_t *val) +{ + ism6hg256x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + + switch (fifo_ctrl4.odr_t_batch) + { + case ISM6HG256X_TEMP_NOT_BATCHED: + *val = ISM6HG256X_TEMP_NOT_BATCHED; + break; + + case ISM6HG256X_TEMP_BATCHED_AT_1Hz875: + *val = ISM6HG256X_TEMP_BATCHED_AT_1Hz875; + break; + + case ISM6HG256X_TEMP_BATCHED_AT_15Hz: + *val = ISM6HG256X_TEMP_BATCHED_AT_15Hz; + break; + + case ISM6HG256X_TEMP_BATCHED_AT_60Hz: + *val = ISM6HG256X_TEMP_BATCHED_AT_60Hz; + break; + + default: + *val = ISM6HG256X_TEMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_timestamp_batch_t val) +{ + ism6hg256x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x03U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_timestamp_batch_t *val) +{ + ism6hg256x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + + switch (fifo_ctrl4.dec_ts_batch) + { + case ISM6HG256X_TMSTMP_NOT_BATCHED: + *val = ISM6HG256X_TMSTMP_NOT_BATCHED; + break; + + case ISM6HG256X_TMSTMP_DEC_1: + *val = ISM6HG256X_TMSTMP_DEC_1; + break; + + case ISM6HG256X_TMSTMP_DEC_8: + *val = ISM6HG256X_TMSTMP_DEC_8; + break; + + case ISM6HG256X_TMSTMP_DEC_32: + *val = ISM6HG256X_TMSTMP_DEC_32; + break; + + default: + *val = ISM6HG256X_TMSTMP_NOT_BATCHED; + break; + } + + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val) +{ + ism6hg256x_counter_bdr_reg1_t counter_bdr_reg1; + ism6hg256x_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU; + counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); + } + + + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_COUNTER_BDR_REG1, &buff[0], 2); + if (ret != 0) + { + return ret; + } + + *val = (uint16_t)buff[0] & 0x3U; + *val = (*val * 256U) + (uint16_t)buff[1]; + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events.[set] + * + * @param ctx read / write interface definitions + * @param val ism6hg256x_fifo_batch_cnt_event_t struct + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_batch_cnt_event_t val) +{ + ism6hg256x_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + } + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events.[get] + * + * @param ctx read / write interface definitions + * @param val ism6hg256x_fifo_batch_cnt_event_t struct + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_batch_cnt_event_t *val) +{ + ism6hg256x_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + + switch (counter_bdr_reg1.trig_counter_bdr) + { + case 0: + *val = ISM6HG256X_XL_LG_BATCH_EVENT; + break; + + case 1: + *val = ISM6HG256X_GY_BATCH_EVENT; + break; + + case 2: + *val = ISM6HG256X_GY_EIS_BATCH_EVENT; + break; + + case 3: + *val = ISM6HG256X_XL_HG_BATCH_EVENT; + break; + + default: + *val = ISM6HG256X_XL_LG_BATCH_EVENT; + break; + } + + return ret; +} + +int32_t ism6hg256x_fifo_status_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_status_t *val) +{ + uint8_t buff[2]; + ism6hg256x_fifo_status2_t status; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + if (ret != 0) + { + return ret; + } + + bytecpy((uint8_t *)&status, &buff[1]); + + val->fifo_bdr = status.counter_bdr_ia; + val->fifo_ovr = status.fifo_ovr_ia; + val->fifo_full = status.fifo_full_ia; + val->fifo_th = status.fifo_wtm_ia; + + val->fifo_level = (uint16_t)buff[1] & 0x01U; + val->fifo_level = (val->fifo_level * 256U) + buff[0]; + + return ret; +} + + +/** + * @brief FIFO data output[get] + * + * @param ctx read / write interface definitions + * @param val FIFO tag + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_out_raw_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_out_raw_t *val) +{ + ism6hg256x_fifo_data_out_tag_t fifo_data_out_tag; + uint8_t buff[7]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FIFO_DATA_OUT_TAG, buff, 7); + if (ret != 0) + { + return ret; + } + + bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); + + switch (fifo_data_out_tag.tag_sensor) + { + case 0: + val->tag = ISM6HG256X_FIFO_EMPTY; + break; + + case 1: + val->tag = ISM6HG256X_GY_NC_TAG; + break; + + case 2: + val->tag = ISM6HG256X_XL_NC_TAG; + break; + + case 3: + val->tag = ISM6HG256X_TEMPERATURE_TAG; + break; + + case 4: + val->tag = ISM6HG256X_TIMESTAMP_TAG; + break; + + case 5: + val->tag = ISM6HG256X_CFG_CHANGE_TAG; + break; + + case 6: + val->tag = ISM6HG256X_XL_NC_T_2_TAG; + break; + + case 7: + val->tag = ISM6HG256X_XL_NC_T_1_TAG; + break; + + case 8: + val->tag = ISM6HG256X_XL_2XC_TAG; + break; + + case 9: + val->tag = ISM6HG256X_XL_3XC_TAG; + break; + + case 0xA: + val->tag = ISM6HG256X_GY_NC_T_2_TAG; + break; + + case 0xB: + val->tag = ISM6HG256X_GY_NC_T_1_TAG; + break; + + case 0xC: + val->tag = ISM6HG256X_GY_2XC_TAG; + break; + + case 0xD: + val->tag = ISM6HG256X_GY_3XC_TAG; + break; + + case 0xE: + val->tag = ISM6HG256X_SENSORHUB_TARGET0_TAG; + break; + + case 0xF: + val->tag = ISM6HG256X_SENSORHUB_TARGET1_TAG; + break; + + case 0x10: + val->tag = ISM6HG256X_SENSORHUB_TARGET2_TAG; + break; + + case 0x11: + val->tag = ISM6HG256X_SENSORHUB_TARGET3_TAG; + break; + + case 0x12: + val->tag = ISM6HG256X_STEP_COUNTER_TAG; + break; + + case 0x13: + val->tag = ISM6HG256X_SFLP_GAME_ROTATION_VECTOR_TAG; + break; + + case 0x16: + val->tag = ISM6HG256X_SFLP_GYROSCOPE_BIAS_TAG; + break; + + case 0x17: + val->tag = ISM6HG256X_SFLP_GRAVITY_VECTOR_TAG; + break; + + case 0x18: + val->tag = ISM6HG256X_HG_XL_PEAK_TAG; + break; + + case 0x19: + val->tag = ISM6HG256X_SENSORHUB_NACK_TAG; + break; + + case 0x1A: + val->tag = ISM6HG256X_MLC_RESULT_TAG; + break; + + case 0x1B: + val->tag = ISM6HG256X_MLC_FILTER; + break; + + case 0x1C: + val->tag = ISM6HG256X_MLC_FEATURE; + break; + + case 0x1D: + val->tag = ISM6HG256X_XL_HG_TAG; + break; + + case 0x1E: + val->tag = ISM6HG256X_GY_ENHANCED_EIS; + break; + + case 0x1F: + val->tag = ISM6HG256X_FSM_RESULT_TAG; + break; + + default: + val->tag = ISM6HG256X_FIFO_EMPTY; + break; + } + + val->cnt = fifo_data_out_tag.tag_cnt; + + val->data[0] = buff[1]; + val->data[1] = buff[2]; + val->data[2] = buff[3]; + val->data[3] = buff[4]; + val->data[4] = buff[5]; + val->data[5] = buff[6]; + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } + emb_func_fifo_en_a.step_counter_fifo_en = val; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } + *val = emb_func_fifo_en_a.step_counter_fifo_en; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of finite state machine results.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of finite state machine results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret != 0) + { + goto exit; + } + emb_func_fifo_en_b.fsm_fifo_en = val; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of finite state machine results.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of finite state machine results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret != 0) + { + goto exit; + } + *val = emb_func_fifo_en_b.fsm_fifo_en; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of machine learning core results.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of machine learning core results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } + emb_func_fifo_en_a.mlc_fifo_en = val; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of machine learning core results.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of machine learning core results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } + *val = emb_func_fifo_en_a.mlc_fifo_en; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables batching in FIFO buffer of machine learning core filters and features.[set] + * + * @param ctx read / write interface definitions + * @param val Enables batching in FIFO buffer of machine learning core filters and features. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret != 0) + { + goto exit; + } + emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables batching in FIFO buffer of machine learning core filters and features.[get] + * + * @param ctx read / write interface definitions + * @param val Enables batching in FIFO buffer of machine learning core filters and features. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret != 0) + { + goto exit; + } + *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of target idx.[set] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of target idx. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_sh_batch_target_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val) +{ + ism6hg256x_tgt0_config_t tgt_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TGT0_CONFIG + idx * 3U, (uint8_t *)&tgt_config, 1); + if (ret != 0) + { + goto exit; + } + tgt_config.batch_ext_sens_0_en = val; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_TGT0_CONFIG + idx * 3U, (uint8_t *)&tgt_config, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of target idx.[get] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of target idx. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_sh_batch_target_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val) +{ + ism6hg256x_tgt0_config_t tgt_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TGT0_CONFIG + idx * 3U, (uint8_t *)&tgt_config, 1); + if (ret != 0) + { + goto exit; + } + *val = tgt_config.batch_ext_sens_0_en; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_sflp_raw_t val) +{ + ism6hg256x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } + emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; + emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; + emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_A, + (uint8_t *)&emb_func_fifo_en_a, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_sflp_raw_t *val) +{ + ism6hg256x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } + val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; + val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; + val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Protocol anti-spike filters.[set] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_anti_spike_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_anti_spike_t val) +{ + ism6hg256x_if_cfg_t if_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + + if (ret == 0) + { + if_cfg.asf_ctrl = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Protocol anti-spike filters.[get] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_anti_spike_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_anti_spike_t *val) +{ + ism6hg256x_if_cfg_t if_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + + switch (if_cfg.asf_ctrl) + { + case ISM6HG256X_AUTO: + *val = ISM6HG256X_AUTO; + break; + + case ISM6HG256X_ALWAYS_ACTIVE: + *val = ISM6HG256X_ALWAYS_ACTIVE; + break; + + default: + *val = ISM6HG256X_AUTO; + break; + } + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_settling_mask_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_settling_mask_t val) +{ + ism6hg256x_emb_func_cfg_t emb_func_cfg; + ism6hg256x_ui_int_ois_t ui_int_ois; + ism6hg256x_ctrl4_t ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + ctrl4.drdy_mask = val.drdy; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } + emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; + emb_func_cfg.emb_func_irq_mask_xl_hg_settl = val.irq_xl_hg; + emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + if (ret != 0) + { + return ret; + } + ui_int_ois.drdy_mask_ois = val.ois_drdy; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_settling_mask_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_settling_mask_t *val) +{ + ism6hg256x_emb_func_cfg_t emb_func_cfg; + ism6hg256x_ui_int_ois_t ui_int_ois; + ism6hg256x_ctrl4_t ctrl4; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL4, (uint8_t *)&ctrl4, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + if (ret != 0) + { + return ret; + } + val->ois_drdy = ui_int_ois.drdy_mask_ois; + + val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl; + val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl; + val->drdy = ctrl4.drdy_mask; + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends from OIS interface. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_ois_settling_mask_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_ois_settling_mask_t val) +{ + ism6hg256x_if2_int_ois_t if2_int_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF2_INT_OIS, (uint8_t *)&if2_int_ois, 1); + + if (ret == 0) + { + if2_int_ois.drdy_mask_ois = val.ois_drdy; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_IF2_INT_OIS, (uint8_t *)&if2_int_ois, 1); + } + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_ois_settling_mask_t *val) +{ + + ism6hg256x_if2_int_ois_t if2_int_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF2_INT_OIS, (uint8_t *)&if2_int_ois, 1); + if (ret != 0) + { + return ret; + } + + val->ois_drdy = if2_int_ois.drdy_mask_ois; + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_gy_lp1_bandwidth_t val) +{ + ism6hg256x_ctrl6_t ctrl6; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret == 0) + { + ctrl6.lpf1_g_bw = (uint8_t)val & 0x0Fu; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_gy_lp1_bandwidth_t *val) +{ + ism6hg256x_ctrl6_t ctrl6; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl6.lpf1_g_bw) + { + case ISM6HG256X_GY_ULTRA_LIGHT: + *val = ISM6HG256X_GY_ULTRA_LIGHT; + break; + + case ISM6HG256X_GY_VERY_LIGHT: + *val = ISM6HG256X_GY_VERY_LIGHT; + break; + + case ISM6HG256X_GY_LIGHT: + *val = ISM6HG256X_GY_LIGHT; + break; + + case ISM6HG256X_GY_MEDIUM: + *val = ISM6HG256X_GY_MEDIUM; + break; + + case ISM6HG256X_GY_STRONG: + *val = ISM6HG256X_GY_STRONG; + break; + + case ISM6HG256X_GY_VERY_STRONG: + *val = ISM6HG256X_GY_VERY_STRONG; + break; + + case ISM6HG256X_GY_AGGRESSIVE: + *val = ISM6HG256X_GY_AGGRESSIVE; + break; + + case ISM6HG256X_GY_XTREME: + *val = ISM6HG256X_GY_XTREME; + break; + + default: + *val = ISM6HG256X_GY_ULTRA_LIGHT; + break; + } + + return ret; +} + +/** + * @brief It enables gyroscope digital LPF1 filter.[set] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_ctrl7_t ctrl7; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ctrl7.lpf1_g_en = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + + +/** + * @brief It enables gyroscope digital LPF1 filter.[get] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_ctrl7_t ctrl7; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + + *val = ctrl7.lpf1_g_en; + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_xl_lp2_bandwidth_t val) +{ + ism6hg256x_ctrl8_t ctrl8; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x07U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_xl_lp2_bandwidth_t *val) +{ + ism6hg256x_ctrl8_t ctrl8; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl8.hp_lpf2_xl_bw) + { + case ISM6HG256X_XL_ULTRA_LIGHT: + *val = ISM6HG256X_XL_ULTRA_LIGHT; + break; + + case ISM6HG256X_XL_VERY_LIGHT: + *val = ISM6HG256X_XL_VERY_LIGHT; + break; + + case ISM6HG256X_XL_LIGHT: + *val = ISM6HG256X_XL_LIGHT; + break; + + case ISM6HG256X_XL_MEDIUM: + *val = ISM6HG256X_XL_MEDIUM; + break; + + case ISM6HG256X_XL_STRONG: + *val = ISM6HG256X_XL_STRONG; + break; + + case ISM6HG256X_XL_VERY_STRONG: + *val = ISM6HG256X_XL_VERY_STRONG; + break; + + case ISM6HG256X_XL_AGGRESSIVE: + *val = ISM6HG256X_XL_AGGRESSIVE; + break; + + case ISM6HG256X_XL_XTREME: + *val = ISM6HG256X_XL_XTREME; + break; + + default: + *val = ISM6HG256X_XL_ULTRA_LIGHT; + break; + } + + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_ctrl9_t ctrl9; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.lpf2_xl_en = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_ctrl9_t ctrl9; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + + *val = ctrl9.lpf2_xl_en; + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_ctrl9_t ctrl9; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_slope_xl_en = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_ctrl9_t ctrl9; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + + *val = ctrl9.hp_slope_xl_en; + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_ctrl9_t ctrl9; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.xl_fastsettl_mode = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_ctrl9_t ctrl9; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + + *val = ctrl9.xl_fastsettl_mode; + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[set] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_xl_hp_mode_t val) +{ + ism6hg256x_ctrl9_t ctrl9; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[get] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_xl_hp_mode_t *val) +{ + ism6hg256x_ctrl9_t ctrl9; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl9.hp_ref_mode_xl) + { + case ISM6HG256X_HP_MD_NORMAL: + *val = ISM6HG256X_HP_MD_NORMAL; + break; + + case ISM6HG256X_HP_MD_REFERENCE: + *val = ISM6HG256X_HP_MD_REFERENCE; + break; + + default: + *val = ISM6HG256X_HP_MD_NORMAL; + break; + } + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_wkup_act_feed_t val) +{ + ism6hg256x_wake_up_ths_t wake_up_ths; + ism6hg256x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + + tap_cfg0.slope_fds = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + + wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_wkup_act_feed_t *val) +{ + ism6hg256x_wake_up_ths_t wake_up_ths; + ism6hg256x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + + switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) + { + case ISM6HG256X_WK_FEED_SLOPE: + *val = ISM6HG256X_WK_FEED_SLOPE; + break; + + case ISM6HG256X_WK_FEED_HIGH_PASS: + *val = ISM6HG256X_WK_FEED_HIGH_PASS; + break; + + case ISM6HG256X_WK_FEED_LP_WITH_OFFSET: + *val = ISM6HG256X_WK_FEED_LP_WITH_OFFSET; + break; + + default: + *val = ISM6HG256X_WK_FEED_SLOPE; + break; + } + + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[set] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret == 0) + { + tap_cfg0.hw_func_mask_xl_settl = val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[get] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + + *val = tap_cfg0.hw_func_mask_xl_settl; + + return ret; +} + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[set] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_sixd_feed_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_sixd_feed_t val) +{ + ism6hg256x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret == 0) + { + tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[get] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_sixd_feed_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_sixd_feed_t *val) +{ + ism6hg256x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + + switch (tap_cfg0.low_pass_on_6d) + { + case ISM6HG256X_SIXD_FEED_ODR_DIV_2: + *val = ISM6HG256X_SIXD_FEED_ODR_DIV_2; + break; + + case ISM6HG256X_SIXD_FEED_LOW_PASS: + *val = ISM6HG256X_SIXD_FEED_LOW_PASS; + break; + + default: + *val = ISM6HG256X_SIXD_FEED_ODR_DIV_2; + break; + } + + return ret; +} + +/** + * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[set] + * + * @param ctx read / write interface definitions + * @param val EIS_LP_NORMAL, EIS_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_gy_eis_lp_bandwidth_t val) +{ + ism6hg256x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.lpf_g_eis_bw = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[get] + * + * @param ctx read / write interface definitions + * @param val EIS_LP_NORMAL, EIS_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_gy_eis_lp_bandwidth_t *val) +{ + ism6hg256x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl_eis.lpf_g_eis_bw) + { + case ISM6HG256X_EIS_LP_NORMAL: + *val = ISM6HG256X_EIS_LP_NORMAL; + break; + + case ISM6HG256X_EIS_LP_LIGHT: + *val = ISM6HG256X_EIS_LP_LIGHT; + break; + + default: + *val = ISM6HG256X_EIS_LP_NORMAL; + break; + } + + return ret; +} + +/** + * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (IF2_CTRL2_OIS = UI_CTRL2_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_gy_ois_lp_bandwidth_t val) +{ + ism6hg256x_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + + if (ret == 0) + { + ui_ctrl2_ois.lpf1_g_ois_bw = (uint8_t)val & 0x03U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + } + + return ret; +} + +/** + * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (IF2_CTRL2_OIS = UI_CTRL2_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_gy_ois_lp_bandwidth_t *val) +{ + + ism6hg256x_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (ui_ctrl2_ois.lpf1_g_ois_bw) + { + case ISM6HG256X_OIS_GY_LP_NORMAL: + *val = ISM6HG256X_OIS_GY_LP_NORMAL; + break; + + case ISM6HG256X_OIS_GY_LP_STRONG: + *val = ISM6HG256X_OIS_GY_LP_STRONG; + break; + + case ISM6HG256X_OIS_GY_LP_AGGRESSIVE: + *val = ISM6HG256X_OIS_GY_LP_AGGRESSIVE; + break; + + case ISM6HG256X_OIS_GY_LP_LIGHT: + *val = ISM6HG256X_OIS_GY_LP_LIGHT; + break; + + default: + *val = ISM6HG256X_OIS_GY_LP_NORMAL; + break; + } + + return ret; +} + +/** + * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (IF2_CTRL3_OIS = UI_CTRL3_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_xl_ois_lp_bandwidth_t val) +{ + ism6hg256x_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + + if (ret == 0) + { + ui_ctrl3_ois.lpf_xl_ois_bw = (uint8_t)val & 0x07U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + } + + return ret; +} + +/** + * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (IF2_CTRL3_OIS = UI_CTRL3_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_xl_ois_lp_bandwidth_t *val) +{ + ism6hg256x_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (ui_ctrl3_ois.lpf_xl_ois_bw) + { + case ISM6HG256X_OIS_XL_LP_ULTRA_LIGHT: + *val = ISM6HG256X_OIS_XL_LP_ULTRA_LIGHT; + break; + + case ISM6HG256X_OIS_XL_LP_VERY_LIGHT: + *val = ISM6HG256X_OIS_XL_LP_VERY_LIGHT; + break; + + case ISM6HG256X_OIS_XL_LP_LIGHT: + *val = ISM6HG256X_OIS_XL_LP_LIGHT; + break; + + case ISM6HG256X_OIS_XL_LP_NORMAL: + *val = ISM6HG256X_OIS_XL_LP_NORMAL; + break; + + case ISM6HG256X_OIS_XL_LP_STRONG: + *val = ISM6HG256X_OIS_XL_LP_STRONG; + break; + + case ISM6HG256X_OIS_XL_LP_VERY_STRONG: + *val = ISM6HG256X_OIS_XL_LP_VERY_STRONG; + break; + + case ISM6HG256X_OIS_XL_LP_AGGRESSIVE: + *val = ISM6HG256X_OIS_XL_LP_AGGRESSIVE; + break; + + case ISM6HG256X_OIS_XL_LP_XTREME: + *val = ISM6HG256X_OIS_XL_LP_XTREME; + break; + + default: + *val = ISM6HG256X_OIS_XL_LP_ULTRA_LIGHT; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Finite State Machine (FSM) + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_permission_set(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_permission_t val) +{ + ism6hg256x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_permission_get(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_permission_t *val) +{ + ism6hg256x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + + switch (func_cfg_access.fsm_wr_ctrl_en) + { + case ISM6HG256X_PROTECT_CTRL_REGS: + *val = ISM6HG256X_PROTECT_CTRL_REGS; + break; + + case ISM6HG256X_WRITE_CTRL_REG: + *val = ISM6HG256X_WRITE_CTRL_REG; + break; + + default: + *val = ISM6HG256X_PROTECT_CTRL_REGS; + break; + } + + return ret; +} + +/** + * @brief Get the FSM permission status + * + * @param ctx read / write interface definitions + * @param val 0: All reg writable from std if - 1: some regs are under FSM control. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_ctrl_status_t ctrl_status; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL_STATUS, (uint8_t *)&ctrl_status, 1); + if (ret != 0) + { + return ret; + } + + *val = ctrl_status.fsm_wr_ctrl_status; + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[set] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_fsm_mode_t val) +{ + ism6hg256x_emb_func_en_b_t emb_func_en_b; + ism6hg256x_fsm_enable_t fsm_enable; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + if (ret != 0) + { + goto exit; + } + + if ((val.fsm1_en | val.fsm2_en | val.fsm3_en | val.fsm4_en + | val.fsm5_en | val.fsm6_en | val.fsm7_en | val.fsm8_en) == PROPERTY_ENABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + + fsm_enable.fsm1_en = val.fsm1_en; + fsm_enable.fsm2_en = val.fsm2_en; + fsm_enable.fsm3_en = val.fsm3_en; + fsm_enable.fsm4_en = val.fsm4_en; + fsm_enable.fsm5_en = val.fsm5_en; + fsm_enable.fsm6_en = val.fsm6_en; + fsm_enable.fsm7_en = val.fsm7_en; + fsm_enable.fsm8_en = val.fsm8_en; + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[get] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_fsm_mode_t *val) +{ + ism6hg256x_fsm_enable_t fsm_enable; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + val->fsm1_en = fsm_enable.fsm1_en; + val->fsm2_en = fsm_enable.fsm2_en; + val->fsm3_en = fsm_enable.fsm3_en; + val->fsm4_en = fsm_enable.fsm4_en; + val->fsm5_en = fsm_enable.fsm5_en; + val->fsm6_en = fsm_enable.fsm6_en; + val->fsm7_en = fsm_enable.fsm7_en; + val->fsm8_en = fsm_enable.fsm8_en; + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_FSM_LONG_COUNTER_L, &buff[0], 2); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM output registers[get] + * + * @param ctx read / write interface definitions + * @param val FSM output registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_out_get(const stmdev_ctx_t *ctx, ism6hg256x_fsm_out_t *val) +{ + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_FSM_OUTS1, (uint8_t *)val, 8); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_data_rate_t val) +{ + ism6hg256x_fsm_odr_t fsm_odr; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + if (ret != 0) + { + goto exit; + } + fsm_odr.fsm_odr = (uint8_t)val & 0x07U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_data_rate_t *val) +{ + ism6hg256x_fsm_odr_t fsm_odr; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (fsm_odr.fsm_odr) + { + case ISM6HG256X_FSM_15Hz: + *val = ISM6HG256X_FSM_15Hz; + break; + + case ISM6HG256X_FSM_30Hz: + *val = ISM6HG256X_FSM_30Hz; + break; + + case ISM6HG256X_FSM_60Hz: + *val = ISM6HG256X_FSM_60Hz; + break; + + case ISM6HG256X_FSM_120Hz: + *val = ISM6HG256X_FSM_120Hz; + break; + + case ISM6HG256X_FSM_240Hz: + *val = ISM6HG256X_FSM_240Hz; + break; + + case ISM6HG256X_FSM_480Hz: + *val = ISM6HG256X_FSM_480Hz; + break; + + case ISM6HG256X_FSM_960Hz: + *val = ISM6HG256X_FSM_960Hz; + break; + + default: + *val = ISM6HG256X_FSM_15Hz; + break; + } + + return ret; +} + +/* + * Original conversion routines taken from: https://github.com/numpy/numpy + * + * uint16_t npy_floatbits_to_halfbits(uint32_t f); + * uint16_t npy_float_to_half(float_t f); + * uint32_t npy_halfbits_to_floatbits(uint16_t h) + * float_t npy_half_to_float(uint16_t h) + * + * Released under BSD-3-Clause License + */ +typedef union +{ + float_t f; + uint32_t fbits; +} hf_conv_t; + +static uint16_t npy_floatbits_to_halfbits(uint32_t f) +{ + uint32_t f_exp, f_sig; + uint16_t h_sgn, h_exp, h_sig; + + h_sgn = (uint16_t)((f & 0x80000000u) >> 16); + f_exp = (f & 0x7f800000u); + + /* Exponent overflow/NaN converts to signed inf/NaN */ + if (f_exp >= 0x47800000u) + { + if (f_exp == 0x7f800000u) + { + /* Inf or NaN */ + f_sig = (f & 0x007fffffu); + if (f_sig != 0U) + { + /* NaN - propagate the flag in the significand... */ + uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13)); + /* ...but make sure it stays a NaN */ + if (ret == 0x7c00u) + { + ret++; + } + return h_sgn + ret; + } + else + { + /* signed inf */ + return (uint16_t)(h_sgn + 0x7c00u); + } + } + else + { + /* overflow to signed inf */ +#if NPY_HALF_GENERATE_OVERFLOW + npy_set_floatstatus_overflow(); +#endif + return (uint16_t)(h_sgn + 0x7c00u); + } + } + + /* Exponent underflow converts to a subnormal half or signed zero */ + if (f_exp <= 0x38000000u) + { + /* + * Signed zeros, subnormal floats, and floats with small + * exponents all convert to signed zero half-floats. + */ + if (f_exp < 0x33000000u) + { +#if NPY_HALF_GENERATE_UNDERFLOW + /* If f != 0, it underflowed to 0 */ + if ((f & 0x7fffffff) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + return h_sgn; + } + /* Make the subnormal significand */ + f_exp >>= 23; + f_sig = (0x00800000u + (f & 0x007fffffu)); +#if NPY_HALF_GENERATE_UNDERFLOW + /* If it's not exactly represented, it underflowed */ + if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + /* + * Usually the significand is shifted by 13. For subnormals an + * additional shift needs to occur. This shift is one for the largest + * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which + * offsets the new first bit. At most the shift can be 1+10 bits. + */ + f_sig >>= (113U - f_exp); + /* Handle rounding by adding 1 to the bit beyond half precision */ +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. However, the (113 - f_exp) + * shift can lose up to 11 bits, so the || checks them in the original. + * In all other cases, we can just add one. + */ + if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu)) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp from zero to one and h_sig will be zero. + * This is the correct result. + */ + return (uint16_t)(h_sgn + h_sig); + } + + /* Regular case with no overflow or underflow */ + h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13); + /* Handle rounding by adding 1 to the bit beyond half precision */ + f_sig = (f & 0x007fffffu); +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. In all other cases, we do. + */ + if ((f_sig & 0x00003fffu) != 0x00001000u) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp by one and h_sig will be zero. This is the + * correct result. h_exp may increment to 15, at greatest, in + * which case the result overflows to a signed inf. + */ +#if NPY_HALF_GENERATE_OVERFLOW + h_sig += h_exp; + if (h_sig == 0x7c00u) + { + npy_set_floatstatus_overflow(); + } + return h_sgn + h_sig; +#else + return h_sgn + h_exp + h_sig; +#endif +} + +static uint16_t npy_float_to_half(float_t f) +{ + hf_conv_t conv; + + conv.f = f; + return npy_floatbits_to_halfbits(conv.fbits); +} + +static uint32_t npy_halfbits_to_floatbits(uint16_t h) +{ + uint16_t h_exp = (h & 0x7c00u); + uint32_t f_sgn = ((uint32_t)h & 0x8000u) << 16; + switch (h_exp) + { + case 0x0000u: // 0 or subnormal + { + uint16_t h_sig = (h & 0x03ffu); + // Signed zero + if (h_sig == 0) + { + return f_sgn; + } + // Subnormal + h_sig <<= 1; + while ((h_sig & 0x0400u) == 0) + { + h_sig <<= 1; + h_exp++; + } + uint32_t f_exp = ((uint32_t)(127 - 15 - h_exp)) << 23; + uint32_t f_sig = ((uint32_t)(h_sig & 0x03ffu)) << 13; + return f_sgn + f_exp + f_sig; + } + case 0x7c00u: // inf or NaN + // All-ones exponent and a copy of the significand + return f_sgn + 0x7f800000u + (((uint32_t)(h & 0x03ffu)) << 13); + default: // normalized + // Just need to adjust the exponent and shift + return f_sgn + (((uint32_t)(h & 0x7fffu) + 0x1c000u) << 13); + } +} + +static float_t npy_half_to_float(uint16_t h) +{ + hf_conv_t conv; + + conv.fbits = npy_halfbits_to_floatbits(h); + + return conv.f; +} + +/** + * @brief SFLP GBIAS value. The register value is expressed as half-precision + * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent + * bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val GBIAS x/y/z val. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sflp_game_gbias_set(const stmdev_ctx_t *ctx, + ism6hg256x_sflp_gbias_t *val) +{ + ism6hg256x_sflp_data_rate_t sflp_odr; + uint16_t gbias_hf[3]; + float_t k = 0.005f; + int32_t ret; + + ret = ism6hg256x_sflp_data_rate_get(ctx, &sflp_odr); + if (ret != 0) + { + return ret; + } + + /* Calculate k factor */ + switch (sflp_odr) + { + default: + case ISM6HG256X_SFLP_15Hz: + k = 0.04f; + break; + case ISM6HG256X_SFLP_30Hz: + k = 0.02f; + break; + case ISM6HG256X_SFLP_60Hz: + k = 0.01f; + break; + case ISM6HG256X_SFLP_120Hz: + k = 0.005f; + break; + case ISM6HG256X_SFLP_240Hz: + k = 0.0025f; + break; + case ISM6HG256X_SFLP_480Hz: + k = 0.00125f; + break; + } + + /* compute gbias as half precision float in order to be put in embedded advanced feature register */ + gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k); + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_SFLP_GBIASX_INIT_L, (uint8_t *)&gbias_hf[0], 6); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_FSM_EXT_SENSITIVITY_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_FSM_EXT_SENSITIVITY_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_ext_sens_offset_set(const stmdev_ctx_t *ctx, + ism6hg256x_xl_fsm_ext_sens_offset_t val) +{ + uint8_t buff[6]; + int32_t ret; + + buff[1] = (uint8_t)(val.x / 256U); + buff[0] = (uint8_t)(val.x - (buff[1] * 256U)); + buff[3] = (uint8_t)(val.y / 256U); + buff[2] = (uint8_t)(val.y - (buff[3] * 256U)); + buff[5] = (uint8_t)(val.z / 256U); + buff[4] = (uint8_t)(val.z - (buff[5] * 256U)); + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_FSM_EXT_OFFX_L, (uint8_t *)&buff[0], 6); + + return ret; +} + +/** + * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_ext_sens_offset_get(const stmdev_ctx_t *ctx, + ism6hg256x_xl_fsm_ext_sens_offset_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_FSM_EXT_OFFX_L, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val->x = buff[1]; + val->x = (val->x * 256U) + buff[0]; + val->y = buff[3]; + val->y = (val->y * 256U) + buff[2]; + val->z = buff[5]; + val->z = (val->z * 256U) + buff[4]; + + return ret; +} + +/** + * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_ext_sens_matrix_set(const stmdev_ctx_t *ctx, + ism6hg256x_xl_fsm_ext_sens_matrix_t val) +{ + uint8_t buff[12]; + int32_t ret; + + buff[1] = (uint8_t)(val.xx / 256U); + buff[0] = (uint8_t)(val.xx - (buff[1] * 256U)); + buff[3] = (uint8_t)(val.xy / 256U); + buff[2] = (uint8_t)(val.xy - (buff[3] * 256U)); + buff[5] = (uint8_t)(val.xz / 256U); + buff[4] = (uint8_t)(val.xz - (buff[5] * 256U)); + buff[7] = (uint8_t)(val.yy / 256U); + buff[6] = (uint8_t)(val.yy - (buff[7] * 256U)); + buff[9] = (uint8_t)(val.yz / 256U); + buff[8] = (uint8_t)(val.yz - (buff[9] * 256U)); + buff[11] = (uint8_t)(val.zz / 256U); + buff[10] = (uint8_t)(val.zz - (buff[11] * 256U)); + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_FSM_EXT_MATRIX_XX_L, (uint8_t *)&buff[0], 12); + + return ret; +} + +/** + * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_ext_sens_matrix_get(const stmdev_ctx_t *ctx, + ism6hg256x_xl_fsm_ext_sens_matrix_t *val) +{ + uint8_t buff[12]; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_FSM_EXT_MATRIX_XX_L, &buff[0], 12); + if (ret != 0) + { + return ret; + } + + val->xx = buff[1]; + val->xx = (val->xx * 256U) + buff[0]; + val->xy = buff[3]; + val->xy = (val->xy * 256U) + buff[2]; + val->xz = buff[5]; + val->xz = (val->xz * 256U) + buff[4]; + val->yy = buff[7]; + val->yy = (val->yy * 256U) + buff[6]; + val->yz = buff[9]; + val->yz = (val->yz * 256U) + buff[8]; + val->zz = buff[11]; + val->zz = (val->zz * 256U) + buff[10]; + + return ret; +} + +/** + * @brief External sensor z-axis coordinates rotation.[set] + * + * @param ctx read / write interface definitions + * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_ext_sens_z_orient_t val) +{ + ism6hg256x_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret != 0) + { + return ret; + } + ext_cfg_a.ext_z_axis = (uint8_t)val & 0x07U; + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + + return ret; +} + +/** + * @brief External sensor z-axis coordinates rotation.[get] + * + * @param ctx read / write interface definitions + * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_ext_sens_z_orient_get(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_ext_sens_z_orient_t *val) +{ + ism6hg256x_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret != 0) + { + return ret; + } + + switch (ext_cfg_a.ext_z_axis) + { + case ISM6HG256X_Z_EQ_Y: + *val = ISM6HG256X_Z_EQ_Y; + break; + + case ISM6HG256X_Z_EQ_MIN_Y: + *val = ISM6HG256X_Z_EQ_MIN_Y; + break; + + case ISM6HG256X_Z_EQ_X: + *val = ISM6HG256X_Z_EQ_X; + break; + + case ISM6HG256X_Z_EQ_MIN_X: + *val = ISM6HG256X_Z_EQ_MIN_X; + break; + + case ISM6HG256X_Z_EQ_MIN_Z: + *val = ISM6HG256X_Z_EQ_MIN_Z; + break; + + case ISM6HG256X_Z_EQ_Z: + *val = ISM6HG256X_Z_EQ_Z; + break; + + default: + *val = ISM6HG256X_Z_EQ_Y; + break; + } + + return ret; +} + +/** + * @brief External sensor Y-axis coordinates rotation.[set] + * + * @param ctx read / write interface definitions + * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_ext_sens_y_orient_set(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_ext_sens_y_orient_t val) +{ + ism6hg256x_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret == 0) + { + ext_cfg_a.ext_y_axis = (uint8_t)val & 0x7U; + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + } + + return ret; +} + +/** + * @brief External sensor Y-axis coordinates rotation.[get] + * + * @param ctx read / write interface definitions + * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_ext_sens_y_orient_get(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_ext_sens_y_orient_t *val) +{ + ism6hg256x_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret != 0) + { + return ret; + } + + switch (ext_cfg_a.ext_y_axis) + { + case ISM6HG256X_Y_EQ_Y: + *val = ISM6HG256X_Y_EQ_Y; + break; + + case ISM6HG256X_Y_EQ_MIN_Y: + *val = ISM6HG256X_Y_EQ_MIN_Y; + break; + + case ISM6HG256X_Y_EQ_X: + *val = ISM6HG256X_Y_EQ_X; + break; + + case ISM6HG256X_Y_EQ_MIN_X: + *val = ISM6HG256X_Y_EQ_MIN_X; + break; + + case ISM6HG256X_Y_EQ_MIN_Z: + *val = ISM6HG256X_Y_EQ_MIN_Z; + break; + + case ISM6HG256X_Y_EQ_Z: + *val = ISM6HG256X_Y_EQ_Z; + break; + + default: + *val = ISM6HG256X_Y_EQ_Y; + break; + } + + return ret; +} + +/** + * @brief External sensor X-axis coordinates rotation.[set] + * + * @param ctx read / write interface definitions + * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_ext_sens_x_orient_set(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_ext_sens_x_orient_t val) +{ + ism6hg256x_ext_cfg_b_t ext_cfg_b; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); + if (ret == 0) + { + ext_cfg_b.ext_x_axis = (uint8_t)val & 0x7U; + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); + } + + return ret; +} + +/** + * @brief External sensor X-axis coordinates rotation.[get] + * + * @param ctx read / write interface definitions + * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_ext_sens_x_orient_get(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_ext_sens_x_orient_t *val) +{ + ism6hg256x_ext_cfg_b_t ext_cfg_b; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); + if (ret != 0) + { + return ret; + } + + switch (ext_cfg_b.ext_x_axis) + { + case ISM6HG256X_X_EQ_Y: + *val = ISM6HG256X_X_EQ_Y; + break; + + case ISM6HG256X_X_EQ_MIN_Y: + *val = ISM6HG256X_X_EQ_MIN_Y; + break; + + case ISM6HG256X_X_EQ_X: + *val = ISM6HG256X_X_EQ_X; + break; + + case ISM6HG256X_X_EQ_MIN_X: + *val = ISM6HG256X_X_EQ_MIN_X; + break; + + case ISM6HG256X_X_EQ_MIN_Z: + *val = ISM6HG256X_X_EQ_MIN_Z; + break; + + case ISM6HG256X_X_EQ_Z: + *val = ISM6HG256X_X_EQ_Z; + break; + + default: + *val = ISM6HG256X_X_EQ_Y; + break; + } + + return ret; +} + +/** + * @brief High-g accelerometer peak tracking enable.[set] + * + * @param ctx read / write interface definitions + * @param val 0: disable, 1: enable + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_hg_peak_tracking_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); + if (ret != 0) + { + goto exit; + } + emb_func_init_b.pt_init = val; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief High-g accelerometer peak tracking enable.[get] + * + * @param ctx read / write interface definitions + * @param val 0: disable, 1: enable + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_hg_peak_tracking_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); + if (ret != 0) + { + goto exit; + } + *val = emb_func_init_b.pt_init; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Hihg-g accelerometer sensitivity value register for FSM and MLC.[set] + * + * @param ctx read / write interface definitions + * @param val Hihg-g accelerometer sensitivity value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_hg_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_XL_HG_SENSITIVITY_L, + (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Hihg-g accelerometer sensitivity value register for FSM and MLC.[get] + * + * @param ctx read / write interface definitions + * @param val Hihg-g accelerometer sensitivity value + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_xl_hg_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_XL_HG_SENSITIVITY_L, &buff[0], + 2); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_FSM_LC_TIMEOUT_L, + (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_FSM_LC_TIMEOUT_L, &buff[0], + 2); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM number of programs.[set] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_fsm_programs_t fsm_programs; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_FSM_PROGRAMS, + (uint8_t *)&fsm_programs, 1); + if (ret == 0) + { + fsm_programs.fsm_n_prog = val; + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_FSM_PROGRAMS, + (uint8_t *)&fsm_programs, 1); + } + + return ret; +} + +/** + * @brief FSM number of programs.[get] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_fsm_programs_t fsm_programs; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_FSM_PROGRAMS, + (uint8_t *)&fsm_programs, 1); + if (ret == 0) + { + *val = fsm_programs.fsm_n_prog; + } + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[set] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_FSM_START_ADD_L, + (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[get] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_FSM_START_ADD_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Free fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_wake_up_dur_t wake_up_dur; + ism6hg256x_free_fall_t free_fall; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } + free_fall.ff_dur = (uint8_t)val & 0x1FU; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_FREE_FALL, (uint8_t *)&free_fall, 1); + + return ret; +} + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_wake_up_dur_t wake_up_dur; + ism6hg256x_free_fall_t free_fall; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } + + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ff_thresholds_set(const stmdev_ctx_t *ctx, + ism6hg256x_ff_thresholds_t val) +{ + ism6hg256x_free_fall_t free_fall; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = (uint8_t)val & 0x7U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ff_thresholds_get(const stmdev_ctx_t *ctx, + ism6hg256x_ff_thresholds_t *val) +{ + ism6hg256x_free_fall_t free_fall; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } + + switch (free_fall.ff_ths) + { + case ISM6HG256X_156_mg: + *val = ISM6HG256X_156_mg; + break; + + case ISM6HG256X_219_mg: + *val = ISM6HG256X_219_mg; + break; + + case ISM6HG256X_250_mg: + *val = ISM6HG256X_250_mg; + break; + + case ISM6HG256X_312_mg: + *val = ISM6HG256X_312_mg; + break; + + case ISM6HG256X_344_mg: + *val = ISM6HG256X_344_mg; + break; + + case ISM6HG256X_406_mg: + *val = ISM6HG256X_406_mg; + break; + + case ISM6HG256X_469_mg: + *val = ISM6HG256X_469_mg; + break; + + case ISM6HG256X_500_mg: + *val = ISM6HG256X_500_mg; + break; + + default: + *val = ISM6HG256X_156_mg; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Machine Learning Core (MLC) + * @brief This section group all the functions concerning the + * usage of Machine Learning Core + * @{ + * + */ + +/** + * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[set] + * + * @param ctx read / write interface definitions + * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_mlc_set(const stmdev_ctx_t *ctx, ism6hg256x_mlc_mode_t val) +{ + ism6hg256x_emb_func_en_b_t emb_en_b; + ism6hg256x_emb_func_en_a_t emb_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + if (ret != 0) + { + goto exit; + } + + switch (val) + { + case ISM6HG256X_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case ISM6HG256X_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case ISM6HG256X_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + break; + } + + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[get] + * + * @param ctx read / write interface definitions + * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_mlc_get(const stmdev_ctx_t *ctx, ism6hg256x_mlc_mode_t *val) +{ + ism6hg256x_emb_func_en_b_t emb_en_b; + ism6hg256x_emb_func_en_a_t emb_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + if (ret != 0) + { + goto exit; + } + + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = ISM6HG256X_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = ISM6HG256X_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = ISM6HG256X_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_mlc_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_mlc_data_rate_t val) +{ + ism6hg256x_mlc_odr_t mlc_odr; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_MLC_ODR, (uint8_t *)&mlc_odr, 1); + if (ret != 0) + { + goto exit; + } + + mlc_odr.mlc_odr = (uint8_t)val & 0x07U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_MLC_ODR, (uint8_t *)&mlc_odr, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_mlc_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_mlc_data_rate_t *val) +{ + ism6hg256x_mlc_odr_t mlc_odr; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_MLC_ODR, (uint8_t *)&mlc_odr, 1); + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (mlc_odr.mlc_odr) + { + case 0: + *val = ISM6HG256X_MLC_15Hz; + break; + + case 1: + *val = ISM6HG256X_MLC_30Hz; + break; + + case 2: + *val = ISM6HG256X_MLC_60Hz; + break; + + case 3: + *val = ISM6HG256X_MLC_120Hz; + break; + + case 4: + *val = ISM6HG256X_MLC_240Hz; + break; + + case 5: + *val = ISM6HG256X_MLC_480Hz; + break; + + case 6: + *val = ISM6HG256X_MLC_960Hz; + break; + + default: + *val = ISM6HG256X_MLC_15Hz; + break; + } + + return ret; +} + +/** + * @brief Output value of all MLC decision trees.[get] + * + * @param ctx read / write interface definitions + * @param val Output value of all MLC decision trees. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_mlc_out_get(const stmdev_ctx_t *ctx, ism6hg256x_mlc_out_t *val) +{ + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_MLC1_SRC, (uint8_t *)val, 8); + } + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_mlc_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_MLC_EXT_SENSITIVITY_L, + (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_mlc_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_MLC_EXT_SENSITIVITY_L, + &buff[0], 2); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Optical Image Stabilization (OIS) + * @brief This section groups all the functions concerning + * Optical Image Stabilization (OIS). + * @{ + * + */ + +/** + * @brief Enable the full control of OIS configurations from the UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_ctrl_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_ois_ctrl_mode_t val) +{ + ism6hg256x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.ois_ctrl_from_ui = (uint8_t)val & 0x1U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enable the full control of OIS configurations from the UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_ctrl_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_ctrl_mode_t *val) +{ + ism6hg256x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + + switch (func_cfg_access.ois_ctrl_from_ui) + { + case ISM6HG256X_OIS_CTRL_FROM_OIS: + *val = ISM6HG256X_OIS_CTRL_FROM_OIS; + break; + + case ISM6HG256X_OIS_CTRL_FROM_UI: + *val = ISM6HG256X_OIS_CTRL_FROM_UI; + break; + + default: + *val = ISM6HG256X_OIS_CTRL_FROM_OIS; + break; + } + + return ret; +} + +/** + * @brief Resets the control registers of OIS from the UI (User Interface)[set] + * + * @param ctx read / write interface definitions + * @param val Resets the control registers of OIS from the UI (User Interface) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_reset_set(const stmdev_ctx_t *ctx, int8_t val) +{ + ism6hg256x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.if2_reset = (uint8_t)val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Resets the control registers of OIS from the UI (User Interface)[get] + * + * @param ctx read / write interface definitions + * @param val Resets the control registers of OIS from the UI (User Interface) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val) +{ + ism6hg256x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + *val = (int8_t)func_cfg_access.if2_reset; + + return ret; +} + +/** + * @brief Enable/disable pull up on OIS interface.[set] + * + * @param ctx read / write interface definitions + * @param val Enable/disable pull up on OIS interface. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.ois_pu_dis = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enable/disable pull up on OIS interface.[get] + * + * @param ctx read / write interface definitions + * @param val Enable/disable pull up on OIS interface. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.ois_pu_dis; + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) IF2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_IF2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface controller to request access to the UI_IF2_SHARED registers. When the R/W operation is finished, the controller must reset this bit.[set] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) IF2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_IF2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface controller to request access to the UI_IF2_SHARED registers. When the R/W operation is finished, the controller must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_handshake_from_ui_set(const stmdev_ctx_t *ctx, + ism6hg256x_ois_handshake_t val) +{ + ism6hg256x_ui_handshake_ctrl_t ui_handshake_ctrl; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); + if (ret == 0) + { + ui_handshake_ctrl.ui_shared_ack = val.ack; + ui_handshake_ctrl.ui_shared_req = val.req; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); + } + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) IF2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_IF2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface controller to request access to the UI_IF2_SHARED registers. When the R/W operation is finished, the controller must reset this bit.[get] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) IF2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_IF2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface controller to request access to the UI_IF2_SHARED registers. When the R/W operation is finished, the controller must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_handshake_from_ui_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_handshake_t *val) +{ + ism6hg256x_ui_handshake_ctrl_t ui_handshake_ctrl; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); + if (ret != 0) + { + return ret; + } + + val->ack = ui_handshake_ctrl.ui_shared_ack; + val->req = ui_handshake_ctrl.ui_shared_req; + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) IF2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_IF2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface controller to request access to the UI_IF2_SHARED registers. When the R/W operation is finished, the controller must reset this bit.[set] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) IF2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_IF2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface controller to request access to the UI_IF2_SHARED registers. When the R/W operation is finished, the controller must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_handshake_from_ois_set(const stmdev_ctx_t *ctx, + ism6hg256x_ois_handshake_t val) +{ + ism6hg256x_if2_handshake_ctrl_t if2_handshake_ctrl; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF2_HANDSHAKE_CTRL, (uint8_t *)&if2_handshake_ctrl, 1); + if (ret == 0) + { + if2_handshake_ctrl.if2_shared_ack = val.ack; + if2_handshake_ctrl.if2_shared_req = val.req; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_IF2_HANDSHAKE_CTRL, (uint8_t *)&if2_handshake_ctrl, 1); + } + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) IF2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_IF2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface controller to request access to the UI_IF2_SHARED registers. When the R/W operation is finished, the controller must reset this bit.[get] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) IF2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_IF2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface controller to request access to the UI_IF2_SHARED registers. When the R/W operation is finished, the controller must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_handshake_from_ois_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_handshake_t *val) +{ + ism6hg256x_if2_handshake_ctrl_t if2_handshake_ctrl; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF2_HANDSHAKE_CTRL, (uint8_t *)&if2_handshake_ctrl, 1); + if (ret != 0) + { + return ret; + } + + val->ack = if2_handshake_ctrl.if2_shared_ack; + val->req = if2_handshake_ctrl.if2_shared_req; + + return ret; +} + +/** + * @brief User interface (UI) / IF2 (OIS) shared registers[set] + * + * @param ctx read / write interface definitions + * @param val User interface (UI) / IF2 (OIS) shared registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_shared_set(const stmdev_ctx_t *ctx, uint8_t val[6]) +{ + int32_t ret; + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_UI_IF2_SHARED_0, val, 6); + + return ret; +} + +/** + * @brief User interface (UI) / IF2 (OIS) shared registers[get] + * + * @param ctx read / write interface definitions + * @param val User interface (UI) / IF2 (OIS) shared registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_shared_get(const stmdev_ctx_t *ctx, uint8_t val[6]) +{ + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_IF2_SHARED_0, val, 6); + + return ret; +} + +/** + * @brief In User Interface (UI) full control mode, enables IF2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = IF2_CTRL1_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val In User Interface (UI) full control mode, enables IF2 (OIS Interface) for reading OIS data. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_on_if2_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret == 0) + { + ui_ctrl1_ois.if2_spi_read_en = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + } + + return ret; +} + +/** + * @brief In User Interface (UI) full control mode, enables IF2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = IF2_CTRL1_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val In User Interface (UI) full control mode, enables IF2 (OIS Interface) for reading OIS data. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_on_if2_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } + *val = ui_ctrl1_ois.if2_spi_read_en; + + return ret; +} + +/** + * @brief Enables gyroscope/accelerometer OIS chain. This function works also on OIS (UI_CTRL1_OIS = IF2_CTRL1_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val Enables gyroscope/accelerometer OIS chain. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_chain_set(const stmdev_ctx_t *ctx, ism6hg256x_ois_chain_t val) +{ + ism6hg256x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret == 0) + { + ui_ctrl1_ois.ois_g_en = val.gy; + ui_ctrl1_ois.ois_xl_en = val.xl; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + } + + return ret; +} + +/** + * @brief Enables gyroscope/accelerometer OIS chain.[get] + * + * @param ctx read / write interface definitions + * @param val Enables gyroscope/accelerometer OIS chain. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_chain_get(const stmdev_ctx_t *ctx, ism6hg256x_ois_chain_t *val) +{ + ism6hg256x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } + + val->gy = ui_ctrl1_ois.ois_g_en; + val->xl = ui_ctrl1_ois.ois_xl_en; + + return ret; +} + +/** + * @brief Gyroscope OIS full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_gy_full_scale_set(const stmdev_ctx_t *ctx, + ism6hg256x_ois_gy_full_scale_t val) +{ + ism6hg256x_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + if (ret == 0) + { + ui_ctrl2_ois.fs_g_ois = (uint8_t)val & 0x03U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + } + + return ret; +} + +/** + * @brief Gyroscope OIS full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_gy_full_scale_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_gy_full_scale_t *val) +{ + ism6hg256x_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (ui_ctrl2_ois.fs_g_ois) + { + case ISM6HG256X_OIS_250dps: + *val = ISM6HG256X_OIS_250dps; + break; + + case ISM6HG256X_OIS_500dps: + *val = ISM6HG256X_OIS_500dps; + break; + + case ISM6HG256X_OIS_1000dps: + *val = ISM6HG256X_OIS_1000dps; + break; + + case ISM6HG256X_OIS_2000dps: + *val = ISM6HG256X_OIS_2000dps; + break; + + default: + *val = ISM6HG256X_OIS_250dps; + break; + } + + return ret; +} + +/** + * @brief Selects accelerometer OIS channel full-scale.[set] + * + * @param ctx read / write interface definitions + * @param val OIS_2g, OIS_4g, OIS_8g, OIS_16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_xl_full_scale_set(const stmdev_ctx_t *ctx, + ism6hg256x_ois_xl_full_scale_t val) +{ + ism6hg256x_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + if (ret == 0) + { + ui_ctrl3_ois.fs_xl_ois = (uint8_t)val & 0x3U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + } + + return ret; +} + +/** + * @brief Selects accelerometer OIS channel full-scale.[get] + * + * @param ctx read / write interface definitions + * @param val OIS_2g, OIS_4g, OIS_8g, OIS_16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ois_xl_full_scale_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_xl_full_scale_t *val) +{ + ism6hg256x_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (ui_ctrl3_ois.fs_xl_ois) + { + case ISM6HG256X_OIS_2g: + *val = ISM6HG256X_OIS_2g; + break; + + case ISM6HG256X_OIS_4g: + *val = ISM6HG256X_OIS_4g; + break; + + case ISM6HG256X_OIS_8g: + *val = ISM6HG256X_OIS_8g; + break; + + case ISM6HG256X_OIS_16g: + *val = ISM6HG256X_OIS_16g; + break; + + default: + *val = ISM6HG256X_OIS_2g; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Orientation 6D (and 4D) + * @brief This section groups all the functions concerning six position + * detection (6D). + * @{ + * + */ + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_6d_threshold_set(const stmdev_ctx_t *ctx, + ism6hg256x_6d_threshold_t val) +{ + ism6hg256x_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret == 0) + { + tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_6d_threshold_get(const stmdev_ctx_t *ctx, + ism6hg256x_6d_threshold_t *val) +{ + ism6hg256x_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + + switch (tap_ths_6d.sixd_ths) + { + case ISM6HG256X_DEG_80: + *val = ISM6HG256X_DEG_80; + break; + + case ISM6HG256X_DEG_70: + *val = ISM6HG256X_DEG_70; + break; + + case ISM6HG256X_DEG_60: + *val = ISM6HG256X_DEG_60; + break; + + case ISM6HG256X_DEG_50: + *val = ISM6HG256X_DEG_50; + break; + + default: + *val = ISM6HG256X_DEG_80; + break; + } + + return ret; +} + +/** + * @brief 4D orientation detection enable. Z-axis position detection is disabled.[set] + * + * @param ctx read / write interface definitions + * @param val 4D orientation detection enable. Z-axis position detection is disabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret == 0) + { + tap_ths_6d.d4d_en = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief 4D orientation detection enable. Z-axis position detection is disabled.[get] + * + * @param ctx read / write interface definitions + * @param val 4D orientation detection enable. Z-axis position detection is disabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + + *val = tap_ths_6d.d4d_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup SenseWire (I3C) + * @brief This section group all the functions concerning the + * usage of SenseWire (I3C) + * @{ + * + */ + +/** + * @brief I3C configuration.[set] + * + * @param ctx read / write interface definitions + * @param val rst_mode, ibi_time, if2_ta0_pid + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_i3c_config_set(const stmdev_ctx_t *ctx, + ism6hg256x_i3c_config_t val) +{ + ism6hg256x_pin_ctrl_t pin_ctrl; + ism6hg256x_ctrl5_t ctrl5; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + pin_ctrl.ibhr_por_en = (uint8_t)val.rst_mode & 0x01U; + ctrl5.bus_act_sel = (uint8_t)val.ibi_time & 0x03U; + ctrl5.if2_ta0_pid = (uint8_t)val.if2_ta0_pid & 0x01U; + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief I3C configuration.[get] + * + * @param ctx read / write interface definitions + * @param val rst_mode, ibi_time, if2_ta0_pid + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_i3c_config_get(const stmdev_ctx_t *ctx, + ism6hg256x_i3c_config_t *val) +{ + ism6hg256x_pin_ctrl_t pin_ctrl; + ism6hg256x_ctrl5_t ctrl5; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + + switch (pin_ctrl.ibhr_por_en) + { + case ISM6HG256X_SW_RST_DYN_ADDRESS_RST: + val->rst_mode = ISM6HG256X_SW_RST_DYN_ADDRESS_RST; + break; + + case ISM6HG256X_I3C_GLOBAL_RST: + val->rst_mode = ISM6HG256X_I3C_GLOBAL_RST; + break; + + default: + val->rst_mode = ISM6HG256X_SW_RST_DYN_ADDRESS_RST; + break; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl5.bus_act_sel) + { + case 0: + val->ibi_time = ISM6HG256X_IBI_50us; + break; + + case 1: + val->ibi_time = ISM6HG256X_IBI_2us; + break; + + case 2: + val->ibi_time = ISM6HG256X_IBI_1ms; + break; + + case 3: + val->ibi_time = ISM6HG256X_IBI_50ms; + break; + + default: + val->ibi_time = ISM6HG256X_IBI_50us; + break; + } + + val->if2_ta0_pid = ctrl5.if2_ta0_pid; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor hub + * @brief This section groups all the functions that manage the + * sensor hub. + * @{ + * + */ + +/** + * @brief Sensor Hub controller I2C pull-up enable.[set] + * + * @param ctx read / write interface definitions + * @param val Sensor Hub controller I2C pull-up enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_controller_interface_pull_up_set(const stmdev_ctx_t *ctx, + uint8_t val) +{ + ism6hg256x_if_cfg_t if_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.shub_pu_en = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Sensor Hub controller I2C pull-up enable.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor Hub controller I2C pull-up enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_controller_interface_pull_up_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + ism6hg256x_if_cfg_t if_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + + *val = if_cfg.shub_pu_en; + + return ret; +} + +/** + * @brief Sensor hub output registers.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor hub output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, + uint8_t len) +{ + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_SENSOR_HUB_1, val, len); +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[set] + * + * @param ctx read / write interface definitions + * @param val TGT_0, TGT_0_1, TGT_0_1_2, TGT_0_1_2_3, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_target_connected_set(const stmdev_ctx_t *ctx, + ism6hg256x_sh_target_connected_t val) +{ + ism6hg256x_controller_config_t controller_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } + controller_config.aux_sens_on = (uint8_t)val & 0x3U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[get] + * + * @param ctx read / write interface definitions + * @param val TGT_0, TGT_0_1, TGT_0_1_2, TGT_0_1_2_3, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_target_connected_get(const stmdev_ctx_t *ctx, + ism6hg256x_sh_target_connected_t *val) +{ + ism6hg256x_controller_config_t controller_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (controller_config.aux_sens_on) + { + case ISM6HG256X_TGT_0: + *val = ISM6HG256X_TGT_0; + break; + + case ISM6HG256X_TGT_0_1: + *val = ISM6HG256X_TGT_0_1; + break; + + case ISM6HG256X_TGT_0_1_2: + *val = ISM6HG256X_TGT_0_1_2; + break; + + case ISM6HG256X_TGT_0_1_2_3: + *val = ISM6HG256X_TGT_0_1_2_3; + break; + + default: + *val = ISM6HG256X_TGT_0; + break; + } + + return ret; +} + +/** + * @brief Sensor hub I2C controller enable.[set] + * + * @param ctx read / write interface definitions + * @param val Sensor hub I2C controller enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_controller_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_controller_config_t controller_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } + + controller_config.controller_on = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub I2C controller enable.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor hub I2C controller enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_controller_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_controller_config_t controller_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } + + *val = controller_config.controller_on; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief I2C interface pass-through.[set] + * + * @param ctx read / write interface definitions + * @param val I2C interface pass-through. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_controller_config_t controller_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } + + controller_config.pass_through_mode = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief I2C interface pass-through.[get] + * + * @param ctx read / write interface definitions + * @param val I2C interface pass-through. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_controller_config_t controller_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } + + *val = controller_config.pass_through_mode; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[set] + * + * @param ctx read / write interface definitions + * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_syncro_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_sh_syncro_mode_t val) +{ + ism6hg256x_controller_config_t controller_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } + + controller_config.start_config = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[get] + * + * @param ctx read / write interface definitions + * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_syncro_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_sh_syncro_mode_t *val) +{ + ism6hg256x_controller_config_t controller_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (controller_config.start_config) + { + case ISM6HG256X_SH_TRG_XL_GY_DRDY: + *val = ISM6HG256X_SH_TRG_XL_GY_DRDY; + break; + + case ISM6HG256X_SH_TRIG_INT2: + *val = ISM6HG256X_SH_TRIG_INT2; + break; + + default: + *val = ISM6HG256X_SH_TRG_XL_GY_DRDY; + break; + } + + return ret; +} + +/** + * @brief Target 0 write operation is performed only at the first sensor hub cycle.[set] + * + * @param ctx read / write interface definitions + * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_write_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_sh_write_mode_t val) +{ + ism6hg256x_controller_config_t controller_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } + + controller_config.write_once = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Target 0 write operation is performed only at the first sensor hub cycle.[get] + * + * @param ctx read / write interface definitions + * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_write_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_sh_write_mode_t *val) +{ + ism6hg256x_controller_config_t controller_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (controller_config.write_once) + { + case ISM6HG256X_EACH_SH_CYCLE: + *val = ISM6HG256X_EACH_SH_CYCLE; + break; + + case ISM6HG256X_ONLY_FIRST_CYCLE: + *val = ISM6HG256X_ONLY_FIRST_CYCLE; + break; + + default: + *val = ISM6HG256X_EACH_SH_CYCLE; + break; + } + + return ret; +} + +/** + * @brief Reset Controller logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set] + * + * @param ctx read / write interface definitions + * @param val Reset Controller logic and output registers. Must be set to ‘1’ and then set it to ‘0’. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_controller_config_t controller_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } + + controller_config.rst_controller_regs = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset Controller logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get] + * + * @param ctx read / write interface definitions + * @param val Reset Controller logic and output registers. Must be set to ‘1’ and then set it to ‘0’. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_controller_config_t controller_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } + + *val = controller_config.rst_controller_regs; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Configure target 0 for perform a write.[set] + * + * @param ctx read / write interface definitions + * @param val a structure that contain + * - uint8_t tgt1_add; 8 bit i2c device address + * - uint8_t tgt1_subadd; 8 bit register device address + * - uint8_t tgt1_data; 8 bit data to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_cfg_write(const stmdev_ctx_t *ctx, + ism6hg256x_sh_cfg_write_t *val) +{ + ism6hg256x_tgt0_add_t reg; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + reg.target0_add = val->tgt0_add; + reg.rw_0 = 0; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TGT0_ADD, (uint8_t *)®, 1); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TGT0_SUBADD, + &(val->tgt0_subadd), 1); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_DATAWRITE_TGT0, + &(val->tgt0_data), 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Rate at which the controller communicates.[set] + * + * @param ctx read / write interface definitions + * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_sh_data_rate_t val) +{ + ism6hg256x_tgt0_config_t tgt0_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_TGT0_CONFIG, (uint8_t *)&tgt0_config, 1); + if (ret != 0) + { + goto exit; + } + + tgt0_config.shub_odr = (uint8_t)val & 0x07U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TGT0_CONFIG, (uint8_t *)&tgt0_config, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Rate at which the controller communicates.[get] + * + * @param ctx read / write interface definitions + * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_sh_data_rate_t *val) +{ + ism6hg256x_tgt0_config_t tgt0_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_TGT0_CONFIG, (uint8_t *)&tgt0_config, 1); + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (tgt0_config.shub_odr) + { + case ISM6HG256X_SH_15Hz: + *val = ISM6HG256X_SH_15Hz; + break; + + case ISM6HG256X_SH_30Hz: + *val = ISM6HG256X_SH_30Hz; + break; + + case ISM6HG256X_SH_60Hz: + *val = ISM6HG256X_SH_60Hz; + break; + + case ISM6HG256X_SH_120Hz: + *val = ISM6HG256X_SH_120Hz; + break; + + case ISM6HG256X_SH_240Hz: + *val = ISM6HG256X_SH_240Hz; + break; + + case ISM6HG256X_SH_480Hz: + *val = ISM6HG256X_SH_480Hz; + break; + + default: + *val = ISM6HG256X_SH_15Hz; + break; + } + + return ret; +} + +/** + * @brief Configure target idx for perform a read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t tgt_add; 8 bit i2c device address + * - uint8_t tgt_subadd; 8 bit register device address + * - uint8_t tgt_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_tgt_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, + ism6hg256x_sh_cfg_read_t *val) +{ + ism6hg256x_tgt0_add_t tgt_add; + ism6hg256x_tgt0_config_t tgt_config; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } + + tgt_add.target0_add = val->tgt_add; + tgt_add.rw_0 = 1; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TGT0_ADD + idx * 3U, + (uint8_t *)&tgt_add, 1); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TGT0_SUBADD + idx * 3U, + &(val->tgt_subadd), 1); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TGT0_CONFIG + idx * 3U, + (uint8_t *)&tgt_config, 1); + if (ret != 0) + { + goto exit; + } + + tgt_config.target0_numop = val->tgt_len; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TGT0_CONFIG + idx * 3U, + (uint8_t *)&tgt_config, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub source register.[get] + * + * @param ctx read / write interface definitions + * @param val union of registers from STATUS_CONTROLLER to + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sh_status_get(const stmdev_ctx_t *ctx, + ism6hg256x_status_controller_t *val) +{ + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_STATUS_CONTROLLER_MAINPAGE, (uint8_t *) val, 1); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Serial interfaces + * @brief This section groups all the functions concerning + * serial interfaces management (not auxiliary) + * @{ + * + */ + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.sdo_pu_en = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + + *val = pin_ctrl.sdo_pu_en; + + return ret; +} + +/** + * @brief Pad strength.[set] + * + * @param ctx read / write interface definitions + * @param val Pad strength + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_pad_strength_set(const stmdev_ctx_t *ctx, ism6hg256x_pad_strength_t val) +{ + ism6hg256x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.io_pad_strength = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Pad strength.[get] + * + * @param ctx read / write interface definitions + * @param val Pad strength + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_pad_strength_get(const stmdev_ctx_t *ctx, ism6hg256x_pad_strength_t *val) +{ + ism6hg256x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + + switch (pin_ctrl.io_pad_strength) + { + case 0: + *val = ISM6HG256X_PAD_LOW_STRENGTH; + break; + + case 1: + *val = ISM6HG256X_PAD_MIDDLE_STRENGTH; + break; + + case 2: + default: + *val = ISM6HG256X_PAD_HIGH_STRENGTH; + break; + } + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_ui_i2c_i3c_mode_t val) +{ + ism6hg256x_if_cfg_t if_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.i2c_i3c_disable = (uint8_t)val & 0x1U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_ui_i2c_i3c_mode_t *val) +{ + ism6hg256x_if_cfg_t if_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + + switch (if_cfg.i2c_i3c_disable) + { + case ISM6HG256X_I2C_I3C_ENABLE: + *val = ISM6HG256X_I2C_I3C_ENABLE; + break; + + case ISM6HG256X_I2C_I3C_DISABLE: + *val = ISM6HG256X_I2C_I3C_DISABLE; + break; + + default: + *val = ISM6HG256X_I2C_I3C_ENABLE; + break; + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_spi_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_spi_mode_t val) +{ + ism6hg256x_if_cfg_t if_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sim = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_spi_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_spi_mode_t *val) +{ + ism6hg256x_if_cfg_t if_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + + switch (if_cfg.sim) + { + case ISM6HG256X_SPI_4_WIRE: + *val = ISM6HG256X_SPI_4_WIRE; + break; + + case ISM6HG256X_SPI_3_WIRE: + *val = ISM6HG256X_SPI_3_WIRE; + break; + + default: + *val = ISM6HG256X_SPI_4_WIRE; + break; + } + + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_if_cfg_t if_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sda_pu_en = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_if_cfg_t if_cfg; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + + *val = if_cfg.sda_pu_en; + + return ret; +} + +/** + * @brief IF2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = IF2_CTRL1_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_if2_spi_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_spi_mode_t val) +{ + ism6hg256x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret == 0) + { + ui_ctrl1_ois.sim_ois = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + } + + return ret; +} + +/** + * @brief IF2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = IF2_CTRL1_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_if2_spi_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_spi_mode_t *val) +{ + ism6hg256x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (ui_ctrl1_ois.sim_ois) + { + case ISM6HG256X_SPI_4_WIRE: + *val = ISM6HG256X_SPI_4_WIRE; + break; + + case ISM6HG256X_SPI_3_WIRE: + *val = ISM6HG256X_SPI_3_WIRE; + break; + + default: + *val = ISM6HG256X_SPI_4_WIRE; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Significant motion detection + * @brief This section groups all the functions that manage the + * significant motion detection. + * @{ + * + */ + + +/** + * @brief Enables significant motion detection function.[set] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret != 0) + { + goto exit; + } + emb_func_en_a.sign_motion_en = val; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables significant motion detection function.[get] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret != 0) + { + goto exit; + } + *val = emb_func_en_a.sign_motion_en; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Step Counter (Pedometer) + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Step counter mode[set] + * + * @param ctx read / write interface definitions + * @param val Step counter mode + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_stpcnt_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_stpcnt_mode_t val) +{ + ism6hg256x_emb_func_en_a_t emb_func_en_a; + ism6hg256x_emb_func_en_b_t emb_func_en_b; + ism6hg256x_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + if (ret != 0) + { + goto exit; + } + + if ((val.false_step_rej == PROPERTY_ENABLE) + && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == + PROPERTY_DISABLE)) + { + emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + } + + emb_func_en_a.pedo_en = val.step_counter_enable; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); + if (ret != 0) + { + return ret; + } + pedo_cmd_reg.fp_rejection_en = val.false_step_rej; + ret += ism6hg256x_ln_pg_write(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); + } + + return ret; +} + +/** + * @brief Step counter mode[get] + * + * @param ctx read / write interface definitions + * @param val false_step_rej, step_counter, step_detector, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_stpcnt_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_stpcnt_mode_t *val) +{ + ism6hg256x_emb_func_en_a_t emb_func_en_a; + ism6hg256x_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); + if (ret != 0) + { + return ret; + } + + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + + return ret; +} + +/** + * @brief Step counter output, number of detected steps.[get] + * + * @param ctx read / write interface definitions + * @param val Step counter output, number of detected steps. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_STEP_COUNTER_L, &buff[0], 2); + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Reset step counter.[set] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_emb_func_src_t emb_func_src; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + if (ret != 0) + { + goto exit; + } + + emb_func_src.pedo_rst_step = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset step counter.[get] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_emb_func_src_t emb_func_src; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + if (ret != 0) + { + goto exit; + } + *val = emb_func_src.pedo_rst_step; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); + if (ret == 0) + { + pedo_deb_steps_conf.deb_step = val; + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); + } + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); + if (ret != 0) + { + return ret; + } + *val = pedo_deb_steps_conf.deb_step; + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[set] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = ism6hg256x_ln_pg_write(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_PEDO_SC_DELTAT_L, + (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[get] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism6hg256x_ln_pg_read(ctx, ISM6HG256X_EMB_ADV_PG_1 + ISM6HG256X_PEDO_SC_DELTAT_L, &buff[0], + 2); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor Fusion Low Power (SFLP) + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[set] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret != 0) + { + goto exit; + } + + emb_func_en_a.sflp_game_en = val; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[get] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret != 0) + { + goto exit; + } + *val = emb_func_en_a.sflp_game_en; + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset SFLP Game Rotation Vector logic (6x). + * + * @param ctx read / write interface definitions + * @param val 1: reset, 0: stop reset procedure + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sflp_game_rotation_reset(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_emb_func_init_a_t emb_func_init_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_INIT_A, (uint8_t *)&emb_func_init_a, 1); + if (ret != 0) + { + goto exit; + } + emb_func_init_a.sflp_game_init = val; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_INIT_A, (uint8_t *)&emb_func_init_a, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sflp_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_sflp_data_rate_t val) +{ + ism6hg256x_sflp_odr_t sflp_odr; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + if (ret != 0) + { + goto exit; + } + + sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + +exit: + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_sflp_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_sflp_data_rate_t *val) +{ + ism6hg256x_sflp_odr_t sflp_odr; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (sflp_odr.sflp_game_odr) + { + case ISM6HG256X_SFLP_15Hz: + *val = ISM6HG256X_SFLP_15Hz; + break; + + case ISM6HG256X_SFLP_30Hz: + *val = ISM6HG256X_SFLP_30Hz; + break; + + case ISM6HG256X_SFLP_60Hz: + *val = ISM6HG256X_SFLP_60Hz; + break; + + case ISM6HG256X_SFLP_120Hz: + *val = ISM6HG256X_SFLP_120Hz; + break; + + case ISM6HG256X_SFLP_240Hz: + *val = ISM6HG256X_SFLP_240Hz; + break; + + case ISM6HG256X_SFLP_480Hz: + *val = ISM6HG256X_SFLP_480Hz; + break; + + default: + *val = ISM6HG256X_SFLP_15Hz; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tap - Double Tap + * @brief This section groups all the functions that manage the + * tap and double tap event generation. + * @{ + * + */ + +/** + * @brief Enable axis for Tap - Double Tap detection.[set] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_tap_detection_set(const stmdev_ctx_t *ctx, + ism6hg256x_tap_detection_t val) +{ + ism6hg256x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.tap_x_en = val.tap_x_en; + tap_cfg0.tap_y_en = val.tap_y_en; + tap_cfg0.tap_z_en = val.tap_z_en; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Enable axis for Tap - Double Tap detection.[get] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_tap_detection_get(const stmdev_ctx_t *ctx, + ism6hg256x_tap_detection_t *val) +{ + ism6hg256x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + + val->tap_x_en = tap_cfg0.tap_x_en; + val->tap_y_en = tap_cfg0.tap_y_en; + val->tap_z_en = tap_cfg0.tap_z_en; + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[set] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_tap_thresholds_set(const stmdev_ctx_t *ctx, + ism6hg256x_tap_thresholds_t val) +{ + ism6hg256x_tap_ths_6d_t tap_ths_6d; + ism6hg256x_tap_cfg2_t tap_cfg2; + ism6hg256x_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + + tap_cfg1.tap_ths_x = val.x; + tap_cfg2.tap_ths_y = val.y; + tap_ths_6d.tap_ths_z = val.z; + + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[get] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_tap_thresholds_get(const stmdev_ctx_t *ctx, + ism6hg256x_tap_thresholds_t *val) +{ + ism6hg256x_tap_ths_6d_t tap_ths_6d; + ism6hg256x_tap_cfg2_t tap_cfg2; + ism6hg256x_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + + val->x = tap_cfg1.tap_ths_x; + val->y = tap_cfg2.tap_ths_y; + val->z = tap_ths_6d.tap_ths_z; + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[set] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_tap_axis_priority_set(const stmdev_ctx_t *ctx, + ism6hg256x_tap_axis_priority_t val) +{ + ism6hg256x_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + tap_cfg1.tap_priority = (uint8_t)val & 0x7U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[get] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_tap_axis_priority_get(const stmdev_ctx_t *ctx, + ism6hg256x_tap_axis_priority_t *val) +{ + ism6hg256x_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) + { + return ret; + } + + switch (tap_cfg1.tap_priority) + { + case ISM6HG256X_XYZ : + *val = ISM6HG256X_XYZ ; + break; + + case ISM6HG256X_YXZ : + *val = ISM6HG256X_YXZ ; + break; + + case ISM6HG256X_XZY: + *val = ISM6HG256X_XZY; + break; + + case ISM6HG256X_ZYX : + *val = ISM6HG256X_ZYX ; + break; + + case ISM6HG256X_YZX : + *val = ISM6HG256X_YZX ; + break; + + case ISM6HG256X_ZXY : + *val = ISM6HG256X_ZXY ; + break; + + default: + *val = ISM6HG256X_XYZ ; + break; + } + + return ret; +} + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_tap_time_windows_set(const stmdev_ctx_t *ctx, + ism6hg256x_tap_time_windows_t val) +{ + ism6hg256x_tap_dur_t tap_dur; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret == 0) + { + tap_dur.shock = val.shock; + tap_dur.quiet = val.quiet; + tap_dur.dur = val.tap_gap; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_TAP_DUR, (uint8_t *)&tap_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_tap_time_windows_get(const stmdev_ctx_t *ctx, + ism6hg256x_tap_time_windows_t *val) +{ + ism6hg256x_tap_dur_t tap_dur; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret != 0) + { + return ret; + } + + val->shock = tap_dur.shock; + val->quiet = tap_dur.quiet; + val->tap_gap = tap_dur.dur; + + return ret; +} + +/** + * @brief Single/double-tap event enable.[set] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_tap_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_tap_mode_t val) +{ + ism6hg256x_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.single_double_tap = (uint8_t)val & 0x01U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Single/double-tap event enable.[get] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_tap_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_tap_mode_t *val) +{ + ism6hg256x_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + + switch (wake_up_ths.single_double_tap) + { + case ISM6HG256X_ONLY_SINGLE: + *val = ISM6HG256X_ONLY_SINGLE; + break; + + case ISM6HG256X_BOTH_SINGLE_DOUBLE: + *val = ISM6HG256X_BOTH_SINGLE_DOUBLE; + break; + + default: + *val = ISM6HG256X_ONLY_SINGLE; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tilt detection + * @brief This section groups all the functions that manage the tilt + * event detection. + * @{ + * + */ + +/** + * @brief Tilt calculation.[set] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.tilt_en = val; + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Tilt calculation.[get] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = ism6hg256x_mem_bank_set(ctx, ISM6HG256X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.tilt_en; + + ret += ism6hg256x_mem_bank_set(ctx, ISM6HG256X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Timestamp data output.[get] + * + * @param ctx read / write interface definitions + * @param val Timestamp data output. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_TIMESTAMP0, &buff[0], 4); + if (ret != 0) + { + return ret; + } + + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism6hg256x_functions_enable_t functions_enable; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.timestamp_en = val; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism6hg256x_functions_enable_t functions_enable; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + + *val = functions_enable.timestamp_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Wake Up - Activity - Inactivity (Sleep) + * @brief This section groups all the functions that manage the Wake Up + * event generation. + * @{ + * + */ + +/** + * @brief Enable activity/inactivity (sleep) function.[set] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_act_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_act_mode_t val) +{ + ism6hg256x_functions_enable_t functions_enable; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.inact_en = (uint8_t)val & 0x3U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enable activity/inactivity (sleep) function.[get] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_act_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_act_mode_t *val) +{ + ism6hg256x_functions_enable_t functions_enable; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + + switch (functions_enable.inact_en) + { + case ISM6HG256X_XL_AND_GY_NOT_AFFECTED: + *val = ISM6HG256X_XL_AND_GY_NOT_AFFECTED; + break; + + case ISM6HG256X_XL_LOW_POWER_GY_NOT_AFFECTED: + *val = ISM6HG256X_XL_LOW_POWER_GY_NOT_AFFECTED; + break; + + case ISM6HG256X_XL_LOW_POWER_GY_SLEEP: + *val = ISM6HG256X_XL_LOW_POWER_GY_SLEEP; + break; + + case ISM6HG256X_XL_LOW_POWER_GY_POWER_DOWN: + *val = ISM6HG256X_XL_LOW_POWER_GY_POWER_DOWN; + break; + + default: + *val = ISM6HG256X_XL_AND_GY_NOT_AFFECTED; + break; + } + + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, + ism6hg256x_act_from_sleep_to_act_dur_t val) +{ + ism6hg256x_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.inact_dur = (uint8_t)val & 0x3U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, + ism6hg256x_act_from_sleep_to_act_dur_t *val) +{ + ism6hg256x_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret != 0) + { + return ret; + } + + switch (inactivity_dur.inact_dur) + { + case ISM6HG256X_SLEEP_TO_ACT_AT_1ST_SAMPLE: + *val = ISM6HG256X_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + + case ISM6HG256X_SLEEP_TO_ACT_AT_2ND_SAMPLE: + *val = ISM6HG256X_SLEEP_TO_ACT_AT_2ND_SAMPLE; + break; + + case ISM6HG256X_SLEEP_TO_ACT_AT_3RD_SAMPLE: + *val = ISM6HG256X_SLEEP_TO_ACT_AT_3RD_SAMPLE; + break; + + case ISM6HG256X_SLEEP_TO_ACT_AT_4th_SAMPLE: + *val = ISM6HG256X_SLEEP_TO_ACT_AT_4th_SAMPLE; + break; + + default: + *val = ISM6HG256X_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + } + + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[set] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, + ism6hg256x_act_sleep_xl_odr_t val) +{ + ism6hg256x_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[get] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, + ism6hg256x_act_sleep_xl_odr_t *val) +{ + ism6hg256x_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret != 0) + { + return ret; + } + + switch (inactivity_dur.xl_inact_odr) + { + case ISM6HG256X_1Hz875: + *val = ISM6HG256X_1Hz875; + break; + + case ISM6HG256X_15Hz: + *val = ISM6HG256X_15Hz; + break; + + case ISM6HG256X_30Hz: + *val = ISM6HG256X_30Hz; + break; + + case ISM6HG256X_60Hz: + *val = ISM6HG256X_60Hz; + break; + + default: + *val = ISM6HG256X_1Hz875; + break; + } + + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[set] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_act_thresholds_set(const stmdev_ctx_t *ctx, + ism6hg256x_act_thresholds_t *val) +{ + ism6hg256x_inactivity_ths_t inactivity_ths; + ism6hg256x_inactivity_dur_t inactivity_dur; + ism6hg256x_wake_up_ths_t wake_up_ths; + ism6hg256x_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + + inactivity_dur.wu_inact_ths_w = val->inactivity_cfg.wu_inact_ths_w; + inactivity_dur.xl_inact_odr = val->inactivity_cfg.xl_inact_odr; + inactivity_dur.inact_dur = val->inactivity_cfg.inact_dur; + + inactivity_ths.inact_ths = val->inactivity_ths; + wake_up_ths.wk_ths = val->threshold; + wake_up_dur.wake_dur = val->duration; + + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += ism6hg256x_write_reg(ctx, ISM6HG256X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[get] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_act_thresholds_get(const stmdev_ctx_t *ctx, + ism6hg256x_act_thresholds_t *val) +{ + ism6hg256x_inactivity_dur_t inactivity_dur; + ism6hg256x_inactivity_ths_t inactivity_ths; + ism6hg256x_wake_up_ths_t wake_up_ths; + ism6hg256x_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += ism6hg256x_read_reg(ctx, ISM6HG256X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + + val->inactivity_cfg.wu_inact_ths_w = inactivity_dur.wu_inact_ths_w; + val->inactivity_cfg.xl_inact_odr = inactivity_dur.xl_inact_odr; + val->inactivity_cfg.inact_dur = inactivity_dur.inact_dur; + + val->inactivity_ths = inactivity_ths.inact_ths; + val->threshold = wake_up_ths.wk_ths; + val->duration = wake_up_dur.wake_dur; + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, + ism6hg256x_act_wkup_time_windows_t val) +{ + ism6hg256x_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_dur = val.shock; + wake_up_dur.sleep_dur = val.quiet; + ret = ism6hg256x_write_reg(ctx, ISM6HG256X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism6hg256x_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, + ism6hg256x_act_wkup_time_windows_t *val) +{ + ism6hg256x_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = ism6hg256x_read_reg(ctx, ISM6HG256X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + + val->shock = wake_up_dur.wake_dur; + val->quiet = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ diff --git a/sensor/stmemsc/ism6hg256x_STdC/driver/ism6hg256x_reg.h b/sensor/stmemsc/ism6hg256x_STdC/driver/ism6hg256x_reg.h new file mode 100644 index 0000000..42e3f31 --- /dev/null +++ b/sensor/stmemsc/ism6hg256x_STdC/driver/ism6hg256x_reg.h @@ -0,0 +1,5828 @@ +/** + ****************************************************************************** + * @file ism6hg256x_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * ism6hg256x_reg.c driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef ISM6HG256X_REGS_H +#define ISM6HG256X_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup ISM6HG256X + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; + + /** private data **/ + void *priv_data; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup ISM6HG256X_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define ISM6HG256X_I2C_ADD_L 0xD5U +#define ISM6HG256X_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define ISM6HG256X_ID 0x73U + +/** + * @} + * + */ + +/** @defgroup bitfields page main + * @{ + * + */ + +#define ISM6HG256X_FUNC_CFG_ACCESS 0x1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ois_ctrl_from_ui : 1; + uint8_t if2_reset : 1; + uint8_t sw_por : 1; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t not_used0 : 2; + uint8_t shub_reg_access : 1; + uint8_t emb_func_reg_access : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_reg_access : 1; + uint8_t shub_reg_access : 1; + uint8_t not_used0 : 2; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t sw_por : 1; + uint8_t if2_reset : 1; + uint8_t ois_ctrl_from_ui : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_func_cfg_access_t; + +#define ISM6HG256X_PIN_CTRL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t io_pad_strength : 2; + uint8_t not_used0 : 3; + uint8_t ibhr_por_en : 1; + uint8_t sdo_pu_en : 1; + uint8_t ois_pu_dis : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ois_pu_dis : 1; + uint8_t sdo_pu_en : 1; + uint8_t ibhr_por_en : 1; + uint8_t not_used0 : 3; + uint8_t io_pad_strength : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_pin_ctrl_t; + +#define ISM6HG256X_IF_CFG 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t i2c_i3c_disable : 1; + uint8_t not_used0 : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t asf_ctrl : 1; + uint8_t shub_pu_en : 1; + uint8_t sda_pu_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sda_pu_en : 1; + uint8_t shub_pu_en : 1; + uint8_t asf_ctrl : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t not_used0 : 1; + uint8_t i2c_i3c_disable : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if_cfg_t; + +#define ISM6HG256X_ODR_TRIG_CFG 0x6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_trig_nodr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_trig_nodr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_odr_trig_cfg_t; + +#define ISM6HG256X_FIFO_CTRL1 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wtm : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wtm : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_ctrl1_t; + +#define ISM6HG256X_FIFO_CTRL2 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used2 : 1; + uint8_t uncompr_rate : 2; + uint8_t not_used0 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used1 : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t stop_on_wtm : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stop_on_wtm : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t not_used1 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used0 : 1; + uint8_t uncompr_rate : 2; + uint8_t not_used2 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_ctrl2_t; + +#define ISM6HG256X_FIFO_CTRL3 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 4; + uint8_t bdr_gy : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bdr_gy : 4; + uint8_t bdr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_ctrl3_t; + +#define ISM6HG256X_FIFO_CTRL4 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t g_eis_fifo_en : 1; + uint8_t odr_t_batch : 2; + uint8_t dec_ts_batch : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dec_ts_batch : 2; + uint8_t odr_t_batch : 2; + uint8_t g_eis_fifo_en : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_ctrl4_t; + +#define ISM6HG256X_COUNTER_BDR_REG1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 2; + uint8_t not_used0 : 1; + uint8_t xl_hg_batch_en : 1; + uint8_t not_used2 : 1; + uint8_t trig_counter_bdr : 2; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t trig_counter_bdr : 2; + uint8_t not_used2 : 1; + uint8_t xl_hg_batch_en : 1; + uint8_t not_used0 : 1; + uint8_t cnt_bdr_th : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_counter_bdr_reg1_t; + +#define ISM6HG256X_COUNTER_BDR_REG2 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t cnt_bdr_th : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_counter_bdr_reg2_t; + +#define ISM6HG256X_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t not_used0 : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t not_used0 : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_int1_ctrl_t; + +#define ISM6HG256X_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_g_eis : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_emb_func_endop : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_emb_func_endop : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_drdy_g_eis : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_int2_ctrl_t; + +#define ISM6HG256X_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_who_am_i_t; + +#define ISM6HG256X_CTRL1 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_xl : 4; + uint8_t op_mode_xl : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_xl : 3; + uint8_t odr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl1_t; + +#define ISM6HG256X_CTRL2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_g : 4; + uint8_t op_mode_g : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_g : 3; + uint8_t odr_g : 4; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl2_t; + +#define ISM6HG256X_CTRL3 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used0 : 1; + uint8_t if_inc : 1; + uint8_t not_used1 : 3; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t not_used1 : 3; + uint8_t if_inc : 1; + uint8_t not_used0 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl3_t; + +#define ISM6HG256X_CTRL4 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_in_lh : 1; + uint8_t drdy_pulsed : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_mask : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_on_int1 : 1; + uint8_t drdy_mask : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_pulsed : 1; + uint8_t int2_in_lh : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl4_t; + +#define ISM6HG256X_CTRL5 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int_en_i3c : 1; + uint8_t bus_act_sel : 2; + uint8_t not_used0 : 4; + uint8_t if2_ta0_pid : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_ta0_pid : 1; + uint8_t not_used0 : 4; + uint8_t not_used0 : 4; + uint8_t bus_act_sel : 2; + uint8_t int_en_i3c : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl5_t; + +#define ISM6HG256X_CTRL6 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g : 3; + uint8_t not_used1 : 1; + uint8_t lpf1_g_bw : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t lpf1_g_bw : 3; + uint8_t not_used1 : 1; + uint8_t fs_g : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl6_t; + +#define ISM6HG256X_CTRL7 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lpf1_g_en : 1; + uint8_t not_used0 : 5; + uint8_t int2_drdy_xl_hg : 1; + uint8_t int1_drdy_xl_hg : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_drdy_xl_hg : 1; + uint8_t int2_drdy_xl_hg : 1; + uint8_t not_used0 : 5; + uint8_t lpf1_g_en : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl7_t; + +#define ISM6HG256X_CTRL8 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl : 2; + uint8_t not_used0 : 3; + uint8_t hp_lpf2_xl_bw : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hp_lpf2_xl_bw : 3; + uint8_t not_used0 : 3; + uint8_t fs_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl8_t; + +#define ISM6HG256X_CTRL9 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t usr_off_on_out : 1; + uint8_t usr_off_w : 1; + uint8_t not_used0 : 1; + uint8_t lpf2_xl_en : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t lpf2_xl_en : 1; + uint8_t not_used0 : 1; + uint8_t usr_off_w : 1; + uint8_t usr_off_on_out : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl9_t; + +#define ISM6HG256X_CTRL10 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t not_used0 : 2; + uint8_t emb_func_debug : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t emb_func_debug : 1; + uint8_t not_used0 : 2; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl10_t; + +#define ISM6HG256X_CTRL_STATUS 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl_status_t; + +#define ISM6HG256X_FIFO_STATUS1 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t diff_fifo : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_status1_t; + +#define ISM6HG256X_FIFO_STATUS2 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 1; + uint8_t not_used0 : 2; + uint8_t fifo_ovr_latched : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_ovr_latched : 1; + uint8_t not_used0 : 2; + uint8_t diff_fifo : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_status2_t; + +#define ISM6HG256X_ALL_INT_SRC 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia : 1; + uint8_t wu_ia : 1; + uint8_t tap_ia : 1; + uint8_t hg_ia : 1; + uint8_t d6d_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t shub_ia : 1; + uint8_t emb_func_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_ia : 1; + uint8_t shub_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t d6d_ia : 1; + uint8_t hg_ia : 1; + uint8_t tap_ia : 1; + uint8_t wu_ia : 1; + uint8_t ff_ia : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_all_int_src_t; + +#define ISM6HG256X_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t xlhgda : 1; + uint8_t gda_eis : 1; + uint8_t ois_drdy : 1; + uint8_t not_used0 : 1; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used0 : 1; + uint8_t ois_drdy : 1; + uint8_t gda_eis : 1; + uint8_t xlhgda : 1; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_status_reg_t; + +#define ISM6HG256X_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_out_temp_l_t; + +#define ISM6HG256X_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_out_temp_h_t; + +#define ISM6HG256X_OUTX_L_G 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_outx_l_g_t; + +#define ISM6HG256X_OUTX_H_G 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_outx_h_g_t; + +#define ISM6HG256X_OUTY_L_G 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_outy_l_g_t; + +#define ISM6HG256X_OUTY_H_G 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_outy_h_g_t; + +#define ISM6HG256X_OUTZ_L_G 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_outz_l_g_t; + +#define ISM6HG256X_OUTZ_H_G 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_outz_h_g_t; + +#define ISM6HG256X_OUTX_L_A 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_outx_l_a_t; + +#define ISM6HG256X_OUTX_H_A 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_outx_h_a_t; + +#define ISM6HG256X_OUTY_L_A 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_outy_l_a_t; + +#define ISM6HG256X_OUTY_H_A 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_outy_h_a_t; + +#define ISM6HG256X_OUTZ_L_A 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_outz_l_a_t; + +#define ISM6HG256X_OUTZ_H_A 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_outz_h_a_t; + +#define ISM6HG256X_UI_OUTX_L_G_OIS_EIS 0x2EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_outx_l_g_ois_eis_t; + +#define ISM6HG256X_UI_OUTX_H_G_OIS_EIS 0x2FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_outx_h_g_ois_eis_t; + +#define ISM6HG256X_UI_OUTY_L_G_OIS_EIS 0x30U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_outy_l_g_ois_eis_t; + +#define ISM6HG256X_UI_OUTY_H_G_OIS_EIS 0x31U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_outy_h_g_ois_eis_t; + +#define ISM6HG256X_UI_OUTZ_L_G_OIS_EIS 0x32U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_outz_l_g_ois_eis_t; + +#define ISM6HG256X_UI_OUTZ_H_G_OIS_EIS 0x33U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_outz_h_g_ois_eis_t; + +#define ISM6HG256X_UI_OUTX_L_A_OIS_HG 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_ois_hg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_ois_hg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_outx_l_a_ois_hg_t; + +#define ISM6HG256X_UI_OUTX_H_A_OIS_HG 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_ois_hg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_ois_hg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_outx_h_a_ois_hg_t; + +#define ISM6HG256X_UI_OUTY_L_A_OIS_HG 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_ois_hg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_ois_hg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_outy_l_a_ois_hg_t; + +#define ISM6HG256X_UI_OUTY_H_A_OIS_HG 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_ois_hg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_ois_hg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_outy_h_a_ois_hg_t; + +#define ISM6HG256X_UI_OUTZ_L_A_OIS_HG 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_ois_hg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_ois_hg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_outz_l_a_ois_hg_t; + +#define ISM6HG256X_UI_OUTZ_H_A_OIS_HG 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_ois_hg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_ois_hg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_outz_h_a_ois_hg_t; + +#define ISM6HG256X_TIMESTAMP0 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_timestamp0_t; + +#define ISM6HG256X_TIMESTAMP1 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_timestamp1_t; + +#define ISM6HG256X_TIMESTAMP2 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_timestamp2_t; + +#define ISM6HG256X_TIMESTAMP3 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_timestamp3_t; + +#define ISM6HG256X_UI_STATUS_REG_OIS 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda_ois : 1; + uint8_t gda_ois : 1; + uint8_t gyro_settling : 1; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t gyro_settling : 1; + uint8_t gda_ois : 1; + uint8_t xlda_ois : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_status_reg_ois_t; + +#define ISM6HG256X_WAKE_UP_SRC 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_wake_up_src_t; + +#define ISM6HG256X_TAP_SRC 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; + uint8_t tap_sign : 1; + uint8_t double_tap : 1; + uint8_t single_tap : 1; + uint8_t tap_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t tap_ia : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_sign : 1; + uint8_t x_tap : 1; + uint8_t y_tap : 1; + uint8_t z_tap : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tap_src_t; + +#define ISM6HG256X_D6D_SRC 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t zh : 1; + uint8_t zl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t xh : 1; + uint8_t xl : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_d6d_src_t; + +#define ISM6HG256X_STATUS_CONTROLLER_MAINPAGE 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used0 : 2; + uint8_t target0_nack : 1; + uint8_t target1_nack : 1; + uint8_t target2_nack : 1; + uint8_t target3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t target3_nack : 1; + uint8_t target2_nack : 1; + uint8_t target1_nack : 1; + uint8_t target0_nack : 1; + uint8_t not_used0 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_status_controller_mainpage_t; + +#define ISM6HG256X_EMB_FUNC_STATUS_MAINPAGE 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_status_mainpage_t; + +#define ISM6HG256X_FSM_STATUS_MAINPAGE 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_status_mainpage_t; + +#define ISM6HG256X_MLC_STATUS_MAINPAGE 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_mlc8 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc_status_mainpage_t; + +#define ISM6HG256X_HG_WAKE_UP_SRC 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t hg_z_wu : 1; + uint8_t hg_y_wu : 1; + uint8_t hg_x_wu : 1; + uint8_t hg_wu_ia : 1; + uint8_t hg_wu_change_ia : 1; + uint8_t hg_shock_state : 1; + uint8_t hg_shock_change_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t hg_shock_change_ia : 1; + uint8_t hg_shock_state : 1; + uint8_t hg_wu_change_ia : 1; + uint8_t hg_wu_ia : 1; + uint8_t hg_x_wu : 1; + uint8_t hg_y_wu : 1; + uint8_t hg_z_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_hg_wake_up_src_t; + +#define ISM6HG256X_CTRL2_XL_HG 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_hg_st : 2; + uint8_t not_used0 : 2; + uint8_t hg_usr_off_on_wu : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t hg_usr_off_on_wu : 1; + uint8_t not_used0 : 2; + uint8_t xl_hg_st : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl2_xl_hg_t; + +#define ISM6HG256X_CTRL1_XL_HG 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl_hg : 3; + uint8_t odr_xl_hg : 3; + uint8_t hg_usr_off_on_out : 1; + uint8_t xl_hg_regout_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t xl_hg_regout_en : 1; + uint8_t hg_usr_off_on_out : 1; + uint8_t odr_xl_hg : 3; + uint8_t fs_xl_hg : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl1_xl_hg_t; + +#define ISM6HG256X_INTERNAL_FREQ 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t freq_fine : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t freq_fine : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_internal_freq_t; + +#define ISM6HG256X_FUNCTIONS_ENABLE 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_en : 2; + uint8_t not_used0 : 1; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used1 : 2; + uint8_t timestamp_en : 1; + uint8_t interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t timestamp_en : 1; + uint8_t not_used1 : 2; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used0 : 1; + uint8_t inact_en : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_functions_enable_t; + +#define ISM6HG256X_HG_FUNCTIONS_ENABLE 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t hg_shock_dur : 4; + uint8_t int1_hg_wu : 1; + uint8_t int2_hg_wu : 1; + uint8_t hg_wu_change_int_sel : 1; + uint8_t hg_interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hg_interrupts_enable : 1; + uint8_t hg_wu_change_int_sel : 1; + uint8_t int2_hg_wu : 1; + uint8_t int1_hg_wu : 1; + uint8_t hg_shock_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_hg_functions_enable_t; + +#define ISM6HG256X_HG_WAKE_UP_THS 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t hg_wk_ths : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hg_wk_ths : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_hg_wake_up_ths_t; + +#define ISM6HG256X_INACTIVITY_DUR 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_dur : 2; + uint8_t xl_inact_odr : 2; + uint8_t wu_inact_ths_w : 3; + uint8_t sleep_status_on_int : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sleep_status_on_int : 1; + uint8_t wu_inact_ths_w : 3; + uint8_t xl_inact_odr : 2; + uint8_t inact_dur : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_inactivity_dur_t; + +#define ISM6HG256X_INACTIVITY_THS 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_ths : 6; + uint8_t int1_hg_shock_change : 1; + uint8_t int2_hg_shock_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_hg_shock_change : 1; + uint8_t int1_hg_shock_change : 1; + uint8_t inact_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_inactivity_ths_t; + +#define ISM6HG256X_TAP_CFG0 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lir : 1; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; + uint8_t slope_fds : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t low_pass_on_6d : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t low_pass_on_6d : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t slope_fds : 1; + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; + uint8_t lir : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tap_cfg0_t; + +#define ISM6HG256X_TAP_CFG1 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_x : 5; + uint8_t tap_priority : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_priority : 3; + uint8_t tap_ths_x : 5; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tap_cfg1_t; + +#define ISM6HG256X_TAP_CFG2 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_y : 5; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t tap_ths_y : 5; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tap_cfg2_t; + +#define ISM6HG256X_TAP_THS_6D 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_z : 5; + uint8_t sixd_ths : 2; + uint8_t d4d_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t d4d_en : 1; + uint8_t sixd_ths : 2; + uint8_t tap_ths_z : 5; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tap_ths_6d_t; + +#define ISM6HG256X_TAP_DUR 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t dur : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dur : 4; + uint8_t quiet : 2; + uint8_t shock : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tap_dur_t; + +#define ISM6HG256X_WAKE_UP_THS 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t usr_off_on_wu : 1; + uint8_t single_double_tap : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t single_double_tap : 1; + uint8_t usr_off_on_wu : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_wake_up_ths_t; + +#define ISM6HG256X_WAKE_UP_DUR 0x5CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t not_used0 : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t not_used0 : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_wake_up_dur_t; + +#define ISM6HG256X_FREE_FALL 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_free_fall_t; + +#define ISM6HG256X_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_shub : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_6d : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_shub : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_md1_cfg_t; + +#define ISM6HG256X_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_6d : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_md2_cfg_t; + +#define ISM6HG256X_HAODR_CFG 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t haodr_sel : 2; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t haodr_sel : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_haodr_cfg_t; + +#define ISM6HG256X_EMB_FUNC_CFG 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t emb_func_disable : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t emb_func_irq_mask_xl_hg_settl: 1; + uint8_t hg_usr_off_on_emb_func : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hg_usr_off_on_emb_func : 1; + uint8_t emb_func_irq_mask_xl_hg_settl: 1; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_disable : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_cfg_t; + +#define ISM6HG256X_UI_HANDSHAKE_CTRL 0x64U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_shared_req : 1; + uint8_t ui_shared_ack : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t ui_shared_ack : 1; + uint8_t ui_shared_req : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_handshake_ctrl_t; + +#define ISM6HG256X_UI_IF2_SHARED_0 0x65U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_if2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_if2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_if2_shared_0_t; + +#define ISM6HG256X_UI_IF2_SHARED_1 0x66U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_if2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_if2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_if2_shared_1_t; + +#define ISM6HG256X_UI_IF2_SHARED_2 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_if2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_if2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_if2_shared_2_t; + +#define ISM6HG256X_UI_IF2_SHARED_3 0x68U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_if2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_if2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_if2_shared_3_t; + +#define ISM6HG256X_UI_IF2_SHARED_4 0x69U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_if2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_if2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_if2_shared_4_t; + +#define ISM6HG256X_UI_IF2_SHARED_5 0x6AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_if2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_if2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_if2_shared_5_t; + +#define ISM6HG256X_CTRL_EIS 0x6BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g_eis : 3; + uint8_t g_eis_on_g_ois_out_reg : 1; + uint8_t lpf_g_eis_bw : 1; + uint8_t not_used0 : 1; + uint8_t odr_g_eis : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_g_eis : 2; + uint8_t not_used0 : 1; + uint8_t lpf_g_eis_bw : 1; + uint8_t g_eis_on_g_ois_out_reg : 1; + uint8_t fs_g_eis : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ctrl_eis_t; + +#define ISM6HG256X_XL_HG_X_OFS_USR 0x6CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_hg_x_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t xl_hg_x_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_hg_x_ofs_usr_t; + +#define ISM6HG256X_XL_HG_Y_OFS_USR 0x6DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_hg_y_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t xl_hg_y_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_hg_y_ofs_usr_t; + +#define ISM6HG256X_XL_HG_Z_OFS_USR 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_hg_z_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t xl_hg_z_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_hg_z_ofs_usr_t; + +#define ISM6HG256X_UI_INT_OIS 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t st_ois_clampdis : 1; + uint8_t not_used1 : 1; + uint8_t drdy_mask_ois : 1; + uint8_t int2_drdy_ois : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_drdy_ois : 1; + uint8_t drdy_mask_ois : 1; + uint8_t not_used1 : 1; + uint8_t st_ois_clampdis : 1; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_int_ois_t; + +#define ISM6HG256X_UI_CTRL1_OIS 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_spi_read_en : 1; + uint8_t ois_g_en : 1; + uint8_t ois_xl_en : 1; + uint8_t not_used0 : 2; + uint8_t sim_ois : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sim_ois : 1; + uint8_t not_used0 : 2; + uint8_t ois_xl_en : 1; + uint8_t ois_g_en : 1; + uint8_t if2_spi_read_en : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_ctrl1_ois_t; + +#define ISM6HG256X_UI_CTRL2_OIS 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g_ois : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t fs_g_ois : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_ctrl2_ois_t; + +#define ISM6HG256X_UI_CTRL3_OIS 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl_ois : 2; + uint8_t not_used0 : 1; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used0 : 1; + uint8_t fs_xl_ois : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ui_ctrl3_ois_t; + +#define ISM6HG256X_X_OFS_USR 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t x_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_x_ofs_usr_t; + +#define ISM6HG256X_Y_OFS_USR 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t y_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t y_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_y_ofs_usr_t; + +#define ISM6HG256X_Z_OFS_USR 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t z_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_z_ofs_usr_t; + +#define ISM6HG256X_FIFO_DATA_OUT_TAG 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t tag_cnt : 2; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t tag_cnt : 2; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_data_out_tag_t; + +#define ISM6HG256X_FIFO_DATA_OUT_X_L 0x79U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_data_out_x_l_t; + +#define ISM6HG256X_FIFO_DATA_OUT_X_H 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_data_out_x_h_t; + +#define ISM6HG256X_FIFO_DATA_OUT_Y_L 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_data_out_y_l_t; + +#define ISM6HG256X_FIFO_DATA_OUT_Y_H 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_data_out_y_h_t; + +#define ISM6HG256X_FIFO_DATA_OUT_Z_L 0x7DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_data_out_z_l_t; + +#define ISM6HG256X_FIFO_DATA_OUT_Z_H 0x7EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fifo_data_out_z_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page if2 + * @{ + * + */ + +#define ISM6HG256X_IF2_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_who_am_i_t; + +#define ISM6HG256X_IF2_STATUS_REG_OIS 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t gyro_settling : 1; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t gyro_settling : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_status_reg_ois_t; + +#define ISM6HG256X_IF2_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_out_temp_l_t; + +#define ISM6HG256X_IF2_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_out_temp_h_t; + +#define ISM6HG256X_IF2_OUTX_L_G_OIS 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_outx_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_outx_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_outx_l_g_ois_t; + +#define ISM6HG256X_IF2_OUTX_H_G_OIS 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_outx_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_outx_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_outx_h_g_ois_t; + +#define ISM6HG256X_IF2_OUTY_L_G_OIS 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_outy_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_outy_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_outy_l_g_ois_t; + +#define ISM6HG256X_IF2_OUTY_H_G_OIS 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_outy_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_outy_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_outy_h_g_ois_t; + +#define ISM6HG256X_IF2_OUTZ_L_G_OIS 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_outz_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_outz_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_outz_l_g_ois_t; + +#define ISM6HG256X_IF2_OUTZ_H_G_OIS 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_outz_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_outz_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_outz_h_g_ois_t; + +#define ISM6HG256X_IF2_OUTX_L_A_OIS 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_outx_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_outx_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_outx_l_a_ois_t; + +#define ISM6HG256X_IF2_OUTX_H_A_OIS 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_outx_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_outx_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_outx_h_a_ois_t; + +#define ISM6HG256X_IF2_OUTY_L_A_OIS 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_outy_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_outy_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_outy_l_a_ois_t; + +#define ISM6HG256X_IF2_OUTY_H_A_OIS 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_outy_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_outy_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_outy_h_a_ois_t; + +#define ISM6HG256X_IF2_OUTZ_L_A_OIS 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_outz_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_outz_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_outz_l_a_ois_t; + +#define ISM6HG256X_IF2_OUTZ_H_A_OIS 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_outz_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t if2_outz_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_outz_h_a_ois_t; + +#define ISM6HG256X_IF2_HANDSHAKE_CTRL 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_shared_ack : 1; + uint8_t if2_shared_req : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t if2_shared_req : 1; + uint8_t if2_shared_ack : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_handshake_ctrl_t; + +#define ISM6HG256X_IF2_INT_OIS 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl_ois : 2; + uint8_t st_g_ois : 2; + uint8_t st_ois_clampdis : 1; + uint8_t not_used0 : 1; + uint8_t drdy_mask_ois : 1; + uint8_t int2_drdy_ois : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_drdy_ois : 1; + uint8_t drdy_mask_ois : 1; + uint8_t not_used0 : 1; + uint8_t st_ois_clampdis : 1; + uint8_t st_g_ois : 2; + uint8_t st_xl_ois : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_int_ois_t; + +#define ISM6HG256X_IF2_CTRL1_OIS 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t if2_spi_read_en : 1; + uint8_t ois_g_en : 1; + uint8_t ois_xl_en : 1; + uint8_t not_used0 : 2; + uint8_t sim_ois : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sim_ois : 1; + uint8_t not_used0 : 2; + uint8_t ois_xl_en : 1; + uint8_t ois_g_en : 1; + uint8_t if2_spi_read_en : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_ctrl1_ois_t; + +#define ISM6HG256X_IF2_CTRL2_OIS 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g_ois : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t fs_g_ois : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_ctrl2_ois_t; + +#define ISM6HG256X_IF2_CTRL3_OIS 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl_ois : 2; + uint8_t not_used0 : 1; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used0 : 1; + uint8_t fs_xl_ois : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_if2_ctrl3_ois_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page embedded + * @{ + * + */ + +#define ISM6HG256X_PAGE_SEL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_page_sel_t; + +#define ISM6HG256X_EMB_FUNC_EN_A 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used2 : 1; + uint8_t pedo_en : 1; + uint8_t tilt_en : 1; + uint8_t sign_motion_en : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_en : 1; + uint8_t not_used1 : 1; + uint8_t sign_motion_en : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t not_used2 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_en_a_t; + +#define ISM6HG256X_EMB_FUNC_EN_B 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_en : 1; + uint8_t mlc_en : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_en : 1; + uint8_t fifo_compr_en : 1; + uint8_t not_used0 : 2; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_en_b_t; + +#define ISM6HG256X_EMB_FUNC_EXEC_STATUS 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t emb_func_endop : 1; + uint8_t emb_func_exec_ovr : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t emb_func_exec_ovr : 1; + uint8_t emb_func_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_exec_status_t; + +#define ISM6HG256X_PAGE_ADDRESS 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_page_address_t; + +#define ISM6HG256X_PAGE_VALUE 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_value : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_value : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_page_value_t; + +#define ISM6HG256X_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int1_step_detector : 1; + uint8_t int1_tilt : 1; + uint8_t int1_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int1_sig_mot : 1; + uint8_t int1_tilt : 1; + uint8_t int1_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_int1_t; + +#define ISM6HG256X_FSM_INT1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_int1_t; + +#define ISM6HG256X_MLC_INT1 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_mlc1 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc5 : 1; + uint8_t int1_mlc6 : 1; + uint8_t int1_mlc7 : 1; + uint8_t int1_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_mlc8 : 1; + uint8_t int1_mlc7 : 1; + uint8_t int1_mlc6 : 1; + uint8_t int1_mlc5 : 1; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc_int1_t; + +#define ISM6HG256X_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_step_detector : 1; + uint8_t int2_tilt : 1; + uint8_t int2_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int2_sig_mot : 1; + uint8_t int2_tilt : 1; + uint8_t int2_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_int2_t; + +#define ISM6HG256X_FSM_INT2 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_int2_t; + +#define ISM6HG256X_MLC_INT2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_mlc1 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc5 : 1; + uint8_t int2_mlc6 : 1; + uint8_t int2_mlc7 : 1; + uint8_t int2_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_mlc8 : 1; + uint8_t int2_mlc7 : 1; + uint8_t int2_mlc6 : 1; + uint8_t int2_mlc5 : 1; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc_int2_t; + +#define ISM6HG256X_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_status_t; + +#define ISM6HG256X_FSM_STATUS 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_status_t; + +#define ISM6HG256X_MLC_STATUS 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_mlc8 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc_status_t; + +#define ISM6HG256X_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t page_read : 1; + uint8_t page_write : 1; + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_write : 1; + uint8_t page_read : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_page_rw_t; + +#define ISM6HG256X_SFLP_GBIASX_L 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gbiasx_l_t; + +#define ISM6HG256X_SFLP_GBIASX_H 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gbiasx_h_t; + +#define ISM6HG256X_SFLP_GBIASY_L 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gbiasy_l_t; + +#define ISM6HG256X_SFLP_GBIASY_H 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gbiasy_h_t; + +#define ISM6HG256X_SFLP_GBIASZ_L 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gbiasz_l_t; + +#define ISM6HG256X_SFLP_GBIASZ_H 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gbiasz_h_t; + +#define ISM6HG256X_SFLP_GRAVX_L 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gravx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gravx : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gravx_l_t; + +#define ISM6HG256X_SFLP_GRAVX_H 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gravx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gravx : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gravx_h_t; + +#define ISM6HG256X_SFLP_GRAVY_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gravy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gravy : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gravy_l_t; + +#define ISM6HG256X_SFLP_GRAVY_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gravy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gravy : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gravy_h_t; + +#define ISM6HG256X_SFLP_GRAVZ_L 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gravz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gravz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gravz_l_t; + +#define ISM6HG256X_SFLP_GRAVZ_H 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gravz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gravz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gravz_h_t; + +#define ISM6HG256X_SFLP_QUATW_L 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_quatw : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_quatw : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_quatw_l_t; + +#define ISM6HG256X_SFLP_QUATW_H 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_quatw : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_quatw : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_quatw_h_t; + +#define ISM6HG256X_SFLP_QUATX_L 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_quatx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_quatx : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_quatx_l_t; + +#define ISM6HG256X_SFLP_QUATX_H 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_quatx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_quatx : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_quatx_h_t; + +#define ISM6HG256X_SFLP_QUATY_L 0x2EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_quaty : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_quaty : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_quaty_l_t; + +#define ISM6HG256X_SFLP_QUATY_H 0x2FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_quaty : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_quaty : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_quaty_h_t; + +#define ISM6HG256X_SFLP_QUATZ_L 0x30U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_quatz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_quatz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_quatz_l_t; + +#define ISM6HG256X_SFLP_QUATZ_H 0x31U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_quatz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_quatz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_quatz_h_t; + +#define ISM6HG256X_SFLP_GBIASX_INIT_L 0x32U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gbiasx_init : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gbiasx_init : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gbiasx_init_l_t; + +#define ISM6HG256X_SFLP_GBIASX_INIT_H 0x33U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gbiasx_init : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gbiasx_init : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gbiasx_init_h_t; + +#define ISM6HG256X_SFLP_GBIASY_INIT_L 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gbiasy_init : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gbiasy_init : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gbiasy_init_l_t; + +#define ISM6HG256X_SFLP_GBIASY_INIT_H 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gbiasy_init : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gbiasy_init : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gbiasy_init_h_t; + +#define ISM6HG256X_SFLP_GBIASZ_INIT_L 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gbiasz_init : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gbiasz_init : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gbiasz_init_l_t; + +#define ISM6HG256X_SFLP_GBIASZ_INIT_H 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sflp_gbiasz_init : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sflp_gbiasz_init : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_gbiasz_init_h_t; + +#define ISM6HG256X_EMB_FUNC_FIFO_EN_A 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t mlc_fifo_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_fifo_en_a_t; + +#define ISM6HG256X_EMB_FUNC_FIFO_EN_B 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t fsm_fifo_en : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t fsm_fifo_en : 1; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_fifo_en_b_t; + +#define ISM6HG256X_FSM_ENABLE 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_enable_t; + +#define ISM6HG256X_FSM_LONG_COUNTER_L 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_long_counter_l_t; + +#define ISM6HG256X_FSM_LONG_COUNTER_H 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_long_counter_h_t; + +#define ISM6HG256X_INT_ACK_MASK 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t iack_mask : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t iack_mask : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_int_ack_mask_t; + +#define ISM6HG256X_FSM_OUTS1 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_n_v : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_z : 1; + uint8_t fsm1_p_z : 1; + uint8_t fsm1_n_y : 1; + uint8_t fsm1_p_y : 1; + uint8_t fsm1_n_x : 1; + uint8_t fsm1_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm1_p_x : 1; + uint8_t fsm1_n_x : 1; + uint8_t fsm1_p_y : 1; + uint8_t fsm1_n_y : 1; + uint8_t fsm1_p_z : 1; + uint8_t fsm1_n_z : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_outs1_t; + +#define ISM6HG256X_FSM_OUTS2 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm2_n_v : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_z : 1; + uint8_t fsm2_p_z : 1; + uint8_t fsm2_n_y : 1; + uint8_t fsm2_p_y : 1; + uint8_t fsm2_n_x : 1; + uint8_t fsm2_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm2_p_x : 1; + uint8_t fsm2_n_x : 1; + uint8_t fsm2_p_y : 1; + uint8_t fsm2_n_y : 1; + uint8_t fsm2_p_z : 1; + uint8_t fsm2_n_z : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_outs2_t; + +#define ISM6HG256X_FSM_OUTS3 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm3_n_v : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_z : 1; + uint8_t fsm3_p_z : 1; + uint8_t fsm3_n_y : 1; + uint8_t fsm3_p_y : 1; + uint8_t fsm3_n_x : 1; + uint8_t fsm3_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm3_p_x : 1; + uint8_t fsm3_n_x : 1; + uint8_t fsm3_p_y : 1; + uint8_t fsm3_n_y : 1; + uint8_t fsm3_p_z : 1; + uint8_t fsm3_n_z : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_outs3_t; + +#define ISM6HG256X_FSM_OUTS4 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm4_n_v : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_z : 1; + uint8_t fsm4_p_z : 1; + uint8_t fsm4_n_y : 1; + uint8_t fsm4_p_y : 1; + uint8_t fsm4_n_x : 1; + uint8_t fsm4_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm4_p_x : 1; + uint8_t fsm4_n_x : 1; + uint8_t fsm4_p_y : 1; + uint8_t fsm4_n_y : 1; + uint8_t fsm4_p_z : 1; + uint8_t fsm4_n_z : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_outs4_t; + +#define ISM6HG256X_FSM_OUTS5 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm5_n_v : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_z : 1; + uint8_t fsm5_p_z : 1; + uint8_t fsm5_n_y : 1; + uint8_t fsm5_p_y : 1; + uint8_t fsm5_n_x : 1; + uint8_t fsm5_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm5_p_x : 1; + uint8_t fsm5_n_x : 1; + uint8_t fsm5_p_y : 1; + uint8_t fsm5_n_y : 1; + uint8_t fsm5_p_z : 1; + uint8_t fsm5_n_z : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_outs5_t; + +#define ISM6HG256X_FSM_OUTS6 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm6_n_v : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_z : 1; + uint8_t fsm6_p_z : 1; + uint8_t fsm6_n_y : 1; + uint8_t fsm6_p_y : 1; + uint8_t fsm6_n_x : 1; + uint8_t fsm6_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm6_p_x : 1; + uint8_t fsm6_n_x : 1; + uint8_t fsm6_p_y : 1; + uint8_t fsm6_n_y : 1; + uint8_t fsm6_p_z : 1; + uint8_t fsm6_n_z : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_outs6_t; + +#define ISM6HG256X_FSM_OUTS7 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm7_n_v : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_z : 1; + uint8_t fsm7_p_z : 1; + uint8_t fsm7_n_y : 1; + uint8_t fsm7_p_y : 1; + uint8_t fsm7_n_x : 1; + uint8_t fsm7_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm7_p_x : 1; + uint8_t fsm7_n_x : 1; + uint8_t fsm7_p_y : 1; + uint8_t fsm7_n_y : 1; + uint8_t fsm7_p_z : 1; + uint8_t fsm7_n_z : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_outs7_t; + +#define ISM6HG256X_FSM_OUTS8 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm8_n_v : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_z : 1; + uint8_t fsm8_p_z : 1; + uint8_t fsm8_n_y : 1; + uint8_t fsm8_p_y : 1; + uint8_t fsm8_n_x : 1; + uint8_t fsm8_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_p_x : 1; + uint8_t fsm8_n_x : 1; + uint8_t fsm8_p_y : 1; + uint8_t fsm8_n_y : 1; + uint8_t fsm8_p_z : 1; + uint8_t fsm8_n_z : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_outs8_t; + +#define ISM6HG256X_SFLP_ODR 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t sflp_game_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sflp_game_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sflp_odr_t; + +#define ISM6HG256X_FSM_ODR 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t fsm_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t fsm_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_odr_t; + +#define ISM6HG256X_MLC_ODR 0x60U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t mlc_odr : 3; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t mlc_odr : 3; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc_odr_t; + +#define ISM6HG256X_STEP_COUNTER_L 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_step_counter_l_t; + +#define ISM6HG256X_STEP_COUNTER_H 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_step_counter_h_t; + +#define ISM6HG256X_EMB_FUNC_SRC 0x64U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t stepcounter_bit_set : 1; + uint8_t step_overflow : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_detected : 1; + uint8_t not_used1 : 1; + uint8_t pedo_rst_step : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pedo_rst_step : 1; + uint8_t not_used1 : 1; + uint8_t step_detected : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_overflow : 1; + uint8_t stepcounter_bit_set : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_src_t; + +#define ISM6HG256X_EMB_FUNC_INIT_A 0x66U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used2 : 1; + uint8_t step_det_init : 1; + uint8_t tilt_init : 1; + uint8_t sig_mot_init : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_init : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_init : 1; + uint8_t not_used1 : 1; + uint8_t sig_mot_init : 1; + uint8_t tilt_init : 1; + uint8_t step_det_init : 1; + uint8_t not_used2 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_init_a_t; + +#define ISM6HG256X_EMB_FUNC_INIT_B 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used0 : 1; + uint8_t pt_init : 1; + uint8_t fifo_compr_init : 1; + uint8_t mlc_init : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_init : 1; + uint8_t fifo_compr_init : 1; + uint8_t pt_init : 1; + uint8_t not_used0 : 1; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_init_b_t; + +#define ISM6HG256X_EMB_FUNC_SENSOR_CONV_EN 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_hg_conv_en : 1; + uint8_t gyro_conv_en : 1; + uint8_t temp_conv_en : 1; + uint8_t ext_sensor_conv_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t ext_sensor_conv_en : 1; + uint8_t temp_conv_en : 1; + uint8_t gyro_conv_en : 1; + uint8_t xl_hg_conv_en : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_emb_func_sensor_conv_en_t; + +#define ISM6HG256X_MLC1_SRC 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc1_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc1_src : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc1_src_t; + +#define ISM6HG256X_MLC2_SRC 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc2_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc2_src : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc2_src_t; + +#define ISM6HG256X_MLC3_SRC 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc3_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc3_src : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc3_src_t; + +#define ISM6HG256X_MLC4_SRC 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc4_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc4_src : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc4_src_t; + +#define ISM6HG256X_MLC5_SRC 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc5_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc5_src : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc5_src_t; + +#define ISM6HG256X_MLC6_SRC 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc6_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc6_src : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc6_src_t; + +#define ISM6HG256X_MLC7_SRC 0x76U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc7_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc7_src : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc7_src_t; + +#define ISM6HG256X_MLC8_SRC 0x77U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc8_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc8_src : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc8_src_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg0_emb_adv + * @{ + * + */ +#define ISM6HG256X_EMB_ADV_PG_0 0x000U + +#define ISM6HG256X_FSM_EXT_SENSITIVITY_L 0xBAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_sensitivity_l_t; + +#define ISM6HG256X_FSM_EXT_SENSITIVITY_H 0xBBU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_sensitivity_h_t; + +#define ISM6HG256X_FSM_EXT_OFFX_L 0xC0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offx : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_offx_l_t; + +#define ISM6HG256X_FSM_EXT_OFFX_H 0xC1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offx : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_offx_h_t; + +#define ISM6HG256X_FSM_EXT_OFFY_L 0xC2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offy : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_offy_l_t; + +#define ISM6HG256X_FSM_EXT_OFFY_H 0xC3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offy : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_offy_h_t; + +#define ISM6HG256X_FSM_EXT_OFFZ_L 0xC4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_offz_l_t; + +#define ISM6HG256X_FSM_EXT_OFFZ_H 0xC5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_offz_h_t; + +#define ISM6HG256X_FSM_EXT_MATRIX_XX_L 0xC6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_matrix_xx_l_t; + +#define ISM6HG256X_FSM_EXT_MATRIX_XX_H 0xC7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_matrix_xx_h_t; + +#define ISM6HG256X_FSM_EXT_MATRIX_XY_L 0xC8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_matrix_xy_l_t; + +#define ISM6HG256X_FSM_EXT_MATRIX_XY_H 0xC9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_matrix_xy_h_t; + +#define ISM6HG256X_FSM_EXT_MATRIX_XZ_L 0xCAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_matrix_xz_l_t; + +#define ISM6HG256X_FSM_EXT_MATRIX_XZ_H 0xCBU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_matrix_xz_h_t; + +#define ISM6HG256X_FSM_EXT_MATRIX_YY_L 0xCCU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_matrix_yy_l_t; + +#define ISM6HG256X_FSM_EXT_MATRIX_YY_H 0xCDU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_matrix_yy_h_t; + +#define ISM6HG256X_FSM_EXT_MATRIX_YZ_L 0xCEU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_matrix_yz_l_t; + +#define ISM6HG256X_FSM_EXT_MATRIX_YZ_H 0xCFU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_matrix_yz_h_t; + +#define ISM6HG256X_FSM_EXT_MATRIX_ZZ_L 0xD0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_matrix_zz_l_t; + +#define ISM6HG256X_FSM_EXT_MATRIX_ZZ_H 0xD1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_ext_matrix_zz_h_t; + +#define ISM6HG256X_EXT_CFG_A 0xD4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_z_axis : 3; + uint8_t not_used0 : 1; + uint8_t ext_y_axis : 3; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t ext_y_axis : 3; + uint8_t not_used0 : 1; + uint8_t ext_z_axis : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ext_cfg_a_t; + +#define ISM6HG256X_EXT_CFG_B 0xD5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_x_axis : 3; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t ext_x_axis : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ext_cfg_b_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg1_emb_adv + * @{ + * + */ +#define ISM6HG256X_EMB_ADV_PG_1 0x100U + +#define ISM6HG256X_XL_HG_SENSITIVITY_L 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_hg_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t xl_hg_s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_xl_hg_sensitivity_l_t; + +#define ISM6HG256X_XL_HG_SENSITIVITY_H 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_hg_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t xl_hg_s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_xl_hg_sensitivity_h_t; + +#define ISM6HG256X_FSM_LC_TIMEOUT_L 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_lc_timeout_l_t; + +#define ISM6HG256X_FSM_LC_TIMEOUT_H 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_lc_timeout_h_t; + +#define ISM6HG256X_FSM_PROGRAMS 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_n_prog : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_n_prog : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_programs_t; + +#define ISM6HG256X_FSM_START_ADD_L 0x7EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_start_add_l_t; + +#define ISM6HG256X_FSM_START_ADD_H 0x7FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_fsm_start_add_h_t; + +#define ISM6HG256X_PEDO_CMD_REG 0x83U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fp_rejection_en : 1; + uint8_t carry_count_en : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t carry_count_en : 1; + uint8_t fp_rejection_en : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_pedo_cmd_reg_t; + +#define ISM6HG256X_PEDO_DEB_STEPS_CONF 0x84U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deb_step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t deb_step : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_pedo_deb_steps_conf_t; + +#define ISM6HG256X_PEDO_SC_DELTAT_L 0xD0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_pedo_sc_deltat_l_t; + +#define ISM6HG256X_PEDO_SC_DELTAT_H 0xD1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_pedo_sc_deltat_h_t; + +#define ISM6HG256X_MLC_EXT_SENSITIVITY_L 0xE8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc_ext_sensitivity_l_t; + +#define ISM6HG256X_MLC_EXT_SENSITIVITY_H 0xE9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_mlc_ext_sensitivity_h_t; + +/** @defgroup bitfields page pg2_emb_adv + * @{ + * + */ +#define ISM6HG256X_EMB_ADV_PG_2 0x200U + +#define ISM6HG256X_EXT_FORMAT 0x00 +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t ext_format_sel : 1; + uint8_t not_used1 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 6; + uint8_t ext_format_sel : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ext_format_t; + +#define ISM6HG256X_EXT_3BYTE_SENSITIVITY_L 0x02U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ext_3byte_sensitivity_l_t; + +#define ISM6HG256X_EXT_3BYTE_SENSITIVITY_H 0x03U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ext_3byte_sensitivity_h_t; + +#define ISM6HG256X_EXT_3BYTE_OFFSET_XL 0x06U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_off : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_off : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ext_3byte_offset_xl_t; + +#define ISM6HG256X_EXT_3BYTE_OFFSET_L 0x07U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_off : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_off : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ext_3byte_offset_l_t; + +#define ISM6HG256X_EXT_3BYTE_OFFSET_H 0x08U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_off : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_off : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_ext_3byte_offset_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page sensor_hub + * @{ + * + */ + +#define ISM6HG256X_SENSOR_HUB_1 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub1 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_1_t; + +#define ISM6HG256X_SENSOR_HUB_2 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub2 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_2_t; + +#define ISM6HG256X_SENSOR_HUB_3 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub3 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_3_t; + +#define ISM6HG256X_SENSOR_HUB_4 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub4 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_4_t; + +#define ISM6HG256X_SENSOR_HUB_5 0x6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub5 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub5 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_5_t; + +#define ISM6HG256X_SENSOR_HUB_6 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub6 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub6 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_6_t; + +#define ISM6HG256X_SENSOR_HUB_7 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub7 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub7 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_7_t; + +#define ISM6HG256X_SENSOR_HUB_8 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub8 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub8 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_8_t; + +#define ISM6HG256X_SENSOR_HUB_9 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub9 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub9 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_9_t; + +#define ISM6HG256X_SENSOR_HUB_10 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub10 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub10 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_10_t; + +#define ISM6HG256X_SENSOR_HUB_11 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub11 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub11 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_11_t; + +#define ISM6HG256X_SENSOR_HUB_12 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub12 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub12 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_12_t; + +#define ISM6HG256X_SENSOR_HUB_13 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub13 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub13 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_13_t; + +#define ISM6HG256X_SENSOR_HUB_14 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub14 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub14 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_14_t; + +#define ISM6HG256X_SENSOR_HUB_15 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub15 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub15 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_15_t; + +#define ISM6HG256X_SENSOR_HUB_16 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub16 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub16 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_16_t; + +#define ISM6HG256X_SENSOR_HUB_17 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub17 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub17 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_17_t; + +#define ISM6HG256X_SENSOR_HUB_18 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub18 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub18 : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_sensor_hub_18_t; + +#define ISM6HG256X_CONTROLLER_CONFIG 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t aux_sens_on : 2; + uint8_t controller_on : 1; + uint8_t not_used0 : 1; + uint8_t pass_through_mode : 1; + uint8_t start_config : 1; + uint8_t write_once : 1; + uint8_t rst_controller_regs : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t rst_controller_regs : 1; + uint8_t write_once : 1; + uint8_t start_config : 1; + uint8_t pass_through_mode : 1; + uint8_t not_used0 : 1; + uint8_t controller_on : 1; + uint8_t aux_sens_on : 2; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_controller_config_t; + +#define ISM6HG256X_TGT0_ADD 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t rw_0 : 1; + uint8_t target0_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t target0_add : 7; + uint8_t rw_0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tgt0_add_t; + +#define ISM6HG256X_TGT0_SUBADD 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t target0_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t target0_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tgt0_subadd_t; + +#define ISM6HG256X_TGT0_CONFIG 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t target0_numop : 3; + uint8_t batch_ext_sens_0_en : 1; + uint8_t not_used0 : 1; + uint8_t shub_odr : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t shub_odr : 3; + uint8_t not_used0 : 1; + uint8_t batch_ext_sens_0_en : 1; + uint8_t target0_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tgt0_config_t; + +#define ISM6HG256X_TGT1_ADD 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_1 : 1; + uint8_t target1_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t target1_add : 7; + uint8_t r_1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tgt1_add_t; + +#define ISM6HG256X_TGT1_SUBADD 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t target1_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t target1_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tgt1_subadd_t; + +#define ISM6HG256X_TGT1_CONFIG 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t target1_numop : 3; + uint8_t batch_ext_sens_1_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t batch_ext_sens_1_en : 1; + uint8_t target1_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tgt1_config_t; + +#define ISM6HG256X_TGT2_ADD 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_2 : 1; + uint8_t target2_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t target2_add : 7; + uint8_t r_2 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tgt2_add_t; + +#define ISM6HG256X_TGT2_SUBADD 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t target2_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t target2_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tgt2_subadd_t; + +#define ISM6HG256X_TGT2_CONFIG 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t target2_numop : 3; + uint8_t batch_ext_sens_2_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t batch_ext_sens_2_en : 1; + uint8_t target2_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tgt2_config_t; + +#define ISM6HG256X_TGT3_ADD 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_3 : 1; + uint8_t target3_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t target3_add : 7; + uint8_t r_3 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tgt3_add_t; + +#define ISM6HG256X_TGT3_SUBADD 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t target3_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t target3_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tgt3_subadd_t; + +#define ISM6HG256X_TGT3_CONFIG 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t target3_numop : 3; + uint8_t batch_ext_sens_3_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t batch_ext_sens_3_en : 1; + uint8_t target3_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_tgt3_config_t; + +#define ISM6HG256X_DATAWRITE_TGT0 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t target0_dataw : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t target0_dataw : 8; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_datawrite_tgt0_t; + +#define ISM6HG256X_STATUS_CONTROLLER 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used0 : 2; + uint8_t target0_nack : 1; + uint8_t target1_nack : 1; + uint8_t target2_nack : 1; + uint8_t target3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t target3_nack : 1; + uint8_t target2_nack : 1; + uint8_t target1_nack : 1; + uint8_t target0_nack : 1; + uint8_t not_used0 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} ism6hg256x_status_controller_t; + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSO_Register_Union + * @brief This union group all the registers having a bit-field + * description. + * This union is useful but it's not needed by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + /* master page registers */ + ism6hg256x_func_cfg_access_t func_cfg_access; + ism6hg256x_pin_ctrl_t pin_ctrl; + ism6hg256x_if_cfg_t if_cfg; + ism6hg256x_odr_trig_cfg_t odr_trig_cfg; + ism6hg256x_fifo_ctrl1_t fifo_ctrl1; + ism6hg256x_fifo_ctrl2_t fifo_ctrl2; + ism6hg256x_fifo_ctrl3_t fifo_ctrl3; + ism6hg256x_fifo_ctrl4_t fifo_ctrl4; + ism6hg256x_counter_bdr_reg1_t counter_bdr_reg1; + ism6hg256x_counter_bdr_reg2_t counter_bdr_reg2; + ism6hg256x_int1_ctrl_t int1_ctrl; + ism6hg256x_int2_ctrl_t int2_ctrl; + ism6hg256x_who_am_i_t who_am_i; + ism6hg256x_ctrl1_t ctrl1; + ism6hg256x_ctrl2_t ctrl2; + ism6hg256x_ctrl3_t ctrl3; + ism6hg256x_ctrl4_t ctrl4; + ism6hg256x_ctrl5_t ctrl5; + ism6hg256x_ctrl6_t ctrl6; + ism6hg256x_ctrl7_t ctrl7; + ism6hg256x_ctrl8_t ctrl8; + ism6hg256x_ctrl9_t ctrl9; + ism6hg256x_ctrl10_t ctrl10; + ism6hg256x_ctrl_status_t ctrl_status; + ism6hg256x_fifo_status1_t fifo_status1; + ism6hg256x_fifo_status2_t fifo_status2; + ism6hg256x_all_int_src_t all_int_src; + ism6hg256x_status_reg_t status_reg; + ism6hg256x_out_temp_l_t out_temp_l; + ism6hg256x_out_temp_h_t out_temp_h; + ism6hg256x_outx_l_g_t outx_l_g; + ism6hg256x_outx_h_g_t outx_h_g; + ism6hg256x_outy_l_g_t outy_l_g; + ism6hg256x_outy_h_g_t outy_h_g; + ism6hg256x_outz_l_g_t outz_l_g; + ism6hg256x_outz_h_g_t outz_h_g; + ism6hg256x_outx_l_a_t outx_l_a; + ism6hg256x_outx_h_a_t outx_h_a; + ism6hg256x_outy_l_a_t outy_l_a; + ism6hg256x_outy_h_a_t outy_h_a; + ism6hg256x_outz_l_a_t outz_l_a; + ism6hg256x_outz_h_a_t outz_h_a; + ism6hg256x_ui_outx_l_g_ois_eis_t ui_outx_l_g_ois_eis; + ism6hg256x_ui_outx_h_g_ois_eis_t ui_outx_h_g_ois_eis; + ism6hg256x_ui_outy_l_g_ois_eis_t ui_outy_l_g_ois_eis; + ism6hg256x_ui_outy_h_g_ois_eis_t ui_outy_h_g_ois_eis; + ism6hg256x_ui_outz_l_g_ois_eis_t ui_outz_l_g_ois_eis; + ism6hg256x_ui_outz_h_g_ois_eis_t ui_outz_h_g_ois_eis; + ism6hg256x_ui_outx_l_a_ois_hg_t ui_outx_l_a_ois_hg; + ism6hg256x_ui_outx_h_a_ois_hg_t ui_outx_h_a_ois_hg; + ism6hg256x_ui_outy_l_a_ois_hg_t ui_outy_l_a_ois_hg; + ism6hg256x_ui_outy_h_a_ois_hg_t ui_outy_h_a_ois_hg; + ism6hg256x_ui_outz_l_a_ois_hg_t ui_outz_l_a_ois_hg; + ism6hg256x_ui_outz_h_a_ois_hg_t ui_outz_h_a_ois_hg; + ism6hg256x_timestamp0_t timestamp0; + ism6hg256x_timestamp1_t timestamp1; + ism6hg256x_timestamp2_t timestamp2; + ism6hg256x_timestamp3_t timestamp3; + ism6hg256x_ui_status_reg_ois_t ui_status_reg_ois; + ism6hg256x_wake_up_src_t wake_up_src; + ism6hg256x_tap_src_t tap_src; + ism6hg256x_d6d_src_t d6d_src; + ism6hg256x_status_controller_mainpage_t status_controller_mainpage; + ism6hg256x_emb_func_status_mainpage_t emb_func_status_mainpage; + ism6hg256x_fsm_status_mainpage_t fsm_status_mainpage; + ism6hg256x_mlc_status_mainpage_t mlc_status_mainpage; + ism6hg256x_hg_wake_up_src_t hg_wake_up_src; + ism6hg256x_ctrl2_xl_hg_t ctrl2_xl_hg; + ism6hg256x_ctrl1_xl_hg_t ctrl1_xl_hg; + ism6hg256x_internal_freq_t internal_freq; + ism6hg256x_functions_enable_t functions_enable; + ism6hg256x_inactivity_dur_t inactivity_dur; + ism6hg256x_inactivity_ths_t inactivity_ths; + ism6hg256x_tap_cfg0_t tap_cfg0; + ism6hg256x_tap_cfg1_t tap_cfg1; + ism6hg256x_tap_cfg2_t tap_cfg2; + ism6hg256x_tap_ths_6d_t tap_ths_6d; + ism6hg256x_tap_dur_t tap_dur; + ism6hg256x_wake_up_ths_t wake_up_ths; + ism6hg256x_wake_up_dur_t wake_up_dur; + ism6hg256x_free_fall_t free_fall; + ism6hg256x_md1_cfg_t md1_cfg; + ism6hg256x_md2_cfg_t md2_cfg; + ism6hg256x_emb_func_cfg_t emb_func_cfg; + ism6hg256x_ui_handshake_ctrl_t ui_handshake_ctrl; + ism6hg256x_ui_if2_shared_0_t ui_if2_shared_0; + ism6hg256x_ui_if2_shared_1_t ui_if2_shared_1; + ism6hg256x_ui_if2_shared_2_t ui_if2_shared_2; + ism6hg256x_ui_if2_shared_3_t ui_if2_shared_3; + ism6hg256x_ui_if2_shared_4_t ui_if2_shared_4; + ism6hg256x_ui_if2_shared_5_t ui_if2_shared_5; + ism6hg256x_ctrl_eis_t ctrl_eis; + ism6hg256x_hg_x_ofs_usr_t hg_x_ofs_usr; + ism6hg256x_hg_y_ofs_usr_t hg_y_ofs_usr; + ism6hg256x_hg_z_ofs_usr_t hg_z_ofs_usr; + ism6hg256x_ui_int_ois_t ui_int_ois; + ism6hg256x_ui_ctrl1_ois_t ui_ctrl1_ois; + ism6hg256x_ui_ctrl2_ois_t ui_ctrl2_ois; + ism6hg256x_ui_ctrl3_ois_t ui_ctrl3_ois; + ism6hg256x_x_ofs_usr_t x_ofs_usr; + ism6hg256x_y_ofs_usr_t y_ofs_usr; + ism6hg256x_z_ofs_usr_t z_ofs_usr; + ism6hg256x_fifo_data_out_tag_t fifo_data_out_tag; + ism6hg256x_fifo_data_out_x_l_t fifo_data_out_x_l; + ism6hg256x_fifo_data_out_x_h_t fifo_data_out_x_h; + ism6hg256x_fifo_data_out_y_l_t fifo_data_out_y_l; + ism6hg256x_fifo_data_out_y_h_t fifo_data_out_y_h; + ism6hg256x_fifo_data_out_z_l_t fifo_data_out_z_l; + ism6hg256x_fifo_data_out_z_h_t fifo_data_out_z_h; + /* IF2 registers */ + ism6hg256x_if2_who_am_i_t if2_who_am_i; + ism6hg256x_if2_status_reg_ois_t if2_status_reg_ois; + ism6hg256x_if2_out_temp_l_t if2_out_temp_l; + ism6hg256x_if2_out_temp_h_t if2_out_temp_h; + ism6hg256x_if2_outx_l_g_ois_t if2_outx_l_g_ois; + ism6hg256x_if2_outx_h_g_ois_t if2_outx_h_g_ois; + ism6hg256x_if2_outy_l_g_ois_t if2_outy_l_g_ois; + ism6hg256x_if2_outy_h_g_ois_t if2_outy_h_g_ois; + ism6hg256x_if2_outz_l_g_ois_t if2_outz_l_g_ois; + ism6hg256x_if2_outz_h_g_ois_t if2_outz_h_g_ois; + ism6hg256x_if2_outx_l_a_ois_t if2_outx_l_a_ois; + ism6hg256x_if2_outx_h_a_ois_t if2_outx_h_a_ois; + ism6hg256x_if2_outy_l_a_ois_t if2_outy_l_a_ois; + ism6hg256x_if2_outy_h_a_ois_t if2_outy_h_a_ois; + ism6hg256x_if2_outz_l_a_ois_t if2_outz_l_a_ois; + ism6hg256x_if2_outz_h_a_ois_t if2_outz_h_a_ois; + ism6hg256x_if2_handshake_ctrl_t if2_handshake_ctrl; + ism6hg256x_if2_int_ois_t if2_int_ois; + ism6hg256x_if2_ctrl1_ois_t if2_ctrl1_ois; + ism6hg256x_if2_ctrl2_ois_t if2_ctrl2_ois; + ism6hg256x_if2_ctrl3_ois_t if2_ctrl3_ois; + /* Embedded functions registers */ + ism6hg256x_page_sel_t page_sel; + ism6hg256x_emb_func_en_a_t emb_func_en_a; + ism6hg256x_emb_func_en_b_t emb_func_en_b; + ism6hg256x_emb_func_exec_status_t emb_func_exec_status; + ism6hg256x_page_address_t page_address; + ism6hg256x_page_value_t page_value; + ism6hg256x_emb_func_int1_t emb_func_int1; + ism6hg256x_fsm_int1_t fsm_int1; + ism6hg256x_mlc_int1_t mlc_int1; + ism6hg256x_emb_func_int2_t emb_func_int2; + ism6hg256x_fsm_int2_t fsm_int2; + ism6hg256x_mlc_int2_t mlc_int2; + ism6hg256x_emb_func_status_t emb_func_status; + ism6hg256x_fsm_status_t fsm_status; + ism6hg256x_mlc_status_t mlc_status; + ism6hg256x_page_rw_t page_rw; + ism6hg256x_sflp_gbiasx_l_t sflp_gbiasx_l; + ism6hg256x_sflp_gbiasx_h_t sflp_gbiasx_h; + ism6hg256x_sflp_gbiasy_l_t sflp_gbiasy_l; + ism6hg256x_sflp_gbiasy_h_t sflp_gbiasy_h; + ism6hg256x_sflp_gbiasz_l_t sflp_gbiasz_l; + ism6hg256x_sflp_gbiasz_h_t sflp_gbiasz_h; + ism6hg256x_sflp_gravx_l_t sflp_gravx_l; + ism6hg256x_sflp_gravx_h_t sflp_gravx_h; + ism6hg256x_sflp_gravy_l_t sflp_gravy_l; + ism6hg256x_sflp_gravy_h_t sflp_gravy_h; + ism6hg256x_sflp_gravz_l_t sflp_gravz_l; + ism6hg256x_sflp_gravz_h_t sflp_gravz_h; + ism6hg256x_sflp_quatw_l_t sflp_quatw_l; + ism6hg256x_sflp_quatw_h_t sflp_quatw_h; + ism6hg256x_sflp_quatx_l_t sflp_quatx_l; + ism6hg256x_sflp_quatx_h_t sflp_quatx_h; + ism6hg256x_sflp_quaty_l_t sflp_quaty_l; + ism6hg256x_sflp_quaty_h_t sflp_quaty_h; + ism6hg256x_sflp_quatz_l_t sflp_quatz_l; + ism6hg256x_sflp_quatz_h_t sflp_quatz_h; + ism6hg256x_sflp_gbiasx_init_l_t sflp_gbiasx_init_l; + ism6hg256x_sflp_gbiasx_init_h_t sflp_gbiasx_init_h; + ism6hg256x_sflp_gbiasy_init_l_t sflp_gbiasy_init_l; + ism6hg256x_sflp_gbiasy_init_h_t sflp_gbiasy_init_h; + ism6hg256x_sflp_gbiasz_init_l_t sflp_gbiasz_init_l; + ism6hg256x_sflp_gbiasz_init_h_t sflp_gbiasz_init_h; + ism6hg256x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + ism6hg256x_emb_func_fifo_en_b_t emb_func_fifo_en_b; + ism6hg256x_fsm_enable_t fsm_enable; + ism6hg256x_fsm_long_counter_l_t fsm_long_counter_l; + ism6hg256x_fsm_long_counter_h_t fsm_long_counter_h; + ism6hg256x_int_ack_mask_t int_ack_mask; + ism6hg256x_fsm_outs1_t fsm_outs1; + ism6hg256x_fsm_outs2_t fsm_outs2; + ism6hg256x_fsm_outs3_t fsm_outs3; + ism6hg256x_fsm_outs4_t fsm_outs4; + ism6hg256x_fsm_outs5_t fsm_outs5; + ism6hg256x_fsm_outs6_t fsm_outs6; + ism6hg256x_fsm_outs7_t fsm_outs7; + ism6hg256x_fsm_outs8_t fsm_outs8; + ism6hg256x_sflp_odr_t sflp_odr; + ism6hg256x_fsm_odr_t fsm_odr; + ism6hg256x_mlc_odr_t mlc_odr; + ism6hg256x_step_counter_l_t step_counter_l; + ism6hg256x_step_counter_h_t step_counter_h; + ism6hg256x_emb_func_src_t emb_func_src; + ism6hg256x_emb_func_init_a_t emb_func_init_a; + ism6hg256x_emb_func_init_b_t emb_func_init_b; + ism6hg256x_emb_func_sensor_conv_en_t emb_func_sensor_conv_en; + ism6hg256x_mlc1_src_t mlc1_src; + ism6hg256x_mlc2_src_t mlc2_src; + ism6hg256x_mlc3_src_t mlc3_src; + ism6hg256x_mlc4_src_t mlc4_src; + ism6hg256x_mlc5_src_t mlc5_src; + ism6hg256x_mlc6_src_t mlc6_src; + ism6hg256x_mlc7_src_t mlc7_src; + /* Embedded functions extended page 0 registers */ + ism6hg256x_fsm_ext_sensitivity_l_t fsm_ext_sensitivity_l; + ism6hg256x_fsm_ext_sensitivity_h_t fsm_ext_sensitivity_h; + ism6hg256x_fsm_ext_offx_l_t fsm_ext_offx_l; + ism6hg256x_fsm_ext_offx_h_t fsm_ext_offx_h; + ism6hg256x_fsm_ext_offy_l_t fsm_ext_offy_l; + ism6hg256x_fsm_ext_offy_h_t fsm_ext_offy_h; + ism6hg256x_fsm_ext_offz_l_t fsm_ext_offz_l; + ism6hg256x_fsm_ext_offz_h_t fsm_ext_offz_h; + ism6hg256x_fsm_ext_matrix_xx_l_t fsm_ext_matrix_xx_l; + ism6hg256x_fsm_ext_matrix_xx_h_t fsm_ext_matrix_xx_h; + ism6hg256x_fsm_ext_matrix_xy_l_t fsm_ext_matrix_xy_l; + ism6hg256x_fsm_ext_matrix_xy_h_t fsm_ext_matrix_xy_h; + ism6hg256x_fsm_ext_matrix_xz_l_t fsm_ext_matrix_xz_l; + ism6hg256x_fsm_ext_matrix_xz_h_t fsm_ext_matrix_xz_h; + ism6hg256x_fsm_ext_matrix_yy_l_t fsm_ext_matrix_yy_l; + ism6hg256x_fsm_ext_matrix_yy_h_t fsm_ext_matrix_yy_h; + ism6hg256x_fsm_ext_matrix_yz_l_t fsm_ext_matrix_yz_l; + ism6hg256x_fsm_ext_matrix_yz_h_t fsm_ext_matrix_yz_h; + ism6hg256x_fsm_ext_matrix_zz_l_t fsm_ext_matrix_zz_l; + ism6hg256x_fsm_ext_matrix_zz_h_t fsm_ext_matrix_zz_h; + ism6hg256x_ext_cfg_a_t ext_cfg_a; + ism6hg256x_ext_cfg_b_t ext_cfg_b; + /* Embedded functions extended page 1 registers */ + ism6hg256x_xl_hg_sensitivity_l_t xl_hg_sensitivity_l; + ism6hg256x_xl_hg_sensitivity_h_t xl_hg_sensitivity_h; + ism6hg256x_fsm_lc_timeout_l_t fsm_lc_timeout_l; + ism6hg256x_fsm_lc_timeout_h_t fsm_lc_timeout_h; + ism6hg256x_fsm_programs_t fsm_programs; + ism6hg256x_fsm_start_add_l_t fsm_start_add_l; + ism6hg256x_fsm_start_add_h_t fsm_start_add_h; + ism6hg256x_pedo_cmd_reg_t pedo_cmd_reg; + ism6hg256x_pedo_deb_steps_conf_t pedo_deb_steps_conf; + ism6hg256x_pedo_sc_deltat_l_t pedo_sc_deltat_l; + ism6hg256x_pedo_sc_deltat_h_t pedo_sc_deltat_h; + ism6hg256x_mlc_ext_sensitivity_l_t mlc_ext_sensitivity_l; + ism6hg256x_mlc_ext_sensitivity_h_t mlc_ext_sensitivity_h; + /* Embedded functions extended page 2 registers */ + ism6hg256x_ext_format_t ext_format; + ism6hg256x_ext_3byte_sensitivity_l_t ext_3byte_sensitivity_l; + ism6hg256x_ext_3byte_sensitivity_h_t ext_3byte_sensitivity_h; + ism6hg256x_ext_3byte_offset_xl_t ext_3byte_offset_xl; + ism6hg256x_ext_3byte_offset_l_t ext_3byte_offset_l; + ism6hg256x_ext_3byte_offset_h_t ext_3byte_offset_h; + /* Sensor HUB registers */ + ism6hg256x_sensor_hub_1_t sensor_hub_1; + ism6hg256x_sensor_hub_2_t sensor_hub_2; + ism6hg256x_sensor_hub_3_t sensor_hub_3; + ism6hg256x_sensor_hub_4_t sensor_hub_4; + ism6hg256x_sensor_hub_5_t sensor_hub_5; + ism6hg256x_sensor_hub_6_t sensor_hub_6; + ism6hg256x_sensor_hub_7_t sensor_hub_7; + ism6hg256x_sensor_hub_8_t sensor_hub_8; + ism6hg256x_sensor_hub_9_t sensor_hub_9; + ism6hg256x_sensor_hub_10_t sensor_hub_10; + ism6hg256x_sensor_hub_11_t sensor_hub_11; + ism6hg256x_sensor_hub_12_t sensor_hub_12; + ism6hg256x_sensor_hub_13_t sensor_hub_13; + ism6hg256x_sensor_hub_14_t sensor_hub_14; + ism6hg256x_sensor_hub_15_t sensor_hub_15; + ism6hg256x_sensor_hub_16_t sensor_hub_16; + ism6hg256x_sensor_hub_17_t sensor_hub_17; + ism6hg256x_sensor_hub_18_t sensor_hub_18; + ism6hg256x_controller_config_t controller_config; + ism6hg256x_tgt0_add_t tgt0_add; + ism6hg256x_tgt0_subadd_t tgt0_subadd; + ism6hg256x_tgt0_config_t tgt0_config; + ism6hg256x_tgt1_add_t tgt1_add; + ism6hg256x_tgt1_subadd_t tgt1_subadd; + ism6hg256x_tgt1_config_t tgt1_config; + ism6hg256x_tgt2_add_t tgt2_add; + ism6hg256x_tgt2_subadd_t tgt2_subadd; + ism6hg256x_tgt2_config_t tgt2_config; + ism6hg256x_tgt3_add_t tgt3_add; + ism6hg256x_tgt3_subadd_t tgt3_subadd; + ism6hg256x_tgt3_config_t tgt3_config; + ism6hg256x_datawrite_tgt0_t datawrite_tgt0; + ism6hg256x_status_controller_t status_controller; + bitwise_t bitwise; + uint8_t byte; +} ism6hg256x_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t ism6hg256x_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t ism6hg256x_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t ism6hg256x_from_sflp_to_mg(int16_t lsb); +float_t ism6hg256x_from_fs2_to_mg(int16_t lsb); +float_t ism6hg256x_from_fs4_to_mg(int16_t lsb); +float_t ism6hg256x_from_fs8_to_mg(int16_t lsb); +float_t ism6hg256x_from_fs16_to_mg(int16_t lsb); + +float_t ism6hg256x_from_fs32_to_mg(int16_t lsb); +float_t ism6hg256x_from_fs64_to_mg(int16_t lsb); +float_t ism6hg256x_from_fs128_to_mg(int16_t lsb); +float_t ism6hg256x_from_fs256_to_mg(int16_t lsb); + +float_t ism6hg256x_from_fs125_to_mdps(int16_t lsb); +float_t ism6hg256x_from_fs250_to_mdps(int16_t lsb); +float_t ism6hg256x_from_fs500_to_mdps(int16_t lsb); +float_t ism6hg256x_from_fs1000_to_mdps(int16_t lsb); +float_t ism6hg256x_from_fs2000_to_mdps(int16_t lsb); +float_t ism6hg256x_from_fs4000_to_mdps(int16_t lsb); + +float_t ism6hg256x_from_lsb_to_celsius(int16_t lsb); + +uint64_t ism6hg256x_from_lsb_to_nsec(uint32_t lsb); + +float_t ism6hg256x_from_lsb_to_mv(int16_t lsb); + +float_t ism6hg256x_from_gbias_lsb_to_mdps(int16_t lsb); +float_t ism6hg256x_from_gravity_lsb_to_mg(int16_t lsb); +float_t ism6hg256x_from_quaternion_lsb_to_float(uint16_t lsb); + +uint32_t ism6hg256x_from_f16_to_f32(uint16_t val); + +int32_t ism6hg256x_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + float_t z_mg; + float_t y_mg; + float_t x_mg; +} ism6hg256x_xl_offset_mg_t; +int32_t ism6hg256x_xl_offset_mg_set(const stmdev_ctx_t *ctx, + ism6hg256x_xl_offset_mg_t val); +int32_t ism6hg256x_xl_offset_mg_get(const stmdev_ctx_t *ctx, + ism6hg256x_xl_offset_mg_t *val); + +int32_t ism6hg256x_hg_xl_offset_mg_set(const stmdev_ctx_t *ctx, + ism6hg256x_xl_offset_mg_t val); +int32_t ism6hg256x_hg_xl_offset_mg_get(const stmdev_ctx_t *ctx, + ism6hg256x_xl_offset_mg_t *val); + +typedef enum +{ + ISM6HG256X_READY = 0x0, + ISM6HG256X_GLOBAL_RST = 0x1, + ISM6HG256X_RESTORE_CAL_PARAM = 0x2, + ISM6HG256X_RESTORE_CTRL_REGS = 0x4, +} ism6hg256x_reset_t; +int32_t ism6hg256x_reset_set(const stmdev_ctx_t *ctx, ism6hg256x_reset_t val); +int32_t ism6hg256x_reset_get(const stmdev_ctx_t *ctx, ism6hg256x_reset_t *val); + +typedef enum +{ + ISM6HG256X_MAIN_MEM_BANK = 0x0, + ISM6HG256X_EMBED_FUNC_MEM_BANK = 0x1, + ISM6HG256X_SENSOR_HUB_MEM_BANK = 0x2, +} ism6hg256x_mem_bank_t; +int32_t ism6hg256x_mem_bank_set(const stmdev_ctx_t *ctx, ism6hg256x_mem_bank_t val); +int32_t ism6hg256x_mem_bank_get(const stmdev_ctx_t *ctx, ism6hg256x_mem_bank_t *val); + +int32_t ism6hg256x_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_ODR_OFF = 0x0, + ISM6HG256X_ODR_AT_1Hz875 = 0x1, + ISM6HG256X_ODR_AT_7Hz5 = 0x2, + ISM6HG256X_ODR_AT_15Hz = 0x3, + ISM6HG256X_ODR_AT_30Hz = 0x4, + ISM6HG256X_ODR_AT_60Hz = 0x5, + ISM6HG256X_ODR_AT_120Hz = 0x6, + ISM6HG256X_ODR_AT_240Hz = 0x7, + ISM6HG256X_ODR_AT_480Hz = 0x8, + ISM6HG256X_ODR_AT_960Hz = 0x9, + ISM6HG256X_ODR_AT_1920Hz = 0xA, + ISM6HG256X_ODR_AT_3840Hz = 0xB, + ISM6HG256X_ODR_AT_7680Hz = 0xC, + ISM6HG256X_ODR_HA01_AT_15Hz625 = 0x13, + ISM6HG256X_ODR_HA01_AT_31Hz25 = 0x14, + ISM6HG256X_ODR_HA01_AT_62Hz5 = 0x15, + ISM6HG256X_ODR_HA01_AT_125Hz = 0x16, + ISM6HG256X_ODR_HA01_AT_250Hz = 0x17, + ISM6HG256X_ODR_HA01_AT_500Hz = 0x18, + ISM6HG256X_ODR_HA01_AT_1000Hz = 0x19, + ISM6HG256X_ODR_HA01_AT_2000Hz = 0x1A, + ISM6HG256X_ODR_HA01_AT_4000Hz = 0x1B, + ISM6HG256X_ODR_HA01_AT_8000Hz = 0x1C, + ISM6HG256X_ODR_HA02_AT_12Hz5 = 0x23, + ISM6HG256X_ODR_HA02_AT_25Hz = 0x24, + ISM6HG256X_ODR_HA02_AT_50Hz = 0x25, + ISM6HG256X_ODR_HA02_AT_100Hz = 0x26, + ISM6HG256X_ODR_HA02_AT_200Hz = 0x27, + ISM6HG256X_ODR_HA02_AT_400Hz = 0x28, + ISM6HG256X_ODR_HA02_AT_800Hz = 0x29, + ISM6HG256X_ODR_HA02_AT_1600Hz = 0x2A, + ISM6HG256X_ODR_HA02_AT_3200Hz = 0x2B, + ISM6HG256X_ODR_HA02_AT_6400Hz = 0x2C, + ISM6HG256X_ODR_HA03_AT_13Hz = 0x33, + ISM6HG256X_ODR_HA03_AT_26Hz = 0x34, + ISM6HG256X_ODR_HA03_AT_52Hz = 0x35, + ISM6HG256X_ODR_HA03_AT_104Hz = 0x36, + ISM6HG256X_ODR_HA03_AT_208Hz = 0x37, + ISM6HG256X_ODR_HA03_AT_417Hz = 0x38, + ISM6HG256X_ODR_HA03_AT_833Hz = 0x39, + ISM6HG256X_ODR_HA03_AT_1667Hz = 0x3A, + ISM6HG256X_ODR_HA03_AT_3333Hz = 0x3B, + ISM6HG256X_ODR_HA03_AT_6667Hz = 0x3C, +} ism6hg256x_data_rate_t; +int32_t ism6hg256x_xl_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_data_rate_t val); +int32_t ism6hg256x_xl_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_data_rate_t *val); +int32_t ism6hg256x_gy_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_data_rate_t val); +int32_t ism6hg256x_gy_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_data_rate_t *val); + +typedef enum +{ + ISM6HG256X_HG_XL_ODR_OFF = 0x0, + ISM6HG256X_HG_XL_ODR_AT_480Hz = 0x3, + ISM6HG256X_HG_XL_ODR_AT_960Hz = 0x4, + ISM6HG256X_HG_XL_ODR_AT_1920Hz = 0x5, + ISM6HG256X_HG_XL_ODR_AT_3840Hz = 0x6, + ISM6HG256X_HG_XL_ODR_AT_7680Hz = 0x7, +} ism6hg256x_hg_xl_data_rate_t; +int32_t ism6hg256x_hg_xl_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_hg_xl_data_rate_t val, + uint8_t reg_out_en); +int32_t ism6hg256x_hg_xl_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_hg_xl_data_rate_t *val, + uint8_t *reg_out_en); + +typedef enum +{ + ISM6HG256X_XL_HIGH_PERFORMANCE_MD = 0x0, + ISM6HG256X_XL_HIGH_ACCURACY_ODR_MD = 0x1, + ISM6HG256X_XL_ODR_TRIGGERED_MD = 0x3, + ISM6HG256X_XL_LOW_POWER_2_AVG_MD = 0x4, + ISM6HG256X_XL_LOW_POWER_4_AVG_MD = 0x5, + ISM6HG256X_XL_LOW_POWER_8_AVG_MD = 0x6, + ISM6HG256X_XL_NORMAL_MD = 0x7, +} ism6hg256x_xl_mode_t; +int32_t ism6hg256x_xl_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_xl_mode_t val); +int32_t ism6hg256x_xl_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_xl_mode_t *val); + +typedef enum +{ + ISM6HG256X_GY_HIGH_PERFORMANCE_MD = 0x0, + ISM6HG256X_GY_HIGH_ACCURACY_ODR_MD = 0x1, + ISM6HG256X_GY_ODR_TRIGGERED_MD = 0x3, + ISM6HG256X_GY_SLEEP_MD = 0x4, + ISM6HG256X_GY_LOW_POWER_MD = 0x5, +} ism6hg256x_gy_mode_t; +int32_t ism6hg256x_gy_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_gy_mode_t val); +int32_t ism6hg256x_gy_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_gy_mode_t *val); + +int32_t ism6hg256x_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_odr_trig_cfg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_DRDY_LATCHED = 0x0, + ISM6HG256X_DRDY_PULSED = 0x1, +} ism6hg256x_data_ready_mode_t; +int32_t ism6hg256x_data_ready_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_data_ready_mode_t val); +int32_t ism6hg256x_data_ready_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_data_ready_mode_t *val); + +typedef struct +{ + uint8_t hg_event : 1; + uint8_t hg_wakeup_z : 1; + uint8_t hg_wakeup_y : 1; + uint8_t hg_wakeup_x : 1; + uint8_t hg_wakeup : 1; + uint8_t hg_wakeup_chg : 1; + uint8_t hg_shock : 1; + uint8_t hg_shock_change : 1; +} ism6hg256x_hg_event_t; +int32_t ism6hg256x_hg_event_get(const stmdev_ctx_t *ctx, ism6hg256x_hg_event_t *val); + +typedef struct +{ + uint8_t hg_wakeup_ths : 8; + uint8_t hg_shock_dur : 4; +} ism6hg256x_hg_wake_up_cfg_t; +int32_t ism6hg256x_hg_wake_up_cfg_set(const stmdev_ctx_t *ctx, + ism6hg256x_hg_wake_up_cfg_t val); +int32_t ism6hg256x_hg_wake_up_cfg_get(const stmdev_ctx_t *ctx, + ism6hg256x_hg_wake_up_cfg_t *val); + +typedef struct +{ + uint8_t hg_interrupts_enable : 1; + uint8_t hg_wakeup_int_sel : 1; +} ism6hg256x_hg_wu_interrupt_cfg_t; +int32_t ism6hg256x_hg_wu_interrupt_cfg_set(const stmdev_ctx_t *ctx, + ism6hg256x_hg_wu_interrupt_cfg_t val); +int32_t ism6hg256x_hg_wu_interrupt_cfg_get(const stmdev_ctx_t *ctx, + ism6hg256x_hg_wu_interrupt_cfg_t *val); + +int32_t ism6hg256x_hg_emb_usr_off_correction_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_hg_emb_usr_off_correction_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_hg_wu_usr_off_correction_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_hg_wu_usr_off_correction_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t enable : 1; /* interrupt enable */ + uint8_t lir : 1; /* interrupt pulsed or latched */ +} ism6hg256x_interrupt_mode_t; +int32_t ism6hg256x_interrupt_enable_set(const stmdev_ctx_t *ctx, + ism6hg256x_interrupt_mode_t val); +int32_t ism6hg256x_interrupt_enable_get(const stmdev_ctx_t *ctx, + ism6hg256x_interrupt_mode_t *val); + +typedef enum +{ + ISM6HG256X_250dps = 0x1, + ISM6HG256X_500dps = 0x2, + ISM6HG256X_1000dps = 0x3, + ISM6HG256X_2000dps = 0x4, + ISM6HG256X_4000dps = 0x5, +} ism6hg256x_gy_full_scale_t; +int32_t ism6hg256x_gy_full_scale_set(const stmdev_ctx_t *ctx, + ism6hg256x_gy_full_scale_t val); +int32_t ism6hg256x_gy_full_scale_get(const stmdev_ctx_t *ctx, + ism6hg256x_gy_full_scale_t *val); + +typedef enum +{ + ISM6HG256X_2g = 0x0, + ISM6HG256X_4g = 0x1, + ISM6HG256X_8g = 0x2, + ISM6HG256X_16g = 0x3, +} ism6hg256x_xl_full_scale_t; +int32_t ism6hg256x_xl_full_scale_set(const stmdev_ctx_t *ctx, + ism6hg256x_xl_full_scale_t val); +int32_t ism6hg256x_xl_full_scale_get(const stmdev_ctx_t *ctx, + ism6hg256x_xl_full_scale_t *val); + +typedef enum +{ + ISM6HG256X_32g = 0x0, + ISM6HG256X_64g = 0x1, + ISM6HG256X_128g = 0x2, + ISM6HG256X_256g = 0x3, +} ism6hg256x_hg_xl_full_scale_t; +int32_t ism6hg256x_hg_xl_full_scale_set(const stmdev_ctx_t *ctx, + ism6hg256x_hg_xl_full_scale_t val); +int32_t ism6hg256x_hg_xl_full_scale_get(const stmdev_ctx_t *ctx, + ism6hg256x_hg_xl_full_scale_t *val); + +typedef enum +{ + ISM6HG256X_ST_DISABLE = 0x0, + ISM6HG256X_ST_POSITIVE = 0x1, + ISM6HG256X_ST_NEGATIVE = 0x2, +} ism6hg256x_self_test_t; +int32_t ism6hg256x_xl_self_test_set(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t val); +int32_t ism6hg256x_xl_self_test_get(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t *val); + +int32_t ism6hg256x_ois_xl_self_test_set(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t val); +int32_t ism6hg256x_ois_xl_self_test_get(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t *val); + +int32_t ism6hg256x_gy_self_test_set(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t val); +int32_t ism6hg256x_gy_self_test_get(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t *val); + +int32_t ism6hg256x_hg_xl_self_test_set(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t val); +int32_t ism6hg256x_hg_xl_self_test_get(const stmdev_ctx_t *ctx, ism6hg256x_self_test_t *val); + +typedef enum +{ + ISM6HG256X_OIS_GY_ST_DISABLE = 0x0, + ISM6HG256X_OIS_GY_ST_POSITIVE = 0x1, + ISM6HG256X_OIS_GY_ST_NEGATIVE = 0x2, + ISM6HG256X_OIS_GY_ST_CLAMP_POS = 0x5, + ISM6HG256X_OIS_GY_ST_CLAMP_NEG = 0x6, + +} ism6hg256x_ois_gy_self_test_t; +int32_t ism6hg256x_ois_gy_self_test_set(const stmdev_ctx_t *ctx, + ism6hg256x_ois_gy_self_test_t val); +int32_t ism6hg256x_ois_gy_self_test_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_gy_self_test_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t drdy_xlhgda : 1; + uint8_t drdy_eis : 1; + uint8_t drdy_ois : 1; + uint8_t gy_settling : 1; + uint8_t timestamp : 1; + uint8_t hg : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t wake_up_z : 1; + uint8_t wake_up_y : 1; + uint8_t wake_up_x : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_z : 1; + uint8_t tap_y : 1; + uint8_t tap_x : 1; + uint8_t tap_sign : 1; + uint8_t six_d : 1; + uint8_t six_d_xl : 1; + uint8_t six_d_xh : 1; + uint8_t six_d_yl : 1; + uint8_t six_d_yh : 1; + uint8_t six_d_zl : 1; + uint8_t six_d_zh : 1; + uint8_t sleep_change : 1; + uint8_t sleep_state : 1; + uint8_t step_detector : 1; + uint8_t step_count_inc : 1; + uint8_t step_count_overflow : 1; + uint8_t step_on_delta_time : 1; + uint8_t emb_func_stand_by : 1; + uint8_t emb_func_time_exceed : 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t mlc1 : 1; + uint8_t mlc2 : 1; + uint8_t mlc3 : 1; + uint8_t mlc4 : 1; + uint8_t mlc5 : 1; + uint8_t mlc6 : 1; + uint8_t mlc7 : 1; + uint8_t mlc8 : 1; + uint8_t sh_endop : 1; + uint8_t sh_target0_nack : 1; + uint8_t sh_target1_nack : 1; + uint8_t sh_target2_nack : 1; + uint8_t sh_target3_nack : 1; + uint8_t sh_wr_once : 1; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} ism6hg256x_all_sources_t; +int32_t ism6hg256x_all_sources_get(const stmdev_ctx_t *ctx, + ism6hg256x_all_sources_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_g : 1; + uint8_t drdy_g_eis : 1; + uint8_t drdy_temp : 1; + uint8_t fifo_th : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_full : 1; + uint8_t cnt_bdr : 1; + uint8_t timestamp : 1; + uint8_t shub : 1; + uint8_t sixd : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t wakeup : 1; + uint8_t freefall : 1; + uint8_t sleep_change : 1; + uint8_t drdy_hg_xl : 1; /* High-g */ + uint8_t hg_wakeup : 1; + uint8_t hg_shock_change : 1; + uint8_t step_detector : 1; /* Embedded Functions */ + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t emb_func_endop : 1; + uint8_t fsm1 : 1; /* FSM */ + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t mlc1 : 1; /* MLC */ + uint8_t mlc2 : 1; + uint8_t mlc3 : 1; + uint8_t mlc4 : 1; + uint8_t mlc5 : 1; + uint8_t mlc6 : 1; + uint8_t mlc7 : 1; + uint8_t mlc8 : 1; +} ism6hg256x_pin_int_route_t; + +int32_t ism6hg256x_pin_int1_route_set(const stmdev_ctx_t *ctx, ism6hg256x_pin_int_route_t *val); +int32_t ism6hg256x_pin_int1_route_get(const stmdev_ctx_t *ctx, ism6hg256x_pin_int_route_t *val); +int32_t ism6hg256x_pin_int2_route_set(const stmdev_ctx_t *ctx, ism6hg256x_pin_int_route_t *val); +int32_t ism6hg256x_pin_int2_route_get(const stmdev_ctx_t *ctx, ism6hg256x_pin_int_route_t *val); + +int32_t ism6hg256x_pin_int1_route_hg_set(const stmdev_ctx_t *ctx, ism6hg256x_pin_int_route_t *val); +int32_t ism6hg256x_pin_int1_route_hg_get(const stmdev_ctx_t *ctx, ism6hg256x_pin_int_route_t *val); +int32_t ism6hg256x_pin_int2_route_hg_set(const stmdev_ctx_t *ctx, ism6hg256x_pin_int_route_t *val); +int32_t ism6hg256x_pin_int2_route_hg_get(const stmdev_ctx_t *ctx, ism6hg256x_pin_int_route_t *val); + +int32_t ism6hg256x_pin_int1_route_embedded_set(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val); +int32_t ism6hg256x_pin_int1_route_embedded_get(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val); +int32_t ism6hg256x_pin_int2_route_embedded_set(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val); +int32_t ism6hg256x_pin_int2_route_embedded_get(const stmdev_ctx_t *ctx, + ism6hg256x_pin_int_route_t *val); + +typedef struct +{ + uint8_t drdy_hgxl : 1; + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; +} ism6hg256x_data_ready_t; +int32_t ism6hg256x_flag_data_ready_get(const stmdev_ctx_t *ctx, + ism6hg256x_data_ready_t *val); + +int32_t ism6hg256x_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism6hg256x_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism6hg256x_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism6hg256x_ois_eis_angular_rate_raw_get(const stmdev_ctx_t *ctx, + int16_t *val); + +int32_t ism6hg256x_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism6hg256x_ois_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism6hg256x_hg_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism6hg256x_sflp_gbias_raw_get(const stmdev_ctx_t *ctx, int16_t *val); +int32_t ism6hg256x_sflp_gravity_raw_get(const stmdev_ctx_t *ctx, int16_t *val); +int32_t ism6hg256x_sflp_quaternion_raw_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t ism6hg256x_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); + +int32_t ism6hg256x_disable_embedded_function_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_disable_embedded_function_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t xl_hg_conv_en : 1; + uint8_t gyro_conv_en : 1; + uint8_t temp_conv_en : 1; + uint8_t ext_sensor_conv_en : 1; +} ism6hg256x_emb_func_conv_t; +int32_t ism6hg256x_emb_func_conv_set(const stmdev_ctx_t *ctx, ism6hg256x_emb_func_conv_t val); +int32_t ism6hg256x_emb_func_conv_get(const stmdev_ctx_t *ctx, ism6hg256x_emb_func_conv_t *val); + +int32_t ism6hg256x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t ism6hg256x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, + uint8_t len); + +int32_t ism6hg256x_emb_function_dbg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_emb_function_dbg_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_DEN_ACT_LOW = 0x0, + ISM6HG256X_DEN_ACT_HIGH = 0x1, +} ism6hg256x_den_polarity_t; +int32_t ism6hg256x_den_polarity_set(const stmdev_ctx_t *ctx, + ism6hg256x_den_polarity_t val); +int32_t ism6hg256x_den_polarity_get(const stmdev_ctx_t *ctx, + ism6hg256x_den_polarity_t *val); + +typedef enum +{ + ISM6HG256X_EIS_250dps = 0x1, + ISM6HG256X_EIS_500dps = 0x2, + ISM6HG256X_EIS_1000dps = 0x3, + ISM6HG256X_EIS_2000dps = 0x4, + ISM6HG256X_EIS_4000dps = 0x5, +} ism6hg256x_eis_gy_full_scale_t; +int32_t ism6hg256x_eis_gy_full_scale_set(const stmdev_ctx_t *ctx, + ism6hg256x_eis_gy_full_scale_t val); +int32_t ism6hg256x_eis_gy_full_scale_get(const stmdev_ctx_t *ctx, + ism6hg256x_eis_gy_full_scale_t *val); + +int32_t ism6hg256x_eis_gy_on_if2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_eis_gy_on_if2_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_EIS_ODR_OFF = 0x0, + ISM6HG256X_EIS_1920Hz = 0x1, + ISM6HG256X_EIS_960Hz = 0x2, +} ism6hg256x_gy_eis_data_rate_t; +int32_t ism6hg256x_gy_eis_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_gy_eis_data_rate_t val); +int32_t ism6hg256x_gy_eis_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_gy_eis_data_rate_t *val); + +int32_t ism6hg256x_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_CMP_DISABLE = 0x0, + ISM6HG256X_CMP_8_TO_1 = 0x1, + ISM6HG256X_CMP_16_TO_1 = 0x2, + ISM6HG256X_CMP_32_TO_1 = 0x3, +} ism6hg256x_fifo_compress_algo_t; +int32_t ism6hg256x_fifo_compress_algo_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_compress_algo_t val); +int32_t ism6hg256x_fifo_compress_algo_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_compress_algo_t *val); + +int32_t ism6hg256x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism6hg256x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t ism6hg256x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism6hg256x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +typedef enum +{ + ISM6HG256X_FIFO_EV_WTM = 0x0, + ISM6HG256X_FIFO_EV_FULL = 0x1, +} ism6hg256x_fifo_event_t; + +int32_t ism6hg256x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, ism6hg256x_fifo_event_t val); +int32_t ism6hg256x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, ism6hg256x_fifo_event_t *val); + +typedef enum +{ + ISM6HG256X_XL_NOT_BATCHED = 0x0, + ISM6HG256X_XL_BATCHED_AT_1Hz875 = 0x1, + ISM6HG256X_XL_BATCHED_AT_7Hz5 = 0x2, + ISM6HG256X_XL_BATCHED_AT_15Hz = 0x3, + ISM6HG256X_XL_BATCHED_AT_30Hz = 0x4, + ISM6HG256X_XL_BATCHED_AT_60Hz = 0x5, + ISM6HG256X_XL_BATCHED_AT_120Hz = 0x6, + ISM6HG256X_XL_BATCHED_AT_240Hz = 0x7, + ISM6HG256X_XL_BATCHED_AT_480Hz = 0x8, + ISM6HG256X_XL_BATCHED_AT_960Hz = 0x9, + ISM6HG256X_XL_BATCHED_AT_1920Hz = 0xa, + ISM6HG256X_XL_BATCHED_AT_3840Hz = 0xb, + ISM6HG256X_XL_BATCHED_AT_7680Hz = 0xc, +} ism6hg256x_fifo_xl_batch_t; +int32_t ism6hg256x_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_xl_batch_t val); +int32_t ism6hg256x_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_xl_batch_t *val); + +typedef enum +{ + ISM6HG256X_GY_NOT_BATCHED = 0x0, + ISM6HG256X_GY_BATCHED_AT_1Hz875 = 0x1, + ISM6HG256X_GY_BATCHED_AT_7Hz5 = 0x2, + ISM6HG256X_GY_BATCHED_AT_15Hz = 0x3, + ISM6HG256X_GY_BATCHED_AT_30Hz = 0x4, + ISM6HG256X_GY_BATCHED_AT_60Hz = 0x5, + ISM6HG256X_GY_BATCHED_AT_120Hz = 0x6, + ISM6HG256X_GY_BATCHED_AT_240Hz = 0x7, + ISM6HG256X_GY_BATCHED_AT_480Hz = 0x8, + ISM6HG256X_GY_BATCHED_AT_960Hz = 0x9, + ISM6HG256X_GY_BATCHED_AT_1920Hz = 0xa, + ISM6HG256X_GY_BATCHED_AT_3840Hz = 0xb, + ISM6HG256X_GY_BATCHED_AT_7680Hz = 0xc, +} ism6hg256x_fifo_gy_batch_t; +int32_t ism6hg256x_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_gy_batch_t val); +int32_t ism6hg256x_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_gy_batch_t *val); + +int32_t ism6hg256x_fifo_hg_xl_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_fifo_hg_xl_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_BYPASS_MODE = 0x0, + ISM6HG256X_FIFO_MODE = 0x1, + ISM6HG256X_STREAM_WTM_TO_FULL_MODE = 0x2, + ISM6HG256X_STREAM_TO_FIFO_MODE = 0x3, + ISM6HG256X_BYPASS_TO_STREAM_MODE = 0x4, + ISM6HG256X_STREAM_MODE = 0x6, + ISM6HG256X_BYPASS_TO_FIFO_MODE = 0x7, +} ism6hg256x_fifo_mode_t; +int32_t ism6hg256x_fifo_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_fifo_mode_t val); +int32_t ism6hg256x_fifo_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_mode_t *val); + +int32_t ism6hg256x_fifo_gy_eis_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_TEMP_NOT_BATCHED = 0x0, + ISM6HG256X_TEMP_BATCHED_AT_1Hz875 = 0x1, + ISM6HG256X_TEMP_BATCHED_AT_15Hz = 0x2, + ISM6HG256X_TEMP_BATCHED_AT_60Hz = 0x3, +} ism6hg256x_fifo_temp_batch_t; +int32_t ism6hg256x_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_temp_batch_t val); +int32_t ism6hg256x_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_temp_batch_t *val); + +typedef enum +{ + ISM6HG256X_TMSTMP_NOT_BATCHED = 0x0, + ISM6HG256X_TMSTMP_DEC_1 = 0x1, + ISM6HG256X_TMSTMP_DEC_8 = 0x2, + ISM6HG256X_TMSTMP_DEC_32 = 0x3, +} ism6hg256x_fifo_timestamp_batch_t; +int32_t ism6hg256x_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_timestamp_batch_t val); +int32_t ism6hg256x_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_timestamp_batch_t *val); + +int32_t ism6hg256x_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t ism6hg256x_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val); + +typedef enum +{ + ISM6HG256X_XL_LG_BATCH_EVENT = 0x0, + ISM6HG256X_GY_BATCH_EVENT = 0x1, + ISM6HG256X_GY_EIS_BATCH_EVENT = 0x2, + ISM6HG256X_XL_HG_BATCH_EVENT = 0x3, +} ism6hg256x_fifo_batch_cnt_event_t; +int32_t ism6hg256x_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_batch_cnt_event_t val); +int32_t ism6hg256x_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_batch_cnt_event_t *val); + +typedef struct +{ + uint16_t fifo_level : 9; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} ism6hg256x_fifo_status_t; + +int32_t ism6hg256x_fifo_status_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_status_t *val); + +typedef struct +{ + enum + { + ISM6HG256X_FIFO_EMPTY = 0x0, + ISM6HG256X_GY_NC_TAG = 0x1, + ISM6HG256X_XL_NC_TAG = 0x2, + ISM6HG256X_TEMPERATURE_TAG = 0x3, + ISM6HG256X_TIMESTAMP_TAG = 0x4, + ISM6HG256X_CFG_CHANGE_TAG = 0x5, + ISM6HG256X_XL_NC_T_2_TAG = 0x6, + ISM6HG256X_XL_NC_T_1_TAG = 0x7, + ISM6HG256X_XL_2XC_TAG = 0x8, + ISM6HG256X_XL_3XC_TAG = 0x9, + ISM6HG256X_GY_NC_T_2_TAG = 0xA, + ISM6HG256X_GY_NC_T_1_TAG = 0xB, + ISM6HG256X_GY_2XC_TAG = 0xC, + ISM6HG256X_GY_3XC_TAG = 0xD, + ISM6HG256X_SENSORHUB_TARGET0_TAG = 0xE, + ISM6HG256X_SENSORHUB_TARGET1_TAG = 0xF, + ISM6HG256X_SENSORHUB_TARGET2_TAG = 0x10, + ISM6HG256X_SENSORHUB_TARGET3_TAG = 0x11, + ISM6HG256X_STEP_COUNTER_TAG = 0x12, + ISM6HG256X_SFLP_GAME_ROTATION_VECTOR_TAG = 0x13, + ISM6HG256X_SFLP_GYROSCOPE_BIAS_TAG = 0x16, + ISM6HG256X_SFLP_GRAVITY_VECTOR_TAG = 0x17, + ISM6HG256X_HG_XL_PEAK_TAG = 0x18, + ISM6HG256X_SENSORHUB_NACK_TAG = 0x19, + ISM6HG256X_MLC_RESULT_TAG = 0x1A, + ISM6HG256X_MLC_FILTER = 0x1B, + ISM6HG256X_MLC_FEATURE = 0x1C, + ISM6HG256X_XL_HG_TAG = 0x1D, + ISM6HG256X_GY_ENHANCED_EIS = 0x1E, + ISM6HG256X_FSM_RESULT_TAG = 0x1F, + } tag; + uint8_t cnt; + uint8_t data[6]; +} ism6hg256x_fifo_out_raw_t; +int32_t ism6hg256x_fifo_out_raw_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_out_raw_t *val); + +int32_t ism6hg256x_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_fifo_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_fifo_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_fifo_sh_batch_target_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val); +int32_t ism6hg256x_fifo_sh_batch_target_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val); + +typedef struct +{ + uint8_t game_rotation : 1; + uint8_t gravity : 1; + uint8_t gbias : 1; +} ism6hg256x_fifo_sflp_raw_t; +int32_t ism6hg256x_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_sflp_raw_t val); +int32_t ism6hg256x_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, + ism6hg256x_fifo_sflp_raw_t *val); + +typedef enum +{ + ISM6HG256X_AUTO = 0x0, + ISM6HG256X_ALWAYS_ACTIVE = 0x1, +} ism6hg256x_filt_anti_spike_t; +int32_t ism6hg256x_filt_anti_spike_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_anti_spike_t val); +int32_t ism6hg256x_filt_anti_spike_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_anti_spike_t *val); + +typedef struct +{ + uint8_t drdy : 1; + uint8_t ois_drdy : 1; + uint8_t irq_xl : 1; + uint8_t irq_xl_hg : 1; + uint8_t irq_g : 1; +} ism6hg256x_filt_settling_mask_t; +int32_t ism6hg256x_filt_settling_mask_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_settling_mask_t val); +int32_t ism6hg256x_filt_settling_mask_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_settling_mask_t *val); + +typedef struct +{ + uint8_t ois_drdy : 1; +} ism6hg256x_filt_ois_settling_mask_t; +int32_t ism6hg256x_filt_ois_settling_mask_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_ois_settling_mask_t val); +int32_t ism6hg256x_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_ois_settling_mask_t *val); + +typedef enum +{ + ISM6HG256X_GY_ULTRA_LIGHT = 0x0, + ISM6HG256X_GY_VERY_LIGHT = 0x1, + ISM6HG256X_GY_LIGHT = 0x2, + ISM6HG256X_GY_MEDIUM = 0x3, + ISM6HG256X_GY_STRONG = 0x4, + ISM6HG256X_GY_VERY_STRONG = 0x5, + ISM6HG256X_GY_AGGRESSIVE = 0x6, + ISM6HG256X_GY_XTREME = 0x7, +} ism6hg256x_filt_gy_lp1_bandwidth_t; +int32_t ism6hg256x_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_gy_lp1_bandwidth_t val); +int32_t ism6hg256x_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_gy_lp1_bandwidth_t *val); + +int32_t ism6hg256x_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_XL_ULTRA_LIGHT = 0x0, + ISM6HG256X_XL_VERY_LIGHT = 0x1, + ISM6HG256X_XL_LIGHT = 0x2, + ISM6HG256X_XL_MEDIUM = 0x3, + ISM6HG256X_XL_STRONG = 0x4, + ISM6HG256X_XL_VERY_STRONG = 0x5, + ISM6HG256X_XL_AGGRESSIVE = 0x6, + ISM6HG256X_XL_XTREME = 0x7, +} ism6hg256x_filt_xl_lp2_bandwidth_t; +int32_t ism6hg256x_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_xl_lp2_bandwidth_t val); +int32_t ism6hg256x_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_xl_lp2_bandwidth_t *val); + +int32_t ism6hg256x_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_HP_MD_NORMAL = 0x0, + ISM6HG256X_HP_MD_REFERENCE = 0x1, +} ism6hg256x_filt_xl_hp_mode_t; +int32_t ism6hg256x_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_xl_hp_mode_t val); +int32_t ism6hg256x_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_xl_hp_mode_t *val); + +typedef enum +{ + ISM6HG256X_WK_FEED_SLOPE = 0x0, + ISM6HG256X_WK_FEED_HIGH_PASS = 0x1, + ISM6HG256X_WK_FEED_LP_WITH_OFFSET = 0x2, +} ism6hg256x_filt_wkup_act_feed_t; +int32_t ism6hg256x_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_wkup_act_feed_t val); +int32_t ism6hg256x_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_wkup_act_feed_t *val); + +int32_t ism6hg256x_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_SIXD_FEED_ODR_DIV_2 = 0x0, + ISM6HG256X_SIXD_FEED_LOW_PASS = 0x1, +} ism6hg256x_filt_sixd_feed_t; +int32_t ism6hg256x_filt_sixd_feed_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_sixd_feed_t val); +int32_t ism6hg256x_filt_sixd_feed_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_sixd_feed_t *val); + +typedef enum +{ + ISM6HG256X_EIS_LP_NORMAL = 0x0, + ISM6HG256X_EIS_LP_LIGHT = 0x1, +} ism6hg256x_filt_gy_eis_lp_bandwidth_t; +int32_t ism6hg256x_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_gy_eis_lp_bandwidth_t val); +int32_t ism6hg256x_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_gy_eis_lp_bandwidth_t *val); + +typedef enum +{ + ISM6HG256X_OIS_GY_LP_NORMAL = 0x0, + ISM6HG256X_OIS_GY_LP_STRONG = 0x1, + ISM6HG256X_OIS_GY_LP_AGGRESSIVE = 0x2, + ISM6HG256X_OIS_GY_LP_LIGHT = 0x3, +} ism6hg256x_filt_gy_ois_lp_bandwidth_t; +int32_t ism6hg256x_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_gy_ois_lp_bandwidth_t val); +int32_t ism6hg256x_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_gy_ois_lp_bandwidth_t *val); + +typedef enum +{ + ISM6HG256X_OIS_XL_LP_ULTRA_LIGHT = 0x0, + ISM6HG256X_OIS_XL_LP_VERY_LIGHT = 0x1, + ISM6HG256X_OIS_XL_LP_LIGHT = 0x2, + ISM6HG256X_OIS_XL_LP_NORMAL = 0x3, + ISM6HG256X_OIS_XL_LP_STRONG = 0x4, + ISM6HG256X_OIS_XL_LP_VERY_STRONG = 0x5, + ISM6HG256X_OIS_XL_LP_AGGRESSIVE = 0x6, + ISM6HG256X_OIS_XL_LP_XTREME = 0x7, +} ism6hg256x_filt_xl_ois_lp_bandwidth_t; +int32_t ism6hg256x_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, + ism6hg256x_filt_xl_ois_lp_bandwidth_t val); +int32_t ism6hg256x_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, + ism6hg256x_filt_xl_ois_lp_bandwidth_t *val); + +typedef enum +{ + ISM6HG256X_PROTECT_CTRL_REGS = 0x0, + ISM6HG256X_WRITE_CTRL_REG = 0x1, +} ism6hg256x_fsm_permission_t; +int32_t ism6hg256x_fsm_permission_set(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_permission_t val); +int32_t ism6hg256x_fsm_permission_get(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_permission_t *val); +int32_t ism6hg256x_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +} ism6hg256x_fsm_mode_t; +int32_t ism6hg256x_fsm_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_fsm_mode_t val); +int32_t ism6hg256x_fsm_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_fsm_mode_t *val); + +int32_t ism6hg256x_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism6hg256x_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); + + +typedef struct +{ + uint8_t fsm_outs1; + uint8_t fsm_outs2; + uint8_t fsm_outs3; + uint8_t fsm_outs4; + uint8_t fsm_outs5; + uint8_t fsm_outs6; + uint8_t fsm_outs7; + uint8_t fsm_outs8; +} ism6hg256x_fsm_out_t; +int32_t ism6hg256x_fsm_out_get(const stmdev_ctx_t *ctx, ism6hg256x_fsm_out_t *val); + +typedef enum +{ + ISM6HG256X_FSM_15Hz = 0x0, + ISM6HG256X_FSM_30Hz = 0x1, + ISM6HG256X_FSM_60Hz = 0x2, + ISM6HG256X_FSM_120Hz = 0x3, + ISM6HG256X_FSM_240Hz = 0x4, + ISM6HG256X_FSM_480Hz = 0x5, + ISM6HG256X_FSM_960Hz = 0x6, +} ism6hg256x_fsm_data_rate_t; +int32_t ism6hg256x_fsm_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_data_rate_t val); +int32_t ism6hg256x_fsm_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_data_rate_t *val); + +int32_t ism6hg256x_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t ism6hg256x_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, + uint16_t *val); + +typedef struct +{ + uint16_t z; + uint16_t y; + uint16_t x; +} ism6hg256x_xl_fsm_ext_sens_offset_t; +int32_t ism6hg256x_fsm_ext_sens_offset_set(const stmdev_ctx_t *ctx, + ism6hg256x_xl_fsm_ext_sens_offset_t val); +int32_t ism6hg256x_fsm_ext_sens_offset_get(const stmdev_ctx_t *ctx, + ism6hg256x_xl_fsm_ext_sens_offset_t *val); + +typedef struct +{ + uint16_t xx; + uint16_t xy; + uint16_t xz; + uint16_t yy; + uint16_t yz; + uint16_t zz; +} ism6hg256x_xl_fsm_ext_sens_matrix_t; +int32_t ism6hg256x_fsm_ext_sens_matrix_set(const stmdev_ctx_t *ctx, + ism6hg256x_xl_fsm_ext_sens_matrix_t val); +int32_t ism6hg256x_fsm_ext_sens_matrix_get(const stmdev_ctx_t *ctx, + ism6hg256x_xl_fsm_ext_sens_matrix_t *val); + +typedef enum +{ + ISM6HG256X_Z_EQ_Y = 0x0, + ISM6HG256X_Z_EQ_MIN_Y = 0x1, + ISM6HG256X_Z_EQ_X = 0x2, + ISM6HG256X_Z_EQ_MIN_X = 0x3, + ISM6HG256X_Z_EQ_MIN_Z = 0x4, + ISM6HG256X_Z_EQ_Z = 0x5, +} ism6hg256x_fsm_ext_sens_z_orient_t; +int32_t ism6hg256x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_ext_sens_z_orient_t val); +int32_t ism6hg256x_fsm_ext_sens_z_orient_get(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_ext_sens_z_orient_t *val); + +typedef enum +{ + ISM6HG256X_Y_EQ_Y = 0x0, + ISM6HG256X_Y_EQ_MIN_Y = 0x1, + ISM6HG256X_Y_EQ_X = 0x2, + ISM6HG256X_Y_EQ_MIN_X = 0x3, + ISM6HG256X_Y_EQ_MIN_Z = 0x4, + ISM6HG256X_Y_EQ_Z = 0x5, +} ism6hg256x_fsm_ext_sens_y_orient_t; +int32_t ism6hg256x_fsm_ext_sens_y_orient_set(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_ext_sens_y_orient_t val); +int32_t ism6hg256x_fsm_ext_sens_y_orient_get(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_ext_sens_y_orient_t *val); + +typedef enum +{ + ISM6HG256X_X_EQ_Y = 0x0, + ISM6HG256X_X_EQ_MIN_Y = 0x1, + ISM6HG256X_X_EQ_X = 0x2, + ISM6HG256X_X_EQ_MIN_X = 0x3, + ISM6HG256X_X_EQ_MIN_Z = 0x4, + ISM6HG256X_X_EQ_Z = 0x5, +} ism6hg256x_fsm_ext_sens_x_orient_t; +int32_t ism6hg256x_fsm_ext_sens_x_orient_set(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_ext_sens_x_orient_t val); +int32_t ism6hg256x_fsm_ext_sens_x_orient_get(const stmdev_ctx_t *ctx, + ism6hg256x_fsm_ext_sens_x_orient_t *val); + +int32_t ism6hg256x_xl_hg_peak_tracking_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_xl_hg_peak_tracking_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_xl_hg_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism6hg256x_xl_hg_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t ism6hg256x_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism6hg256x_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t ism6hg256x_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism6hg256x_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t ism6hg256x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_156_mg = 0x0, + ISM6HG256X_219_mg = 0x1, + ISM6HG256X_250_mg = 0x2, + ISM6HG256X_312_mg = 0x3, + ISM6HG256X_344_mg = 0x4, + ISM6HG256X_406_mg = 0x5, + ISM6HG256X_469_mg = 0x6, + ISM6HG256X_500_mg = 0x7, +} ism6hg256x_ff_thresholds_t; +int32_t ism6hg256x_ff_thresholds_set(const stmdev_ctx_t *ctx, + ism6hg256x_ff_thresholds_t val); +int32_t ism6hg256x_ff_thresholds_get(const stmdev_ctx_t *ctx, + ism6hg256x_ff_thresholds_t *val); + +typedef enum +{ + ISM6HG256X_MLC_OFF = 0x0, + ISM6HG256X_MLC_ON = 0x1, + ISM6HG256X_MLC_ON_BEFORE_FSM = 0x2, +} ism6hg256x_mlc_mode_t; +int32_t ism6hg256x_mlc_set(const stmdev_ctx_t *ctx, ism6hg256x_mlc_mode_t val); +int32_t ism6hg256x_mlc_get(const stmdev_ctx_t *ctx, ism6hg256x_mlc_mode_t *val); + +typedef enum +{ + ISM6HG256X_MLC_15Hz = 0x0, + ISM6HG256X_MLC_30Hz = 0x1, + ISM6HG256X_MLC_60Hz = 0x2, + ISM6HG256X_MLC_120Hz = 0x3, + ISM6HG256X_MLC_240Hz = 0x4, + ISM6HG256X_MLC_480Hz = 0x5, + ISM6HG256X_MLC_960Hz = 0x6, +} ism6hg256x_mlc_data_rate_t; +int32_t ism6hg256x_mlc_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_mlc_data_rate_t val); +int32_t ism6hg256x_mlc_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_mlc_data_rate_t *val); + +typedef struct +{ + uint8_t mlc1_src; + uint8_t mlc2_src; + uint8_t mlc3_src; + uint8_t mlc4_src; + uint8_t mlc5_src; + uint8_t mlc6_src; + uint8_t mlc7_src; + uint8_t mlc8_src; +} ism6hg256x_mlc_out_t; +int32_t ism6hg256x_mlc_out_get(const stmdev_ctx_t *ctx, ism6hg256x_mlc_out_t *val); + +int32_t ism6hg256x_mlc_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t ism6hg256x_mlc_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, + uint16_t *val); + +typedef enum +{ + ISM6HG256X_OIS_CTRL_FROM_OIS = 0x0, + ISM6HG256X_OIS_CTRL_FROM_UI = 0x1, +} ism6hg256x_ois_ctrl_mode_t; +int32_t ism6hg256x_ois_ctrl_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_ois_ctrl_mode_t val); +int32_t ism6hg256x_ois_ctrl_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_ctrl_mode_t *val); + +int32_t ism6hg256x_ois_reset_set(const stmdev_ctx_t *ctx, int8_t val); +int32_t ism6hg256x_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val); + +int32_t ism6hg256x_ois_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t ack : 1; + uint8_t req : 1; +} ism6hg256x_ois_handshake_t; +int32_t ism6hg256x_ois_handshake_from_ui_set(const stmdev_ctx_t *ctx, + ism6hg256x_ois_handshake_t val); +int32_t ism6hg256x_ois_handshake_from_ui_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_handshake_t *val); +int32_t ism6hg256x_ois_handshake_from_ois_set(const stmdev_ctx_t *ctx, + ism6hg256x_ois_handshake_t val); +int32_t ism6hg256x_ois_handshake_from_ois_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_handshake_t *val); + +int32_t ism6hg256x_ois_shared_set(const stmdev_ctx_t *ctx, uint8_t val[6]); +int32_t ism6hg256x_ois_shared_get(const stmdev_ctx_t *ctx, uint8_t val[6]); + +int32_t ism6hg256x_ois_on_if2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_ois_on_if2_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t gy : 1; + uint8_t xl : 1; +} ism6hg256x_ois_chain_t; +int32_t ism6hg256x_ois_chain_set(const stmdev_ctx_t *ctx, ism6hg256x_ois_chain_t val); +int32_t ism6hg256x_ois_chain_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_chain_t *val); + +typedef enum +{ + ISM6HG256X_OIS_250dps = 0x1, + ISM6HG256X_OIS_500dps = 0x2, + ISM6HG256X_OIS_1000dps = 0x3, + ISM6HG256X_OIS_2000dps = 0x4, +} ism6hg256x_ois_gy_full_scale_t; +int32_t ism6hg256x_ois_gy_full_scale_set(const stmdev_ctx_t *ctx, + ism6hg256x_ois_gy_full_scale_t val); +int32_t ism6hg256x_ois_gy_full_scale_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_gy_full_scale_t *val); + +typedef enum +{ + ISM6HG256X_OIS_2g = 0x0, + ISM6HG256X_OIS_4g = 0x1, + ISM6HG256X_OIS_8g = 0x2, + ISM6HG256X_OIS_16g = 0x3, +} ism6hg256x_ois_xl_full_scale_t; +int32_t ism6hg256x_ois_xl_full_scale_set(const stmdev_ctx_t *ctx, + ism6hg256x_ois_xl_full_scale_t val); +int32_t ism6hg256x_ois_xl_full_scale_get(const stmdev_ctx_t *ctx, + ism6hg256x_ois_xl_full_scale_t *val); + +typedef enum +{ + ISM6HG256X_DEG_80 = 0x0, + ISM6HG256X_DEG_70 = 0x1, + ISM6HG256X_DEG_60 = 0x2, + ISM6HG256X_DEG_50 = 0x3, +} ism6hg256x_6d_threshold_t; +int32_t ism6hg256x_6d_threshold_set(const stmdev_ctx_t *ctx, + ism6hg256x_6d_threshold_t val); +int32_t ism6hg256x_6d_threshold_get(const stmdev_ctx_t *ctx, + ism6hg256x_6d_threshold_t *val); + +int32_t ism6hg256x_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_I2C_I3C_ENABLE = 0x0, + ISM6HG256X_I2C_I3C_DISABLE = 0x1, +} ism6hg256x_ui_i2c_i3c_mode_t; +int32_t ism6hg256x_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_ui_i2c_i3c_mode_t val); +int32_t ism6hg256x_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_ui_i2c_i3c_mode_t *val); + +typedef struct +{ + uint8_t if2_ta0_pid : 1; + enum + { + ISM6HG256X_SW_RST_DYN_ADDRESS_RST = 0x0, + ISM6HG256X_I3C_GLOBAL_RST = 0x1, + } rst_mode; + enum + { + ISM6HG256X_IBI_50us = 0x0, + ISM6HG256X_IBI_2us = 0x1, + ISM6HG256X_IBI_1ms = 0x2, + ISM6HG256X_IBI_50ms = 0x3, + } ibi_time; +} ism6hg256x_i3c_config_t; + +int32_t ism6hg256x_i3c_config_set(const stmdev_ctx_t *ctx, + ism6hg256x_i3c_config_t val); +int32_t ism6hg256x_i3c_config_get(const stmdev_ctx_t *ctx, + ism6hg256x_i3c_config_t *val); + +int32_t ism6hg256x_sh_controller_interface_pull_up_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism6hg256x_sh_controller_interface_pull_up_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t ism6hg256x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, + uint8_t len); + +typedef enum +{ + ISM6HG256X_TGT_0 = 0x0, + ISM6HG256X_TGT_0_1 = 0x1, + ISM6HG256X_TGT_0_1_2 = 0x2, + ISM6HG256X_TGT_0_1_2_3 = 0x3, +} ism6hg256x_sh_target_connected_t; +int32_t ism6hg256x_sh_target_connected_set(const stmdev_ctx_t *ctx, + ism6hg256x_sh_target_connected_t val); +int32_t ism6hg256x_sh_target_connected_get(const stmdev_ctx_t *ctx, + ism6hg256x_sh_target_connected_t *val); + +int32_t ism6hg256x_sh_controller_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_sh_controller_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_SH_TRG_XL_GY_DRDY = 0x0, + ISM6HG256X_SH_TRIG_INT2 = 0x1, +} ism6hg256x_sh_syncro_mode_t; +int32_t ism6hg256x_sh_syncro_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_sh_syncro_mode_t val); +int32_t ism6hg256x_sh_syncro_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_sh_syncro_mode_t *val); + +typedef enum +{ + ISM6HG256X_EACH_SH_CYCLE = 0x0, + ISM6HG256X_ONLY_FIRST_CYCLE = 0x1, +} ism6hg256x_sh_write_mode_t; +int32_t ism6hg256x_sh_write_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_sh_write_mode_t val); +int32_t ism6hg256x_sh_write_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_sh_write_mode_t *val); + +int32_t ism6hg256x_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t tgt0_add; + uint8_t tgt0_subadd; + uint8_t tgt0_data; +} ism6hg256x_sh_cfg_write_t; +int32_t ism6hg256x_sh_cfg_write(const stmdev_ctx_t *ctx, + ism6hg256x_sh_cfg_write_t *val); +typedef enum +{ + ISM6HG256X_SH_15Hz = 0x1, + ISM6HG256X_SH_30Hz = 0x2, + ISM6HG256X_SH_60Hz = 0x3, + ISM6HG256X_SH_120Hz = 0x4, + ISM6HG256X_SH_240Hz = 0x5, + ISM6HG256X_SH_480Hz = 0x6, +} ism6hg256x_sh_data_rate_t; +int32_t ism6hg256x_sh_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_sh_data_rate_t val); +int32_t ism6hg256x_sh_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_sh_data_rate_t *val); + +typedef struct +{ + uint8_t tgt_add; + uint8_t tgt_subadd; + uint8_t tgt_len; +} ism6hg256x_sh_cfg_read_t; +int32_t ism6hg256x_sh_tgt_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, + ism6hg256x_sh_cfg_read_t *val); + +int32_t ism6hg256x_sh_status_get(const stmdev_ctx_t *ctx, + ism6hg256x_status_controller_t *val); + +int32_t ism6hg256x_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_PAD_LOW_STRENGTH = 0x1, + ISM6HG256X_PAD_MIDDLE_STRENGTH = 0x2, + ISM6HG256X_PAD_HIGH_STRENGTH = 0x4, +} ism6hg256x_pad_strength_t; +int32_t ism6hg256x_pad_strength_set(const stmdev_ctx_t *ctx, ism6hg256x_pad_strength_t val); +int32_t ism6hg256x_pad_strength_get(const stmdev_ctx_t *ctx, ism6hg256x_pad_strength_t *val); + +typedef enum +{ + ISM6HG256X_SPI_4_WIRE = 0x0, + ISM6HG256X_SPI_3_WIRE = 0x1, +} ism6hg256x_spi_mode_t; +int32_t ism6hg256x_spi_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_spi_mode_t val); +int32_t ism6hg256x_spi_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_spi_mode_t *val); + +int32_t ism6hg256x_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_if2_spi_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_spi_mode_t val); +int32_t ism6hg256x_if2_spi_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_spi_mode_t *val); + +int32_t ism6hg256x_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t step_counter_enable : 1; + uint8_t false_step_rej : 1; +} ism6hg256x_stpcnt_mode_t; +int32_t ism6hg256x_stpcnt_mode_set(const stmdev_ctx_t *ctx, + ism6hg256x_stpcnt_mode_t val); +int32_t ism6hg256x_stpcnt_mode_get(const stmdev_ctx_t *ctx, + ism6hg256x_stpcnt_mode_t *val); + +int32_t ism6hg256x_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t ism6hg256x_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism6hg256x_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t ism6hg256x_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_sflp_game_rotation_reset(const stmdev_ctx_t *ctx, uint8_t val); + +typedef struct +{ + float_t gbias_x; /* dps */ + float_t gbias_y; /* dps */ + float_t gbias_z; /* dps */ +} ism6hg256x_sflp_gbias_t; +int32_t ism6hg256x_sflp_game_gbias_set(const stmdev_ctx_t *ctx, + ism6hg256x_sflp_gbias_t *val); + +typedef struct +{ + float_t quat_w; + float_t quat_x; + float_t quat_y; + float_t quat_z; +} ism6hg256x_quaternion_t; +int32_t ism6hg256x_sflp_quaternion_get(const stmdev_ctx_t *ctx, ism6hg256x_quaternion_t *quat); + +typedef enum +{ + ISM6HG256X_SFLP_15Hz = 0x0, + ISM6HG256X_SFLP_30Hz = 0x1, + ISM6HG256X_SFLP_60Hz = 0x2, + ISM6HG256X_SFLP_120Hz = 0x3, + ISM6HG256X_SFLP_240Hz = 0x4, + ISM6HG256X_SFLP_480Hz = 0x5, +} ism6hg256x_sflp_data_rate_t; +int32_t ism6hg256x_sflp_data_rate_set(const stmdev_ctx_t *ctx, + ism6hg256x_sflp_data_rate_t val); +int32_t ism6hg256x_sflp_data_rate_get(const stmdev_ctx_t *ctx, + ism6hg256x_sflp_data_rate_t *val); + +typedef struct +{ + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; +} ism6hg256x_tap_detection_t; +int32_t ism6hg256x_tap_detection_set(const stmdev_ctx_t *ctx, + ism6hg256x_tap_detection_t val); +int32_t ism6hg256x_tap_detection_get(const stmdev_ctx_t *ctx, + ism6hg256x_tap_detection_t *val); + +typedef struct +{ + uint8_t x : 5; + uint8_t y : 5; + uint8_t z : 5; +} ism6hg256x_tap_thresholds_t; +int32_t ism6hg256x_tap_thresholds_set(const stmdev_ctx_t *ctx, + ism6hg256x_tap_thresholds_t val); +int32_t ism6hg256x_tap_thresholds_get(const stmdev_ctx_t *ctx, + ism6hg256x_tap_thresholds_t *val); + +typedef enum +{ + ISM6HG256X_XYZ = 0x0, + ISM6HG256X_YXZ = 0x1, + ISM6HG256X_XZY = 0x2, + ISM6HG256X_ZYX = 0x3, + ISM6HG256X_YZX = 0x5, + ISM6HG256X_ZXY = 0x6, +} ism6hg256x_tap_axis_priority_t; +int32_t ism6hg256x_tap_axis_priority_set(const stmdev_ctx_t *ctx, + ism6hg256x_tap_axis_priority_t val); +int32_t ism6hg256x_tap_axis_priority_get(const stmdev_ctx_t *ctx, + ism6hg256x_tap_axis_priority_t *val); + +typedef struct +{ + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t tap_gap : 4; +} ism6hg256x_tap_time_windows_t; +int32_t ism6hg256x_tap_time_windows_set(const stmdev_ctx_t *ctx, + ism6hg256x_tap_time_windows_t val); +int32_t ism6hg256x_tap_time_windows_get(const stmdev_ctx_t *ctx, + ism6hg256x_tap_time_windows_t *val); + +typedef enum +{ + ISM6HG256X_ONLY_SINGLE = 0x0, + ISM6HG256X_BOTH_SINGLE_DOUBLE = 0x1, +} ism6hg256x_tap_mode_t; +int32_t ism6hg256x_tap_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_tap_mode_t val); +int32_t ism6hg256x_tap_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_tap_mode_t *val); + +int32_t ism6hg256x_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism6hg256x_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); + +int32_t ism6hg256x_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism6hg256x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM6HG256X_XL_AND_GY_NOT_AFFECTED = 0x0, + ISM6HG256X_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, + ISM6HG256X_XL_LOW_POWER_GY_SLEEP = 0x2, + ISM6HG256X_XL_LOW_POWER_GY_POWER_DOWN = 0x3, +} ism6hg256x_act_mode_t; +int32_t ism6hg256x_act_mode_set(const stmdev_ctx_t *ctx, ism6hg256x_act_mode_t val); +int32_t ism6hg256x_act_mode_get(const stmdev_ctx_t *ctx, ism6hg256x_act_mode_t *val); + +typedef enum +{ + ISM6HG256X_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, + ISM6HG256X_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, + ISM6HG256X_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, + ISM6HG256X_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, +} ism6hg256x_act_from_sleep_to_act_dur_t; +int32_t ism6hg256x_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, + ism6hg256x_act_from_sleep_to_act_dur_t val); +int32_t ism6hg256x_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, + ism6hg256x_act_from_sleep_to_act_dur_t *val); + +typedef enum +{ + ISM6HG256X_1Hz875 = 0x0, + ISM6HG256X_15Hz = 0x1, + ISM6HG256X_30Hz = 0x2, + ISM6HG256X_60Hz = 0x3, +} ism6hg256x_act_sleep_xl_odr_t; +int32_t ism6hg256x_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, + ism6hg256x_act_sleep_xl_odr_t val); +int32_t ism6hg256x_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, + ism6hg256x_act_sleep_xl_odr_t *val); + +typedef struct +{ + ism6hg256x_inactivity_dur_t inactivity_cfg; + uint8_t inactivity_ths; + uint8_t threshold; + uint8_t duration; +} ism6hg256x_act_thresholds_t; +int32_t ism6hg256x_act_thresholds_set(const stmdev_ctx_t *ctx, + ism6hg256x_act_thresholds_t *val); +int32_t ism6hg256x_act_thresholds_get(const stmdev_ctx_t *ctx, + ism6hg256x_act_thresholds_t *val); + +typedef struct +{ + uint8_t shock : 2; + uint8_t quiet : 4; +} ism6hg256x_act_wkup_time_windows_t; +int32_t ism6hg256x_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, + ism6hg256x_act_wkup_time_windows_t val); +int32_t ism6hg256x_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, + ism6hg256x_act_wkup_time_windows_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /*ISM6HG256X_DRIVER_H */ diff --git a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c index ed46a14..d464547 100644 --- a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c +++ b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -169,9 +168,13 @@ int32_t l3gd20h_gy_axis_get(const stmdev_ctx_t *ctx, l3gd20h_gy_axis_t *val) l3gd20h_ctrl1_t ctrl1; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1); - val->xen = ctrl1.xen; - val->yen = ctrl1.yen; - val->zen = ctrl1.zen; + + if (ret == 0) + { + val->xen = ctrl1.xen; + val->yen = ctrl1.yen; + val->zen = ctrl1.zen; + } return ret; } @@ -228,11 +231,9 @@ int32_t l3gd20h_gy_data_rate_get(const stmdev_ctx_t *ctx, l3gd20h_ctrl1_t ctrl1; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1); + ret += l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1); - if (ret == 0) - { - ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1); - } + if (ret != 0) { return ret; } switch ((ctrl1.pd << 7) + (low_odr.low_odr << 4) + ctrl1.dr) { @@ -315,6 +316,8 @@ int32_t l3gd20h_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) { return ret; } + switch (ctrl4.fs) { case L3GD20H_245dps: @@ -368,6 +371,9 @@ int32_t l3gd20h_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) l3gd20h_ctrl4_t ctrl4; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret != 0) { return ret; } + *val = ctrl4.bdu; return ret; @@ -386,6 +392,9 @@ int32_t l3gd20h_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, l3gd20h_status_t status; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.zyxda; return ret; @@ -405,7 +414,7 @@ int32_t l3gd20h_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers together - * express a 16-bit word in two’s complement..[get] + * express a 16-bit word in two's complement..[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores the data read.(ptr) @@ -422,7 +431,7 @@ int32_t l3gd20h_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) /** * @brief Angular rate sensor. The value is expressed as a 16-bit - * word in two’s complement..[get] + * word in two's complement..[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores the data read.(ptr) @@ -434,6 +443,8 @@ int32_t l3gd20h_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[6]; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_OUT_X_L, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -511,6 +522,8 @@ int32_t l3gd20h_dev_data_format_get(const stmdev_ctx_t *ctx, int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) { return ret; } + switch (ctrl4.ble) { case L3GD20H_LSB_LOW_ADDRESS: @@ -565,6 +578,9 @@ int32_t l3gd20h_dev_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) l3gd20h_ctrl5_t ctrl5; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1); + + if (ret != 0) { return ret; } + *val = ctrl5.boot; return ret; @@ -583,6 +599,9 @@ int32_t l3gd20h_dev_status_get(const stmdev_ctx_t *ctx, l3gd20h_status_t status; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + val->xda = status.xda; val->yda = status.yda; val->zda = status.zda; @@ -631,6 +650,9 @@ int32_t l3gd20h_dev_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) l3gd20h_low_odr_t low_odr; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1); + + if (ret != 0) { return ret; } + *val = low_odr.sw_res; return ret; @@ -688,11 +710,9 @@ int32_t l3gd20h_gy_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, l3gd20h_ctrl1_t ctrl1; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL1, (uint8_t *)&ctrl1, 1); + ret += l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1); - if (ret == 0) - { - ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1); - } + if (ret != 0) { return ret; } switch ((low_odr.low_odr << 7) + (ctrl1.dr << 4) + ctrl1.bw) { @@ -792,10 +812,7 @@ int32_t l3gd20h_gy_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1); - if (ret == 0) - { - ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1); - } + if (ret != 0) { return ret; } switch ((ctrl2.hpm << 4) + ctrl2.hpcf) { @@ -895,6 +912,8 @@ int32_t l3gd20h_gy_filter_out_path_get(const stmdev_ctx_t *ctx, int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) { return ret; } + switch ((ctrl5.hpen << 4) + ctrl5.out_sel) { case L3GD20H_LPF1_OUT: @@ -962,6 +981,8 @@ int32_t l3gd20h_gy_filter_int_path_get(const stmdev_ctx_t *ctx, ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) { return ret; } + switch ((ctrl5.hpen << 4) + ctrl5.ig_sel) { case L3GD20H_LPF1_INT: @@ -1072,6 +1093,8 @@ int32_t l3gd20h_spi_mode_get(const stmdev_ctx_t *ctx, l3gd20h_sim_t *val) int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) { return ret; } + switch (ctrl4.sim) { case L3GD20H_SPI_4_WIRE: @@ -1129,6 +1152,8 @@ int32_t l3gd20h_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_LOW_ODR, (uint8_t *)&low_odr, 1); + if (ret != 0) { return ret; } + switch (low_odr.i2c_dis) { case L3GD20H_I2C_ENABLE: @@ -1199,6 +1224,9 @@ int32_t l3gd20h_pin_int2_route_get(const stmdev_ctx_t *ctx, l3gd20h_ctrl3_t ctrl3; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret != 0) { return ret; } + val->int2_empty = ctrl3.int2_empty; val->int2_orun = ctrl3.int2_orun; val->int2_fth = ctrl3.int2_fth; @@ -1244,6 +1272,8 @@ int32_t l3gd20h_pin_mode_get(const stmdev_ctx_t *ctx, l3gd20h_pp_od_t *val) int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) { return ret; } + switch (ctrl3.pp_od) { case L3GD20H_PUSH_PULL: @@ -1313,6 +1343,8 @@ int32_t l3gd20h_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) { return ret; } + switch (ctrl3.h_lactive) { case L3GD20H_ACTIVE_HIGH: @@ -1370,6 +1402,9 @@ int32_t l3gd20h_pin_int1_route_get(const stmdev_ctx_t *ctx, l3gd20h_ctrl3_t ctrl3; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret != 0) { return ret; } + val->int1_boot = ctrl3.int1_boot; val->int1_ig = ctrl3.int1_ig; @@ -1416,6 +1451,8 @@ int32_t l3gd20h_pin_notification_get(const stmdev_ctx_t *ctx, ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1); + if (ret != 0) { return ret; } + switch (ig_cfg.lir) { case L3GD20H_INT_PULSED: @@ -1473,6 +1510,8 @@ int32_t l3gd20h_pin_logic_get(const stmdev_ctx_t *ctx, int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1); + if (ret != 0) { return ret; } + switch (ig_cfg.and_or) { case L3GD20H_LOGIC_OR: @@ -1550,6 +1589,9 @@ int32_t l3gd20h_gy_trshld_axis_get(const stmdev_ctx_t *ctx, int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_IG_CFG, (uint8_t *)&ig_cfg, 1); + + if (ret != 0) { return ret; } + val->xlie = ig_cfg.xlie; val->xhie = ig_cfg.xhie; val->ylie = ig_cfg.ylie; @@ -1574,6 +1616,9 @@ int32_t l3gd20h_gy_trshld_src_get(const stmdev_ctx_t *ctx, l3gd20h_ig_src_t ig_src; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_IG_SRC, (uint8_t *)&ig_src, 1); + + if (ret != 0) { return ret; } + val->xl = ig_src.xl; val->xh = ig_src.xh; val->yl = ig_src.yl; @@ -1638,6 +1683,9 @@ int32_t l3gd20h_gy_trshld_x_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1); + + if (ret != 0) { return ret; } + *val = ig_ths_xh.thsx; *val = *val / 256U; *val += ig_ths_xl.thsx; @@ -1684,6 +1732,8 @@ int32_t l3gd20h_gy_trshld_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_XH, (uint8_t *)&ig_ths_xh, 1); + if (ret != 0) { return ret; } + switch (ig_ths_xh.dcrm) { case L3GD20H_RESET_MODE: @@ -1755,6 +1805,9 @@ int32_t l3gd20h_gy_trshld_y_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_YH, (uint8_t *)&ig_ths_yh, 1); + + if (ret != 0) { return ret; } + *val = ig_ths_yh.thsy; *val = *val / 256U; *val += ig_ths_yl.thsy; @@ -1816,6 +1869,9 @@ int32_t l3gd20h_gy_trshld_z_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = l3gd20h_read_reg(ctx, L3GD20H_IG_THS_ZH, (uint8_t *)&ig_ths_zh, 1); + + if (ret != 0) { return ret; } + *val = ig_ths_zh.thsz; *val = *val / 256U; *val += ig_ths_zh.thsz; @@ -1876,6 +1932,9 @@ int32_t l3gd20h_gy_trshld_min_sample_get(const stmdev_ctx_t *ctx, int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_IG_DURATION, (uint8_t *)&ig_duration, 1); + + if (ret != 0) { return ret; } + *val = ig_duration.d; return ret; @@ -1929,6 +1988,9 @@ int32_t l3gd20h_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) l3gd20h_ctrl5_t ctrl5; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1); + + if (ret != 0) { return ret; } + *val = ctrl5.stoponfth; return ret; @@ -1983,11 +2045,9 @@ int32_t l3gd20h_fifo_mode_get(const stmdev_ctx_t *ctx, l3gd20h_fifo_ctrl_t fifo_ctrl; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + ret += l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1); - if (ret == 0) - { - ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL5, (uint8_t *)&ctrl5, 1); - } + if (ret != 0) { return ret; } switch ((ctrl5.fifo_en << 4) + fifo_ctrl.fm) { @@ -2058,6 +2118,9 @@ int32_t l3gd20h_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) l3gd20h_fifo_ctrl_t fifo_ctrl; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl.fth; return ret; @@ -2077,6 +2140,9 @@ int32_t l3gd20h_fifo_src_get(const stmdev_ctx_t *ctx, l3gd20h_fifo_src_t fifo_src; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t *)&fifo_src, 1); + + if (ret != 0) { return ret; } + val->fss = fifo_src.fss; val->empty = fifo_src.empty; val->ovrn = fifo_src.ovrn; @@ -2098,6 +2164,9 @@ int32_t l3gd20h_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) l3gd20h_fifo_src_t fifo_src; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t *)&fifo_src, 1); + + if (ret != 0) { return ret; } + *val = fifo_src.fss; return ret; @@ -2116,6 +2185,9 @@ int32_t l3gd20h_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) l3gd20h_fifo_src_t fifo_src; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t *)&fifo_src, 1); + + if (ret != 0) { return ret; } + *val = fifo_src.fss; return ret; @@ -2134,6 +2206,9 @@ int32_t l3gd20h_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) l3gd20h_fifo_src_t fifo_src; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_FIFO_SRC, (uint8_t *)&fifo_src, 1); + + if (ret != 0) { return ret; } + *val = fifo_src.fth; return ret; @@ -2201,11 +2276,9 @@ int32_t l3gd20h_den_mode_get(const stmdev_ctx_t *ctx, l3gd20h_den_md_t *val) l3gd20h_ctrl4_t ctrl4; int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1); + ret += l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1); - if (ret == 0) - { - ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL2, (uint8_t *)&ctrl2, 1); - } + if (ret != 0) { return ret; } switch ((ctrl2.lvlen << 2) + (ctrl2.extren << 1) + ctrl4.impen) { @@ -2283,6 +2356,8 @@ int32_t l3gd20h_gy_self_test_get(const stmdev_ctx_t *ctx, l3gd20h_st_t *val) int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) { return ret; } + switch (ctrl4.st) { case L3GD20H_ST_DISABLE: @@ -2314,5 +2389,3 @@ int32_t l3gd20h_gy_self_test_get(const stmdev_ctx_t *ctx, l3gd20h_st_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h index 0d98c12..78b0eb7 100644 --- a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h +++ b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -889,5 +891,3 @@ int32_t l3gd20h_gy_self_test_get(const stmdev_ctx_t *ctx, #endif #endif /* L3GD20H_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c index 4e996e4..d929c07 100644 --- a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c +++ b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -236,12 +235,15 @@ int32_t lis25ba_bus_mode_get(const stmdev_ctx_t *ctx, bytecpy((uint8_t *)&tdm_cmax_l, ®[1]); } - val->tdm.en = ~tdm_ctrl_reg.tdm_pd; - val->tdm.clk_pol = tdm_ctrl_reg.data_valid; - val->tdm.clk_edge = tdm_ctrl_reg.delayed; - val->tdm.mapping = tdm_ctrl_reg.wclk_fq; - val->tdm.cmax = tdm_cmax_h.tdm_cmax * 256U; - val->tdm.cmax += tdm_cmax_l.tdm_cmax; + if (ret == 0) + { + val->tdm.en = ~tdm_ctrl_reg.tdm_pd; + val->tdm.clk_pol = tdm_ctrl_reg.data_valid; + val->tdm.clk_edge = tdm_ctrl_reg.delayed; + val->tdm.mapping = tdm_ctrl_reg.wclk_fq; + val->tdm.cmax = tdm_cmax_h.tdm_cmax * 256U; + val->tdm.cmax += tdm_cmax_l.tdm_cmax; + } return ret; } @@ -324,6 +326,8 @@ int32_t lis25ba_mode_get(const stmdev_ctx_t *ctx, lis25ba_md_t *val) bytecpy((uint8_t *)&axes_ctrl_reg, ®[1]); } + if (ret != 0) { return ret; } + val->xl.axis.x = axes_ctrl_reg.axisx_en; val->xl.axis.y = axes_ctrl_reg.axisy_en; val->xl.axis.z = axes_ctrl_reg.axisz_en; @@ -435,7 +439,11 @@ int32_t lis25ba_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis25ba_read_reg(ctx, LIS25BA_TEST_REG, (uint8_t *)&test_reg, 1); - *val = test_reg.st; + + if (ret == 0) + { + *val = test_reg.st; + } return ret; } @@ -449,5 +457,3 @@ int32_t lis25ba_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h index fdffb76..de94d94 100644 --- a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h +++ b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -388,5 +390,3 @@ int32_t lis25ba_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /*LIS25BA_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c index b8d62f7..3bf68a1 100644 --- a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c +++ b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -168,6 +167,9 @@ int32_t lis2de12_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG_AUX, (uint8_t *)&status_reg_aux, 1); + + if (ret != 0) { return ret; } + *val = status_reg_aux.tda; return ret; @@ -187,6 +189,9 @@ int32_t lis2de12_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG_AUX, (uint8_t *)&status_reg_aux, 1); + + if (ret != 0) { return ret; } + *val = status_reg_aux.tor; return ret; @@ -205,6 +210,9 @@ int32_t lis2de12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2de12_read_reg(ctx, LIS2DE12_OUT_TEMP_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -254,6 +262,8 @@ int32_t lis2de12_temperature_meas_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_TEMP_CFG_REG, (uint8_t *)&temp_cfg_reg, 1); + if (ret != 0) { return ret; } + switch (temp_cfg_reg.temp_en) { case LIS2DE12_TEMP_DISABLE: @@ -315,6 +325,8 @@ int32_t lis2de12_data_rate_get(const stmdev_ctx_t *ctx, lis2de12_odr_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1.odr) { case LIS2DE12_POWER_DOWN: @@ -410,6 +422,9 @@ int32_t lis2de12_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg2.fds; return ret; @@ -471,6 +486,8 @@ int32_t lis2de12_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hpcf) { case LIS2DE12_AGGRESSIVE: @@ -541,6 +558,8 @@ int32_t lis2de12_high_pass_mode_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hpm) { case LIS2DE12_NORMAL_WITH_RST: @@ -609,6 +628,8 @@ int32_t lis2de12_full_scale_get(const stmdev_ctx_t *ctx, lis2de12_fs_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.fs) { case LIS2DE12_2g: @@ -677,6 +698,9 @@ int32_t lis2de12_block_data_update_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg4.bdu; return ret; @@ -734,6 +758,9 @@ int32_t lis2de12_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -753,6 +780,9 @@ int32_t lis2de12_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.zyxor; return ret; @@ -771,6 +801,9 @@ int32_t lis2de12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_READ_START, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -850,6 +883,8 @@ int32_t lis2de12_self_test_get(const stmdev_ctx_t *ctx, lis2de12_st_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.st) { case LIS2DE12_ST_DISABLE: @@ -913,6 +948,9 @@ int32_t lis2de12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.boot; return ret; @@ -1045,6 +1083,9 @@ int32_t lis2de12_int1_gen_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_THS, (uint8_t *)&int1_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int1_ths.ths; return ret; @@ -1094,6 +1135,9 @@ int32_t lis2de12_int1_gen_duration_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_INT1_DURATION, (uint8_t *)&int1_duration, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int1_duration.d; return ret; @@ -1208,6 +1252,9 @@ int32_t lis2de12_int2_gen_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_THS, (uint8_t *)&int2_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int2_ths.ths; return ret; @@ -1257,6 +1304,9 @@ int32_t lis2de12_int2_gen_duration_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_INT2_DURATION, (uint8_t *)&int2_duration, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int2_duration.d; return ret; @@ -1318,6 +1368,8 @@ int32_t lis2de12_high_pass_int_conf_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hp) { case LIS2DE12_DISC_FROM_INT_GENERATOR: @@ -1441,6 +1493,9 @@ int32_t lis2de12_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.d4d_int2; return ret; @@ -1494,6 +1549,8 @@ int32_t lis2de12_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg5.lir_int2) { case LIS2DE12_INT2_PULSED: @@ -1557,6 +1614,9 @@ int32_t lis2de12_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.d4d_int1; return ret; @@ -1608,6 +1668,8 @@ int32_t lis2de12_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg5.lir_int1) { case LIS2DE12_INT1_PULSED: @@ -1714,6 +1776,9 @@ int32_t lis2de12_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.fifo_en; return ret; @@ -1760,6 +1825,9 @@ int32_t lis2de12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_ctrl_reg.fth; return ret; @@ -1809,6 +1877,8 @@ int32_t lis2de12_fifo_trigger_event_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl_reg.tr) { case LIS2DE12_INT1_GEN: @@ -1869,6 +1939,8 @@ int32_t lis2de12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2de12_fm_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl_reg.fm) { case LIS2DE12_BYPASS_MODE: @@ -1927,6 +1999,9 @@ int32_t lis2de12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.fss; return ret; @@ -1946,6 +2021,9 @@ int32_t lis2de12_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.empty; return ret; @@ -1965,6 +2043,9 @@ int32_t lis2de12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.ovrn_fifo; return ret; @@ -1984,6 +2065,9 @@ int32_t lis2de12_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.wtm; return ret; @@ -2096,6 +2180,9 @@ int32_t lis2de12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS, (uint8_t *)&click_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)click_ths.ths; return ret; @@ -2151,6 +2238,8 @@ int32_t lis2de12_tap_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_CLICK_THS, (uint8_t *)&click_ths, 1); + if (ret != 0) { return ret; } + switch (click_ths.lir_click) { case LIS2DE12_TAP_PULSED: @@ -2214,6 +2303,9 @@ int32_t lis2de12_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LIMIT, (uint8_t *)&time_limit, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)time_limit.tli; return ret; @@ -2266,6 +2358,9 @@ int32_t lis2de12_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_LATENCY, (uint8_t *)&time_latency, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)time_latency.tla; return ret; @@ -2320,6 +2415,9 @@ int32_t lis2de12_double_tap_timeout_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_TIME_WINDOW, (uint8_t *)&time_window, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)time_window.tw; return ret; @@ -2380,6 +2478,9 @@ int32_t lis2de12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_THS, (uint8_t *)&act_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)act_ths.acth; return ret; @@ -2425,6 +2526,9 @@ int32_t lis2de12_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2de12_read_reg(ctx, LIS2DE12_ACT_DUR, (uint8_t *)&act_dur, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)act_dur.actd; return ret; @@ -2487,6 +2591,8 @@ int32_t lis2de12_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG0, (uint8_t *)&ctrl_reg0, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg0.sdo_pu_disc) { case LIS2DE12_PULL_UP_DISCONNECT: @@ -2547,6 +2653,8 @@ int32_t lis2de12_spi_mode_get(const stmdev_ctx_t *ctx, lis2de12_sim_t *val) ret = lis2de12_read_reg(ctx, LIS2DE12_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.sim) { case LIS2DE12_SPI_4_WIRE: @@ -2574,5 +2682,3 @@ int32_t lis2de12_spi_mode_get(const stmdev_ctx_t *ctx, lis2de12_sim_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h index 02a3a0f..ad3864c 100644 --- a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h +++ b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1035,5 +1037,3 @@ int32_t lis2de12_spi_mode_get(const stmdev_ctx_t *ctx, lis2de12_sim_t *val); #endif #endif /* LIS2DE12_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c index e56befd..efbcd93 100644 --- a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c +++ b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -218,6 +217,9 @@ int32_t lis2dh12_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX, (uint8_t *)&status_reg_aux, 1); + + if (ret != 0) { return ret; } + *val = status_reg_aux.tda; return ret; @@ -237,6 +239,9 @@ int32_t lis2dh12_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX, (uint8_t *)&status_reg_aux, 1); + + if (ret != 0) { return ret; } + *val = status_reg_aux.tor; return ret; @@ -255,6 +260,9 @@ int32_t lis2dh12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2dh12_read_reg(ctx, LIS2DH12_OUT_TEMP_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -304,6 +312,8 @@ int32_t lis2dh12_temperature_meas_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_TEMP_CFG_REG, (uint8_t *)&temp_cfg_reg, 1); + if (ret != 0) { return ret; } + switch (temp_cfg_reg.temp_en) { case LIS2DH12_TEMP_DISABLE: @@ -397,12 +407,11 @@ int32_t lis2dh12_operating_mode_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + ret += lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, + (uint8_t *)&ctrl_reg4, 1); if (ret == 0) { - ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - if (ctrl_reg1.lpen == PROPERTY_ENABLE) { *val = LIS2DH12_LP_8bit; @@ -464,6 +473,8 @@ int32_t lis2dh12_data_rate_get(const stmdev_ctx_t *ctx, lis2dh12_odr_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1.odr) { case LIS2DH12_POWER_DOWN: @@ -559,6 +570,9 @@ int32_t lis2dh12_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg2.fds; return ret; @@ -620,6 +634,8 @@ int32_t lis2dh12_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hpcf) { case LIS2DH12_AGGRESSIVE: @@ -690,6 +706,8 @@ int32_t lis2dh12_high_pass_mode_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hpm) { case LIS2DH12_NORMAL_WITH_RST: @@ -758,6 +776,8 @@ int32_t lis2dh12_full_scale_get(const stmdev_ctx_t *ctx, lis2dh12_fs_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.fs) { case LIS2DH12_2g: @@ -826,6 +846,9 @@ int32_t lis2dh12_block_data_update_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg4.bdu; return ret; @@ -883,6 +906,9 @@ int32_t lis2dh12_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -902,6 +928,9 @@ int32_t lis2dh12_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.zyxor; return ret; @@ -920,6 +949,9 @@ int32_t lis2dh12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2dh12_read_reg(ctx, LIS2DH12_OUT_X_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -999,6 +1031,8 @@ int32_t lis2dh12_self_test_get(const stmdev_ctx_t *ctx, lis2dh12_st_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.st) { case LIS2DH12_ST_DISABLE: @@ -1065,6 +1099,8 @@ int32_t lis2dh12_data_format_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.ble) { case LIS2DH12_LSB_AT_LOW_ADD: @@ -1124,6 +1160,9 @@ int32_t lis2dh12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.boot; return ret; @@ -1256,6 +1295,9 @@ int32_t lis2dh12_int1_gen_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_THS, (uint8_t *)&int1_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int1_ths.ths; return ret; @@ -1305,6 +1347,9 @@ int32_t lis2dh12_int1_gen_duration_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_DURATION, (uint8_t *)&int1_duration, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int1_duration.d; return ret; @@ -1419,6 +1464,9 @@ int32_t lis2dh12_int2_gen_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_THS, (uint8_t *)&int2_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int2_ths.ths; return ret; @@ -1468,6 +1516,9 @@ int32_t lis2dh12_int2_gen_duration_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_DURATION, (uint8_t *)&int2_duration, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int2_duration.d; return ret; @@ -1529,6 +1580,8 @@ int32_t lis2dh12_high_pass_int_conf_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hp) { case LIS2DH12_DISC_FROM_INT_GENERATOR: @@ -1652,6 +1705,9 @@ int32_t lis2dh12_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.d4d_int2; return ret; @@ -1705,6 +1761,8 @@ int32_t lis2dh12_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg5.lir_int2) { case LIS2DH12_INT2_PULSED: @@ -1768,6 +1826,9 @@ int32_t lis2dh12_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.d4d_int1; return ret; @@ -1819,6 +1880,8 @@ int32_t lis2dh12_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg5.lir_int1) { case LIS2DH12_INT1_PULSED: @@ -1925,6 +1988,9 @@ int32_t lis2dh12_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.fifo_en; return ret; @@ -1971,6 +2037,9 @@ int32_t lis2dh12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_ctrl_reg.fth; return ret; @@ -2020,6 +2089,8 @@ int32_t lis2dh12_fifo_trigger_event_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl_reg.tr) { case LIS2DH12_INT1_GEN: @@ -2080,6 +2151,8 @@ int32_t lis2dh12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dh12_fm_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl_reg.fm) { case LIS2DH12_BYPASS_MODE: @@ -2138,6 +2211,9 @@ int32_t lis2dh12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.fss; return ret; @@ -2157,6 +2233,9 @@ int32_t lis2dh12_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.empty; return ret; @@ -2176,6 +2255,9 @@ int32_t lis2dh12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.ovrn_fifo; return ret; @@ -2195,6 +2277,9 @@ int32_t lis2dh12_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.wtm; return ret; @@ -2307,6 +2392,9 @@ int32_t lis2dh12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t *)&click_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)click_ths.ths; return ret; @@ -2362,6 +2450,8 @@ int32_t lis2dh12_tap_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, (uint8_t *)&click_ths, 1); + if (ret != 0) { return ret; } + switch (click_ths.lir_click) { case LIS2DH12_TAP_PULSED: @@ -2425,6 +2515,9 @@ int32_t lis2dh12_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LIMIT, (uint8_t *)&time_limit, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)time_limit.tli; return ret; @@ -2477,6 +2570,9 @@ int32_t lis2dh12_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LATENCY, (uint8_t *)&time_latency, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)time_latency.tla; return ret; @@ -2531,6 +2627,9 @@ int32_t lis2dh12_double_tap_timeout_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_WINDOW, (uint8_t *)&time_window, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)time_window.tw; return ret; @@ -2591,6 +2690,9 @@ int32_t lis2dh12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_THS, (uint8_t *)&act_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)act_ths.acth; return ret; @@ -2636,6 +2738,9 @@ int32_t lis2dh12_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t *)&act_dur, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)act_dur.actd; return ret; @@ -2698,6 +2803,8 @@ int32_t lis2dh12_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG0, (uint8_t *)&ctrl_reg0, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg0.sdo_pu_disc) { case LIS2DH12_PULL_UP_DISCONNECT: @@ -2758,6 +2865,8 @@ int32_t lis2dh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dh12_sim_t *val) ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.sim) { case LIS2DH12_SPI_4_WIRE: @@ -2786,5 +2895,3 @@ int32_t lis2dh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dh12_sim_t *val) * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h index eb8d5ce..267e75f 100644 --- a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h +++ b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -121,6 +120,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1068,5 +1070,3 @@ int32_t lis2dh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dh12_sim_t *val); #endif #endif /* LIS2DH12_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c index 96a8552..5141a9e 100644 --- a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c +++ b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -232,6 +231,9 @@ int32_t lis2ds12_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret != 0) { return ret; } + *val = ctrl1.bdu; return ret; @@ -278,6 +280,8 @@ int32_t lis2ds12_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) { return ret; } + switch (ctrl1.fs) { case LIS2DS12_2g: @@ -346,6 +350,8 @@ int32_t lis2ds12_xl_data_rate_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) { return ret; } + switch ((ctrl1.hf_odr << 4) + ctrl1.odr) { case LIS2DS12_XL_ODR_OFF: @@ -465,6 +471,9 @@ int32_t lis2ds12_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.drdy; return ret; @@ -502,7 +511,7 @@ int32_t lis2ds12_acceleration_module_raw_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers together - * express a 16-bit word in two’s complement.[get] + * express a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions.(ptr) * @param buff buffer that stores data read.(ptr) @@ -520,7 +529,7 @@ int32_t lis2ds12_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) /** * @brief Linear acceleration output register. The value is expressed as a - * 16-bit word in two’s complement.[get] + * 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions.(ptr) * @param buff buffer that stores data read.(ptr) @@ -533,6 +542,9 @@ int32_t lis2ds12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_OUT_X_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -557,6 +569,9 @@ int32_t lis2ds12_number_of_steps_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -632,6 +647,9 @@ int32_t lis2ds12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1); + + if (ret != 0) { return ret; } + *val = ctrl2.if_add_inc; return ret; @@ -721,6 +739,9 @@ int32_t lis2ds12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1); + + if (ret != 0) { return ret; } + *val = ctrl2.soft_reset; return ret; @@ -764,6 +785,9 @@ int32_t lis2ds12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1); + + if (ret != 0) { return ret; } + *val = ctrl2.boot; return ret; @@ -810,6 +834,8 @@ int32_t lis2ds12_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) { return ret; } + switch (ctrl3.st) { case LIS2DS12_XL_ST_DISABLE: @@ -873,6 +899,8 @@ int32_t lis2ds12_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) { return ret; } + switch (ctrl5.drdy_pulsed) { case LIS2DS12_DRDY_LATCHED: @@ -945,6 +973,8 @@ int32_t lis2ds12_xl_hp_path_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) { return ret; } + switch (ctrl2.fds_slope) { case LIS2DS12_HP_INTERNAL_ONLY: @@ -1015,6 +1045,8 @@ int32_t lis2ds12_spi_mode_get(const stmdev_ctx_t *ctx, lis2ds12_sim_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) { return ret; } + switch (ctrl2.sim) { case LIS2DS12_SPI_4_WIRE: @@ -1074,6 +1106,8 @@ int32_t lis2ds12_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) { return ret; } + switch (ctrl2.i2c_disable) { case LIS2DS12_I2C_ENABLE: @@ -1136,6 +1170,8 @@ int32_t lis2ds12_cs_mode_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl.if_cs_pu_dis) { case LIS2DS12_PULL_UP_CONNECTED: @@ -1207,6 +1243,8 @@ int32_t lis2ds12_pin_mode_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) { return ret; } + switch (ctrl3.pp_od) { case LIS2DS12_PUSH_PULL: @@ -1266,6 +1304,8 @@ int32_t lis2ds12_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) { return ret; } + switch (ctrl3.h_lactive) { case LIS2DS12_ACTIVE_HIGH: @@ -1325,6 +1365,8 @@ int32_t lis2ds12_int_notification_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) { return ret; } + switch (ctrl3.lir) { case LIS2DS12_INT_PULSED: @@ -1405,6 +1447,8 @@ int32_t lis2ds12_pin_int1_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); if (ret == 0) { @@ -1416,8 +1460,7 @@ int32_t lis2ds12_pin_int1_route_get(const stmdev_ctx_t *ctx, val->int1_wu = ctrl4.int1_wu; val->int1_s_tap = ctrl4.int1_s_tap; val->int1_master_drdy = ctrl4.int1_master_drdy; - ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + val->int1_fss7 = wake_up_dur.int1_fss7; } @@ -1469,6 +1512,9 @@ int32_t lis2ds12_pin_int2_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1); + + if (ret != 0) { return ret; } + val->int2_boot = ctrl5.int2_boot; val->int2_tilt = ctrl5.int2_tilt; val->int2_sig_mot = ctrl5.int2_sig_mot; @@ -1517,6 +1563,9 @@ int32_t lis2ds12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL5, (uint8_t *)&ctrl5, 1); + + if (ret != 0) { return ret; } + *val = ctrl5.int2_on_int1; return ret; @@ -1578,6 +1627,8 @@ int32_t lis2ds12_sh_pin_mode_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t *)&func_ctrl, 1); + if (ret != 0) { return ret; } + switch (func_ctrl.tud_en) { case LIS2DS12_EXT_PULL_UP: @@ -1650,6 +1701,9 @@ int32_t lis2ds12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { return ret; } + *val = wake_up_ths.wu_ths; return ret; @@ -1696,6 +1750,9 @@ int32_t lis2ds12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + if (ret != 0) { return ret; } + *val = wake_up_dur.wu_dur; return ret; @@ -1755,6 +1812,9 @@ int32_t lis2ds12_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { return ret; } + *val = wake_up_ths.sleep_on; return ret; @@ -1801,6 +1861,9 @@ int32_t lis2ds12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + if (ret != 0) { return ret; } + *val = wake_up_dur.sleep_dur; return ret; @@ -1859,6 +1922,9 @@ int32_t lis2ds12_tap_detection_on_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret != 0) { return ret; } + *val = ctrl3.tap_z_en; return ret; @@ -1904,6 +1970,9 @@ int32_t lis2ds12_tap_detection_on_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret != 0) { return ret; } + *val = ctrl3.tap_y_en; return ret; @@ -1949,6 +2018,9 @@ int32_t lis2ds12_tap_detection_on_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret != 0) { return ret; } + *val = ctrl3.tap_x_en; return ret; @@ -1995,6 +2067,9 @@ int32_t lis2ds12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS, (uint8_t *)&tap_6d_ths, 1); + + if (ret != 0) { return ret; } + *val = tap_6d_ths.tap_ths; return ret; @@ -2046,6 +2121,9 @@ int32_t lis2ds12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1); + + if (ret != 0) { return ret; } + *val = int_dur.shock; return ret; @@ -2097,6 +2175,9 @@ int32_t lis2ds12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1); + + if (ret != 0) { return ret; } + *val = int_dur.quiet; return ret; @@ -2148,6 +2229,9 @@ int32_t lis2ds12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_INT_DUR, (uint8_t *)&int_dur, 1); + + if (ret != 0) { return ret; } + *val = int_dur.lat; return ret; @@ -2197,6 +2281,8 @@ int32_t lis2ds12_tap_mode_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) { return ret; } + switch (wake_up_ths.single_double_tap) { case LIS2DS12_ONLY_SINGLE: @@ -2290,6 +2376,8 @@ int32_t lis2ds12_6d_threshold_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS, (uint8_t *)&tap_6d_ths, 1); + if (ret != 0) { return ret; } + switch (tap_6d_ths._6d_ths) { case LIS2DS12_DEG_80: @@ -2357,6 +2445,9 @@ int32_t lis2ds12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_TAP_6D_THS, (uint8_t *)&tap_6d_ths, 1); + + if (ret != 0) { return ret; } + *val = tap_6d_ths._4d_en; return ret; @@ -2449,10 +2540,11 @@ int32_t lis2ds12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL, (uint8_t *)&free_fall, 1); + ret += lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) { - ret = lis2ds12_read_reg(ctx, LIS2DS12_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; } @@ -2500,6 +2592,9 @@ int32_t lis2ds12_ff_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_FREE_FALL, (uint8_t *)&free_fall, 1); + + if (ret != 0) { return ret; } + *val = free_fall.ff_ths; return ret; @@ -2562,6 +2657,9 @@ int32_t lis2ds12_fifo_xl_module_batch_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl.module_to_fifo; return ret; @@ -2611,6 +2709,8 @@ int32_t lis2ds12_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl.fmode) { case LIS2DS12_BYPASS_MODE: @@ -2689,6 +2789,9 @@ int32_t lis2ds12_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1); + + if (ret != 0) { return ret; } + *val = fifo_src.diff; return ret; @@ -2708,6 +2811,9 @@ int32_t lis2ds12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1); + + if (ret != 0) { return ret; } + *val = fifo_src.fifo_ovr; return ret; @@ -2727,6 +2833,9 @@ int32_t lis2ds12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1); + + if (ret != 0) { return ret; } + *val = fifo_src.fth; return ret; @@ -2747,10 +2856,10 @@ int32_t lis2ds12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_THS, (uint8_t *)&fifo_ths, 1); + ret += lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1); if (ret == 0) { - ret = lis2ds12_read_reg(ctx, LIS2DS12_FIFO_SRC, (uint8_t *)&fifo_src, 1); *val = fifo_src.diff; *val = (*val * 256U) + fifo_ths.fth; } @@ -2829,6 +2938,9 @@ int32_t lis2ds12_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS, (uint8_t *)&step_counter_minths, 1); + + if (ret != 0) { return ret; } + *val = step_counter_minths.sc_mths; return ret; @@ -2878,6 +2990,8 @@ int32_t lis2ds12_pedo_full_scale_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS, (uint8_t *)&step_counter_minths, 1); + if (ret != 0) { return ret; } + switch (step_counter_minths.pedo4g) { case LIS2DS12_PEDO_AT_2g: @@ -2937,6 +3051,9 @@ int32_t lis2ds12_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNTER_MINTHS, (uint8_t *)&step_counter_minths, 1); + + if (ret != 0) { return ret; } + *val = step_counter_minths.rst_nstep; return ret; @@ -2958,6 +3075,9 @@ int32_t lis2ds12_pedo_step_detect_flag_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CK_GATE, (uint8_t *)&func_ck_gate, 1); + + if (ret != 0) { return ret; } + *val = func_ck_gate.step_detect; return ret; @@ -3004,6 +3124,9 @@ int32_t lis2ds12_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t *)&func_ctrl, 1); + + if (ret != 0) { return ret; } + *val = func_ctrl.step_cnt_on; return ret; @@ -3038,10 +3161,7 @@ int32_t lis2ds12_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, (uint8_t *)&pedo_deb_reg, 1); } - if (ret == 0) - { - ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); - } + ret += lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); return ret; } @@ -3071,9 +3191,10 @@ int32_t lis2ds12_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = pedo_deb_reg.deb_step; - ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); } + ret += lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); + return ret; } @@ -3107,10 +3228,7 @@ int32_t lis2ds12_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&pedo_deb_reg, 1); } - if (ret == 0) - { - ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); - } + ret += lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); return ret; } @@ -3141,9 +3259,10 @@ int32_t lis2ds12_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = pedo_deb_reg.deb_time; - ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); } + ret += lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); + return ret; } @@ -3168,10 +3287,7 @@ int32_t lis2ds12_pedo_steps_period_set(const stmdev_ctx_t *ctx, ret = lis2ds12_write_reg(ctx, LIS2DS12_STEP_COUNT_DELTA, buff, 1); } - if (ret == 0) - { - ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); - } + ret += lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); return ret; } @@ -3197,10 +3313,7 @@ int32_t lis2ds12_pedo_steps_period_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_STEP_COUNT_DELTA, buff, 1); } - if (ret == 0) - { - ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); - } + ret += lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); return ret; } @@ -3234,6 +3347,9 @@ int32_t lis2ds12_motion_data_ready_flag_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CK_GATE, (uint8_t *)&func_ck_gate, 1); + + if (ret != 0) { return ret; } + *val = func_ck_gate.sig_mot_detect; return ret; @@ -3280,6 +3396,9 @@ int32_t lis2ds12_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t *)&func_ctrl, 1); + + if (ret != 0) { return ret; } + *val = func_ctrl.sign_mot_on; return ret; @@ -3315,10 +3434,7 @@ int32_t lis2ds12_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lis2ds12_write_reg(ctx, LIS2DS12_SM_THS, (uint8_t *)&sm_ths, 1); } - if (ret == 0) - { - ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); - } + ret += lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); return ret; } @@ -3350,9 +3466,10 @@ int32_t lis2ds12_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = sm_ths.sm_ths; - ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); } + ret += lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); + return ret; } @@ -3385,6 +3502,9 @@ int32_t lis2ds12_tilt_data_ready_flag_get(const stmdev_ctx_t *ctx, ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CK_GATE, (uint8_t *)&func_ck_gate, 1); + + if (ret != 0) { return ret; } + *val = func_ck_gate.tilt_int; return ret; @@ -3431,6 +3551,9 @@ int32_t lis2ds12_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t *)&func_ctrl, 1); + + if (ret != 0) { return ret; } + *val = func_ctrl.tilt_on; return ret; @@ -3490,6 +3613,9 @@ int32_t lis2ds12_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t *)&func_ctrl, 1); + + if (ret != 0) { return ret; } + *val = func_ctrl.module_on; return ret; @@ -3568,6 +3694,9 @@ int32_t lis2ds12_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_CTRL, (uint8_t *)&func_ctrl, 1); + + if (ret != 0) { return ret; } + *val = func_ctrl.master_on; return ret; @@ -3612,10 +3741,7 @@ int32_t lis2ds12_sh_cfg_write(const stmdev_ctx_t *ctx, &(val->slv_data), 1); } - if (ret == 0) - { - ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); - } + ret += lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); return ret; } @@ -3667,10 +3793,7 @@ int32_t lis2ds12_sh_slv_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); - } + ret += lis2ds12_mem_bank_set(ctx, LIS2DS12_USER_BANK); return ret; } @@ -3689,6 +3812,9 @@ int32_t lis2ds12_sh_end_op_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2ds12_read_reg(ctx, LIS2DS12_FUNC_SRC, (uint8_t *)&func_src, 1); + + if (ret != 0) { return ret; } + *val = func_src.sensorhub_end_op; return ret; @@ -3703,5 +3829,3 @@ int32_t lis2ds12_sh_end_op_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h index 312c0c3..b0db608 100644 --- a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h +++ b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1357,5 +1359,3 @@ int32_t lis2ds12_sh_end_op_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /*__LIS2DS12_DRIVER__H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c index 64a0e1a..c74da43 100644 --- a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c +++ b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -214,11 +213,10 @@ int32_t lis2dtw12_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1); + ret += lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1); if (ret == 0) { - ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1); - switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) + ctrl1.lp_mode)) { @@ -356,11 +354,10 @@ int32_t lis2dtw12_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL1, (uint8_t *) &ctrl1, 1); + ret += lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) &ctrl3, 1); if (ret == 0) { - ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) &ctrl3, 1); - switch ((ctrl3.slp_mode << 4) + ctrl1.odr) { case LIS2DTW12_XL_ODR_OFF: @@ -460,6 +457,9 @@ int32_t lis2dtw12_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.bdu; return ret; @@ -506,6 +506,8 @@ int32_t lis2dtw12_full_scale_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.fs) { case LIS2DTW12_2g: @@ -564,6 +566,9 @@ int32_t lis2dtw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_STATUS, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.drdy; return ret; @@ -589,7 +594,7 @@ int32_t lis2dtw12_all_sources_get(const stmdev_ctx_t *ctx, } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -608,7 +613,7 @@ int32_t lis2dtw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -627,7 +632,7 @@ int32_t lis2dtw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -646,7 +651,7 @@ int32_t lis2dtw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -665,7 +670,7 @@ int32_t lis2dtw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -684,7 +689,7 @@ int32_t lis2dtw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -746,6 +751,8 @@ int32_t lis2dtw12_offset_weight_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.usr_off_w) { case LIS2DTW12_LSb_977ug: @@ -778,7 +785,7 @@ int32_t lis2dtw12_offset_weight_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers - * together express a 16-bit word in two’s complement.[get] + * together express a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -791,6 +798,9 @@ int32_t lis2dtw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_OUT_T_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -799,7 +809,7 @@ int32_t lis2dtw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed as - * a 16-bit word in two’s complement.[get] + * a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -813,6 +823,9 @@ int32_t lis2dtw12_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_OUT_X_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -892,6 +905,9 @@ int32_t lis2dtw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.if_add_inc; return ret; @@ -935,6 +951,9 @@ int32_t lis2dtw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.soft_reset; return ret; @@ -978,6 +997,9 @@ int32_t lis2dtw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.boot; return ret; @@ -1023,6 +1045,8 @@ int32_t lis2dtw12_self_test_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.st) { case LIS2DTW12_XL_ST_DISABLE: @@ -1086,6 +1110,8 @@ int32_t lis2dtw12_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.drdy_pulsed) { case LIS2DTW12_DRDY_LATCHED: @@ -1172,12 +1198,11 @@ int32_t lis2dtw12_filter_path_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) &ctrl6, 1); + ret += lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, + (uint8_t *) &ctrl_reg7, 1); if (ret == 0) { - ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, - (uint8_t *) &ctrl_reg7, 1); - switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out) { case LIS2DTW12_LPF_ON_OUT: @@ -1244,6 +1269,8 @@ int32_t lis2dtw12_filter_bandwidth_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL6, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.bw_filt) { case LIS2DTW12_ODR_DIV_2: @@ -1308,6 +1335,9 @@ int32_t lis2dtw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.hp_ref_mode; return ret; @@ -1366,6 +1396,8 @@ int32_t lis2dtw12_spi_mode_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sim) { case LIS2DTW12_SPI_4_WIRE: @@ -1426,6 +1458,8 @@ int32_t lis2dtw12_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.i2c_disable) { case LIS2DTW12_I2C_ENABLE: @@ -1485,6 +1519,8 @@ int32_t lis2dtw12_cs_mode_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.cs_pu_disc) { case LIS2DTW12_PULL_UP_CONNECT: @@ -1556,6 +1592,8 @@ int32_t lis2dtw12_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.h_lactive) { case LIS2DTW12_ACTIVE_HIGH: @@ -1615,6 +1653,8 @@ int32_t lis2dtw12_int_notification_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.lir) { case LIS2DTW12_INT_PULSED: @@ -1674,6 +1714,8 @@ int32_t lis2dtw12_pin_mode_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.pp_od) { case LIS2DTW12_PUSH_PULL: @@ -1850,6 +1892,9 @@ int32_t lis2dtw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.int2_on_int1; return ret; @@ -1907,6 +1952,9 @@ int32_t lis2dtw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.wk_ths; return ret; @@ -1951,6 +1999,9 @@ int32_t lis2dtw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.wake_dur; return ret; @@ -1997,6 +2048,8 @@ int32_t lis2dtw12_wkup_feed_data_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.usr_off_on_wu) { case LIS2DTW12_HP_FEED: @@ -2089,12 +2142,11 @@ int32_t lis2dtw12_act_mode_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS, (uint8_t *) &wake_up_ths, 1); + ret += lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, + (uint8_t *) &wake_up_dur, 1); if (ret == 0) { - ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, - (uint8_t *) &wake_up_dur, 1); - switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on) { case LIS2DTW12_NO_DETECTION: @@ -2157,6 +2209,9 @@ int32_t lis2dtw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.sleep_dur; return ret; @@ -2213,6 +2268,9 @@ int32_t lis2dtw12_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_thsx; return ret; @@ -2256,6 +2314,9 @@ int32_t lis2dtw12_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_thsy; return ret; @@ -2302,6 +2363,8 @@ int32_t lis2dtw12_tap_axis_priority_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Y, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.tap_prior) { case LIS2DTW12_XYZ: @@ -2374,6 +2437,9 @@ int32_t lis2dtw12_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_thsz; return ret; @@ -2419,6 +2485,9 @@ int32_t lis2dtw12_tap_detection_on_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_z_en; return ret; @@ -2464,6 +2533,9 @@ int32_t lis2dtw12_tap_detection_on_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_y_en; return ret; @@ -2509,6 +2581,9 @@ int32_t lis2dtw12_tap_detection_on_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_Z, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_x_en; return ret; @@ -2560,6 +2635,9 @@ int32_t lis2dtw12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.shock; return ret; @@ -2611,6 +2689,9 @@ int32_t lis2dtw12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.quiet; return ret; @@ -2664,6 +2745,9 @@ int32_t lis2dtw12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_INT_DUR, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.latency; return ret; @@ -2711,6 +2795,8 @@ int32_t lis2dtw12_tap_mode_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_THS, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.single_double_tap) { case LIS2DTW12_ONLY_SINGLE: @@ -2798,6 +2884,9 @@ int32_t lis2dtw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg._6d_ths; return ret; @@ -2841,6 +2930,9 @@ int32_t lis2dtw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_TAP_THS_X, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg._4d_en; return ret; @@ -2904,6 +2996,8 @@ int32_t lis2dtw12_6d_feed_data_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.lpass_on6d) { case LIS2DTW12_ODR_DIV_2_FEED: @@ -2993,11 +3087,12 @@ int32_t lis2dtw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dtw12_read_reg(ctx, LIS2DTW12_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); + ret += lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL, + (uint8_t *) &free_fall, 1); if (ret == 0) { - ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL, - (uint8_t *) &free_fall, 1); + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; } @@ -3045,6 +3140,8 @@ int32_t lis2dtw12_ff_threshold_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FREE_FALL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.ff_ths) { case LIS2DTW12_FF_TSH_5LSb_FS2g: @@ -3137,6 +3234,9 @@ int32_t lis2dtw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fth; return ret; @@ -3183,6 +3283,8 @@ int32_t lis2dtw12_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.fmode) { case LIS2DTW12_BYPASS_MODE: @@ -3228,6 +3330,9 @@ int32_t lis2dtw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_SAMPLES, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.diff; return ret; @@ -3247,6 +3352,9 @@ int32_t lis2dtw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_SAMPLES, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_ovr; return ret; @@ -3266,6 +3374,9 @@ int32_t lis2dtw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dtw12_read_reg(ctx, LIS2DTW12_FIFO_SAMPLES, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_fth; return ret; @@ -3280,5 +3391,3 @@ int32_t lis2dtw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h index e66da51..1100cfb 100644 --- a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h +++ b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1084,5 +1086,3 @@ int32_t lis2dtw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /*LIS2DTW12_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.c b/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.c index 5062b5e..f295961 100644 --- a/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.c +++ b/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -170,6 +169,9 @@ int32_t lis2du12_id_get(const stmdev_ctx_t *ctx, lis2du12_id_t *val) int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_WHO_AM_I, ®, 1); + + if (ret != 0) { return ret; } + val->whoami = reg; return ret; @@ -225,10 +227,10 @@ int32_t lis2du12_bus_mode_get(const stmdev_ctx_t *ctx, lis2du12_bus_mode_t *val) int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); - if (ret == 0) - { - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); - } + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret != 0) { return ret; } + switch ((ctrl1.sim << 2) | (if_ctrl.i2c_disable) << 1 | (if_ctrl.i3c_disable)) { @@ -262,26 +264,29 @@ int32_t lis2du12_init_set(const stmdev_ctx_t *ctx, lis2du12_init_t val) ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret != 0) { return ret; } + switch (val) { case LIS2DU12_BOOT: ctrl4.boot = PROPERTY_ENABLE; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); + ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); break; case LIS2DU12_RESET: ctrl1.sw_reset = PROPERTY_ENABLE; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); + ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); break; case LIS2DU12_DRV_RDY: ctrl4.bdu = PROPERTY_ENABLE; ctrl1.if_add_inc = PROPERTY_ENABLE; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); + ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); break; default: ctrl1.sw_reset = PROPERTY_ENABLE; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); + ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); break; } @@ -305,14 +310,10 @@ int32_t lis2du12_status_get(const stmdev_ctx_t *ctx, lis2du12_status_t *val) ret = lis2du12_read_reg(ctx, LIS2DU12_STATUS, (uint8_t *)&status_register, 1); - if (ret == 0) - { - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); - } - if (ret == 0) - { - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); - } + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret != 0) { return ret; } val->sw_reset = ctrl1.sw_reset; val->boot = ctrl4.boot; @@ -339,41 +340,25 @@ int32_t lis2du12_pin_conf_set(const stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val) int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t *)&if_pu_ctrl, 1); - if (ret == 0) - { - ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); - } - if (ret == 0) - { - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); - } - if (ret == 0) - { - ret = lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); - } + ret += lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret == 0) - { - if_pu_ctrl.sdo_pu_disc = ~val->sdo_pull_up; - if_pu_ctrl.sda_pu_en = val->sda_pull_up; - if_pu_ctrl.cs_pu_disc = ~val->cs_pull_up; - ret = lis2du12_write_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t *)&if_pu_ctrl, 1); - } - if (ret == 0) - { - if_ctrl.pd_dis_int1 = val->int1_pull_down; - ret = lis2du12_write_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); - } - if (ret == 0) - { - ctrl1.pp_od = val->int1_int2_push_pull; - ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); - } - if (ret == 0) - { - md2_cfg.pd_dis_int2 = val->int2_pull_down; - ret = lis2du12_write_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); - } + if (ret != 0) { return ret; } + + if_pu_ctrl.sdo_pu_disc = ~val->sdo_pull_up; + if_pu_ctrl.sda_pu_en = val->sda_pull_up; + if_pu_ctrl.cs_pu_disc = ~val->cs_pull_up; + ret = lis2du12_write_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t *)&if_pu_ctrl, 1); + + if_ctrl.pd_dis_int1 = val->int1_pull_down; + ret = lis2du12_write_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); + + ctrl1.pp_od = val->int1_int2_push_pull; + ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); + + md2_cfg.pd_dis_int2 = val->int2_pull_down; + ret = lis2du12_write_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); return ret; } @@ -395,18 +380,12 @@ int32_t lis2du12_pin_conf_get(const stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val) int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t *)&if_pu_ctrl, 1); - if (ret == 0) - { - ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); - } - if (ret == 0) - { - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); - } - if (ret == 0) - { - ret = lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); - } + ret += lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); + + if (ret != 0) { return ret; } + val->sdo_pull_up = ~if_pu_ctrl.sdo_pu_disc; val->sda_pull_up = if_pu_ctrl.sda_pu_en; val->cs_pull_up = ~if_pu_ctrl.cs_pu_disc; @@ -447,12 +426,15 @@ int32_t lis2du12_all_sources_get(const stmdev_ctx_t *ctx, ret = lis2du12_read_reg(ctx, LIS2DU12_SIXD_SRC, (uint8_t *)&sixd_src, 1); - val->six_d_xl = sixd_src.xl; - val->six_d_xh = sixd_src.xh; - val->six_d_yl = sixd_src.yl; - val->six_d_yh = sixd_src.yh; - val->six_d_zl = sixd_src.zl; - val->six_d_zh = sixd_src.zh; + if (ret == 0) + { + val->six_d_xl = sixd_src.xl; + val->six_d_xh = sixd_src.xh; + val->six_d_yl = sixd_src.yl; + val->six_d_yh = sixd_src.yh; + val->six_d_zl = sixd_src.zl; + val->six_d_zh = sixd_src.zh; + } } if (all_int_src.wu_ia_all == 1U || all_int_src.sleep_change_ia_all == 1U) @@ -461,10 +443,13 @@ int32_t lis2du12_all_sources_get(const stmdev_ctx_t *ctx, ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_SRC, (uint8_t *)&wu_src, 1); - val->wake_up_z = wu_src.z_wu; - val->wake_up_y = wu_src.y_wu; - val->wake_up_x = wu_src.x_wu; - val->sleep_state = wu_src.sleep_state; + if (ret == 0) + { + val->wake_up_z = wu_src.z_wu; + val->wake_up_y = wu_src.y_wu; + val->wake_up_x = wu_src.x_wu; + val->sleep_state = wu_src.sleep_state; + } } if (all_int_src.single_tap_all == 1U || all_int_src.double_tap_all == 1U) @@ -473,10 +458,13 @@ int32_t lis2du12_all_sources_get(const stmdev_ctx_t *ctx, ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_SRC, (uint8_t *)&tap_src, 1); - val->tap_z = tap_src.z_tap; - val->tap_y = tap_src.y_tap; - val->tap_x = tap_src.x_tap; - val->tap_sign = tap_src.tap_sign; + if (ret == 0) + { + val->tap_z = tap_src.z_tap; + val->tap_y = tap_src.y_tap; + val->tap_x = tap_src.x_tap; + val->tap_sign = tap_src.tap_sign; + } } } @@ -498,6 +486,8 @@ int32_t lis2du12_mode_set(const stmdev_ctx_t *ctx, lis2du12_md_t *val) ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) { return ret; } + ctrl5.odr = (uint8_t)val->odr; ctrl5.fs = (uint8_t)val->fs; ctrl5.bw = (uint8_t)val->bw; @@ -522,6 +512,8 @@ int32_t lis2du12_mode_get(const stmdev_ctx_t *ctx, lis2du12_md_t *val) ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) { return ret; } + switch (ctrl5.odr) { case LIS2DU12_OFF: @@ -628,8 +620,11 @@ int32_t lis2du12_trigger_sw(const stmdev_ctx_t *ctx, lis2du12_md_t *md) if (md->odr == LIS2DU12_TRIG_SW) { ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret != 0) { return ret; } + ctrl4.soc = PROPERTY_ENABLE; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); + ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); } return ret; } @@ -653,6 +648,8 @@ int32_t lis2du12_data_get(const stmdev_ctx_t *ctx, lis2du12_md_t *md, ret = lis2du12_read_reg(ctx, LIS2DU12_OUTX_L, (uint8_t *)&buff, 8); + if (ret != 0) { return ret; } + /* acceleration conversion */ j = 0U; for (i = 0U; i < 3U; i++) @@ -729,8 +726,12 @@ int32_t lis2du12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val) } ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); - ctrl3.st = (uint8_t) val; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret == 0) + { + ctrl3.st = (uint8_t) val; + ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); + } return ret; } @@ -749,8 +750,11 @@ int32_t lis2du12_self_test_stop(const stmdev_ctx_t *ctx) int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); - ctrl3.st = 0; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ctrl3.st = 0; + ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); + } return ret; } @@ -785,6 +789,8 @@ int32_t lis2du12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val) ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_CTRL, reg, 2); + if (ret != 0) { return ret; } + bytecpy((uint8_t *)&fifo_ctrl, ®[0]); bytecpy((uint8_t *)&fifo_wtm, ®[1]); @@ -827,6 +833,8 @@ int32_t lis2du12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val) ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_CTRL, reg, 2); + if (ret != 0) { return ret; } + bytecpy((uint8_t *)&fifo_ctrl, ®[0]); bytecpy((uint8_t *)&fifo_wtm, ®[1]); @@ -880,6 +888,8 @@ int32_t lis2du12_fifo_status_get(const stmdev_ctx_t *ctx, lis2du12_fifo_status_t ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + if (ret != 0) { return ret; } + val->fifo_fth = fifo_status1.fth; val->fifo_ovr = fifo_status1.fifo_ovr; @@ -904,6 +914,8 @@ int32_t lis2du12_fifo_level_get(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *md, ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); + if (ret != 0) { return ret; } + *val = fifo_status2.fss; return ret; @@ -929,6 +941,8 @@ int32_t lis2du12_fifo_data_get(const stmdev_ctx_t *ctx, lis2du12_md_t *md, ret = lis2du12_read_reg(ctx, LIS2DU12_OUTX_L, fifo_data, 8); + if (ret != 0) { return ret; } + if (fmd->store == LIS2DU12_8_BIT) { for (i = 0; i < 3; i++) @@ -1013,6 +1027,8 @@ int32_t lis2du12_interrupt_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&interrupt_cfg, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) { return ret; } + interrupt_cfg.int_short_en = (uint8_t)val->base_sig & 0x01U; interrupt_cfg.lir = ((uint8_t)val->base_sig & 0x02U) >> 1 ; @@ -1021,7 +1037,7 @@ int32_t lis2du12_interrupt_mode_set(const stmdev_ctx_t *ctx, interrupt_cfg.interrupts_enable = val->enable; - ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG, + ret = lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); @@ -1047,6 +1063,8 @@ int32_t lis2du12_interrupt_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&interrupt_cfg, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) { return ret; } + val->active_low = interrupt_cfg.h_lactive; val->drdy_latched = ~ctrl1.drdy_pulsed; val->enable = interrupt_cfg.interrupts_enable; @@ -1087,6 +1105,8 @@ int32_t lis2du12_pin_int1_route_set(const stmdev_ctx_t *ctx, ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) { return ret; } + ctrl2.int1_boot = val->boot; ctrl2.int1_drdy = val->drdy_xl; ctrl2.int1_f_fth = val->fifo_th; @@ -1110,7 +1130,7 @@ int32_t lis2du12_pin_int1_route_set(const stmdev_ctx_t *ctx, md1_cfg.int1_sleep_change = PROPERTY_ENABLE; } - ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG, + ret = lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); ret += lis2du12_write_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1); ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL2, (uint8_t *)&ctrl2, 1); @@ -1139,6 +1159,8 @@ int32_t lis2du12_pin_int1_route_get(const stmdev_ctx_t *ctx, ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) { return ret; } + val->boot = ctrl2.int1_boot; val->drdy_xl = ctrl2.int1_drdy; val->fifo_th = ctrl2.int1_f_fth; @@ -1186,6 +1208,8 @@ int32_t lis2du12_pin_int2_route_set(const stmdev_ctx_t *ctx, ret += lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) { return ret; } + ctrl3.int2_boot = val->boot; ctrl3.int2_drdy = val->drdy_xl; ctrl3.int2_f_fth = val->fifo_th; @@ -1238,6 +1262,8 @@ int32_t lis2du12_pin_int2_route_get(const stmdev_ctx_t *ctx, ret += lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) { return ret; } + val->boot = ctrl3.int2_boot; val->drdy_xl = ctrl3.int2_drdy; val->fifo_th = ctrl3.int2_f_fth; @@ -1305,18 +1331,20 @@ int32_t lis2du12_wake_up_mode_set(const stmdev_ctx_t *ctx, lis2du12_wkup_md_t *v ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) { return ret; } + ctrl1.wu_z_en = val->z_en; ctrl1.wu_y_en = val->y_en; ctrl1.wu_x_en = val->x_en; if (val->threshold > 63U) { - interrupt_cfg.wake_ths_w = PROPERTY_ENABLE; + interrupt_cfg.wake_ths_w = PROPERTY_DISABLE; wake_up_ths.wk_ths = val->threshold / 4U; } else { - interrupt_cfg.wake_ths_w = PROPERTY_DISABLE; + interrupt_cfg.wake_ths_w = PROPERTY_ENABLE; wake_up_ths.wk_ths = val->threshold; } @@ -1376,11 +1404,13 @@ int32_t lis2du12_wake_up_mode_get(const stmdev_ctx_t *ctx, lis2du12_wkup_md_t *v ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) { return ret; } + val->z_en = ctrl1.wu_z_en; val->y_en = ctrl1.wu_y_en; val->x_en = ctrl1.wu_x_en; - if (interrupt_cfg.wake_ths_w == PROPERTY_ENABLE) + if (interrupt_cfg.wake_ths_w == PROPERTY_DISABLE) { val->threshold = wake_up_ths.wk_ths * 4U; } @@ -1460,6 +1490,8 @@ int32_t lis2du12_tap_mode_set(const stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t *)&tap_ths_z, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_INT_DUR, (uint8_t *)&int_dur, 1); + if (ret != 0) { return ret; } + tap_ths_z.tap_z_en = val->z_en; tap_ths_z.tap_y_en = val->y_en; tap_ths_z.tap_x_en = val->x_en; @@ -1510,6 +1542,8 @@ int32_t lis2du12_tap_mode_get(const stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t *)&tap_ths_z, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_INT_DUR, (uint8_t *)&int_dur, 1); + if (ret != 0) { return ret; } + val->z_en = tap_ths_z.tap_z_en; val->y_en = tap_ths_z.tap_y_en; val->x_en = tap_ths_z.tap_x_en; @@ -1583,6 +1617,8 @@ int32_t lis2du12_free_fall_mode_set(const stmdev_ctx_t *ctx, lis2du12_ff_md_t *v (uint8_t *)&wake_up_dur, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) { return ret; } + wake_up_dur.ff_dur = val->duration & 0x1FU; free_fall.ff_dur = (val->duration) & 0x20U >> 5; @@ -1613,6 +1649,8 @@ int32_t lis2du12_free_fall_mode_get(const stmdev_ctx_t *ctx, lis2du12_ff_md_t *v (uint8_t *)&wake_up_dur, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) { return ret; } + val->duration = (free_fall.ff_dur * 32U) + wake_up_dur.ff_dur; switch (free_fall.ff_ths) @@ -1678,6 +1716,8 @@ int32_t lis2du12_orientation_mode_set(const stmdev_ctx_t *ctx, ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t *)&tap_ths_x, 1); + if (ret != 0) { return ret; } + tap_ths_x.d6d_ths = (uint8_t)val->threshold; tap_ths_x.d4d_en = (uint8_t)val->deg_of_freedom; @@ -1702,6 +1742,8 @@ int32_t lis2du12_orientation_mode_get(const stmdev_ctx_t *ctx, ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t *)&tap_ths_x, 1); + if (ret != 0) { return ret; } + switch (tap_ths_x.d6d_ths) { case LIS2DU12_DEG_80: @@ -1743,5 +1785,3 @@ int32_t lis2du12_orientation_mode_get(const stmdev_ctx_t *ctx, */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.h b/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.h index 885a891..2de57a6 100644 --- a/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.h +++ b/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -990,7 +992,7 @@ typedef struct uint8_t x_en : 1; /* Detection on X-axis */ uint8_t y_en : 1; /* Detection on Y-axis */ uint8_t z_en : 1; /* Detection on Z-axis */ - uint8_t threshold; /* full scale dependent */ + uint8_t threshold; /* 1 LSB = FS_XL / 2^8 */ uint8_t duration; /* 1 LSb: 1 ODR_time */ struct { @@ -1089,5 +1091,3 @@ int32_t lis2du12_orientation_mode_get(const stmdev_ctx_t *ctx, #endif #endif /* LIS2DU12_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.c b/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.c index a22055b..0f3c9e5 100644 --- a/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.c +++ b/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -161,6 +160,10 @@ int32_t lis2dux12_init_set(const stmdev_ctx_t *ctx, lis2dux12_init_t val) ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (val) { case LIS2DUX12_BOOT: @@ -273,9 +276,12 @@ int32_t lis2dux12_status_get(const stmdev_ctx_t *ctx, lis2dux12_status_t *val) ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); - val->sw_reset = ctrl1.sw_reset; - val->boot = ctrl4.boot; - val->drdy = status_register.drdy; + if (ret == 0) + { + val->sw_reset = ctrl1.sw_reset; + val->boot = ctrl4.boot; + val->drdy = status_register.drdy; + } return ret; } @@ -290,16 +296,17 @@ int32_t lis2dux12_status_get(const stmdev_ctx_t *ctx, lis2dux12_status_t *val) */ int32_t lis2dux12_embedded_status_get(const stmdev_ctx_t *ctx, lis2dux12_embedded_status_t *val) { - lis2dux12_emb_func_status_t status; + lis2dux12_emb_func_status_mainpage_t status; int32_t ret; - ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); - ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_STATUS, (uint8_t *)&status, 1); - ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_STATUS_MAINPAGE, (uint8_t *)&status, 1); - val->is_step_det = status.is_step_det; - val->is_tilt = status.is_tilt; - val->is_sigmot = status.is_sigmot; + if (ret == 0) + { + val->is_step_det = status.is_step_det; + val->is_tilt = status.is_tilt; + val->is_sigmot = status.is_sigmot; + } return ret; } @@ -343,6 +350,11 @@ int32_t lis2dux12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2dux12_data_re ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl1.drdy_pulsed)) { case 0x0: @@ -375,6 +387,10 @@ int32_t lis2dux12_mode_set(const stmdev_ctx_t *ctx, const lis2dux12_md_t *val) int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } ctrl5.odr = (uint8_t)val->odr & 0xFU; ctrl5.fs = (uint8_t)val->fs; @@ -464,11 +480,6 @@ int32_t lis2dux12_mode_set(const stmdev_ctx_t *ctx, const lis2dux12_md_t *val) break; } - if (ret != 0) - { - return ret; - } - ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1); ctrl3.hp_en = (((uint8_t)val->odr & 0x30U) == 0x10U) ? 1U : 0U; @@ -499,6 +510,11 @@ int32_t lis2dux12_mode_get(const stmdev_ctx_t *ctx, lis2dux12_md_t *val) ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL5, (uint8_t *)&ctrl5, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5.odr) { case 0x00: @@ -627,7 +643,10 @@ int32_t lis2dux12_temp_disable_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&temp, 1); - *val = temp.t_dis; + if (ret == 0) + { + *val = temp.t_dis; + } return ret; } @@ -694,7 +713,10 @@ int32_t lis2dux12_disable_hard_reset_from_cs_set(const stmdev_ctx_t *ctx, uint8_ ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); fifo_ctrl.dis_hard_rst_cs = (val == 1) ? PROPERTY_ENABLE : PROPERTY_DISABLE; - ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret == 0) + { + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + } return ret; } @@ -712,7 +734,10 @@ int32_t lis2dux12_disable_hard_reset_from_cs_get(const stmdev_ctx_t *ctx, uint8_ int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - *val = fifo_ctrl.dis_hard_rst_cs; + if (ret == 0) + { + *val = fifo_ctrl.dis_hard_rst_cs; + } return ret; } @@ -760,6 +785,11 @@ int32_t lis2dux12_all_sources_get(const stmdev_ctx_t *ctx, lis2dux12_all_sources ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_SRC, (uint8_t *)&wu_src, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_SRC, (uint8_t *)&tap_src, 1); + if (ret != 0) + { + return ret; + } + val->six_d = sixd_src.d6d_ia; val->six_d_xl = sixd_src.xl; val->six_d_xh = sixd_src.xh; @@ -803,6 +833,11 @@ int32_t lis2dux12_xl_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md, ret = lis2dux12_read_reg(ctx, LIS2DUX12_OUT_X_L, buff, 6); + if (ret != 0) + { + return ret; + } + /* acceleration conversion */ j = 0U; for (i = 0U; i < 3U; i++) @@ -850,6 +885,11 @@ int32_t lis2dux12_outt_data_get(const stmdev_ctx_t *ctx, ret = lis2dux12_read_reg(ctx, LIS2DUX12_OUT_T_L, buff, 2); + if (ret != 0) + { + return ret; + } + data->heat.raw = (int16_t)buff[1U]; data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[0]; /* temperature conversion */ @@ -874,6 +914,10 @@ int32_t lis2dux12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2dux12_xl_self_ ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1); + if (ret != 0) + { + return ret; + } switch (val) { @@ -983,13 +1027,19 @@ int32_t lis2dux12_i3c_configure_set(const stmdev_ctx_t *ctx, const lis2dux12_i3c * @param val configuration params * @retval interface status (MANDATORY: return 0 -> no Error) * - */int32_t lis2dux12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val) + */ +int32_t lis2dux12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val) { lis2dux12_i3c_if_ctrl_t i3c_cfg; int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1); + if (ret != 0) + { + return ret; + } + val->drstdaa_en = i3c_cfg.dis_drstdaa; val->asf_on = i3c_cfg.asf_on; @@ -1054,6 +1104,10 @@ int32_t lis2dux12_mem_bank_get(const stmdev_ctx_t *ctx, lis2dux12_mem_bank_t *va int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } switch ((func_cfg_access.emb_func_reg_access)) { @@ -1104,12 +1158,20 @@ int32_t lis2dux12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* page write */ ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_ENABLE; ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); /* set page num */ ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -1129,6 +1191,10 @@ int32_t lis2dux12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t { msb++; ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -1145,6 +1211,10 @@ int32_t lis2dux12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -1187,6 +1257,10 @@ int32_t lis2dux12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* page read */ ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -1197,6 +1271,10 @@ int32_t lis2dux12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* set page num */ ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -1222,6 +1300,10 @@ int32_t lis2dux12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* set page */ ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -1238,6 +1320,10 @@ int32_t lis2dux12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -1274,8 +1360,11 @@ int32_t lis2dux12_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_EXT_CLK_CFG, (uint8_t *)&clk, 1); - clk.ext_clk_en = val; - ret += lis2dux12_write_reg(ctx, LIS2DUX12_EXT_CLK_CFG, (uint8_t *)&clk, 1); + if (ret == 0) + { + clk.ext_clk_en = val; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EXT_CLK_CFG, (uint8_t *)&clk, 1); + } return ret; } @@ -1294,7 +1383,10 @@ int32_t lis2dux12_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_EXT_CLK_CFG, (uint8_t *)&clk, 1); - *val = clk.ext_clk_en; + if (ret == 0) + { + *val = clk.ext_clk_en; + } return ret; } @@ -1344,12 +1436,15 @@ int32_t lis2dux12_pin_conf_get(const stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *va ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); - val->cs_pull_up = ~pin_ctrl.cs_pu_dis; - val->int1_pull_down = ~pin_ctrl.pd_dis_int1; - val->int2_pull_down = ~pin_ctrl.pd_dis_int2; - val->sda_pull_up = pin_ctrl.sda_pu_en; - val->sdo_pull_up = pin_ctrl.sdo_pu_en; - val->int1_int2_push_pull = ~pin_ctrl.pp_od; + if (ret == 0) + { + val->cs_pull_up = ~pin_ctrl.cs_pu_dis; + val->int1_pull_down = ~pin_ctrl.pd_dis_int1; + val->int2_pull_down = ~pin_ctrl.pd_dis_int2; + val->sda_pull_up = pin_ctrl.sda_pu_en; + val->sdo_pull_up = pin_ctrl.sdo_pu_en; + val->int1_int2_push_pull = ~pin_ctrl.pp_od; + } return ret; } @@ -1393,6 +1488,11 @@ int32_t lis2dux12_int_pin_polarity_get(const stmdev_ctx_t *ctx, lis2dux12_int_pi ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + switch ((pin_ctrl.h_lactive)) { case 0x0: @@ -1448,6 +1548,10 @@ int32_t lis2dux12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dux12_spi_mode *val) int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch ((pin_ctrl.sim)) { @@ -1702,8 +1806,8 @@ int32_t lis2dux12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2dux12_pin_int_ lis2dux12_md2_cfg_t md2_cfg; int32_t ret; - ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL2, (uint8_t *)&ctrl3, 1); - ret += lis2dux12_read_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md2_cfg, 1); + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_MD2_CFG, (uint8_t *)&md2_cfg, 1); if (ret == 0) { @@ -1897,19 +2001,22 @@ int32_t lis2dux12_embedded_int_cfg_set(const stmdev_ctx_t *ctx, lis2dux12_embedd { ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); - switch (val) + if (ret == 0) { - case LIS2DUX12_EMBEDDED_INT_LEVEL: - page_rw.emb_func_lir = 0; - break; + switch (val) + { + case LIS2DUX12_EMBEDDED_INT_LEVEL: + page_rw.emb_func_lir = 0; + break; - case LIS2DUX12_EMBEDDED_INT_LATCHED: - default: - page_rw.emb_func_lir = 1; - break; - } + case LIS2DUX12_EMBEDDED_INT_LATCHED: + default: + page_rw.emb_func_lir = 1; + break; + } - ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); + } } ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); @@ -1936,13 +2043,16 @@ int32_t lis2dux12_embedded_int_cfg_get(const stmdev_ctx_t *ctx, { ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); - if (page_rw.emb_func_lir == 0U) - { - *val = LIS2DUX12_EMBEDDED_INT_LEVEL; - } - else + if (ret == 0) { - *val = LIS2DUX12_EMBEDDED_INT_LATCHED; + if (page_rw.emb_func_lir == 0U) + { + *val = LIS2DUX12_EMBEDDED_INT_LEVEL; + } + else + { + *val = LIS2DUX12_EMBEDDED_INT_LATCHED; + } } } @@ -1976,12 +2086,10 @@ int32_t lis2dux12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t v lis2dux12_ctrl4_t ctrl4; lis2dux12_fifo_ctrl_t fifo_ctrl; lis2dux12_fifo_wtm_t fifo_wtm; - lis2dux12_fifo_batch_dec_t fifo_batch; int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); if (ret == 0) @@ -2003,23 +2111,11 @@ int32_t lis2dux12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t v /* Set xl_only_fifo */ fifo_wtm.xl_only_fifo = val.xl_only; - /* set batching info */ - fifo_batch.dec_ts_batch = (uint8_t)val.batch.dec_ts; - fifo_batch.bdr_xl = (uint8_t)val.batch.bdr_xl; - fifo_ctrl.cfg_chg_en = val.cfg_change_in_fifo; - /* set watermark */ - if (val.watermark > 0U) - { - fifo_ctrl.stop_on_fth = (val.fifo_event == LIS2DUX12_FIFO_EV_WTM) ? 1 : 0; - fifo_wtm.fth = val.watermark; - } - - ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); - ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); - ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); } return ret; @@ -2038,12 +2134,10 @@ int32_t lis2dux12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t * lis2dux12_ctrl4_t ctrl4; lis2dux12_fifo_ctrl_t fifo_ctrl; lis2dux12_fifo_wtm_t fifo_wtm; - lis2dux12_fifo_batch_dec_t fifo_batch; int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); if (ret == 0) @@ -2065,12 +2159,155 @@ int32_t lis2dux12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t * /* Get xl_only_fifo */ val->xl_only = fifo_wtm.xl_only_fifo; - /* get batching info */ - val->batch.dec_ts = (lis2dux12_dec_ts_t)fifo_batch.dec_ts_batch; - val->batch.bdr_xl = (lis2dux12_bdr_xl_t)fifo_batch.bdr_xl; + } + + return ret; +} + +/** + * @brief FIFO watermark threshold.[set] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold, maximum value is 127. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lis2dux12_fifo_wtm_t fifo_wtm; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + + if (ret == 0) + { + fifo_wtm.fth = val; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark threshold.[get] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold, maximum value is 127. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2dux12_fifo_wtm_t fifo_wtm; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + + if (ret == 0) + { + *val = fifo_wtm.fth; + } + + return ret; +} + + +/** + * @brief FIFO batch.[set] + * + * @param ctx read / write interface definitions + * @param val Select value for bdr_xl: BDR_XL_ODR, BDR_XL_ODR_DIV_2, BDR_XL_ODR_DIV_4, BDR_XL_ODR_DIV_8, + * BDR_XL_ODR_DIV_16, BDR_XL_ODR_DIV_32, BDR_XL_ODR_DIV_64, BDR_XL_ODR_OFF; + * and dec_ts: DEC_TS_OFF, DEC_TS_1, DEC_TS_8, DEC_TS_32 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_fifo_batch_set(const stmdev_ctx_t *ctx, lis2dux12_fifo_batch_t val) +{ + lis2dux12_fifo_batch_dec_t fifo_batch; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); - /* get watermark */ - val->watermark = fifo_wtm.fth; + if (ret == 0) + { + fifo_batch.dec_ts_batch = (uint8_t)val.dec_ts; + fifo_batch.bdr_xl = (uint8_t)val.bdr_xl; + + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + } + + return ret; +} + +/** + * @brief FIFO batch.[get] + * + * @param ctx read / write interface definitions + * @param val Select value for bdr_xl: BDR_XL_ODR, BDR_XL_ODR_DIV_2, BDR_XL_ODR_DIV_4, BDR_XL_ODR_DIV_8, + * BDR_XL_ODR_DIV_16, BDR_XL_ODR_DIV_32, BDR_XL_ODR_DIV_64, BDR_XL_ODR_OFF; + * and dec_ts: DEC_TS_OFF, DEC_TS_1, DEC_TS_8, DEC_TS_32 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_fifo_batch_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_batch_t *val) +{ + lis2dux12_fifo_batch_dec_t fifo_batch; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + + if (ret == 0) + { + val->dec_ts = fifo_batch.dec_ts_batch; + val->bdr_xl = fifo_batch.bdr_xl; + } + + return ret; +} + +/** + * @brief FIFO stop on wtm.[set] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable stop on wtm functionality. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lis2dux12_fifo_event_t val) +{ + lis2dux12_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + + if (ret == 0) + { + fifo_ctrl.stop_on_fth = (val == LIS2DUX12_FIFO_EV_WTM) ? 1 : 0; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + } + + return ret; +} + +/** + * @brief FIFO stop on wtm.[get] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable stop on wtm functionality. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_event_t *val) +{ + lis2dux12_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + + if (ret == 0) + { + *val = (fifo_ctrl.stop_on_fth == 1) ? LIS2DUX12_FIFO_EV_WTM : LIS2DUX12_FIFO_EV_FULL; } return ret; @@ -2091,7 +2328,10 @@ int32_t lis2dux12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_STATUS2, &buff, 1); - *val = buff; + if (ret == 0) + { + *val = buff; + } return ret; } @@ -2103,7 +2343,10 @@ int32_t lis2dux12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); - *val = fifo_status1.fifo_wtm_ia; + if (ret == 0) + { + *val = fifo_status1.fifo_wtm_ia; + } return ret; } @@ -2115,7 +2358,10 @@ int32_t lis2dux12_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_se ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); - *val = (lis2dux12_fifo_sensor_tag_t) fifo_tag.tag_sensor; + if (ret == 0) + { + *val = (lis2dux12_fifo_sensor_tag_t) fifo_tag.tag_sensor; + } return ret; } @@ -2138,6 +2384,10 @@ int32_t lis2dux12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *m int32_t ret, i; ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); + if (ret != 0) + { + return ret; + } data->tag = fifo_tag.tag_sensor; switch (fifo_tag.tag_sensor) @@ -2145,6 +2395,10 @@ int32_t lis2dux12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *m case LIS2DUX12_XL_ONLY_2X_TAG: /* A FIFO sample consists of 2X 8-bits 3-axis XL at ODR/2 */ ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } for (i = 0; i < 3; i++) { data->xl[0].raw[i] = (int16_t)fifo_raw[i] * 256; @@ -2153,6 +2407,10 @@ int32_t lis2dux12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *m break; case LIS2DUX12_XL_TEMP_TAG: ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } if (fmd->xl_only == 0x0U) { /* A FIFO sample consists of 12-bits 3-axis XL + T at ODR*/ @@ -2176,6 +2434,10 @@ int32_t lis2dux12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *m break; case LIS2DUX12_TIMESTAMP_TAG: ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } data->cfg_chg.cfg_change = fifo_raw[0] >> 7; data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU; @@ -2193,6 +2455,10 @@ int32_t lis2dux12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *m case LIS2DUX12_STEP_COUNTER_TAG: ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } data->pedo.steps = fifo_raw[1]; data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0]; @@ -2267,19 +2533,23 @@ int32_t lis2dux12_stpcnt_mode_set(const stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); - if ((val.false_step_rej == PROPERTY_ENABLE) - && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) + if (ret == 0) { - emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; - } + if ((val.false_step_rej == PROPERTY_ENABLE) + && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) + { + emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + } - emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo; - ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); + emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); - emb_func_en_a.pedo_en = val.step_counter_enable; - ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.pedo_en = val.step_counter_enable; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + ret += lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); @@ -2304,17 +2574,24 @@ int32_t lis2dux12_stpcnt_mode_set(const stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode int32_t lis2dux12_stpcnt_mode_get(const stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t *val) { lis2dux12_emb_func_en_a_t emb_func_en_a; + lis2dux12_emb_func_fifo_en_t emb_func_fifo_en; lis2dux12_pedo_cmd_reg_t pedo_cmd_reg; int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); ret += lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); - val->false_step_rej = pedo_cmd_reg.fp_rejection_en; - val->step_counter_enable = emb_func_en_a.pedo_en; + + if (ret == 0) + { + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + val->step_counter_in_fifo = emb_func_fifo_en.step_counter_fifo_en; + } return ret; } @@ -2336,8 +2613,11 @@ int32_t lis2dux12_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) ret += lis2dux12_read_reg(ctx, LIS2DUX12_STEP_COUNTER_L, &buff[0], 2); ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -2356,9 +2636,9 @@ int32_t lis2dux12_stpcnt_rst_step_set(const stmdev_ctx_t *ctx) int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); emb_func_src.pedo_rst_step = 1; ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); } @@ -2403,7 +2683,10 @@ int32_t lis2dux12_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); - *val = pedo_deb_steps_conf.deb_step; + if (ret == 0) + { + *val = pedo_deb_steps_conf.deb_step; + } return ret; } @@ -2445,8 +2728,11 @@ int32_t lis2dux12_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -2465,6 +2751,10 @@ int32_t lis2dux12_smart_power_set(const stmdev_ctx_t *ctx, lis2dux12_smart_power int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } ctrl1.smart_power_en = val.enable; ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); @@ -2496,12 +2786,16 @@ int32_t lis2dux12_smart_power_get(const stmdev_ctx_t *ctx, lis2dux12_smart_power int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); - val->enable = ctrl1.smart_power_en; ret += lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_SMART_POWER_CTRL, (uint8_t *)&smart_power_ctrl, 1); - val->window = smart_power_ctrl.smart_power_ctrl_win; - val->duration = smart_power_ctrl.smart_power_ctrl_dur; + + if (ret == 0) + { + val->enable = ctrl1.smart_power_en; + val->window = smart_power_ctrl.smart_power_ctrl_win; + val->duration = smart_power_ctrl.smart_power_ctrl_dur; + } return ret; } @@ -2531,9 +2825,9 @@ int32_t lis2dux12_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); emb_func_en_a.tilt_en = val; ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } @@ -2557,9 +2851,9 @@ int32_t lis2dux12_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); *val = emb_func_en_a.tilt_en; } @@ -2593,9 +2887,9 @@ int32_t lis2dux12_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); emb_func_en_a.sign_motion_en = val; ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } @@ -2619,9 +2913,9 @@ int32_t lis2dux12_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); *val = emb_func_en_a.sign_motion_en; } @@ -2664,9 +2958,9 @@ int32_t lis2dux12_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); } + ret += lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); free_fall.ff_dur = val & 0x1FU; ret += lis2dux12_write_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); } @@ -2691,7 +2985,10 @@ int32_t lis2dux12_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); - *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur; + if (ret == 0) + { + *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur; + } return ret; } @@ -2710,8 +3007,11 @@ int32_t lis2dux12_ff_thresholds_set(const stmdev_ctx_t *ctx, lis2dux12_ff_thresh int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); - free_fall.ff_ths = ((uint8_t)val & 0x7U); - ret += lis2dux12_write_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = ((uint8_t)val & 0x7U); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); + } return ret; } @@ -2731,6 +3031,11 @@ int32_t lis2dux12_ff_thresholds_get(const stmdev_ctx_t *ctx, lis2dux12_ff_thresh ret = lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } + switch (free_fall.ff_ths) { case 0x0: @@ -2823,6 +3128,10 @@ int32_t lis2dux12_sixd_config_get(const stmdev_ctx_t *ctx, lis2dux12_sixd_config int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_SIXD, (uint8_t *)&sixd, 1); + if (ret != 0) + { + return ret; + } val->mode = (lis2dux12_mode_t)sixd.d4d_en; @@ -3130,7 +3439,10 @@ int32_t lis2dux12_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); - *val = int_cfg.timestamp_en; + if (ret == 0) + { + *val = int_cfg.timestamp_en; + } return ret; } @@ -3151,6 +3463,10 @@ int32_t lis2dux12_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_TIMESTAMP0, buff, 4); + if (ret != 0) + { + return ret; + } *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -3188,12 +3504,10 @@ int32_t lis2dux12_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); - + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_STATUS, + (uint8_t *)&emb_func_status, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_STATUS, - (uint8_t *)&emb_func_status, 1); - *val = emb_func_status.is_fsm_lc; } @@ -3216,12 +3530,10 @@ int32_t lis2dux12_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) lis2dux12_emb_func_en_b_t emb_func_en_b; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); - + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - emb_func_en_b.fsm_en = (uint8_t)val; ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, @@ -3247,16 +3559,11 @@ int32_t lis2dux12_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) lis2dux12_emb_func_en_b_t emb_func_en_b; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); - + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - *val = emb_func_en_b.fsm_en; - - ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); } ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); @@ -3286,11 +3593,10 @@ int32_t lis2dux12_fsm_enable_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_enable, 1); } + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - if ((val->fsm_enable.fsm1_en | val->fsm_enable.fsm2_en | val->fsm_enable.fsm3_en | @@ -3451,12 +3757,10 @@ int32_t lis2dux12_fsm_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); - + ret += lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ODR, + (uint8_t *)&fsm_odr_reg, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ODR, - (uint8_t *)&fsm_odr_reg, 1); - fsm_odr_reg.fsm_odr = (uint8_t)val; ret += lis2dux12_write_reg(ctx, LIS2DUX12_FSM_ODR, (uint8_t *)&fsm_odr_reg, 1); @@ -3485,6 +3789,11 @@ int32_t lis2dux12_fsm_data_rate_get(const stmdev_ctx_t *ctx, ret += lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ODR, (uint8_t *)&fsm_odr_reg, 1); ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (fsm_odr_reg.fsm_odr) { case 0: @@ -3537,12 +3846,11 @@ int32_t lis2dux12_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); - emb_func_init_b.fsm_init = (uint8_t)val; ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B, @@ -3568,12 +3876,10 @@ int32_t lis2dux12_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); - + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); - *val = emb_func_init_b.fsm_init; } @@ -3596,10 +3902,9 @@ int32_t lis2dux12_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); - + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); fifo_reg.fsm_fifo_en = val; ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); } @@ -3623,10 +3928,9 @@ int32_t lis2dux12_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); - + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); *val = fifo_reg.fsm_fifo_en; } @@ -3677,8 +3981,11 @@ int32_t lis2dux12_long_cnt_int_value_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_FSM_LC_TIMEOUT_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -3755,8 +4062,11 @@ int32_t lis2dux12_fsm_start_address_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_FSM_START_ADD_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -3796,27 +4106,30 @@ int32_t lis2dux12_mlc_set(const stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t val) ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - switch (val) + if (ret == 0) { - case LIS2DUX12_MLC_OFF: - emb_en_a.mlc_before_fsm_en = 0; - emb_en_b.mlc_en = 0; - break; - case LIS2DUX12_MLC_ON: - emb_en_a.mlc_before_fsm_en = 0; - emb_en_b.mlc_en = 1; - break; - case LIS2DUX12_MLC_ON_BEFORE_FSM: - emb_en_a.mlc_before_fsm_en = 1; - emb_en_b.mlc_en = 0; - break; - default: - /* do nothing */ - break; - } + switch (val) + { + case LIS2DUX12_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case LIS2DUX12_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case LIS2DUX12_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + /* do nothing */ + break; + } - ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); - ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } } ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); @@ -3846,21 +4159,24 @@ int32_t lis2dux12_mlc_get(const stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t *val) ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) - { - *val = LIS2DUX12_MLC_OFF; - } - else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) - { - *val = LIS2DUX12_MLC_ON; - } - else if (emb_en_a.mlc_before_fsm_en == 1U) - { - *val = LIS2DUX12_MLC_ON_BEFORE_FSM; - } - else + if (ret == 0) { - /* Do nothing */ + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = LIS2DUX12_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = LIS2DUX12_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = LIS2DUX12_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } } } @@ -3921,10 +4237,10 @@ int32_t lis2dux12_mlc_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_MLC_ODR, (uint8_t *)®, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_MLC_ODR, (uint8_t *)®, 1); reg.mlc_odr = (uint8_t)val; ret += lis2dux12_write_reg(ctx, LIS2DUX12_MLC_ODR, (uint8_t *)®, 1); } @@ -3952,10 +4268,10 @@ int32_t lis2dux12_mlc_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_MLC_ODR, (uint8_t *)®, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_MLC_ODR, (uint8_t *)®, 1); switch (reg.mlc_odr) { @@ -4004,10 +4320,9 @@ int32_t lis2dux12_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); - + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); fifo_reg.mlc_fifo_en = val; ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); } @@ -4031,10 +4346,10 @@ int32_t lis2dux12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); *val = fifo_reg.mlc_fifo_en; } @@ -4047,5 +4362,3 @@ int32_t lis2dux12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.h b/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.h index 8a76fc3..5b34a60 100644 --- a/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.h +++ b/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -2093,7 +2095,6 @@ typedef struct uint8_t sw_reset : 1; /* Restoring configuration registers */ uint8_t boot : 1; /* Restoring calibration parameters */ uint8_t drdy : 1; /* Accelerometer data ready */ - uint8_t power_down : 1; /* Monitors power-down. */ } lis2dux12_status_t; int32_t lis2dux12_status_get(const stmdev_ctx_t *ctx, lis2dux12_status_t *val); @@ -2172,7 +2173,6 @@ int32_t lis2dux12_trigger_sw(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md); typedef struct { uint8_t drdy : 1; - uint8_t timestamp : 1; uint8_t free_fall : 1; uint8_t wake_up : 1; uint8_t wake_up_z : 1; @@ -2190,11 +2190,6 @@ typedef struct uint8_t six_d_zh : 1; uint8_t sleep_change : 1; uint8_t sleep_state : 1; - uint8_t tilt : 1; - uint8_t fifo_bdr : 1; - uint8_t fifo_full : 1; - uint8_t fifo_ovr : 1; - uint8_t fifo_th : 1; } lis2dux12_all_sources_t; int32_t lis2dux12_all_sources_get(const stmdev_ctx_t *ctx, lis2dux12_all_sources_t *val); @@ -2407,18 +2402,26 @@ typedef struct lis2dux12_operation_t operation; lis2dux12_store_t store; uint8_t xl_only : 1; /* only XL samples (16-bit) are stored in FIFO */ - uint8_t watermark : 7; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ uint8_t cfg_change_in_fifo : 1; - lis2dux12_fifo_event_t fifo_event : 1; /* 0: FIFO watermark, 1: FIFO full */ - struct - { - lis2dux12_dec_ts_t dec_ts; /* decimation for timestamp batching*/ - lis2dux12_bdr_xl_t bdr_xl; /* accelerometer batch data rate*/ - } batch; } lis2dux12_fifo_mode_t; int32_t lis2dux12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t val); int32_t lis2dux12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t *val); +int32_t lis2dux12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + lis2dux12_dec_ts_t dec_ts; /* decimation for timestamp batching*/ + lis2dux12_bdr_xl_t bdr_xl; /* accelerometer batch data rate*/ +} lis2dux12_fifo_batch_t; + +int32_t lis2dux12_fifo_batch_set(const stmdev_ctx_t *ctx, lis2dux12_fifo_batch_t val); +int32_t lis2dux12_fifo_batch_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_batch_t *val); + +int32_t lis2dux12_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lis2dux12_fifo_event_t val); +int32_t lis2dux12_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_event_t *val); + int32_t lis2dux12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); int32_t lis2dux12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); @@ -2566,10 +2569,10 @@ typedef enum typedef enum { - LIS2DUX12_ODR_NO_CHANGE = 0, /* no odr change during inactivity state */ - LIS2DUX12_ODR_1_6_HZ = 1, /* set odr to 1.6Hz during inactivity state */ - LIS2DUX12_ODR_3_HZ = 1, /* set odr to 3Hz during inactivity state */ - LIS2DUX12_ODR_25_HZ = 1, /* set odr to 25Hz during inactivity state */ + LIS2DUX12_ODR_NO_CHANGE = 0x0, /* no odr change during inactivity state */ + LIS2DUX12_ODR_1_6_HZ = 0x1, /* set odr to 1.6Hz during inactivity state */ + LIS2DUX12_ODR_3_HZ = 0x2, /* set odr to 3Hz during inactivity state */ + LIS2DUX12_ODR_25_HZ = 0x3, /* set odr to 25Hz during inactivity state */ } lis2dux12_inact_odr_t; typedef struct @@ -2711,5 +2714,3 @@ int32_t lis2dux12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* LIS2DUX12_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.c b/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.c index 1f6f80b..dc847b3 100644 --- a/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.c +++ b/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -166,6 +165,10 @@ int32_t lis2duxs12_init_set(const stmdev_ctx_t *ctx, lis2duxs12_init_t val) ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (val) { case LIS2DUXS12_BOOT: @@ -278,9 +281,12 @@ int32_t lis2duxs12_status_get(const stmdev_ctx_t *ctx, lis2duxs12_status_t *val) ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); - val->sw_reset = ctrl1.sw_reset; - val->boot = ctrl4.boot; - val->drdy = status_register.drdy; + if (ret == 0) + { + val->sw_reset = ctrl1.sw_reset; + val->boot = ctrl4.boot; + val->drdy = status_register.drdy; + } return ret; } @@ -295,16 +301,17 @@ int32_t lis2duxs12_status_get(const stmdev_ctx_t *ctx, lis2duxs12_status_t *val) */ int32_t lis2duxs12_embedded_status_get(const stmdev_ctx_t *ctx, lis2duxs12_embedded_status_t *val) { - lis2duxs12_emb_func_status_t status; + lis2duxs12_emb_func_status_mainpage_t status; int32_t ret; - ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); - ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS, (uint8_t *)&status, 1); - ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS_MAINPAGE, (uint8_t *)&status, 1); - val->is_step_det = status.is_step_det; - val->is_tilt = status.is_tilt; - val->is_sigmot = status.is_sigmot; + if (ret == 0) + { + val->is_step_det = status.is_step_det; + val->is_tilt = status.is_tilt; + val->is_sigmot = status.is_sigmot; + } return ret; } @@ -348,6 +355,11 @@ int32_t lis2duxs12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_data_ ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl1.drdy_pulsed)) { case 0x0: @@ -380,6 +392,10 @@ int32_t lis2duxs12_mode_set(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *val) int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } ctrl5.odr = (uint8_t)val->odr & 0xFU; ctrl5.fs = (uint8_t)val->fs; @@ -469,11 +485,6 @@ int32_t lis2duxs12_mode_set(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *val) break; } - if (ret != 0) - { - return ret; - } - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1); ctrl3.hp_en = (((uint8_t)val->odr & 0x30U) == 0x10U) ? 1U : 0U; @@ -504,6 +515,11 @@ int32_t lis2duxs12_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_md_t *val) ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t *)&ctrl5, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5.odr) { case 0x00: @@ -632,7 +648,10 @@ int32_t lis2duxs12_t_ah_qvar_dis_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&temp, 1); - *val = temp.t_ah_qvar_dis; + if (ret == 0) + { + *val = temp.t_ah_qvar_dis; + } return ret; } @@ -699,7 +718,10 @@ int32_t lis2duxs12_disable_hard_reset_from_cs_set(const stmdev_ctx_t *ctx, uint8 ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); fifo_ctrl.dis_hard_rst_cs = (val == 1) ? PROPERTY_ENABLE : PROPERTY_DISABLE; - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret == 0) + { + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + } return ret; } @@ -717,7 +739,10 @@ int32_t lis2duxs12_disable_hard_reset_from_cs_get(const stmdev_ctx_t *ctx, uint8 int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - *val = fifo_ctrl.dis_hard_rst_cs; + if (ret == 0) + { + *val = fifo_ctrl.dis_hard_rst_cs; + } return ret; } @@ -765,6 +790,11 @@ int32_t lis2duxs12_all_sources_get(const stmdev_ctx_t *ctx, lis2duxs12_all_sourc ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_SRC, (uint8_t *)&wu_src, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_SRC, (uint8_t *)&tap_src, 1); + if (ret != 0) + { + return ret; + } + val->six_d = sixd_src.d6d_ia; val->six_d_xl = sixd_src.xl; val->six_d_xh = sixd_src.xh; @@ -808,6 +838,11 @@ int32_t lis2duxs12_xl_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *m ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_X_L, buff, 6); + if (ret != 0) + { + return ret; + } + /* acceleration conversion */ j = 0U; for (i = 0U; i < 3U; i++) @@ -855,6 +890,11 @@ int32_t lis2duxs12_outt_data_get(const stmdev_ctx_t *ctx, ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_T_AH_QVAR_L, buff, 2); + if (ret != 0) + { + return ret; + } + data->heat.raw = (int16_t)buff[1U]; data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[0]; /* temperature conversion */ @@ -881,6 +921,11 @@ int32_t lis2duxs12_ah_qvar_data_get(const stmdev_ctx_t *ctx, /* Read and discard also OUT_Z_H reg to clear drdy */ ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_T_AH_QVAR_L - 1, buff, 3); + if (ret != 0) + { + return ret; + } + data->raw = (int16_t)buff[2U]; data->raw = (data->raw * 256) + (int16_t) buff[1U]; @@ -904,6 +949,10 @@ int32_t lis2duxs12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2duxs12_xl_sel ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1); + if (ret != 0) + { + return ret; + } switch (val) { @@ -1013,13 +1062,19 @@ int32_t lis2duxs12_i3c_configure_set(const stmdev_ctx_t *ctx, const lis2duxs12_i * @param val configuration params * @retval interface status (MANDATORY: return 0 -> no Error) * - */int32_t lis2duxs12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val) + */ +int32_t lis2duxs12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val) { lis2duxs12_i3c_if_ctrl_t i3c_cfg; int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1); + if (ret != 0) + { + return ret; + } + val->drstdaa_en = i3c_cfg.dis_drstdaa; val->asf_on = i3c_cfg.asf_on; @@ -1084,6 +1139,10 @@ int32_t lis2duxs12_mem_bank_get(const stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t * int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } switch ((func_cfg_access.emb_func_reg_access)) { @@ -1134,12 +1193,20 @@ int32_t lis2duxs12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_ /* page write */ ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_ENABLE; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); /* set page num */ ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -1159,6 +1226,10 @@ int32_t lis2duxs12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_ { msb++; ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -1175,6 +1246,10 @@ int32_t lis2duxs12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_ ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -1217,6 +1292,10 @@ int32_t lis2duxs12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* page read */ ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -1227,6 +1306,10 @@ int32_t lis2duxs12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* set page num */ ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -1252,6 +1335,10 @@ int32_t lis2duxs12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* set page */ ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -1268,6 +1355,10 @@ int32_t lis2duxs12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -1304,8 +1395,11 @@ int32_t lis2duxs12_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EXT_CLK_CFG, (uint8_t *)&clk, 1); - clk.ext_clk_en = val; - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EXT_CLK_CFG, (uint8_t *)&clk, 1); + if (ret == 0) + { + clk.ext_clk_en = val; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EXT_CLK_CFG, (uint8_t *)&clk, 1); + } return ret; } @@ -1324,7 +1418,10 @@ int32_t lis2duxs12_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EXT_CLK_CFG, (uint8_t *)&clk, 1); - *val = clk.ext_clk_en; + if (ret == 0) + { + *val = clk.ext_clk_en; + } return ret; } @@ -1374,12 +1471,15 @@ int32_t lis2duxs12_pin_conf_get(const stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t * ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); - val->cs_pull_up = ~pin_ctrl.cs_pu_dis; - val->int1_pull_down = ~pin_ctrl.pd_dis_int1; - val->int2_pull_down = ~pin_ctrl.pd_dis_int2; - val->sda_pull_up = pin_ctrl.sda_pu_en; - val->sdo_pull_up = pin_ctrl.sdo_pu_en; - val->int1_int2_push_pull = ~pin_ctrl.pp_od; + if (ret == 0) + { + val->cs_pull_up = ~pin_ctrl.cs_pu_dis; + val->int1_pull_down = ~pin_ctrl.pd_dis_int1; + val->int2_pull_down = ~pin_ctrl.pd_dis_int2; + val->sda_pull_up = pin_ctrl.sda_pu_en; + val->sdo_pull_up = pin_ctrl.sdo_pu_en; + val->int1_int2_push_pull = ~pin_ctrl.pp_od; + } return ret; } @@ -1423,6 +1523,11 @@ int32_t lis2duxs12_int_pin_polarity_get(const stmdev_ctx_t *ctx, lis2duxs12_int_ ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + switch ((pin_ctrl.h_lactive)) { case 0x0: @@ -1478,6 +1583,10 @@ int32_t lis2duxs12_spi_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_spi_mode *va int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch ((pin_ctrl.sim)) { @@ -1734,8 +1843,8 @@ int32_t lis2duxs12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2duxs12_pin_in lis2duxs12_md2_cfg_t md2_cfg; int32_t ret; - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL2, (uint8_t *)&ctrl3, 1); - ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD1_CFG, (uint8_t *)&md2_cfg, 1); + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MD2_CFG, (uint8_t *)&md2_cfg, 1); if (ret == 0) { @@ -1930,19 +2039,22 @@ int32_t lis2duxs12_embedded_int_cfg_set(const stmdev_ctx_t *ctx, { ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); - switch (val) + if (ret == 0) { - case LIS2DUXS12_EMBEDDED_INT_LEVEL: - page_rw.emb_func_lir = 0; - break; + switch (val) + { + case LIS2DUXS12_EMBEDDED_INT_LEVEL: + page_rw.emb_func_lir = 0; + break; - case LIS2DUXS12_EMBEDDED_INT_LATCHED: - default: - page_rw.emb_func_lir = 1; - break; - } + case LIS2DUXS12_EMBEDDED_INT_LATCHED: + default: + page_rw.emb_func_lir = 1; + break; + } - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); + } } ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); @@ -1969,13 +2081,16 @@ int32_t lis2duxs12_embedded_int_cfg_get(const stmdev_ctx_t *ctx, { ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); - if (page_rw.emb_func_lir == 0U) - { - *val = LIS2DUXS12_EMBEDDED_INT_LEVEL; - } - else + if (ret == 0) { - *val = LIS2DUXS12_EMBEDDED_INT_LATCHED; + if (page_rw.emb_func_lir == 0U) + { + *val = LIS2DUXS12_EMBEDDED_INT_LEVEL; + } + else + { + *val = LIS2DUXS12_EMBEDDED_INT_LATCHED; + } } } @@ -2009,12 +2124,10 @@ int32_t lis2duxs12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t lis2duxs12_ctrl4_t ctrl4; lis2duxs12_fifo_ctrl_t fifo_ctrl; lis2duxs12_fifo_wtm_t fifo_wtm; - lis2duxs12_fifo_batch_dec_t fifo_batch; int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); if (ret == 0) @@ -2036,23 +2149,11 @@ int32_t lis2duxs12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t /* Set xl_only_fifo */ fifo_wtm.xl_only_fifo = val.xl_only; - /* set batching info */ - fifo_batch.dec_ts_batch = (uint8_t)val.batch.dec_ts; - fifo_batch.bdr_xl = (uint8_t)val.batch.bdr_xl; - fifo_ctrl.cfg_chg_en = val.cfg_change_in_fifo; - /* set watermark */ - if (val.watermark > 0U) - { - fifo_ctrl.stop_on_fth = (val.fifo_event == LIS2DUXS12_FIFO_EV_WTM) ? 1 : 0; - fifo_wtm.fth = val.watermark; - } - - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); } return ret; @@ -2071,12 +2172,10 @@ int32_t lis2duxs12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t lis2duxs12_ctrl4_t ctrl4; lis2duxs12_fifo_ctrl_t fifo_ctrl; lis2duxs12_fifo_wtm_t fifo_wtm; - lis2duxs12_fifo_batch_dec_t fifo_batch; int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); if (ret == 0) @@ -2098,12 +2197,155 @@ int32_t lis2duxs12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t /* Get xl_only_fifo */ val->xl_only = fifo_wtm.xl_only_fifo; - /* get batching info */ - val->batch.dec_ts = (lis2duxs12_dec_ts_t)fifo_batch.dec_ts_batch; - val->batch.bdr_xl = (lis2duxs12_bdr_xl_t)fifo_batch.bdr_xl; + } + + return ret; +} + +/** + * @brief FIFO watermark threshold.[set] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold, maximum value is 127. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lis2duxs12_fifo_wtm_t fifo_wtm; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + + if (ret == 0) + { + fifo_wtm.fth = val; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark threshold.[get] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold, maximum value is 127. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2duxs12_fifo_wtm_t fifo_wtm; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + + if (ret == 0) + { + *val = fifo_wtm.fth; + } + + return ret; +} + + +/** + * @brief FIFO batch.[set] + * + * @param ctx read / write interface definitions + * @param val Select value for bdr_xl: BDR_XL_ODR, BDR_XL_ODR_DIV_2, BDR_XL_ODR_DIV_4, BDR_XL_ODR_DIV_8, + * BDR_XL_ODR_DIV_16, BDR_XL_ODR_DIV_32, BDR_XL_ODR_DIV_64, BDR_XL_ODR_OFF; + * and dec_ts: DEC_TS_OFF, DEC_TS_1, DEC_TS_8, DEC_TS_32 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_fifo_batch_set(const stmdev_ctx_t *ctx, lis2duxs12_fifo_batch_t val) +{ + lis2duxs12_fifo_batch_dec_t fifo_batch; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + + if (ret == 0) + { + fifo_batch.dec_ts_batch = (uint8_t)val.dec_ts; + fifo_batch.bdr_xl = (uint8_t)val.bdr_xl; + + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + } + + return ret; +} + +/** + * @brief FIFO batch.[get] + * + * @param ctx read / write interface definitions + * @param val Select value for bdr_xl: BDR_XL_ODR, BDR_XL_ODR_DIV_2, BDR_XL_ODR_DIV_4, BDR_XL_ODR_DIV_8, + * BDR_XL_ODR_DIV_16, BDR_XL_ODR_DIV_32, BDR_XL_ODR_DIV_64, BDR_XL_ODR_OFF; + * and dec_ts: DEC_TS_OFF, DEC_TS_1, DEC_TS_8, DEC_TS_32 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_fifo_batch_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_batch_t *val) +{ + lis2duxs12_fifo_batch_dec_t fifo_batch; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1); + + if (ret == 0) + { + val->dec_ts = fifo_batch.dec_ts_batch; + val->bdr_xl = fifo_batch.bdr_xl; + } + + return ret; +} + +/** + * @brief FIFO stop on wtm.[set] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable stop on wtm functionality. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lis2duxs12_fifo_event_t val) +{ + lis2duxs12_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - /* get watermark */ - val->watermark = fifo_wtm.fth; + if (ret == 0) + { + fifo_ctrl.stop_on_fth = (val == LIS2DUXS12_FIFO_EV_WTM) ? 1 : 0; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + } + + return ret; +} + +/** + * @brief FIFO stop on wtm.[get] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable stop on wtm functionality. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_event_t *val) +{ + lis2duxs12_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + + if (ret == 0) + { + *val = (fifo_ctrl.stop_on_fth == 1) ? LIS2DUXS12_FIFO_EV_WTM : LIS2DUXS12_FIFO_EV_FULL; } return ret; @@ -2124,7 +2366,10 @@ int32_t lis2duxs12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_STATUS2, &buff, 1); - *val = buff; + if (ret == 0) + { + *val = buff; + } return ret; } @@ -2136,7 +2381,10 @@ int32_t lis2duxs12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); - *val = fifo_status1.fifo_wtm_ia; + if (ret == 0) + { + *val = fifo_status1.fifo_wtm_ia; + } return ret; } @@ -2148,7 +2396,10 @@ int32_t lis2duxs12_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_ ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); - *val = (lis2duxs12_fifo_sensor_tag_t) fifo_tag.tag_sensor; + if (ret == 0) + { + *val = (lis2duxs12_fifo_sensor_tag_t) fifo_tag.tag_sensor; + } return ret; } @@ -2171,6 +2422,10 @@ int32_t lis2duxs12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t int32_t ret, i; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); + if (ret != 0) + { + return ret; + } data->tag = fifo_tag.tag_sensor; switch (fifo_tag.tag_sensor) @@ -2179,6 +2434,10 @@ int32_t lis2duxs12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t case LIS2DUXS12_XL_ONLY_2X_TAG_2ND: /* A FIFO sample consists of 2X 8-bits 3-axis XL at ODR/2 */ ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } for (i = 0; i < 3; i++) { data->xl[0].raw[i] = (int16_t)fifo_raw[i] * 256; @@ -2188,6 +2447,10 @@ int32_t lis2duxs12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t case LIS2DUXS12_XL_AND_QVAR: case LIS2DUXS12_XL_TEMP_TAG: ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } if (fmd->xl_only == 0x0U) { /* A FIFO sample consists of 12-bits 3-axis XL + T at ODR*/ @@ -2219,6 +2482,10 @@ int32_t lis2duxs12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t break; case LIS2DUXS12_TIMESTAMP_TAG: ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } data->cfg_chg.cfg_change = fifo_raw[0] >> 7; data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU; @@ -2237,6 +2504,10 @@ int32_t lis2duxs12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t case LIS2DUXS12_STEP_COUNTER_TAG: ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } data->pedo.steps = fifo_raw[1]; data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0]; @@ -2327,6 +2598,10 @@ int32_t lis2duxs12_ah_qvar_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_AH_QVAR_CFG, (uint8_t *)&ah_qvar_cfg, 1); + if (ret != 0) + { + return ret; + } switch (ah_qvar_cfg.ah_qvar_gain) { @@ -2413,19 +2688,23 @@ int32_t lis2duxs12_stpcnt_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mo ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); - if ((val.false_step_rej == PROPERTY_ENABLE) - && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) + if (ret == 0) { - emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; - } + if ((val.false_step_rej == PROPERTY_ENABLE) + && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) + { + emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + } - emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo; - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); + emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); - emb_func_en_a.pedo_en = val.step_counter_enable; - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.pedo_en = val.step_counter_enable; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); @@ -2450,17 +2729,24 @@ int32_t lis2duxs12_stpcnt_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mo int32_t lis2duxs12_stpcnt_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t *val) { lis2duxs12_emb_func_en_a_t emb_func_en_a; + lis2duxs12_emb_func_fifo_en_t emb_func_fifo_en; lis2duxs12_pedo_cmd_reg_t pedo_cmd_reg; int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); - val->false_step_rej = pedo_cmd_reg.fp_rejection_en; - val->step_counter_enable = emb_func_en_a.pedo_en; + + if (ret == 0) + { + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + val->step_counter_in_fifo = emb_func_fifo_en.step_counter_fifo_en; + } return ret; } @@ -2482,8 +2768,11 @@ int32_t lis2duxs12_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_STEP_COUNTER_L, &buff[0], 2); ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -2502,9 +2791,9 @@ int32_t lis2duxs12_stpcnt_rst_step_set(const stmdev_ctx_t *ctx) int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); emb_func_src.pedo_rst_step = 1; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); } @@ -2549,7 +2838,10 @@ int32_t lis2duxs12_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); - *val = pedo_deb_steps_conf.deb_step; + if (ret == 0) + { + *val = pedo_deb_steps_conf.deb_step; + } return ret; } @@ -2591,8 +2883,11 @@ int32_t lis2duxs12_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -2611,6 +2906,10 @@ int32_t lis2duxs12_smart_power_set(const stmdev_ctx_t *ctx, lis2duxs12_smart_pow int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } ctrl1.smart_power_en = val.enable; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); @@ -2642,12 +2941,16 @@ int32_t lis2duxs12_smart_power_get(const stmdev_ctx_t *ctx, lis2duxs12_smart_pow int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); - val->enable = ctrl1.smart_power_en; ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_SMART_POWER_CTRL, (uint8_t *)&smart_power_ctrl, 1); - val->window = smart_power_ctrl.smart_power_ctrl_win; - val->duration = smart_power_ctrl.smart_power_ctrl_dur; + + if (ret == 0) + { + val->enable = ctrl1.smart_power_en; + val->window = smart_power_ctrl.smart_power_ctrl_win; + val->duration = smart_power_ctrl.smart_power_ctrl_dur; + } return ret; } @@ -2677,9 +2980,9 @@ int32_t lis2duxs12_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); emb_func_en_a.tilt_en = val; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } @@ -2703,9 +3006,9 @@ int32_t lis2duxs12_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); *val = emb_func_en_a.tilt_en; } @@ -2739,9 +3042,9 @@ int32_t lis2duxs12_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); emb_func_en_a.sign_motion_en = val; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } @@ -2765,9 +3068,9 @@ int32_t lis2duxs12_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); *val = emb_func_en_a.sign_motion_en; } @@ -2810,9 +3113,9 @@ int32_t lis2duxs12_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); } + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); free_fall.ff_dur = val & 0x1FU; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); } @@ -2837,7 +3140,10 @@ int32_t lis2duxs12_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); - *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur; + if (ret == 0) + { + *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur; + } return ret; } @@ -2856,8 +3162,11 @@ int32_t lis2duxs12_ff_thresholds_set(const stmdev_ctx_t *ctx, lis2duxs12_ff_thre int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); - free_fall.ff_ths = ((uint8_t)val & 0x7U); - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = ((uint8_t)val & 0x7U); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); + } return ret; } @@ -2877,6 +3186,11 @@ int32_t lis2duxs12_ff_thresholds_get(const stmdev_ctx_t *ctx, lis2duxs12_ff_thre ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } + switch (free_fall.ff_ths) { case 0x0: @@ -2969,6 +3283,10 @@ int32_t lis2duxs12_sixd_config_get(const stmdev_ctx_t *ctx, lis2duxs12_sixd_conf int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD, (uint8_t *)&sixd, 1); + if (ret != 0) + { + return ret; + } val->mode = (lis2duxs12_mode_t)sixd.d4d_en; @@ -3276,7 +3594,10 @@ int32_t lis2duxs12_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); - *val = int_cfg.timestamp_en; + if (ret == 0) + { + *val = int_cfg.timestamp_en; + } return ret; } @@ -3297,6 +3618,10 @@ int32_t lis2duxs12_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_TIMESTAMP0, buff, 4); + if (ret != 0) + { + return ret; + } *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -3334,12 +3659,10 @@ int32_t lis2duxs12_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); - + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS, + (uint8_t *)&emb_func_status, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS, - (uint8_t *)&emb_func_status, 1); - *val = emb_func_status.is_fsm_lc; } @@ -3362,12 +3685,10 @@ int32_t lis2duxs12_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) lis2duxs12_emb_func_en_b_t emb_func_en_b; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); - + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - emb_func_en_b.fsm_en = (uint8_t)val; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, @@ -3393,16 +3714,11 @@ int32_t lis2duxs12_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) lis2duxs12_emb_func_en_b_t emb_func_en_b; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); - + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - *val = emb_func_en_b.fsm_en; - - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); } ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); @@ -3432,11 +3748,10 @@ int32_t lis2duxs12_fsm_enable_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_enable, 1); } + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - if ((val->fsm_enable.fsm1_en | val->fsm_enable.fsm2_en | val->fsm_enable.fsm3_en | @@ -3597,12 +3912,10 @@ int32_t lis2duxs12_fsm_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); - + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ODR, + (uint8_t *)&fsm_odr_reg, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ODR, - (uint8_t *)&fsm_odr_reg, 1); - fsm_odr_reg.fsm_odr = (uint8_t)val; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_FSM_ODR, (uint8_t *)&fsm_odr_reg, 1); @@ -3631,6 +3944,11 @@ int32_t lis2duxs12_fsm_data_rate_get(const stmdev_ctx_t *ctx, ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ODR, (uint8_t *)&fsm_odr_reg, 1); ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (fsm_odr_reg.fsm_odr) { case 0: @@ -3683,12 +4001,11 @@ int32_t lis2duxs12_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); - emb_func_init_b.fsm_init = (uint8_t)val; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B, @@ -3714,12 +4031,10 @@ int32_t lis2duxs12_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); - + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); - *val = emb_func_init_b.fsm_init; } @@ -3742,10 +4057,9 @@ int32_t lis2duxs12_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); - + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); fifo_reg.fsm_fifo_en = val; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); } @@ -3769,10 +4083,9 @@ int32_t lis2duxs12_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); - + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); *val = fifo_reg.fsm_fifo_en; } @@ -3823,8 +4136,11 @@ int32_t lis2duxs12_long_cnt_int_value_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_LC_TIMEOUT_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -3901,8 +4217,11 @@ int32_t lis2duxs12_fsm_start_address_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_START_ADD_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -3942,27 +4261,30 @@ int32_t lis2duxs12_mlc_set(const stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val) ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - switch (val) + if (ret == 0) { - case LIS2DUXS12_MLC_OFF: - emb_en_a.mlc_before_fsm_en = 0; - emb_en_b.mlc_en = 0; - break; - case LIS2DUXS12_MLC_ON: - emb_en_a.mlc_before_fsm_en = 0; - emb_en_b.mlc_en = 1; - break; - case LIS2DUXS12_MLC_ON_BEFORE_FSM: - emb_en_a.mlc_before_fsm_en = 1; - emb_en_b.mlc_en = 0; - break; - default: - /* do nothing */ - break; - } + switch (val) + { + case LIS2DUXS12_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case LIS2DUXS12_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case LIS2DUXS12_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + /* do nothing */ + break; + } - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } } ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); @@ -3992,21 +4314,24 @@ int32_t lis2duxs12_mlc_get(const stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t *val) ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) - { - *val = LIS2DUXS12_MLC_OFF; - } - else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) - { - *val = LIS2DUXS12_MLC_ON; - } - else if (emb_en_a.mlc_before_fsm_en == 1U) - { - *val = LIS2DUXS12_MLC_ON_BEFORE_FSM; - } - else + if (ret == 0) { - /* Do nothing */ + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = LIS2DUXS12_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = LIS2DUXS12_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = LIS2DUXS12_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } } } @@ -4067,10 +4392,10 @@ int32_t lis2duxs12_mlc_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1); reg.mlc_odr = (uint8_t)val; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1); } @@ -4098,10 +4423,10 @@ int32_t lis2duxs12_mlc_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_ODR, (uint8_t *)®, 1); switch (reg.mlc_odr) { @@ -4150,10 +4475,9 @@ int32_t lis2duxs12_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); - + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); fifo_reg.mlc_fifo_en = val; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); } @@ -4177,10 +4501,10 @@ int32_t lis2duxs12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); *val = fifo_reg.mlc_fifo_en; } @@ -4193,5 +4517,3 @@ int32_t lis2duxs12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.h b/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.h index ef9f093..f852c68 100644 --- a/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.h +++ b/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -2115,7 +2117,6 @@ typedef struct uint8_t sw_reset : 1; /* Restoring configuration registers */ uint8_t boot : 1; /* Restoring calibration parameters */ uint8_t drdy : 1; /* Accelerometer data ready */ - uint8_t power_down : 1; /* Monitors power-down. */ } lis2duxs12_status_t; int32_t lis2duxs12_status_get(const stmdev_ctx_t *ctx, lis2duxs12_status_t *val); @@ -2194,7 +2195,6 @@ int32_t lis2duxs12_trigger_sw(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md typedef struct { uint8_t drdy : 1; - uint8_t timestamp : 1; uint8_t free_fall : 1; uint8_t wake_up : 1; uint8_t wake_up_z : 1; @@ -2212,11 +2212,6 @@ typedef struct uint8_t six_d_zh : 1; uint8_t sleep_change : 1; uint8_t sleep_state : 1; - uint8_t tilt : 1; - uint8_t fifo_bdr : 1; - uint8_t fifo_full : 1; - uint8_t fifo_ovr : 1; - uint8_t fifo_th : 1; } lis2duxs12_all_sources_t; int32_t lis2duxs12_all_sources_get(const stmdev_ctx_t *ctx, lis2duxs12_all_sources_t *val); @@ -2439,18 +2434,26 @@ typedef struct lis2duxs12_operation_t operation; lis2duxs12_store_t store; uint8_t xl_only : 1; /* only XL samples (16-bit) are stored in FIFO */ - uint8_t watermark : 7; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ uint8_t cfg_change_in_fifo : 1; - lis2duxs12_fifo_event_t fifo_event : 1; /* 0: FIFO watermark, 1: FIFO full */ - struct - { - lis2duxs12_dec_ts_t dec_ts; /* decimation for timestamp batching*/ - lis2duxs12_bdr_xl_t bdr_xl; /* accelerometer batch data rate*/ - } batch; } lis2duxs12_fifo_mode_t; int32_t lis2duxs12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val); int32_t lis2duxs12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val); +int32_t lis2duxs12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + lis2duxs12_dec_ts_t dec_ts; /* decimation for timestamp batching*/ + lis2duxs12_bdr_xl_t bdr_xl; /* accelerometer batch data rate*/ +} lis2duxs12_fifo_batch_t; + +int32_t lis2duxs12_fifo_batch_set(const stmdev_ctx_t *ctx, lis2duxs12_fifo_batch_t val); +int32_t lis2duxs12_fifo_batch_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_batch_t *val); + +int32_t lis2duxs12_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lis2duxs12_fifo_event_t val); +int32_t lis2duxs12_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_event_t *val); + int32_t lis2duxs12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); int32_t lis2duxs12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); @@ -2641,10 +2644,10 @@ typedef enum typedef enum { - LIS2DUXS12_ODR_NO_CHANGE = 0, /* no odr change during inactivity state */ - LIS2DUXS12_ODR_1_6_HZ = 1, /* set odr to 1.6Hz during inactivity state */ - LIS2DUXS12_ODR_3_HZ = 1, /* set odr to 3Hz during inactivity state */ - LIS2DUXS12_ODR_25_HZ = 1, /* set odr to 25Hz during inactivity state */ + LIS2DUXS12_ODR_NO_CHANGE = 0x0, /* no odr change during inactivity state */ + LIS2DUXS12_ODR_1_6_HZ = 0x1, /* set odr to 1.6Hz during inactivity state */ + LIS2DUXS12_ODR_3_HZ = 0x2, /* set odr to 3Hz during inactivity state */ + LIS2DUXS12_ODR_25_HZ = 0x3, /* set odr to 25Hz during inactivity state */ } lis2duxs12_inact_odr_t; typedef struct @@ -2786,5 +2789,3 @@ int32_t lis2duxs12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* LIS2DUXS12_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c index ed65bf0..46ce5ea 100644 --- a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c +++ b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -214,11 +213,10 @@ int32_t lis2dw12_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1); + ret += lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1); if (ret == 0) { - ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1); - switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) + ctrl1.lp_mode)) { @@ -354,11 +352,10 @@ int32_t lis2dw12_data_rate_get(const stmdev_ctx_t *ctx, lis2dw12_odr_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1); + ret += lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1); if (ret == 0) { - ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1); - switch ((ctrl3.slp_mode << 4) + ctrl1.odr) { case LIS2DW12_XL_ODR_OFF: @@ -457,6 +454,9 @@ int32_t lis2dw12_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.bdu; return ret; @@ -501,6 +501,8 @@ int32_t lis2dw12_full_scale_get(const stmdev_ctx_t *ctx, lis2dw12_fs_t *val) ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.fs) { case LIS2DW12_2g: @@ -559,6 +561,9 @@ int32_t lis2dw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.drdy; return ret; @@ -583,7 +588,7 @@ int32_t lis2dw12_all_sources_get(const stmdev_ctx_t *ctx, } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -602,7 +607,7 @@ int32_t lis2dw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -621,7 +626,7 @@ int32_t lis2dw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -640,7 +645,7 @@ int32_t lis2dw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -659,7 +664,7 @@ int32_t lis2dw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[set] * @@ -678,7 +683,7 @@ int32_t lis2dw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on bit USR_OFF_W. The value must be * in the range [-127 127].[get] * @@ -740,6 +745,8 @@ int32_t lis2dw12_offset_weight_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.usr_off_w) { case LIS2DW12_LSb_977ug: @@ -772,7 +779,7 @@ int32_t lis2dw12_offset_weight_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers - * together express a 16-bit word in two’s complement.[get] + * together express a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param val buffer that stores data read @@ -785,6 +792,9 @@ int32_t lis2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_T_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -793,7 +803,7 @@ int32_t lis2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed as - * a 16-bit word in two’s complement.[get] + * a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param val buffer that stores data read @@ -806,6 +816,9 @@ int32_t lis2dw12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_X_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -885,6 +898,9 @@ int32_t lis2dw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.if_add_inc; return ret; @@ -928,6 +944,9 @@ int32_t lis2dw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.soft_reset; return ret; @@ -971,6 +990,9 @@ int32_t lis2dw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.boot; return ret; @@ -1015,6 +1037,8 @@ int32_t lis2dw12_self_test_get(const stmdev_ctx_t *ctx, lis2dw12_st_t *val) ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.st) { case LIS2DW12_XL_ST_DISABLE: @@ -1078,6 +1102,8 @@ int32_t lis2dw12_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.drdy_pulsed) { case LIS2DW12_DRDY_LATCHED: @@ -1164,12 +1190,11 @@ int32_t lis2dw12_filter_path_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1); + ret += lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, + (uint8_t *) &ctrl_reg7, 1); if (ret == 0) { - ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, - (uint8_t *) &ctrl_reg7, 1); - switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out) { case LIS2DW12_LPF_ON_OUT: @@ -1236,6 +1261,8 @@ int32_t lis2dw12_filter_bandwidth_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.bw_filt) { case LIS2DW12_ODR_DIV_2: @@ -1300,6 +1327,9 @@ int32_t lis2dw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.hp_ref_mode; return ret; @@ -1357,6 +1387,8 @@ int32_t lis2dw12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dw12_sim_t *val) ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sim) { case LIS2DW12_SPI_4_WIRE: @@ -1417,6 +1449,8 @@ int32_t lis2dw12_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.i2c_disable) { case LIS2DW12_I2C_ENABLE: @@ -1476,6 +1510,8 @@ int32_t lis2dw12_cs_mode_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.cs_pu_disc) { case LIS2DW12_PULL_UP_CONNECT: @@ -1547,6 +1583,8 @@ int32_t lis2dw12_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.h_lactive) { case LIS2DW12_ACTIVE_HIGH: @@ -1606,6 +1644,8 @@ int32_t lis2dw12_int_notification_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.lir) { case LIS2DW12_INT_PULSED: @@ -1664,6 +1704,8 @@ int32_t lis2dw12_pin_mode_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.pp_od) { case LIS2DW12_PUSH_PULL: @@ -1699,11 +1741,7 @@ int32_t lis2dw12_pin_int1_route_set(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL, (uint8_t *)&ctrl5_int2_pad_ctrl, 1); - - if (ret == 0) - { - ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); - } + ret += lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); if (ret == 0) { @@ -1771,11 +1809,7 @@ int32_t lis2dw12_pin_int2_route_set(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL, (uint8_t *) &ctrl4_int1_pad_ctrl, 1); - - if (ret == 0) - { - ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); - } + ret += lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); if (ret == 0) { @@ -1862,6 +1896,9 @@ int32_t lis2dw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.int2_on_int1; return ret; @@ -1918,6 +1955,9 @@ int32_t lis2dw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.wk_ths; return ret; @@ -1961,6 +2001,9 @@ int32_t lis2dw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.wake_dur; return ret; @@ -2007,6 +2050,8 @@ int32_t lis2dw12_wkup_feed_data_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.usr_off_on_wu) { case LIS2DW12_HP_FEED: @@ -2099,12 +2144,11 @@ int32_t lis2dw12_act_mode_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) &wake_up_ths, 1); + ret += lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, + (uint8_t *) &wake_up_dur, 1); if (ret == 0) { - ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, - (uint8_t *) &wake_up_dur, 1); - switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on) { case LIS2DW12_NO_DETECTION: @@ -2166,6 +2210,9 @@ int32_t lis2dw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.sleep_dur; return ret; @@ -2222,6 +2269,9 @@ int32_t lis2dw12_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_thsx; return ret; @@ -2265,6 +2315,9 @@ int32_t lis2dw12_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_thsy; return ret; @@ -2311,6 +2364,8 @@ int32_t lis2dw12_tap_axis_priority_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.tap_prior) { case LIS2DW12_XYZ: @@ -2383,6 +2438,9 @@ int32_t lis2dw12_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_thsz; return ret; @@ -2428,6 +2486,9 @@ int32_t lis2dw12_tap_detection_on_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_z_en; return ret; @@ -2473,6 +2534,9 @@ int32_t lis2dw12_tap_detection_on_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_y_en; return ret; @@ -2518,6 +2582,9 @@ int32_t lis2dw12_tap_detection_on_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_x_en; return ret; @@ -2569,6 +2636,9 @@ int32_t lis2dw12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.shock; return ret; @@ -2620,6 +2690,9 @@ int32_t lis2dw12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.quiet; return ret; @@ -2673,6 +2746,9 @@ int32_t lis2dw12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.latency; return ret; @@ -2719,6 +2795,8 @@ int32_t lis2dw12_tap_mode_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.single_double_tap) { case LIS2DW12_ONLY_SINGLE: @@ -2806,6 +2884,9 @@ int32_t lis2dw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg._6d_ths; return ret; @@ -2849,6 +2930,9 @@ int32_t lis2dw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg._4d_en; return ret; @@ -2912,6 +2996,8 @@ int32_t lis2dw12_6d_feed_data_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.lpass_on6d) { case LIS2DW12_ODR_DIV_2_FEED: @@ -2960,12 +3046,8 @@ int32_t lis2dw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); - - if (ret == 0) - { - ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, - (uint8_t *) &free_fall, 1); - } + ret += lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, + (uint8_t *) &free_fall, 1); if (ret == 0) { @@ -3001,11 +3083,11 @@ int32_t lis2dw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) &wake_up_dur, 1); + ret += lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, + (uint8_t *) &free_fall, 1); if (ret == 0) { - ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, - (uint8_t *) &free_fall, 1); *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; } @@ -3053,6 +3135,8 @@ int32_t lis2dw12_ff_threshold_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.ff_ths) { case LIS2DW12_FF_TSH_5LSb_FS2g: @@ -3145,6 +3229,9 @@ int32_t lis2dw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fth; return ret; @@ -3191,6 +3278,8 @@ int32_t lis2dw12_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.fmode) { case LIS2DW12_BYPASS_MODE: @@ -3235,6 +3324,9 @@ int32_t lis2dw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.diff; return ret; @@ -3253,6 +3345,9 @@ int32_t lis2dw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_ovr; return ret; @@ -3271,6 +3366,9 @@ int32_t lis2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_fth; return ret; @@ -3285,5 +3383,3 @@ int32_t lis2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h index 7aea50d..76a2723 100644 --- a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h +++ b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1074,5 +1076,3 @@ int32_t lis2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /*LIS2DW12_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c index a880de5..6242641 100644 --- a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c +++ b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -175,6 +174,9 @@ int32_t lis2hh12_xl_axis_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret != 0) { return ret; } + val->xen = ctrl1.xen; val->yen = ctrl1.yen; val->zen = ctrl1.zen; @@ -221,6 +223,9 @@ int32_t lis2hh12_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl1.bdu; return ret; @@ -267,6 +272,8 @@ int32_t lis2hh12_xl_data_rate_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) { return ret; } + switch (ctrl1.odr) { case LIS2HH12_XL_ODR_OFF: @@ -346,6 +353,8 @@ int32_t lis2hh12_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) { return ret; } + switch (ctrl4.fs) { case LIS2HH12_2g: @@ -409,6 +418,8 @@ int32_t lis2hh12_xl_decimation_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) { return ret; } + switch (ctrl5.dec) { case LIS2HH12_NO_DECIMATION: @@ -450,6 +461,9 @@ int32_t lis2hh12_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.zyxda; return ret; @@ -469,7 +483,7 @@ int32_t lis2hh12_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers together - * express a 16-bit word in two’s complement.[get] + * express a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores the data read.(ptr) @@ -482,6 +496,9 @@ int32_t lis2hh12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_TEMP_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -490,7 +507,7 @@ int32_t lis2hh12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed - * as a 16-bit word in two’s complement.[get] + * as a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores the data read.(ptr) @@ -503,6 +520,9 @@ int32_t lis2hh12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_OUT_X_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -582,6 +602,9 @@ int32_t lis2hh12_dev_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl5.soft_reset; return ret; @@ -625,6 +648,9 @@ int32_t lis2hh12_dev_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl6.boot; return ret; @@ -645,6 +671,9 @@ int32_t lis2hh12_dev_status_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + val->xda = status.xda; val->yda = status.yda; val->zda = status.zda; @@ -711,6 +740,8 @@ int32_t lis2hh12_xl_filter_int_path_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) { return ret; } + switch (ctrl2.hpis) { case LIS2HH12_HP_DISABLE: @@ -749,6 +780,7 @@ int32_t lis2hh12_xl_filter_out_path_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1); if (ret == 0) { @@ -756,11 +788,6 @@ int32_t lis2hh12_xl_filter_out_path_set(const stmdev_ctx_t *ctx, ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1); } - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1); - } - if (ret == 0) { ctrl2.fds = ((uint8_t) val & 0x02U) >> 1; @@ -786,11 +813,10 @@ int32_t lis2hh12_xl_filter_out_path_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1); if (ret == 0) { - ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1); - switch ((ctrl2.fds << 1) | ctrl1.hr) { case LIS2HH12_BYPASSED: @@ -858,6 +884,8 @@ int32_t lis2hh12_xl_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) { return ret; } + switch ((ctrl2.dfc << 4) | ctrl2.hpm) { case LIS2HH12_HP_ODR_DIV_50: @@ -943,6 +971,8 @@ int32_t lis2hh12_xl_filter_low_bandwidth_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) { return ret; } + switch (ctrl2.dfc) { case LIS2HH12_LP_ODR_DIV_50: @@ -1011,6 +1041,8 @@ int32_t lis2hh12_xl_filter_aalias_bandwidth_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) { return ret; } + switch ((ctrl4.bw_scale_odr << 4) | ctrl4.bw) { case LIS2HH12_AUTO: @@ -1081,6 +1113,9 @@ int32_t lis2hh12_xl_filter_reference_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_XL_REFERENCE, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1143,6 +1178,8 @@ int32_t lis2hh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2hh12_sim_t *val) ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) { return ret; } + switch (ctrl4.sim) { case LIS2HH12_SPI_4_WIRE: @@ -1202,6 +1239,8 @@ int32_t lis2hh12_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) { return ret; } + switch (ctrl4.i2c_disable) { case LIS2HH12_I2C_ENABLE: @@ -1263,6 +1302,8 @@ int32_t lis2hh12_auto_increment_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) { return ret; } + switch (ctrl4.if_add_inc) { case LIS2HH12_DISABLE: @@ -1339,6 +1380,9 @@ int32_t lis2hh12_pin_int1_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret != 0) { return ret; } + val->int1_drdy = ctrl3.int1_drdy; val->int1_fth = ctrl3.int1_fth; val->int1_ovr = ctrl3.int1_ovr; @@ -1389,6 +1433,8 @@ int32_t lis2hh12_pin_mode_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) { return ret; } + switch (ctrl5.pp_od) { case LIS2HH12_PUSH_PULL: @@ -1448,6 +1494,8 @@ int32_t lis2hh12_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) { return ret; } + switch (ctrl5.h_lactive) { case LIS2HH12_ACTIVE_HIGH: @@ -1511,6 +1559,9 @@ int32_t lis2hh12_pin_int2_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1); + + if (ret != 0) { return ret; } + val->int2_drdy = ctrl6.int2_drdy; val->int2_fth = ctrl6.int2_fth; val->int2_empty = ctrl6.int2_empty; @@ -1562,6 +1613,8 @@ int32_t lis2hh12_pin_notification_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) { return ret; } + switch (ctrl7.lir) { case LIS2HH12_INT_PULSED: @@ -1596,6 +1649,7 @@ int32_t lis2hh12_pin_logic_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); if (ret == 0) { @@ -1603,11 +1657,6 @@ int32_t lis2hh12_pin_logic_set(const stmdev_ctx_t *ctx, ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1); } - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); - } - if (ret == 0) { ig_cfg2.aoi = (((uint8_t) val & 0x02U) >> 1); @@ -1633,11 +1682,9 @@ int32_t lis2hh12_pin_logic_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); - } + if (ret != 0) { return ret; } switch ((ig_cfg2.aoi << 1) | ig_cfg1.aoi) { @@ -1719,6 +1766,8 @@ int32_t lis2hh12_xl_trshld_mode_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) { return ret; } + switch (ctrl7.dcrm) { case LIS2HH12_RESET_MODE: @@ -1754,6 +1803,7 @@ int32_t lis2hh12_xl_trshld_axis_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); if (ret == 0) { @@ -1766,11 +1816,6 @@ int32_t lis2hh12_xl_trshld_axis_set(const stmdev_ctx_t *ctx, ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1); } - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); - } - if (ret == 0) { ig_cfg2.xlie = (uint8_t)val.ig2_xlie; @@ -1802,11 +1847,9 @@ int32_t lis2hh12_xl_trshld_axis_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); - } + if (ret != 0) { return ret; } val->ig1_xlie = ig_cfg1.xlie; val->ig1_xhie = ig_cfg1.xhie; @@ -1840,11 +1883,9 @@ int32_t lis2hh12_xl_trshld_src_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_SRC1, (uint8_t *)&ig_src1, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_IG_SRC2, (uint8_t *)&ig_src2, 1); - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_SRC2, (uint8_t *)&ig_src2, 1); - } + if (ret != 0) { return ret; } val->ig1_xl = ig_src1.xl; val->ig1_xh = ig_src1.xh; @@ -1948,6 +1989,7 @@ int32_t lis2hh12_xl_trshld_min_sample_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR1, (uint8_t *)&ig_dur1, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t *)&ig_dur2, 1); if (ret == 0) { @@ -1965,11 +2007,6 @@ int32_t lis2hh12_xl_trshld_min_sample_set(const stmdev_ctx_t *ctx, ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_DUR1, (uint8_t *)&ig_dur1, 1); } - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t *)&ig_dur2, 1); - } - if (ret == 0) { if (ig2_sam == 0x00U) @@ -2005,11 +2042,11 @@ int32_t lis2hh12_xl_trshld_min_sample_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR1, (uint8_t *)&ig_dur1, 1); - *ig1_sam = (uint8_t)ig_dur1.dur1; + ret += lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t *)&ig_dur2, 1); if (ret == 0) { - ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t *)&ig_dur2, 1); + *ig1_sam = (uint8_t)ig_dur1.dur1; *ig2_sam = (uint8_t)ig_dur2.dur2; } @@ -2067,6 +2104,9 @@ int32_t lis2hh12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_THS, (uint8_t *)&act_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)act_ths.ths; return ret; @@ -2110,6 +2150,9 @@ int32_t lis2hh12_act_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_DUR, (uint8_t *)&act_dur, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)act_dur.dur; return ret; @@ -2145,6 +2188,8 @@ int32_t lis2hh12_6d_mode_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1); if (ret == 0) { @@ -2152,22 +2197,12 @@ int32_t lis2hh12_6d_mode_set(const stmdev_ctx_t *ctx, ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1); } - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); - } - if (ret == 0) { ig_cfg2._6d = ((uint8_t)val & 0x02U) >> 1; ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); } - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1); - } - if (ret == 0) { ig_cfg1._6d = (uint8_t)val & 0x01U; @@ -2194,16 +2229,10 @@ int32_t lis2hh12_6d_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1); - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1); - } - - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1); - } + if (ret != 0) { return ret; } switch ((ctrl7._4d_ig << 4) | (ig_cfg2._6d << 1) | ig_cfg1._6d) { @@ -2263,12 +2292,8 @@ int32_t lis2hh12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1); - - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL, - (uint8_t *)&fifo_ctrl, 1); - } + ret += lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL, + (uint8_t *)&fifo_ctrl, 1); if (ret == 0) { @@ -2310,6 +2335,9 @@ int32_t lis2hh12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_ctrl.fth; return ret; @@ -2331,6 +2359,8 @@ int32_t lis2hh12_fifo_mode_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL, + (uint8_t *)&fifo_ctrl, 1); if (ret == 0) { @@ -2338,12 +2368,6 @@ int32_t lis2hh12_fifo_mode_set(const stmdev_ctx_t *ctx, ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1); } - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL, - (uint8_t *)&fifo_ctrl, 1); - } - if (ret == 0) { fifo_ctrl.fmode = ((uint8_t)val & 0x0FU); @@ -2370,12 +2394,10 @@ int32_t lis2hh12_fifo_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL, + (uint8_t *)&fifo_ctrl, 1); - if (ret == 0) - { - ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL, - (uint8_t *)&fifo_ctrl, 1); - } + if (ret != 0) { return ret; } switch ((ctrl3.fifo_en << 4) | fifo_ctrl.fmode) { @@ -2430,6 +2452,9 @@ int32_t lis2hh12_fifo_status_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_SRC, (uint8_t *)&fifo_src, 1); + + if (ret != 0) { return ret; } + val->fss = fifo_src.fss; val->empty = fifo_src.empty; val->ovr = fifo_src.ovr; @@ -2492,6 +2517,8 @@ int32_t lis2hh12_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) { return ret; } + switch (ctrl5.st) { case LIS2HH12_ST_DISABLE: @@ -2523,5 +2550,3 @@ int32_t lis2hh12_xl_self_test_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h index 46ed50f..69dd119 100644 --- a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h +++ b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -979,5 +981,3 @@ int32_t lis2hh12_xl_self_test_get(const stmdev_ctx_t *ctx, #endif #endif /* LIS2HH12_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c index 42cd92e..34d1db0 100644 --- a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c +++ b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -125,7 +124,7 @@ float_t lis2mdl_from_lsb_to_celsius(int16_t lsb) /** * @brief These registers comprise a 3 group of 16-bit number and represent * hard-iron offset in order to compensate environmental effects. - * Data format is the same of output data raw: two’s complement + * Data format is the same of output data raw: two's complement * with 1LSb = 1.5mG. These values act on the magnetic output data * value in order to delete the environmental offset.[set] * @@ -153,7 +152,7 @@ int32_t lis2mdl_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief These registers comprise a 3 group of 16-bit number and represent * hard-iron offset in order to compensate environmental effects. - * Data format is the same of output data raw: two’s complement + * Data format is the same of output data raw: two's complement * with 1LSb = 1.5mG. These values act on the magnetic output data * value in order to delete the environmental offset.[get] * @@ -168,6 +167,9 @@ int32_t lis2mdl_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_OFFSET_X_REG_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -219,6 +221,8 @@ int32_t lis2mdl_operating_mode_get(const stmdev_ctx_t *ctx, ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.md) { case LIS2MDL_POWER_DOWN: @@ -280,6 +284,8 @@ int32_t lis2mdl_data_rate_get(const stmdev_ctx_t *ctx, lis2mdl_odr_t *val) ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.odr) { case LIS2MDL_ODR_10Hz: @@ -345,6 +351,8 @@ int32_t lis2mdl_power_mode_get(const stmdev_ctx_t *ctx, lis2mdl_lp_t *val) ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.lp) { case LIS2MDL_HIGH_RESOLUTION: @@ -401,6 +409,9 @@ int32_t lis2mdl_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.comp_temp_en; return ret; @@ -447,6 +458,8 @@ int32_t lis2mdl_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.lpf) { case LIS2MDL_ODR_DIV_2: @@ -506,6 +519,8 @@ int32_t lis2mdl_set_rst_mode_get(const stmdev_ctx_t *ctx, ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.set_rst) { case LIS2MDL_SET_SENS_ODR_DIV_63: @@ -576,6 +591,9 @@ int32_t lis2mdl_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.off_canc_one_shot; return ret; @@ -619,6 +637,9 @@ int32_t lis2mdl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.bdu; return ret; @@ -638,6 +659,9 @@ int32_t lis2mdl_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.zyxda; return ret; @@ -657,6 +681,9 @@ int32_t lis2mdl_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.zyxor; return ret; @@ -676,6 +703,9 @@ int32_t lis2mdl_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_OUTX_L_REG, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -700,6 +730,9 @@ int32_t lis2mdl_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_TEMP_OUT_L_REG, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -773,6 +806,9 @@ int32_t lis2mdl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.soft_rst; return ret; @@ -816,6 +852,9 @@ int32_t lis2mdl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.reboot; return ret; @@ -859,6 +898,9 @@ int32_t lis2mdl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.self_test; return ret; @@ -903,6 +945,8 @@ int32_t lis2mdl_data_format_get(const stmdev_ctx_t *ctx, lis2mdl_ble_t *val) ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.ble) { case LIS2MDL_LSB_AT_LOW_ADD: @@ -994,6 +1038,8 @@ int32_t lis2mdl_offset_int_conf_get(const stmdev_ctx_t *ctx, ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.int_on_dataoff) { case LIS2MDL_CHECK_BEFORE: @@ -1050,6 +1096,9 @@ int32_t lis2mdl_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.drdy_on_pin; return ret; @@ -1093,6 +1142,9 @@ int32_t lis2mdl_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.int_on_pin; return ret; @@ -1154,7 +1206,7 @@ int32_t lis2mdl_int_gen_source_get(const stmdev_ctx_t *ctx, /** * @brief User-defined threshold value for xl interrupt event on generator. - * Data format is the same of output data raw: two’s complement with + * Data format is the same of output data raw: two's complement with * 1LSb = 1.5mG.[set] * * @param ctx read / write interface definitions.(ptr) @@ -1176,7 +1228,7 @@ int32_t lis2mdl_int_gen_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) /** * @brief User-defined threshold value for xl interrupt event on generator. - * Data format is the same of output data raw: two’s complement with + * Data format is the same of output data raw: two's complement with * 1LSb = 1.5mG.[get] * * @param ctx read / write interface definitions.(ptr) @@ -1190,6 +1242,9 @@ int32_t lis2mdl_int_gen_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_THS_L_REG, buff, 2); + + if (ret != 0) { return ret; } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -1248,6 +1303,8 @@ int32_t lis2mdl_spi_mode_get(const stmdev_ctx_t *ctx, lis2mdl_sim_t *val) ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg._4wspi) { case LIS2MDL_SPI_4_WIRE: @@ -1307,6 +1364,8 @@ int32_t lis2mdl_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.i2c_dis) { case LIS2MDL_I2C_ENABLE: @@ -1329,5 +1388,3 @@ int32_t lis2mdl_i2c_interface_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h index 985a98e..9bc653d 100644 --- a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h +++ b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -534,5 +536,3 @@ int32_t lis2mdl_i2c_interface_get(const stmdev_ctx_t *ctx, #endif #endif /* LIS2MDL_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c index 1ccc1ee..2de7e68 100644 --- a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c +++ b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -169,6 +168,9 @@ int32_t lis331dlh_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg1.xen; return ret; @@ -215,6 +217,9 @@ int32_t lis331dlh_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg1.yen; return ret; @@ -261,6 +266,9 @@ int32_t lis331dlh_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg1.zen; return ret; @@ -310,6 +318,8 @@ int32_t lis331dlh_data_rate_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm) { case LIS331DLH_ODR_OFF: @@ -404,6 +414,8 @@ int32_t lis331dlh_reference_mode_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hpm) { case LIS331DLH_NORMAL_MODE: @@ -466,6 +478,8 @@ int32_t lis331dlh_full_scale_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.fs) { case LIS331DLH_2g: @@ -531,6 +545,9 @@ int32_t lis331dlh_block_data_update_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg4.bdu; return ret; @@ -569,6 +586,9 @@ int32_t lis331dlh_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis331dlh_read_reg(ctx, LIS331DLH_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -588,7 +608,7 @@ int32_t lis331dlh_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) /** * @brief Linear acceleration output register. The value is expressed - * as a 16-bit word in two’s complement.[get] + * as a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions(ptr) * @param buff buffer that stores data read @@ -602,6 +622,9 @@ int32_t lis331dlh_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis331dlh_read_reg(ctx, LIS331DLH_OUT_X_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -682,6 +705,9 @@ int32_t lis331dlh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg2.boot; return ret; @@ -730,6 +756,8 @@ int32_t lis331dlh_self_test_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.st) { case LIS331DLH_ST_DISABLE: @@ -796,6 +824,8 @@ int32_t lis331dlh_data_format_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.ble) { case LIS331DLH_LSB_AT_LOW_ADD: @@ -871,6 +901,8 @@ int32_t lis331dlh_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hpcf) { case LIS331DLH_CUT_OFF_8Hz: @@ -941,6 +973,8 @@ int32_t lis331dlh_hp_path_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen) { case LIS331DLH_HP_DISABLE: @@ -1098,6 +1132,8 @@ int32_t lis331dlh_spi_mode_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.sim) { case LIS331DLH_SPI_4_WIRE: @@ -1173,6 +1209,8 @@ int32_t lis331dlh_pin_int1_route_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg3.i1_cfg) { case LIS331DLH_PAD1_INT1_SRC: @@ -1245,6 +1283,8 @@ int32_t lis331dlh_int1_notification_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg3.lir1) { case LIS331DLH_INT1_PULSED: @@ -1307,6 +1347,8 @@ int32_t lis331dlh_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg3.i2_cfg) { case LIS331DLH_PAD2_INT2_SRC: @@ -1379,6 +1421,8 @@ int32_t lis331dlh_int2_notification_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg3.lir2) { case LIS331DLH_INT2_PULSED: @@ -1441,6 +1485,8 @@ int32_t lis331dlh_pin_mode_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg3.pp_od) { case LIS331DLH_PUSH_PULL: @@ -1503,6 +1549,8 @@ int32_t lis331dlh_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg3.ihl) { case LIS331DLH_ACTIVE_HIGH: @@ -1582,6 +1630,9 @@ int32_t lis331dlh_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG, (uint8_t *)&int1_cfg, 1); + + if (ret != 0) { return ret; } + val->int1_xlie = int1_cfg.xlie; val->int1_xhie = int1_cfg.xhie; val->int1_ylie = int1_cfg.ylie; @@ -1636,6 +1687,8 @@ int32_t lis331dlh_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } + switch (int1_cfg.aoi) { case LIS331DLH_INT1_ON_THRESHOLD_OR: @@ -1713,6 +1766,9 @@ int32_t lis331dlh_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS, (uint8_t *)&int1_ths, 1); + + if (ret != 0) { return ret; } + *val = int1_ths.ths; return ret; @@ -1759,6 +1815,9 @@ int32_t lis331dlh_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_DURATION, (uint8_t *)&int1_duration, 1); + + if (ret != 0) { return ret; } + *val = int1_duration.d; return ret; @@ -1812,6 +1871,9 @@ int32_t lis331dlh_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG, (uint8_t *)&int2_cfg, 1); + + if (ret != 0) { return ret; } + val->int2_xlie = int2_cfg.xlie; val->int2_xhie = int2_cfg.xhie; val->int2_ylie = int2_cfg.ylie; @@ -1866,6 +1928,8 @@ int32_t lis331dlh_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } + switch (int2_cfg.aoi) { case LIS331DLH_INT2_ON_THRESHOLD_OR: @@ -1943,6 +2007,9 @@ int32_t lis331dlh_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS, (uint8_t *)&int2_ths, 1); + + if (ret != 0) { return ret; } + *val = int2_ths.ths; return ret; @@ -1989,6 +2056,9 @@ int32_t lis331dlh_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_DURATION, (uint8_t *)&int2_duration, 1); + + if (ret != 0) { return ret; } + *val = int2_duration.d; return ret; @@ -2048,6 +2118,9 @@ int32_t lis331dlh_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis331dlh_read_reg(ctx, LIS331DLH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg5.turnon; return ret; @@ -2111,6 +2184,8 @@ int32_t lis331dlh_int1_6d_mode_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_CFG, (uint8_t *)&int1_cfg, 1); + if (ret != 0) { return ret; } + switch ((int1_cfg.aoi << 1) + int1_cfg._6d) { case LIS331DLH_6D_INT1_DISABLE: @@ -2193,6 +2268,9 @@ int32_t lis331dlh_int1_6d_threshold_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_INT1_THS, (uint8_t *)&int1_ths, 1); + + if (ret != 0) { return ret; } + *val = int1_ths.ths; return ret; @@ -2243,6 +2321,8 @@ int32_t lis331dlh_int2_6d_mode_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_CFG, (uint8_t *)&int2_cfg, 1); + if (ret != 0) { return ret; } + switch ((int2_cfg.aoi << 1) + int2_cfg._6d) { case LIS331DLH_6D_INT2_DISABLE: @@ -2325,6 +2405,9 @@ int32_t lis331dlh_int2_6d_threshold_get(const stmdev_ctx_t *ctx, ret = lis331dlh_read_reg(ctx, LIS331DLH_INT2_THS, (uint8_t *)&int2_ths, 1); + + if (ret != 0) { return ret; } + *val = int2_ths.ths; return ret; @@ -2339,5 +2422,3 @@ int32_t lis331dlh_int2_6d_threshold_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h index 963ebb3..1fd7141 100644 --- a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h +++ b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -822,5 +824,3 @@ int32_t lis331dlh_int2_6d_threshold_get(const stmdev_ctx_t *ctx, #endif #endif /* LIS331DLH_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c index 3183fb4..3a87d57 100644 --- a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c +++ b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -167,6 +166,9 @@ int32_t lis3de_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG_AUX, (uint8_t *)&status_reg_aux, 1); + + if (ret != 0) { return ret; } + *val = status_reg_aux._3da; return ret; @@ -186,6 +188,9 @@ int32_t lis3de_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG_AUX, (uint8_t *)&status_reg_aux, 1); + + if (ret != 0) { return ret; } + *val = status_reg_aux._3or; return ret; @@ -233,6 +238,9 @@ int32_t lis3de_adc_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_OUT_ADC1_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -295,6 +303,8 @@ int32_t lis3de_aux_adc_get(const stmdev_ctx_t *ctx, lis3de_temp_en_t *val) ret = lis3de_read_reg(ctx, LIS3DE_TEMP_CFG_REG, (uint8_t *)&temp_cfg_reg, 1); + if (ret != 0) { return ret; } + if ((temp_cfg_reg.temp_en & temp_cfg_reg.adc_pd) == PROPERTY_ENABLE) { @@ -411,6 +421,8 @@ int32_t lis3de_data_rate_get(const stmdev_ctx_t *ctx, lis3de_odr_t *val) ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1.odr) { case LIS3DE_POWER_DOWN: @@ -503,6 +515,9 @@ int32_t lis3de_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg2.fds; return ret; @@ -561,6 +576,8 @@ int32_t lis3de_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hpcf) { case LIS3DE_AGGRESSIVE: @@ -627,6 +644,8 @@ int32_t lis3de_high_pass_mode_get(const stmdev_ctx_t *ctx, ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hpm) { case LIS3DE_NORMAL_WITH_RST: @@ -692,6 +711,8 @@ int32_t lis3de_full_scale_get(const stmdev_ctx_t *ctx, lis3de_fs_t *val) ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.fs) { case LIS3DE_2g: @@ -756,6 +777,9 @@ int32_t lis3de_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg4.bdu; return ret; @@ -810,6 +834,9 @@ int32_t lis3de_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -828,6 +855,9 @@ int32_t lis3de_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.zyxor; return ret; @@ -930,6 +960,8 @@ int32_t lis3de_self_test_get(const stmdev_ctx_t *ctx, lis3de_st_t *val) ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.st) { case LIS3DE_ST_DISABLE: @@ -990,6 +1022,9 @@ int32_t lis3de_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.boot; return ret; @@ -1119,6 +1154,9 @@ int32_t lis3de_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_IG1_THS, (uint8_t *)&int1_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int1_ths.ths; return ret; @@ -1167,6 +1205,9 @@ int32_t lis3de_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3de_read_reg(ctx, LIS3DE_IG1_DURATION, (uint8_t *)&int1_duration, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int1_duration.d; return ret; @@ -1279,6 +1320,9 @@ int32_t lis3de_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_IG2_THS, (uint8_t *)&int2_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int2_ths.ths; return ret; @@ -1327,6 +1371,9 @@ int32_t lis3de_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3de_read_reg(ctx, LIS3DE_IG2_DURATION, (uint8_t *)&int2_duration, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int2_duration.d; return ret; @@ -1385,6 +1432,8 @@ int32_t lis3de_high_pass_int_conf_get(const stmdev_ctx_t *ctx, ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hp) { case LIS3DE_DISC_FROM_INT_GENERATOR: @@ -1503,6 +1552,9 @@ int32_t lis3de_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.d4d_ig2; return ret; @@ -1553,6 +1605,8 @@ int32_t lis3de_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg5.lir_ig2) { case LIS3DE_INT2_PULSED: @@ -1611,6 +1665,9 @@ int32_t lis3de_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.d4d_ig1; return ret; @@ -1659,6 +1716,8 @@ int32_t lis3de_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg5.lir_ig1) { case LIS3DE_INT1_PULSED: @@ -1762,6 +1821,9 @@ int32_t lis3de_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.fifo_en; return ret; @@ -1808,6 +1870,9 @@ int32_t lis3de_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_ctrl_reg.fth; return ret; @@ -1857,6 +1922,8 @@ int32_t lis3de_fifo_trigger_event_get(const stmdev_ctx_t *ctx, ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl_reg.tr) { case LIS3DE_INT1_GEN: @@ -1917,6 +1984,8 @@ int32_t lis3de_fifo_mode_get(const stmdev_ctx_t *ctx, lis3de_fm_t *val) ret = lis3de_read_reg(ctx, LIS3DE_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl_reg.fm) { case LIS3DE_BYPASS_MODE: @@ -1975,6 +2044,9 @@ int32_t lis3de_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.fss; return ret; @@ -1994,6 +2066,9 @@ int32_t lis3de_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.empty; return ret; @@ -2013,6 +2088,9 @@ int32_t lis3de_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.ovrn_fifo; return ret; @@ -2032,6 +2110,9 @@ int32_t lis3de_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3de_read_reg(ctx, LIS3DE_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.wtm; return ret; @@ -2141,6 +2222,9 @@ int32_t lis3de_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_CLICK_THS, (uint8_t *)&click_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)click_ths.ths; return ret; @@ -2193,6 +2277,8 @@ int32_t lis3de_tap_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis3de_read_reg(ctx, LIS3DE_CLICK_THS, (uint8_t *)&click_ths, 1); + if (ret != 0) { return ret; } + switch (click_ths.lir) { case LIS3DE_TAP_PULSED: @@ -2253,6 +2339,9 @@ int32_t lis3de_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_TIME_LIMIT, (uint8_t *)&time_limit, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)time_limit.tli; return ret; @@ -2305,6 +2394,9 @@ int32_t lis3de_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3de_read_reg(ctx, LIS3DE_TIME_LATENCY, (uint8_t *)&time_latency, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)time_latency.tla; return ret; @@ -2357,6 +2449,9 @@ int32_t lis3de_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3de_read_reg(ctx, LIS3DE_TIME_WINDOW, (uint8_t *)&time_window, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)time_window.tw; return ret; @@ -2417,6 +2512,9 @@ int32_t lis3de_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_ACT_THS, (uint8_t *)&act_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)act_ths.acth; return ret; @@ -2462,6 +2560,9 @@ int32_t lis3de_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3de_read_reg(ctx, LIS3DE_ACT_DUR, (uint8_t *)&act_dur, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)act_dur.actd; return ret; @@ -2519,6 +2620,8 @@ int32_t lis3de_spi_mode_get(const stmdev_ctx_t *ctx, lis3de_sim_t *val) ret = lis3de_read_reg(ctx, LIS3DE_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.sim) { case LIS3DE_SPI_4_WIRE: @@ -2546,5 +2649,3 @@ int32_t lis3de_spi_mode_get(const stmdev_ctx_t *ctx, lis3de_sim_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h index 665c471..550e5e3 100644 --- a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h +++ b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1016,5 +1018,3 @@ int32_t lis3de_spi_mode_get(const stmdev_ctx_t *ctx, lis3de_sim_t *val); #endif #endif /* LIS3DE_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c index e4457a5..b3cbfc2 100644 --- a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c +++ b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -217,6 +216,9 @@ int32_t lis3dh_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX, (uint8_t *)&status_reg_aux, 1); + + if (ret != 0) { return ret; } + *val = status_reg_aux._3da; return ret; @@ -236,6 +238,9 @@ int32_t lis3dh_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX, (uint8_t *)&status_reg_aux, 1); + + if (ret != 0) { return ret; } + *val = status_reg_aux._3or; return ret; @@ -254,6 +259,9 @@ int32_t lis3dh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_OUT_ADC3_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -286,6 +294,9 @@ int32_t lis3dh_adc_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_OUT_ADC1_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -348,6 +359,8 @@ int32_t lis3dh_aux_adc_get(const stmdev_ctx_t *ctx, lis3dh_temp_en_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_TEMP_CFG_REG, (uint8_t *)&temp_cfg_reg, 1); + if (ret != 0) { return ret; } + if ((temp_cfg_reg.temp_en & temp_cfg_reg.adc_pd) == PROPERTY_ENABLE) { @@ -386,12 +399,8 @@ int32_t lis3dh_operating_mode_set(const stmdev_ctx_t *ctx, ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - } + ret += lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, + (uint8_t *)&ctrl_reg4, 1); if (ret == 0) { @@ -440,25 +449,25 @@ int32_t lis3dh_operating_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + ret += lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); - if (ret == 0) - { - ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { + return ret; + } - if (ctrl_reg1.lpen == PROPERTY_ENABLE) - { - *val = LIS3DH_LP_8bit; - } + if (ctrl_reg1.lpen == PROPERTY_ENABLE) + { + *val = LIS3DH_LP_8bit; + } - else if (ctrl_reg4.hr == PROPERTY_ENABLE) - { - *val = LIS3DH_HR_12bit; - } + else if (ctrl_reg4.hr == PROPERTY_ENABLE) + { + *val = LIS3DH_HR_12bit; + } - else - { - *val = LIS3DH_NM_10bit; - } + else + { + *val = LIS3DH_NM_10bit; } return ret; @@ -503,6 +512,8 @@ int32_t lis3dh_data_rate_get(const stmdev_ctx_t *ctx, lis3dh_odr_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1.odr) { case LIS3DH_POWER_DOWN: @@ -595,6 +606,9 @@ int32_t lis3dh_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg2.fds; return ret; @@ -653,6 +667,8 @@ int32_t lis3dh_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hpcf) { case LIS3DH_AGGRESSIVE: @@ -719,6 +735,8 @@ int32_t lis3dh_high_pass_mode_get(const stmdev_ctx_t *ctx, ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hpm) { case LIS3DH_NORMAL_WITH_RST: @@ -784,6 +802,8 @@ int32_t lis3dh_full_scale_get(const stmdev_ctx_t *ctx, lis3dh_fs_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.fs) { case LIS3DH_2g: @@ -848,6 +868,9 @@ int32_t lis3dh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg4.bdu; return ret; @@ -902,6 +925,9 @@ int32_t lis3dh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.zyxda; return ret; @@ -920,6 +946,9 @@ int32_t lis3dh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.zyxor; return ret; @@ -938,6 +967,9 @@ int32_t lis3dh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_OUT_X_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1014,6 +1046,8 @@ int32_t lis3dh_self_test_get(const stmdev_ctx_t *ctx, lis3dh_st_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.st) { case LIS3DH_ST_DISABLE: @@ -1075,6 +1109,8 @@ int32_t lis3dh_data_format_get(const stmdev_ctx_t *ctx, lis3dh_ble_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.ble) { case LIS3DH_LSB_AT_LOW_ADD: @@ -1131,6 +1167,9 @@ int32_t lis3dh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.boot; return ret; @@ -1260,6 +1299,9 @@ int32_t lis3dh_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_INT1_THS, (uint8_t *)&int1_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int1_ths.ths; return ret; @@ -1308,6 +1350,9 @@ int32_t lis3dh_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_INT1_DURATION, (uint8_t *)&int1_duration, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int1_duration.d; return ret; @@ -1420,6 +1465,9 @@ int32_t lis3dh_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_INT2_THS, (uint8_t *)&int2_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int2_ths.ths; return ret; @@ -1468,6 +1516,9 @@ int32_t lis3dh_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_INT2_DURATION, (uint8_t *)&int2_duration, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int2_duration.d; return ret; @@ -1526,6 +1577,8 @@ int32_t lis3dh_high_pass_int_conf_get(const stmdev_ctx_t *ctx, ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.hp) { case LIS3DH_DISC_FROM_INT_GENERATOR: @@ -1644,6 +1697,9 @@ int32_t lis3dh_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.d4d_int2; return ret; @@ -1694,6 +1750,8 @@ int32_t lis3dh_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg5.lir_int2) { case LIS3DH_INT2_PULSED: @@ -1752,6 +1810,9 @@ int32_t lis3dh_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.d4d_int1; return ret; @@ -1800,6 +1861,8 @@ int32_t lis3dh_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg5.lir_int1) { case LIS3DH_INT1_PULSED: @@ -1903,6 +1966,9 @@ int32_t lis3dh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.fifo_en; return ret; @@ -1949,6 +2015,9 @@ int32_t lis3dh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_ctrl_reg.fth; return ret; @@ -1998,6 +2067,8 @@ int32_t lis3dh_fifo_trigger_event_get(const stmdev_ctx_t *ctx, ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl_reg.tr) { case LIS3DH_INT1_GEN: @@ -2058,6 +2129,8 @@ int32_t lis3dh_fifo_mode_get(const stmdev_ctx_t *ctx, lis3dh_fm_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG, (uint8_t *)&fifo_ctrl_reg, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl_reg.fm) { case LIS3DH_BYPASS_MODE: @@ -2116,6 +2189,9 @@ int32_t lis3dh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.fss; return ret; @@ -2135,6 +2211,9 @@ int32_t lis3dh_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.empty; return ret; @@ -2154,6 +2233,9 @@ int32_t lis3dh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.ovrn_fifo; return ret; @@ -2173,6 +2255,9 @@ int32_t lis3dh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t *)&fifo_src_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_src_reg.wtm; return ret; @@ -2282,6 +2367,9 @@ int32_t lis3dh_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)click_ths.ths; return ret; @@ -2334,6 +2422,8 @@ int32_t lis3dh_tap_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1); + if (ret != 0) { return ret; } + switch (click_ths.lir_click) { case LIS3DH_TAP_PULSED: @@ -2394,6 +2484,9 @@ int32_t lis3dh_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t *)&time_limit, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)time_limit.tli; return ret; @@ -2446,6 +2539,9 @@ int32_t lis3dh_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LATENCY, (uint8_t *)&time_latency, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)time_latency.tla; return ret; @@ -2498,6 +2594,9 @@ int32_t lis3dh_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_TIME_WINDOW, (uint8_t *)&time_window, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)time_window.tw; return ret; @@ -2558,6 +2657,9 @@ int32_t lis3dh_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_ACT_THS, (uint8_t *)&act_ths, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)act_ths.acth; return ret; @@ -2603,6 +2705,9 @@ int32_t lis3dh_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dh_read_reg(ctx, LIS3DH_ACT_DUR, (uint8_t *)&act_dur, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)act_dur.actd; return ret; @@ -2662,6 +2767,8 @@ int32_t lis3dh_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t *)&ctrl_reg0, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg0.sdo_pu_disc) { case LIS3DH_PULL_UP_DISCONNECT: @@ -2719,6 +2826,8 @@ int32_t lis3dh_spi_mode_get(const stmdev_ctx_t *ctx, lis3dh_sim_t *val) ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.sim) { case LIS3DH_SPI_4_WIRE: @@ -2746,5 +2855,3 @@ int32_t lis3dh_spi_mode_get(const stmdev_ctx_t *ctx, lis3dh_sim_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h index ada8f20..c1d32e2 100644 --- a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h +++ b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1062,5 +1064,3 @@ int32_t lis3dh_spi_mode_get(const stmdev_ctx_t *ctx, lis3dh_sim_t *val); #endif #endif /* LIS3DH_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c index cbc554a..cb9c16a 100644 --- a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c +++ b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -161,6 +160,9 @@ int32_t lis3dhh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg1.bdu; return ret; @@ -207,6 +209,8 @@ int32_t lis3dhh_data_rate_get(const stmdev_ctx_t *ctx, ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1.norm_mod_en) { case LIS3DHH_POWER_DOWN: @@ -239,6 +243,9 @@ int32_t lis3dhh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_OUT_TEMP_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; *val = (*val / 16); @@ -260,6 +267,9 @@ int32_t lis3dhh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_OUT_X_L_XL, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -284,6 +294,9 @@ int32_t lis3dhh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.zyxda; return ret; @@ -303,6 +316,9 @@ int32_t lis3dhh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.zyxor; return ret; @@ -375,6 +391,9 @@ int32_t lis3dhh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg1.sw_reset; return ret; @@ -418,6 +437,9 @@ int32_t lis3dhh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg1.boot; return ret; @@ -462,6 +484,8 @@ int32_t lis3dhh_self_test_get(const stmdev_ctx_t *ctx, lis3dhh_st_t *val) ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.st) { case LIS3DHH_ST_DISABLE: @@ -525,6 +549,8 @@ int32_t lis3dhh_filter_config_get(const stmdev_ctx_t *ctx, ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.dsp) { case LIS3DHH_LINEAR_PHASE_440Hz: @@ -621,6 +647,8 @@ int32_t lis3dhh_drdy_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1.drdy_pulse) { case LIS3DHH_LATCHED: @@ -682,6 +710,8 @@ int32_t lis3dhh_int1_mode_get(const stmdev_ctx_t *ctx, ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) { return ret; } + switch (int1_ctrl.int1_ext) { case LIS3DHH_PIN_AS_INTERRUPT: @@ -740,6 +770,9 @@ int32_t lis3dhh_fifo_threshold_on_int1_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + + if (ret != 0) { return ret; } + *val = int1_ctrl.int1_fth; return ret; @@ -783,6 +816,9 @@ int32_t lis3dhh_fifo_full_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + + if (ret != 0) { return ret; } + *val = int1_ctrl.int1_fss5; return ret; @@ -826,6 +862,9 @@ int32_t lis3dhh_fifo_ovr_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + + if (ret != 0) { return ret; } + *val = int1_ctrl.int1_ovr; return ret; @@ -869,6 +908,9 @@ int32_t lis3dhh_boot_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + + if (ret != 0) { return ret; } + *val = int1_ctrl.int1_boot; return ret; @@ -912,6 +954,9 @@ int32_t lis3dhh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + + if (ret != 0) { return ret; } + *val = int1_ctrl.int1_drdy; return ret; @@ -957,6 +1002,9 @@ int32_t lis3dhh_fifo_threshold_on_int2_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + if (ret != 0) { return ret; } + *val = int2_ctrl.int2_fth; return ret; @@ -1000,6 +1048,9 @@ int32_t lis3dhh_fifo_full_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + if (ret != 0) { return ret; } + *val = int2_ctrl.int2_fss5; return ret; @@ -1043,6 +1094,9 @@ int32_t lis3dhh_fifo_ovr_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + if (ret != 0) { return ret; } + *val = int2_ctrl.int2_ovr; return ret; @@ -1086,6 +1140,9 @@ int32_t lis3dhh_boot_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + if (ret != 0) { return ret; } + *val = int2_ctrl.int2_boot; return ret; @@ -1129,6 +1186,9 @@ int32_t lis3dhh_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + if (ret != 0) { return ret; } + *val = int2_ctrl.int2_drdy; return ret; @@ -1173,6 +1233,8 @@ int32_t lis3dhh_pin_mode_get(const stmdev_ctx_t *ctx, lis3dhh_pp_od_t *val) ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.pp_od) { case LIS3DHH_ALL_PUSH_PULL: @@ -1250,6 +1312,9 @@ int32_t lis3dhh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg4.fifo_en; return ret; @@ -1299,6 +1364,9 @@ int32_t lis3dhh_fifo_block_spi_hs_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg5.fifo_spi_hs_on; return ret; @@ -1342,6 +1410,9 @@ int32_t lis3dhh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl.fth; return ret; @@ -1386,6 +1457,8 @@ int32_t lis3dhh_fifo_mode_get(const stmdev_ctx_t *ctx, lis3dhh_fmode_t *val) ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl.fmode) { case LIS3DHH_BYPASS_MODE: @@ -1448,6 +1521,9 @@ int32_t lis3dhh_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t *)&fifo_src, 1); + + if (ret != 0) { return ret; } + *val = fifo_src.fss; return ret; @@ -1467,6 +1543,9 @@ int32_t lis3dhh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t *)&fifo_src, 1); + + if (ret != 0) { return ret; } + *val = fifo_src.ovrn; return ret; @@ -1486,6 +1565,9 @@ int32_t lis3dhh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t *)&fifo_src, 1); + + if (ret != 0) { return ret; } + *val = fifo_src.fth; return ret; @@ -1544,6 +1626,9 @@ int32_t lis3dhh_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg1.if_add_inc; return ret; @@ -1558,5 +1643,3 @@ int32_t lis3dhh_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h index 3a0dc23..2f93a2a 100644 --- a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h +++ b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -547,5 +549,3 @@ int32_t lis3dhh_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* LIS3DHH_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c index 47af7bf..62d03d9 100644 --- a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c +++ b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -153,6 +152,8 @@ int32_t lis3mdl_data_rate_set(const stmdev_ctx_t *ctx, lis3mdl_om_t val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + /* set mode also for z axis, ctrl_reg4 -> omz */ + ret += lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); if (ret == 0) { @@ -160,12 +161,6 @@ int32_t lis3mdl_data_rate_set(const stmdev_ctx_t *ctx, lis3mdl_om_t val) ret = lis3mdl_write_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); } - if (ret == 0) - { - /* set mode also for z axis, ctrl_reg4 -> omz */ - ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); - } - if (ret == 0) { ctrl_reg4.omz = (uint8_t)(((uint8_t) val >> 4) & 0x03U); @@ -192,6 +187,8 @@ int32_t lis3mdl_data_rate_get(const stmdev_ctx_t *ctx, lis3mdl_om_t *val) /* z axis, ctrl_reg4 -> omz is aligned with x/y axis ctrl_reg1 -> om*/ ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1.om) { case LIS3MDL_LP_Hz625: @@ -372,6 +369,9 @@ int32_t lis3mdl_temperature_meas_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg1.temp_en; return ret; @@ -416,6 +416,8 @@ int32_t lis3mdl_full_scale_get(const stmdev_ctx_t *ctx, lis3mdl_fs_t *val) ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.fs) { case LIS3MDL_4_GAUSS: @@ -483,6 +485,8 @@ int32_t lis3mdl_operating_mode_get(const stmdev_ctx_t *ctx, ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg3.md) { case LIS3MDL_CONTINUOUS_MODE: @@ -543,6 +547,9 @@ int32_t lis3mdl_fast_low_power_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg3.lp; return ret; @@ -586,6 +593,9 @@ int32_t lis3mdl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.bdu; return ret; @@ -631,6 +641,9 @@ int32_t lis3mdl_high_part_cycle_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg5.fast_read; return ret; @@ -651,6 +664,9 @@ int32_t lis3mdl_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3mdl_read_reg(ctx, LIS3MDL_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)status_reg.zyxda; return ret; @@ -671,6 +687,9 @@ int32_t lis3mdl_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lis3mdl_read_reg(ctx, LIS3MDL_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)status_reg.zyxor; return ret; @@ -689,6 +708,9 @@ int32_t lis3mdl_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_OUT_X_L, (uint8_t *) buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -712,6 +734,9 @@ int32_t lis3mdl_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_TEMP_OUT_L, (uint8_t *) buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -784,6 +809,9 @@ int32_t lis3mdl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg1.st; return ret; @@ -827,6 +855,9 @@ int32_t lis3mdl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg2.soft_rst; return ret; @@ -870,6 +901,9 @@ int32_t lis3mdl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg2.reboot; return ret; @@ -914,6 +948,8 @@ int32_t lis3mdl_data_format_get(const stmdev_ctx_t *ctx, lis3mdl_ble_t *val) ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4.ble) { case LIS3MDL_LSB_AT_LOW_ADD: @@ -1022,6 +1058,9 @@ int32_t lis3mdl_int_generation_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int_cfg.ien; return ret; @@ -1070,6 +1109,8 @@ int32_t lis3mdl_int_notification_mode_get(const stmdev_ctx_t *ctx, ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1); + if (ret != 0) { return ret; } + switch (int_cfg.lir) { case LIS3MDL_INT_PULSED: @@ -1128,6 +1169,8 @@ int32_t lis3mdl_int_polarity_get(const stmdev_ctx_t *ctx, ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1); + if (ret != 0) { return ret; } + switch (int_cfg.iea) { case LIS3MDL_ACTIVE_HIGH: @@ -1184,6 +1227,9 @@ int32_t lis3mdl_int_on_z_ax_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int_cfg.zien; return ret; @@ -1227,6 +1273,9 @@ int32_t lis3mdl_int_on_y_ax_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int_cfg.yien; return ret; @@ -1270,6 +1319,9 @@ int32_t lis3mdl_int_on_x_ax_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *)&int_cfg, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int_cfg.xien; return ret; @@ -1304,6 +1356,9 @@ int32_t lis3mdl_interrupt_event_flag_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int_src.int_; return ret; @@ -1324,6 +1379,9 @@ int32_t lis3mdl_int_mag_over_range_flag_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int_src.mroi; return ret; @@ -1343,6 +1401,9 @@ int32_t lis3mdl_int_neg_z_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int_src.nth_z; return ret; @@ -1362,6 +1423,9 @@ int32_t lis3mdl_int_neg_y_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int_src.nth_y; return ret; @@ -1380,6 +1444,9 @@ int32_t lis3mdl_int_neg_x_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int_src.nth_x; return ret; @@ -1398,6 +1465,9 @@ int32_t lis3mdl_int_pos_z_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int_src.pth_z; return ret; @@ -1416,6 +1486,9 @@ int32_t lis3mdl_int_pos_y_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int_src.pth_y; return ret; @@ -1434,6 +1507,9 @@ int32_t lis3mdl_int_pos_x_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *)&int_src, 1); + + if (ret != 0) { return ret; } + *val = (uint8_t)int_src.pth_x; return ret; @@ -1472,6 +1548,9 @@ int32_t lis3mdl_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lis3mdl_read_reg(ctx, LIS3MDL_INT_THS_L, buff, 2); + + if (ret != 0) { return ret; } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -1530,6 +1609,8 @@ int32_t lis3mdl_spi_mode_get(const stmdev_ctx_t *ctx, lis3mdl_sim_t *val) ret = lis3mdl_read_reg(ctx, LIS3MDL_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg3.sim) { case LIS3MDL_SPI_4_WIRE: @@ -1557,5 +1638,3 @@ int32_t lis3mdl_spi_mode_get(const stmdev_ctx_t *ctx, lis3mdl_sim_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h index e444c15..d4ac42d 100644 --- a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h +++ b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -590,5 +592,3 @@ int32_t lis3mdl_spi_mode_get(const stmdev_ctx_t *ctx, lis3mdl_sim_t *val); #endif #endif /* LIS3MDL_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c index 9ff29d0..32d1440 100644 --- a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c +++ b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -160,6 +159,9 @@ int32_t lps22ch_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.reset_az; return ret; @@ -203,6 +205,9 @@ int32_t lps22ch_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.autozero; return ret; @@ -246,6 +251,9 @@ int32_t lps22ch_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.reset_arp; return ret; @@ -289,6 +297,9 @@ int32_t lps22ch_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.autorefp; return ret; @@ -332,6 +343,9 @@ int32_t lps22ch_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.bdu; return ret; @@ -352,11 +366,7 @@ int32_t lps22ch_data_rate_set(const stmdev_ctx_t *ctx, lps22ch_odr_t val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } + ret += lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); if (ret == 0) { @@ -389,16 +399,10 @@ int32_t lps22ch_data_rate_get(const stmdev_ctx_t *ctx, lps22ch_odr_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + ret += lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); if (ret == 0) { - ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - if (ret == 0) - { - ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) + ctrl_reg1.odr)) { @@ -506,6 +510,9 @@ int32_t lps22ch_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_REF_P_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -551,6 +558,9 @@ int32_t lps22ch_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_RPDS_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -621,6 +631,9 @@ int32_t lps22ch_press_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_STATUS, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.p_da; return ret; @@ -641,6 +654,9 @@ int32_t lps22ch_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_STATUS, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.t_da; return ret; @@ -672,6 +688,9 @@ int32_t lps22ch_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) uint8_t reg[3]; ret = lps22ch_read_reg(ctx, LPS22CH_PRESS_OUT_XL, reg, 3); + + if (ret != 0) { return ret; } + *buff = reg[2]; *buff = (*buff * 256) + reg[1]; *buff = (*buff * 256) + reg[0]; @@ -694,6 +713,9 @@ int32_t lps22ch_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) uint8_t reg[2]; ret = lps22ch_read_reg(ctx, LPS22CH_TEMP_OUT_L, reg, 2); + + if (ret != 0) { return ret; } + *buff = reg[1]; *buff = (*buff * 256) + reg[0]; @@ -714,7 +736,10 @@ int32_t lps22ch_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, int32_t ret; uint8_t reg[3]; - ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_DATA_OUT_PRESS_XL, reg, 3); + ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_DATA_OUT_PRESS_XL, reg, 3); + + if (ret != 0) { return ret; } + *buff = reg[2]; *buff = (*buff * 256) + reg[1]; *buff = (*buff * 256) + reg[0]; @@ -737,7 +762,10 @@ int32_t lps22ch_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, int32_t ret; uint8_t reg[2]; - ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_DATA_OUT_TEMP_L, reg, 2); + ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_DATA_OUT_TEMP_L, reg, 2); + + if (ret != 0) { return ret; } + *buff = reg[1]; *buff = (*buff * 256) + reg[0]; @@ -813,6 +841,9 @@ int32_t lps22ch_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.swreset; return ret; @@ -860,6 +891,9 @@ int32_t lps22ch_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.if_add_inc; return ret; @@ -905,6 +939,9 @@ int32_t lps22ch_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.boot; return ret; @@ -964,6 +1001,8 @@ int32_t lps22ch_lp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.lpfp_cfg) { case LPS22CH_LPF_ODR_DIV_2: @@ -1040,6 +1079,8 @@ int32_t lps22ch_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.i2c_disable) { case LPS22CH_I2C_ENABLE: @@ -1100,6 +1141,8 @@ int32_t lps22ch_i3c_interface_get(const stmdev_ctx_t *ctx, ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.i3c_disable) { case LPS22CH_I3C_ENABLE: @@ -1159,6 +1202,8 @@ int32_t lps22ch_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sdo_pu_en) { case LPS22CH_PULL_UP_DISCONNECT: @@ -1216,6 +1261,8 @@ int32_t lps22ch_sda_mode_get(const stmdev_ctx_t *ctx, lps22ch_pu_en_t *val) ret = lps22ch_read_reg(ctx, LPS22CH_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sda_pu_en) { case LPS22CH_PULL_UP_DISCONNECT: @@ -1273,6 +1320,8 @@ int32_t lps22ch_spi_mode_get(const stmdev_ctx_t *ctx, lps22ch_sim_t *val) ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG1, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sim) { case LPS22CH_SPI_4_WIRE: @@ -1345,6 +1394,8 @@ int32_t lps22ch_int_notification_get(const stmdev_ctx_t *ctx, ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.lir) { case LPS22CH_INT_PULSED: @@ -1402,6 +1453,8 @@ int32_t lps22ch_pin_mode_get(const stmdev_ctx_t *ctx, lps22ch_pp_od_t *val) ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.pp_od) { case LPS22CH_PUSH_PULL: @@ -1461,6 +1514,8 @@ int32_t lps22ch_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.int_h_l) { case LPS22CH_ACTIVE_HIGH: @@ -1580,6 +1635,8 @@ int32_t lps22ch_int_on_threshold_get(const stmdev_ctx_t *ctx, ret = lps22ch_read_reg(ctx, LPS22CH_INTERRUPT_CFG, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.pe) { case LPS22CH_NO_THRESHOLD: @@ -1648,13 +1705,13 @@ int32_t lps22ch_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff) lps22ch_ths_p_l_t ths_p_l; lps22ch_ths_p_h_t ths_p_h; - ret = lps22ch_read_reg(ctx, LPS22CH_THS_P_L, + ret = lps22ch_read_reg(ctx, LPS22CH_THS_P_L, (uint8_t *)&ths_p_l, 1); + ret += lps22ch_read_reg(ctx, LPS22CH_THS_P_H, + (uint8_t *)&ths_p_h, 1); if (ret == 0) { - ret = lps22ch_read_reg(ctx, LPS22CH_THS_P_H, - (uint8_t *)&ths_p_h, 1); *buff = (uint16_t)ths_p_h.ths; *buff = (*buff * 256U) + (uint16_t)ths_p_l.ths; } @@ -1714,6 +1771,8 @@ int32_t lps22ch_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.f_mode) { case LPS22CH_BYPASS_MODE: @@ -1792,6 +1851,9 @@ int32_t lps22ch_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_CTRL, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.stop_on_wtm; return ret; @@ -1835,6 +1897,9 @@ int32_t lps22ch_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_WTM, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.wtm; return ret; @@ -1889,6 +1954,9 @@ int32_t lps22ch_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_full_ia; return ret; @@ -1908,6 +1976,9 @@ int32_t lps22ch_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_ovr_ia; return ret; @@ -1927,6 +1998,9 @@ int32_t lps22ch_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_FIFO_STATUS2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_wtm_ia; return ret; @@ -1970,6 +2044,9 @@ int32_t lps22ch_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.int_f_ovr; return ret; @@ -2015,6 +2092,9 @@ int32_t lps22ch_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.int_f_wtm; return ret; @@ -2058,6 +2138,9 @@ int32_t lps22ch_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22ch_read_reg(ctx, LPS22CH_CTRL_REG3, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.int_f_full; return ret; @@ -2072,5 +2155,3 @@ int32_t lps22ch_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h index d28cd4d..7987e09 100644 --- a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h +++ b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -692,5 +694,3 @@ int32_t lps22ch_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /*LPS22CH_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.c b/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.c index 9944082..dc3dfd2 100644 --- a/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.c +++ b/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.c @@ -6,18 +6,18 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ #include "lps22df_reg.h" +#include /** * @defgroup LPS22DF @@ -216,6 +216,10 @@ int32_t lps22df_bus_mode_get(const stmdev_ctx_t *ctx, lps22df_bus_mode_t *val) { ret = lps22df_read_reg(ctx, LPS22DF_I3C_IF_CTRL, (uint8_t *)&i3c_if_ctrl, 1); + if (ret != 0) + { + return ret; + } switch ((if_ctrl.int_en_i3c << 2) | (if_ctrl.i2c_i3c_dis << 1) | if_ctrl.sim) @@ -416,6 +420,10 @@ int32_t lps22df_status_get(const stmdev_ctx_t *ctx, lps22df_stat_t *val) ret = lps22df_read_reg(ctx, LPS22DF_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); } + if (ret != 0) + { + return ret; + } val->sw_reset = ctrl_reg2.swreset; val->boot = int_source.boot_on; val->drdy_pres = status.p_da; @@ -485,6 +493,10 @@ int32_t lps22df_pin_conf_get(const stmdev_ctx_t *ctx, lps22df_pin_conf_t *val) ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); } + if (ret != 0) + { + return ret; + } val->sda_pull_up = if_ctrl.sda_pu_en; val->cs_pull_up = ~if_ctrl.cs_pu_dis; val->int_pull_down = ~if_ctrl.int_pd_dis; @@ -522,6 +534,10 @@ int32_t lps22df_all_sources_get(const stmdev_ctx_t *ctx, (uint8_t *)&fifo_status2, 1); } + if (ret != 0) + { + return ret; + } val->drdy_pres = status.p_da; val->drdy_temp = status.t_da; val->over_pres = int_source.ph; @@ -715,6 +731,10 @@ int32_t lps22df_data_get(const stmdev_ctx_t *ctx, lps22df_data_t *data) int32_t ret; ret = lps22df_read_reg(ctx, LPS22DF_PRESS_OUT_XL, buff, 5); + if (ret != 0) + { + return ret; + } /* pressure conversion */ data->pressure.raw = (int32_t)buff[2]; @@ -747,6 +767,11 @@ int32_t lps22df_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) uint8_t reg[3]; ret = lps22df_read_reg(ctx, LPS22DF_PRESS_OUT_XL, reg, 3); + if (ret != 0) + { + return ret; + } + *buff = reg[2]; *buff = (*buff * 256U) + reg[1]; *buff = (*buff * 256U) + reg[0]; @@ -769,6 +794,11 @@ int32_t lps22df_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) uint8_t reg[2]; ret = lps22df_read_reg(ctx, LPS22DF_TEMP_OUT_L, reg, 2); + if (ret != 0) + { + return ret; + } + *buff = (int16_t)reg[1]; *buff = (*buff * 256) + (int16_t)reg[0]; @@ -792,41 +822,22 @@ int32_t lps22df_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) * @brief FIFO operation mode selection.[set] * * @param ctx communication interface handler.(ptr) - * @param val set the FIFO operation mode.(ptr) + * @param val set the FIFO operation mode. * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_fifo_mode_set(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val) +int32_t lps22df_fifo_mode_set(const stmdev_ctx_t *ctx, lps22df_operation_t val) { lps22df_fifo_ctrl_t fifo_ctrl; - lps22df_fifo_wtm_t fifo_wtm; - uint8_t reg[2]; int32_t ret; - ret = lps22df_read_reg(ctx, LPS22DF_FIFO_CTRL, reg, 2); + ret = lps22df_read_reg(ctx, LPS22DF_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); if (ret == 0) { - bytecpy((uint8_t *)&fifo_ctrl, ®[0]); - bytecpy((uint8_t *)&fifo_wtm, ®[1]); - - fifo_ctrl.f_mode = (uint8_t)val->operation & 0x03U; - fifo_ctrl.trig_modes = ((uint8_t)val->operation & 0x04U) >> 2; - - if (val->watermark != 0x00U) - { - fifo_ctrl.stop_on_wtm = PROPERTY_ENABLE; - } - else - { - fifo_ctrl.stop_on_wtm = PROPERTY_DISABLE; - } - - fifo_wtm.wtm = val->watermark; - - bytecpy(®[0], (uint8_t *)&fifo_ctrl); - bytecpy(®[1], (uint8_t *)&fifo_wtm); + fifo_ctrl.f_mode = (uint8_t)val & 0x03U; + fifo_ctrl.trig_modes = ((uint8_t)val & 0x04U) >> 2; - ret = lps22df_write_reg(ctx, LPS22DF_FIFO_CTRL, reg, 2); + ret = lps22df_write_reg(ctx, LPS22DF_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); } return ret; } @@ -839,48 +850,137 @@ int32_t lps22df_fifo_mode_set(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_fifo_mode_get(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val) +int32_t lps22df_fifo_mode_get(const stmdev_ctx_t *ctx, lps22df_operation_t *val) { lps22df_fifo_ctrl_t fifo_ctrl; - lps22df_fifo_wtm_t fifo_wtm; - uint8_t reg[2]; int32_t ret; - ret = lps22df_read_reg(ctx, LPS22DF_FIFO_CTRL, reg, 2); - - bytecpy((uint8_t *)&fifo_ctrl, ®[0]); - bytecpy((uint8_t *)&fifo_wtm, ®[1]); + ret = lps22df_read_reg(ctx, LPS22DF_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret != 0) + { + return ret; + } switch ((fifo_ctrl.trig_modes << 2) | fifo_ctrl.f_mode) { case LPS22DF_BYPASS: - val->operation = LPS22DF_BYPASS; + *val = LPS22DF_BYPASS; break; case LPS22DF_FIFO: - val->operation = LPS22DF_FIFO; + *val = LPS22DF_FIFO; break; case LPS22DF_STREAM: - val->operation = LPS22DF_STREAM; + *val = LPS22DF_STREAM; break; case LPS22DF_STREAM_TO_FIFO: - val->operation = LPS22DF_STREAM_TO_FIFO; + *val = LPS22DF_STREAM_TO_FIFO; break; case LPS22DF_BYPASS_TO_STREAM: - val->operation = LPS22DF_BYPASS_TO_STREAM; + *val = LPS22DF_BYPASS_TO_STREAM; break; case LPS22DF_BYPASS_TO_FIFO: - val->operation = LPS22DF_BYPASS_TO_FIFO; + *val = LPS22DF_BYPASS_TO_FIFO; break; default: - val->operation = LPS22DF_BYPASS; + *val = LPS22DF_BYPASS; break; } - val->watermark = fifo_wtm.wtm; return ret; } +/** + * @brief FIFO watermark selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val watermark value (0 disable; max 128) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lps22df_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lps22df_fifo_wtm_t fifo_wtm; + int32_t ret; + + assert(val < 128); + + ret = lps22df_read_reg(ctx, LPS22DF_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + if (ret == 0) + { + fifo_wtm.wtm = val & 0x7F; + + ret = lps22df_write_reg(ctx, LPS22DF_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + } + return ret; +} + +/** + * @brief FIFO watermark selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val watermark value (0 disable; max 128) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lps22df_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lps22df_fifo_wtm_t fifo_wtm; + int32_t ret; + + ret = lps22df_read_reg(ctx, LPS22DF_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + if (ret == 0) + { + *val = fifo_wtm.wtm; + } + return ret; +} + +/** + * @brief FIFO stop_on_wtm selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val set the stop_on_wtm mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lps22df_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lps22df_fifo_event_t *val) +{ + lps22df_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = lps22df_read_reg(ctx, LPS22DF_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret == 0) + { + fifo_ctrl.stop_on_wtm = (val == LPS22DF_FIFO_EV_WTM) ? 1 : 0; + + ret = lps22df_write_reg(ctx, LPS22DF_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + } + return ret; +} + +/** + * @brief FIFO stop_on_wtm selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val get the stop_on_wtm mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lps22df_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lps22df_fifo_event_t *val) +{ + lps22df_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = lps22df_read_reg(ctx, LPS22DF_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret == 0) + { + *val = (fifo_ctrl.stop_on_wtm == 1) ? LPS22DF_FIFO_EV_WTM : LPS22DF_FIFO_EV_FULL; + } + return ret; +} + + /** * @brief Get the number of samples stored in FIFO.[get] * @@ -896,6 +996,10 @@ int32_t lps22df_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22df_read_reg(ctx, LPS22DF_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + if (ret != 0) + { + return ret; + } *val = fifo_status1.fss; @@ -919,7 +1023,11 @@ int32_t lps22df_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, lps22df_fif for (i = 0U; i < samp; i++) { - ret = lps22df_read_reg(ctx, LPS22DF_FIFO_DATA_OUT_PRESS_XL, fifo_data, 3); + ret += lps22df_read_reg(ctx, LPS22DF_FIFO_DATA_OUT_PRESS_XL, fifo_data, 3); + if (ret != 0) + { + return ret; + } data[i].raw = (int32_t)fifo_data[2]; data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[1]; data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[0]; @@ -1005,6 +1113,10 @@ int32_t lps22df_interrupt_mode_get(const stmdev_ctx_t *ctx, ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG3, reg, 2); ret += lps22df_read_reg(ctx, LPS22DF_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&ctrl_reg3, ®[0]); bytecpy((uint8_t *)&ctrl_reg4, ®[1]); @@ -1058,6 +1170,10 @@ int32_t lps22df_pin_int_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) + { + return ret; + } val->drdy_pres = ctrl_reg4.drdy; val->fifo_th = ctrl_reg4.int_f_wtm; @@ -1149,6 +1265,10 @@ int32_t lps22df_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps22df_read_reg(ctx, LPS22DF_INTERRUPT_CFG, reg, 3); + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&interrupt_cfg, ®[0]); bytecpy((uint8_t *)&ths_p_l, ®[1]); @@ -1220,6 +1340,10 @@ int32_t lps22df_reference_mode_get(const stmdev_ctx_t *ctx, lps22df_ref_md_t *va ret = lps22df_read_reg(ctx, LPS22DF_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + if (ret != 0) + { + return ret; + } switch ((interrupt_cfg.reset_az << 1) | interrupt_cfg.autorefp) @@ -1275,6 +1399,10 @@ int32_t lps22df_opc_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps22df_read_reg(ctx, LPS22DF_RPDS_L, reg, 2); + if (ret != 0) + { + return ret; + } *val = (int16_t)reg[1]; *val = *val * 256 + (int16_t)reg[0]; @@ -1292,4 +1420,3 @@ int32_t lps22df_opc_get(const stmdev_ctx_t *ctx, int16_t *val) * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.h b/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.h index 61cd266..f3a9d28 100644 --- a/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.h +++ b/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -664,13 +666,21 @@ typedef enum LPS22DF_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ } lps22df_operation_t; -typedef struct + +int32_t lps22df_fifo_mode_set(const stmdev_ctx_t *ctx, lps22df_operation_t val); +int32_t lps22df_fifo_mode_get(const stmdev_ctx_t *ctx, lps22df_operation_t *val); + +int32_t lps22df_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22df_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { - lps22df_operation_t operation; - uint8_t watermark : 7; /* (0 disable) max 128.*/ -} lps22df_fifo_md_t; -int32_t lps22df_fifo_mode_set(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val); -int32_t lps22df_fifo_mode_get(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val); + LPS22DF_FIFO_EV_WTM = 0x0, + LPS22DF_FIFO_EV_FULL = 0x1, +} lps22df_fifo_event_t; + +int32_t lps22df_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lps22df_fifo_event_t *val); +int32_t lps22df_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lps22df_fifo_event_t *val); int32_t lps22df_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val); @@ -744,4 +754,3 @@ int32_t lps22df_opc_get(const stmdev_ctx_t *ctx, int16_t *val); #endif /* LPS22DF_REGS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c index 1761e13..2c6fb3b 100644 --- a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c +++ b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -184,6 +183,9 @@ int32_t lps22hb_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + + if (ret != 0) { return ret; } + *val = interrupt_cfg.reset_az; return ret; @@ -230,6 +232,9 @@ int32_t lps22hb_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + + if (ret != 0) { return ret; } + *val = interrupt_cfg.autozero; return ret; @@ -276,6 +281,9 @@ int32_t lps22hb_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + + if (ret != 0) { return ret; } + *val = interrupt_cfg.reset_arp; return ret; @@ -322,6 +330,9 @@ int32_t lps22hb_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + + if (ret != 0) { return ret; } + *val = interrupt_cfg.autorifp; return ret; @@ -365,6 +376,9 @@ int32_t lps22hb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg1.bdu; return ret; @@ -411,6 +425,8 @@ int32_t lps22hb_low_pass_filter_mode_get(const stmdev_ctx_t *ctx, ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1.lpfp) { case LPS22HB_LPF_ODR_DIV_2: @@ -472,6 +488,8 @@ int32_t lps22hb_data_rate_get(const stmdev_ctx_t *ctx, lps22hb_odr_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1.odr) { case LPS22HB_POWER_DOWN: @@ -544,6 +562,9 @@ int32_t lps22hb_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg2.one_shot; return ret; @@ -589,6 +610,9 @@ int32_t lps22hb_pressure_ref_get(const stmdev_ctx_t *ctx, int32_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_REF_P_XL, buff, 3); + + if (ret != 0) { return ret; } + *val = (int32_t)buff[2]; *val = (*val * 256) + (int32_t)buff[1]; *val = (*val * 256) + (int32_t)buff[0]; @@ -632,6 +656,9 @@ int32_t lps22hb_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_RPDS_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -652,6 +679,9 @@ int32_t lps22hb_press_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.p_da; return ret; @@ -671,6 +701,9 @@ int32_t lps22hb_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.t_da; return ret; @@ -691,6 +724,9 @@ int32_t lps22hb_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *press_val, uint int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *press_val = status.p_da; *temp_val = status.t_da; @@ -711,6 +747,9 @@ int32_t lps22hb_press_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.p_or; return ret; @@ -730,6 +769,9 @@ int32_t lps22hb_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.t_or; return ret; @@ -749,6 +791,9 @@ int32_t lps22hb_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_PRESS_OUT_XL, reg, 3); + + if (ret != 0) { return ret; } + *buff = reg[2]; *buff = (*buff * 256) + reg[1]; *buff = (*buff * 256) + reg[0]; @@ -771,6 +816,9 @@ int32_t lps22hb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_TEMP_OUT_L, (uint8_t *) reg, 2); + + if (ret != 0) { return ret; } + *buff = reg[1]; *buff = (*buff * 256) + reg[0]; @@ -910,6 +958,9 @@ int32_t lps22hb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg2.swreset; return ret; @@ -953,6 +1004,9 @@ int32_t lps22hb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg2.boot; return ret; @@ -996,6 +1050,9 @@ int32_t lps22hb_low_power_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_RES_CONF, (uint8_t *)&res_conf, 1); + + if (ret != 0) { return ret; } + *val = res_conf.lc_en; return ret; @@ -1016,6 +1073,9 @@ int32_t lps22hb_boot_status_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE, (uint8_t *)&int_source, 1); + + if (ret != 0) { return ret; } + *val = int_source.boot_status; return ret; @@ -1095,6 +1155,8 @@ int32_t lps22hb_sign_of_int_threshold_get(const stmdev_ctx_t *ctx, ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + if (ret != 0) { return ret; } + switch (interrupt_cfg.pe) { case LPS22HB_NO_THRESHOLD: @@ -1167,6 +1229,8 @@ int32_t lps22hb_int_notification_mode_get(const stmdev_ctx_t *ctx, ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + if (ret != 0) { return ret; } + switch (interrupt_cfg.lir) { case LPS22HB_INT_PULSED: @@ -1226,6 +1290,9 @@ int32_t lps22hb_int_generation_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + + if (ret != 0) { return ret; } + *val = interrupt_cfg.diff_en; return ret; @@ -1265,6 +1332,9 @@ int32_t lps22hb_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_THS_P_L, (uint8_t *) buff, 2); + + if (ret != 0) { return ret; } + *val = buff[1]; *val = (*val * 256) + buff[0]; @@ -1312,6 +1382,8 @@ int32_t lps22hb_int_pin_mode_get(const stmdev_ctx_t *ctx, ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg3.int_s) { case LPS22HB_DRDY_OR_FIFO_FLAGS: @@ -1376,6 +1448,9 @@ int32_t lps22hb_drdy_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg3.drdy; return ret; @@ -1419,6 +1494,9 @@ int32_t lps22hb_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg3.f_ovr; return ret; @@ -1464,6 +1542,9 @@ int32_t lps22hb_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg3.f_fth; return ret; @@ -1507,6 +1588,9 @@ int32_t lps22hb_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg3.f_fss5; return ret; @@ -1551,6 +1635,8 @@ int32_t lps22hb_pin_mode_get(const stmdev_ctx_t *ctx, lps22hb_pp_od_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg3.pp_od) { case LPS22HB_PUSH_PULL: @@ -1610,6 +1696,8 @@ int32_t lps22hb_int_polarity_get(const stmdev_ctx_t *ctx, ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg3.int_h_l) { case LPS22HB_ACTIVE_HIGH: @@ -1661,6 +1749,9 @@ int32_t lps22hb_int_on_press_high_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE, (uint8_t *)&int_source, 1); + + if (ret != 0) { return ret; } + *val = int_source.ph; return ret; @@ -1681,6 +1772,9 @@ int32_t lps22hb_int_on_press_low_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE, (uint8_t *)&int_source, 1); + + if (ret != 0) { return ret; } + *val = int_source.pl; return ret; @@ -1701,6 +1795,9 @@ int32_t lps22hb_interrupt_event_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_INT_SOURCE, (uint8_t *)&int_source, 1); + + if (ret != 0) { return ret; } + *val = int_source.ia; return ret; @@ -1759,6 +1856,9 @@ int32_t lps22hb_stop_on_fifo_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg2.stop_on_fth; return ret; @@ -1802,6 +1902,9 @@ int32_t lps22hb_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg2.fifo_en; return ret; @@ -1845,6 +1948,9 @@ int32_t lps22hb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl.wtm; return ret; @@ -1890,6 +1996,8 @@ int32_t lps22hb_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl.f_mode) { case LPS22HB_BYPASS_MODE: @@ -1943,6 +2051,9 @@ int32_t lps22hb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_STATUS, (uint8_t *)&fifo_status, 1); + + if (ret != 0) { return ret; } + *val = fifo_status.fss; return ret; @@ -1963,6 +2074,9 @@ int32_t lps22hb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_STATUS, (uint8_t *)&fifo_status, 1); + + if (ret != 0) { return ret; } + *val = fifo_status.ovr; return ret; @@ -1983,6 +2097,9 @@ int32_t lps22hb_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_FIFO_STATUS, (uint8_t *)&fifo_status, 1); + + if (ret != 0) { return ret; } + *val = fifo_status.fth_fifo; return ret; @@ -2040,6 +2157,8 @@ int32_t lps22hb_spi_mode_get(const stmdev_ctx_t *ctx, lps22hb_sim_t *val) ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1.sim) { case LPS22HB_SPI_4_WIRE: @@ -2099,6 +2218,8 @@ int32_t lps22hb_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2.i2c_dis) { case LPS22HB_I2C_ENABLE: @@ -2157,6 +2278,9 @@ int32_t lps22hb_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hb_read_reg(ctx, LPS22HB_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg2.if_add_inc; return ret; @@ -2171,5 +2295,3 @@ int32_t lps22hb_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h index afecd8b..fa3be35 100644 --- a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h +++ b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct _stmdev_ctx_t stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -670,5 +672,3 @@ int32_t lps22hb_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* LPS22HB_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c index 9c85120..7d934e3 100644 --- a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c +++ b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -160,6 +159,9 @@ int32_t lps22hh_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.reset_az; return ret; @@ -203,6 +205,9 @@ int32_t lps22hh_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.autozero; return ret; @@ -246,6 +251,9 @@ int32_t lps22hh_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.reset_arp; return ret; @@ -289,6 +297,9 @@ int32_t lps22hh_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.autorefp; return ret; @@ -332,6 +343,9 @@ int32_t lps22hh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.bdu; return ret; @@ -352,11 +366,7 @@ int32_t lps22hh_data_rate_set(const stmdev_ctx_t *ctx, lps22hh_odr_t val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } + ret += lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); if (ret == 0) { @@ -389,16 +399,10 @@ int32_t lps22hh_data_rate_get(const stmdev_ctx_t *ctx, lps22hh_odr_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + ret += lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); if (ret == 0) { - ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - if (ret == 0) - { - ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) + ctrl_reg1.odr)) { @@ -506,6 +510,9 @@ int32_t lps22hh_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_REF_P_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -551,6 +558,9 @@ int32_t lps22hh_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_RPDS_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -569,14 +579,16 @@ int32_t lps22hh_all_sources_get(const stmdev_ctx_t *ctx, lps22hh_all_sources_t *val) { int32_t ret; + uint8_t buff[2]; - ret = lps22hh_read_reg(ctx, LPS22HH_INT_SOURCE, - (uint8_t *) & (val->int_source), 1); + ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS1, (uint8_t *) &buff, 2); - if (ret == 0) + if (ret == 0) { - ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, - (uint8_t *) & (val->fifo_status2), 1); + *((uint8_t *)&val->fifo_status2) = buff[1]; + + ret = lps22hh_read_reg(ctx, LPS22HH_INT_SOURCE, + (uint8_t *) & (val->int_source), 1); } if (ret == 0) @@ -621,6 +633,9 @@ int32_t lps22hh_press_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.p_da; return ret; @@ -641,6 +656,9 @@ int32_t lps22hh_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.t_da; return ret; @@ -672,6 +690,9 @@ int32_t lps22hh_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) uint8_t reg[3]; ret = lps22hh_read_reg(ctx, LPS22HH_PRESS_OUT_XL, reg, 3); + + if (ret != 0) { return ret; } + *buff = reg[2]; *buff = (*buff * 256U) + reg[1]; *buff = (*buff * 256U) + reg[0]; @@ -694,6 +715,9 @@ int32_t lps22hh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) uint8_t reg[2]; ret = lps22hh_read_reg(ctx, LPS22HH_TEMP_OUT_L, reg, 2); + + if (ret != 0) { return ret; } + *buff = (int16_t)reg[1]; *buff = (*buff * 256) + (int16_t)reg[0]; @@ -715,6 +739,9 @@ int32_t lps22hh_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, uint8_t reg[3]; ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_DATA_OUT_PRESS_XL, reg, 3); + + if (ret != 0) { return ret; } + *buff = reg[2]; *buff = (*buff * 256U) + reg[1]; *buff = (*buff * 256U) + reg[0]; @@ -738,6 +765,9 @@ int32_t lps22hh_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t reg[2]; ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_DATA_OUT_TEMP_L, reg, 2); + + if (ret != 0) { return ret; } + *buff = (int16_t)reg[1]; *buff = (*buff * 256) + (int16_t)reg[0]; @@ -813,6 +843,9 @@ int32_t lps22hh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.swreset; return ret; @@ -860,6 +893,9 @@ int32_t lps22hh_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.if_add_inc; return ret; @@ -905,6 +941,9 @@ int32_t lps22hh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.boot; return ret; @@ -964,6 +1003,8 @@ int32_t lps22hh_lp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.lpfp_cfg) { case LPS22HH_LPF_ODR_DIV_2: @@ -1040,6 +1081,8 @@ int32_t lps22hh_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.i2c_disable) { case LPS22HH_I2C_ENABLE: @@ -1100,6 +1143,8 @@ int32_t lps22hh_i3c_interface_get(const stmdev_ctx_t *ctx, ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch ((reg.int_en_i3c << 4) + reg.int_en_i3c) { case LPS22HH_I3C_ENABLE: @@ -1163,6 +1208,8 @@ int32_t lps22hh_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sdo_pu_en) { case LPS22HH_PULL_UP_DISCONNECT: @@ -1220,6 +1267,8 @@ int32_t lps22hh_sda_mode_get(const stmdev_ctx_t *ctx, lps22hh_pu_en_t *val) ret = lps22hh_read_reg(ctx, LPS22HH_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sda_pu_en) { case LPS22HH_PULL_UP_DISCONNECT: @@ -1277,6 +1326,8 @@ int32_t lps22hh_spi_mode_get(const stmdev_ctx_t *ctx, lps22hh_sim_t *val) ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sim) { case LPS22HH_SPI_4_WIRE: @@ -1349,6 +1400,8 @@ int32_t lps22hh_int_notification_get(const stmdev_ctx_t *ctx, ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.lir) { case LPS22HH_INT_PULSED: @@ -1406,6 +1459,8 @@ int32_t lps22hh_pin_mode_get(const stmdev_ctx_t *ctx, lps22hh_pp_od_t *val) ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.pp_od) { case LPS22HH_PUSH_PULL: @@ -1465,6 +1520,8 @@ int32_t lps22hh_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.int_h_l) { case LPS22HH_ACTIVE_HIGH: @@ -1526,6 +1583,8 @@ int32_t lps22hh_pin_int_route_get(const stmdev_ctx_t *ctx, ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) { return ret; } + val->drdy_pres = ctrl_reg3.drdy; val->fifo_th = ctrl_reg3.int_f_wtm; val->fifo_ovr = ctrl_reg3.int_f_ovr; @@ -1599,6 +1658,8 @@ int32_t lps22hh_int_on_threshold_get(const stmdev_ctx_t *ctx, ret = lps22hh_read_reg(ctx, LPS22HH_INTERRUPT_CFG, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.pe) { case LPS22HH_NO_THRESHOLD: @@ -1667,13 +1728,13 @@ int32_t lps22hh_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff) lps22hh_ths_p_l_t ths_p_l; lps22hh_ths_p_h_t ths_p_h; - ret = lps22hh_read_reg(ctx, LPS22HH_THS_P_L, + ret = lps22hh_read_reg(ctx, LPS22HH_THS_P_L, (uint8_t *)&ths_p_l, 1); + ret += lps22hh_read_reg(ctx, LPS22HH_THS_P_H, + (uint8_t *)&ths_p_h, 1); if (ret == 0) { - ret = lps22hh_read_reg(ctx, LPS22HH_THS_P_H, - (uint8_t *)&ths_p_h, 1); *buff = (uint16_t)ths_p_h.ths; *buff = (*buff * 256U) + (uint16_t)ths_p_l.ths; } @@ -1733,6 +1794,8 @@ int32_t lps22hh_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.f_mode) { case LPS22HH_BYPASS_MODE: @@ -1811,6 +1874,9 @@ int32_t lps22hh_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.stop_on_wtm; return ret; @@ -1854,6 +1920,9 @@ int32_t lps22hh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.wtm; return ret; @@ -1870,8 +1939,12 @@ int32_t lps22hh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t lps22hh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *num) { int32_t ret; + uint8_t buff[2]; + ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS1, (uint8_t *) &buff, 2); - ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS1, num, 1); + if (ret != 0) { return ret; } + + *num = buff[0]; return ret; } @@ -1889,7 +1962,12 @@ int32_t lps22hh_fifo_src_get(const stmdev_ctx_t *ctx, { int32_t ret; - ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) val, 1); + uint8_t buff[2]; + ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS1, (uint8_t *) &buff, 2); + + if (ret != 0) { return ret; } + + *((uint8_t *)&val) = buff[1]; return ret; } @@ -1908,6 +1986,9 @@ int32_t lps22hh_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_full_ia; return ret; @@ -1927,6 +2008,9 @@ int32_t lps22hh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_ovr_ia; return ret; @@ -1946,6 +2030,9 @@ int32_t lps22hh_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_wtm_ia; return ret; @@ -1960,5 +2047,3 @@ int32_t lps22hh_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h index 1bc1b2a..ad431dc 100644 --- a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h +++ b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -628,5 +630,3 @@ int32_t lps22hh_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /*LPS22HH_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c index 1f8b041..c76a60b 100644 --- a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c +++ b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -161,6 +160,9 @@ int32_t lps25hb_pressure_ref_get(const stmdev_ctx_t *ctx, int32_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_REF_P_XL, buff, 3); + + if (ret != 0) { return ret; } + *val = (int32_t)buff[2]; *val = (*val * 256) + (int32_t)buff[1]; *val = (*val * 256) + (int32_t)buff[0]; @@ -209,6 +211,8 @@ int32_t lps25hb_pressure_avg_get(const stmdev_ctx_t *ctx, ret = lps25hb_read_reg(ctx, LPS25HB_RES_CONF, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.avgp) { case LPS25HB_P_AVG_8: @@ -276,6 +280,8 @@ int32_t lps25hb_temperature_avg_get(const stmdev_ctx_t *ctx, ret = lps25hb_read_reg(ctx, LPS25HB_RES_CONF, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.avgt) { case LPS25HB_T_AVG_8: @@ -340,6 +346,9 @@ int32_t lps25hb_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.reset_az; return ret; @@ -383,6 +392,9 @@ int32_t lps25hb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.bdu; return ret; @@ -427,6 +439,8 @@ int32_t lps25hb_data_rate_get(const stmdev_ctx_t *ctx, lps25hb_odr_t *val) ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.odr) { case LPS25HB_POWER_DOWN: @@ -499,6 +513,9 @@ int32_t lps25hb_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.one_shot; return ret; @@ -542,6 +559,9 @@ int32_t lps25hb_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.autozero; return ret; @@ -589,6 +609,9 @@ int32_t lps25hb_fifo_mean_decimator_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_mean_dec; return ret; @@ -608,6 +631,9 @@ int32_t lps25hb_press_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.p_da; return ret; @@ -627,6 +653,9 @@ int32_t lps25hb_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.t_da; return ret; @@ -646,6 +675,9 @@ int32_t lps25hb_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.t_or; return ret; @@ -665,6 +697,9 @@ int32_t lps25hb_press_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_STATUS_REG, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.p_or; return ret; @@ -684,6 +719,9 @@ int32_t lps25hb_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_PRESS_OUT_XL, reg, 3); + + if (ret != 0) { return ret; } + *buff = reg[2]; *buff = (*buff * 256) + reg[1]; *buff = (*buff * 256) + reg[0]; @@ -706,6 +744,9 @@ int32_t lps25hb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_TEMP_OUT_L, reg, 2); + + if (ret != 0) { return ret; } + *buff = reg[1]; *buff = (*buff * 256) + reg[0]; @@ -728,7 +769,7 @@ int32_t lps25hb_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val) buff[1] = (uint8_t)((uint16_t)val / 256U); buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U)); - ret = lps25hb_read_reg(ctx, LPS25HB_RPDS_L, buff, 2); + ret = lps25hb_write_reg(ctx, LPS25HB_RPDS_L, buff, 2); return ret; } @@ -748,6 +789,9 @@ int32_t lps25hb_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_RPDS_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -821,6 +865,9 @@ int32_t lps25hb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.swreset; return ret; @@ -864,6 +911,9 @@ int32_t lps25hb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.boot; return ret; @@ -937,6 +987,9 @@ int32_t lps25hb_int_generation_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.diff_en; return ret; @@ -983,6 +1036,8 @@ int32_t lps25hb_int_pin_mode_get(const stmdev_ctx_t *ctx, ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.int_s) { case LPS25HB_DRDY_OR_FIFO_FLAGS: @@ -1048,6 +1103,8 @@ int32_t lps25hb_pin_mode_get(const stmdev_ctx_t *ctx, lps25hb_pp_od_t *val) ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.pp_od) { case LPS25HB_PUSH_PULL: @@ -1107,6 +1164,8 @@ int32_t lps25hb_int_polarity_get(const stmdev_ctx_t *ctx, ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG3, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.int_h_l) { case LPS25HB_ACTIVE_HIGH: @@ -1163,6 +1222,9 @@ int32_t lps25hb_drdy_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.drdy; return ret; @@ -1206,6 +1268,9 @@ int32_t lps25hb_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.f_ovr; return ret; @@ -1251,6 +1316,9 @@ int32_t lps25hb_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.f_fth; return ret; @@ -1294,6 +1362,9 @@ int32_t lps25hb_fifo_empty_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG4, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.f_empty; return ret; @@ -1340,6 +1411,8 @@ int32_t lps25hb_sign_of_int_threshold_get(const stmdev_ctx_t *ctx, ret = lps25hb_read_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.pe) { case LPS25HB_NO_THRESHOLD: @@ -1407,6 +1480,8 @@ int32_t lps25hb_int_notification_mode_get(const stmdev_ctx_t *ctx, ret = lps25hb_read_reg(ctx, LPS25HB_INTERRUPT_CFG, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.lir) { case LPS25HB_INT_PULSED: @@ -1457,6 +1532,9 @@ int32_t lps25hb_int_on_press_high_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_INT_SOURCE, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.ph; return ret; @@ -1476,6 +1554,9 @@ int32_t lps25hb_int_on_press_low_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_INT_SOURCE, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.pl; return ret; @@ -1495,6 +1576,9 @@ int32_t lps25hb_interrupt_event_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_INT_SOURCE, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.ia; return ret; @@ -1534,6 +1618,9 @@ int32_t lps25hb_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_THS_P_L, buff, 2); + + if (ret != 0) { return ret; } + *val = buff[1]; *val = (*val * 256) + buff[0]; @@ -1592,6 +1679,9 @@ int32_t lps25hb_stop_on_fifo_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.stop_on_fth; return ret; @@ -1635,6 +1725,9 @@ int32_t lps25hb_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_en; return ret; @@ -1678,6 +1771,9 @@ int32_t lps25hb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.wtm_point; return ret; @@ -1723,6 +1819,8 @@ int32_t lps25hb_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_CTRL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.f_mode) { case LPS25HB_BYPASS_MODE: @@ -1793,6 +1891,9 @@ int32_t lps25hb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.fss; return ret; @@ -1812,6 +1913,9 @@ int32_t lps25hb_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.empty_fifo; return ret; @@ -1831,6 +1935,9 @@ int32_t lps25hb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.ovr; return ret; @@ -1850,6 +1957,9 @@ int32_t lps25hb_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps25hb_read_reg(ctx, LPS25HB_FIFO_STATUS, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.fth_fifo; return ret; @@ -1907,6 +2017,8 @@ int32_t lps25hb_spi_mode_get(const stmdev_ctx_t *ctx, lps25hb_sim_t *val) ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.sim) { case LPS25HB_SPI_4_WIRE: @@ -1966,6 +2078,8 @@ int32_t lps25hb_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lps25hb_read_reg(ctx, LPS25HB_CTRL_REG2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.i2c_dis) { case LPS25HB_I2C_ENABLE: @@ -1993,5 +2107,3 @@ int32_t lps25hb_i2c_interface_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h index 8b78f80..64543f1 100644 --- a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h +++ b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -123,6 +122,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -652,5 +654,3 @@ int32_t lps25hb_i2c_interface_get(const stmdev_ctx_t *ctx, #endif #endif /* LPS25HB_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c index ebd20c3..3e74bb1 100644 --- a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c +++ b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -163,6 +162,9 @@ int32_t lps27hhtw_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.reset_az; return ret; @@ -209,6 +211,9 @@ int32_t lps27hhtw_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.autozero; return ret; @@ -257,6 +262,9 @@ int32_t lps27hhtw_pressure_snap_rst_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.reset_arp; return ret; @@ -303,6 +311,9 @@ int32_t lps27hhtw_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.autorefp; return ret; @@ -348,6 +359,9 @@ int32_t lps27hhtw_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.bdu; return ret; @@ -370,12 +384,8 @@ int32_t lps27hhtw_data_rate_set(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - } + ret += lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, + (uint8_t *)&ctrl_reg2, 1); if (ret == 0) { @@ -412,18 +422,11 @@ int32_t lps27hhtw_data_rate_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + ret += lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, + (uint8_t *)&ctrl_reg2, 1); if (ret == 0) { - ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - } - - if (ret == 0) - { - ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) + ctrl_reg1.odr)) { @@ -531,6 +534,9 @@ int32_t lps27hhtw_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_REF_P_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -576,6 +582,9 @@ int32_t lps27hhtw_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_RPDS_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -646,6 +655,9 @@ int32_t lps27hhtw_press_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_STATUS, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.p_da; return ret; @@ -666,6 +678,9 @@ int32_t lps27hhtw_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_STATUS, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.t_da; return ret; @@ -697,6 +712,9 @@ int32_t lps27hhtw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_PRESS_OUT_XL, reg, 3); + + if (ret != 0) { return ret; } + *buff = reg[2]; *buff = (*buff * 256) + reg[1]; *buff = (*buff * 256) + reg[0]; @@ -720,6 +738,9 @@ int32_t lps27hhtw_temperature_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_TEMP_OUT_L, reg, 2); + + if (ret != 0) { return ret; } + *buff = reg[1]; *buff = (*buff * 256) + reg[0]; @@ -742,6 +763,9 @@ int32_t lps27hhtw_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_DATA_OUT_PRESS_XL, reg, 3); + + if (ret != 0) { return ret; } + *buff = reg[2]; *buff = (*buff * 256) + reg[1]; *buff = (*buff * 256) + reg[0]; @@ -766,6 +790,9 @@ int32_t lps27hhtw_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_DATA_OUT_TEMP_L, reg, 2); + + if (ret != 0) { return ret; } + *buff = reg[1]; *buff = (*buff * 256) + reg[0]; @@ -841,6 +868,9 @@ int32_t lps27hhtw_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.swreset; return ret; @@ -888,6 +918,9 @@ int32_t lps27hhtw_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.if_add_inc; return ret; @@ -933,6 +966,9 @@ int32_t lps27hhtw_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.boot; return ret; @@ -992,6 +1028,8 @@ int32_t lps27hhtw_lp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.lpfp_cfg) { case LPS27HHTW_LPF_ODR_DIV_2: @@ -1068,6 +1106,8 @@ int32_t lps27hhtw_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.i2c_disable) { case LPS27HHTW_I2C_ENABLE: @@ -1128,6 +1168,8 @@ int32_t lps27hhtw_i3c_interface_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch ((reg.int_en_i3c << 4) + reg.int_en_i3c) { case LPS27HHTW_I3C_ENABLE: @@ -1191,6 +1233,8 @@ int32_t lps27hhtw_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sdo_pu_en) { case LPS27HHTW_PULL_UP_DISCONNECT: @@ -1250,6 +1294,8 @@ int32_t lps27hhtw_sda_mode_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sda_pu_en) { case LPS27HHTW_PULL_UP_DISCONNECT: @@ -1308,6 +1354,8 @@ int32_t lps27hhtw_spi_mode_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG1, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sim) { case LPS27HHTW_SPI_4_WIRE: @@ -1383,6 +1431,8 @@ int32_t lps27hhtw_int_notification_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.lir) { case LPS27HHTW_INT_PULSED: @@ -1442,6 +1492,8 @@ int32_t lps27hhtw_pin_mode_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.pp_od) { case LPS27HHTW_PUSH_PULL: @@ -1501,6 +1553,8 @@ int32_t lps27hhtw_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.int_h_l) { case LPS27HHTW_ACTIVE_HIGH: @@ -1623,6 +1677,8 @@ int32_t lps27hhtw_int_on_threshold_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_INTERRUPT_CFG, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.pe) { case LPS27HHTW_NO_THRESHOLD: @@ -1691,13 +1747,13 @@ int32_t lps27hhtw_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff) lps27hhtw_ths_p_l_t ths_p_l; lps27hhtw_ths_p_h_t ths_p_h; - ret = lps27hhtw_read_reg(ctx, LPS27HHTW_THS_P_L, + ret = lps27hhtw_read_reg(ctx, LPS27HHTW_THS_P_L, (uint8_t *)&ths_p_l, 1); + ret += lps27hhtw_read_reg(ctx, LPS27HHTW_THS_P_H, + (uint8_t *)&ths_p_h, 1); if (ret == 0) { - ret = lps27hhtw_read_reg(ctx, LPS27HHTW_THS_P_H, - (uint8_t *)&ths_p_h, 1); *buff = (uint16_t)ths_p_h.ths << 8; *buff |= (uint16_t)ths_p_l.ths; } @@ -1758,6 +1814,8 @@ int32_t lps27hhtw_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.f_mode) { case LPS27HHTW_BYPASS_MODE: @@ -1837,6 +1895,9 @@ int32_t lps27hhtw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_CTRL, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.stop_on_wtm; return ret; @@ -1880,6 +1941,9 @@ int32_t lps27hhtw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_WTM, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.wtm; return ret; @@ -1937,6 +2001,9 @@ int32_t lps27hhtw_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_full_ia; return ret; @@ -1957,6 +2024,9 @@ int32_t lps27hhtw_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_ovr_ia; return ret; @@ -1976,6 +2046,9 @@ int32_t lps27hhtw_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_FIFO_STATUS2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_wtm_ia; return ret; @@ -2019,6 +2092,9 @@ int32_t lps27hhtw_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.int_f_ovr; return ret; @@ -2064,6 +2140,9 @@ int32_t lps27hhtw_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.int_f_wtm; return ret; @@ -2108,6 +2187,9 @@ int32_t lps27hhtw_fifo_full_on_int_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhtw_read_reg(ctx, LPS27HHTW_CTRL_REG3, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.int_f_full; return ret; @@ -2122,5 +2204,3 @@ int32_t lps27hhtw_fifo_full_on_int_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h index 0b2f2b0..4af0277 100644 --- a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h +++ b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -713,5 +715,3 @@ int32_t lps27hhtw_fifo_full_on_int_get(const stmdev_ctx_t *ctx, #endif #endif /*LPS27HHTW_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c index 24650a2..473041f 100644 --- a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c +++ b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -161,6 +160,9 @@ int32_t lps27hhw_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.reset_az; return ret; @@ -205,6 +207,9 @@ int32_t lps27hhw_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.autozero; return ret; @@ -250,6 +255,9 @@ int32_t lps27hhw_pressure_snap_rst_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.reset_arp; return ret; @@ -294,6 +302,9 @@ int32_t lps27hhw_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.autorefp; return ret; @@ -338,6 +349,9 @@ int32_t lps27hhw_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.bdu; return ret; @@ -359,12 +373,8 @@ int32_t lps27hhw_data_rate_set(const stmdev_ctx_t *ctx, lps27hhw_odr_t val) ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - } + ret += lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, + (uint8_t *)&ctrl_reg2, 1); if (ret == 0) { @@ -400,18 +410,11 @@ int32_t lps27hhw_data_rate_get(const stmdev_ctx_t *ctx, lps27hhw_odr_t *val) ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + ret += lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, + (uint8_t *)&ctrl_reg2, 1); if (ret == 0) { - ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - } - - if (ret == 0) - { - ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) + ctrl_reg1.odr)) { @@ -519,6 +522,9 @@ int32_t lps27hhw_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_REF_P_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -564,6 +570,9 @@ int32_t lps27hhw_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_RPDS_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -634,6 +643,9 @@ int32_t lps27hhw_press_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.p_da; return ret; @@ -654,6 +666,9 @@ int32_t lps27hhw_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_STATUS, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.t_da; return ret; @@ -685,6 +700,9 @@ int32_t lps27hhw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_PRESS_OUT_XL, reg, 3); + + if (ret != 0) { return ret; } + *buff = reg[2]; *buff = (*buff * 256) + reg[1]; *buff = (*buff * 256) + reg[0]; @@ -707,6 +725,9 @@ int32_t lps27hhw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_TEMP_OUT_L, reg, 2); + + if (ret != 0) { return ret; } + *buff = reg[1]; *buff = (*buff * 256) + reg[0]; @@ -729,6 +750,9 @@ int32_t lps27hhw_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_DATA_OUT_PRESS_XL, reg, 3); + + if (ret != 0) { return ret; } + *buff = reg[2]; *buff = (*buff * 256) + reg[1]; *buff = (*buff * 256) + reg[0]; @@ -752,6 +776,9 @@ int32_t lps27hhw_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_DATA_OUT_TEMP_L, reg, 2); + + if (ret != 0) { return ret; } + *buff = reg[1]; *buff = (*buff * 256) + reg[0]; @@ -827,6 +854,9 @@ int32_t lps27hhw_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.swreset; return ret; @@ -874,6 +904,9 @@ int32_t lps27hhw_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.if_add_inc; return ret; @@ -919,6 +952,9 @@ int32_t lps27hhw_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.boot; return ret; @@ -978,6 +1014,8 @@ int32_t lps27hhw_lp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.lpfp_cfg) { case LPS27HHW_LPF_ODR_DIV_2: @@ -1054,6 +1092,8 @@ int32_t lps27hhw_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.i2c_disable) { case LPS27HHW_I2C_ENABLE: @@ -1114,6 +1154,8 @@ int32_t lps27hhw_i3c_interface_get(const stmdev_ctx_t *ctx, ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch ((reg.int_en_i3c << 4) + reg.int_en_i3c) { case LPS27HHW_I3C_ENABLE: @@ -1177,6 +1219,8 @@ int32_t lps27hhw_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sdo_pu_en) { case LPS27HHW_PULL_UP_DISCONNECT: @@ -1235,6 +1279,8 @@ int32_t lps27hhw_sda_mode_get(const stmdev_ctx_t *ctx, ret = lps27hhw_read_reg(ctx, LPS27HHW_IF_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sda_pu_en) { case LPS27HHW_PULL_UP_DISCONNECT: @@ -1292,6 +1338,8 @@ int32_t lps27hhw_spi_mode_get(const stmdev_ctx_t *ctx, lps27hhw_sim_t *val) ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG1, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.sim) { case LPS27HHW_SPI_4_WIRE: @@ -1365,6 +1413,8 @@ int32_t lps27hhw_int_notification_get(const stmdev_ctx_t *ctx, ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.lir) { case LPS27HHW_INT_PULSED: @@ -1423,6 +1473,8 @@ int32_t lps27hhw_pin_mode_get(const stmdev_ctx_t *ctx, ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.pp_od) { case LPS27HHW_PUSH_PULL: @@ -1482,6 +1534,8 @@ int32_t lps27hhw_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG2, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.int_h_l) { case LPS27HHW_ACTIVE_HIGH: @@ -1602,6 +1656,8 @@ int32_t lps27hhw_int_on_threshold_get(const stmdev_ctx_t *ctx, ret = lps27hhw_read_reg(ctx, LPS27HHW_INTERRUPT_CFG, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.pe) { case LPS27HHW_NO_THRESHOLD: @@ -1670,13 +1726,13 @@ int32_t lps27hhw_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff) lps27hhw_ths_p_l_t ths_p_l; lps27hhw_ths_p_h_t ths_p_h; - ret = lps27hhw_read_reg(ctx, LPS27HHW_THS_P_L, + ret += lps27hhw_read_reg(ctx, LPS27HHW_THS_P_L, (uint8_t *)&ths_p_l, 1); + ret += lps27hhw_read_reg(ctx, LPS27HHW_THS_P_H, + (uint8_t *)&ths_p_h, 1); if (ret == 0) { - ret = lps27hhw_read_reg(ctx, LPS27HHW_THS_P_H, - (uint8_t *)&ths_p_h, 1); *buff = (uint16_t)ths_p_h.ths << 8; *buff |= (uint16_t)ths_p_l.ths; } @@ -1737,6 +1793,8 @@ int32_t lps27hhw_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } + switch (reg.f_mode) { case LPS27HHW_BYPASS_MODE: @@ -1815,6 +1873,9 @@ int32_t lps27hhw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_CTRL, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.stop_on_wtm; return ret; @@ -1858,6 +1919,9 @@ int32_t lps27hhw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_WTM, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.wtm; return ret; @@ -1912,6 +1976,9 @@ int32_t lps27hhw_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_full_ia; return ret; @@ -1931,6 +1998,9 @@ int32_t lps27hhw_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t *) ®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_ovr_ia; return ret; @@ -1950,6 +2020,9 @@ int32_t lps27hhw_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_FIFO_STATUS2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_wtm_ia; return ret; @@ -1993,6 +2066,9 @@ int32_t lps27hhw_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.int_f_ovr; return ret; @@ -2038,6 +2114,9 @@ int32_t lps27hhw_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.int_f_wtm; return ret; @@ -2081,6 +2160,9 @@ int32_t lps27hhw_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps27hhw_read_reg(ctx, LPS27HHW_CTRL_REG3, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.int_f_full; return ret; @@ -2095,5 +2177,3 @@ int32_t lps27hhw_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h index c9071b1..8647b0c 100644 --- a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h +++ b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -706,5 +708,3 @@ int32_t lps27hhw_fifo_full_on_int_get(const stmdev_ctx_t *ctx, #endif #endif /*LPS27HHW_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.c b/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.c index 368fca3..a0d23cd 100644 --- a/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.c +++ b/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.c @@ -6,18 +6,18 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ #include "lps28dfw_reg.h" +#include /** * @defgroup LPS28DFW @@ -96,7 +96,7 @@ int32_t __weak lps28dfw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t * @brief Section collect all the utility functions needed by APIs. * @{ * - */ +*/ static void bytecpy(uint8_t *target, uint8_t *source) { @@ -160,6 +160,11 @@ int32_t lps28dfw_id_get(const stmdev_ctx_t *ctx, lps28dfw_id_t *val) int32_t ret; ret = lps28dfw_read_reg(ctx, LPS28DFW_WHO_AM_I, ®, 1); + if (ret != 0) + { + return ret; + } + val->whoami = reg; return ret; @@ -222,6 +227,10 @@ int32_t lps28dfw_bus_mode_get(const stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val) if (ret == 0) { ret = lps28dfw_read_reg(ctx, LPS28DFW_IF_CTRL, (uint8_t *)&if_ctrl, 1); + if (ret != 0) + { + return ret; + } switch (if_ctrl.int_en_i3c << 2) { @@ -353,6 +362,12 @@ int32_t lps28dfw_status_get(const stmdev_ctx_t *ctx, lps28dfw_stat_t *val) ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); } + + if (ret != 0) + { + return ret; + } + val->sw_reset = ctrl_reg2.swreset; val->boot = int_source.boot_on; val->drdy_pres = status.p_da; @@ -415,9 +430,14 @@ int32_t lps28dfw_pin_conf_get(const stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val) int32_t ret; ret = lps28dfw_read_reg(ctx, LPS28DFW_IF_CTRL, (uint8_t *)&if_ctrl, 1); - if (ret == 0) + if (ret != 0) { - ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + return ret; + } + ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); + if (ret != 0) + { + return ret; } val->int_pull_down = ~if_ctrl.int_pd_dis; @@ -444,15 +464,21 @@ int32_t lps28dfw_all_sources_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps28dfw_read_reg(ctx, LPS28DFW_STATUS, (uint8_t *)&status, 1); - if (ret == 0) + if (ret != 0) { - ret = lps28dfw_read_reg(ctx, LPS28DFW_INT_SOURCE, - (uint8_t *)&int_source, 1); + return ret; } - if (ret == 0) + ret = lps28dfw_read_reg(ctx, LPS28DFW_INT_SOURCE, + (uint8_t *)&int_source, 1); + if (ret != 0) { - ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); + return ret; + } + ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + if (ret != 0) + { + return ret; } val->drdy_pres = status.p_da; @@ -520,6 +546,10 @@ int32_t lps28dfw_mode_get(const stmdev_ctx_t *ctx, lps28dfw_md_t *val) int32_t ret; ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG1, reg, 2); + if (ret != 0) + { + return ret; + } if (ret == 0) { @@ -665,6 +695,10 @@ int32_t lps28dfw_data_get(const stmdev_ctx_t *ctx, lps28dfw_md_t *md, int32_t ret; ret = lps28dfw_read_reg(ctx, LPS28DFW_PRESS_OUT_XL, buff, 5); + if (ret != 0) + { + return ret; + } /* pressure conversion */ data->pressure.raw = (int32_t)buff[2]; @@ -707,6 +741,11 @@ int32_t lps28dfw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) uint8_t reg[3]; ret = lps28dfw_read_reg(ctx, LPS28DFW_PRESS_OUT_XL, reg, 3); + if (ret != 0) + { + return ret; + } + *buff = reg[2]; *buff = (*buff * 256U) + reg[1]; *buff = (*buff * 256U) + reg[0]; @@ -729,6 +768,11 @@ int32_t lps28dfw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) uint8_t reg[2]; ret = lps28dfw_read_reg(ctx, LPS28DFW_TEMP_OUT_L, reg, 2); + if (ret != 0) + { + return ret; + } + *buff = (int16_t)reg[1]; *buff = (*buff * 256) + (int16_t)reg[0]; @@ -752,41 +796,22 @@ int32_t lps28dfw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) * @brief FIFO operation mode selection.[set] * * @param ctx communication interface handler.(ptr) - * @param val set the FIFO operation mode.(ptr) + * @param val set the FIFO operation mode. * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_fifo_mode_set(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val) +int32_t lps28dfw_fifo_mode_set(const stmdev_ctx_t *ctx, lps28dfw_operation_t val) { lps28dfw_fifo_ctrl_t fifo_ctrl; - lps28dfw_fifo_wtm_t fifo_wtm; - uint8_t reg[2]; int32_t ret; - ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_CTRL, reg, 2); + ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); if (ret == 0) { - bytecpy((uint8_t *)&fifo_ctrl, ®[0]); - bytecpy((uint8_t *)&fifo_wtm, ®[1]); - - fifo_ctrl.f_mode = (uint8_t)val->operation & 0x03U; - fifo_ctrl.trig_modes = ((uint8_t)val->operation & 0x04U) >> 2; - - if (val->watermark != 0x00U) - { - fifo_ctrl.stop_on_wtm = PROPERTY_ENABLE; - } - else - { - fifo_ctrl.stop_on_wtm = PROPERTY_DISABLE; - } - - fifo_wtm.wtm = val->watermark; - - bytecpy(®[0], (uint8_t *)&fifo_ctrl); - bytecpy(®[1], (uint8_t *)&fifo_wtm); + fifo_ctrl.f_mode = (uint8_t)val & 0x03U; + fifo_ctrl.trig_modes = ((uint8_t)val & 0x04U) >> 2; - ret = lps28dfw_write_reg(ctx, LPS28DFW_FIFO_CTRL, reg, 2); + ret = lps28dfw_write_reg(ctx, LPS28DFW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); } return ret; } @@ -799,45 +824,132 @@ int32_t lps28dfw_fifo_mode_set(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_fifo_mode_get(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val) +int32_t lps28dfw_fifo_mode_get(const stmdev_ctx_t *ctx, lps28dfw_operation_t *val) { lps28dfw_fifo_ctrl_t fifo_ctrl; - lps28dfw_fifo_wtm_t fifo_wtm; - uint8_t reg[2]; int32_t ret; - ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_CTRL, reg, 2); - - bytecpy((uint8_t *)&fifo_ctrl, ®[0]); - bytecpy((uint8_t *)&fifo_wtm, ®[1]); + ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret != 0) + { + return ret; + } switch ((fifo_ctrl.trig_modes << 2) | fifo_ctrl.f_mode) { case LPS28DFW_BYPASS: - val->operation = LPS28DFW_BYPASS; + *val = LPS28DFW_BYPASS; break; case LPS28DFW_FIFO: - val->operation = LPS28DFW_FIFO; + *val = LPS28DFW_FIFO; break; case LPS28DFW_STREAM: - val->operation = LPS28DFW_STREAM; + *val = LPS28DFW_STREAM; break; case LPS28DFW_STREAM_TO_FIFO: - val->operation = LPS28DFW_STREAM_TO_FIFO; + *val = LPS28DFW_STREAM_TO_FIFO; break; case LPS28DFW_BYPASS_TO_STREAM: - val->operation = LPS28DFW_BYPASS_TO_STREAM; + *val = LPS28DFW_BYPASS_TO_STREAM; break; case LPS28DFW_BYPASS_TO_FIFO: - val->operation = LPS28DFW_BYPASS_TO_FIFO; + *val = LPS28DFW_BYPASS_TO_FIFO; break; default: - val->operation = LPS28DFW_BYPASS; + *val = LPS28DFW_BYPASS; break; } - val->watermark = fifo_wtm.wtm; + return ret; +} +/** + * @brief FIFO watermark selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val watermark value (0 disable; max 128) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lps28dfw_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lps28dfw_fifo_wtm_t fifo_wtm; + int32_t ret; + + assert(val < 128); + + ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + if (ret == 0) + { + fifo_wtm.wtm = val & 0x7F; + + ret = lps28dfw_write_reg(ctx, LPS28DFW_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + } + return ret; +} + +/** + * @brief FIFO watermark selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val watermark value (0 disable; max 128) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lps28dfw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lps28dfw_fifo_wtm_t fifo_wtm; + int32_t ret; + + ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_WTM, (uint8_t *)&fifo_wtm, 1); + if (ret == 0) + { + *val = fifo_wtm.wtm; + } + return ret; +} + +/** + * @brief FIFO stop_on_wtm selection.[set] + * + * @param ctx communication interface handler.(ptr) + * @param val set the stop_on_wtm mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lps28dfw_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lps28dfw_fifo_event_t val) +{ + lps28dfw_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret == 0) + { + fifo_ctrl.stop_on_wtm = (val == LPS28DFW_FIFO_EV_WTM) ? 1 : 0; + + ret = lps28dfw_write_reg(ctx, LPS28DFW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + } + return ret; +} + +/** + * @brief FIFO stop_on_wtm selection.[get] + * + * @param ctx communication interface handler.(ptr) + * @param val set the stop_on_wtm mode.(ptr) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lps28dfw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lps28dfw_fifo_event_t *val) +{ + lps28dfw_fifo_ctrl_t fifo_ctrl; + int32_t ret; + + ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret == 0) + { + *val = (fifo_ctrl.stop_on_wtm == 1) ? LPS28DFW_FIFO_EV_WTM : LPS28DFW_FIFO_EV_FULL; + } return ret; } @@ -857,6 +969,10 @@ int32_t lps28dfw_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + if (ret != 0) + { + return ret; + } *val = fifo_status1.fss; @@ -884,6 +1000,11 @@ int32_t lps28dfw_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, for (i = 0U; i < samp; i++) { ret = lps28dfw_read_reg(ctx, LPS28DFW_FIFO_DATA_OUT_PRESS_XL, fifo_data, 3); + if (ret != 0) + { + return ret; + } + data[i].raw = (int32_t)fifo_data[2]; data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[1]; data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[0]; @@ -982,10 +1103,15 @@ int32_t lps28dfw_interrupt_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG3, reg, 2); - if (ret == 0) + if (ret != 0) { - ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); + return ret; + } + ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG, + (uint8_t *)&interrupt_cfg, 1); + if (ret != 0) + { + return ret; } bytecpy((uint8_t *)&ctrl_reg3, ®[0]); @@ -1049,6 +1175,10 @@ int32_t lps28dfw_pin_int_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps28dfw_read_reg(ctx, LPS28DFW_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) + { + return ret; + } val->drdy_pres = ctrl_reg4.drdy; val->fifo_th = ctrl_reg4.int_f_wtm; @@ -1128,6 +1258,10 @@ int32_t lps28dfw_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG, reg, 3); + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&interrupt_cfg, ®[0]); bytecpy((uint8_t *)&ths_p_l, ®[1]); @@ -1199,6 +1333,10 @@ int32_t lps28dfw_reference_mode_get(const stmdev_ctx_t *ctx, lps28dfw_ref_md_t * ret = lps28dfw_read_reg(ctx, LPS28DFW_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1); + if (ret != 0) + { + return ret; + } switch ((interrupt_cfg.reset_az << 1) | interrupt_cfg.autorefp) @@ -1232,6 +1370,10 @@ int32_t lps28dfw_refp_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps28dfw_read_reg(ctx, LPS28DFW_REF_P_L, reg, 2); + if (ret != 0) + { + return ret; + } *val = (int16_t)reg[1]; *val = *val * 256 + (int16_t)reg[0]; @@ -1274,6 +1416,10 @@ int32_t lps28dfw_opc_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps28dfw_read_reg(ctx, LPS28DFW_RPDS_L, reg, 2); + if (ret != 0) + { + return ret; + } *val = (int16_t)reg[1]; *val = *val * 256 + (int16_t)reg[0]; @@ -1291,5 +1437,3 @@ int32_t lps28dfw_opc_get(const stmdev_ctx_t *ctx, int16_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.h b/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.h index 0ffbda5..546b5cc 100644 --- a/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.h +++ b/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -668,13 +670,20 @@ typedef enum LPS28DFW_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ } lps28dfw_operation_t; -typedef struct +int32_t lps28dfw_fifo_mode_set(const stmdev_ctx_t *ctx, lps28dfw_operation_t val); +int32_t lps28dfw_fifo_mode_get(const stmdev_ctx_t *ctx, lps28dfw_operation_t *val); + +int32_t lps28dfw_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps28dfw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { - lps28dfw_operation_t operation; - uint8_t watermark : 7; /* (0 disable) max 128.*/ -} lps28dfw_fifo_md_t; -int32_t lps28dfw_fifo_mode_set(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val); -int32_t lps28dfw_fifo_mode_get(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val); + LPS28DFW_FIFO_EV_WTM = 0x0, + LPS28DFW_FIFO_EV_FULL = 0x1, +} lps28dfw_fifo_event_t; + +int32_t lps28dfw_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lps28dfw_fifo_event_t val); +int32_t lps28dfw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lps28dfw_fifo_event_t *val); int32_t lps28dfw_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val); @@ -754,5 +763,3 @@ int32_t lps28dfw_opc_get(const stmdev_ctx_t *ctx, int16_t *val); #endif #endif /* LPS28DFW_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c index 40a1c35..bbd000a 100644 --- a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c +++ b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -159,6 +158,9 @@ int32_t lps33k_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg1.bdu; return ret; @@ -205,6 +207,8 @@ int32_t lps33k_low_pass_filter_mode_get(const stmdev_ctx_t *ctx, ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1.lpfp) { case LPS33K_LPF_ODR_DIV_2: @@ -266,6 +270,8 @@ int32_t lps33k_data_rate_get(const stmdev_ctx_t *ctx, lps33k_odr_t *val) ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1.odr) { case LPS33K_POWER_DOWN: @@ -338,6 +344,9 @@ int32_t lps33k_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg2.one_shot; return ret; @@ -379,6 +388,9 @@ int32_t lps33k_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_RPDS_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -399,6 +411,9 @@ int32_t lps33k_press_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.p_da; return ret; @@ -418,6 +433,9 @@ int32_t lps33k_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.t_da; return ret; @@ -437,6 +455,9 @@ int32_t lps33k_press_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.p_or; return ret; @@ -456,6 +477,9 @@ int32_t lps33k_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) { return ret; } + *val = status.t_or; return ret; @@ -475,6 +499,9 @@ int32_t lps33k_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_PRESS_OUT_XL, reg, 3); + + if (ret != 0) { return ret; } + *buff = reg[2]; *buff = (*buff * 256) + reg[1]; *buff = (*buff * 256) + reg[0]; @@ -497,6 +524,9 @@ int32_t lps33k_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_TEMP_OUT_L, (uint8_t *) reg, 2); + + if (ret != 0) { return ret; } + *buff = reg[1]; *buff = (*buff * 256) + reg[0]; @@ -590,6 +620,9 @@ int32_t lps33k_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg2.swreset; return ret; @@ -633,6 +666,9 @@ int32_t lps33k_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg2.boot; return ret; @@ -676,6 +712,9 @@ int32_t lps33k_low_power_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_RES_CONF, (uint8_t *)&res_conf, 1); + + if (ret != 0) { return ret; } + *val = res_conf.lc_en; return ret; @@ -734,6 +773,9 @@ int32_t lps33k_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lps33k_read_reg(ctx, LPS33K_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg2.if_add_inc; return ret; @@ -748,5 +790,3 @@ int32_t lps33k_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h index 5d7917a..aae8b3f 100644 --- a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h +++ b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -384,5 +386,3 @@ int32_t lps33k_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* LPS33K_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c index ae3241f..9f7605e 100644 --- a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c +++ b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -225,6 +224,9 @@ int32_t lsm303agr_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_AUX_A, (uint8_t *)&status_reg_aux_a, 1); + + if (ret != 0) { return ret; } + *val = status_reg_aux_a.tda; return ret; @@ -245,6 +247,9 @@ int32_t lsm303agr_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_AUX_A, (uint8_t *)&status_reg_aux_a, 1); + + if (ret != 0) { return ret; } + *val = status_reg_aux_a.tor; return ret; @@ -264,6 +269,9 @@ int32_t lsm303agr_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm303agr_read_reg(ctx, LSM303AGR_OUT_TEMP_L_A, buff, 2); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -314,6 +322,8 @@ int32_t lsm303agr_temperature_meas_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_TEMP_CFG_REG_A, (uint8_t *)&temp_cfg_reg_a, 1); + if (ret != 0) { return ret; } + switch (temp_cfg_reg_a.temp_en) { case LSM303AGR_TEMP_DISABLE: @@ -412,12 +422,10 @@ int32_t lsm303agr_xl_operating_mode_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG1_A, (uint8_t *)&ctrl_reg1_a, 1); + ret += lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A, + (uint8_t *)&ctrl_reg4_a, 1); - if (ret == 0) - { - ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A, - (uint8_t *)&ctrl_reg4_a, 1); - } + if (ret != 0) { return ret; } if (ctrl_reg1_a.lpen != PROPERTY_DISABLE) { @@ -481,6 +489,8 @@ int32_t lsm303agr_xl_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG1_A, (uint8_t *)&ctrl_reg1_a, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1_a.odr) { case LSM303AGR_XL_POWER_DOWN: @@ -575,6 +585,9 @@ int32_t lsm303agr_xl_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A, (uint8_t *)&ctrl_reg2_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg2_a.fds; return ret; @@ -638,6 +651,8 @@ int32_t lsm303agr_xl_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A, (uint8_t *)&ctrl_reg2_a, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2_a.hpcf) { case LSM303AGR_AGGRESSIVE: @@ -708,6 +723,8 @@ int32_t lsm303agr_xl_high_pass_mode_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A, (uint8_t *)&ctrl_reg2_a, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2_a.hpm) { case LSM303AGR_NORMAL_WITH_RST: @@ -778,6 +795,8 @@ int32_t lsm303agr_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A, (uint8_t *)&ctrl_reg4_a, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4_a.fs) { case LSM303AGR_2g: @@ -847,6 +866,9 @@ int32_t lsm303agr_xl_block_data_update_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A, (uint8_t *)&ctrl_reg4_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg4_a.bdu; return ret; @@ -905,6 +927,9 @@ int32_t lsm303agr_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_A, (uint8_t *)&status_reg_a, 1); + + if (ret != 0) { return ret; } + *val = status_reg_a.zyxda; return ret; @@ -925,6 +950,9 @@ int32_t lsm303agr_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_A, (uint8_t *)&status_reg_a, 1); + + if (ret != 0) { return ret; } + *val = status_reg_a.zyxor; return ret; @@ -945,6 +973,9 @@ int32_t lsm303agr_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm303agr_read_reg(ctx, LSM303AGR_OUT_X_L_A, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -960,7 +991,7 @@ int32_t lsm303agr_acceleration_raw_get(const stmdev_ctx_t *ctx, * 16-bit number and represent hard-iron * offset in order to compensate environmental * effects. Data format is the same of - * output data raw: two’s complement with + * output data raw: two's complement with * 1LSb = 1.5mG. These values act on the * magnetic output data value in order to * delete the environmental offset.[set] @@ -991,7 +1022,7 @@ int32_t lsm303agr_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val) * 16-bit number and represent hard-iron * offset in order to compensate environmental * effects. Data format is the same of - * output data raw: two’s complement with + * output data raw: two's complement with * 1LSb = 1.5mG. These values act on the * magnetic output data value in order to * delete the environmental offset.[get] @@ -1007,6 +1038,9 @@ int32_t lsm303agr_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm303agr_read_reg(ctx, LSM303AGR_OFFSET_X_REG_L_M, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1061,6 +1095,8 @@ int32_t lsm303agr_mag_operating_mode_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_a_m.md) { case LSM303AGR_CONTINUOUS_MODE: @@ -1127,6 +1163,8 @@ int32_t lsm303agr_mag_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_a_m.odr) { case LSM303AGR_MG_ODR_10Hz: @@ -1197,6 +1235,8 @@ int32_t lsm303agr_mag_power_mode_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_a_m.lp) { case LSM303AGR_HIGH_RESOLUTION: @@ -1258,6 +1298,9 @@ int32_t lsm303agr_mag_offset_temp_comp_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_a_m.comp_temp_en; return ret; @@ -1307,6 +1350,8 @@ int32_t lsm303agr_mag_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M, (uint8_t *)&cfg_reg_b_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_b_m.lpf) { case LSM303AGR_ODR_DIV_2: @@ -1369,6 +1414,8 @@ int32_t lsm303agr_mag_set_rst_mode_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M, (uint8_t *)&cfg_reg_b_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_b_m.set_rst) { case LSM303AGR_SET_SENS_ODR_DIV_63: @@ -1447,6 +1494,9 @@ int32_t lsm303agr_mag_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M, (uint8_t *)&cfg_reg_b_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_b_m.off_canc_one_shot; return ret; @@ -1495,6 +1545,9 @@ int32_t lsm303agr_mag_block_data_update_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_c_m.bdu; return ret; @@ -1515,6 +1568,9 @@ int32_t lsm303agr_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_M, (uint8_t *)&status_reg_m, 1); + + if (ret != 0) { return ret; } + *val = status_reg_m.zyxda; return ret; @@ -1535,6 +1591,9 @@ int32_t lsm303agr_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_M, (uint8_t *)&status_reg_m, 1); + + if (ret != 0) { return ret; } + *val = status_reg_m.zyxor; return ret; @@ -1554,6 +1613,9 @@ int32_t lsm303agr_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm303agr_read_reg(ctx, LSM303AGR_OUTX_L_REG_M, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1637,6 +1699,8 @@ int32_t lsm303agr_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A, (uint8_t *)&ctrl_reg4_a, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4_a.st) { case LSM303AGR_ST_DISABLE: @@ -1703,6 +1767,8 @@ int32_t lsm303agr_xl_data_format_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A, (uint8_t *)&ctrl_reg4_a, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4_a.ble) { case LSM303AGR_XL_LSB_AT_LOW_ADD: @@ -1762,6 +1828,9 @@ int32_t lsm303agr_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A, (uint8_t *)&ctrl_reg5_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg5_a.boot; return ret; @@ -1843,6 +1912,9 @@ int32_t lsm303agr_mag_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_a_m.soft_rst; return ret; @@ -1889,6 +1961,9 @@ int32_t lsm303agr_mag_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_a_m.reboot; return ret; @@ -1935,6 +2010,9 @@ int32_t lsm303agr_mag_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_c_m.self_test; return ret; @@ -1984,6 +2062,8 @@ int32_t lsm303agr_mag_data_format_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_c_m.ble) { case LSM303AGR_MG_LSB_AT_LOW_ADD: @@ -2134,6 +2214,9 @@ int32_t lsm303agr_xl_int1_gen_threshold_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_THS_A, (uint8_t *)&int1_ths_a, 1); + + if (ret != 0) { return ret; } + *val = int1_ths_a.ths; return ret; @@ -2184,6 +2267,9 @@ int32_t lsm303agr_xl_int1_gen_duration_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_DURATION_A, (uint8_t *)&int1_duration_a, 1); + + if (ret != 0) { return ret; } + *val = int1_duration_a.d; return ret; @@ -2303,6 +2389,9 @@ int32_t lsm303agr_xl_int2_gen_threshold_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_THS_A, (uint8_t *)&int2_ths_a, 1); + + if (ret != 0) { return ret; } + *val = int2_ths_a.ths; return ret; @@ -2353,6 +2442,9 @@ int32_t lsm303agr_xl_int2_gen_duration_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_DURATION_A, (uint8_t *)&int2_duration_a, 1); + + if (ret != 0) { return ret; } + *val = int2_duration_a.d; return ret; @@ -2415,6 +2507,8 @@ int32_t lsm303agr_xl_high_pass_int_conf_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A, (uint8_t *)&ctrl_reg2_a, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg2_a.hp) { case LSM303AGR_DISC_FROM_INT_GENERATOR: @@ -2538,6 +2632,9 @@ int32_t lsm303agr_xl_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A, (uint8_t *)&ctrl_reg5_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg5_a.d4d_int2; return ret; @@ -2591,6 +2688,8 @@ int32_t lsm303agr_xl_int2pin_notification_mode_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A, (uint8_t *)&ctrl_reg5_a, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg5_a.lir_int2) { case LSM303AGR_INT2_PULSED: @@ -2654,6 +2753,9 @@ int32_t lsm303agr_xl_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A, (uint8_t *)&ctrl_reg5_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg5_a.d4d_int1; return ret; @@ -2707,6 +2809,8 @@ int32_t lsm303agr_xl_int1pin_notification_mode_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A, (uint8_t *)&ctrl_reg5_a, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg5_a.lir_int1) { case LSM303AGR_INT1_PULSED: @@ -2822,6 +2926,8 @@ int32_t lsm303agr_mag_offset_int_conf_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M, (uint8_t *)&cfg_reg_b_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_b_m.int_on_dataoff) { case LSM303AGR_CHECK_BEFORE: @@ -2881,6 +2987,9 @@ int32_t lsm303agr_mag_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_c_m.int_mag; return ret; @@ -2927,6 +3036,9 @@ int32_t lsm303agr_mag_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_c_m.int_mag_pin; return ret; @@ -2992,7 +3104,7 @@ int32_t lsm303agr_mag_int_gen_source_get(const stmdev_ctx_t *ctx, /** * @brief User-defined threshold value for xl interrupt event on generator. * Data format is the same of output - * data raw: two’s complement with + * data raw: two's complement with * 1LSb = 1.5mG.[set] * * @param ctx Read / write interface definitions.(ptr) @@ -3016,7 +3128,7 @@ int32_t lsm303agr_mag_int_gen_threshold_set(const stmdev_ctx_t *ctx, /** * @brief User-defined threshold value for xl interrupt event on generator. * Data format is the same of output - * data raw: two’s complement with + * data raw: two's complement with * 1LSb = 1.5mG.[get] * * @param ctx Read / write interface definitions.(ptr) @@ -3031,6 +3143,9 @@ int32_t lsm303agr_mag_int_gen_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm303agr_read_reg(ctx, LSM303AGR_INT_THS_L_REG_M, buff, 2); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -3091,6 +3206,9 @@ int32_t lsm303agr_xl_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A, (uint8_t *)&ctrl_reg5_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl_reg5_a.fifo_en; return ret; @@ -3139,6 +3257,9 @@ int32_t lsm303agr_xl_fifo_watermark_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A, (uint8_t *)&fifo_ctrl_reg_a, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl_reg_a.fth; return ret; @@ -3188,6 +3309,8 @@ int32_t lsm303agr_xl_fifo_trigger_event_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A, (uint8_t *)&fifo_ctrl_reg_a, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl_reg_a.tr) { case LSM303AGR_INT1_GEN: @@ -3250,6 +3373,8 @@ int32_t lsm303agr_xl_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A, (uint8_t *)&fifo_ctrl_reg_a, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl_reg_a.fm) { case LSM303AGR_BYPASS_MODE: @@ -3311,6 +3436,9 @@ int32_t lsm303agr_xl_fifo_data_level_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A, (uint8_t *)&fifo_src_reg_a, 1); + + if (ret != 0) { return ret; } + *val = fifo_src_reg_a.fss; return ret; @@ -3332,6 +3460,9 @@ int32_t lsm303agr_xl_fifo_empty_flag_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A, (uint8_t *)&fifo_src_reg_a, 1); + + if (ret != 0) { return ret; } + *val = fifo_src_reg_a.empty; return ret; @@ -3353,6 +3484,9 @@ int32_t lsm303agr_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A, (uint8_t *)&fifo_src_reg_a, 1); + + if (ret != 0) { return ret; } + *val = fifo_src_reg_a.ovrn_fifo; return ret; @@ -3374,6 +3508,9 @@ int32_t lsm303agr_xl_fifo_fth_flag_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A, (uint8_t *)&fifo_src_reg_a, 1); + + if (ret != 0) { return ret; } + *val = fifo_src_reg_a.wtm; return ret; @@ -3489,6 +3626,9 @@ int32_t lsm303agr_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_CLICK_THS_A, (uint8_t *)&click_ths_a, 1); + + if (ret != 0) { return ret; } + *val = click_ths_a.ths; return ret; @@ -3539,6 +3679,9 @@ int32_t lsm303agr_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_LIMIT_A, (uint8_t *)&time_limit_a, 1); + + if (ret != 0) { return ret; } + *val = time_limit_a.tli; return ret; @@ -3590,6 +3733,9 @@ int32_t lsm303agr_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_LATENCY_A, (uint8_t *)&time_latency_a, 1); + + if (ret != 0) { return ret; } + *val = time_latency_a.tla; return ret; @@ -3644,6 +3790,9 @@ int32_t lsm303agr_double_tap_timeout_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_WINDOW_A, (uint8_t *)&time_window_a, 1); + + if (ret != 0) { return ret; } + *val = time_window_a.tw; return ret; @@ -3707,6 +3856,9 @@ int32_t lsm303agr_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_ACT_THS_A, (uint8_t *)&act_ths_a, 1); + + if (ret != 0) { return ret; } + *val = act_ths_a.acth; return ret; @@ -3753,6 +3905,9 @@ int32_t lsm303agr_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303agr_read_reg(ctx, LSM303AGR_ACT_DUR_A, (uint8_t *)&act_dur_a, 1); + + if (ret != 0) { return ret; } + *val = act_dur_a.actd; return ret; @@ -3815,6 +3970,8 @@ int32_t lsm303agr_xl_spi_mode_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A, (uint8_t *)&ctrl_reg4_a, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg4_a.spi_enable) { case LSM303AGR_SPI_4_WIRE: @@ -3877,6 +4034,8 @@ int32_t lsm303agr_mag_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_c_m.i2c_dis) { case LSM303AGR_I2C_ENABLE: @@ -3904,5 +4063,3 @@ int32_t lsm303agr_mag_i2c_interface_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h index 1a332c1..6d625a1 100644 --- a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h +++ b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1357,5 +1359,3 @@ int32_t lsm303agr_mag_i2c_interface_get(const stmdev_ctx_t *ctx, #endif #endif /* LSM303AGR_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c index ae56f40..a5058ea 100644 --- a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c +++ b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -238,6 +237,9 @@ int32_t lsm303ah_xl_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t *)&ctrl1_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl1_a.bdu; return ret; @@ -286,6 +288,9 @@ int32_t lsm303ah_mg_block_data_update_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_c_m.bdu; return ret; @@ -335,6 +340,8 @@ int32_t lsm303ah_mg_data_format_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_c_m.ble) { case LSM303AH_MG_LSB_AT_LOW_ADD: @@ -394,6 +401,8 @@ int32_t lsm303ah_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t *)&ctrl1_a, 1); + if (ret != 0) { return ret; } + switch (ctrl1_a.fs) { case LSM303AH_XL_2g: @@ -462,6 +471,8 @@ int32_t lsm303ah_xl_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL1_A, (uint8_t *)&ctrl1_a, 1); + if (ret != 0) { return ret; } + switch ((ctrl1_a.hf_odr << 4) + ctrl1_a.odr) { case LSM303AH_XL_ODR_OFF: @@ -599,6 +610,9 @@ int32_t lsm303ah_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_A, (uint8_t *)&status_a, 1); + + if (ret != 0) { return ret; } + *val = status_a.drdy; return ret; @@ -619,6 +633,9 @@ int32_t lsm303ah_mg_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_REG_M, (uint8_t *)&status_reg_m, 1); + + if (ret != 0) { return ret; } + *val = status_reg_m.zyxda; return ret; @@ -639,6 +656,9 @@ int32_t lsm303ah_mg_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_STATUS_REG_M, (uint8_t *)&status_reg_m, 1); + + if (ret != 0) { return ret; } + *val = status_reg_m.zyxor; return ret; @@ -647,7 +667,7 @@ int32_t lsm303ah_mg_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) /** * @brief These registers comprise a 3 group of 16-bit number and represent * hard-iron offset in order to compensate environmental effects. Data - * format is the same of output data raw: two’s complement with + * format is the same of output data raw: two's complement with * 1LSb = 1.5mG. These values act on the magnetic output data value in * order to delete the environmental offset.[set] * @@ -675,7 +695,7 @@ int32_t lsm303ah_mg_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief These registers comprise a 3 group of 16-bit number and represent * hard-iron offset in order to compensate environmental effects. Data - * format is the same of output data raw: two’s complement with + * format is the same of output data raw: two's complement with * 1LSb = 1.5mG. These values act on the magnetic output data value in * order to delete the environmental offset.[get] * @@ -690,6 +710,9 @@ int32_t lsm303ah_mg_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_OFFSET_X_REG_L_M, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -744,6 +767,8 @@ int32_t lsm303ah_mg_operating_mode_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_a_m.md) { case LSM303AH_MG_CONTINUOUS_MODE: @@ -810,6 +835,8 @@ int32_t lsm303ah_mg_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_a_m.odr) { case LSM303AH_MG_ODR_10Hz: @@ -880,6 +907,8 @@ int32_t lsm303ah_mg_power_mode_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_a_m.lp) { case LSM303AH_MG_HIGH_RESOLUTION: @@ -941,6 +970,9 @@ int32_t lsm303ah_mg_offset_temp_comp_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_a_m.comp_temp_en; return ret; @@ -990,6 +1022,8 @@ int32_t lsm303ah_mg_set_rst_mode_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t *)&cfg_reg_b_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_b_m.set_rst) { case LSM303AH_MG_SET_SENS_ODR_DIV_63: @@ -1061,6 +1095,9 @@ int32_t lsm303ah_mg_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t *)&cfg_reg_b_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_b_m.off_canc_one_shot; return ret; @@ -1098,7 +1135,7 @@ int32_t lsm303ah_acceleration_module_raw_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers together - * express a 16-bit word in two’s complement.[get] + * express a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions.(ptr) * @param buff buffer that stores data read.(ptr) @@ -1117,7 +1154,7 @@ int32_t lsm303ah_xl_temperature_raw_get(const stmdev_ctx_t *ctx, /** * @brief Linear acceleration output register. - * The value is expressed as a 16-bit word in two’s complement.[get] + * The value is expressed as a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions.(ptr) * @param buff buffer that stores data read.(ptr) @@ -1130,6 +1167,9 @@ int32_t lsm303ah_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_OUT_X_L_A, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1154,6 +1194,9 @@ int32_t lsm303ah_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_OUTX_L_REG_M, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1178,6 +1221,9 @@ int32_t lsm303ah_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNTER_L_A, buff, 2); + + if (ret != 0) { return ret; } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -1271,6 +1317,9 @@ int32_t lsm303ah_xl_auto_increment_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl2_a.if_add_inc; return ret; @@ -1358,6 +1407,9 @@ int32_t lsm303ah_xl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl2_a.soft_reset; return ret; @@ -1404,6 +1456,9 @@ int32_t lsm303ah_mg_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_a_m.soft_rst; return ret; @@ -1447,6 +1502,9 @@ int32_t lsm303ah_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl2_a.boot; return ret; @@ -1493,6 +1551,9 @@ int32_t lsm303ah_mg_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_A_M, (uint8_t *)&cfg_reg_a_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_a_m.reboot; return ret; @@ -1539,6 +1600,8 @@ int32_t lsm303ah_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1); + if (ret != 0) { return ret; } + switch (ctrl3_a.st) { case LSM303AH_XL_ST_DISABLE: @@ -1602,6 +1665,9 @@ int32_t lsm303ah_mg_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_c_m.self_test; return ret; @@ -1648,6 +1714,8 @@ int32_t lsm303ah_xl_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t *)&ctrl5_a, 1); + if (ret != 0) { return ret; } + switch (ctrl5_a.drdy_pulsed) { case LSM303AH_XL_DRDY_LATCHED: @@ -1720,6 +1788,8 @@ int32_t lsm303ah_xl_hp_path_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1); + if (ret != 0) { return ret; } + switch (ctrl2_a.fds_slope) { case LSM303AH_XL_HP_INTERNAL_ONLY: @@ -1782,6 +1852,8 @@ int32_t lsm303ah_mg_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t *)&cfg_reg_b_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_b_m.lpf) { case LSM303AH_MG_ODR_DIV_2: @@ -1854,6 +1926,8 @@ int32_t lsm303ah_xl_spi_mode_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1); + if (ret != 0) { return ret; } + switch (ctrl2_a.sim) { case LSM303AH_XL_SPI_4_WIRE: @@ -1913,6 +1987,8 @@ int32_t lsm303ah_xl_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL2_A, (uint8_t *)&ctrl2_a, 1); + if (ret != 0) { return ret; } + switch (ctrl2_a.i2c_disable) { case LSM303AH_XL_I2C_ENABLE: @@ -1975,6 +2051,8 @@ int32_t lsm303ah_mg_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_c_m.i2c_dis) { case LSM303AH_MG_I2C_ENABLE: @@ -2037,6 +2115,8 @@ int32_t lsm303ah_xl_cs_mode_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A, (uint8_t *)&fifo_ctrl_a, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl_a.if_cs_pu_dis) { case LSM303AH_XL_PULL_UP_CONNECTED: @@ -2109,6 +2189,8 @@ int32_t lsm303ah_xl_pin_mode_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1); + if (ret != 0) { return ret; } + switch (ctrl3_a.pp_od) { case LSM303AH_XL_PUSH_PULL: @@ -2168,6 +2250,8 @@ int32_t lsm303ah_xl_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1); + if (ret != 0) { return ret; } + switch (ctrl3_a.h_lactive) { case LSM303AH_XL_ACTIVE_HIGH: @@ -2227,6 +2311,8 @@ int32_t lsm303ah_xl_int_notification_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1); + if (ret != 0) { return ret; } + switch (ctrl3_a.lir) { case LSM303AH_XL_INT_PULSED: @@ -2306,6 +2392,8 @@ int32_t lsm303ah_xl_pin_int1_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL4_A, (uint8_t *)&ctrl4_a, 1); + ret += lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, + (uint8_t *)&wake_up_dur_a, 1); if (ret == 0) { @@ -2316,15 +2404,10 @@ int32_t lsm303ah_xl_pin_int1_route_get(const stmdev_ctx_t *ctx, val->int1_ff = ctrl4_a.int1_ff; val->int1_wu = ctrl4_a.int1_wu; val->int1_s_tap = ctrl4_a.int1_s_tap; - } - if (ret == 0) - { - ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, - (uint8_t *)&wake_up_dur_a, 1); + val->int1_fss7 = wake_up_dur_a.int1_fss7; } - val->int1_fss7 = wake_up_dur_a.int1_fss7; return ret; } @@ -2374,6 +2457,9 @@ int32_t lsm303ah_xl_pin_int2_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t *)&ctrl5_a, 1); + + if (ret != 0) { return ret; } + val->int2_boot = ctrl5_a.int2_boot; val->int2_tilt = ctrl5_a.int2_tilt; val->int2_sig_mot = ctrl5_a.int2_sig_mot; @@ -2422,6 +2508,9 @@ int32_t lsm303ah_xl_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL5_A, (uint8_t *)&ctrl5_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl5_a.int2_on_int1; return ret; @@ -2468,6 +2557,9 @@ int32_t lsm303ah_mg_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_c_m.int_mag; return ret; @@ -2514,6 +2606,9 @@ int32_t lsm303ah_mg_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_C_M, (uint8_t *)&cfg_reg_c_m, 1); + + if (ret != 0) { return ret; } + *val = cfg_reg_c_m.int_mag_pin; return ret; @@ -2577,7 +2672,7 @@ int32_t lsm303ah_mg_int_gen_source_get(const stmdev_ctx_t *ctx, /** * @brief User-defined threshold value for xl interrupt event on generator. - * Data format is the same of output data raw: two’s complement with + * Data format is the same of output data raw: two's complement with * 1LSb = 1.5mG.[set] * * @param ctx read / write interface definitions.(ptr) @@ -2600,7 +2695,7 @@ int32_t lsm303ah_mg_int_gen_threshold_set(const stmdev_ctx_t *ctx, /** * @brief User-defined threshold value for xl interrupt event on generator. - * Data format is the same of output data raw: two’s complement with + * Data format is the same of output data raw: two's complement with * 1LSb = 1.5mG.[get] * * @param ctx read / write interface definitions.(ptr) @@ -2615,6 +2710,9 @@ int32_t lsm303ah_mg_int_gen_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_INT_THS_L_REG_M, buff, 2); + + if (ret != 0) { return ret; } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -2694,6 +2792,8 @@ int32_t lsm303ah_mg_offset_int_conf_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_CFG_REG_B_M, (uint8_t *)&cfg_reg_b_m, 1); + if (ret != 0) { return ret; } + switch (cfg_reg_b_m.int_on_dataoff) { case LSM303AH_MG_CHECK_BEFORE: @@ -2754,6 +2854,9 @@ int32_t lsm303ah_xl_wkup_threshold_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A, (uint8_t *)&wake_up_ths_a, 1); + + if (ret != 0) { return ret; } + *val = wake_up_ths_a.wu_ths; return ret; @@ -2800,6 +2903,9 @@ int32_t lsm303ah_xl_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t *)&wake_up_dur_a, 1); + + if (ret != 0) { return ret; } + *val = wake_up_dur_a.wu_dur; return ret; @@ -2858,6 +2964,9 @@ int32_t lsm303ah_xl_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A, (uint8_t *)&wake_up_ths_a, 1); + + if (ret != 0) { return ret; } + *val = wake_up_ths_a.sleep_on; return ret; @@ -2904,6 +3013,9 @@ int32_t lsm303ah_xl_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t *)&wake_up_dur_a, 1); + + if (ret != 0) { return ret; } + *val = wake_up_dur_a.sleep_dur; return ret; @@ -2962,6 +3074,9 @@ int32_t lsm303ah_xl_tap_detection_on_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_a.tap_z_en; return ret; @@ -3007,6 +3122,9 @@ int32_t lsm303ah_xl_tap_detection_on_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_a.tap_y_en; return ret; @@ -3052,6 +3170,9 @@ int32_t lsm303ah_xl_tap_detection_on_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm303ah_read_reg(ctx, LSM303AH_CTRL3_A, (uint8_t *)&ctrl3_a, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_a.tap_x_en; return ret; @@ -3098,6 +3219,9 @@ int32_t lsm303ah_xl_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A, (uint8_t *)&tap_6d_ths_a, 1); + + if (ret != 0) { return ret; } + *val = tap_6d_ths_a.tap_ths; return ret; @@ -3152,6 +3276,9 @@ int32_t lsm303ah_xl_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A, (uint8_t *)&int_dur_a, 1); + + if (ret != 0) { return ret; } + *val = int_dur_a.shock; return ret; @@ -3206,6 +3333,9 @@ int32_t lsm303ah_xl_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A, (uint8_t *)&int_dur_a, 1); + + if (ret != 0) { return ret; } + *val = int_dur_a.quiet; return ret; @@ -3260,6 +3390,9 @@ int32_t lsm303ah_xl_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_INT_DUR_A, (uint8_t *)&int_dur_a, 1); + + if (ret != 0) { return ret; } + *val = int_dur_a.lat; return ret; @@ -3309,6 +3442,8 @@ int32_t lsm303ah_xl_tap_mode_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_THS_A, (uint8_t *)&wake_up_ths_a, 1); + if (ret != 0) { return ret; } + switch (wake_up_ths_a.single_double_tap) { case LSM303AH_XL_ONLY_SINGLE: @@ -3402,6 +3537,8 @@ int32_t lsm303ah_xl_6d_threshold_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A, (uint8_t *)&tap_6d_ths_a, 1); + if (ret != 0) { return ret; } + switch (tap_6d_ths_a._6d_ths) { case LSM303AH_XL_DEG_80: @@ -3469,6 +3606,9 @@ int32_t lsm303ah_xl_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_TAP_6D_THS_A, (uint8_t *)&tap_6d_ths_a, 1); + + if (ret != 0) { return ret; } + *val = tap_6d_ths_a._4d_en; return ret; @@ -3561,12 +3701,10 @@ int32_t lsm303ah_xl_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_WAKE_UP_DUR_A, (uint8_t *)&wake_up_dur_a, 1); + ret += lsm303ah_read_reg(ctx, LSM303AH_FREE_FALL_A, + (uint8_t *)&free_fall_a, 1); - if (ret == 0) - { - ret = lsm303ah_read_reg(ctx, LSM303AH_FREE_FALL_A, - (uint8_t *)&free_fall_a, 1); - } + if (ret != 0) { return ret; } *val = (wake_up_dur_a.ff_dur << 5) + free_fall_a.ff_dur; @@ -3614,6 +3752,9 @@ int32_t lsm303ah_xl_ff_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_FREE_FALL_A, (uint8_t *)&free_fall_a, 1); + + if (ret != 0) { return ret; } + *val = free_fall_a.ff_ths; return ret; @@ -3676,6 +3817,9 @@ int32_t lsm303ah_xl_fifo_xl_module_batch_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A, (uint8_t *)&fifo_ctrl_a, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl_a.module_to_fifo; return ret; @@ -3725,6 +3869,8 @@ int32_t lsm303ah_xl_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_CTRL_A, (uint8_t *)&fifo_ctrl_a, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl_a.fmode) { case LSM303AH_XL_BYPASS_MODE: @@ -3806,6 +3952,9 @@ int32_t lsm303ah_xl_fifo_full_flag_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A, (uint8_t *)&fifo_src_a, 1); + + if (ret != 0) { return ret; } + *val = fifo_src_a.diff; return ret; @@ -3826,6 +3975,9 @@ int32_t lsm303ah_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A, (uint8_t *)&fifo_src_a, 1); + + if (ret != 0) { return ret; } + *val = fifo_src_a.fifo_ovr; return ret; @@ -3846,6 +3998,9 @@ int32_t lsm303ah_xl_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A, (uint8_t *)&fifo_src_a, 1); + + if (ret != 0) { return ret; } + *val = fifo_src_a.fth; return ret; @@ -3868,10 +4023,10 @@ int32_t lsm303ah_xl_fifo_data_level_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SRC_A, (uint8_t *)&fifo_src_a, 1); + ret += lsm303ah_read_reg(ctx, LSM303AH_FIFO_SAMPLES_A, &fifo_sample_a, 1); if (ret == 0) { - ret = lsm303ah_read_reg(ctx, LSM303AH_FIFO_SAMPLES_A, &fifo_sample_a, 1); *val = fifo_src_a.diff; *val = *val << 8; *val += fifo_sample_a; @@ -3952,6 +4107,9 @@ int32_t lsm303ah_xl_pedo_threshold_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A, (uint8_t *)&step_counter_minths_a, 1); + + if (ret != 0) { return ret; } + *val = step_counter_minths_a.sc_mths; return ret; @@ -4001,6 +4159,8 @@ int32_t lsm303ah_xl_pedo_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A, (uint8_t *)&step_counter_minths_a, 1); + if (ret != 0) { return ret; } + switch (step_counter_minths_a.pedo4g) { case LSM303AH_XL_PEDO_AT_2g: @@ -4062,6 +4222,9 @@ int32_t lsm303ah_xl_pedo_step_reset_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNTER_MINTHS_A, (uint8_t *)&step_counter_minths_a, 1); + + if (ret != 0) { return ret; } + *val = step_counter_minths_a.rst_nstep; return ret; @@ -4083,6 +4246,9 @@ int32_t lsm303ah_xl_pedo_step_detect_flag_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CK_GATE_A, (uint8_t *)&func_ck_gate_a, 1); + + if (ret != 0) { return ret; } + *val = func_ck_gate_a.step_detect; return ret; @@ -4129,6 +4295,9 @@ int32_t lsm303ah_xl_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t *)&func_ctrl_a, 1); + + if (ret != 0) { return ret; } + *val = func_ctrl_a.step_cnt_on; return ret; @@ -4163,10 +4332,7 @@ int32_t lsm303ah_xl_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, (uint8_t *)&pedo_deb_reg_a, 1); } - if (ret == 0) - { - ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); - } + ret += lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); return ret; } @@ -4196,9 +4362,10 @@ int32_t lsm303ah_xl_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = pedo_deb_reg_a.deb_step; - ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); } + ret += lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); + return ret; } @@ -4232,10 +4399,7 @@ int32_t lsm303ah_xl_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&pedo_deb_reg_a, 1); } - if (ret == 0) - { - ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); - } + ret += lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); return ret; } @@ -4266,9 +4430,10 @@ int32_t lsm303ah_xl_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = pedo_deb_reg_a.deb_time; - ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); } + ret += lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); + return ret; } @@ -4293,10 +4458,7 @@ int32_t lsm303ah_xl_pedo_steps_period_set(const stmdev_ctx_t *ctx, ret = lsm303ah_write_reg(ctx, LSM303AH_STEP_COUNT_DELTA_A, buff, 1); } - if (ret == 0) - { - ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); - } + ret += lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); return ret; } @@ -4322,10 +4484,7 @@ int32_t lsm303ah_xl_pedo_steps_period_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_STEP_COUNT_DELTA_A, buff, 1); } - if (ret == 0) - { - ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); - } + ret += lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); return ret; } @@ -4359,6 +4518,9 @@ int32_t lsm303ah_xl_motion_data_ready_flag_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CK_GATE_A, (uint8_t *)&func_ck_gate_a, 1); + + if (ret != 0) { return ret; } + *val = func_ck_gate_a.sig_mot_detect; return ret; @@ -4405,6 +4567,9 @@ int32_t lsm303ah_xl_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t *)&func_ctrl_a, 1); + + if (ret != 0) { return ret; } + *val = func_ctrl_a.sign_mot_on; return ret; @@ -4441,10 +4606,7 @@ int32_t lsm303ah_xl_motion_threshold_set(const stmdev_ctx_t *ctx, ret = lsm303ah_write_reg(ctx, LSM303AH_SM_THS_A, (uint8_t *)&sm_ths_a, 1); } - if (ret == 0) - { - ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); - } + ret += lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); return ret; } @@ -4477,9 +4639,10 @@ int32_t lsm303ah_xl_motion_threshold_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = sm_ths_a.sm_ths; - ret = lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); } + ret += lsm303ah_xl_mem_bank_set(ctx, LSM303AH_XL_USER_BANK); + return ret; } @@ -4512,6 +4675,9 @@ int32_t lsm303ah_xl_tilt_data_ready_flag_get(const stmdev_ctx_t *ctx, ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CK_GATE_A, (uint8_t *)&func_ck_gate_a, 1); + + if (ret != 0) { return ret; } + *val = func_ck_gate_a.tilt_int; return ret; @@ -4558,6 +4724,9 @@ int32_t lsm303ah_xl_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t *)&func_ctrl_a, 1); + + if (ret != 0) { return ret; } + *val = func_ctrl_a.tilt_on; return ret; @@ -4617,6 +4786,9 @@ int32_t lsm303ah_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm303ah_read_reg(ctx, LSM303AH_FUNC_CTRL_A, (uint8_t *)&func_ctrl_a, 1); + + if (ret != 0) { return ret; } + *val = func_ctrl_a.module_on; return ret; @@ -4631,5 +4803,3 @@ int32_t lsm303ah_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h index 126e909..96798e4 100644 --- a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h +++ b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1424,5 +1426,3 @@ int32_t lsm303ah_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /*LSM303AH_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c index 6bc987f..46a81ed 100644 --- a/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c +++ b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -208,6 +207,8 @@ int32_t lsm6ds3tr_c_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl1_xl.fs_xl) { case LSM6DS3TR_C_2g: @@ -278,6 +279,8 @@ int32_t lsm6ds3tr_c_xl_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl1_xl.odr_xl) { case LSM6DS3TR_C_XL_ODR_OFF: @@ -380,6 +383,8 @@ int32_t lsm6ds3tr_c_gy_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) { return ret; } + switch (ctrl2_g.fs_g) { case LSM6DS3TR_C_250dps: @@ -454,6 +459,8 @@ int32_t lsm6ds3tr_c_gy_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) { return ret; } + switch (ctrl2_g.odr_g) { case LSM6DS3TR_C_GY_ODR_OFF: @@ -551,6 +558,9 @@ int32_t lsm6ds3tr_c_block_data_update_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_c.bdu; return ret; @@ -602,6 +612,8 @@ int32_t lsm6ds3tr_c_xl_offset_weight_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } + switch (ctrl6_c.usr_off_w) { case LSM6DS3TR_C_LSb_1mg: @@ -664,6 +676,8 @@ int32_t lsm6ds3tr_c_xl_power_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } + switch (ctrl6_c.xl_hm_mode) { case LSM6DS3TR_C_XL_HIGH_PERFORMANCE: @@ -730,6 +744,8 @@ int32_t lsm6ds3tr_c_rounding_on_status_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) { return ret; } + switch (ctrl7_g.rounding_status) { case LSM6DS3TR_C_STAT_RND_DISABLE: @@ -792,6 +808,8 @@ int32_t lsm6ds3tr_c_gy_power_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) { return ret; } + switch (ctrl7_g.g_hm_mode) { case LSM6DS3TR_C_GY_HIGH_PERFORMANCE: @@ -866,17 +884,14 @@ int32_t lsm6ds3tr_c_all_sources_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B); - } - if (ret == 0) - { - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK, - (uint8_t *) & (val->a_wrist_tilt_mask), 1); - } + if (ret == 0) + { + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK, + (uint8_t *) & (val->a_wrist_tilt_mask), 1); + } - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); } return ret; @@ -916,6 +931,9 @@ int32_t lsm6ds3tr_c_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.xlda; return ret; @@ -937,6 +955,9 @@ int32_t lsm6ds3tr_c_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.gda; return ret; @@ -958,13 +979,16 @@ int32_t lsm6ds3tr_c_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.tda; return ret; } /** - * @brief Accelerometer axis user offset correction expressed in two’s + * @brief Accelerometer axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C. * The value must be in the range [-127 127].[set] * @@ -984,7 +1008,7 @@ int32_t lsm6ds3tr_c_xl_usr_offset_set(const stmdev_ctx_t *ctx, } /** - * @brief Accelerometer axis user offset correction xpressed in two’s + * @brief Accelerometer axis user offset correction xpressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C. * The value must be in the range [-127 127].[get] * @@ -1064,6 +1088,9 @@ int32_t lsm6ds3tr_c_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.timer_en; return ret; @@ -1123,6 +1150,8 @@ int32_t lsm6ds3tr_c_timestamp_res_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) { return ret; } + switch (wake_up_dur.timer_hr) { case LSM6DS3TR_C_LSB_6ms4: @@ -1199,6 +1228,8 @@ int32_t lsm6ds3tr_c_rounding_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.rounding) { case LSM6DS3TR_C_ROUND_DISABLE: @@ -1243,7 +1274,7 @@ int32_t lsm6ds3tr_c_rounding_mode_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers together - * express a 16-bit word in two’s complement.[get] + * express a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -1257,6 +1288,9 @@ int32_t lsm6ds3tr_c_temperature_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUT_TEMP_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1265,7 +1299,7 @@ int32_t lsm6ds3tr_c_temperature_raw_get(const stmdev_ctx_t *ctx, /** * @brief Angular rate sensor. The value is expressed as a 16-bit word in - * two’s complement.[get] + * two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -1279,6 +1313,9 @@ int32_t lsm6ds3tr_c_angular_rate_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUTX_L_G, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1291,7 +1328,7 @@ int32_t lsm6ds3tr_c_angular_rate_raw_get(const stmdev_ctx_t *ctx, /** * @brief Linear acceleration output register. The value is expressed - * as a 16-bit word in two’s complement.[get] + * as a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -1305,6 +1342,9 @@ int32_t lsm6ds3tr_c_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUTX_L_XL, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1330,6 +1370,9 @@ int32_t lsm6ds3tr_c_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUT_MAG_RAW_X_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1419,6 +1462,8 @@ int32_t lsm6ds3tr_c_mem_bank_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) { return ret; } + switch (func_cfg_access.func_cfg_en) { case LSM6DS3TR_C_USER_BANK: @@ -1481,6 +1526,8 @@ int32_t lsm6ds3tr_c_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G, (uint8_t *)&drdy_pulse_cfg_g, 1); + if (ret != 0) { return ret; } + switch (drdy_pulse_cfg_g.drdy_pulsed) { case LSM6DS3TR_C_DRDY_LATCHED: @@ -1557,6 +1604,9 @@ int32_t lsm6ds3tr_c_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_c.sw_reset; return ret; @@ -1606,6 +1656,8 @@ int32_t lsm6ds3tr_c_data_format_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + switch (ctrl3_c.ble) { case LSM6DS3TR_C_LSB_AT_LOW_ADD: @@ -1668,6 +1720,9 @@ int32_t lsm6ds3tr_c_auto_increment_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_c.if_inc; return ret; @@ -1714,6 +1769,9 @@ int32_t lsm6ds3tr_c_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_c.boot; return ret; @@ -1763,6 +1821,8 @@ int32_t lsm6ds3tr_c_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.st_xl) { case LSM6DS3TR_C_XL_ST_DISABLE: @@ -1829,6 +1889,8 @@ int32_t lsm6ds3tr_c_gy_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.st_g) { case LSM6DS3TR_C_GY_ST_DISABLE: @@ -1909,6 +1971,9 @@ int32_t lsm6ds3tr_c_filter_settling_mask_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl4_c.drdy_mask; return ret; @@ -1960,6 +2025,8 @@ int32_t lsm6ds3tr_c_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t *)&tap_cfg, 1); + if (ret != 0) { return ret; } + switch (tap_cfg.slope_fds) { case LSM6DS3TR_C_USE_SLOPE: @@ -2037,6 +2104,8 @@ int32_t lsm6ds3tr_c_xl_filter_analog_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl1_xl.bw0_xl) { case LSM6DS3TR_C_XL_ANA_BW_1k5Hz: @@ -2143,19 +2212,22 @@ int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - switch (ctrl1_xl.lpf1_bw_sel) + if (ret == 0) { - case LSM6DS3TR_C_XL_LP1_ODR_DIV_2: - *val = LSM6DS3TR_C_XL_LP1_ODR_DIV_2; - break; + switch (ctrl1_xl.lpf1_bw_sel) + { + case LSM6DS3TR_C_XL_LP1_ODR_DIV_2: + *val = LSM6DS3TR_C_XL_LP1_ODR_DIV_2; + break; - case LSM6DS3TR_C_XL_LP1_ODR_DIV_4: - *val = LSM6DS3TR_C_XL_LP1_ODR_DIV_4; - break; + case LSM6DS3TR_C_XL_LP1_ODR_DIV_4: + *val = LSM6DS3TR_C_XL_LP1_ODR_DIV_4; + break; - default: - *val = LSM6DS3TR_C_XL_LP1_NA; - break; + default: + *val = LSM6DS3TR_C_XL_LP1_NA; + break; + } } } } @@ -2307,6 +2379,9 @@ int32_t lsm6ds3tr_c_xl_reference_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl8_xl.hp_ref_mode; return ret; @@ -2358,6 +2433,8 @@ int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { return ret; } + if (ctrl8_xl.hp_slope_xl_en == 0x00U) { *val = LSM6DS3TR_C_XL_HP_NA; @@ -2476,72 +2553,67 @@ int32_t lsm6ds3tr_c_gy_band_pass_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + ret += lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, + (uint8_t *)&ctrl4_c, 1); + ret += lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, + (uint8_t *)&ctrl7_g, 1); if (ret == 0) { - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, - (uint8_t *)&ctrl4_c, 1); - - if (ret == 0) + switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) + + (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype) { - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, - (uint8_t *)&ctrl7_g, 1); - - switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) + - (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype) - { - case LSM6DS3TR_C_HP_16mHz_LP2: - *val = LSM6DS3TR_C_HP_16mHz_LP2; - break; + case LSM6DS3TR_C_HP_16mHz_LP2: + *val = LSM6DS3TR_C_HP_16mHz_LP2; + break; - case LSM6DS3TR_C_HP_65mHz_LP2: - *val = LSM6DS3TR_C_HP_65mHz_LP2; - break; + case LSM6DS3TR_C_HP_65mHz_LP2: + *val = LSM6DS3TR_C_HP_65mHz_LP2; + break; - case LSM6DS3TR_C_HP_260mHz_LP2: - *val = LSM6DS3TR_C_HP_260mHz_LP2; - break; + case LSM6DS3TR_C_HP_260mHz_LP2: + *val = LSM6DS3TR_C_HP_260mHz_LP2; + break; - case LSM6DS3TR_C_HP_1Hz04_LP2: - *val = LSM6DS3TR_C_HP_1Hz04_LP2; - break; + case LSM6DS3TR_C_HP_1Hz04_LP2: + *val = LSM6DS3TR_C_HP_1Hz04_LP2; + break; - case LSM6DS3TR_C_HP_DISABLE_LP1_LIGHT: - *val = LSM6DS3TR_C_HP_DISABLE_LP1_LIGHT; - break; + case LSM6DS3TR_C_HP_DISABLE_LP1_LIGHT: + *val = LSM6DS3TR_C_HP_DISABLE_LP1_LIGHT; + break; - case LSM6DS3TR_C_HP_DISABLE_LP1_NORMAL: - *val = LSM6DS3TR_C_HP_DISABLE_LP1_NORMAL; - break; + case LSM6DS3TR_C_HP_DISABLE_LP1_NORMAL: + *val = LSM6DS3TR_C_HP_DISABLE_LP1_NORMAL; + break; - case LSM6DS3TR_C_HP_DISABLE_LP_STRONG: - *val = LSM6DS3TR_C_HP_DISABLE_LP_STRONG; - break; + case LSM6DS3TR_C_HP_DISABLE_LP_STRONG: + *val = LSM6DS3TR_C_HP_DISABLE_LP_STRONG; + break; - case LSM6DS3TR_C_HP_DISABLE_LP1_AGGRESSIVE: - *val = LSM6DS3TR_C_HP_DISABLE_LP1_AGGRESSIVE; - break; + case LSM6DS3TR_C_HP_DISABLE_LP1_AGGRESSIVE: + *val = LSM6DS3TR_C_HP_DISABLE_LP1_AGGRESSIVE; + break; - case LSM6DS3TR_C_HP_16mHz_LP1_LIGHT: - *val = LSM6DS3TR_C_HP_16mHz_LP1_LIGHT; - break; + case LSM6DS3TR_C_HP_16mHz_LP1_LIGHT: + *val = LSM6DS3TR_C_HP_16mHz_LP1_LIGHT; + break; - case LSM6DS3TR_C_HP_65mHz_LP1_NORMAL: - *val = LSM6DS3TR_C_HP_65mHz_LP1_NORMAL; - break; + case LSM6DS3TR_C_HP_65mHz_LP1_NORMAL: + *val = LSM6DS3TR_C_HP_65mHz_LP1_NORMAL; + break; - case LSM6DS3TR_C_HP_260mHz_LP1_STRONG: - *val = LSM6DS3TR_C_HP_260mHz_LP1_STRONG; - break; + case LSM6DS3TR_C_HP_260mHz_LP1_STRONG: + *val = LSM6DS3TR_C_HP_260mHz_LP1_STRONG; + break; - case LSM6DS3TR_C_HP_1Hz04_LP1_AGGRESSIVE: - *val = LSM6DS3TR_C_HP_1Hz04_LP1_AGGRESSIVE; - break; + case LSM6DS3TR_C_HP_1Hz04_LP1_AGGRESSIVE: + *val = LSM6DS3TR_C_HP_1Hz04_LP1_AGGRESSIVE; + break; - default: - *val = LSM6DS3TR_C_HP_GY_BAND_NA; - break; - } + default: + *val = LSM6DS3TR_C_HP_GY_BAND_NA; + break; } } @@ -2605,6 +2677,8 @@ int32_t lsm6ds3tr_c_spi_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + switch (ctrl3_c.sim) { case LSM6DS3TR_C_SPI_4_WIRE: @@ -2667,6 +2741,8 @@ int32_t lsm6ds3tr_c_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { return ret; } + switch (ctrl4_c.i2c_disable) { case LSM6DS3TR_C_I2C_ENABLE: @@ -2843,6 +2919,12 @@ int32_t lsm6ds3tr_c_pin_int1_route_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + ret += lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG, + (uint8_t *)&md1_cfg, 1); + ret += lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, + (uint8_t *)&ctrl4_c, 1); + ret += lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t *)&master_config, 1); if (ret == 0) { @@ -2854,30 +2936,19 @@ int32_t lsm6ds3tr_c_pin_int1_route_get(const stmdev_ctx_t *ctx, val->int1_full_flag = int1_ctrl.int1_full_flag; val->int1_sign_mot = int1_ctrl.int1_sign_mot; val->int1_step_detector = int1_ctrl.int1_step_detector ; - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG, - (uint8_t *)&md1_cfg, 1); - if (ret == 0) - { - val->int1_timer = md1_cfg.int1_timer; - val->int1_tilt = md1_cfg.int1_tilt; - val->int1_6d = md1_cfg.int1_6d; - val->int1_double_tap = md1_cfg.int1_double_tap; - val->int1_ff = md1_cfg.int1_ff; - val->int1_wu = md1_cfg.int1_wu; - val->int1_single_tap = md1_cfg.int1_single_tap; - val->int1_inact_state = md1_cfg.int1_inact_state; - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, - (uint8_t *)&ctrl4_c, 1); + val->int1_timer = md1_cfg.int1_timer; + val->int1_tilt = md1_cfg.int1_tilt; + val->int1_6d = md1_cfg.int1_6d; + val->int1_double_tap = md1_cfg.int1_double_tap; + val->int1_ff = md1_cfg.int1_ff; + val->int1_wu = md1_cfg.int1_wu; + val->int1_single_tap = md1_cfg.int1_single_tap; + val->int1_inact_state = md1_cfg.int1_inact_state; - if (ret == 0) - { - val->den_drdy_int1 = ctrl4_c.den_drdy_int1; - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - val->den_drdy_int1 = master_config.drdy_on_int1; - } - } + val->den_drdy_int1 = ctrl4_c.den_drdy_int1; + + val->den_drdy_int1 = master_config.drdy_on_int1; } return ret; @@ -3011,6 +3082,10 @@ int32_t lsm6ds3tr_c_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + ret += lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG, + (uint8_t *)&md2_cfg, 1); + ret += lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G, + (uint8_t *)&drdy_pulse_cfg_g, 1); if (ret == 0) { @@ -3022,23 +3097,17 @@ int32_t lsm6ds3tr_c_pin_int2_route_get(const stmdev_ctx_t *ctx, val->int2_full_flag = int2_ctrl.int2_full_flag; val->int2_step_count_ov = int2_ctrl.int2_step_count_ov; val->int2_step_delta = int2_ctrl.int2_step_delta; - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG, - (uint8_t *)&md2_cfg, 1); - if (ret == 0) - { - val->int2_iron = md2_cfg.int2_iron; - val->int2_tilt = md2_cfg.int2_tilt; - val->int2_6d = md2_cfg.int2_6d; - val->int2_double_tap = md2_cfg.int2_double_tap; - val->int2_ff = md2_cfg.int2_ff; - val->int2_wu = md2_cfg.int2_wu; - val->int2_single_tap = md2_cfg.int2_single_tap; - val->int2_inact_state = md2_cfg.int2_inact_state; - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G, - (uint8_t *)&drdy_pulse_cfg_g, 1); - val->int2_wrist_tilt = drdy_pulse_cfg_g.int2_wrist_tilt; - } + val->int2_iron = md2_cfg.int2_iron; + val->int2_tilt = md2_cfg.int2_tilt; + val->int2_6d = md2_cfg.int2_6d; + val->int2_double_tap = md2_cfg.int2_double_tap; + val->int2_ff = md2_cfg.int2_ff; + val->int2_wu = md2_cfg.int2_wu; + val->int2_single_tap = md2_cfg.int2_single_tap; + val->int2_inact_state = md2_cfg.int2_inact_state; + + val->int2_wrist_tilt = drdy_pulse_cfg_g.int2_wrist_tilt; } return ret; @@ -3088,6 +3157,8 @@ int32_t lsm6ds3tr_c_pin_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + switch (ctrl3_c.pp_od) { case LSM6DS3TR_C_PUSH_PULL: @@ -3150,6 +3221,8 @@ int32_t lsm6ds3tr_c_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + switch (ctrl3_c.h_lactive) { case LSM6DS3TR_C_ACTIVE_HIGH: @@ -3209,6 +3282,9 @@ int32_t lsm6ds3tr_c_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl4_c.int2_on_int1; return ret; @@ -3258,6 +3334,8 @@ int32_t lsm6ds3tr_c_int_notification_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t *)&tap_cfg, 1); + if (ret != 0) { return ret; } + switch (tap_cfg.lir) { case LSM6DS3TR_C_INT_PULSED: @@ -3331,6 +3409,9 @@ int32_t lsm6ds3tr_c_wkup_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { return ret; } + *val = wake_up_ths.wk_ths; return ret; @@ -3377,6 +3458,9 @@ int32_t lsm6ds3tr_c_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + if (ret != 0) { return ret; } + *val = wake_up_dur.wake_dur; return ret; @@ -3436,6 +3520,9 @@ int32_t lsm6ds3tr_c_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl4_c.sleep; return ret; @@ -3485,6 +3572,8 @@ int32_t lsm6ds3tr_c_act_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t *)&tap_cfg, 1); + if (ret != 0) { return ret; } + switch (tap_cfg.inact_en) { case LSM6DS3TR_C_PROPERTY_DISABLE: @@ -3552,6 +3641,9 @@ int32_t lsm6ds3tr_c_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + if (ret != 0) { return ret; } + *val = wake_up_dur.sleep_dur; return ret; @@ -3630,6 +3722,9 @@ int32_t lsm6ds3tr_c_tap_detection_on_z_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret != 0) { return ret; } + *val = tap_cfg.tap_z_en; return ret; @@ -3678,6 +3773,9 @@ int32_t lsm6ds3tr_c_tap_detection_on_y_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret != 0) { return ret; } + *val = tap_cfg.tap_y_en; return ret; @@ -3726,6 +3824,9 @@ int32_t lsm6ds3tr_c_tap_detection_on_x_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret != 0) { return ret; } + *val = tap_cfg.tap_x_en; return ret; @@ -3774,6 +3875,9 @@ int32_t lsm6ds3tr_c_tap_threshold_x_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + + if (ret != 0) { return ret; } + *val = tap_ths_6d.tap_ths; return ret; @@ -3830,6 +3934,9 @@ int32_t lsm6ds3tr_c_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t *)&int_dur2, 1); + + if (ret != 0) { return ret; } + *val = int_dur2.shock; return ret; @@ -3886,6 +3993,9 @@ int32_t lsm6ds3tr_c_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t *)&int_dur2, 1); + + if (ret != 0) { return ret; } + *val = int_dur2.quiet; return ret; @@ -3944,6 +4054,9 @@ int32_t lsm6ds3tr_c_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t *)&int_dur2, 1); + + if (ret != 0) { return ret; } + *val = int_dur2.dur; return ret; @@ -3995,6 +4108,8 @@ int32_t lsm6ds3tr_c_tap_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) { return ret; } + switch (wake_up_ths.single_double_tap) { case LSM6DS3TR_C_ONLY_SINGLE: @@ -4071,6 +4186,8 @@ int32_t lsm6ds3tr_c_6d_feed_data_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl8_xl.low_pass_on_6d) { case LSM6DS3TR_C_ODR_DIV_2_FEED: @@ -4133,6 +4250,8 @@ int32_t lsm6ds3tr_c_6d_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) { return ret; } + switch (tap_ths_6d.sixd_ths) { case LSM6DS3TR_C_DEG_80: @@ -4200,6 +4319,9 @@ int32_t lsm6ds3tr_c_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + + if (ret != 0) { return ret; } + *val = tap_ths_6d.d4d_en; return ret; @@ -4274,12 +4396,10 @@ int32_t lsm6ds3tr_c_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + ret += lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL, + (uint8_t *)&free_fall, 1); - if (ret == 0) - { - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL, - (uint8_t *)&free_fall, 1); - } + if (ret != 0) { return ret; } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -4330,6 +4450,8 @@ int32_t lsm6ds3tr_c_ff_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) { return ret; } + switch (free_fall.ff_ths) { case LSM6DS3TR_C_FF_TSH_156mg: @@ -4437,12 +4559,10 @@ int32_t lsm6ds3tr_c_fifo_watermark_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); - if (ret == 0) - { - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); - } + if (ret != 0) { return ret; } *val = ((uint16_t)fifo_ctrl2.fth << 8) + (uint16_t)fifo_ctrl1.fth; @@ -4468,11 +4588,11 @@ int32_t lsm6ds3tr_c_fifo_data_level_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + ret += lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); if (ret == 0) { - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); *val = ((uint16_t) fifo_status2.diff_fifo << 8) + (uint16_t) fifo_status1.diff_fifo; } @@ -4495,6 +4615,9 @@ int32_t lsm6ds3tr_c_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); + + if (ret != 0) { return ret; } + *val = fifo_status2.waterm; return ret; @@ -4517,14 +4640,13 @@ int32_t lsm6ds3tr_c_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS3, (uint8_t *)&fifo_status3, 1); + ret += lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS4, + (uint8_t *)&fifo_status4, 1); - if (ret == 0) - { - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS4, - (uint8_t *)&fifo_status4, 1); - *val = ((uint16_t)fifo_status4.fifo_pattern << 8) + - fifo_status3.fifo_pattern; - } + if (ret != 0) { return ret; } + + *val = ((uint16_t)fifo_status4.fifo_pattern << 8) + + fifo_status3.fifo_pattern; return ret; } @@ -4572,6 +4694,9 @@ int32_t lsm6ds3tr_c_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl2.fifo_temp_en; return ret; @@ -4637,12 +4762,11 @@ int32_t lsm6ds3tr_c_fifo_write_trigger_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + ret += lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t *)&master_config, 1); if (ret == 0) { - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - switch ((fifo_ctrl2.timer_pedo_fifo_drdy << 1) + fifo_ctrl2. timer_pedo_fifo_drdy) { @@ -4714,6 +4838,9 @@ int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_get( ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl2.timer_pedo_fifo_en; return ret; @@ -4765,6 +4892,8 @@ int32_t lsm6ds3tr_c_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl3.dec_fifo_xl) { case LSM6DS3TR_C_FIFO_XL_DISABLE: @@ -4853,6 +4982,8 @@ int32_t lsm6ds3tr_c_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl3.dec_fifo_gyro) { case LSM6DS3TR_C_FIFO_GY_DISABLE: @@ -4941,6 +5072,8 @@ int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl4.dec_ds3_fifo) { case LSM6DS3TR_C_FIFO_DS3_DISABLE: @@ -5029,6 +5162,8 @@ int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl4.dec_ds4_fifo) { case LSM6DS3TR_C_FIFO_DS4_DISABLE: @@ -5114,6 +5249,9 @@ int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl4.only_high_data; return ret; @@ -5164,6 +5302,9 @@ int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl4.stop_on_fth; return ret; @@ -5213,6 +5354,8 @@ int32_t lsm6ds3tr_c_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t *)&fifo_ctrl5, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl5.fifo_mode) { case LSM6DS3TR_C_BYPASS_MODE: @@ -5287,6 +5430,8 @@ int32_t lsm6ds3tr_c_fifo_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t *)&fifo_ctrl5, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl5.odr_fifo) { case LSM6DS3TR_C_FIFO_DISABLE: @@ -5398,6 +5543,8 @@ int32_t lsm6ds3tr_c_den_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.den_lh) { case LSM6DS3TR_C_DEN_ACT_LOW: @@ -5460,6 +5607,8 @@ int32_t lsm6ds3tr_c_den_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } + switch (ctrl6_c.den_mode) { case LSM6DS3TR_C_DEN_DISABLE: @@ -5546,12 +5695,11 @@ int32_t lsm6ds3tr_c_den_enable_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + ret += lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); if (ret == 0) { - ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, - (uint8_t *)&ctrl9_xl, 1); - switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g) { case LSM6DS3TR_C_STAMP_IN_GY_DATA: @@ -5618,6 +5766,9 @@ int32_t lsm6ds3tr_c_den_mark_axis_z_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_z; return ret; @@ -5666,6 +5817,9 @@ int32_t lsm6ds3tr_c_den_mark_axis_y_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_y; return ret; @@ -5714,6 +5868,9 @@ int32_t lsm6ds3tr_c_den_mark_axis_x_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_x; return ret; @@ -5774,6 +5931,9 @@ int32_t lsm6ds3tr_c_pedo_step_reset_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.pedo_rst_step; return ret; @@ -5826,6 +5986,9 @@ int32_t lsm6ds3tr_c_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.pedo_en; return ret; @@ -5858,13 +6021,11 @@ int32_t lsm6ds3tr_c_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN, (uint8_t *)&config_pedo_ths_min, 1); - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -5888,12 +6049,13 @@ int32_t lsm6ds3tr_c_pedo_threshold_get(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN, (uint8_t *)&config_pedo_ths_min, 1); + } - if (ret == 0) - { - *val = config_pedo_ths_min.ths_min; - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + + if (ret == 0) + { + *val = config_pedo_ths_min.ths_min; } return ret; @@ -5926,14 +6088,11 @@ int32_t lsm6ds3tr_c_pedo_full_scale_set(const stmdev_ctx_t *ctx, config_pedo_ths_min.pedo_fs = (uint8_t) val; ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN, (uint8_t *)&config_pedo_ths_min, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -5958,27 +6117,27 @@ int32_t lsm6ds3tr_c_pedo_full_scale_get(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN, (uint8_t *)&config_pedo_ths_min, 1); + } - if (ret == 0) - { - switch (config_pedo_ths_min.pedo_fs) - { - case LSM6DS3TR_C_PEDO_AT_2g: - *val = LSM6DS3TR_C_PEDO_AT_2g; - break; + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - case LSM6DS3TR_C_PEDO_AT_4g: - *val = LSM6DS3TR_C_PEDO_AT_4g; - break; + if (ret == 0) + { + switch (config_pedo_ths_min.pedo_fs) + { + case LSM6DS3TR_C_PEDO_AT_2g: + *val = LSM6DS3TR_C_PEDO_AT_2g; + break; - default: - *val = LSM6DS3TR_C_PEDO_FS_ND; - break; - } + case LSM6DS3TR_C_PEDO_AT_4g: + *val = LSM6DS3TR_C_PEDO_AT_4g; + break; - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + default: + *val = LSM6DS3TR_C_PEDO_FS_ND; + break; } - } + } return ret; } @@ -6009,14 +6168,11 @@ int32_t lsm6ds3tr_c_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, pedo_deb_reg.deb_step = val; ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG, (uint8_t *)&pedo_deb_reg, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6040,12 +6196,13 @@ int32_t lsm6ds3tr_c_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG, (uint8_t *)&pedo_deb_reg, 1); + } - if (ret == 0) - { - *val = pedo_deb_reg.deb_step; - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + + if (ret == 0) + { + *val = pedo_deb_reg.deb_step; } return ret; @@ -6078,14 +6235,11 @@ int32_t lsm6ds3tr_c_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) pedo_deb_reg.deb_time = val; ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG, (uint8_t *)&pedo_deb_reg, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6114,10 +6268,11 @@ int32_t lsm6ds3tr_c_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = pedo_deb_reg.deb_time; - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6139,13 +6294,10 @@ int32_t lsm6ds3tr_c_pedo_steps_period_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_STEP_COUNT_DELTA, buff, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6167,13 +6319,10 @@ int32_t lsm6ds3tr_c_pedo_steps_period_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STEP_COUNT_DELTA, buff, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6236,6 +6385,9 @@ int32_t lsm6ds3tr_c_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.sign_motion_en; return ret; @@ -6259,13 +6411,10 @@ int32_t lsm6ds3tr_c_motion_threshold_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SM_THS, buff, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6287,13 +6436,10 @@ int32_t lsm6ds3tr_c_motion_threshold_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SM_THS, buff, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6357,6 +6503,9 @@ int32_t lsm6ds3tr_c_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.tilt_en; return ret; @@ -6411,6 +6560,9 @@ int32_t lsm6ds3tr_c_wrist_tilt_sens_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.wrist_tilt_en; return ret; @@ -6435,13 +6587,10 @@ int32_t lsm6ds3tr_c_tilt_latency_set(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_LAT, buff, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6464,13 +6613,10 @@ int32_t lsm6ds3tr_c_tilt_latency_get(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_LAT, buff, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6494,13 +6640,10 @@ int32_t lsm6ds3tr_c_tilt_threshold_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_THS, buff, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6524,13 +6667,10 @@ int32_t lsm6ds3tr_c_tilt_threshold_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_THS, buff, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6553,13 +6693,10 @@ int32_t lsm6ds3tr_c_tilt_src_set(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK, (uint8_t *) val, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6582,13 +6719,10 @@ int32_t lsm6ds3tr_c_tilt_src_get(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK, (uint8_t *) val, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6646,6 +6780,9 @@ int32_t lsm6ds3tr_c_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl9_xl.soft_en; return ret; @@ -6710,6 +6847,9 @@ int32_t lsm6ds3tr_c_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + if (ret != 0) { return ret; } + *val = master_config.iron_en; return ret; @@ -6734,13 +6874,10 @@ int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MAG_SI_XX, buff, 9); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6763,19 +6900,16 @@ int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MAG_SI_XX, buff, 9); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } /** * @brief Offset for hard-iron compensation register (r/w). The value is - * expressed as a 16-bit word in two’s complement.[set] + * expressed as a 16-bit word in two's complement.[set] * * @param ctx Read / write interface definitions * @param buff Buffer that contains data to write @@ -6798,19 +6932,16 @@ int32_t lsm6ds3tr_c_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) buff[5] = (uint8_t)((uint16_t)val[2] / 256U); buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U)); ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MAG_OFFX_L, buff, 6); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } /** * @brief Offset for hard-iron compensation register(r/w). - * The value is expressed as a 16-bit word in two’s complement.[get] + * The value is expressed as a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -6836,10 +6967,11 @@ int32_t lsm6ds3tr_c_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) val[1] = (val[1] * 256) + (int16_t)buff[2]; val[2] = (int16_t)buff[5]; val[2] = (val[2] * 256) + (int16_t)buff[4]; - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -6927,6 +7059,9 @@ int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME, (uint8_t *)&sensor_sync_time_frame, 1); + + if (ret != 0) { return ret; } + *val = sensor_sync_time_frame.tph; return ret; @@ -6976,6 +7111,8 @@ int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO, (uint8_t *)&sensor_sync_res_ratio, 1); + if (ret != 0) { return ret; } + switch (sensor_sync_res_ratio.rr) { case LSM6DS3TR_C_RES_RATIO_2_11: @@ -7043,6 +7180,9 @@ int32_t lsm6ds3tr_c_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + if (ret != 0) { return ret; } + *val = master_config.master_on; return ret; @@ -7091,6 +7231,9 @@ int32_t lsm6ds3tr_c_sh_pass_through_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + if (ret != 0) { return ret; } + *val = master_config.pass_through_mode; return ret; @@ -7140,6 +7283,8 @@ int32_t lsm6ds3tr_c_sh_pin_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) { return ret; } + switch (master_config.pull_up_en) { case LSM6DS3TR_C_EXT_PULL_UP: @@ -7202,6 +7347,8 @@ int32_t lsm6ds3tr_c_sh_syncro_mode_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) { return ret; } + switch (master_config.start_config) { case LSM6DS3TR_C_XL_GY_DRDY: @@ -7263,6 +7410,9 @@ int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + if (ret != 0) { return ret; } + *val = master_config.drdy_on_int1; return ret; @@ -7338,6 +7488,9 @@ int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CMD_CODE, (uint8_t *)&master_cmd_code, 1); + + if (ret != 0) { return ret; } + *val = master_cmd_code.master_cmd_code; return ret; @@ -7388,6 +7541,9 @@ int32_t lsm6ds3tr_c_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE, (uint8_t *)&sens_sync_spi_error_code, 1); + + if (ret != 0) { return ret; } + *val = sens_sync_spi_error_code.error_code; return ret; @@ -7419,14 +7575,11 @@ int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, slave0_config.aux_sens_on = (uint8_t) val; ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -7450,33 +7603,33 @@ int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); + } - if (ret == 0) - { - switch (slave0_config.aux_sens_on) - { - case LSM6DS3TR_C_SLV_0: - *val = LSM6DS3TR_C_SLV_0; - break; + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - case LSM6DS3TR_C_SLV_0_1: - *val = LSM6DS3TR_C_SLV_0_1; - break; + if (ret == 0) + { + switch (slave0_config.aux_sens_on) + { + case LSM6DS3TR_C_SLV_0: + *val = LSM6DS3TR_C_SLV_0; + break; - case LSM6DS3TR_C_SLV_0_1_2: - *val = LSM6DS3TR_C_SLV_0_1_2; - break; + case LSM6DS3TR_C_SLV_0_1: + *val = LSM6DS3TR_C_SLV_0_1; + break; - case LSM6DS3TR_C_SLV_0_1_2_3: - *val = LSM6DS3TR_C_SLV_0_1_2_3; - break; + case LSM6DS3TR_C_SLV_0_1_2: + *val = LSM6DS3TR_C_SLV_0_1_2; + break; - default: - *val = LSM6DS3TR_C_SLV_EN_ND; - break; - } + case LSM6DS3TR_C_SLV_0_1_2_3: + *val = LSM6DS3TR_C_SLV_0_1_2_3; + break; - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + default: + *val = LSM6DS3TR_C_SLV_EN_ND; + break; } } @@ -7519,15 +7672,12 @@ int32_t lsm6ds3tr_c_sh_cfg_write(const stmdev_ctx_t *ctx, ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_DATAWRITE_SRC_MODE_SUB_SLV0, &(val->slv0_data), 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -7573,16 +7723,13 @@ int32_t lsm6ds3tr_c_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -7628,16 +7775,13 @@ int32_t lsm6ds3tr_c_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -7683,16 +7827,13 @@ int32_t lsm6ds3tr_c_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, slave2_config.slave2_numop = val->slv_len; ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG, (uint8_t *)&slave2_config, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -7738,16 +7879,13 @@ int32_t lsm6ds3tr_c_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, slave3_config.slave3_numop = val->slv_len; ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG, (uint8_t *)&slave3_config, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -7778,14 +7916,11 @@ int32_t lsm6ds3tr_c_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, slave0_config.slave0_rate = (uint8_t) val; ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -7810,33 +7945,33 @@ int32_t lsm6ds3tr_c_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); + } - if (ret == 0) - { - switch (slave0_config.slave0_rate) - { - case LSM6DS3TR_C_SL0_NO_DEC: - *val = LSM6DS3TR_C_SL0_NO_DEC; - break; + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - case LSM6DS3TR_C_SL0_DEC_2: - *val = LSM6DS3TR_C_SL0_DEC_2; - break; + if (ret == 0) + { + switch (slave0_config.slave0_rate) + { + case LSM6DS3TR_C_SL0_NO_DEC: + *val = LSM6DS3TR_C_SL0_NO_DEC; + break; - case LSM6DS3TR_C_SL0_DEC_4: - *val = LSM6DS3TR_C_SL0_DEC_4; - break; + case LSM6DS3TR_C_SL0_DEC_2: + *val = LSM6DS3TR_C_SL0_DEC_2; + break; - case LSM6DS3TR_C_SL0_DEC_8: - *val = LSM6DS3TR_C_SL0_DEC_8; - break; + case LSM6DS3TR_C_SL0_DEC_4: + *val = LSM6DS3TR_C_SL0_DEC_4; + break; - default: - *val = LSM6DS3TR_C_SL0_DEC_ND; - break; - } + case LSM6DS3TR_C_SL0_DEC_8: + *val = LSM6DS3TR_C_SL0_DEC_8; + break; - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + default: + *val = LSM6DS3TR_C_SL0_DEC_ND; + break; } } @@ -7872,14 +8007,11 @@ int32_t lsm6ds3tr_c_sh_write_mode_set(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -7906,25 +8038,25 @@ int32_t lsm6ds3tr_c_sh_write_mode_get(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); + } - if (ret == 0) - { - switch (slave1_config.write_once) - { - case LSM6DS3TR_C_EACH_SH_CYCLE: - *val = LSM6DS3TR_C_EACH_SH_CYCLE; - break; + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - case LSM6DS3TR_C_ONLY_FIRST_CYCLE: - *val = LSM6DS3TR_C_ONLY_FIRST_CYCLE; - break; + if (ret == 0) + { + switch (slave1_config.write_once) + { + case LSM6DS3TR_C_EACH_SH_CYCLE: + *val = LSM6DS3TR_C_EACH_SH_CYCLE; + break; - default: - *val = LSM6DS3TR_C_SH_WR_MODE_ND; - break; - } + case LSM6DS3TR_C_ONLY_FIRST_CYCLE: + *val = LSM6DS3TR_C_ONLY_FIRST_CYCLE; + break; - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + default: + *val = LSM6DS3TR_C_SH_WR_MODE_ND; + break; } } @@ -7958,14 +8090,11 @@ int32_t lsm6ds3tr_c_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, slave1_config.slave1_rate = (uint8_t) val; ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -7989,33 +8118,33 @@ int32_t lsm6ds3tr_c_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); + } - if (ret == 0) - { - switch (slave1_config.slave1_rate) - { - case LSM6DS3TR_C_SL1_NO_DEC: - *val = LSM6DS3TR_C_SL1_NO_DEC; - break; + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - case LSM6DS3TR_C_SL1_DEC_2: - *val = LSM6DS3TR_C_SL1_DEC_2; - break; + if (ret == 0) + { + switch (slave1_config.slave1_rate) + { + case LSM6DS3TR_C_SL1_NO_DEC: + *val = LSM6DS3TR_C_SL1_NO_DEC; + break; - case LSM6DS3TR_C_SL1_DEC_4: - *val = LSM6DS3TR_C_SL1_DEC_4; - break; + case LSM6DS3TR_C_SL1_DEC_2: + *val = LSM6DS3TR_C_SL1_DEC_2; + break; - case LSM6DS3TR_C_SL1_DEC_8: - *val = LSM6DS3TR_C_SL1_DEC_8; - break; + case LSM6DS3TR_C_SL1_DEC_4: + *val = LSM6DS3TR_C_SL1_DEC_4; + break; - default: - *val = LSM6DS3TR_C_SL1_DEC_ND; - break; - } + case LSM6DS3TR_C_SL1_DEC_8: + *val = LSM6DS3TR_C_SL1_DEC_8; + break; - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + default: + *val = LSM6DS3TR_C_SL1_DEC_ND; + break; } } @@ -8049,14 +8178,11 @@ int32_t lsm6ds3tr_c_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, slave2_config.slave2_rate = (uint8_t) val; ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG, (uint8_t *)&slave2_config, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -8081,33 +8207,33 @@ int32_t lsm6ds3tr_c_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG, (uint8_t *)&slave2_config, 1); + } - if (ret == 0) - { - switch (slave2_config.slave2_rate) - { - case LSM6DS3TR_C_SL2_NO_DEC: - *val = LSM6DS3TR_C_SL2_NO_DEC; - break; + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - case LSM6DS3TR_C_SL2_DEC_2: - *val = LSM6DS3TR_C_SL2_DEC_2; - break; + if (ret == 0) + { + switch (slave2_config.slave2_rate) + { + case LSM6DS3TR_C_SL2_NO_DEC: + *val = LSM6DS3TR_C_SL2_NO_DEC; + break; - case LSM6DS3TR_C_SL2_DEC_4: - *val = LSM6DS3TR_C_SL2_DEC_4; - break; + case LSM6DS3TR_C_SL2_DEC_2: + *val = LSM6DS3TR_C_SL2_DEC_2; + break; - case LSM6DS3TR_C_SL2_DEC_8: - *val = LSM6DS3TR_C_SL2_DEC_8; - break; + case LSM6DS3TR_C_SL2_DEC_4: + *val = LSM6DS3TR_C_SL2_DEC_4; + break; - default: - *val = LSM6DS3TR_C_SL2_DEC_ND; - break; - } + case LSM6DS3TR_C_SL2_DEC_8: + *val = LSM6DS3TR_C_SL2_DEC_8; + break; - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + default: + *val = LSM6DS3TR_C_SL2_DEC_ND; + break; } } @@ -8141,14 +8267,11 @@ int32_t lsm6ds3tr_c_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG, (uint8_t *)&slave3_config, 1); - - if (ret == 0) - { - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - } } } + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + return ret; } @@ -8173,33 +8296,33 @@ int32_t lsm6ds3tr_c_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, { ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG, (uint8_t *)&slave3_config, 1); + } - if (ret == 0) - { - switch (slave3_config.slave3_rate) - { - case LSM6DS3TR_C_SL3_NO_DEC: - *val = LSM6DS3TR_C_SL3_NO_DEC; - break; + ret += lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); - case LSM6DS3TR_C_SL3_DEC_2: - *val = LSM6DS3TR_C_SL3_DEC_2; - break; + if (ret == 0) + { + switch (slave3_config.slave3_rate) + { + case LSM6DS3TR_C_SL3_NO_DEC: + *val = LSM6DS3TR_C_SL3_NO_DEC; + break; - case LSM6DS3TR_C_SL3_DEC_4: - *val = LSM6DS3TR_C_SL3_DEC_4; - break; + case LSM6DS3TR_C_SL3_DEC_2: + *val = LSM6DS3TR_C_SL3_DEC_2; + break; - case LSM6DS3TR_C_SL3_DEC_8: - *val = LSM6DS3TR_C_SL3_DEC_8; - break; + case LSM6DS3TR_C_SL3_DEC_4: + *val = LSM6DS3TR_C_SL3_DEC_4; + break; - default: - *val = LSM6DS3TR_C_SL3_DEC_ND; - break; - } + case LSM6DS3TR_C_SL3_DEC_8: + *val = LSM6DS3TR_C_SL3_DEC_8; + break; - ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + default: + *val = LSM6DS3TR_C_SL3_DEC_ND; + break; } } @@ -8215,5 +8338,3 @@ int32_t lsm6ds3tr_c_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h index 3411c79..9b5080a 100644 --- a/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h +++ b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -2800,5 +2802,3 @@ int32_t lsm6ds3tr_c_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, #endif #endif /* LSM6DS3TR_C_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c index 8192aff..733a4e7 100644 --- a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c +++ b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -205,6 +204,8 @@ int32_t lsm6dsl_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl1_xl.fs_xl) { case LSM6DSL_2g: @@ -272,6 +273,8 @@ int32_t lsm6dsl_xl_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl1_xl.odr_xl) { case LSM6DSL_XL_ODR_OFF: @@ -371,6 +374,8 @@ int32_t lsm6dsl_gy_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) { return ret; } + switch (ctrl2_g.fs_g) { case LSM6DSL_250dps: @@ -442,6 +447,8 @@ int32_t lsm6dsl_gy_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) { return ret; } + switch (ctrl2_g.odr_g) { case LSM6DSL_GY_ODR_OFF: @@ -534,6 +541,9 @@ int32_t lsm6dsl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_c.bdu; return ret; @@ -582,6 +592,8 @@ int32_t lsm6dsl_xl_offset_weight_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } + switch (ctrl6_c.usr_off_w) { case LSM6DSL_LSb_1mg: @@ -641,6 +653,8 @@ int32_t lsm6dsl_xl_power_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } + switch (ctrl6_c.xl_hm_mode) { case LSM6DSL_XL_HIGH_PERFORMANCE: @@ -704,6 +718,8 @@ int32_t lsm6dsl_rounding_on_status_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) { return ret; } + switch (ctrl7_g.rounding_status) { case LSM6DSL_STAT_RND_DISABLE: @@ -763,6 +779,8 @@ int32_t lsm6dsl_gy_power_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) { return ret; } + switch (ctrl7_g.g_hm_mode) { case LSM6DSL_GY_HIGH_PERFORMANCE: @@ -837,17 +855,14 @@ int32_t lsm6dsl_all_sources_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B); - } - if (ret == 0) - { - ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK, - (uint8_t *) & (val->a_wrist_tilt_mask), 1); - } + if (ret == 0) + { + ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK, + (uint8_t *) & (val->a_wrist_tilt_mask), 1); + } - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); } return ret; @@ -886,6 +901,9 @@ int32_t lsm6dsl_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.xlda; return ret; @@ -907,6 +925,9 @@ int32_t lsm6dsl_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.gda; return ret; @@ -928,13 +949,16 @@ int32_t lsm6dsl_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.tda; return ret; } /** - * @brief Accelerometer axis user offset correction expressed in two’s + * @brief Accelerometer axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C. * The value must be in the range [-127 127].[set] * @@ -953,7 +977,7 @@ int32_t lsm6dsl_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer axis user offset correction xpressed in two’s + * @brief Accelerometer axis user offset correction xpressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C. * The value must be in the range [-127 127].[get] * @@ -1029,6 +1053,9 @@ int32_t lsm6dsl_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.timer_en; return ret; @@ -1088,6 +1115,8 @@ int32_t lsm6dsl_timestamp_res_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) { return ret; } + switch (wake_up_dur.timer_hr) { case LSM6DSL_LSB_6ms4: @@ -1161,6 +1190,8 @@ int32_t lsm6dsl_rounding_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.rounding) { case LSM6DSL_ROUND_DISABLE: @@ -1205,7 +1236,7 @@ int32_t lsm6dsl_rounding_mode_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers together - * express a 16-bit word in two’s complement.[get] + * express a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -1218,6 +1249,9 @@ int32_t lsm6dsl_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUT_TEMP_L, buff, 2); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1226,7 +1260,7 @@ int32_t lsm6dsl_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Angular rate sensor. The value is expressed as a 16-bit word in - * two’s complement.[get] + * two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -1239,6 +1273,9 @@ int32_t lsm6dsl_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUTX_L_G, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1251,7 +1288,7 @@ int32_t lsm6dsl_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed - * as a 16-bit word in two’s complement.[get] + * as a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -1264,6 +1301,9 @@ int32_t lsm6dsl_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUTX_L_XL, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1289,6 +1329,9 @@ int32_t lsm6dsl_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUT_MAG_RAW_X_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1376,6 +1419,8 @@ int32_t lsm6dsl_mem_bank_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) { return ret; } + switch (func_cfg_access.func_cfg_en) { case LSM6DSL_USER_BANK: @@ -1438,6 +1483,8 @@ int32_t lsm6dsl_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G, (uint8_t *)&drdy_pulse_cfg_g, 1); + if (ret != 0) { return ret; } + switch (drdy_pulse_cfg_g.drdy_pulsed) { case LSM6DSL_DRDY_LATCHED: @@ -1511,6 +1558,9 @@ int32_t lsm6dsl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_c.sw_reset; return ret; @@ -1555,6 +1605,8 @@ int32_t lsm6dsl_data_format_get(const stmdev_ctx_t *ctx, lsm6dsl_ble_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + switch (ctrl3_c.ble) { case LSM6DSL_LSB_AT_LOW_ADD: @@ -1613,6 +1665,9 @@ int32_t lsm6dsl_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_c.if_inc; return ret; @@ -1656,6 +1711,9 @@ int32_t lsm6dsl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_c.boot; return ret; @@ -1702,6 +1760,8 @@ int32_t lsm6dsl_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.st_xl) { case LSM6DSL_XL_ST_DISABLE: @@ -1765,6 +1825,8 @@ int32_t lsm6dsl_gy_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.st_g) { case LSM6DSL_GY_ST_DISABLE: @@ -1842,6 +1904,9 @@ int32_t lsm6dsl_filter_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl4_c.drdy_mask; return ret; @@ -1890,6 +1955,8 @@ int32_t lsm6dsl_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + if (ret != 0) { return ret; } + switch (tap_cfg.slope_fds) { case LSM6DSL_USE_SLOPE: @@ -1964,6 +2031,8 @@ int32_t lsm6dsl_xl_filter_analog_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl1_xl.bw0_xl) { case LSM6DSL_XL_ANA_BW_1k5Hz: @@ -2064,19 +2133,22 @@ int32_t lsm6dsl_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, { ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - switch (ctrl1_xl.lpf1_bw_sel) + if (ret == 0) { - case LSM6DSL_XL_LP1_ODR_DIV_2: - *val = LSM6DSL_XL_LP1_ODR_DIV_2; - break; + switch (ctrl1_xl.lpf1_bw_sel) + { + case LSM6DSL_XL_LP1_ODR_DIV_2: + *val = LSM6DSL_XL_LP1_ODR_DIV_2; + break; - case LSM6DSL_XL_LP1_ODR_DIV_4: - *val = LSM6DSL_XL_LP1_ODR_DIV_4; - break; + case LSM6DSL_XL_LP1_ODR_DIV_4: + *val = LSM6DSL_XL_LP1_ODR_DIV_4; + break; - default: - *val = LSM6DSL_XL_LP1_NA; - break; + default: + *val = LSM6DSL_XL_LP1_NA; + break; + } } } } @@ -2220,6 +2292,9 @@ int32_t lsm6dsl_xl_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl8_xl.hp_ref_mode; return ret; @@ -2268,6 +2343,8 @@ int32_t lsm6dsl_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { return ret; } + if (ctrl8_xl.hp_slope_xl_en == 0x00U) { *val = LSM6DSL_XL_HP_NA; @@ -2381,70 +2458,65 @@ int32_t lsm6dsl_gy_band_pass_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + ret += lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + ret += lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); if (ret == 0) { - ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - - if (ret == 0) + switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) + + (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype) { - ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - - switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) + - (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype) - { - case LSM6DSL_HP_16mHz_LP2: - *val = LSM6DSL_HP_16mHz_LP2; - break; + case LSM6DSL_HP_16mHz_LP2: + *val = LSM6DSL_HP_16mHz_LP2; + break; - case LSM6DSL_HP_65mHz_LP2: - *val = LSM6DSL_HP_65mHz_LP2; - break; + case LSM6DSL_HP_65mHz_LP2: + *val = LSM6DSL_HP_65mHz_LP2; + break; - case LSM6DSL_HP_260mHz_LP2: - *val = LSM6DSL_HP_260mHz_LP2; - break; + case LSM6DSL_HP_260mHz_LP2: + *val = LSM6DSL_HP_260mHz_LP2; + break; - case LSM6DSL_HP_1Hz04_LP2: - *val = LSM6DSL_HP_1Hz04_LP2; - break; + case LSM6DSL_HP_1Hz04_LP2: + *val = LSM6DSL_HP_1Hz04_LP2; + break; - case LSM6DSL_HP_DISABLE_LP1_LIGHT: - *val = LSM6DSL_HP_DISABLE_LP1_LIGHT; - break; + case LSM6DSL_HP_DISABLE_LP1_LIGHT: + *val = LSM6DSL_HP_DISABLE_LP1_LIGHT; + break; - case LSM6DSL_HP_DISABLE_LP1_NORMAL: - *val = LSM6DSL_HP_DISABLE_LP1_NORMAL; - break; + case LSM6DSL_HP_DISABLE_LP1_NORMAL: + *val = LSM6DSL_HP_DISABLE_LP1_NORMAL; + break; - case LSM6DSL_HP_DISABLE_LP_STRONG: - *val = LSM6DSL_HP_DISABLE_LP_STRONG; - break; + case LSM6DSL_HP_DISABLE_LP1_STRONG: + *val = LSM6DSL_HP_DISABLE_LP1_STRONG; + break; - case LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE: - *val = LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE; - break; + case LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE: + *val = LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE; + break; - case LSM6DSL_HP_16mHz_LP1_LIGHT: - *val = LSM6DSL_HP_16mHz_LP1_LIGHT; - break; + case LSM6DSL_HP_16mHz_LP1_LIGHT: + *val = LSM6DSL_HP_16mHz_LP1_LIGHT; + break; - case LSM6DSL_HP_65mHz_LP1_NORMAL: - *val = LSM6DSL_HP_65mHz_LP1_NORMAL; - break; + case LSM6DSL_HP_65mHz_LP1_NORMAL: + *val = LSM6DSL_HP_65mHz_LP1_NORMAL; + break; - case LSM6DSL_HP_260mHz_LP1_STRONG: - *val = LSM6DSL_HP_260mHz_LP1_STRONG; - break; + case LSM6DSL_HP_260mHz_LP1_STRONG: + *val = LSM6DSL_HP_260mHz_LP1_STRONG; + break; - case LSM6DSL_HP_1Hz04_LP1_AGGRESSIVE: - *val = LSM6DSL_HP_1Hz04_LP1_AGGRESSIVE; - break; + case LSM6DSL_HP_1Hz04_LP1_AGGRESSIVE: + *val = LSM6DSL_HP_1Hz04_LP1_AGGRESSIVE; + break; - default: - *val = LSM6DSL_HP_GY_BAND_NA; - break; - } + default: + *val = LSM6DSL_HP_GY_BAND_NA; + break; } } @@ -2503,6 +2575,8 @@ int32_t lsm6dsl_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_sim_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + switch (ctrl3_c.sim) { case LSM6DSL_SPI_4_WIRE: @@ -2562,6 +2636,8 @@ int32_t lsm6dsl_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { return ret; } + switch (ctrl4_c.i2c_disable) { case LSM6DSL_I2C_ENABLE: @@ -2728,6 +2804,10 @@ int32_t lsm6dsl_pin_int1_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + ret += lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1); + ret += lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + ret += lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); if (ret == 0) { @@ -2739,28 +2819,19 @@ int32_t lsm6dsl_pin_int1_route_get(const stmdev_ctx_t *ctx, val->int1_full_flag = int1_ctrl.int1_full_flag; val->int1_sign_mot = int1_ctrl.int1_sign_mot; val->int1_step_detector = int1_ctrl.int1_step_detector ; - ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret == 0) - { - val->int1_timer = md1_cfg.int1_timer; - val->int1_tilt = md1_cfg.int1_tilt; - val->int1_6d = md1_cfg.int1_6d; - val->int1_double_tap = md1_cfg.int1_double_tap; - val->int1_ff = md1_cfg.int1_ff; - val->int1_wu = md1_cfg.int1_wu; - val->int1_single_tap = md1_cfg.int1_single_tap; - val->int1_inact_state = md1_cfg.int1_inact_state; - ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + val->int1_timer = md1_cfg.int1_timer; + val->int1_tilt = md1_cfg.int1_tilt; + val->int1_6d = md1_cfg.int1_6d; + val->int1_double_tap = md1_cfg.int1_double_tap; + val->int1_ff = md1_cfg.int1_ff; + val->int1_wu = md1_cfg.int1_wu; + val->int1_single_tap = md1_cfg.int1_single_tap; + val->int1_inact_state = md1_cfg.int1_inact_state; - if (ret == 0) - { - val->den_drdy_int1 = ctrl4_c.den_drdy_int1; - ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - val->den_drdy_int1 = master_config.drdy_on_int1; - } - } + val->den_drdy_int1 = ctrl4_c.den_drdy_int1; + + val->den_drdy_int1 = master_config.drdy_on_int1; } return ret; @@ -2886,6 +2957,9 @@ int32_t lsm6dsl_pin_int2_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + ret += lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1); + ret += lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G, + (uint8_t *)&drdy_pulse_cfg_g, 1); if (ret == 0) { @@ -2897,22 +2971,17 @@ int32_t lsm6dsl_pin_int2_route_get(const stmdev_ctx_t *ctx, val->int2_full_flag = int2_ctrl.int2_full_flag; val->int2_step_count_ov = int2_ctrl.int2_step_count_ov; val->int2_step_delta = int2_ctrl.int2_step_delta; - ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret == 0) - { - val->int2_iron = md2_cfg.int2_iron; - val->int2_tilt = md2_cfg.int2_tilt; - val->int2_6d = md2_cfg.int2_6d; - val->int2_double_tap = md2_cfg.int2_double_tap; - val->int2_ff = md2_cfg.int2_ff; - val->int2_wu = md2_cfg.int2_wu; - val->int2_single_tap = md2_cfg.int2_single_tap; - val->int2_inact_state = md2_cfg.int2_inact_state; - ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G, - (uint8_t *)&drdy_pulse_cfg_g, 1); - val->int2_wrist_tilt = drdy_pulse_cfg_g.int2_wrist_tilt; - } + val->int2_iron = md2_cfg.int2_iron; + val->int2_tilt = md2_cfg.int2_tilt; + val->int2_6d = md2_cfg.int2_6d; + val->int2_double_tap = md2_cfg.int2_double_tap; + val->int2_ff = md2_cfg.int2_ff; + val->int2_wu = md2_cfg.int2_wu; + val->int2_single_tap = md2_cfg.int2_single_tap; + val->int2_inact_state = md2_cfg.int2_inact_state; + + val->int2_wrist_tilt = drdy_pulse_cfg_g.int2_wrist_tilt; } return ret; @@ -2957,6 +3026,8 @@ int32_t lsm6dsl_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_pp_od_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + switch (ctrl3_c.pp_od) { case LSM6DSL_PUSH_PULL: @@ -3016,6 +3087,8 @@ int32_t lsm6dsl_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + switch (ctrl3_c.h_lactive) { case LSM6DSL_ACTIVE_HIGH: @@ -3072,6 +3145,9 @@ int32_t lsm6dsl_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl4_c.int2_on_int1; return ret; @@ -3118,6 +3194,8 @@ int32_t lsm6dsl_int_notification_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + if (ret != 0) { return ret; } + switch (tap_cfg.lir) { case LSM6DSL_INT_PULSED: @@ -3190,6 +3268,9 @@ int32_t lsm6dsl_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { return ret; } + *val = wake_up_ths.wk_ths; return ret; @@ -3236,6 +3317,9 @@ int32_t lsm6dsl_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + if (ret != 0) { return ret; } + *val = wake_up_dur.wake_dur; return ret; @@ -3292,6 +3376,9 @@ int32_t lsm6dsl_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl4_c.sleep; return ret; @@ -3338,6 +3425,8 @@ int32_t lsm6dsl_act_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + if (ret != 0) { return ret; } + switch (tap_cfg.inact_en) { case LSM6DSL_PROPERTY_DISABLE: @@ -3405,6 +3494,9 @@ int32_t lsm6dsl_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + if (ret != 0) { return ret; } + *val = wake_up_dur.sleep_dur; return ret; @@ -3478,6 +3570,9 @@ int32_t lsm6dsl_tap_detection_on_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret != 0) { return ret; } + *val = tap_cfg.tap_z_en; return ret; @@ -3522,6 +3617,9 @@ int32_t lsm6dsl_tap_detection_on_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret != 0) { return ret; } + *val = tap_cfg.tap_y_en; return ret; @@ -3566,6 +3664,9 @@ int32_t lsm6dsl_tap_detection_on_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret != 0) { return ret; } + *val = tap_cfg.tap_x_en; return ret; @@ -3612,6 +3713,9 @@ int32_t lsm6dsl_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + + if (ret != 0) { return ret; } + *val = tap_ths_6d.tap_ths; return ret; @@ -3665,6 +3769,9 @@ int32_t lsm6dsl_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1); + + if (ret != 0) { return ret; } + *val = int_dur2.shock; return ret; @@ -3718,6 +3825,9 @@ int32_t lsm6dsl_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1); + + if (ret != 0) { return ret; } + *val = int_dur2.quiet; return ret; @@ -3773,6 +3883,9 @@ int32_t lsm6dsl_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1); + + if (ret != 0) { return ret; } + *val = int_dur2.dur; return ret; @@ -3824,6 +3937,8 @@ int32_t lsm6dsl_tap_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) { return ret; } + switch (wake_up_ths.single_double_tap) { case LSM6DSL_ONLY_SINGLE: @@ -3897,6 +4012,8 @@ int32_t lsm6dsl_6d_feed_data_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl8_xl.low_pass_on_6d) { case LSM6DSL_ODR_DIV_2_FEED: @@ -3959,6 +4076,8 @@ int32_t lsm6dsl_6d_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) { return ret; } + switch (tap_ths_6d.sixd_ths) { case LSM6DSL_DEG_80: @@ -4026,6 +4145,9 @@ int32_t lsm6dsl_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + + if (ret != 0) { return ret; } + *val = tap_ths_6d.d4d_en; return ret; @@ -4098,11 +4220,9 @@ int32_t lsm6dsl_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + ret += lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1); - if (ret == 0) - { - ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1); - } + if (ret != 0) { return ret; } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -4150,6 +4270,8 @@ int32_t lsm6dsl_ff_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) { return ret; } + switch (free_fall.ff_ths) { case LSM6DSL_FF_TSH_156mg: @@ -4255,12 +4377,8 @@ int32_t lsm6dsl_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); - - if (ret == 0) - { - ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); - } + ret += lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); *val = ((uint16_t)fifo_ctrl2.fth << 8) + (uint16_t)fifo_ctrl1.fth; @@ -4285,11 +4403,11 @@ int32_t lsm6dsl_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + ret += lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); if (ret == 0) { - ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); *val = ((uint16_t) fifo_status2.diff_fifo << 8) + (uint16_t) fifo_status1.diff_fifo; } @@ -4312,6 +4430,9 @@ int32_t lsm6dsl_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); + + if (ret != 0) { return ret; } + *val = fifo_status2.waterm; return ret; @@ -4334,11 +4455,11 @@ int32_t lsm6dsl_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS3, (uint8_t *)&fifo_status3, 1); + ret += lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS4, + (uint8_t *)&fifo_status4, 1); if (ret == 0) { - ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS4, - (uint8_t *)&fifo_status4, 1); *val = ((uint16_t)fifo_status4.fifo_pattern << 8) + fifo_status3.fifo_pattern; } @@ -4387,6 +4508,9 @@ int32_t lsm6dsl_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl2.fifo_temp_en; return ret; @@ -4452,12 +4576,11 @@ int32_t lsm6dsl_fifo_write_trigger_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + ret += lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, + (uint8_t *)&master_config, 1); if (ret == 0) { - ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - switch ((fifo_ctrl2.timer_pedo_fifo_drdy << 1) + fifo_ctrl2. timer_pedo_fifo_drdy) { @@ -4527,6 +4650,9 @@ int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl2.timer_pedo_fifo_en; return ret; @@ -4578,6 +4704,8 @@ int32_t lsm6dsl_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl3.dec_fifo_xl) { case LSM6DSL_FIFO_XL_DISABLE: @@ -4666,6 +4794,8 @@ int32_t lsm6dsl_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl3.dec_fifo_gyro) { case LSM6DSL_FIFO_GY_DISABLE: @@ -4754,6 +4884,8 @@ int32_t lsm6dsl_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl4.dec_ds3_fifo) { case LSM6DSL_FIFO_DS3_DISABLE: @@ -4842,6 +4974,8 @@ int32_t lsm6dsl_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl4.dec_ds4_fifo) { case LSM6DSL_FIFO_DS4_DISABLE: @@ -4927,6 +5061,9 @@ int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl4.only_high_data; return ret; @@ -4975,6 +5112,9 @@ int32_t lsm6dsl_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl4.stop_on_fth; return ret; @@ -5024,6 +5164,8 @@ int32_t lsm6dsl_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5, (uint8_t *)&fifo_ctrl5, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl5.fifo_mode) { case LSM6DSL_BYPASS_MODE: @@ -5098,6 +5240,8 @@ int32_t lsm6dsl_fifo_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5, (uint8_t *)&fifo_ctrl5, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl5.odr_fifo) { case LSM6DSL_FIFO_DISABLE: @@ -5206,6 +5350,8 @@ int32_t lsm6dsl_den_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.den_lh) { case LSM6DSL_DEN_ACT_LOW: @@ -5265,6 +5411,8 @@ int32_t lsm6dsl_den_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } + switch (ctrl6_c.den_mode) { case LSM6DSL_DEN_DISABLE: @@ -5346,11 +5494,10 @@ int32_t lsm6dsl_den_enable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + ret += lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); if (ret == 0) { - ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g) { case LSM6DSL_STAMP_IN_GY_DATA: @@ -5412,6 +5559,9 @@ int32_t lsm6dsl_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_z; return ret; @@ -5455,6 +5605,9 @@ int32_t lsm6dsl_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_y; return ret; @@ -5498,6 +5651,9 @@ int32_t lsm6dsl_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_x; return ret; @@ -5553,6 +5709,9 @@ int32_t lsm6dsl_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.pedo_rst_step; return ret; @@ -5602,6 +5761,9 @@ int32_t lsm6dsl_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.pedo_en; return ret; @@ -5633,14 +5795,11 @@ int32_t lsm6dsl_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) config_pedo_ths_min.ths_min = val; ret = lsm6dsl_write_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN, (uint8_t *)&config_pedo_ths_min, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -5663,12 +5822,13 @@ int32_t lsm6dsl_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN, (uint8_t *)&config_pedo_ths_min, 1); + } - if (ret == 0) - { - *val = config_pedo_ths_min.ths_min; - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + + if (ret == 0) + { + *val = config_pedo_ths_min.ths_min; } return ret; @@ -5701,14 +5861,11 @@ int32_t lsm6dsl_pedo_full_scale_set(const stmdev_ctx_t *ctx, config_pedo_ths_min.pedo_fs = (uint8_t) val; ret = lsm6dsl_write_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN, (uint8_t *)&config_pedo_ths_min, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -5733,25 +5890,25 @@ int32_t lsm6dsl_pedo_full_scale_get(const stmdev_ctx_t *ctx, { ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN, (uint8_t *)&config_pedo_ths_min, 1); + } - if (ret == 0) - { - switch (config_pedo_ths_min.pedo_fs) - { - case LSM6DSL_PEDO_AT_2g: - *val = LSM6DSL_PEDO_AT_2g; - break; + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - case LSM6DSL_PEDO_AT_4g: - *val = LSM6DSL_PEDO_AT_4g; - break; + if (ret == 0) + { + switch (config_pedo_ths_min.pedo_fs) + { + case LSM6DSL_PEDO_AT_2g: + *val = LSM6DSL_PEDO_AT_2g; + break; - default: - *val = LSM6DSL_PEDO_FS_ND; - break; - } + case LSM6DSL_PEDO_AT_4g: + *val = LSM6DSL_PEDO_AT_4g; + break; - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + default: + *val = LSM6DSL_PEDO_FS_ND; + break; } } @@ -5784,14 +5941,11 @@ int32_t lsm6dsl_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, pedo_deb_reg.deb_step = val; ret = lsm6dsl_write_reg(ctx, LSM6DSL_PEDO_DEB_REG, (uint8_t *)&pedo_deb_reg, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -5815,12 +5969,13 @@ int32_t lsm6dsl_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, { ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG, (uint8_t *)&pedo_deb_reg, 1); + } - if (ret == 0) - { - *val = pedo_deb_reg.deb_step; - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + + if (ret == 0) + { + *val = pedo_deb_reg.deb_step; } return ret; @@ -5853,14 +6008,11 @@ int32_t lsm6dsl_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) pedo_deb_reg.deb_time = val; ret = lsm6dsl_write_reg(ctx, LSM6DSL_PEDO_DEB_REG, (uint8_t *)&pedo_deb_reg, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -5885,12 +6037,13 @@ int32_t lsm6dsl_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG, (uint8_t *)&pedo_deb_reg, 1); + } - if (ret == 0) - { - *val = pedo_deb_reg.deb_time; - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + + if (ret == 0) + { + *val = pedo_deb_reg.deb_time; } return ret; @@ -5914,13 +6067,10 @@ int32_t lsm6dsl_pedo_steps_period_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsl_write_reg(ctx, LSM6DSL_STEP_COUNT_DELTA, buff, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -5942,13 +6092,10 @@ int32_t lsm6dsl_pedo_steps_period_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsl_read_reg(ctx, LSM6DSL_STEP_COUNT_DELTA, buff, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -6008,6 +6155,9 @@ int32_t lsm6dsl_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.sign_motion_en; return ret; @@ -6030,13 +6180,10 @@ int32_t lsm6dsl_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6dsl_write_reg(ctx, LSM6DSL_SM_THS, buff, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -6057,13 +6204,10 @@ int32_t lsm6dsl_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6dsl_read_reg(ctx, LSM6DSL_SM_THS, buff, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -6124,6 +6268,9 @@ int32_t lsm6dsl_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.tilt_en; return ret; @@ -6173,6 +6320,9 @@ int32_t lsm6dsl_wrist_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.wrist_tilt_en; return ret; @@ -6197,13 +6347,10 @@ int32_t lsm6dsl_tilt_latency_set(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6dsl_write_reg(ctx, LSM6DSL_A_WRIST_TILT_LAT, buff, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -6226,13 +6373,10 @@ int32_t lsm6dsl_tilt_latency_get(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_LAT, buff, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -6255,13 +6399,10 @@ int32_t lsm6dsl_tilt_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6dsl_write_reg(ctx, LSM6DSL_A_WRIST_TILT_THS, buff, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -6284,13 +6425,10 @@ int32_t lsm6dsl_tilt_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_THS, buff, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -6313,13 +6451,10 @@ int32_t lsm6dsl_tilt_src_set(const stmdev_ctx_t *ctx, { ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK, (uint8_t *) val, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -6342,13 +6477,10 @@ int32_t lsm6dsl_tilt_src_get(const stmdev_ctx_t *ctx, { ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK, (uint8_t *) val, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -6403,6 +6535,9 @@ int32_t lsm6dsl_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl9_xl.soft_en; return ret; @@ -6466,6 +6601,9 @@ int32_t lsm6dsl_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + if (ret != 0) { return ret; } + *val = master_config.iron_en; return ret; @@ -6490,13 +6628,10 @@ int32_t lsm6dsl_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsl_write_reg(ctx, LSM6DSL_MAG_SI_XX, buff, 9); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -6519,19 +6654,16 @@ int32_t lsm6dsl_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsl_read_reg(ctx, LSM6DSL_MAG_SI_XX, buff, 9); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } /** * @brief Offset for hard-iron compensation register (r/w). The value is - * expressed as a 16-bit word in two’s complement.[set] + * expressed as a 16-bit word in two's complement.[set] * * @param ctx Read / write interface definitions * @param buff Buffer that contains data to write @@ -6554,19 +6686,16 @@ int32_t lsm6dsl_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) buff[5] = (uint8_t)((uint16_t)val[2] / 256U); buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U)); ret = lsm6dsl_write_reg(ctx, LSM6DSL_MAG_OFFX_L, buff, 6); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } /** * @brief Offset for hard-iron compensation register(r/w). - * The value is expressed as a 16-bit word in two’s complement.[get] + * The value is expressed as a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -6589,13 +6718,10 @@ int32_t lsm6dsl_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) val[1] = (val[1] * 256) + (int16_t)buff[2]; val[2] = (int16_t)buff[5]; val[2] = (val[2] * 256) + (int16_t)buff[4]; - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -6680,6 +6806,9 @@ int32_t lsm6dsl_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_TIME_FRAME, (uint8_t *)&sensor_sync_time_frame, 1); + + if (ret != 0) { return ret; } + *val = sensor_sync_time_frame.tph; return ret; @@ -6729,6 +6858,8 @@ int32_t lsm6dsl_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_RES_RATIO, (uint8_t *)&sensor_sync_res_ratio, 1); + if (ret != 0) { return ret; } + switch (sensor_sync_res_ratio.rr) { case LSM6DSL_RES_RATIO_2_11: @@ -6796,6 +6927,9 @@ int32_t lsm6dsl_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + if (ret != 0) { return ret; } + *val = master_config.master_on; return ret; @@ -6842,6 +6976,9 @@ int32_t lsm6dsl_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + if (ret != 0) { return ret; } + *val = master_config.pass_through_mode; return ret; @@ -6891,6 +7028,8 @@ int32_t lsm6dsl_sh_pin_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) { return ret; } + switch (master_config.pull_up_en) { case LSM6DSL_EXT_PULL_UP: @@ -6953,6 +7092,8 @@ int32_t lsm6dsl_sh_syncro_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) { return ret; } + switch (master_config.start_config) { case LSM6DSL_XL_GY_DRDY: @@ -7012,6 +7153,9 @@ int32_t lsm6dsl_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + if (ret != 0) { return ret; } + *val = master_config.drdy_on_int1; return ret; @@ -7085,6 +7229,9 @@ int32_t lsm6dsl_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CMD_CODE, (uint8_t *)&master_cmd_code, 1); + + if (ret != 0) { return ret; } + *val = master_cmd_code.master_cmd_code; return ret; @@ -7133,6 +7280,9 @@ int32_t lsm6dsl_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENS_SYNC_SPI_ERROR_CODE, (uint8_t *)&sens_sync_spi_error_code, 1); + + if (ret != 0) { return ret; } + *val = sens_sync_spi_error_code.error_code; return ret; @@ -7164,14 +7314,11 @@ int32_t lsm6dsl_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, slave0_config.aux_sens_on = (uint8_t) val; ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7220,11 +7367,11 @@ int32_t lsm6dsl_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, *val = LSM6DSL_SLV_EN_ND; break; } - - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7262,15 +7409,12 @@ int32_t lsm6dsl_sh_cfg_write(const stmdev_ctx_t *ctx, { ret = lsm6dsl_write_reg(ctx, LSM6DSL_DATAWRITE_SRC_MODE_SUB_SLV0, &(val->slv0_data), 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7315,16 +7459,13 @@ int32_t lsm6dsl_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, { ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7369,16 +7510,13 @@ int32_t lsm6dsl_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, { ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7423,16 +7561,13 @@ int32_t lsm6dsl_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, slave2_config.slave2_numop = val->slv_len; ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE2_CONFIG, (uint8_t *)&slave2_config, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7477,16 +7612,13 @@ int32_t lsm6dsl_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, slave3_config.slave3_numop = val->slv_len; ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE3_CONFIG, (uint8_t *)&slave3_config, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7517,14 +7649,11 @@ int32_t lsm6dsl_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, slave0_config.slave0_rate = (uint8_t) val; ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7574,11 +7703,11 @@ int32_t lsm6dsl_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, *val = LSM6DSL_SL0_DEC_ND; break; } - - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7611,14 +7740,11 @@ int32_t lsm6dsl_sh_write_mode_set(const stmdev_ctx_t *ctx, { ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7662,11 +7788,11 @@ int32_t lsm6dsl_sh_write_mode_get(const stmdev_ctx_t *ctx, *val = LSM6DSL_SH_WR_MODE_ND; break; } - - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7697,14 +7823,11 @@ int32_t lsm6dsl_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, slave1_config.slave1_rate = (uint8_t) val; ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7753,11 +7876,11 @@ int32_t lsm6dsl_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, *val = LSM6DSL_SL1_DEC_ND; break; } - - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7788,14 +7911,11 @@ int32_t lsm6dsl_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, slave2_config.slave2_rate = (uint8_t) val; ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE2_CONFIG, (uint8_t *)&slave2_config, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7845,11 +7965,11 @@ int32_t lsm6dsl_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, *val = LSM6DSL_SL2_DEC_ND; break; } - - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7880,14 +8000,11 @@ int32_t lsm6dsl_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, { ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE3_CONFIG, (uint8_t *)&slave3_config, 1); - - if (ret == 0) - { - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); - } } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7937,11 +8054,11 @@ int32_t lsm6dsl_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, *val = LSM6DSL_SL3_DEC_ND; break; } - - ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); } } + ret += lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK); + return ret; } @@ -7954,5 +8071,3 @@ int32_t lsm6dsl_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h index 51049ff..12093f4 100644 --- a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h +++ b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -2060,7 +2062,7 @@ typedef enum LSM6DSL_HP_DISABLE_LP1_LIGHT = 0x0A, LSM6DSL_HP_DISABLE_LP1_NORMAL = 0x09, - LSM6DSL_HP_DISABLE_LP_STRONG = 0x08, + LSM6DSL_HP_DISABLE_LP1_STRONG = 0x08, LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE = 0x0B, LSM6DSL_HP_16mHz_LP1_LIGHT = 0x8A, @@ -2742,5 +2744,3 @@ int32_t lsm6dsl_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, #endif #endif /* LSM6DSL_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c index 5f23d34..873ab85 100644 --- a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c +++ b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -205,6 +204,8 @@ int32_t lsm6dsm_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl1_xl.fs_xl) { case LSM6DSM_2g: @@ -272,6 +273,8 @@ int32_t lsm6dsm_xl_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl1_xl.odr_xl) { case LSM6DSM_XL_ODR_OFF: @@ -371,6 +374,8 @@ int32_t lsm6dsm_gy_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) { return ret; } + switch (ctrl2_g.fs_g) { case LSM6DSM_250dps: @@ -442,6 +447,8 @@ int32_t lsm6dsm_gy_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) { return ret; } + switch (ctrl2_g.odr_g) { case LSM6DSM_GY_ODR_OFF: @@ -534,6 +541,9 @@ int32_t lsm6dsm_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_c.bdu; return ret; @@ -582,6 +592,8 @@ int32_t lsm6dsm_xl_offset_weight_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } + switch (ctrl6_c.usr_off_w) { case LSM6DSM_LSb_1mg: @@ -641,6 +653,8 @@ int32_t lsm6dsm_xl_power_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } + switch (ctrl6_c.xl_hm_mode) { case LSM6DSM_XL_HIGH_PERFORMANCE: @@ -704,6 +718,8 @@ int32_t lsm6dsm_rounding_on_status_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) { return ret; } + switch (ctrl7_g.rounding_status) { case LSM6DSM_STAT_RND_DISABLE: @@ -763,6 +779,8 @@ int32_t lsm6dsm_gy_power_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) { return ret; } + switch (ctrl7_g.g_hm_mode) { case LSM6DSM_GY_HIGH_PERFORMANCE: @@ -837,17 +855,14 @@ int32_t lsm6dsm_all_sources_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B); - } - if (ret == 0) - { - ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK, - (uint8_t *) & (val->a_wrist_tilt_mask), 1); - } + if (ret == 0) + { + ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK, + (uint8_t *) & (val->a_wrist_tilt_mask), 1); + } - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); } return ret; @@ -886,6 +901,9 @@ int32_t lsm6dsm_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.xlda; return ret; @@ -907,6 +925,9 @@ int32_t lsm6dsm_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.gda; return ret; @@ -928,13 +949,16 @@ int32_t lsm6dsm_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) { return ret; } + *val = status_reg.tda; return ret; } /** - * @brief Accelerometer axis user offset correction expressed in two’s + * @brief Accelerometer axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C. * The value must be in the range [-127 127].[set] * @@ -953,7 +977,7 @@ int32_t lsm6dsm_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer axis user offset correction xpressed in two’s + * @brief Accelerometer axis user offset correction xpressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C. * The value must be in the range [-127 127].[get] * @@ -1029,6 +1053,9 @@ int32_t lsm6dsm_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.timer_en; return ret; @@ -1088,6 +1115,8 @@ int32_t lsm6dsm_timestamp_res_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) { return ret; } + switch (wake_up_dur.timer_hr) { case LSM6DSM_LSB_6ms4: @@ -1161,6 +1190,8 @@ int32_t lsm6dsm_rounding_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.rounding) { case LSM6DSM_ROUND_DISABLE: @@ -1205,7 +1236,7 @@ int32_t lsm6dsm_rounding_mode_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers together - * express a 16-bit word in two’s complement.[get] + * express a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -1218,6 +1249,9 @@ int32_t lsm6dsm_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUT_TEMP_L, buff, 2); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1226,7 +1260,7 @@ int32_t lsm6dsm_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Angular rate sensor. The value is expressed as a 16-bit word in - * two’s complement.[get] + * two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -1239,6 +1273,9 @@ int32_t lsm6dsm_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUTX_L_G, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1251,7 +1288,7 @@ int32_t lsm6dsm_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed - * as a 16-bit word in two’s complement.[get] + * as a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -1264,6 +1301,9 @@ int32_t lsm6dsm_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUTX_L_XL, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1289,6 +1329,9 @@ int32_t lsm6dsm_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUT_MAG_RAW_X_L, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1376,6 +1419,8 @@ int32_t lsm6dsm_mem_bank_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) { return ret; } + switch (func_cfg_access.func_cfg_en) { case LSM6DSM_USER_BANK: @@ -1438,6 +1483,8 @@ int32_t lsm6dsm_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG, (uint8_t *)&drdy_pulse_cfg, 1); + if (ret != 0) { return ret; } + switch (drdy_pulse_cfg.drdy_pulsed) { case LSM6DSM_DRDY_LATCHED: @@ -1511,6 +1558,9 @@ int32_t lsm6dsm_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_c.sw_reset; return ret; @@ -1555,6 +1605,8 @@ int32_t lsm6dsm_data_format_get(const stmdev_ctx_t *ctx, lsm6dsm_ble_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + switch (ctrl3_c.ble) { case LSM6DSM_LSB_AT_LOW_ADD: @@ -1613,6 +1665,9 @@ int32_t lsm6dsm_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_c.if_inc; return ret; @@ -1656,6 +1711,9 @@ int32_t lsm6dsm_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl3_c.boot; return ret; @@ -1702,6 +1760,8 @@ int32_t lsm6dsm_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.st_xl) { case LSM6DSM_XL_ST_DISABLE: @@ -1765,6 +1825,8 @@ int32_t lsm6dsm_gy_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.st_g) { case LSM6DSM_GY_ST_DISABLE: @@ -1842,6 +1904,9 @@ int32_t lsm6dsm_filter_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl4_c.drdy_mask; return ret; @@ -1890,6 +1955,8 @@ int32_t lsm6dsm_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1); + if (ret != 0) { return ret; } + switch (tap_cfg.slope_fds) { case LSM6DSM_USE_SLOPE: @@ -1964,6 +2031,8 @@ int32_t lsm6dsm_xl_filter_analog_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl1_xl.bw0_xl) { case LSM6DSM_XL_ANA_BW_1k5Hz: @@ -2065,19 +2134,22 @@ int32_t lsm6dsm_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, { ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - switch (ctrl1_xl.lpf1_bw_sel) + if (ret == 0) { - case LSM6DSM_XL_LP1_ODR_DIV_2: - *val = LSM6DSM_XL_LP1_ODR_DIV_2; - break; + switch (ctrl1_xl.lpf1_bw_sel) + { + case LSM6DSM_XL_LP1_ODR_DIV_2: + *val = LSM6DSM_XL_LP1_ODR_DIV_2; + break; - case LSM6DSM_XL_LP1_ODR_DIV_4: - *val = LSM6DSM_XL_LP1_ODR_DIV_4; - break; + case LSM6DSM_XL_LP1_ODR_DIV_4: + *val = LSM6DSM_XL_LP1_ODR_DIV_4; + break; - default: - *val = LSM6DSM_XL_LP1_ODR_DIV_2; - break; + default: + *val = LSM6DSM_XL_LP1_ODR_DIV_2; + break; + } } } } @@ -2221,6 +2293,9 @@ int32_t lsm6dsm_xl_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl8_xl.hp_ref_mode; return ret; @@ -2269,6 +2344,8 @@ int32_t lsm6dsm_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { return ret; } + if (ctrl8_xl.hp_slope_xl_en == 0x00U) { *val = LSM6DSM_XL_HP_NA; @@ -2381,19 +2458,22 @@ int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(const stmdev_ctx_t *ctx, { ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - switch (ctrl1_xl.lpf1_bw_sel) + if (ret == 0) { - case LSM6DSM_XL_UI_LP1_ODR_DIV_2: - *val = LSM6DSM_XL_UI_LP1_ODR_DIV_2; - break; + switch (ctrl1_xl.lpf1_bw_sel) + { + case LSM6DSM_XL_UI_LP1_ODR_DIV_2: + *val = LSM6DSM_XL_UI_LP1_ODR_DIV_2; + break; - case LSM6DSM_XL_UI_LP1_ODR_DIV_4: - *val = LSM6DSM_XL_UI_LP1_ODR_DIV_4; - break; + case LSM6DSM_XL_UI_LP1_ODR_DIV_4: + *val = LSM6DSM_XL_UI_LP1_ODR_DIV_4; + break; - default: - *val = LSM6DSM_XL_UI_LP1_ODR_DIV_2; - break; + default: + *val = LSM6DSM_XL_UI_LP1_ODR_DIV_2; + break; + } } } } @@ -2439,6 +2519,9 @@ int32_t lsm6dsm_xl_ui_slope_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl8_xl.hp_slope_xl_en; return ret; @@ -2511,6 +2594,8 @@ int32_t lsm6dsm_xl_aux_lp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) { return ret; } + switch (ctrl3_ois.filter_xl_conf_ois) { case LSM6DSM_AUX_LP_LIGHT: @@ -2620,71 +2705,63 @@ int32_t lsm6dsm_gy_band_pass_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - if (ret == 0) + switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) + + (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype) { - ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - - if (ret == 0) - { - ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - - switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) + - (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype) - { - case LSM6DSM_HP_16mHz_LP2: - *val = LSM6DSM_HP_16mHz_LP2; - break; + case LSM6DSM_HP_16mHz_LP2: + *val = LSM6DSM_HP_16mHz_LP2; + break; - case LSM6DSM_HP_65mHz_LP2: - *val = LSM6DSM_HP_65mHz_LP2; - break; + case LSM6DSM_HP_65mHz_LP2: + *val = LSM6DSM_HP_65mHz_LP2; + break; - case LSM6DSM_HP_260mHz_LP2: - *val = LSM6DSM_HP_260mHz_LP2; - break; + case LSM6DSM_HP_260mHz_LP2: + *val = LSM6DSM_HP_260mHz_LP2; + break; - case LSM6DSM_HP_1Hz04_LP2: - *val = LSM6DSM_HP_1Hz04_LP2; - break; + case LSM6DSM_HP_1Hz04_LP2: + *val = LSM6DSM_HP_1Hz04_LP2; + break; - case LSM6DSM_HP_DISABLE_LP1_LIGHT: - *val = LSM6DSM_HP_DISABLE_LP1_LIGHT; - break; + case LSM6DSM_HP_DISABLE_LP1_LIGHT: + *val = LSM6DSM_HP_DISABLE_LP1_LIGHT; + break; - case LSM6DSM_HP_DISABLE_LP1_NORMAL: - *val = LSM6DSM_HP_DISABLE_LP1_NORMAL; - break; + case LSM6DSM_HP_DISABLE_LP1_NORMAL: + *val = LSM6DSM_HP_DISABLE_LP1_NORMAL; + break; - case LSM6DSM_HP_DISABLE_LP_STRONG: - *val = LSM6DSM_HP_DISABLE_LP_STRONG; - break; + case LSM6DSM_HP_DISABLE_LP_STRONG: + *val = LSM6DSM_HP_DISABLE_LP_STRONG; + break; - case LSM6DSM_HP_DISABLE_LP1_AGGRESSIVE: - *val = LSM6DSM_HP_DISABLE_LP1_AGGRESSIVE; - break; + case LSM6DSM_HP_DISABLE_LP1_AGGRESSIVE: + *val = LSM6DSM_HP_DISABLE_LP1_AGGRESSIVE; + break; - case LSM6DSM_HP_16mHz_LP1_LIGHT: - *val = LSM6DSM_HP_16mHz_LP1_LIGHT; - break; + case LSM6DSM_HP_16mHz_LP1_LIGHT: + *val = LSM6DSM_HP_16mHz_LP1_LIGHT; + break; - case LSM6DSM_HP_65mHz_LP1_NORMAL: - *val = LSM6DSM_HP_65mHz_LP1_NORMAL; - break; + case LSM6DSM_HP_65mHz_LP1_NORMAL: + *val = LSM6DSM_HP_65mHz_LP1_NORMAL; + break; - case LSM6DSM_HP_260mHz_LP1_STRONG: - *val = LSM6DSM_HP_260mHz_LP1_STRONG; - break; + case LSM6DSM_HP_260mHz_LP1_STRONG: + *val = LSM6DSM_HP_260mHz_LP1_STRONG; + break; - case LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE: - *val = LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE; - break; + case LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE: + *val = LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE; + break; - default: - *val = LSM6DSM_HP_65mHz_LP2; - break; - } - } + default: + *val = LSM6DSM_HP_65mHz_LP2; + break; } return ret; @@ -2744,6 +2821,9 @@ int32_t lsm6dsm_gy_ui_high_pass_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + if (ret != 0) { return ret; } + *val = ctrl7_g.hp_en_g; return ret; @@ -2809,6 +2889,8 @@ int32_t lsm6dsm_gy_aux_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1); + if (ret != 0) { return ret; } + switch (((ctrl2_ois.hp_en_ois << 7) + (ctrl2_ois.hpm_ois << 4) + ctrl2_ois.ftype_ois)) { @@ -2899,6 +2981,9 @@ int32_t lsm6dsm_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX, (uint8_t *)&status_spiaux, 1); + + if (ret != 0) { return ret; } + *val = status_spiaux.xlda; return ret; @@ -2920,6 +3005,9 @@ int32_t lsm6dsm_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX, (uint8_t *)&status_spiaux, 1); + + if (ret != 0) { return ret; } + *val = status_spiaux.gda; return ret; @@ -2941,6 +3029,9 @@ int32_t lsm6dsm_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX, (uint8_t *)&status_spiaux, 1); + + if (ret != 0) { return ret; } + *val = status_spiaux.gyro_settling; return ret; @@ -2999,11 +3090,10 @@ int32_t lsm6dsm_aux_den_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); if (ret == 0) { - ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); - switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) { case LSM6DSM_AUX_DEN_DISABLE: @@ -3067,6 +3157,9 @@ int32_t lsm6dsm_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1); + + if (ret != 0) { return ret; } + *val = int_ois.int2_drdy_ois; return ret; @@ -3128,6 +3221,8 @@ int32_t lsm6dsm_aux_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) { return ret; } + switch ((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2) { case LSM6DSM_AUX_DISABLE: @@ -3191,6 +3286,8 @@ int32_t lsm6dsm_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) { return ret; } + switch (ctrl1_ois.fs_g_ois) { case LSM6DSM_250dps_AUX: @@ -3262,6 +3359,8 @@ int32_t lsm6dsm_aux_spi_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) { return ret; } + switch (ctrl1_ois.sim_ois) { case LSM6DSM_AUX_SPI_4_WIRE: @@ -3321,6 +3420,8 @@ int32_t lsm6dsm_aux_data_format_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) { return ret; } + switch (ctrl1_ois.ble_ois) { case LSM6DSM_AUX_LSB_AT_LOW_ADD: @@ -3388,6 +3489,8 @@ int32_t lsm6dsm_aux_gy_clamp_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) { return ret; } + switch (ctrl3_ois.st_ois_clampdis) { case LSM6DSM_ENABLE_CLAMP: @@ -3447,6 +3550,8 @@ int32_t lsm6dsm_aux_gy_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) { return ret; } + switch (ctrl3_ois.st_ois) { case LSM6DSM_AUX_GY_DISABLE: @@ -3510,6 +3615,8 @@ int32_t lsm6dsm_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) { return ret; } + switch (ctrl3_ois.fs_xl_ois) { case LSM6DSM_AUX_2g: @@ -3577,6 +3684,8 @@ int32_t lsm6dsm_aux_den_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) { return ret; } + switch (ctrl3_ois.den_lh_ois) { case LSM6DSM_AUX_DEN_ACTIVE_LOW: @@ -3647,6 +3756,8 @@ int32_t lsm6dsm_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_sim_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + switch (ctrl3_c.sim) { case LSM6DSM_SPI_4_WIRE: @@ -3706,6 +3817,8 @@ int32_t lsm6dsm_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) { return ret; } + switch (ctrl4_c.i2c_disable) { case LSM6DSM_I2C_ENABLE: @@ -3872,6 +3985,10 @@ int32_t lsm6dsm_pin_int1_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG, + (uint8_t *)&master_config, 1); if (ret == 0) { @@ -3883,28 +4000,19 @@ int32_t lsm6dsm_pin_int1_route_get(const stmdev_ctx_t *ctx, val->int1_full_flag = int1_ctrl.int1_full_flag; val->int1_sign_mot = int1_ctrl.int1_sign_mot; val->int1_step_detector = int1_ctrl.int1_step_detector ; - ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret == 0) - { - val->int1_timer = md1_cfg.int1_timer; - val->int1_tilt = md1_cfg.int1_tilt; - val->int1_6d = md1_cfg.int1_6d; - val->int1_double_tap = md1_cfg.int1_double_tap; - val->int1_ff = md1_cfg.int1_ff; - val->int1_wu = md1_cfg.int1_wu; - val->int1_single_tap = md1_cfg.int1_single_tap; - val->int1_inact_state = md1_cfg.int1_inact_state; - ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + val->int1_timer = md1_cfg.int1_timer; + val->int1_tilt = md1_cfg.int1_tilt; + val->int1_6d = md1_cfg.int1_6d; + val->int1_double_tap = md1_cfg.int1_double_tap; + val->int1_ff = md1_cfg.int1_ff; + val->int1_wu = md1_cfg.int1_wu; + val->int1_single_tap = md1_cfg.int1_single_tap; + val->int1_inact_state = md1_cfg.int1_inact_state; - if (ret == 0) - { - val->den_drdy_int1 = ctrl4_c.den_drdy_int1; - ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - val->den_drdy_int1 = master_config.drdy_on_int1; - } - } + val->den_drdy_int1 = ctrl4_c.den_drdy_int1; + + val->den_drdy_int1 = master_config.drdy_on_int1; } return ret; @@ -4030,6 +4138,9 @@ int32_t lsm6dsm_pin_int2_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG, + (uint8_t *)&drdy_pulse_cfg, 1); if (ret == 0) { @@ -4041,22 +4152,17 @@ int32_t lsm6dsm_pin_int2_route_get(const stmdev_ctx_t *ctx, val->int2_full_flag = int2_ctrl.int2_full_flag; val->int2_step_count_ov = int2_ctrl.int2_step_count_ov; val->int2_step_delta = int2_ctrl.int2_step_delta; - ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret == 0) - { - val->int2_iron = md2_cfg.int2_iron; - val->int2_tilt = md2_cfg.int2_tilt; - val->int2_6d = md2_cfg.int2_6d; - val->int2_double_tap = md2_cfg.int2_double_tap; - val->int2_ff = md2_cfg.int2_ff; - val->int2_wu = md2_cfg.int2_wu; - val->int2_single_tap = md2_cfg.int2_single_tap; - val->int2_inact_state = md2_cfg.int2_inact_state; - ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG, - (uint8_t *)&drdy_pulse_cfg, 1); - val->int2_wrist_tilt = drdy_pulse_cfg.int2_wrist_tilt; - } + val->int2_iron = md2_cfg.int2_iron; + val->int2_tilt = md2_cfg.int2_tilt; + val->int2_6d = md2_cfg.int2_6d; + val->int2_double_tap = md2_cfg.int2_double_tap; + val->int2_ff = md2_cfg.int2_ff; + val->int2_wu = md2_cfg.int2_wu; + val->int2_single_tap = md2_cfg.int2_single_tap; + val->int2_inact_state = md2_cfg.int2_inact_state; + + val->int2_wrist_tilt = drdy_pulse_cfg.int2_wrist_tilt; } return ret; @@ -4101,6 +4207,8 @@ int32_t lsm6dsm_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + switch (ctrl3_c.pp_od) { case LSM6DSM_PUSH_PULL: @@ -4160,6 +4268,8 @@ int32_t lsm6dsm_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) { return ret; } + switch (ctrl3_c.h_lactive) { case LSM6DSM_ACTIVE_HIGH: @@ -4216,6 +4326,9 @@ int32_t lsm6dsm_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl4_c.int2_on_int1; return ret; @@ -4262,6 +4375,8 @@ int32_t lsm6dsm_int_notification_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1); + if (ret != 0) { return ret; } + switch (tap_cfg.lir) { case LSM6DSM_INT_PULSED: @@ -4334,6 +4449,9 @@ int32_t lsm6dsm_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { return ret; } + *val = wake_up_ths.wk_ths; return ret; @@ -4380,6 +4498,9 @@ int32_t lsm6dsm_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + if (ret != 0) { return ret; } + *val = wake_up_dur.wake_dur; return ret; @@ -4436,6 +4557,9 @@ int32_t lsm6dsm_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl4_c.sleep; return ret; @@ -4482,6 +4606,8 @@ int32_t lsm6dsm_act_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1); + if (ret != 0) { return ret; } + switch (tap_cfg.inact_en) { case LSM6DSM_PROPERTY_DISABLE: @@ -4549,6 +4675,9 @@ int32_t lsm6dsm_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + if (ret != 0) { return ret; } + *val = wake_up_dur.sleep_dur; return ret; @@ -4622,6 +4751,9 @@ int32_t lsm6dsm_tap_detection_on_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret != 0) { return ret; } + *val = tap_cfg.tap_z_en; return ret; @@ -4666,6 +4798,9 @@ int32_t lsm6dsm_tap_detection_on_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret != 0) { return ret; } + *val = tap_cfg.tap_y_en; return ret; @@ -4710,6 +4845,9 @@ int32_t lsm6dsm_tap_detection_on_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1); + + if (ret != 0) { return ret; } + *val = tap_cfg.tap_x_en; return ret; @@ -4756,6 +4894,9 @@ int32_t lsm6dsm_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + + if (ret != 0) { return ret; } + *val = tap_ths_6d.tap_ths; return ret; @@ -4809,6 +4950,9 @@ int32_t lsm6dsm_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1); + + if (ret != 0) { return ret; } + *val = int_dur2.shock; return ret; @@ -4862,6 +5006,9 @@ int32_t lsm6dsm_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1); + + if (ret != 0) { return ret; } + *val = int_dur2.quiet; return ret; @@ -4917,6 +5064,9 @@ int32_t lsm6dsm_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1); + + if (ret != 0) { return ret; } + *val = int_dur2.dur; return ret; @@ -4968,6 +5118,8 @@ int32_t lsm6dsm_tap_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) { return ret; } + switch (wake_up_ths.single_double_tap) { case LSM6DSM_ONLY_SINGLE: @@ -5041,6 +5193,8 @@ int32_t lsm6dsm_6d_feed_data_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) { return ret; } + switch (ctrl8_xl.low_pass_on_6d) { case LSM6DSM_ODR_DIV_2_FEED: @@ -5103,6 +5257,8 @@ int32_t lsm6dsm_6d_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) { return ret; } + switch (tap_ths_6d.sixd_ths) { case LSM6DSM_DEG_80: @@ -5170,6 +5326,9 @@ int32_t lsm6dsm_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + + if (ret != 0) { return ret; } + *val = tap_ths_6d.d4d_en; return ret; @@ -5242,11 +5401,9 @@ int32_t lsm6dsm_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1); - if (ret == 0) - { - ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1); - } + if (ret != 0) { return ret; } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -5294,6 +5451,8 @@ int32_t lsm6dsm_ff_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) { return ret; } + switch (free_fall.ff_ths) { case LSM6DSM_FF_TSH_156mg: @@ -5399,12 +5558,10 @@ int32_t lsm6dsm_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); - if (ret == 0) - { - ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); - } + if (ret != 0) { return ret; } *val = ((uint16_t)fifo_ctrl2.fth << 8) + (uint16_t)fifo_ctrl1.fth; @@ -5429,11 +5586,11 @@ int32_t lsm6dsm_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); if (ret == 0) { - ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); *val = ((uint16_t) fifo_status2.diff_fifo << 8) + (uint16_t) fifo_status1.diff_fifo; } @@ -5456,6 +5613,9 @@ int32_t lsm6dsm_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); + + if (ret != 0) { return ret; } + *val = fifo_status2.waterm; return ret; @@ -5476,6 +5636,9 @@ int32_t lsm6dsm_fifo_over_run_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2, (uint8_t *)&fifo_status2, 1); + + if (ret != 0) { return ret; } + *val = fifo_status2.over_run; return ret; @@ -5498,11 +5661,11 @@ int32_t lsm6dsm_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS3, (uint8_t *)&fifo_status3, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS4, + (uint8_t *)&fifo_status4, 1); if (ret == 0) { - ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS4, - (uint8_t *)&fifo_status4, 1); *val = ((uint16_t)fifo_status4.fifo_pattern << 8) + fifo_status3.fifo_pattern; } @@ -5551,6 +5714,9 @@ int32_t lsm6dsm_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl2.fifo_temp_en; return ret; @@ -5616,12 +5782,11 @@ int32_t lsm6dsm_fifo_write_trigger_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG, + (uint8_t *)&master_config, 1); if (ret == 0) { - ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - switch ((master_config.data_valid_sel_fifo << 1) + fifo_ctrl2.timer_pedo_fifo_drdy) { @@ -5691,6 +5856,9 @@ int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl2.timer_pedo_fifo_en; return ret; @@ -5742,6 +5910,8 @@ int32_t lsm6dsm_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl3.dec_fifo_xl) { case LSM6DSM_FIFO_XL_DISABLE: @@ -5830,6 +6000,8 @@ int32_t lsm6dsm_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl3.dec_fifo_gyro) { case LSM6DSM_FIFO_GY_DISABLE: @@ -5918,6 +6090,8 @@ int32_t lsm6dsm_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl4.dec_ds3_fifo) { case LSM6DSM_FIFO_DS3_DISABLE: @@ -6006,6 +6180,8 @@ int32_t lsm6dsm_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl4.dec_ds4_fifo) { case LSM6DSM_FIFO_DS4_DISABLE: @@ -6091,6 +6267,9 @@ int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl4.only_high_data; return ret; @@ -6139,6 +6318,9 @@ int32_t lsm6dsm_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + + if (ret != 0) { return ret; } + *val = fifo_ctrl4.stop_on_fth; return ret; @@ -6188,6 +6370,8 @@ int32_t lsm6dsm_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5, (uint8_t *)&fifo_ctrl5, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl5.fifo_mode) { case LSM6DSM_BYPASS_MODE: @@ -6262,6 +6446,8 @@ int32_t lsm6dsm_fifo_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5, (uint8_t *)&fifo_ctrl5, 1); + if (ret != 0) { return ret; } + switch (fifo_ctrl5.odr_fifo) { case LSM6DSM_FIFO_DISABLE: @@ -6370,6 +6556,8 @@ int32_t lsm6dsm_den_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) { return ret; } + switch (ctrl5_c.den_lh) { case LSM6DSM_DEN_ACT_LOW: @@ -6429,6 +6617,8 @@ int32_t lsm6dsm_den_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) { return ret; } + switch (ctrl6_c.den_mode) { case LSM6DSM_DEN_DISABLE: @@ -6510,11 +6700,10 @@ int32_t lsm6dsm_den_enable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + ret += lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); if (ret == 0) { - ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g) { case LSM6DSM_STAMP_IN_GY_DATA: @@ -6576,6 +6765,9 @@ int32_t lsm6dsm_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_z; return ret; @@ -6619,6 +6811,9 @@ int32_t lsm6dsm_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_y; return ret; @@ -6662,6 +6857,9 @@ int32_t lsm6dsm_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl9_xl.den_x; return ret; @@ -6717,6 +6915,9 @@ int32_t lsm6dsm_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.pedo_rst_step; return ret; @@ -6766,6 +6967,9 @@ int32_t lsm6dsm_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.pedo_en; return ret; @@ -6797,14 +7001,11 @@ int32_t lsm6dsm_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) config_pedo_ths_min.ths_min = val; ret = lsm6dsm_write_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN, (uint8_t *)&config_pedo_ths_min, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -6831,10 +7032,11 @@ int32_t lsm6dsm_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = config_pedo_ths_min.ths_min; - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -6865,14 +7067,11 @@ int32_t lsm6dsm_pedo_full_scale_set(const stmdev_ctx_t *ctx, config_pedo_ths_min.pedo_fs = (uint8_t) val; ret = lsm6dsm_write_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN, (uint8_t *)&config_pedo_ths_min, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -6914,11 +7113,11 @@ int32_t lsm6dsm_pedo_full_scale_get(const stmdev_ctx_t *ctx, *val = LSM6DSM_PEDO_AT_2g; break; } - - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -6948,14 +7147,11 @@ int32_t lsm6dsm_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, pedo_deb_reg.deb_step = val; ret = lsm6dsm_write_reg(ctx, LSM6DSM_PEDO_DEB_REG, (uint8_t *)&pedo_deb_reg, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -6983,10 +7179,11 @@ int32_t lsm6dsm_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = pedo_deb_reg.deb_step; - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7017,14 +7214,11 @@ int32_t lsm6dsm_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) pedo_deb_reg.deb_time = val; ret = lsm6dsm_write_reg(ctx, LSM6DSM_PEDO_DEB_REG, (uint8_t *)&pedo_deb_reg, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7053,10 +7247,11 @@ int32_t lsm6dsm_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = pedo_deb_reg.deb_time; - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7078,13 +7273,10 @@ int32_t lsm6dsm_pedo_steps_period_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsm_write_reg(ctx, LSM6DSM_STEP_COUNT_DELTA, buff, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7106,13 +7298,10 @@ int32_t lsm6dsm_pedo_steps_period_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsm_read_reg(ctx, LSM6DSM_STEP_COUNT_DELTA, buff, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7172,6 +7361,9 @@ int32_t lsm6dsm_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.sign_motion_en; return ret; @@ -7194,13 +7386,10 @@ int32_t lsm6dsm_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6dsm_write_reg(ctx, LSM6DSM_SM_THS, buff, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7221,13 +7410,10 @@ int32_t lsm6dsm_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6dsm_read_reg(ctx, LSM6DSM_SM_THS, buff, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7288,6 +7474,9 @@ int32_t lsm6dsm_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.tilt_en; return ret; @@ -7337,6 +7526,9 @@ int32_t lsm6dsm_wrist_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + + if (ret != 0) { return ret; } + *val = ctrl10_c.wrist_tilt_en; return ret; @@ -7361,13 +7553,10 @@ int32_t lsm6dsm_tilt_latency_set(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6dsm_write_reg(ctx, LSM6DSM_A_WRIST_TILT_LAT, buff, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7390,13 +7579,10 @@ int32_t lsm6dsm_tilt_latency_get(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_LAT, buff, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7419,13 +7605,10 @@ int32_t lsm6dsm_tilt_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6dsm_write_reg(ctx, LSM6DSM_A_WRIST_TILT_THS, buff, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7448,13 +7631,10 @@ int32_t lsm6dsm_tilt_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_THS, buff, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7477,13 +7657,10 @@ int32_t lsm6dsm_tilt_src_set(const stmdev_ctx_t *ctx, { ret = lsm6dsm_write_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK, (uint8_t *) val, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7506,13 +7683,10 @@ int32_t lsm6dsm_tilt_src_get(const stmdev_ctx_t *ctx, { ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK, (uint8_t *) val, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7567,6 +7741,9 @@ int32_t lsm6dsm_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + if (ret != 0) { return ret; } + *val = ctrl9_xl.soft_en; return ret; @@ -7630,6 +7807,9 @@ int32_t lsm6dsm_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + if (ret != 0) { return ret; } + *val = master_config.iron_en; return ret; @@ -7654,13 +7834,10 @@ int32_t lsm6dsm_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsm_write_reg(ctx, LSM6DSM_MAG_SI_XX, buff, 9); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7683,19 +7860,16 @@ int32_t lsm6dsm_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsm_read_reg(ctx, LSM6DSM_MAG_SI_XX, buff, 9); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } /** * @brief Offset for hard-iron compensation register (r/w). The value is - * expressed as a 16-bit word in two’s complement.[set] + * expressed as a 16-bit word in two's complement.[set] * * @param ctx Read / write interface definitions * @param buff Buffer that contains data to write @@ -7718,19 +7892,16 @@ int32_t lsm6dsm_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) buff[5] = (uint8_t)((uint16_t)val[2] / 256U); buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U)); ret = lsm6dsm_write_reg(ctx, LSM6DSM_MAG_OFFX_L, buff, 6); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } /** * @brief Offset for hard-iron compensation register(r/w). - * The value is expressed as a 16-bit word in two’s complement.[get] + * The value is expressed as a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions * @param buff Buffer that stores data read @@ -7756,10 +7927,11 @@ int32_t lsm6dsm_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) val[1] = (val[1] * 256) + (int16_t)buff[2]; val[2] = (int16_t)buff[5]; val[2] = (val[2] * 256) + (int16_t)buff[4]; - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -7844,6 +8016,9 @@ int32_t lsm6dsm_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_TIME_FRAME, (uint8_t *)&sensor_sync_time_frame, 1); + + if (ret != 0) { return ret; } + *val = sensor_sync_time_frame.tph; return ret; @@ -7893,6 +8068,8 @@ int32_t lsm6dsm_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_RES_RATIO, (uint8_t *)&sensor_sync_res_ratio, 1); + if (ret != 0) { return ret; } + switch (sensor_sync_res_ratio.rr) { case LSM6DSM_RES_RATIO_2_11: @@ -7960,6 +8137,9 @@ int32_t lsm6dsm_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + if (ret != 0) { return ret; } + *val = master_config.master_on; return ret; @@ -8006,6 +8186,9 @@ int32_t lsm6dsm_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + if (ret != 0) { return ret; } + *val = master_config.pass_through_mode; return ret; @@ -8055,6 +8238,8 @@ int32_t lsm6dsm_sh_pin_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) { return ret; } + switch (master_config.pull_up_en) { case LSM6DSM_EXT_PULL_UP: @@ -8117,6 +8302,8 @@ int32_t lsm6dsm_sh_syncro_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) { return ret; } + switch (master_config.start_config) { case LSM6DSM_XL_GY_DRDY: @@ -8176,6 +8363,9 @@ int32_t lsm6dsm_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + if (ret != 0) { return ret; } + *val = master_config.drdy_on_int1; return ret; @@ -8249,6 +8439,9 @@ int32_t lsm6dsm_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CMD_CODE, (uint8_t *)&master_cmd_code, 1); + + if (ret != 0) { return ret; } + *val = master_cmd_code.master_cmd_code; return ret; @@ -8297,6 +8490,9 @@ int32_t lsm6dsm_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENS_SYNC_SPI_ERROR_CODE, (uint8_t *)&sens_sync_spi_error_code, 1); + + if (ret != 0) { return ret; } + *val = sens_sync_spi_error_code.error_code; return ret; @@ -8328,14 +8524,11 @@ int32_t lsm6dsm_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, slave0_config.aux_sens_on = (uint8_t) val; ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8384,11 +8577,11 @@ int32_t lsm6dsm_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, *val = LSM6DSM_SLV_0; break; } - - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8426,15 +8619,12 @@ int32_t lsm6dsm_sh_cfg_write(const stmdev_ctx_t *ctx, { ret = lsm6dsm_write_reg(ctx, LSM6DSM_DATAWRITE_SRC_MODE_SUB_SLV0, &(val->slv0_data), 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8479,16 +8669,13 @@ int32_t lsm6dsm_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, { ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8533,16 +8720,13 @@ int32_t lsm6dsm_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, { ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8587,16 +8771,13 @@ int32_t lsm6dsm_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, slave2_config.slave2_numop = val->slv_len; ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE2_CONFIG, (uint8_t *)&slave2_config, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8641,16 +8822,13 @@ int32_t lsm6dsm_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, slave3_config.slave3_numop = val->slv_len; ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE3_CONFIG, (uint8_t *)&slave3_config, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8681,14 +8859,11 @@ int32_t lsm6dsm_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, slave0_config.slave0_rate = (uint8_t) val; ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE0_CONFIG, (uint8_t *)&slave0_config, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8738,11 +8913,11 @@ int32_t lsm6dsm_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, *val = LSM6DSM_SL0_NO_DEC; break; } - - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8775,14 +8950,11 @@ int32_t lsm6dsm_sh_write_mode_set(const stmdev_ctx_t *ctx, { ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8826,11 +8998,11 @@ int32_t lsm6dsm_sh_write_mode_get(const stmdev_ctx_t *ctx, *val = LSM6DSM_EACH_SH_CYCLE; break; } - - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8861,14 +9033,11 @@ int32_t lsm6dsm_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, slave1_config.slave1_rate = (uint8_t) val; ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE1_CONFIG, (uint8_t *)&slave1_config, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8917,11 +9086,11 @@ int32_t lsm6dsm_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, *val = LSM6DSM_SL1_NO_DEC; break; } - - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -8952,14 +9121,11 @@ int32_t lsm6dsm_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, slave2_config.slave2_rate = (uint8_t) val; ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE2_CONFIG, (uint8_t *)&slave2_config, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -9009,11 +9175,11 @@ int32_t lsm6dsm_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, *val = LSM6DSM_SL2_NO_DEC; break; } - - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -9044,14 +9210,11 @@ int32_t lsm6dsm_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, { ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE3_CONFIG, (uint8_t *)&slave3_config, 1); - - if (ret == 0) - { - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); - } } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -9101,11 +9264,11 @@ int32_t lsm6dsm_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, *val = LSM6DSM_SL3_NO_DEC; break; } - - ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); } } + ret += lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK); + return ret; } @@ -9118,5 +9281,3 @@ int32_t lsm6dsm_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h index 22aa1fa..e69b39e 100644 --- a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h +++ b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -123,6 +122,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -2956,5 +2958,3 @@ int32_t lsm6dsm_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, #endif #endif /* LSM6DSM_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.c b/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.c index 9a784a1..35c994e 100644 --- a/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.c +++ b/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -202,7 +201,11 @@ int32_t lsm6dso16is_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); - *val = internal_freq_fine.freq_fine; + + if (ret == 0) + { + *val = internal_freq_fine.freq_fine; + } return ret; } @@ -243,6 +246,11 @@ int32_t lsm6dso16is_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + if (func_cfg_access.shub_reg_access == 1U) { *val = LSM6DSO16IS_SENSOR_HUB_MEM_BANK; @@ -300,6 +308,11 @@ int32_t lsm6dso16is_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1); + if (ret != 0) + { + return ret; + } + switch ((drdy_pulsed_reg.drdy_pulsed)) { case LSM6DSO16IS_DRDY_LATCHED: @@ -403,6 +416,12 @@ int32_t lsm6dso16is_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.boot; return ret; @@ -447,6 +466,11 @@ int32_t lsm6dso16is_xl_hm_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_ ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl6_c.xl_hm_mode)) { case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED: @@ -505,6 +529,11 @@ int32_t lsm6dso16is_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl1_xl.fs_xl)) { case LSM6DSO16IS_2g: @@ -582,6 +611,11 @@ int32_t lsm6dso16is_xl_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl6_c.xl_hm_mode << 4) | (ctrl1_xl.odr_xl)) { case LSM6DSO16IS_XL_ODR_OFF: @@ -719,6 +753,11 @@ int32_t lsm6dso16is_gy_hm_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_ ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl7_g.g_hm_mode)) { case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED: @@ -778,6 +817,11 @@ int32_t lsm6dso16is_gy_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl2_g.fs_125 << 4) | (ctrl2_g.fs_g)) { case LSM6DSO16IS_125dps: @@ -859,6 +903,11 @@ int32_t lsm6dso16is_gy_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl7_g.g_hm_mode << 4) | (ctrl2_g.odr_g)) { case LSM6DSO16IS_GY_ODR_OFF: @@ -992,6 +1041,11 @@ int32_t lsm6dso16is_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.if_inc; return ret; @@ -1036,6 +1090,11 @@ int32_t lsm6dso16is_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.bdu; return ret; @@ -1080,6 +1139,11 @@ int32_t lsm6dso16is_sleep_get(const stmdev_ctx_t *ctx, lsm6dso16is_sleep_t *val) ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl4_c.sleep_g)) { case LSM6DSO16IS_SLEEP_G_ENABLE: @@ -1138,6 +1202,11 @@ int32_t lsm6dso16is_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl5_c.st_xl)) { case LSM6DSO16IS_XL_ST_DISABLE: @@ -1200,6 +1269,11 @@ int32_t lsm6dso16is_gy_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl5_c.st_g)) { case LSM6DSO16IS_GY_ST_DISABLE: @@ -1266,6 +1340,11 @@ int32_t lsm6dso16is_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.sdo_pu_en; return ret; @@ -1310,6 +1389,11 @@ int32_t lsm6dso16is_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl3_c.sim)) { case LSM6DSO16IS_SPI_4_WIRE: @@ -1366,6 +1450,11 @@ int32_t lsm6dso16is_ui_i2c_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_ui_i2c_ ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl4_c.i2c_disable)) { case LSM6DSO16IS_I2C_ENABLE: @@ -1433,6 +1522,11 @@ int32_t lsm6dso16is_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl10_c.timestamp_en; return ret; @@ -1453,6 +1547,11 @@ int32_t lsm6dso16is_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_TIMESTAMP0, &buff[0], 4); + if (ret != 0) + { + return ret; + } + *val = (uint32_t)buff[3]; *val = (*val * 256U) + (uint32_t)buff[2]; *val = (*val * 256U) + (uint32_t)buff[1]; @@ -1547,6 +1646,12 @@ int32_t lsm6dso16is_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) + { + return ret; + } + *val = status_reg.xlda; return ret; @@ -1567,6 +1672,12 @@ int32_t lsm6dso16is_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) + { + return ret; + } + *val = status_reg.gda; return ret; @@ -1587,6 +1698,12 @@ int32_t lsm6dso16is_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, (uint8_t *)&status_reg, 1); + + if (ret != 0) + { + return ret; + } + *val = status_reg.tda; return ret; @@ -1606,6 +1723,12 @@ int32_t lsm6dso16is_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_OUT_TEMP_L, &buff[0], 2); + + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1626,6 +1749,12 @@ int32_t lsm6dso16is_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_OUTX_L_G, buff, 6); + + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1650,6 +1779,12 @@ int32_t lsm6dso16is_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_OUTX_L_A, buff, 6); + + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1845,6 +1980,11 @@ int32_t lsm6dso16is_int_pin_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl3_c.pp_od)) { case LSM6DSO16IS_PUSH_PULL: @@ -1903,6 +2043,11 @@ int32_t lsm6dso16is_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl3_c.h_lactive)) { case LSM6DSO16IS_ACTIVE_HIGH: @@ -1947,7 +2092,10 @@ int32_t lsm6dso16is_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); - ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SENSOR_HUB_1, val, len); + if (ret == 0) + { + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SENSOR_HUB_1, val, len); + } ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); return ret; @@ -2075,13 +2223,12 @@ int32_t lsm6dso16is_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) + + if (ret == 0) { - return ret; + *val = master_config.master_on; } - *val = master_config.master_on; - ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); return ret; @@ -2132,14 +2279,13 @@ int32_t lsm6dso16is_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) + + if (ret == 0) { - return ret; + *val = master_config.shub_pu_en; } - *val = master_config.shub_pu_en; - - ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); return ret; } @@ -2188,8 +2334,10 @@ int32_t lsm6dso16is_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - - *val = master_config.pass_through_mode; + if (ret == 0) + { + *val = master_config.pass_through_mode; + } ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); return ret; @@ -2379,13 +2527,12 @@ int32_t lsm6dso16is_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) + + if (ret == 0) { - return ret; + *val = master_config.rst_master_regs; } - *val = master_config.rst_master_regs; - ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); return ret; @@ -2411,7 +2558,7 @@ int32_t lsm6dso16is_sh_cfg_write(const stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } reg.slave0_add = val->slv0_add; @@ -2537,7 +2684,7 @@ int32_t lsm6dso16is_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } slv_add.slave0_add = val->slv_add; @@ -2641,6 +2788,11 @@ int32_t lsm6dso16is_ispu_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + *val = func_cfg_access.sw_reset_ispu; @@ -2672,6 +2824,11 @@ int32_t lsm6dso16is_ispu_clock_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl10_c.ispu_clk_sel) { default: @@ -2731,6 +2888,11 @@ int32_t lsm6dso16is_ispu_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl9_c.ispu_rate)) { case LSM6DSO16IS_ISPU_ODR_OFF: @@ -2823,6 +2985,11 @@ int32_t lsm6dso16is_ispu_bdu_get(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl9_c.ispu_rate)) { case LSM6DSO16IS_ISPU_BDU_OFF: @@ -2863,6 +3030,11 @@ int32_t lsm6dso16is_ia_ispu_get(const stmdev_ctx_t *ctx, uint32_t *val) ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT_STATUS0_MAINPAGE, &buff[0], 4); + if (ret != 0) + { + return ret; + } + *val = (uint32_t)buff[3]; *val = (*val * 256U) + (uint32_t)buff[2]; *val = (*val * 256U) + (uint32_t)buff[1]; @@ -2940,7 +3112,7 @@ int32_t lsm6dso16is_ispu_boot_set(const stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); @@ -2976,7 +3148,7 @@ int32_t lsm6dso16is_ispu_boot_get(const stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); @@ -3014,7 +3186,7 @@ int32_t lsm6dso16is_ispu_int_latched_set(const stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); @@ -3087,13 +3259,11 @@ int32_t lsm6dso16is_ispu_get_boot_status(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); - if (ret != 0) + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_STATUS, (uint8_t *)&ispu_boot_status, 1); + if (ret == 0) { - return ret; + *val = (lsm6dso16is_ispu_boot_end_t)ispu_boot_status.boot_end; } - - ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_STATUS, (uint8_t *)&ispu_boot_status, 1); - *val = (lsm6dso16is_ispu_boot_end_t)ispu_boot_status.boot_end; ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); return ret; @@ -3140,14 +3310,26 @@ int32_t lsm6dso16is_ispu_write_memory(const stmdev_ctx_t *ctx, { /* disable ISPU clock */ ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); + if (ret != 0) + { + goto exit; + } clk_dis = ispu_cfg.clk_dis; ispu_cfg.clk_dis = 1; - ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); + if (ret != 0) + { + goto exit; + } /* select memory to be written */ ispu_mem_sel.read_mem_en = 0; ispu_mem_sel.mem_sel = (uint8_t)mem_sel; - ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1); + if (ret != 0) + { + goto exit; + } if (mem_sel == LSM6DSO16IS_ISPU_PROGRAM_RAM_MEMORY) { @@ -3185,12 +3367,21 @@ int32_t lsm6dso16is_ispu_write_memory(const stmdev_ctx_t *ctx, ret += lsm6dso16is_ispu_sel_memory_addr(ctx, mem_addr); ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[0], len); } + if (ret != 0) + { + goto exit; + } /* set ISPU clock back to previous value */ ispu_cfg.clk_dis = clk_dis; ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); + if (ret != 0) + { + goto exit; + } } +exit: ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); return ret; @@ -3222,27 +3413,52 @@ int32_t lsm6dso16is_ispu_read_memory(const stmdev_ctx_t *ctx, { /* disable ISPU clock */ ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); + if (ret != 0) + { + goto exit; + } clk_dis = ispu_cfg.clk_dis; ispu_cfg.clk_dis = 1; ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); + if (ret != 0) + { + goto exit; + } /* select memory to be read */ ispu_mem_sel.read_mem_en = 1; ispu_mem_sel.mem_sel = (uint8_t)mem_sel; ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1); + if (ret != 0) + { + goto exit; + } /* select memory address */ ret += lsm6dso16is_ispu_sel_memory_addr(ctx, mem_addr); + if (ret != 0) + { + goto exit; + } /* read data */ ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &dummy, 1); + if (ret != 0) + { + goto exit; + } ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[0], len); + if (ret != 0) + { + goto exit; + } /* set ISPU clock back to previous value */ ispu_cfg.clk_dis = clk_dis; ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1); } +exit: ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); return ret; @@ -3293,10 +3509,11 @@ int32_t lsm6dso16is_ispu_read_flags(const stmdev_ctx_t *ctx, uint16_t *data) int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); + + /* read the flags */ + ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_S2IF_FLAG_L, buff, 2); if (ret == 0) { - /* read the flags */ - ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_S2IF_FLAG_L, buff, 2); data[0] = (uint16_t)buff[1]; data[0] = (data[0] * 256U) + (uint16_t)buff[0]; } @@ -3323,9 +3540,10 @@ int32_t lsm6dso16is_ispu_clear_flags(const stmdev_ctx_t *ctx) if (ret == 0) { ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_S2IF_FLAG_H, &data, 1); - ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); } + ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); + return ret; } @@ -3374,10 +3592,13 @@ int32_t lsm6dso16is_ispu_int1_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val) /* read int1_ctrl reg */ ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL0, &buff[0], 4); - *val = (uint32_t)buff[3]; - *val = (*val * 256U) + (uint32_t)buff[2]; - *val = (*val * 256U) + (uint32_t)buff[1]; - *val = (*val * 256U) + (uint32_t)buff[0]; + if (ret == 0) + { + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } } ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); @@ -3446,10 +3667,13 @@ int32_t lsm6dso16is_ispu_int2_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val) /* read int2_ctrl reg */ ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL0, &buff[0], 4); - *val = (uint32_t)buff[3]; - *val = (*val * 256U) + (uint32_t)buff[2]; - *val = (*val * 256U) + (uint32_t)buff[1]; - *val = (*val * 256U) + (uint32_t)buff[0]; + if (ret == 0) + { + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } } ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); @@ -3518,10 +3742,13 @@ int32_t lsm6dso16is_ispu_int_status_get(const stmdev_ctx_t *ctx, uint32_t *val) /* read int2_ctrl reg */ ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT_STATUS0, &buff[0], 4); - *val = (uint32_t)buff[3]; - *val = (*val * 256U) + (uint32_t)buff[2]; - *val = (*val * 256U) + (uint32_t)buff[1]; - *val = (*val * 256U) + (uint32_t)buff[0]; + if (ret == 0) + { + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } } ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); @@ -3548,10 +3775,13 @@ int32_t lsm6dso16is_ispu_algo_get(const stmdev_ctx_t *ctx, uint32_t *val) /* read int2_ctrl reg */ ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_ALGO0, &buff[0], 4); - *val = (uint32_t)buff[3]; - *val = (*val * 256U) + (uint32_t)buff[2]; - *val = (*val * 256U) + (uint32_t)buff[1]; - *val = (*val * 256U) + (uint32_t)buff[0]; + if (ret == 0) + { + *val = (uint32_t)buff[3]; + *val = (*val * 256U) + (uint32_t)buff[2]; + *val = (*val * 256U) + (uint32_t)buff[1]; + *val = (*val * 256U) + (uint32_t)buff[0]; + } } ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); diff --git a/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.h b/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.h index eee3406..47b12dd 100644 --- a/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.h +++ b/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -2803,5 +2805,3 @@ int32_t lsm6dso16is_ispu_algo_set(const stmdev_ctx_t *ctx, uint32_t val); #endif #endif /*LSM6DSO16IS_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c index 04e8fd9..b7ffde8 100644 --- a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c +++ b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -203,6 +202,8 @@ int32_t lsm6dso32_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.fs_xl) { case LSM6DSO32_4g: @@ -244,7 +245,6 @@ int32_t lsm6dso32_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32_ctrl1_xl_t ctrl1_xl; lsm6dso32_ctrl5_c_t ctrl5_c; lsm6dso32_ctrl6_c_t ctrl6_c; - lsm6dso32_func_cfg_access_t func_cfg_access; int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, @@ -257,12 +257,6 @@ int32_t lsm6dso32_xl_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)&ctrl1_xl, 1); } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS, - (uint8_t *)&func_cfg_access, 1); - } - if (ret == 0) { ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *) &ctrl5_c, 1); @@ -318,27 +312,14 @@ int32_t lsm6dso32_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32_ctrl1_xl_t ctrl1_xl; lsm6dso32_ctrl5_c_t ctrl5_c; lsm6dso32_ctrl6_c_t ctrl6_c; - lsm6dso32_func_cfg_access_t func_cfg_access; int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + ret += lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *) &ctrl5_c, 1); + ret += lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *) &ctrl6_c, 1); - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS, - (uint8_t *)&func_cfg_access, 1); - } - - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *) &ctrl5_c, 1); - } - - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *) &ctrl6_c, 1); - } + if (ret != 0) { return ret; } switch ((ctrl5_c.xl_ulp_en << 5) + (ctrl6_c.xl_hm_mode << 4) + ctrl1_xl.odr_xl) @@ -484,6 +465,8 @@ int32_t lsm6dso32_gy_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.fs_g) { case LSM6DSO32_250dps: @@ -578,11 +561,9 @@ int32_t lsm6dso32_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + ret += lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1); - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1); - } + if (ret != 0) { return ret; } switch ((ctrl7_g.g_hm_mode << 4) + ctrl2_g.odr_g) { @@ -698,6 +679,9 @@ int32_t lsm6dso32_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.bdu; return ret; @@ -746,6 +730,8 @@ int32_t lsm6dso32_xl_offset_weight_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.usr_off_w) { case LSM6DSO32_LSb_1mg: @@ -809,29 +795,26 @@ int32_t lsm6dso32_all_sources_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS, - (uint8_t *)&val->emb_func_status, 1); - } + if (ret == 0) + { + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS, + (uint8_t *)&val->emb_func_status, 1); + } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_STATUS_A, - (uint8_t *)&val->fsm_status_a, 1); - } + if (ret == 0) + { + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_STATUS_A, + (uint8_t *)&val->fsm_status_a, 1); + } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_STATUS_B, - (uint8_t *)&val->fsm_status_b, 1); - } + if (ret == 0) + { + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_STATUS_B, + (uint8_t *)&val->fsm_status_b, 1); + } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -870,6 +853,9 @@ int32_t lsm6dso32_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.xlda; return ret; @@ -890,6 +876,9 @@ int32_t lsm6dso32_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.gda; return ret; @@ -910,6 +899,9 @@ int32_t lsm6dso32_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tda; return ret; @@ -917,7 +909,7 @@ int32_t lsm6dso32_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, /** * @brief Accelerometer X-axis user offset correction expressed in - * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * two's complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * * @param ctx read / write interface definitions @@ -936,7 +928,7 @@ int32_t lsm6dso32_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -956,7 +948,7 @@ int32_t lsm6dso32_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -976,7 +968,7 @@ int32_t lsm6dso32_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -996,7 +988,7 @@ int32_t lsm6dso32_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1016,7 +1008,7 @@ int32_t lsm6dso32_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1073,6 +1065,9 @@ int32_t lsm6dso32_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.usr_off_on_out; return ret; @@ -1129,6 +1124,9 @@ int32_t lsm6dso32_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.timestamp_en; return ret; @@ -1150,6 +1148,9 @@ int32_t lsm6dso32_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TIMESTAMP0, buff, 4); + + if (ret != 0) { return ret; } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1212,6 +1213,8 @@ int32_t lsm6dso32_rounding_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.rounding) { case LSM6DSO32_NO_ROUND: @@ -1240,7 +1243,7 @@ int32_t lsm6dso32_rounding_mode_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). - * L and H registers together express a 16-bit word in two’s + * L and H registers together express a 16-bit word in two's * complement.[get] * * @param ctx read / write interface definitions @@ -1254,6 +1257,9 @@ int32_t lsm6dso32_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_OUT_TEMP_L, buff, 2); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1262,7 +1268,7 @@ int32_t lsm6dso32_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Angular rate sensor. The value is expressed as a 16-bit - * word in two’s complement.[get] + * word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -1276,6 +1282,9 @@ int32_t lsm6dso32_angular_rate_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_OUTX_L_G, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1288,7 +1297,7 @@ int32_t lsm6dso32_angular_rate_raw_get(const stmdev_ctx_t *ctx, /** * @brief Linear acceleration output register. - * The value is expressed as a 16-bit word in two’s complement.[get] + * The value is expressed as a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -1302,6 +1311,9 @@ int32_t lsm6dso32_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_OUTX_L_A, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1354,9 +1366,10 @@ int32_t lsm6dso32_number_of_steps_get(const stmdev_ctx_t *ctx, { *val = buff[1]; *val = (*val * 256U) + buff[0]; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + return ret; } @@ -1386,10 +1399,7 @@ int32_t lsm6dso32_steps_reset(const stmdev_ctx_t *ctx) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -1452,6 +1462,9 @@ int32_t lsm6dso32_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INTERNAL_FREQ_FINE, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.freq_fine; return ret; @@ -1504,6 +1517,8 @@ int32_t lsm6dso32_mem_bank_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.reg_access) { case LSM6DSO32_USER_BANK: @@ -1569,20 +1584,21 @@ int32_t lsm6dso32_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, /* set page write */ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - page_rw.page_rw = 0x02; /* page_write enable*/ - ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); if (ret != 0) { goto exit; } + page_rw.page_rw = 0x02; /* page_write enable*/ + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); /* select page */ - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); + ret += lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } page_sel.page_sel = msb; page_sel.not_used_01 = 1; - ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); if (ret != 0) { goto exit; } /* set page addr */ page_address.page_addr = lsb; - ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS, + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS, (uint8_t *)&page_address, 1); if (ret != 0) { goto exit; } @@ -1614,8 +1630,9 @@ int32_t lsm6dso32_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, /* unset page write */ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); + if (ret != 0) { goto exit; } page_rw.page_rw = 0x00; /* page_write disable */ - ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); exit: ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); @@ -1656,15 +1673,16 @@ int32_t lsm6dso32_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* set page write */ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - page_rw.page_rw = 0x01; /* page_read enable*/ - ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); if (ret != 0) { goto exit; } + page_rw.page_rw = 0x01; /* page_read enable*/ + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); /* select page */ - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); + ret += lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } page_sel.page_sel = msb; page_sel.not_used_01 = 1; - ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); if (ret != 0) { goto exit; } for (i = 0; ((i < len) && (ret == 0)); i++) @@ -1675,7 +1693,7 @@ int32_t lsm6dso32_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t (uint8_t *)&page_address, 1); if (ret != 0) { goto exit; } - ret += lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_VALUE, &buf[i], 1); + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_VALUE, &buf[i], 1); if (ret != 0) { goto exit; } lsb++; @@ -1684,12 +1702,12 @@ int32_t lsm6dso32_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) { msb++; - ret += lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *)&page_sel, 1); + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *)&page_sel, 1); if (ret != 0) { goto exit; } page_sel.page_sel = msb; page_sel.not_used_01 = 1; - ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *)&page_sel, 1); + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *)&page_sel, 1); if (ret != 0) { goto exit; } } } @@ -1701,8 +1719,9 @@ int32_t lsm6dso32_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* unset page write */ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); + if (ret != 0) { goto exit; } page_rw.page_rw = 0x00; /* page_write disable */ - ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); exit: ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); @@ -1757,6 +1776,8 @@ int32_t lsm6dso32_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.dataready_pulsed) { case LSM6DSO32_DRDY_LATCHED: @@ -1831,6 +1852,9 @@ int32_t lsm6dso32_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.sw_reset; return ret; @@ -1876,6 +1900,9 @@ int32_t lsm6dso32_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.if_inc; return ret; @@ -1919,6 +1946,9 @@ int32_t lsm6dso32_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.boot; return ret; @@ -1965,6 +1995,8 @@ int32_t lsm6dso32_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.st_xl) { case LSM6DSO32_XL_ST_DISABLE: @@ -2028,6 +2060,8 @@ int32_t lsm6dso32_gy_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.st_g) { case LSM6DSO32_GY_ST_DISABLE: @@ -2101,6 +2135,9 @@ int32_t lsm6dso32_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.lpf2_xl_en; return ret; @@ -2148,6 +2185,9 @@ int32_t lsm6dso32_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.lpf1_sel_g; return ret; @@ -2195,6 +2235,9 @@ int32_t lsm6dso32_filter_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.drdy_mask; return ret; @@ -2241,6 +2284,8 @@ int32_t lsm6dso32_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.ftype) { case LSM6DSO32_ULTRA_LIGHT: @@ -2321,6 +2366,9 @@ int32_t lsm6dso32_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.low_pass_on_6d; return ret; @@ -2372,6 +2420,8 @@ int32_t lsm6dso32_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) | reg.hpcf_xl) { @@ -2519,6 +2569,9 @@ int32_t lsm6dso32_xl_fast_settling_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.fastsettl_mode_xl; return ret; @@ -2567,6 +2620,8 @@ int32_t lsm6dso32_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.slope_fds) { case LSM6DSO32_USE_SLOPE: @@ -2629,6 +2684,8 @@ int32_t lsm6dso32_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch ((reg.hp_en_g << 7) + reg.hpm_g) { case LSM6DSO32_HP_FILTER_NONE: @@ -2714,6 +2771,8 @@ int32_t lsm6dso32_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.sdo_pu_en) { case LSM6DSO32_PULL_UP_DISC: @@ -2772,6 +2831,8 @@ int32_t lsm6dso32_spi_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.sim) { case LSM6DSO32_SPI_4_WIRE: @@ -2833,6 +2894,8 @@ int32_t lsm6dso32_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.i2c_disable) { case LSM6DSO32_I2C_ENABLE: @@ -2909,12 +2972,11 @@ int32_t lsm6dso32_i3c_disable_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + ret += lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); if (ret == 0) { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); - switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel) { case LSM6DSO32_I3C_DISABLE: @@ -2999,6 +3061,8 @@ int32_t lsm6dso32_int1_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.pd_dis_int1) { case LSM6DSO32_PULL_DOWN_DISC: @@ -3054,10 +3118,7 @@ int32_t lsm6dso32_pin_int1_route_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int1_b, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); if (ret == 0) { @@ -3190,10 +3251,7 @@ int32_t lsm6dso32_pin_int1_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int1_b, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); if (ret == 0) { @@ -3246,10 +3304,7 @@ int32_t lsm6dso32_pin_int2_route_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int2_b, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); if (ret == 0) { @@ -3382,10 +3437,7 @@ int32_t lsm6dso32_pin_int2_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int2_b, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); if (ret == 0) { @@ -3443,6 +3495,8 @@ int32_t lsm6dso32_pin_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.pp_od) { case LSM6DSO32_PUSH_PULL: @@ -3502,6 +3556,8 @@ int32_t lsm6dso32_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.h_lactive) { case LSM6DSO32_ACTIVE_HIGH: @@ -3558,6 +3614,9 @@ int32_t lsm6dso32_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.int2_on_int1; return ret; @@ -3592,23 +3651,20 @@ int32_t lsm6dso32_int_notification_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, + (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -3635,16 +3691,13 @@ int32_t lsm6dso32_int_notification_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } if (ret == 0) @@ -3671,18 +3724,6 @@ int32_t lsm6dso32_int_notification_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32_ALL_INT_PULSED; break; } - - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK); - } - - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -3748,6 +3789,8 @@ int32_t lsm6dso32_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.wake_ths_w) { case LSM6DSO32_LSb_FS_DIV_64: @@ -3806,6 +3849,9 @@ int32_t lsm6dso32_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.wk_ths; return ret; @@ -3853,6 +3899,9 @@ int32_t lsm6dso32_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.usr_off_on_wu; return ret; @@ -3898,6 +3947,9 @@ int32_t lsm6dso32_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.wake_dur; return ret; @@ -3954,6 +4006,9 @@ int32_t lsm6dso32_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.sleep_g; return ret; @@ -4006,6 +4061,8 @@ int32_t lsm6dso32_act_pin_notification_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.sleep_status_on_int) { case LSM6DSO32_DRIVE_SLEEP_CHG_EVENT: @@ -4065,6 +4122,8 @@ int32_t lsm6dso32_act_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.inact_en) { case LSM6DSO32_XL_AND_GY_NOT_AFFECTED: @@ -4131,6 +4190,9 @@ int32_t lsm6dso32_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.sleep_dur; return ret; @@ -4189,6 +4251,9 @@ int32_t lsm6dso32_tap_detection_on_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_z_en; return ret; @@ -4234,6 +4299,9 @@ int32_t lsm6dso32_tap_detection_on_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_y_en; return ret; @@ -4279,6 +4347,9 @@ int32_t lsm6dso32_tap_detection_on_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_x_en; return ret; @@ -4322,6 +4393,9 @@ int32_t lsm6dso32_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_ths_x; return ret; @@ -4368,6 +4442,8 @@ int32_t lsm6dso32_tap_axis_priority_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.tap_priority) { case LSM6DSO32_XYZ: @@ -4440,6 +4516,9 @@ int32_t lsm6dso32_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_ths_y; return ret; @@ -4483,6 +4562,9 @@ int32_t lsm6dso32_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_ths_z; return ret; @@ -4536,6 +4618,9 @@ int32_t lsm6dso32_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.shock; return ret; @@ -4591,6 +4676,9 @@ int32_t lsm6dso32_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.quiet; return ret; @@ -4648,6 +4736,9 @@ int32_t lsm6dso32_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.dur; return ret; @@ -4694,6 +4785,8 @@ int32_t lsm6dso32_tap_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.single_double_tap) { case LSM6DSO32_ONLY_SINGLE: @@ -4766,6 +4859,8 @@ int32_t lsm6dso32_6d_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.sixd_ths) { case LSM6DSO32_DEG_68: @@ -4822,6 +4917,9 @@ int32_t lsm6dso32_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.d4d_en; return ret; @@ -4881,6 +4979,8 @@ int32_t lsm6dso32_ff_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.ff_ths) { case LSM6DSO32_FF_TSH_312mg: @@ -4930,13 +5030,13 @@ int32_t lsm6dso32_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) if (ret == 0) { wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; - free_fall.ff_dur = (uint8_t)val & 0x1FU; ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); } if (ret == 0) { + free_fall.ff_dur = (uint8_t)val & 0x1FU; ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t *)&free_fall, 1); } @@ -4961,11 +5061,11 @@ int32_t lsm6dso32_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + ret += lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL, + (uint8_t *)&free_fall, 1); if (ret == 0) { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL, - (uint8_t *)&free_fall, 1); *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; } @@ -5004,13 +5104,13 @@ int32_t lsm6dso32_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) if (ret == 0) { fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val; - fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8); ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); } if (ret == 0) { + fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8); ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); } @@ -5034,11 +5134,11 @@ int32_t lsm6dso32_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + ret += lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm; } @@ -5075,10 +5175,7 @@ int32_t lsm6dso32_compression_algo_init_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -5109,9 +5206,10 @@ int32_t lsm6dso32_compression_algo_init_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.fifo_compr_init; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + return ret; } @@ -5146,10 +5244,7 @@ int32_t lsm6dso32_compression_algo_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); if (ret == 0) { @@ -5185,6 +5280,8 @@ int32_t lsm6dso32_compression_algo_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate) { case LSM6DSO32_CMP_DISABLE: @@ -5255,6 +5352,9 @@ int32_t lsm6dso32_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.odrchg_en; return ret; @@ -5301,6 +5401,9 @@ int32_t lsm6dso32_compression_algo_real_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_compr_rt_en; return ret; @@ -5347,6 +5450,9 @@ int32_t lsm6dso32_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.stop_on_wtm; return ret; @@ -5395,6 +5501,8 @@ int32_t lsm6dso32_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.bdr_xl) { case LSM6DSO32_XL_NOT_BATCHED: @@ -5496,6 +5604,8 @@ int32_t lsm6dso32_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.bdr_gy) { case LSM6DSO32_GY_NOT_BATCHED: @@ -5595,6 +5705,8 @@ int32_t lsm6dso32_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.fifo_mode) { case LSM6DSO32_BYPASS_MODE: @@ -5672,6 +5784,8 @@ int32_t lsm6dso32_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.odr_t_batch) { case LSM6DSO32_TEMP_NOT_BATCHED: @@ -5743,6 +5857,8 @@ int32_t lsm6dso32_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.odr_ts_batch) { case LSM6DSO32_NO_DECIMATION: @@ -5817,6 +5933,8 @@ int32_t lsm6dso32_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.trig_counter_bdr) { case LSM6DSO32_XL_BATCH_EVENT: @@ -5882,6 +6000,9 @@ int32_t lsm6dso32_rst_batch_counter_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.rst_counter_bdr; return ret; @@ -5908,7 +6029,6 @@ int32_t lsm6dso32_batch_counter_threshold_set(const stmdev_ctx_t *ctx, if (ret == 0) { - counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val; counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8; ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); @@ -5916,6 +6036,7 @@ int32_t lsm6dso32_batch_counter_threshold_set(const stmdev_ctx_t *ctx, if (ret == 0) { + counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val; ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); } @@ -5941,11 +6062,11 @@ int32_t lsm6dso32_batch_counter_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); if (ret == 0) { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8) + (uint16_t)counter_bdr_reg2.cnt_bdr_th; } @@ -5971,6 +6092,7 @@ int32_t lsm6dso32_fifo_data_level_get(const stmdev_ctx_t *ctx, /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS1, (uint8_t *)reg, 2); + if (ret == 0) { *val = fifo_status2->diff_fifo; @@ -5997,6 +6119,7 @@ int32_t lsm6dso32_fifo_status_get(const stmdev_ctx_t *ctx, /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS1, (uint8_t *)reg, 2); + if (ret == 0) { *val = *fifo_status2; @@ -6021,6 +6144,7 @@ int32_t lsm6dso32_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS1, (uint8_t *)reg, 2); + if (ret == 0) { *val = fifo_status2->fifo_full_ia; @@ -6046,6 +6170,7 @@ int32_t lsm6dso32_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS1, (uint8_t *)reg, 2); + if (ret == 0) { *val = fifo_status2->fifo_ovr_ia; @@ -6070,6 +6195,7 @@ int32_t lsm6dso32_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */ ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS1, (uint8_t *)reg, 2); + if (ret == 0) { *val = fifo_status2->fifo_wtm_ia; @@ -6095,6 +6221,8 @@ int32_t lsm6dso32_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_DATA_OUT_TAG, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.tag_sensor) { case LSM6DSO32_GYRO_NC_TAG: @@ -6211,10 +6339,7 @@ int32_t lsm6dso32_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -6241,10 +6366,11 @@ int32_t lsm6dso32_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.pedo_fifo_en; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -6277,10 +6403,7 @@ int32_t lsm6dso32_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -6307,10 +6430,11 @@ int32_t lsm6dso32_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.batch_ext_sens_0_en; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -6343,10 +6467,7 @@ int32_t lsm6dso32_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -6374,10 +6495,7 @@ int32_t lsm6dso32_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, *val = reg.batch_ext_sens_1_en; } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -6409,10 +6527,7 @@ int32_t lsm6dso32_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -6439,10 +6554,11 @@ int32_t lsm6dso32_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.batch_ext_sens_2_en; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -6475,10 +6591,7 @@ int32_t lsm6dso32_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -6505,10 +6618,11 @@ int32_t lsm6dso32_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.batch_ext_sens_3_en; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -6568,6 +6682,8 @@ int32_t lsm6dso32_den_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.den_mode) { case LSM6DSO32_DEN_DISABLE: @@ -6639,6 +6755,8 @@ int32_t lsm6dso32_den_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.den_lh) { case LSM6DSO32_DEN_ACT_LOW: @@ -6698,6 +6816,8 @@ int32_t lsm6dso32_den_enable_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.den_xl_g) { case LSM6DSO32_STAMP_IN_GY_DATA: @@ -6758,6 +6878,9 @@ int32_t lsm6dso32_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.den_z; return ret; @@ -6801,6 +6924,9 @@ int32_t lsm6dso32_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.den_y; return ret; @@ -6844,6 +6970,9 @@ int32_t lsm6dso32_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.den_x; return ret; @@ -6883,39 +7012,36 @@ int32_t lsm6dso32_pedo_sens_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A, - (uint8_t *)&emb_func_en_a, 1); - } + if (ret == 0) + { + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - emb_func_en_a.pedo_en = (uint8_t)val & 0x01U; - emb_func_en_b.pedo_adv_en = ((uint8_t)val & 0x02U) >> 1; - pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4; - pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5; - } + if (ret == 0) + { + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + emb_func_en_a.pedo_en = (uint8_t)val & 0x01U; + emb_func_en_b.pedo_adv_en = ((uint8_t)val & 0x02U) >> 1; + pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4; + pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5; + } - if (ret == 0) - { - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A, - (uint8_t *)&emb_func_en_a, 1); - } + if (ret == 0) + { + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + } - if (ret == 0) - { - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - } + if (ret == 0) + { + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } if (ret == 0) @@ -6949,25 +7075,24 @@ int32_t lsm6dso32_pedo_sens_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A, - (uint8_t *)&emb_func_en_a, 1); - } + if (ret == 0) + { + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - } + if (ret == 0) + { + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } + if (ret != 0) { return ret; } + switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en << 4) | (emb_func_en_b.pedo_adv_en << 1) | emb_func_en_a.pedo_en) @@ -7022,10 +7147,11 @@ int32_t lsm6dso32_pedo_step_detect_get(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.is_step_det; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -7113,11 +7239,11 @@ int32_t lsm6dso32_pedo_steps_period_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_L, &buff[0]); + ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_H, + &buff[1]); if (ret == 0) { - ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_H, - &buff[1]); *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -7171,6 +7297,8 @@ int32_t lsm6dso32_pedo_int_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG, (uint8_t *)®); + if (ret != 0) { return ret; } + switch (reg.carry_count_en) { case LSM6DSO32_EVERY_STEP: @@ -7230,10 +7358,7 @@ int32_t lsm6dso32_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -7259,10 +7384,11 @@ int32_t lsm6dso32_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.sign_motion_en; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -7290,10 +7416,11 @@ int32_t lsm6dso32_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.is_sigmot; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -7340,10 +7467,7 @@ int32_t lsm6dso32_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -7369,10 +7493,11 @@ int32_t lsm6dso32_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.tilt_en; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -7400,10 +7525,11 @@ int32_t lsm6dso32_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.is_tilt; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -7465,11 +7591,11 @@ int32_t lsm6dso32_mag_sensitivity_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_L, &buff[0]); + ret += lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_H, + &buff[1]); if (ret == 0) { - ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_H, - &buff[1]); *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -7576,6 +7702,10 @@ int32_t lsm6dso32_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFZ_H, &buff[5]); + } + + if (ret == 0) + { val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -7805,18 +7935,21 @@ int32_t lsm6dso32_mag_soft_iron_get(const stmdev_ctx_t *ctx, int16_t *val) &buff[index]); } - val[0] = (int16_t)buff[1]; - val[0] = (val[0] * 256) + (int16_t)buff[0]; - val[1] = (int16_t)buff[3]; - val[1] = (val[1] * 256) + (int16_t)buff[2]; - val[2] = (int16_t)buff[5]; - val[2] = (val[2] * 256) + (int16_t)buff[4]; - val[3] = (int16_t)buff[7]; - val[3] = (val[3] * 256) + (int16_t)buff[6]; - val[4] = (int16_t)buff[9]; - val[4] = (val[4] * 256) + (int16_t)buff[8]; - val[5] = (int16_t)buff[11]; - val[5] = (val[5] * 256) + (int16_t)buff[10]; + if (ret == 0) + { + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + val[3] = (int16_t)buff[7]; + val[3] = (val[3] * 256) + (int16_t)buff[6]; + val[4] = (int16_t)buff[9]; + val[4] = (val[4] * 256) + (int16_t)buff[8]; + val[5] = (int16_t)buff[11]; + val[5] = (val[5] * 256) + (int16_t)buff[10]; + } return ret; } @@ -7871,6 +8004,8 @@ int32_t lsm6dso32_mag_z_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A, (uint8_t *)®); + if (ret != 0) { return ret; } + switch (reg.mag_z_axis) { case LSM6DSO32_Z_EQ_Y: @@ -7955,6 +8090,8 @@ int32_t lsm6dso32_mag_y_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A, (uint8_t *)®); + if (ret != 0) { return ret; } + switch (reg.mag_y_axis) { case LSM6DSO32_Y_EQ_Y: @@ -8039,6 +8176,8 @@ int32_t lsm6dso32_mag_x_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_B, (uint8_t *)®); + if (ret != 0) { return ret; } + switch (reg.mag_x_axis) { case LSM6DSO32_X_EQ_Y: @@ -8109,10 +8248,11 @@ int32_t lsm6dso32_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.is_fsm_lc; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -8146,10 +8286,7 @@ int32_t lsm6dso32_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -8182,10 +8319,7 @@ int32_t lsm6dso32_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -8256,10 +8390,7 @@ int32_t lsm6dso32_fsm_enable_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -8285,10 +8416,7 @@ int32_t lsm6dso32_fsm_enable_get(const stmdev_ctx_t *ctx, 2); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -8316,10 +8444,7 @@ int32_t lsm6dso32_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_L, buff, 2); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -8345,9 +8470,10 @@ int32_t lsm6dso32_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_L, buff, 2); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -8385,10 +8511,7 @@ int32_t lsm6dso32_long_clr_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -8416,6 +8539,8 @@ int32_t lsm6dso32_long_clr_get(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { switch (reg.fsm_lc_clr) @@ -8438,11 +8563,6 @@ int32_t lsm6dso32_long_clr_get(const stmdev_ctx_t *ctx, } } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } - return ret; } @@ -8467,10 +8587,7 @@ int32_t lsm6dso32_fsm_out_get(const stmdev_ctx_t *ctx, 16); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -8506,10 +8623,7 @@ int32_t lsm6dso32_fsm_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -8536,6 +8650,8 @@ int32_t lsm6dso32_fsm_data_rate_get(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { switch (reg.fsm_odr) @@ -8560,8 +8676,6 @@ int32_t lsm6dso32_fsm_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32_ODR_FSM_12Hz5; break; } - - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -8595,10 +8709,7 @@ int32_t lsm6dso32_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -8624,10 +8735,11 @@ int32_t lsm6dso32_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.fsm_init; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -8683,11 +8795,11 @@ int32_t lsm6dso32_long_cnt_int_value_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_L, &buff[0]); + ret += lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_H, + &buff[1]); if (ret == 0) { - ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_H, - &buff[1]); *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -8753,7 +8865,6 @@ int32_t lsm6dso32_fsm_start_address_set(const stmdev_ctx_t *ctx, if (ret == 0) { - ; ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_START_ADD_H, &buff[1]); } @@ -8778,11 +8889,11 @@ int32_t lsm6dso32_fsm_start_address_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_START_ADD_L, &buff[0]); + ret += lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_START_ADD_H, + &buff[1]); if (ret == 0) { - ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_START_ADD_H, - &buff[1]); *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -8824,10 +8935,7 @@ int32_t lsm6dso32_sh_read_data_raw_get(const stmdev_ctx_t *ctx, (uint8_t *) val, 18U); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -8861,10 +8969,7 @@ int32_t lsm6dso32_sh_slave_connected_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -8891,6 +8996,8 @@ int32_t lsm6dso32_sh_slave_connected_get(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { switch (reg.aux_sens_on) @@ -8915,8 +9022,6 @@ int32_t lsm6dso32_sh_slave_connected_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32_SLV_0; break; } - - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -8950,10 +9055,7 @@ int32_t lsm6dso32_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -8979,10 +9081,11 @@ int32_t lsm6dso32_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.master_on; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -9017,10 +9120,7 @@ int32_t lsm6dso32_sh_pin_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -9047,6 +9147,8 @@ int32_t lsm6dso32_sh_pin_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { switch (reg.shub_pu_en) @@ -9063,8 +9165,6 @@ int32_t lsm6dso32_sh_pin_mode_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32_EXT_PULL_UP; break; } - - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -9099,10 +9199,7 @@ int32_t lsm6dso32_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -9129,10 +9226,11 @@ int32_t lsm6dso32_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.pass_through_mode; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -9167,10 +9265,7 @@ int32_t lsm6dso32_sh_syncro_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -9197,6 +9292,8 @@ int32_t lsm6dso32_sh_syncro_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { switch (reg.start_config) @@ -9213,8 +9310,6 @@ int32_t lsm6dso32_sh_syncro_mode_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32_EXT_ON_INT2_PIN; break; } - - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -9250,10 +9345,7 @@ int32_t lsm6dso32_sh_write_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -9281,6 +9373,8 @@ int32_t lsm6dso32_sh_write_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { switch (reg.write_once) @@ -9297,8 +9391,6 @@ int32_t lsm6dso32_sh_write_mode_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32_EACH_SH_CYCLE; break; } - - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -9338,10 +9430,7 @@ int32_t lsm6dso32_sh_reset_set(const stmdev_ctx_t *ctx) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -9367,10 +9456,11 @@ int32_t lsm6dso32_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { *val = reg.rst_master_regs; - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -9403,10 +9493,7 @@ int32_t lsm6dso32_sh_data_rate_set(const stmdev_ctx_t *ctx, ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -9432,6 +9519,8 @@ int32_t lsm6dso32_sh_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1); } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); + if (ret == 0) { switch (reg.shub_odr) @@ -9456,8 +9545,6 @@ int32_t lsm6dso32_sh_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32_SH_ODR_104Hz; break; } - - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); } return ret; @@ -9501,10 +9588,7 @@ int32_t lsm6dso32_sh_cfg_write(const stmdev_ctx_t *ctx, &(val->slv0_data), 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -9556,10 +9640,7 @@ int32_t lsm6dso32_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -9611,10 +9692,7 @@ int32_t lsm6dso32_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -9666,10 +9744,7 @@ int32_t lsm6dso32_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -9721,10 +9796,7 @@ int32_t lsm6dso32_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -9750,10 +9822,7 @@ int32_t lsm6dso32_sh_status_get(const stmdev_ctx_t *ctx, (uint8_t *) val, 1); } - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -9767,5 +9836,3 @@ int32_t lsm6dso32_sh_status_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h index 80e314d..83a9440 100644 --- a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h +++ b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -3800,5 +3802,3 @@ int32_t lsm6dso32_sh_status_get(const stmdev_ctx_t *ctx, #endif #endif /*LSM6DSO32_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c index 6e2264e..3088f45 100644 --- a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c +++ b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -226,6 +225,8 @@ int32_t lsm6dso32x_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.fs_xl) { case LSM6DSO32X_16g: @@ -522,6 +523,8 @@ int32_t lsm6dso32x_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.odr_xl) { case LSM6DSO32X_XL_ODR_OFF: @@ -619,6 +622,8 @@ int32_t lsm6dso32x_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.fs_g) { case LSM6DSO32X_250dps: @@ -919,6 +924,8 @@ int32_t lsm6dso32x_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.odr_g) { case LSM6DSO32X_GY_ODR_OFF: @@ -1011,6 +1018,9 @@ int32_t lsm6dso32x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.bdu; return ret; @@ -1059,6 +1069,8 @@ int32_t lsm6dso32x_xl_offset_weight_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.usr_off_w) { case LSM6DSO32X_LSb_1mg: @@ -1136,12 +1148,11 @@ int32_t lsm6dso32x_xl_power_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *) &ctrl5_c, 1); + ret += lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, + (uint8_t *) &ctrl6_c, 1); if (ret == 0) { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, - (uint8_t *) &ctrl6_c, 1); - switch ((ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode) { case LSM6DSO32X_HIGH_PERFORMANCE_MD: @@ -1206,6 +1217,8 @@ int32_t lsm6dso32x_gy_power_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.g_hm_mode) { case LSM6DSO32X_GY_HIGH_PERFORMANCE: @@ -1256,6 +1269,9 @@ int32_t lsm6dso32x_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.xlda; return ret; @@ -1275,6 +1291,9 @@ int32_t lsm6dso32x_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.gda; return ret; @@ -1294,6 +1313,9 @@ int32_t lsm6dso32x_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *va int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tda; return ret; @@ -1301,7 +1323,7 @@ int32_t lsm6dso32x_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *va /** * @brief Accelerometer X-axis user offset correction expressed in - * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * two's complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * * @param ctx read / write interface definitions @@ -1319,7 +1341,7 @@ int32_t lsm6dso32x_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1338,7 +1360,7 @@ int32_t lsm6dso32x_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1357,7 +1379,7 @@ int32_t lsm6dso32x_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1376,7 +1398,7 @@ int32_t lsm6dso32x_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1395,7 +1417,7 @@ int32_t lsm6dso32x_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1451,6 +1473,9 @@ int32_t lsm6dso32x_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.usr_off_on_out; return ret; @@ -1521,6 +1546,9 @@ int32_t lsm6dso32x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL10_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.timestamp_en; return ret; @@ -1542,6 +1570,9 @@ int32_t lsm6dso32x_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TIMESTAMP0, buff, 4); + + if (ret != 0) { return ret; } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1604,6 +1635,8 @@ int32_t lsm6dso32x_rounding_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.rounding) { case LSM6DSO32X_NO_ROUND: @@ -1632,7 +1665,7 @@ int32_t lsm6dso32x_rounding_mode_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). - * L and H registers together express a 16-bit word in two’s + * L and H registers together express a 16-bit word in two's * complement.[get] * * @param ctx read / write interface definitions @@ -1647,6 +1680,9 @@ int32_t lsm6dso32x_temperature_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUT_TEMP_L, buff, 2); + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1655,7 +1691,7 @@ int32_t lsm6dso32x_temperature_raw_get(const stmdev_ctx_t *ctx, /** * @brief Angular rate sensor. The value is expressed as a 16-bit - * word in two’s complement.[get] + * word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -1669,6 +1705,9 @@ int32_t lsm6dso32x_angular_rate_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUTX_L_G, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1681,7 +1720,7 @@ int32_t lsm6dso32x_angular_rate_raw_get(const stmdev_ctx_t *ctx, /** * @brief Linear acceleration output register. - * The value is expressed as a 16-bit word in two’s complement.[get] + * The value is expressed as a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -1695,6 +1734,9 @@ int32_t lsm6dso32x_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUTX_L_A, buff, 6); + + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1741,15 +1783,16 @@ int32_t lsm6dso32x_number_of_steps_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STEP_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; - } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -1780,10 +1823,7 @@ int32_t lsm6dso32x_steps_reset(const stmdev_ctx_t *ctx) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -1807,10 +1847,7 @@ int32_t lsm6dso32x_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC0_SRC, buff, 8); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -1873,6 +1910,9 @@ int32_t lsm6dso32x_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INTERNAL_FREQ_FINE, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.freq_fine; return ret; @@ -1927,6 +1967,8 @@ int32_t lsm6dso32x_mem_bank_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.reg_access) { case LSM6DSO32X_USER_BANK: @@ -2021,10 +2063,7 @@ int32_t lsm6dso32x_ln_pg_write_byte(const stmdev_ctx_t *ctx, (uint8_t *) &page_rw, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -2052,88 +2091,71 @@ int32_t lsm6dso32x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, msb = ((uint8_t)(address >> 8) & 0x0FU); lsb = (uint8_t)address & 0xFFU; ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK); + if (ret != 0) { goto exit; } + + /* page write */ + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x02; /* page_write enable*/ + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); + + /* set page num */ + ret += lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL, + (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL, + (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x02; /* page_write enable*/ - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } - - if (ret == 0) - { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } + /* set page addr */ + page_address.page_addr = lsb; + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { goto exit; } - if (ret == 0) + for (i = 0; ((i < len) && (ret == 0)); i++) { - page_address.page_addr = lsb; - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } + /* write value */ + ret += lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_VALUE, &buf[i], 1); + lsb++; - if (ret == 0) - { - for (i = 0; ((i < len) && (ret == 0)); i++) + /* Check if page wrap */ + if ((lsb == 0x00U) && (ret == 0)) { - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_VALUE, &buf[i], 1); - lsb++; + msb++; + ret += lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } - /* Check if page wrap */ - if ((lsb == 0x00U) && (ret == 0)) - { - msb++; - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL, - (uint8_t *)&page_sel, 1); - if (ret == 0) - { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - } + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; // Default value + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } } } page_sel.page_sel = 0; - page_sel.not_used_01 = 1; + page_sel.not_used_01 = 1; // Default value ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL, (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + page_rw.page_rw = 0x00; /* page_write disable */ + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } +exit: + ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -2157,63 +2179,46 @@ int32_t lsm6dso32x_ln_pg_read_byte(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK); + if (ret != 0) { goto exit; } + + /* page read */ + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x01; /* page_read enable*/ + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); + + /* set page num */ + ret += lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL, + (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } + page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); + page_sel.not_used_01 = 1; // Default value + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL, + (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x01; /* page_read enable*/ - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } - - if (ret == 0) - { - page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); - page_sel.not_used_01 = 1; - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } - - if (ret == 0) - { - page_address.page_addr = (uint8_t)address & 0x00FFU; - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_VALUE, val, 1); - } + /* set page address */ + page_address.page_addr = (uint8_t)address & 0x00FFU; + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + /* read value */ + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_VALUE, val, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_read disable */ - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + /* unset page rw */ + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x00; /* page_read disable */ + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } +exit: + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -2266,6 +2271,8 @@ int32_t lsm6dso32x_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.dataready_pulsed) { case LSM6DSO32X_DRDY_LATCHED: @@ -2340,6 +2347,9 @@ int32_t lsm6dso32x_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.sw_reset; return ret; @@ -2385,6 +2395,9 @@ int32_t lsm6dso32x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.if_inc; return ret; @@ -2428,6 +2441,9 @@ int32_t lsm6dso32x_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.boot; return ret; @@ -2474,6 +2490,8 @@ int32_t lsm6dso32x_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.st_xl) { case LSM6DSO32X_XL_ST_DISABLE: @@ -2537,6 +2555,8 @@ int32_t lsm6dso32x_gy_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.st_g) { case LSM6DSO32X_GY_ST_DISABLE: @@ -2610,6 +2630,9 @@ int32_t lsm6dso32x_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.lpf2_xl_en; return ret; @@ -2657,6 +2680,9 @@ int32_t lsm6dso32x_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.lpf1_sel_g; return ret; @@ -2704,6 +2730,9 @@ int32_t lsm6dso32x_filter_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.drdy_mask; return ret; @@ -2750,6 +2779,8 @@ int32_t lsm6dso32x_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.ftype) { case LSM6DSO32X_ULTRA_LIGHT: @@ -2830,6 +2861,9 @@ int32_t lsm6dso32x_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.low_pass_on_6d; return ret; @@ -2882,6 +2916,8 @@ int32_t lsm6dso32x_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) | reg.hpcf_xl) { @@ -3030,6 +3066,9 @@ int32_t lsm6dso32x_xl_fast_settling_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.fastsettl_mode_xl; return ret; @@ -3078,6 +3117,8 @@ int32_t lsm6dso32x_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.slope_fds) { case LSM6DSO32X_USE_SLOPE: @@ -3142,6 +3183,8 @@ int32_t lsm6dso32x_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch ((reg.hp_en_g << 7) + reg.hpm_g) { case LSM6DSO32X_HP_FILTER_NONE: @@ -3227,6 +3270,8 @@ int32_t lsm6dso32x_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.sdo_pu_en) { case LSM6DSO32X_PULL_UP_DISC: @@ -3286,6 +3331,8 @@ int32_t lsm6dso32x_spi_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.sim) { case LSM6DSO32X_SPI_4_WIRE: @@ -3347,6 +3394,8 @@ int32_t lsm6dso32x_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.i2c_disable) { case LSM6DSO32X_I2C_ENABLE: @@ -3425,12 +3474,11 @@ int32_t lsm6dso32x_i3c_disable_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + ret += lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); if (ret == 0) { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); - switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel) { case LSM6DSO32X_I3C_DISABLE: @@ -3532,12 +3580,10 @@ int32_t lsm6dso32x_pin_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + ret += lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); - } + if (ret != 0) { return ret; } switch ((i3c_bus_avb.pd_dis_int1 << 1) + ctrl3_c.pp_od) { @@ -3606,6 +3652,8 @@ int32_t lsm6dso32x_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.h_lactive) { case LSM6DSO32X_ACTIVE_HIGH: @@ -3662,6 +3710,9 @@ int32_t lsm6dso32x_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.int2_on_int1; return ret; @@ -3696,24 +3747,21 @@ int32_t lsm6dso32x_int_notification_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } return ret; @@ -3740,17 +3788,14 @@ int32_t lsm6dso32x_int_notification_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } if (ret == 0) @@ -3777,19 +3822,6 @@ int32_t lsm6dso32x_int_notification_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32X_ALL_INT_PULSED; break; } - - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK); - } - - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } return ret; @@ -3858,6 +3890,8 @@ int32_t lsm6dso32x_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.wake_ths_w) { case LSM6DSO32X_LSb_FS_DIV_64: @@ -3919,6 +3953,9 @@ int32_t lsm6dso32x_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.wk_ths; return ret; @@ -3969,6 +4006,9 @@ int32_t lsm6dso32x_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.usr_off_on_wu; return ret; @@ -4017,6 +4057,9 @@ int32_t lsm6dso32x_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.wake_dur; return ret; @@ -4073,6 +4116,9 @@ int32_t lsm6dso32x_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.sleep_g; return ret; @@ -4125,6 +4171,8 @@ int32_t lsm6dso32x_act_pin_notification_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.sleep_status_on_int) { case LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT: @@ -4184,6 +4232,8 @@ int32_t lsm6dso32x_act_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.inact_en) { case LSM6DSO32X_XL_AND_GY_NOT_AFFECTED: @@ -4253,6 +4303,9 @@ int32_t lsm6dso32x_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.sleep_dur; return ret; @@ -4311,6 +4364,9 @@ int32_t lsm6dso32x_tap_detection_on_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_z_en; return ret; @@ -4356,6 +4412,9 @@ int32_t lsm6dso32x_tap_detection_on_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_y_en; return ret; @@ -4401,6 +4460,9 @@ int32_t lsm6dso32x_tap_detection_on_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_x_en; return ret; @@ -4445,6 +4507,9 @@ int32_t lsm6dso32x_tap_threshold_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_ths_x; return ret; @@ -4493,6 +4558,8 @@ int32_t lsm6dso32x_tap_axis_priority_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.tap_priority) { case LSM6DSO32X_XYZ: @@ -4566,6 +4633,9 @@ int32_t lsm6dso32x_tap_threshold_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_ths_y; return ret; @@ -4611,6 +4681,9 @@ int32_t lsm6dso32x_tap_threshold_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.tap_ths_z; return ret; @@ -4664,6 +4737,9 @@ int32_t lsm6dso32x_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.shock; return ret; @@ -4719,6 +4795,9 @@ int32_t lsm6dso32x_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.quiet; return ret; @@ -4776,6 +4855,9 @@ int32_t lsm6dso32x_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.dur; return ret; @@ -4825,6 +4907,8 @@ int32_t lsm6dso32x_tap_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.single_double_tap) { case LSM6DSO32X_ONLY_SINGLE: @@ -4898,6 +4982,8 @@ int32_t lsm6dso32x_6d_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.sixd_ths) { case LSM6DSO32X_DEG_80: @@ -4963,6 +5049,9 @@ int32_t lsm6dso32x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.d4d_en; return ret; @@ -5021,6 +5110,8 @@ int32_t lsm6dso32x_ff_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.ff_ths) { case LSM6DSO32X_FF_TSH_312mg: @@ -5101,11 +5192,11 @@ int32_t lsm6dso32x_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + ret += lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL, + (uint8_t *)&free_fall, 1); if (ret == 0) { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL, - (uint8_t *)&free_fall, 1); *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; } @@ -5175,11 +5266,11 @@ int32_t lsm6dso32x_fifo_watermark_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + ret += lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm; } @@ -5216,10 +5307,7 @@ int32_t lsm6dso32x_compression_algo_init_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -5250,9 +5338,10 @@ int32_t lsm6dso32x_compression_algo_init_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.fifo_compr_init; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -5302,6 +5391,8 @@ int32_t lsm6dso32x_compression_algo_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate) { case LSM6DSO32X_CMP_DISABLE: @@ -5373,6 +5464,9 @@ int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.odrchg_en; return ret; @@ -5420,6 +5514,9 @@ int32_t lsm6dso32x_compression_algo_real_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.fifo_compr_rt_en; return ret; @@ -5468,6 +5565,9 @@ int32_t lsm6dso32x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.stop_on_wtm; return ret; @@ -5517,6 +5617,8 @@ int32_t lsm6dso32x_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.bdr_xl) { case LSM6DSO32X_XL_NOT_BATCHED: @@ -5619,6 +5721,8 @@ int32_t lsm6dso32x_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.bdr_gy) { case LSM6DSO32X_GY_NOT_BATCHED: @@ -5719,6 +5823,8 @@ int32_t lsm6dso32x_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.fifo_mode) { case LSM6DSO32X_BYPASS_MODE: @@ -5797,6 +5903,8 @@ int32_t lsm6dso32x_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.odr_t_batch) { case LSM6DSO32X_TEMP_NOT_BATCHED: @@ -5869,6 +5977,8 @@ int32_t lsm6dso32x_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.odr_ts_batch) { case LSM6DSO32X_NO_DECIMATION: @@ -5943,6 +6053,8 @@ int32_t lsm6dso32x_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.trig_counter_bdr) { case LSM6DSO32X_XL_BATCH_EVENT: @@ -6008,6 +6120,9 @@ int32_t lsm6dso32x_rst_batch_counter_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.rst_counter_bdr; return ret; @@ -6067,11 +6182,11 @@ int32_t lsm6dso32x_batch_counter_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); if (ret == 0) { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8) + (uint16_t)counter_bdr_reg2.cnt_bdr_th; } @@ -6221,6 +6336,8 @@ int32_t lsm6dso32x_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_DATA_OUT_TAG, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.tag_sensor) { case LSM6DSO32X_GYRO_NC_TAG: @@ -6349,10 +6466,7 @@ int32_t lsm6dso32x_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -6383,9 +6497,10 @@ int32_t lsm6dso32x_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.pedo_fifo_en; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -6419,10 +6534,7 @@ int32_t lsm6dso32x_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -6453,9 +6565,10 @@ int32_t lsm6dso32x_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.batch_ext_sens_0_en; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -6489,10 +6602,7 @@ int32_t lsm6dso32x_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -6518,14 +6628,15 @@ int32_t lsm6dso32x_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, { ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV1_CONFIG, (uint8_t *)®, 1); - *val = reg.batch_ext_sens_1_en; } if (ret == 0) { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + *val = reg.batch_ext_sens_1_en; } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -6559,10 +6670,7 @@ int32_t lsm6dso32x_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -6593,9 +6701,10 @@ int32_t lsm6dso32x_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.batch_ext_sens_2_en; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -6629,10 +6738,7 @@ int32_t lsm6dso32x_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -6663,9 +6769,10 @@ int32_t lsm6dso32x_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.batch_ext_sens_3_en; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -6723,6 +6830,8 @@ int32_t lsm6dso32x_den_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.den_mode) { case LSM6DSO32X_DEN_DISABLE: @@ -6794,6 +6903,8 @@ int32_t lsm6dso32x_den_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.den_lh) { case LSM6DSO32X_DEN_ACT_LOW: @@ -6853,6 +6964,8 @@ int32_t lsm6dso32x_den_enable_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.den_xl_g) { case LSM6DSO32X_STAMP_IN_GY_DATA: @@ -6914,6 +7027,9 @@ int32_t lsm6dso32x_den_mark_axis_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.den_z; return ret; @@ -6958,6 +7074,9 @@ int32_t lsm6dso32x_den_mark_axis_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.den_y; return ret; @@ -7002,6 +7121,9 @@ int32_t lsm6dso32x_den_mark_axis_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1); + + if (ret != 0) { return ret; } + *val = reg.den_x; return ret; @@ -7064,6 +7186,8 @@ int32_t lsm6dso32x_pedo_sens_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg); + if (ret != 0) { return ret; } + switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en << 4)) { @@ -7112,9 +7236,10 @@ int32_t lsm6dso32x_pedo_step_detect_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.is_step_det; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -7200,11 +7325,11 @@ int32_t lsm6dso32x_pedo_steps_period_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_L, &buff[0]); + ret += lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_H, + &buff[1]); if (ret == 0) { - ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_H, - &buff[1]); *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -7258,6 +7383,8 @@ int32_t lsm6dso32x_pedo_int_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG, (uint8_t *)®); + if (ret != 0) { return ret; } + switch (reg.carry_count_en) { case LSM6DSO32X_EVERY_STEP: @@ -7314,9 +7441,10 @@ int32_t lsm6dso32x_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.is_sigmot; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -7358,9 +7486,10 @@ int32_t lsm6dso32x_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.is_tilt; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -7423,11 +7552,11 @@ int32_t lsm6dso32x_sh_mag_sensitivity_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_L, &buff[0]); + ret += lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_H, + &buff[1]); if (ret == 0) { - ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_H, - &buff[1]); *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -7484,12 +7613,12 @@ int32_t lsm6dso32x_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MLC_MAG_SENSITIVITY_L, &buff[0]); + ret += lsm6dso32x_ln_pg_read_byte(ctx, + LSM6DSO32X_MLC_MAG_SENSITIVITY_H, + &buff[1]); if (ret == 0) { - ret = lsm6dso32x_ln_pg_read_byte(ctx, - LSM6DSO32X_MLC_MAG_SENSITIVITY_H, - &buff[1]); *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -7613,12 +7742,15 @@ int32_t lsm6dso32x_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) &buff[i]); } - val[0] = (int16_t)buff[1]; - val[0] = (val[0] * 256) + (int16_t)buff[0]; - val[1] = (int16_t)buff[3]; - val[1] = (val[1] * 256) + (int16_t)buff[2]; - val[2] = (int16_t)buff[5]; - val[2] = (val[2] * 256) + (int16_t)buff[4]; + if (ret == 0) + { + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + } return ret; } @@ -7841,18 +7973,21 @@ int32_t lsm6dso32x_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) &buff[index]); } - val[0] = buff[1]; - val[0] = (val[0] * 256U) + buff[0]; - val[1] = buff[3]; - val[1] = (val[1] * 256U) + buff[2]; - val[2] = buff[5]; - val[2] = (val[2] * 256U) + buff[4]; - val[3] = buff[7]; - val[3] = (val[3] * 256U) + buff[6]; - val[4] = buff[9]; - val[4] = (val[4] * 256U) + buff[8]; - val[5] = buff[11]; - val[6] = (val[5] * 256U) + buff[10]; + if (ret == 0) + { + val[0] = buff[1]; + val[0] = (val[0] * 256U) + buff[0]; + val[1] = buff[3]; + val[1] = (val[1] * 256U) + buff[2]; + val[2] = buff[5]; + val[2] = (val[2] * 256U) + buff[4]; + val[3] = buff[7]; + val[3] = (val[3] * 256U) + buff[6]; + val[4] = buff[9]; + val[4] = (val[4] * 256U) + buff[8]; + val[5] = buff[11]; + val[6] = (val[5] * 256U) + buff[10]; + } return ret; } @@ -7907,6 +8042,8 @@ int32_t lsm6dso32x_mag_z_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A, (uint8_t *)®); + if (ret != 0) { return ret; } + switch (reg.mag_z_axis) { case LSM6DSO32X_Z_EQ_Y: @@ -7991,6 +8128,8 @@ int32_t lsm6dso32x_mag_y_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A, (uint8_t *)®); + if (ret != 0) { return ret; } + switch (reg.mag_y_axis) { case LSM6DSO32X_Y_EQ_Y: @@ -8075,6 +8214,8 @@ int32_t lsm6dso32x_mag_x_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_B, (uint8_t *)®); + if (ret != 0) { return ret; } + switch (reg.mag_x_axis) { case LSM6DSO32X_X_EQ_Y: @@ -8148,9 +8289,10 @@ int32_t lsm6dso32x_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.is_fsm_lc; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -8181,10 +8323,7 @@ int32_t lsm6dso32x_fsm_enable_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_enable_b, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -8211,10 +8350,7 @@ int32_t lsm6dso32x_fsm_enable_get(const stmdev_ctx_t *ctx, 2); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -8243,10 +8379,7 @@ int32_t lsm6dso32x_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) 2); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -8271,15 +8404,16 @@ int32_t lsm6dso32x_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; } if (ret == 0) { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -8313,10 +8447,7 @@ int32_t lsm6dso32x_long_clr_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -8366,10 +8497,7 @@ int32_t lsm6dso32x_long_clr_get(const stmdev_ctx_t *ctx, } } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -8395,10 +8523,7 @@ int32_t lsm6dso32x_fsm_out_get(const stmdev_ctx_t *ctx, 16); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -8434,10 +8559,7 @@ int32_t lsm6dso32x_fsm_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -8488,10 +8610,10 @@ int32_t lsm6dso32x_fsm_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32X_ODR_FSM_12Hz5; break; } - - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -8523,10 +8645,7 @@ int32_t lsm6dso32x_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -8555,9 +8674,10 @@ int32_t lsm6dso32x_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = reg.fsm_init; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -8618,6 +8738,10 @@ int32_t lsm6dso32x_long_cnt_int_value_get(const stmdev_ctx_t *ctx, { ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_H, &add_h); + } + + if (ret == 0) + { *val = add_h; *val = *val << 8; *val += add_l; @@ -8715,6 +8839,10 @@ int32_t lsm6dso32x_fsm_start_address_get(const stmdev_ctx_t *ctx, { ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_START_ADD_H, &add_h); + } + + if (ret == 0) + { *val = add_h; *val = *val << 8; *val += add_l; @@ -8781,10 +8909,7 @@ int32_t lsm6dso32x_mlc_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -8836,10 +8961,10 @@ int32_t lsm6dso32x_mlc_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32X_ODR_PRGS_12Hz5; break; } - - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -8878,10 +9003,7 @@ int32_t lsm6dso32x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, len); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -8915,10 +9037,7 @@ int32_t lsm6dso32x_sh_slave_connected_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -8969,10 +9088,10 @@ int32_t lsm6dso32x_sh_slave_connected_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32X_SLV_0; break; } - - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -9004,10 +9123,7 @@ int32_t lsm6dso32x_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9036,9 +9152,10 @@ int32_t lsm6dso32x_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = reg.master_on; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -9071,10 +9188,7 @@ int32_t lsm6dso32x_sh_pin_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9117,10 +9231,10 @@ int32_t lsm6dso32x_sh_pin_mode_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32X_EXT_PULL_UP; break; } - - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -9153,10 +9267,7 @@ int32_t lsm6dso32x_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9187,9 +9298,10 @@ int32_t lsm6dso32x_sh_pass_through_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.pass_through_mode; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -9222,10 +9334,7 @@ int32_t lsm6dso32x_sh_syncro_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9268,10 +9377,10 @@ int32_t lsm6dso32x_sh_syncro_mode_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32X_EXT_ON_INT2_PIN; break; } - - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -9305,10 +9414,7 @@ int32_t lsm6dso32x_sh_write_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9352,10 +9458,10 @@ int32_t lsm6dso32x_sh_write_mode_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32X_EACH_SH_CYCLE; break; } - - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -9393,10 +9499,7 @@ int32_t lsm6dso32x_sh_reset_set(const stmdev_ctx_t *ctx) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9425,9 +9528,10 @@ int32_t lsm6dso32x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = reg.rst_master_regs; - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -9460,10 +9564,7 @@ int32_t lsm6dso32x_sh_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9514,10 +9615,10 @@ int32_t lsm6dso32x_sh_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSO32X_SH_ODR_104Hz; break; } - - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + return ret; } @@ -9559,10 +9660,7 @@ int32_t lsm6dso32x_sh_cfg_write(const stmdev_ctx_t *ctx, &(val->slv0_data), 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9614,10 +9712,7 @@ int32_t lsm6dso32x_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9669,10 +9764,7 @@ int32_t lsm6dso32x_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9724,10 +9816,7 @@ int32_t lsm6dso32x_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9779,10 +9868,7 @@ int32_t lsm6dso32x_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9808,10 +9894,7 @@ int32_t lsm6dso32x_sh_status_get(const stmdev_ctx_t *ctx, (uint8_t *) val, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -9908,10 +9991,7 @@ int32_t lsm6dso32x_init_set(const stmdev_ctx_t *ctx, lsm6dso32x_init_t val) (uint8_t *)&emb_func_init_a, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); if (ret == 0) { @@ -10066,7 +10146,10 @@ int32_t lsm6dso32x_bus_mode_get(const stmdev_ctx_t *ctx, { ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + if (ret == 0) + { switch ((i3c_bus_avb.i3c_bus_avb_sel << 4) & (ctrl9_xl.i3c_disable << 2) & (ctrl4_c.i2c_disable << 1) & ctrl3_c.sim) @@ -10134,17 +10217,25 @@ int32_t lsm6dso32x_status_get(const stmdev_ctx_t *ctx, { ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - val->sw_reset = ctrl3_c.sw_reset; - val->boot = ctrl3_c.boot; + + if (ret == 0) + { + val->sw_reset = ctrl3_c.sw_reset; + val->boot = ctrl3_c.boot; + } if ((ret == 0) && (ctrl3_c.sw_reset == PROPERTY_DISABLE) && (ctrl3_c.boot == PROPERTY_DISABLE)) { ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)&status_reg, 1); - val->drdy_xl = status_reg.xlda; - val->drdy_g = status_reg.gda; - val->drdy_temp = status_reg.tda; + + if (ret == 0) + { + val->drdy_xl = status_reg.xlda; + val->drdy_g = status_reg.gda; + val->drdy_temp = status_reg.tda; + } } } @@ -10226,24 +10317,16 @@ int32_t lsm6dso32x_pin_conf_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + ret += lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, + (uint8_t *)&ctrl3_c, 1); + ret += lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); if (ret == 0) { val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en; - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, - (uint8_t *)&ctrl3_c, 1); - } - - if (ret == 0) - { val->int1_int2_push_pull = ~ctrl3_c.pp_od; - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); - } - - if (ret == 0) - { - val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1; + val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1; } return ret; @@ -10292,24 +10375,21 @@ int32_t lsm6dso32x_interrupt_mode_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - page_rw.emb_func_lir = val.emb_latched; - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + page_rw.emb_func_lir = val.emb_latched; + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } return ret; @@ -10333,37 +10413,27 @@ int32_t lsm6dso32x_interrupt_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + ret += lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, + (uint8_t *) &tap_cfg0, 1); if (ret == 0) { - ctrl3_c.h_lactive = val->active_low; - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, - (uint8_t *) &tap_cfg0, 1); - } - - if (ret == 0) - { - tap_cfg0.lir = val->base_latched; - tap_cfg0.int_clr_on_read = val->base_latched | val->emb_latched; ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW, + (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - page_rw.emb_func_lir = val->emb_latched; - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW, - (uint8_t *) &page_rw, 1); + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } if (ret == 0) { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + val->active_low = ctrl3_c.h_lactive; + val->base_latched = tap_cfg0.lir; + val->emb_latched = page_rw.emb_func_lir; } return ret; @@ -10458,35 +10528,32 @@ int32_t lsm6dso32x_pin_int1_route_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MLC_INT1, - (uint8_t *)&mlc_int1, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MLC_INT1, + (uint8_t *)&mlc_int1, 1); + } - if (ret == 0) - { - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INT1, - (uint8_t *)&emb_func_int1, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INT1, + (uint8_t *)&emb_func_int1, 1); + } - if (ret == 0) - { - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT1_A, - (uint8_t *)&fsm_int1_a, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT1_A, + (uint8_t *)&fsm_int1_a, 1); + } - if (ret == 0) - { - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT1_B, - (uint8_t *)&fsm_int1_b, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT1_B, + (uint8_t *)&fsm_int1_b, 1); + } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } if (ret == 0) @@ -10668,10 +10735,7 @@ int32_t lsm6dso32x_pin_int1_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&fsm_int1_b, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); if (ret == 0) { @@ -10697,66 +10761,73 @@ int32_t lsm6dso32x_pin_int1_route_get(const stmdev_ctx_t *ctx, { ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->drdy_temp = int2_ctrl.int2_drdy_temp; } if (ret == 0) { + + val->drdy_temp = int2_ctrl.int2_drdy_temp; ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { val->timestamp = md2_cfg.int2_timestamp; } } - else { val->drdy_temp = PROPERTY_DISABLE; val->timestamp = PROPERTY_DISABLE; } - val->drdy_xl = int1_ctrl.int1_drdy_xl; - val->drdy_g = int1_ctrl.int1_drdy_g; - val->boot = int1_ctrl.int1_boot; - val->fifo_th = int1_ctrl.int1_fifo_th; - val->fifo_ovr = int1_ctrl.int1_fifo_ovr; - val->fifo_full = int1_ctrl.int1_fifo_full; - val->fifo_bdr = int1_ctrl.int1_cnt_bdr; - val->den_flag = int1_ctrl.den_drdy_flag; - val->sh_endop = md1_cfg.int1_shub; - val->six_d = md1_cfg.int1_6d; - val->double_tap = md1_cfg.int1_double_tap; - val->free_fall = md1_cfg.int1_ff; - val->wake_up = md1_cfg.int1_wu; - val->single_tap = md1_cfg.int1_single_tap; - val->sleep_change = md1_cfg.int1_sleep_change; - val->step_detector = emb_func_int1.int1_step_detector; - val->tilt = emb_func_int1.int1_tilt; - val->sig_mot = emb_func_int1.int1_sig_mot; - val->fsm_lc = emb_func_int1.int1_fsm_lc; - val->fsm1 = fsm_int1_a.int1_fsm1; - val->fsm2 = fsm_int1_a.int1_fsm2; - val->fsm3 = fsm_int1_a.int1_fsm3; - val->fsm4 = fsm_int1_a.int1_fsm4; - val->fsm5 = fsm_int1_a.int1_fsm5; - val->fsm6 = fsm_int1_a.int1_fsm6; - val->fsm7 = fsm_int1_a.int1_fsm7; - val->fsm8 = fsm_int1_a.int1_fsm8; - val->fsm9 = fsm_int1_b.int1_fsm9; - val->fsm10 = fsm_int1_b.int1_fsm10; - val->fsm11 = fsm_int1_b.int1_fsm11; - val->fsm12 = fsm_int1_b.int1_fsm12; - val->fsm13 = fsm_int1_b.int1_fsm13; - val->fsm14 = fsm_int1_b.int1_fsm14; - val->fsm15 = fsm_int1_b.int1_fsm15; - val->fsm16 = fsm_int1_b.int1_fsm16; - val->mlc1 = mlc_int1.int1_mlc1; - val->mlc2 = mlc_int1.int1_mlc2; - val->mlc3 = mlc_int1.int1_mlc3; - val->mlc4 = mlc_int1.int1_mlc4; - val->mlc5 = mlc_int1.int1_mlc5; - val->mlc6 = mlc_int1.int1_mlc6; - val->mlc7 = mlc_int1.int1_mlc7; - val->mlc8 = mlc_int1.int1_mlc8; + if (ret == 0) + { + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_g = int1_ctrl.int1_drdy_g; + val->boot = int1_ctrl.int1_boot; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->fifo_bdr = int1_ctrl.int1_cnt_bdr; + val->den_flag = int1_ctrl.den_drdy_flag; + val->sh_endop = md1_cfg.int1_shub; + val->six_d = md1_cfg.int1_6d; + val->double_tap = md1_cfg.int1_double_tap; + val->free_fall = md1_cfg.int1_ff; + val->wake_up = md1_cfg.int1_wu; + val->single_tap = md1_cfg.int1_single_tap; + val->sleep_change = md1_cfg.int1_sleep_change; + val->step_detector = emb_func_int1.int1_step_detector; + val->tilt = emb_func_int1.int1_tilt; + val->sig_mot = emb_func_int1.int1_sig_mot; + val->fsm_lc = emb_func_int1.int1_fsm_lc; + val->fsm1 = fsm_int1_a.int1_fsm1; + val->fsm2 = fsm_int1_a.int1_fsm2; + val->fsm3 = fsm_int1_a.int1_fsm3; + val->fsm4 = fsm_int1_a.int1_fsm4; + val->fsm5 = fsm_int1_a.int1_fsm5; + val->fsm6 = fsm_int1_a.int1_fsm6; + val->fsm7 = fsm_int1_a.int1_fsm7; + val->fsm8 = fsm_int1_a.int1_fsm8; + val->fsm9 = fsm_int1_b.int1_fsm9; + val->fsm10 = fsm_int1_b.int1_fsm10; + val->fsm11 = fsm_int1_b.int1_fsm11; + val->fsm12 = fsm_int1_b.int1_fsm12; + val->fsm13 = fsm_int1_b.int1_fsm13; + val->fsm14 = fsm_int1_b.int1_fsm14; + val->fsm15 = fsm_int1_b.int1_fsm15; + val->fsm16 = fsm_int1_b.int1_fsm16; + val->mlc1 = mlc_int1.int1_mlc1; + val->mlc2 = mlc_int1.int1_mlc2; + val->mlc3 = mlc_int1.int1_mlc3; + val->mlc4 = mlc_int1.int1_mlc4; + val->mlc5 = mlc_int1.int1_mlc5; + val->mlc6 = mlc_int1.int1_mlc6; + val->mlc7 = mlc_int1.int1_mlc7; + val->mlc8 = mlc_int1.int1_mlc8; + } return ret; } @@ -10850,35 +10921,32 @@ int32_t lsm6dso32x_pin_int2_route_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MLC_INT2, - (uint8_t *)&mlc_int2, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MLC_INT2, + (uint8_t *)&mlc_int2, 1); + } - if (ret == 0) - { - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INT2, - (uint8_t *)&emb_func_int2, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INT2, + (uint8_t *)&emb_func_int2, 1); + } - if (ret == 0) - { - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT2_A, - (uint8_t *)&fsm_int2_a, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT2_A, + (uint8_t *)&fsm_int2_a, 1); + } - if (ret == 0) - { - ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT2_B, - (uint8_t *)&fsm_int2_b, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT2_B, + (uint8_t *)&fsm_int2_b, 1); + } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } if (ret == 0) @@ -11037,10 +11105,7 @@ int32_t lsm6dso32x_pin_int2_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&fsm_int2_b, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); if (ret == 0) { @@ -11066,64 +11131,71 @@ int32_t lsm6dso32x_pin_int2_route_get(const stmdev_ctx_t *ctx, { ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->drdy_temp = int2_ctrl.int2_drdy_temp; } if (ret == 0) { + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + val->drdy_temp = int2_ctrl.int2_drdy_temp; val->timestamp = md2_cfg.int2_timestamp; } } - else { val->drdy_temp = PROPERTY_DISABLE; val->timestamp = PROPERTY_DISABLE; } - val->drdy_xl = int2_ctrl.int2_drdy_xl; - val->drdy_g = int2_ctrl.int2_drdy_g; - val->drdy_temp = int2_ctrl.int2_drdy_temp; - val->fifo_th = int2_ctrl.int2_fifo_th; - val->fifo_ovr = int2_ctrl.int2_fifo_ovr; - val->fifo_full = int2_ctrl.int2_fifo_full; - val->fifo_bdr = int2_ctrl.int2_cnt_bdr; - val->timestamp = md2_cfg.int2_timestamp; - val->six_d = md2_cfg.int2_6d; - val->double_tap = md2_cfg.int2_double_tap; - val->free_fall = md2_cfg.int2_ff; - val->wake_up = md2_cfg.int2_wu; - val->single_tap = md2_cfg.int2_single_tap; - val->sleep_change = md2_cfg.int2_sleep_change; - val->step_detector = emb_func_int2. int2_step_detector; - val->tilt = emb_func_int2.int2_tilt; - val->fsm_lc = emb_func_int2.int2_fsm_lc; - val->fsm1 = fsm_int2_a.int2_fsm1; - val->fsm2 = fsm_int2_a.int2_fsm2; - val->fsm3 = fsm_int2_a.int2_fsm3; - val->fsm4 = fsm_int2_a.int2_fsm4; - val->fsm5 = fsm_int2_a.int2_fsm5; - val->fsm6 = fsm_int2_a.int2_fsm6; - val->fsm7 = fsm_int2_a.int2_fsm7; - val->fsm8 = fsm_int2_a.int2_fsm8; - val->fsm9 = fsm_int2_b.int2_fsm9; - val->fsm10 = fsm_int2_b.int2_fsm10; - val->fsm11 = fsm_int2_b.int2_fsm11; - val->fsm12 = fsm_int2_b.int2_fsm12; - val->fsm13 = fsm_int2_b.int2_fsm13; - val->fsm14 = fsm_int2_b.int2_fsm14; - val->fsm15 = fsm_int2_b.int2_fsm15; - val->fsm16 = fsm_int2_b.int2_fsm16; - val->mlc1 = mlc_int2.int2_mlc1; - val->mlc2 = mlc_int2.int2_mlc2; - val->mlc3 = mlc_int2.int2_mlc3; - val->mlc4 = mlc_int2.int2_mlc4; - val->mlc5 = mlc_int2.int2_mlc5; - val->mlc6 = mlc_int2.int2_mlc6; - val->mlc7 = mlc_int2.int2_mlc7; - val->mlc8 = mlc_int2.int2_mlc8; + if (ret == 0) + { + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_g = int2_ctrl.int2_drdy_g; + val->drdy_temp = int2_ctrl.int2_drdy_temp; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->fifo_bdr = int2_ctrl.int2_cnt_bdr; + val->timestamp = md2_cfg.int2_timestamp; + val->six_d = md2_cfg.int2_6d; + val->double_tap = md2_cfg.int2_double_tap; + val->free_fall = md2_cfg.int2_ff; + val->wake_up = md2_cfg.int2_wu; + val->single_tap = md2_cfg.int2_single_tap; + val->sleep_change = md2_cfg.int2_sleep_change; + val->step_detector = emb_func_int2. int2_step_detector; + val->tilt = emb_func_int2.int2_tilt; + val->fsm_lc = emb_func_int2.int2_fsm_lc; + val->fsm1 = fsm_int2_a.int2_fsm1; + val->fsm2 = fsm_int2_a.int2_fsm2; + val->fsm3 = fsm_int2_a.int2_fsm3; + val->fsm4 = fsm_int2_a.int2_fsm4; + val->fsm5 = fsm_int2_a.int2_fsm5; + val->fsm6 = fsm_int2_a.int2_fsm6; + val->fsm7 = fsm_int2_a.int2_fsm7; + val->fsm8 = fsm_int2_a.int2_fsm8; + val->fsm9 = fsm_int2_b.int2_fsm9; + val->fsm10 = fsm_int2_b.int2_fsm10; + val->fsm11 = fsm_int2_b.int2_fsm11; + val->fsm12 = fsm_int2_b.int2_fsm12; + val->fsm13 = fsm_int2_b.int2_fsm13; + val->fsm14 = fsm_int2_b.int2_fsm14; + val->fsm15 = fsm_int2_b.int2_fsm15; + val->fsm16 = fsm_int2_b.int2_fsm16; + val->mlc1 = mlc_int2.int2_mlc1; + val->mlc2 = mlc_int2.int2_mlc2; + val->mlc3 = mlc_int2.int2_mlc3; + val->mlc4 = mlc_int2.int2_mlc4; + val->mlc5 = mlc_int2.int2_mlc5; + val->mlc6 = mlc_int2.int2_mlc6; + val->mlc7 = mlc_int2.int2_mlc7; + val->mlc8 = mlc_int2.int2_mlc8; + } } return ret; @@ -11725,31 +11797,28 @@ int32_t lsm6dso32x_mode_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B, reg, 2); - bytecpy((uint8_t *)&emb_func_odr_cfg_b, ®[0]); - bytecpy((uint8_t *)&emb_func_odr_cfg_c, ®[1]); - } + if (ret == 0) + { + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B, reg, 2); + bytecpy((uint8_t *)&emb_func_odr_cfg_b, ®[0]); + bytecpy((uint8_t *)&emb_func_odr_cfg_c, ®[1]); + } - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - } + if (ret == 0) + { + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } - if (ret == 0) - { - ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_ENABLE_A, reg, 2); - bytecpy((uint8_t *)&fsm_enable_a, ®[0]); - bytecpy((uint8_t *)&fsm_enable_b, ®[1]); - } + if (ret == 0) + { + ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_ENABLE_A, reg, 2); + bytecpy((uint8_t *)&fsm_enable_a, ®[0]); + bytecpy((uint8_t *)&fsm_enable_b, ®[1]); + } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); } } @@ -12101,6 +12170,8 @@ int32_t lsm6dso32x_data_get(const stmdev_ctx_t *ctx, ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUT_TEMP_L, buff, 14); } + if (ret != 0) { return ret; } + j = 0; /* temperature conversion */ data->ui.heat.raw = (int16_t)buff[j + 1U]; @@ -12232,10 +12303,7 @@ int32_t lsm6dso32x_embedded_sens_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -12276,10 +12344,7 @@ int32_t lsm6dso32x_embedded_sens_get(const stmdev_ctx_t *ctx, emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en; } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -12331,10 +12396,7 @@ int32_t lsm6dso32x_embedded_sens_off(const stmdev_ctx_t *ctx) (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); - } + ret += lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK); return ret; } @@ -12348,5 +12410,3 @@ int32_t lsm6dso32x_embedded_sens_off(const stmdev_ctx_t *ctx) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h index 67eb97f..fb12e7c 100644 --- a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h +++ b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -4311,5 +4313,3 @@ int32_t lsm6dso32x_embedded_sens_off(const stmdev_ctx_t *ctx); #endif #endif /*LSM6DSO32X_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c index eae5619..29bc69d 100644 --- a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c +++ b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -10613,7 +10612,7 @@ int32_t lsm6dso_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_ctrl2_g_t ctrl2_g; lsm6dso_ctrl3_c_t ctrl3_c = {0}; lsm6dso_ctrl4_c_t ctrl4_c = {0}; - lsm6dso_ctrl5_c_t ctrl5_c; + lsm6dso_ctrl5_c_t ctrl5_c = {0}; lsm6dso_ctrl6_c_t ctrl6_c; lsm6dso_ctrl7_g_t ctrl7_g; uint8_t xl_hm_mode; @@ -11881,5 +11880,3 @@ int32_t lsm6dso_embedded_sens_off(const stmdev_ctx_t *ctx) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h index 02d789a..f22b597 100644 --- a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h +++ b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; #ifndef __weak @@ -4327,5 +4329,3 @@ int32_t lsm6dso_embedded_sens_off(const stmdev_ctx_t *ctx); #endif #endif /*LSM6DSO_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c index d4b8b96..ad4c06d 100644 --- a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c +++ b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -227,6 +226,8 @@ int32_t lsm6dsox_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + switch (reg.fs_xl) { case LSM6DSOX_2g: @@ -524,6 +525,7 @@ int32_t lsm6dsox_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.odr_xl) { @@ -623,6 +625,7 @@ int32_t lsm6dsox_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.fs_g) { @@ -925,6 +928,7 @@ int32_t lsm6dsox_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.odr_g) { @@ -1019,6 +1023,8 @@ int32_t lsm6dsox_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.bdu; return ret; @@ -1066,6 +1072,7 @@ int32_t lsm6dsox_xl_offset_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.usr_off_w) { @@ -1139,11 +1146,10 @@ int32_t lsm6dsox_xl_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *) &ctrl5_c, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *) &ctrl6_c, 1); if (ret == 0) { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *) &ctrl6_c, 1); - switch ((ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode) { case LSM6DSOX_HIGH_PERFORMANCE_MD: @@ -1207,6 +1213,7 @@ int32_t lsm6dsox_gy_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.g_hm_mode) { @@ -1259,6 +1266,8 @@ int32_t lsm6dsox_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.xlda; return ret; @@ -1279,6 +1288,8 @@ int32_t lsm6dsox_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.gda; return ret; @@ -1299,6 +1310,8 @@ int32_t lsm6dsox_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.tda; return ret; @@ -1306,7 +1319,7 @@ int32_t lsm6dsox_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, /** * @brief Accelerometer X-axis user offset correction expressed in - * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * two's complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * * @param ctx read / write interface definitions @@ -1324,7 +1337,7 @@ int32_t lsm6dsox_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer X-axis user offset correction expressed in two’s + * @brief Accelerometer X-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1343,7 +1356,7 @@ int32_t lsm6dsox_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1362,7 +1375,7 @@ int32_t lsm6dsox_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Y-axis user offset correction expressed in two’s + * @brief Accelerometer Y-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1381,7 +1394,7 @@ int32_t lsm6dsox_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[set] * @@ -1400,7 +1413,7 @@ int32_t lsm6dsox_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Accelerometer Z-axis user offset correction expressed in two’s + * @brief Accelerometer Z-axis user offset correction expressed in two's * complement, weight depends on USR_OFF_W in CTRL6_C (15h). * The value must be in the range [-127 127].[get] * @@ -1456,6 +1469,8 @@ int32_t lsm6dsox_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.usr_off_on_out; return ret; @@ -1525,6 +1540,8 @@ int32_t lsm6dsox_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.timestamp_en; return ret; @@ -1546,6 +1563,8 @@ int32_t lsm6dsox_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TIMESTAMP0, buff, 4); + if (ret != 0) { return ret; } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1607,6 +1626,7 @@ int32_t lsm6dsox_rounding_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.rounding) { @@ -1694,6 +1714,7 @@ int32_t lsm6dsox_rounding_on_status_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.rounding_status) { @@ -1715,7 +1736,7 @@ int32_t lsm6dsox_rounding_on_status_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). - * L and H registers together express a 16-bit word in two’s + * L and H registers together express a 16-bit word in two's * complement.[get] * * @param ctx read / write interface definitions @@ -1729,6 +1750,8 @@ int32_t lsm6dsox_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUT_TEMP_L, buff, 2); + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1737,7 +1760,7 @@ int32_t lsm6dsox_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Angular rate sensor. The value is expressed as a 16-bit - * word in two’s complement.[get] + * word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -1750,6 +1773,8 @@ int32_t lsm6dsox_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_G, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1762,7 +1787,7 @@ int32_t lsm6dsox_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. - * The value is expressed as a 16-bit word in two’s complement.[get] + * The value is expressed as a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -1775,6 +1800,8 @@ int32_t lsm6dsox_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_A, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1805,7 +1832,7 @@ int32_t lsm6dsox_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) /** * @brief ois_angular_rate_raw: [get] OIS angular rate sensor. * The value is expressed as a - * 16-bit word in two’s complement. + * 16-bit word in two's complement. * * @param ctx read / write interface definitions * @param uint8_t * : buffer that stores data read @@ -1819,6 +1846,8 @@ int32_t lsm6dsox_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1832,7 +1861,7 @@ int32_t lsm6dsox_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, /** * @brief ois_acceleration_raw: [get] OIS Linear acceleration output register. * The value is expressed as a - * 16-bit word in two’s complement. + * 16-bit word in two's complement. * * @param ctx read / write interface definitions * @param uint8_t * : buffer that stores data read @@ -1846,6 +1875,8 @@ int32_t lsm6dsox_ois_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_A_OIS, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1860,7 +1891,7 @@ int32_t lsm6dsox_ois_acceleration_raw_get(const stmdev_ctx_t *ctx, * @brief aux_temperature_raw: [get] Temperature from auxiliary * interface. * The value is expressed as a - * 16-bit word in two’s complement. + * 16-bit word in two's complement. * * @param ctx read / write interface definitions * @param uint8_t * : buffer that stores data read @@ -1874,6 +1905,8 @@ int32_t lsm6dsox_aux_temperature_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUT_TEMP_L, buff, 2); + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1884,7 +1917,7 @@ int32_t lsm6dsox_aux_temperature_raw_get(const stmdev_ctx_t *ctx, * @brief aux_ois_angular_rate_raw: [get] OIS angular rate sensor from * auxiliary interface. * The value is expressed as a - * 16-bit word in two’s complement. + * 16-bit word in two's complement. * * @param ctx read / write interface definitions * @param uint8_t * : buffer that stores data read @@ -1898,6 +1931,8 @@ int32_t lsm6dsox_aux_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1912,7 +1947,7 @@ int32_t lsm6dsox_aux_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, * @brief aux_ois_acceleration_raw: [get] OIS linear acceleration output * register from auxiliary interface. * The value is expressed as a - * 16-bit word in two’s complement. + * 16-bit word in two's complement. * * @param ctx read / write interface definitions * @param uint8_t * : buffer that stores data read @@ -1926,6 +1961,8 @@ int32_t lsm6dsox_aux_ois_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_A_OIS, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1954,15 +1991,16 @@ int32_t lsm6dsox_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STEP_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; } if (ret == 0) { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -1991,10 +2029,7 @@ int32_t lsm6dsox_steps_reset(const stmdev_ctx_t *ctx) ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -2018,10 +2053,7 @@ int32_t lsm6dsox_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC0_SRC, buff, 8); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -2084,6 +2116,8 @@ int32_t lsm6dsox_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.freq_fine; return ret; @@ -2137,6 +2171,7 @@ int32_t lsm6dsox_mem_bank_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.reg_access) { @@ -2172,66 +2207,7 @@ int32_t lsm6dsox_mem_bank_get(const stmdev_ctx_t *ctx, int32_t lsm6dsox_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val) { - lsm6dsox_page_rw_t page_rw; - lsm6dsox_page_sel_t page_sel; - lsm6dsox_page_address_t page_address; - int32_t ret; - - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x02; /* page_write enable */ - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *) &page_sel, 1); - } - - if (ret == 0) - { - page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); - page_sel.not_used_01 = 1; - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } - - if (ret == 0) - { - page_address.page_addr = (uint8_t)address & 0xFFU; - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - - if (ret == 0) - { - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1); - } - - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } - - return ret; + return lsm6dsox_ln_pg_write(ctx, address, val, 1); } /** @@ -2257,82 +2233,64 @@ int32_t lsm6dsox_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, msb = ((uint8_t)(address >> 8) & 0x0FU); lsb = (uint8_t)address & 0xFFU; ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret != 0) { return ret; } + + /* set page write */ + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x02; /* page_write enable*/ + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + + /* select page */ + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; // Default value + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, + (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x02; /* page_write enable*/ - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *) &page_sel, 1); - } - - if (ret == 0) - { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } + /* set page addr */ + page_address.page_addr = lsb; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { goto exit; } - if (ret == 0) + for (i = 0; ((i < len) && (ret == 0)); i++) { - page_address.page_addr = lsb; - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { goto exit; } + lsb++; - if (ret == 0) - { - for (i = 0; ((i < len) && (ret == 0)); i++) + /* Check if page wrap */ + if (lsb == 0x00U) { - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, &buf[i], 1); - lsb++; - - /* Check if page wrap */ - if ((lsb == 0x00U) && (ret == 0)) - { - msb++; - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *)&page_sel, 1); - - if (ret == 0) - { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - } + msb++; + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } } } page_sel.page_sel = 0; - page_sel.not_used_01 = 1; + page_sel.not_used_01 = 1; // Default value ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } + /* unset page write */ + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x00; /* page_write disable */ + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } +exit: + ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -2355,58 +2313,41 @@ int32_t lsm6dsox_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address, int32_t ret; ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); + if (ret != 0) { return ret; } + + /* set page read */ + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x01; /* page_read enable*/ + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + + /* select page */ + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } + page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); + page_sel.not_used_01 = 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, + (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x01; /* page_read enable*/ - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *) &page_sel, 1); - } - - if (ret == 0) - { - page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); - page_sel.not_used_01 = 1; - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } - - if (ret == 0) - { - page_address.page_addr = (uint8_t)address & 0x00FFU; - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1); - } + /* set page addr */ + page_address.page_addr = (uint8_t)address & 0x00FFU; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } + /* read value */ + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_read disable */ - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } + /* unset page read */ + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + if (ret != 0) { goto exit; } + page_rw.page_rw = 0x00; /* page_read disable */ + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } +exit: + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -2458,6 +2399,7 @@ int32_t lsm6dsox_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.dataready_pulsed) { @@ -2533,6 +2475,8 @@ int32_t lsm6dsox_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.sw_reset; return ret; @@ -2578,6 +2522,8 @@ int32_t lsm6dsox_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.if_inc; return ret; @@ -2621,6 +2567,8 @@ int32_t lsm6dsox_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.boot; return ret; @@ -2666,6 +2614,7 @@ int32_t lsm6dsox_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.st_xl) { @@ -2729,6 +2678,7 @@ int32_t lsm6dsox_gy_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.st_g) { @@ -2803,6 +2753,8 @@ int32_t lsm6dsox_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.lpf2_xl_en; return ret; @@ -2850,6 +2802,8 @@ int32_t lsm6dsox_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.lpf1_sel_g; return ret; @@ -2897,6 +2851,8 @@ int32_t lsm6dsox_filter_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.drdy_mask; return ret; @@ -2942,6 +2898,7 @@ int32_t lsm6dsox_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.ftype) { @@ -3023,6 +2980,8 @@ int32_t lsm6dsox_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.low_pass_on_6d; return ret; @@ -3074,6 +3033,7 @@ int32_t lsm6dsox_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) | reg.hpcf_xl) @@ -3221,6 +3181,8 @@ int32_t lsm6dsox_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.fastsettl_mode_xl; return ret; @@ -3268,6 +3230,7 @@ int32_t lsm6dsox_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.slope_fds) { @@ -3332,6 +3295,7 @@ int32_t lsm6dsox_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch ((reg.hp_en_g << 7) + reg.hpm_g) { @@ -3393,6 +3357,8 @@ int32_t lsm6dsox_ois_mode_set(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); if (ret == 0) { @@ -3401,12 +3367,6 @@ int32_t lsm6dsox_ois_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&ui_int_ois, 1); } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, - (uint8_t *)&func_cfg_access, 1); - } - if (ret == 0) { func_cfg_access.ois_ctrl_from_ui = (((uint8_t)val & 0x02U) >> 1); @@ -3435,12 +3395,10 @@ int32_t lsm6dsox_ois_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS, - (uint8_t *)&func_cfg_access, 1); - } + if (ret != 0) { return ret; } switch ((func_cfg_access.ois_ctrl_from_ui << 1) + ui_int_ois.spi2_read_en) @@ -3512,6 +3470,7 @@ int32_t lsm6dsox_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.ois_pu_dis) { @@ -3572,6 +3531,7 @@ int32_t lsm6dsox_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.ois_on) { @@ -3642,6 +3602,7 @@ int32_t lsm6dsox_aux_xl_fs_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.xl_fs_mode) { @@ -3696,6 +3657,8 @@ int32_t lsm6dsox_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.xlda; return ret; @@ -3717,6 +3680,8 @@ int32_t lsm6dsox_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.gda; return ret; @@ -3738,6 +3703,8 @@ int32_t lsm6dsox_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.gyro_settling; return ret; @@ -3784,6 +3751,7 @@ int32_t lsm6dsox_aux_den_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.den_lh_ois) { @@ -3861,12 +3829,11 @@ int32_t lsm6dsox_aux_den_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *) &int_ois, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, + (uint8_t *) &ctrl1_ois, 1); if (ret == 0) { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, - (uint8_t *) &ctrl1_ois, 1); - switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) { case LSM6DSOX_AUX_DEN_DISABLE: @@ -3930,6 +3897,8 @@ int32_t lsm6dsox_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.int2_drdy_ois; return ret; @@ -3988,6 +3957,7 @@ int32_t lsm6dsox_aux_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch ((reg.mode4_en << 1) | reg.ois_en_spi2) { @@ -4051,6 +4021,7 @@ int32_t lsm6dsox_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.fs_g_ois) { @@ -4122,6 +4093,7 @@ int32_t lsm6dsox_aux_spi_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.sim_ois) { @@ -4182,6 +4154,7 @@ int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.ftype_ois) { @@ -4250,6 +4223,7 @@ int32_t lsm6dsox_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch ((reg.hp_en_ois << 4) | reg.hpm_ois) { @@ -4331,6 +4305,7 @@ int32_t lsm6dsox_aux_gy_clamp_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.st_ois_clampdis) { @@ -4392,6 +4367,7 @@ int32_t lsm6dsox_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.filter_xl_conf_ois) { @@ -4476,6 +4452,7 @@ int32_t lsm6dsox_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.fs_xl_ois) { @@ -4557,6 +4534,7 @@ int32_t lsm6dsox_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.sdo_pu_en) { @@ -4614,6 +4592,7 @@ int32_t lsm6dsox_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_sim_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.sim) { @@ -4675,6 +4654,7 @@ int32_t lsm6dsox_i2c_interface_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.i2c_disable) { @@ -4751,12 +4731,11 @@ int32_t lsm6dsox_i3c_disable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); if (ret == 0) { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); - switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel) { case LSM6DSOX_I3C_DISABLE: @@ -4815,6 +4794,8 @@ int32_t lsm6dsox_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_pp_od_t val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); if (ret == 0) { @@ -4822,12 +4803,6 @@ int32_t lsm6dsox_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_pp_od_t val) ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); - } - if (ret == 0) { i3c_bus_avb.pd_dis_int1 = ((uint8_t) val & 0x02U) >> 1; @@ -4854,12 +4829,10 @@ int32_t lsm6dsox_pin_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); - } + if (ret != 0) { return ret; } switch ((i3c_bus_avb.pd_dis_int1 << 1) + ctrl3_c.pp_od) { @@ -4927,6 +4900,7 @@ int32_t lsm6dsox_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.h_lactive) { @@ -4984,6 +4958,8 @@ int32_t lsm6dsox_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.int2_on_int1; return ret; @@ -5017,22 +4993,19 @@ int32_t lsm6dsox_int_notification_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } return ret; @@ -5058,16 +5031,13 @@ int32_t lsm6dsox_int_notification_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } if (ret == 0) @@ -5094,18 +5064,6 @@ int32_t lsm6dsox_int_notification_get(const stmdev_ctx_t *ctx, *val = LSM6DSOX_ALL_INT_PULSED; break; } - - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); - } - - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } return ret; @@ -5170,6 +5128,7 @@ int32_t lsm6dsox_wkup_ths_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.wake_ths_w) { @@ -5229,6 +5188,8 @@ int32_t lsm6dsox_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.wk_ths; return ret; @@ -5276,6 +5237,8 @@ int32_t lsm6dsox_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.usr_off_on_wu; return ret; @@ -5321,6 +5284,8 @@ int32_t lsm6dsox_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.wake_dur; return ret; @@ -5377,6 +5342,8 @@ int32_t lsm6dsox_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.sleep_g; return ret; @@ -5428,6 +5395,7 @@ int32_t lsm6dsox_act_pin_notification_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.sleep_status_on_int) { @@ -5487,6 +5455,7 @@ int32_t lsm6dsox_act_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.inact_en) { @@ -5554,6 +5523,8 @@ int32_t lsm6dsox_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.sleep_dur; return ret; @@ -5612,6 +5583,8 @@ int32_t lsm6dsox_tap_detection_on_z_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.tap_z_en; return ret; @@ -5657,6 +5630,8 @@ int32_t lsm6dsox_tap_detection_on_y_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.tap_y_en; return ret; @@ -5702,6 +5677,8 @@ int32_t lsm6dsox_tap_detection_on_x_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.tap_x_en; return ret; @@ -5745,6 +5722,8 @@ int32_t lsm6dsox_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.tap_ths_x; return ret; @@ -5792,6 +5771,7 @@ int32_t lsm6dsox_tap_axis_priority_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.tap_priority) { @@ -5865,6 +5845,8 @@ int32_t lsm6dsox_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.tap_ths_y; return ret; @@ -5908,6 +5890,8 @@ int32_t lsm6dsox_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.tap_ths_z; return ret; @@ -5961,6 +5945,8 @@ int32_t lsm6dsox_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.shock; return ret; @@ -6016,6 +6002,8 @@ int32_t lsm6dsox_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.quiet; return ret; @@ -6073,6 +6061,8 @@ int32_t lsm6dsox_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.dur; return ret; @@ -6118,6 +6108,7 @@ int32_t lsm6dsox_tap_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.single_double_tap) { @@ -6190,6 +6181,7 @@ int32_t lsm6dsox_6d_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.sixd_ths) { @@ -6255,6 +6247,8 @@ int32_t lsm6dsox_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.d4d_en; return ret; @@ -6312,6 +6306,7 @@ int32_t lsm6dsox_ff_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.ff_ths) { @@ -6372,12 +6367,8 @@ int32_t lsm6dsox_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, - (uint8_t *)&free_fall, 1); - } + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, + (uint8_t *)&free_fall, 1); if (ret == 0) { @@ -6413,11 +6404,11 @@ int32_t lsm6dsox_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, + (uint8_t *)&free_fall, 1); if (ret == 0) { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, - (uint8_t *)&free_fall, 1); *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; } @@ -6486,11 +6477,11 @@ int32_t lsm6dsox_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm; } @@ -6527,10 +6518,7 @@ int32_t lsm6dsox_compression_algo_init_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -6561,9 +6549,10 @@ int32_t lsm6dsox_compression_algo_init_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.fifo_compr_init; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -6612,6 +6601,7 @@ int32_t lsm6dsox_compression_algo_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate) { @@ -6683,6 +6673,8 @@ int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.odrchg_en; return ret; @@ -6729,6 +6721,8 @@ int32_t lsm6dsox_compression_algo_real_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.fifo_compr_rt_en; return ret; @@ -6774,6 +6768,8 @@ int32_t lsm6dsox_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.stop_on_wtm; return ret; @@ -6821,6 +6817,7 @@ int32_t lsm6dsox_fifo_xl_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.bdr_xl) { @@ -6922,6 +6919,7 @@ int32_t lsm6dsox_fifo_gy_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.bdr_gy) { @@ -7021,6 +7019,7 @@ int32_t lsm6dsox_fifo_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.fifo_mode) { @@ -7098,6 +7097,7 @@ int32_t lsm6dsox_fifo_temp_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.odr_t_batch) { @@ -7169,6 +7169,7 @@ int32_t lsm6dsox_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.odr_ts_batch) { @@ -7243,6 +7244,7 @@ int32_t lsm6dsox_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.trig_counter_bdr) { @@ -7308,6 +7310,8 @@ int32_t lsm6dsox_rst_batch_counter_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.rst_counter_bdr; return ret; @@ -7367,11 +7371,11 @@ int32_t lsm6dsox_batch_counter_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); if (ret == 0) { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8) + (uint16_t)counter_bdr_reg2.cnt_bdr_th; } @@ -7520,6 +7524,7 @@ int32_t lsm6dsox_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_TAG, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.tag_sensor) { @@ -7649,10 +7654,7 @@ int32_t lsm6dsox_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -7682,9 +7684,10 @@ int32_t lsm6dsox_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = reg.pedo_fifo_en; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -7715,10 +7718,7 @@ int32_t lsm6dsox_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -7747,9 +7747,10 @@ int32_t lsm6dsox_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = reg.batch_ext_sens_0_en; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -7780,10 +7781,7 @@ int32_t lsm6dsox_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -7807,14 +7805,15 @@ int32_t lsm6dsox_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t *)®, 1); - *val = reg.batch_ext_sens_1_en; } if (ret == 0) { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + *val = reg.batch_ext_sens_1_en; } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -7845,10 +7844,7 @@ int32_t lsm6dsox_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -7877,9 +7873,10 @@ int32_t lsm6dsox_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = reg.batch_ext_sens_2_en; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -7910,10 +7907,7 @@ int32_t lsm6dsox_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -7942,9 +7936,10 @@ int32_t lsm6dsox_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = reg.batch_ext_sens_3_en; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -8001,6 +7996,7 @@ int32_t lsm6dsox_den_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.den_mode) { @@ -8072,6 +8068,7 @@ int32_t lsm6dsox_den_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.den_lh) { @@ -8131,6 +8128,7 @@ int32_t lsm6dsox_den_enable_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.den_xl_g) { @@ -8192,6 +8190,8 @@ int32_t lsm6dsox_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.den_z; return ret; @@ -8235,6 +8235,8 @@ int32_t lsm6dsox_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.den_y; return ret; @@ -8278,6 +8280,8 @@ int32_t lsm6dsox_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.den_x; return ret; @@ -8339,6 +8343,7 @@ int32_t lsm6dsox_pedo_sens_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg); + if (ret != 0) { return ret; } switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en << 4)) @@ -8387,9 +8392,10 @@ int32_t lsm6dsox_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = reg.is_step_det; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -8475,11 +8481,11 @@ int32_t lsm6dsox_pedo_steps_period_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L, &buff[0]); + ret += lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H, + &buff[1]); if (ret == 0) { - ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H, - &buff[1]); *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -8532,6 +8538,7 @@ int32_t lsm6dsox_pedo_int_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG, (uint8_t *)®); + if (ret != 0) { return ret; } switch (reg.carry_count_en) { @@ -8589,9 +8596,10 @@ int32_t lsm6dsox_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.is_sigmot; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -8633,9 +8641,10 @@ int32_t lsm6dsox_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.is_tilt; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -8698,11 +8707,11 @@ int32_t lsm6dsox_sh_mag_sensitivity_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L, &buff[0]); + ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H, + &buff[1]); if (ret == 0) { - ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H, - &buff[1]); *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -8756,11 +8765,11 @@ int32_t lsm6dsox_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L, &buff[0]); + ret += lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H, + &buff[1]); if (ret == 0) { - ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H, - &buff[1]); *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -8884,12 +8893,15 @@ int32_t lsm6dsox_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) &buff[i]); } - val[0] = (int16_t)buff[1]; - val[0] = (val[0] * 256) + (int16_t)buff[0]; - val[1] = (int16_t)buff[3]; - val[1] = (val[1] * 256) + (int16_t)buff[2]; - val[2] = (int16_t)buff[5]; - val[2] = (val[2] * 256) + (int16_t)buff[4]; + if (ret == 0) + { + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + } return ret; } @@ -9112,18 +9124,21 @@ int32_t lsm6dsox_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) &buff[index]); } - val[0] = buff[1]; - val[0] = (val[0] * 256U) + buff[0]; - val[1] = buff[3]; - val[1] = (val[1] * 256U) + buff[2]; - val[2] = buff[5]; - val[2] = (val[2] * 256U) + buff[4]; - val[3] = buff[7]; - val[3] = (val[3] * 256U) + buff[6]; - val[4] = buff[9]; - val[4] = (val[4] * 256U) + buff[8]; - val[5] = buff[11]; - val[6] = (val[5] * 256U) + buff[10]; + if (ret == 0) + { + val[0] = buff[1]; + val[0] = (val[0] * 256U) + buff[0]; + val[1] = buff[3]; + val[1] = (val[1] * 256U) + buff[2]; + val[2] = buff[5]; + val[2] = (val[2] * 256U) + buff[4]; + val[3] = buff[7]; + val[3] = (val[3] * 256U) + buff[6]; + val[4] = buff[9]; + val[4] = (val[4] * 256U) + buff[8]; + val[5] = buff[11]; + val[6] = (val[5] * 256U) + buff[10]; + } return ret; } @@ -9177,6 +9192,7 @@ int32_t lsm6dsox_mag_z_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t *)®); + if (ret != 0) { return ret; } switch (reg.mag_z_axis) { @@ -9261,6 +9277,7 @@ int32_t lsm6dsox_mag_y_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A, (uint8_t *)®); + if (ret != 0) { return ret; } switch (reg.mag_y_axis) { @@ -9345,6 +9362,7 @@ int32_t lsm6dsox_mag_x_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B, (uint8_t *)®); + if (ret != 0) { return ret; } switch (reg.mag_x_axis) { @@ -9419,9 +9437,10 @@ int32_t lsm6dsox_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = reg.is_fsm_lc; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -9452,10 +9471,7 @@ int32_t lsm6dsox_fsm_enable_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_enable_b, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -9481,10 +9497,7 @@ int32_t lsm6dsox_fsm_enable_get(const stmdev_ctx_t *ctx, 2); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -9512,10 +9525,7 @@ int32_t lsm6dsox_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -9539,15 +9549,16 @@ int32_t lsm6dsox_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; } if (ret == 0) { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -9581,10 +9592,7 @@ int32_t lsm6dsox_long_clr_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -9634,10 +9642,7 @@ int32_t lsm6dsox_long_clr_get(const stmdev_ctx_t *ctx, } } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -9662,10 +9667,7 @@ int32_t lsm6dsox_fsm_out_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_OUTS1, (uint8_t *)val, 16); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -9701,10 +9703,7 @@ int32_t lsm6dsox_fsm_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -9755,10 +9754,10 @@ int32_t lsm6dsox_fsm_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSOX_ODR_FSM_12Hz5; break; } - - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -9790,10 +9789,7 @@ int32_t lsm6dsox_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -9822,9 +9818,10 @@ int32_t lsm6dsox_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = reg.fsm_init; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -9880,11 +9877,11 @@ int32_t lsm6dsox_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint8_t add_h; ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L, &add_l); + ret += lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H, + &add_h); if (ret == 0) { - ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H, - &add_h); *val = add_h; *val = *val << 8; *val += add_l; @@ -9976,10 +9973,10 @@ int32_t lsm6dsox_fsm_start_address_get(const stmdev_ctx_t *ctx, uint8_t add_l; uint8_t add_h; ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_L, &add_l); + ret += lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h); if (ret == 0) { - ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h); *val = add_h; *val = *val << 8; *val += add_l; @@ -10046,10 +10043,7 @@ int32_t lsm6dsox_mlc_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10101,10 +10095,10 @@ int32_t lsm6dsox_mlc_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSOX_ODR_PRGS_12Hz5; break; } - - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -10142,10 +10136,7 @@ int32_t lsm6dsox_sh_read_data_raw_get(const stmdev_ctx_t *ctx, len); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10177,10 +10168,7 @@ int32_t lsm6dsox_sh_slave_connected_set(const stmdev_ctx_t *ctx, ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10230,10 +10218,10 @@ int32_t lsm6dsox_sh_slave_connected_get(const stmdev_ctx_t *ctx, *val = LSM6DSOX_SLV_0; break; } - - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -10263,10 +10251,7 @@ int32_t lsm6dsox_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10294,9 +10279,10 @@ int32_t lsm6dsox_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = reg.master_on; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -10327,10 +10313,7 @@ int32_t lsm6dsox_sh_pin_mode_set(const stmdev_ctx_t *ctx, ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10372,10 +10355,10 @@ int32_t lsm6dsox_sh_pin_mode_get(const stmdev_ctx_t *ctx, *val = LSM6DSOX_EXT_PULL_UP; break; } - - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -10406,10 +10389,7 @@ int32_t lsm6dsox_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10438,9 +10418,10 @@ int32_t lsm6dsox_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = reg.pass_through_mode; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -10471,10 +10452,7 @@ int32_t lsm6dsox_sh_syncro_mode_set(const stmdev_ctx_t *ctx, ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10516,10 +10494,10 @@ int32_t lsm6dsox_sh_syncro_mode_get(const stmdev_ctx_t *ctx, *val = LSM6DSOX_EXT_ON_INT2_PIN; break; } - - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -10551,10 +10529,7 @@ int32_t lsm6dsox_sh_write_mode_set(const stmdev_ctx_t *ctx, ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10597,10 +10572,10 @@ int32_t lsm6dsox_sh_write_mode_get(const stmdev_ctx_t *ctx, *val = LSM6DSOX_EACH_SH_CYCLE; break; } - - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -10635,10 +10610,7 @@ int32_t lsm6dsox_sh_reset_set(const stmdev_ctx_t *ctx) ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10666,9 +10638,10 @@ int32_t lsm6dsox_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = reg.rst_master_regs; - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -10699,10 +10672,7 @@ int32_t lsm6dsox_sh_data_rate_set(const stmdev_ctx_t *ctx, ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10752,10 +10722,10 @@ int32_t lsm6dsox_sh_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSOX_SH_ODR_104Hz; break; } - - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + return ret; } @@ -10797,10 +10767,7 @@ int32_t lsm6dsox_sh_cfg_write(const stmdev_ctx_t *ctx, &(val->slv0_data), 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10851,10 +10818,7 @@ int32_t lsm6dsox_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10905,10 +10869,7 @@ int32_t lsm6dsox_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -10959,10 +10920,7 @@ int32_t lsm6dsox_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -11013,10 +10971,7 @@ int32_t lsm6dsox_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -11041,10 +10996,7 @@ int32_t lsm6dsox_sh_status_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_MASTER, (uint8_t *) val, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -11102,6 +11054,7 @@ int32_t lsm6dsox_s4s_tph_res_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.tph_h_sel) { @@ -11138,21 +11091,18 @@ int32_t lsm6dsox_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val) ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, + (uint8_t *)&s4s_tph_h, 1); + + s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU); + s4s_tph_h.tph_h = (uint8_t)(val & 0x7F80U) >> 7; if (ret == 0) { - s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU); ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1); } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, - (uint8_t *)&s4s_tph_h, 1); - s4s_tph_h.tph_h = (uint8_t)(val & 0x7F80U) >> 7; - } - if (ret == 0) { ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_H, @@ -11179,11 +11129,11 @@ int32_t lsm6dsox_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, + (uint8_t *)&s4s_tph_h, 1); if (ret == 0) { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H, - (uint8_t *)&s4s_tph_h, 1); *val = s4s_tph_h.tph_h; *val = *val << 7; *val += s4s_tph_l.tph_l; @@ -11234,6 +11184,7 @@ int32_t lsm6dsox_s4s_res_ratio_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t *)®, 1); + if (ret != 0) { return ret; } switch (reg.rr) { @@ -11302,6 +11253,8 @@ int32_t lsm6dsox_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.s4s_st_cmd_code; return ret; @@ -11345,6 +11298,8 @@ int32_t lsm6dsox_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.dt; return ret; @@ -11454,10 +11409,7 @@ int32_t lsm6dsox_init_set(const stmdev_ctx_t *ctx, lsm6dsox_init_t val) (uint8_t *)&emb_func_init_a, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); if (ret == 0) { @@ -11618,6 +11570,8 @@ int32_t lsm6dsox_bus_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, (uint8_t *)&spi2_ctrl1_ois, 1); + if (ret != 0) { return ret; } + switch (spi2_ctrl1_ois.sim_ois) { case LSM6DSOX_SPI_4W_AUX: @@ -11658,7 +11612,10 @@ int32_t lsm6dsox_bus_mode_get(const stmdev_ctx_t *ctx, { ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + if (ret == 0) + { switch ((i3c_bus_avb.i3c_bus_avb_sel << 4) & (ctrl9_xl.i3c_disable << 2) & (ctrl4_c.i2c_disable << 1) & ctrl3_c.sim) @@ -11730,25 +11687,37 @@ int32_t lsm6dsox_status_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, { ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_STATUS_REG_OIS, (uint8_t *)&spi2_status_reg_ois, 1); - val->ois_drdy_xl = spi2_status_reg_ois.xlda; - val->ois_drdy_g = spi2_status_reg_ois.gda; - val->ois_gyro_settling = spi2_status_reg_ois.gyro_settling; + + if (ret == 0) + { + val->ois_drdy_xl = spi2_status_reg_ois.xlda; + val->ois_drdy_g = spi2_status_reg_ois.gda; + val->ois_gyro_settling = spi2_status_reg_ois.gyro_settling; + } } if (ctx != NULL) { ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - val->sw_reset = ctrl3_c.sw_reset; - val->boot = ctrl3_c.boot; + + if (ret == 0) + { + val->sw_reset = ctrl3_c.sw_reset; + val->boot = ctrl3_c.boot; + } if ((ret == 0) && (ctrl3_c.sw_reset == PROPERTY_DISABLE) && (ctrl3_c.boot == PROPERTY_DISABLE)) { ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t *)&status_reg, 1); - val->drdy_xl = status_reg.xlda; - val->drdy_g = status_reg.gda; - val->drdy_temp = status_reg.tda; + + if (ret == 0) + { + val->drdy_xl = status_reg.xlda; + val->drdy_g = status_reg.gda; + val->drdy_temp = status_reg.tda; + } } if (aux_ctx == NULL) @@ -11757,9 +11726,13 @@ int32_t lsm6dsox_status_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, { ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_STATUS_REG_OIS, (uint8_t *)&ui_status_reg_ois, 1); - val->ois_drdy_xl = ui_status_reg_ois.xlda; - val->ois_drdy_g = ui_status_reg_ois.gda; - val->ois_gyro_settling = ui_status_reg_ois.gyro_settling; + + if (ret == 0) + { + val->ois_drdy_xl = ui_status_reg_ois.xlda; + val->ois_drdy_g = ui_status_reg_ois.gda; + val->ois_gyro_settling = ui_status_reg_ois.gyro_settling; + } } } } @@ -11785,34 +11758,27 @@ int32_t lsm6dsox_pin_conf_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); - if (ret == 0) - { - pin_ctrl.ois_pu_dis = ~val.aux_sdo_ocs_pull_up; - pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up; - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); - } + pin_ctrl.ois_pu_dis = ~val.aux_sdo_ocs_pull_up; + pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up; + ctrl3_c.pp_od = ~val.int1_int2_push_pull; + i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down; if (ret == 0) { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); } if (ret == 0) { - ctrl3_c.pp_od = ~val.int1_int2_push_pull; ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); } if (ret == 0) { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); - } - - if (ret == 0) - { - i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down; ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); } @@ -11838,24 +11804,16 @@ int32_t lsm6dsox_pin_conf_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); if (ret == 0) { val->aux_sdo_ocs_pull_up = ~pin_ctrl.ois_pu_dis; val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en; - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - } - - if (ret == 0) - { val->int1_int2_push_pull = ~ctrl3_c.pp_od; - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); - } - - if (ret == 0) - { - val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1; + val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1; } return ret; @@ -11878,22 +11836,19 @@ int32_t lsm6dsox_interrupt_mode_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1); - if (ret == 0) - { - ctrl3_c.h_lactive = val.active_low; - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - } + ctrl3_c.h_lactive = val.active_low; + tap_cfg0.lir = val.base_latched; + tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched; if (ret == 0) { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1); + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); } if (ret == 0) { - tap_cfg0.lir = val.base_latched; - tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched; ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1); } @@ -11901,22 +11856,19 @@ int32_t lsm6dsox_interrupt_mode_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - page_rw.emb_func_lir = val.emb_latched; - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + page_rw.emb_func_lir = val.emb_latched; + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } return ret; @@ -11939,32 +11891,29 @@ int32_t lsm6dsox_interrupt_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + ret += lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1); if (ret == 0) { val->active_low = ctrl3_c.h_lactive; - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1); + val->base_latched = (tap_cfg0.lir & tap_cfg0.int_clr_on_read); } if (ret == 0) { - val->base_latched = (tap_cfg0.lir & tap_cfg0.int_clr_on_read); ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1); + } - if (ret == 0) - { - val->emb_latched = (page_rw.emb_func_lir & tap_cfg0.int_clr_on_read); - } + if (ret == 0) + { + val->emb_latched = (page_rw.emb_func_lir & tap_cfg0.int_clr_on_read); + } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } return ret; @@ -12059,35 +12008,32 @@ int32_t lsm6dsox_pin_int1_route_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT1, - (uint8_t *)&mlc_int1, 1); - } + if (ret == 0) + { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT1, + (uint8_t *)&mlc_int1, 1); + } - if (ret == 0) - { - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT1, - (uint8_t *)&emb_func_int1, 1); - } + if (ret == 0) + { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT1, + (uint8_t *)&emb_func_int1, 1); + } - if (ret == 0) - { - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_A, - (uint8_t *)&fsm_int1_a, 1); - } + if (ret == 0) + { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_A, + (uint8_t *)&fsm_int1_a, 1); + } - if (ret == 0) - { - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_B, - (uint8_t *)&fsm_int1_b, 1); - } + if (ret == 0) + { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_B, + (uint8_t *)&fsm_int1_b, 1); + } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } if (ret == 0) @@ -12265,10 +12211,7 @@ int32_t lsm6dsox_pin_int1_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&fsm_int1_b, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); if (ret == 0) { @@ -12301,7 +12244,6 @@ int32_t lsm6dsox_pin_int1_route_get(const stmdev_ctx_t *ctx, val->timestamp = md2_cfg.int2_timestamp; } } - else { val->drdy_temp = PROPERTY_DISABLE; @@ -12462,35 +12404,32 @@ int32_t lsm6dsox_pin_int2_route_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT2, - (uint8_t *)&mlc_int2, 1); - } + if (ret == 0) + { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT2, + (uint8_t *)&mlc_int2, 1); + } - if (ret == 0) - { - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT2, - (uint8_t *)&emb_func_int2, 1); - } + if (ret == 0) + { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT2, + (uint8_t *)&emb_func_int2, 1); + } - if (ret == 0) - { - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_A, - (uint8_t *)&fsm_int2_a, 1); - } + if (ret == 0) + { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_A, + (uint8_t *)&fsm_int2_a, 1); + } - if (ret == 0) - { - ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_B, - (uint8_t *)&fsm_int2_b, 1); - } + if (ret == 0) + { + ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_B, + (uint8_t *)&fsm_int2_b, 1); + } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } if (ret == 0) @@ -12635,35 +12574,32 @@ int32_t lsm6dsox_pin_int2_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT2, - (uint8_t *)&mlc_int2, 1); - } + if (ret == 0) + { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT2, + (uint8_t *)&mlc_int2, 1); + } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT2, - (uint8_t *)&emb_func_int2, 1); - } + if (ret == 0) + { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT2, + (uint8_t *)&emb_func_int2, 1); + } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_A, - (uint8_t *)&fsm_int2_a, 1); - } + if (ret == 0) + { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_A, + (uint8_t *)&fsm_int2_a, 1); + } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_B, - (uint8_t *)&fsm_int2_b, 1); - } + if (ret == 0) + { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_B, + (uint8_t *)&fsm_int2_b, 1); + } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } if (ret == 0) @@ -12698,7 +12634,6 @@ int32_t lsm6dsox_pin_int2_route_get(const stmdev_ctx_t *ctx, val->timestamp = md2_cfg.int2_timestamp; } } - else { val->drdy_temp = PROPERTY_DISABLE; @@ -13489,31 +13424,28 @@ int32_t lsm6dsox_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, if (ret == 0) { ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B, reg, 2); - bytecpy((uint8_t *)&emb_func_odr_cfg_b, ®[0]); - bytecpy((uint8_t *)&emb_func_odr_cfg_c, ®[1]); - } + if (ret == 0) + { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B, reg, 2); + bytecpy((uint8_t *)&emb_func_odr_cfg_b, ®[0]); + bytecpy((uint8_t *)&emb_func_odr_cfg_c, ®[1]); + } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - } + if (ret == 0) + { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } - if (ret == 0) - { - ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, reg, 2); - bytecpy((uint8_t *)&fsm_enable_a, ®[0]); - bytecpy((uint8_t *)&fsm_enable_b, ®[1]); - } + if (ret == 0) + { + ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, reg, 2); + bytecpy((uint8_t *)&fsm_enable_a, ®[0]); + bytecpy((uint8_t *)&fsm_enable_b, ®[1]); + } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); } } @@ -14149,6 +14081,7 @@ int32_t lsm6dsox_data_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, if (ctx != NULL) { ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUT_TEMP_L, buff, 14); + if (ret != 0) { return ret; } } j = 0; @@ -14235,6 +14168,7 @@ int32_t lsm6dsox_data_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, { ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff, 12); + if (ret != 0) { return ret; } } } @@ -14243,6 +14177,7 @@ int32_t lsm6dsox_data_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, if ((ctx != NULL) && (md->ois.ctrl_md == LSM6DSOX_OIS_ONLY_UI)) { ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 12); + if (ret != 0) { return ret; } } } @@ -14370,10 +14305,7 @@ int32_t lsm6dsox_embedded_sens_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -14406,6 +14338,10 @@ int32_t lsm6dsox_embedded_sens_get(const stmdev_ctx_t *ctx, { ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + if (ret == 0) + { emb_sens->mlc = emb_func_en_b.mlc_en; emb_sens->fsm = emb_func_en_b.fsm_en; emb_sens->tilt = emb_func_en_a.tilt_en; @@ -14414,10 +14350,7 @@ int32_t lsm6dsox_embedded_sens_get(const stmdev_ctx_t *ctx, emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en; } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -14469,10 +14402,7 @@ int32_t lsm6dsox_embedded_sens_off(const stmdev_ctx_t *ctx) (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); - } + ret += lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK); return ret; } @@ -14486,5 +14416,3 @@ int32_t lsm6dsox_embedded_sens_off(const stmdev_ctx_t *ctx) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h index c492cc7..13aa5e9 100644 --- a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h +++ b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -4858,5 +4860,3 @@ int32_t lsm6dsox_embedded_sens_off(const stmdev_ctx_t *ctx); #endif #endif /*LSM6DSOX_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c index ee72da8..b51fc53 100644 --- a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c +++ b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -214,6 +213,10 @@ int32_t lsm6dsr_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1_xl.fs_xl) { @@ -407,6 +410,10 @@ int32_t lsm6dsr_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1_xl.odr_xl) { @@ -507,6 +514,10 @@ int32_t lsm6dsr_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2_g.fs_g) { @@ -708,6 +719,10 @@ int32_t lsm6dsr_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2_g.odr_g) { @@ -804,6 +819,11 @@ int32_t lsm6dsr_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.bdu; return ret; @@ -852,6 +872,10 @@ int32_t lsm6dsr_xl_offset_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.usr_off_w) { @@ -912,6 +936,10 @@ int32_t lsm6dsr_xl_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.xl_hm_mode) { @@ -972,6 +1000,10 @@ int32_t lsm6dsr_gy_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl7_g.g_hm_mode) { @@ -1033,11 +1065,13 @@ int32_t lsm6dsr_all_sources_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->status_reg, 1); } - if (ret == 0) + if (ret != 0) { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK); + return ret; } + ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK); + if (ret == 0) { ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS, @@ -1056,10 +1090,7 @@ int32_t lsm6dsr_all_sources_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_status_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -1098,6 +1129,11 @@ int32_t lsm6dsr_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.xlda; return ret; @@ -1119,6 +1155,11 @@ int32_t lsm6dsr_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.gda; return ret; @@ -1140,6 +1181,11 @@ int32_t lsm6dsr_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.tda; return ret; @@ -1306,6 +1352,11 @@ int32_t lsm6dsr_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7_g.usr_off_on_out; return ret; @@ -1378,6 +1429,11 @@ int32_t lsm6dsr_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl10_c.timestamp_en; return ret; @@ -1399,6 +1455,11 @@ int32_t lsm6dsr_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_TIMESTAMP0, buff, 4); + if (ret != 0) + { + return ret; + } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1462,6 +1523,10 @@ int32_t lsm6dsr_rounding_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.rounding) { @@ -1506,6 +1571,11 @@ int32_t lsm6dsr_temperature_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_OUT_TEMP_L, buff, 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1528,6 +1598,11 @@ int32_t lsm6dsr_angular_rate_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_OUTX_L_G, buff, 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1554,6 +1629,11 @@ int32_t lsm6dsr_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_OUTX_L_A, buff, 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1604,10 +1684,7 @@ int32_t lsm6dsr_number_of_steps_get(const stmdev_ctx_t *ctx, *val = (*val * 256U) + buff[0]; } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -1639,10 +1716,7 @@ int32_t lsm6dsr_steps_reset(const stmdev_ctx_t *ctx) (uint8_t *)&emb_func_src, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -1661,7 +1735,7 @@ int32_t lsm6dsr_steps_reset(const stmdev_ctx_t *ctx) /** * @brief Difference in percentage of the effective ODR (and timestamp rate) - * with respect to the typical.[set] + * with respect to the typical.[get] * Step: 0.15%. 8-bit format, 2's complement. * * @param ctx Read / write interface definitions.(ptr) @@ -1669,42 +1743,19 @@ int32_t lsm6dsr_steps_reset(const stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) { lsm6dsr_internal_freq_fine_t internal_freq_fine; int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); - - if (ret == 0) + if (ret != 0) { - internal_freq_fine.freq_fine = (uint8_t)val; - ret = lsm6dsr_write_reg(ctx, LSM6DSR_INTERNAL_FREQ_FINE, - (uint8_t *)&internal_freq_fine, 1); + return ret; } - return ret; -} - -/** - * @brief Difference in percentage of the effective ODR (and timestamp rate) - * with respect to the typical.[get] - * Step: 0.15%. 8-bit format, 2's complement. - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lsm6dsr_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6dsr_internal_freq_fine_t internal_freq_fine; - int32_t ret; - - ret = lsm6dsr_read_reg(ctx, LSM6DSR_INTERNAL_FREQ_FINE, - (uint8_t *)&internal_freq_fine, 1); - *val = internal_freq_fine.freq_fine; + *val = (int8_t)internal_freq_fine.freq_fine; return ret; } @@ -1754,6 +1805,10 @@ int32_t lsm6dsr_mem_bank_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } switch (func_cfg_access.reg_access) { @@ -1789,71 +1844,7 @@ int32_t lsm6dsr_mem_bank_get(const stmdev_ctx_t *ctx, int32_t lsm6dsr_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { - lsm6dsr_page_rw_t page_rw; - lsm6dsr_page_sel_t page_sel; - lsm6dsr_page_address_t page_address; - int32_t ret; - - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x02U; /* page_write enable */ - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - - if (ret == 0) - { - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_VALUE, val, 1); - } - - if (ret == 0) - { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } - - return ret; + return lsm6dsr_ln_pg_write(ctx, add, val, 1); } /** @@ -1877,98 +1868,105 @@ int32_t lsm6dsr_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, int32_t ret; uint8_t i ; - msb = (uint8_t)((add / 256U) & 0x0FU); + msb = (uint8_t)((add >> 8) & 0x0FU); lsb = (uint8_t)(add - (msb * 256U)); - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK); - if (ret == 0) + ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK); + if (ret != 0) { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); + return ret; } - if (ret == 0) + /* set page write */ + ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, + (uint8_t *)&page_rw, 1); + if (ret != 0) { - page_rw.page_rw = 0x02U; /* page_write enable*/ - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } + page_rw.page_rw = 0x02U; /* page_write enable*/ + ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, + (uint8_t *)&page_rw, 1); - if (ret == 0) + /* select page */ + ret += lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - if (ret == 0) + /* set page addr */ + page_address.page_addr = lsb; + ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { - page_address.page_addr = lsb; - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + goto exit; } for (i = 0; i < len; i++) { - if (ret == 0) + ret += lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_VALUE, &buf[i], 1); + goto exit; + } - if (ret == 0) - { - /* Check if page wrap */ - if (lsb == 0x00U) - { - msb++; - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } + lsb++; - lsb++; + /* Check if page wrap */ + if (lsb == 0x00U) + { + msb++; + ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; // Default value + ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } } } - if (ret == 0) - { - page_sel.page_sel = 0; - page_sel.not_used_01 = 1; - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - - if (ret == 0) + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; // Default value + ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + /* unset page write */ + ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, + (uint8_t *)&page_rw, 1); + if (ret != 0) { - page_rw.page_rw = 0x00U; /* page_write disable */ - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } + page_rw.page_rw = 0x00U; /* page_write disable */ + ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, + (uint8_t *)&page_rw, 1); - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } +exit: + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -1991,63 +1989,67 @@ int32_t lsm6dsr_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, int32_t ret; ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) + if (ret != 0) { - page_rw.page_rw = 0x01U; /* page_read enable*/ - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); + return ret; } - if (ret == 0) + /* set page write */ + ret += lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, + (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } + page_rw.page_rw = 0x01U; /* page_read enable*/ + ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, + (uint8_t *)&page_rw, 1); - if (ret == 0) + /* select page */ + ret += lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - - if (ret == 0) + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; // Default value + ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + goto exit; } - if (ret == 0) + /* set page addr */ + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_VALUE, val, 2); + goto exit; } - if (ret == 0) + /* read value */ + ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_VALUE, val, 2); + if (ret != 0) { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + /* unset page read */ + ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, + (uint8_t *)&page_rw, 1); + if (ret != 0) { - page_rw.page_rw = 0x00U; /* page_read disable */ - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } + page_rw.page_rw = 0x00U; /* page_read disable */ + ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, + (uint8_t *)&page_rw, 1); - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } +exit: + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -2097,6 +2099,10 @@ int32_t lsm6dsr_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } switch (counter_bdr_reg1.dataready_pulsed) { @@ -2174,6 +2180,11 @@ int32_t lsm6dsr_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.sw_reset; return ret; @@ -2222,6 +2233,11 @@ int32_t lsm6dsr_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.if_inc; return ret; @@ -2268,6 +2284,11 @@ int32_t lsm6dsr_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.boot; return ret; @@ -2318,6 +2339,10 @@ int32_t lsm6dsr_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_xl) { @@ -2384,6 +2409,10 @@ int32_t lsm6dsr_gy_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_g) { @@ -2461,6 +2490,11 @@ int32_t lsm6dsr_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl1_xl.lpf2_xl_en; return ret; @@ -2509,6 +2543,11 @@ int32_t lsm6dsr_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.lpf1_sel_g; return ret; @@ -2523,8 +2562,7 @@ int32_t lsm6dsr_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_filter_settling_mask_set(const stmdev_ctx_t *ctx, - uint8_t val) +int32_t lsm6dsr_drdy_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2551,14 +2589,18 @@ int32_t lsm6dsr_filter_settling_mask_set(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_filter_settling_mask_get(const stmdev_ctx_t *ctx, - uint8_t *val) +int32_t lsm6dsr_drdy_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl4_c_t ctrl4_c; int32_t ret; ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.drdy_mask; return ret; @@ -2607,6 +2649,10 @@ int32_t lsm6dsr_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.ftype) { @@ -2691,6 +2737,11 @@ int32_t lsm6dsr_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.low_pass_on_6d; return ret; @@ -2743,6 +2794,10 @@ int32_t lsm6dsr_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) + @@ -2895,6 +2950,11 @@ int32_t lsm6dsr_xl_fast_settling_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.fastsettl_mode_xl; return ret; @@ -2945,6 +3005,10 @@ int32_t lsm6dsr_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } switch (tap_cfg0.slope_fds) { @@ -3010,6 +3074,10 @@ int32_t lsm6dsr_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g) { @@ -3099,6 +3167,10 @@ int32_t lsm6dsr_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch (pin_ctrl.ois_pu_dis) { @@ -3162,6 +3234,10 @@ int32_t lsm6dsr_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl7_g.ois_on) { @@ -3216,6 +3292,11 @@ int32_t lsm6dsr_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX, (uint8_t *)&status_spiaux, 1); + if (ret != 0) + { + return ret; + } + *val = status_spiaux.xlda; return ret; @@ -3237,6 +3318,11 @@ int32_t lsm6dsr_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX, (uint8_t *)&status_spiaux, 1); + if (ret != 0) + { + return ret; + } + *val = status_spiaux.gda; return ret; @@ -3258,6 +3344,11 @@ int32_t lsm6dsr_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX, (uint8_t *)&status_spiaux, 1); + if (ret != 0) + { + return ret; + } + *val = status_spiaux.gyro_settling; return ret; @@ -3308,6 +3399,10 @@ int32_t lsm6dsr_aux_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1); + if (ret != 0) + { + return ret; + } switch (int_ois.st_xl_ois) { @@ -3374,6 +3469,10 @@ int32_t lsm6dsr_aux_den_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1); + if (ret != 0) + { + return ret; + } switch (int_ois.den_lh_ois) { @@ -3452,10 +3551,12 @@ int32_t lsm6dsr_aux_den_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1); - if (ret == 0) + ret += lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, + (uint8_t *)&ctrl1_ois, 1); + + if (ret != 0) { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); + return ret; } switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) @@ -3525,6 +3626,11 @@ int32_t lsm6dsr_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1); + if (ret != 0) + { + return ret; + } + *val = int_ois.int2_drdy_ois; return ret; @@ -3585,6 +3691,10 @@ int32_t lsm6dsr_aux_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2)) { @@ -3652,6 +3762,10 @@ int32_t lsm6dsr_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl1_ois.fs_125_ois << 2) + ctrl1_ois.fs_g_ois) { @@ -3726,6 +3840,10 @@ int32_t lsm6dsr_aux_spi_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1_ois.sim_ois) { @@ -3788,6 +3906,10 @@ int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2_ois.ftype_ois) { @@ -3859,6 +3981,10 @@ int32_t lsm6dsr_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois) { @@ -3937,6 +4063,10 @@ int32_t lsm6dsr_aux_gy_clamp_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_ois.st_ois_clampdis) { @@ -3999,6 +4129,10 @@ int32_t lsm6dsr_aux_gy_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_ois.st_ois) { @@ -4065,6 +4199,10 @@ int32_t lsm6dsr_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_ois.filter_xl_conf_ois) { @@ -4151,6 +4289,10 @@ int32_t lsm6dsr_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_ois.fs_xl_ois) { @@ -4234,6 +4376,10 @@ int32_t lsm6dsr_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch (pin_ctrl.sdo_pu_en) { @@ -4296,6 +4442,10 @@ int32_t lsm6dsr_int1_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); + if (ret != 0) + { + return ret; + } switch (i3c_bus_avb.pd_dis_int1) { @@ -4358,6 +4508,10 @@ int32_t lsm6dsr_spi_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.sim) { @@ -4420,6 +4574,10 @@ int32_t lsm6dsr_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4_c.i2c_disable) { @@ -4496,10 +4654,11 @@ int32_t lsm6dsr_i3c_disable_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - if (ret == 0) + ret += lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + if (ret != 0) { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); + return ret; } switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel) @@ -4580,10 +4739,7 @@ int32_t lsm6dsr_pin_int1_route_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int1_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); if (ret == 0) { @@ -4698,10 +4854,7 @@ int32_t lsm6dsr_pin_int1_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int1_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); if (ret == 0) { @@ -4753,10 +4906,7 @@ int32_t lsm6dsr_pin_int2_route_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int2_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); if (ret == 0) { @@ -4869,10 +5019,7 @@ int32_t lsm6dsr_pin_int2_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int2_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); if (ret == 0) { @@ -4932,6 +5079,10 @@ int32_t lsm6dsr_pin_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.pp_od) { @@ -4994,6 +5145,10 @@ int32_t lsm6dsr_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.h_lactive) { @@ -5054,6 +5209,11 @@ int32_t lsm6dsr_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.int2_on_int1; return ret; @@ -5088,24 +5248,21 @@ int32_t lsm6dsr_int_notification_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, + (uint8_t *)&page_rw, 1); + } - if (ret == 0) - { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, + (uint8_t *)&page_rw, 1); + } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } return ret; @@ -5133,17 +5290,19 @@ int32_t lsm6dsr_int_notification_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, - (uint8_t *)&page_rw, 1); + if (ret == 0) + { + ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, + (uint8_t *)&page_rw, 1); + } + + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } - if (ret == 0) + if (ret != 0) { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir) @@ -5232,6 +5391,10 @@ int32_t lsm6dsr_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } switch (wake_up_dur.wake_ths_w) { @@ -5294,6 +5457,11 @@ int32_t lsm6dsr_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.wk_ths; return ret; @@ -5342,6 +5510,11 @@ int32_t lsm6dsr_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.usr_off_on_wu; return ret; @@ -5388,6 +5561,11 @@ int32_t lsm6dsr_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.wake_dur; return ret; @@ -5447,6 +5625,11 @@ int32_t lsm6dsr_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.sleep_g; return ret; @@ -5499,6 +5682,10 @@ int32_t lsm6dsr_act_pin_notification_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } switch (tap_cfg0. sleep_status_on_int) { @@ -5561,6 +5748,11 @@ int32_t lsm6dsr_act_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg2.inact_en) { @@ -5629,6 +5821,11 @@ int32_t lsm6dsr_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.sleep_dur; return ret; @@ -5690,6 +5887,11 @@ int32_t lsm6dsr_tap_detection_on_z_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.tap_z_en; return ret; @@ -5738,6 +5940,11 @@ int32_t lsm6dsr_tap_detection_on_y_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.tap_y_en; return ret; @@ -5786,6 +5993,11 @@ int32_t lsm6dsr_tap_detection_on_x_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.tap_x_en; return ret; @@ -5833,6 +6045,11 @@ int32_t lsm6dsr_tap_threshold_x_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg1.tap_ths_x; return ret; @@ -5881,6 +6098,10 @@ int32_t lsm6dsr_tap_axis_priority_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) + { + return ret; + } switch (tap_cfg1.tap_priority) { @@ -5958,6 +6179,11 @@ int32_t lsm6dsr_tap_threshold_y_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg2.tap_ths_y; return ret; @@ -6005,6 +6231,11 @@ int32_t lsm6dsr_tap_threshold_z_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = tap_ths_6d.tap_ths_z; return ret; @@ -6059,6 +6290,11 @@ int32_t lsm6dsr_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1); + if (ret != 0) + { + return ret; + } + *val = int_dur2.shock; return ret; @@ -6113,6 +6349,11 @@ int32_t lsm6dsr_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1); + if (ret != 0) + { + return ret; + } + *val = int_dur2.quiet; return ret; @@ -6169,6 +6410,11 @@ int32_t lsm6dsr_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1); + if (ret != 0) + { + return ret; + } + *val = int_dur2.dur; return ret; @@ -6217,6 +6463,10 @@ int32_t lsm6dsr_tap_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } switch (wake_up_ths.single_double_tap) { @@ -6292,6 +6542,10 @@ int32_t lsm6dsr_6d_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } switch (tap_ths_6d.sixd_ths) { @@ -6360,6 +6614,11 @@ int32_t lsm6dsr_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = tap_ths_6d.d4d_en; return ret; @@ -6421,6 +6680,10 @@ int32_t lsm6dsr_ff_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -6526,6 +6789,10 @@ int32_t lsm6dsr_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL, (uint8_t *)&free_fall, 1); } + if (ret != 0) + { + return ret; + } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -6592,6 +6859,11 @@ int32_t lsm6dsr_fifo_watermark_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); ret += lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.wtm; *val = (*val * 256U) + fifo_ctrl1.wtm;; @@ -6627,10 +6899,7 @@ int32_t lsm6dsr_compression_algo_init_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_init_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -6661,9 +6930,10 @@ int32_t lsm6dsr_compression_algo_init_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_init_b.fifo_compr_init; - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -6697,10 +6967,7 @@ int32_t lsm6dsr_compression_algo_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); if (ret == 0) { @@ -6739,6 +7006,10 @@ int32_t lsm6dsr_compression_algo_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } switch ((fifo_ctrl2.fifo_compr_rt_en << 2) + fifo_ctrl2.uncoptr_rate) @@ -6814,6 +7085,11 @@ int32_t lsm6dsr_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odrchg_en; return ret; @@ -6862,6 +7138,11 @@ int32_t lsm6dsr_compression_algo_real_time_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.fifo_compr_rt_en; return ret; @@ -6912,6 +7193,11 @@ int32_t lsm6dsr_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -6962,6 +7248,10 @@ int32_t lsm6dsr_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_xl) { @@ -7066,6 +7356,10 @@ int32_t lsm6dsr_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_gy) { @@ -7168,6 +7462,10 @@ int32_t lsm6dsr_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.fifo_mode) { @@ -7248,6 +7546,10 @@ int32_t lsm6dsr_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.odr_t_batch) { @@ -7323,6 +7625,10 @@ int32_t lsm6dsr_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.odr_ts_batch) { @@ -7397,6 +7703,10 @@ int32_t lsm6dsr_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } switch (counter_bdr_reg1.trig_counter_bdr) { @@ -7461,6 +7771,11 @@ int32_t lsm6dsr_rst_batch_counter_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + *val = counter_bdr_reg1.rst_counter_bdr; return ret; @@ -7522,10 +7837,12 @@ int32_t lsm6dsr_batch_counter_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); - if (ret == 0) + ret += lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + + if (ret != 0) { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); + return ret; } *val = counter_bdr_reg1.cnt_bdr_th; @@ -7675,6 +7992,10 @@ int32_t lsm6dsr_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_data_out_tag, 1); + if (ret != 0) + { + return ret; + } switch (fifo_data_out_tag.tag_sensor) { @@ -7750,18 +8071,6 @@ int32_t lsm6dsr_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, *val = LSM6DSR_STEP_CPUNTER_TAG; break; - case LSM6DSR_GAME_ROTATION_TAG: - *val = LSM6DSR_GAME_ROTATION_TAG; - break; - - case LSM6DSR_GEOMAG_ROTATION_TAG: - *val = LSM6DSR_GEOMAG_ROTATION_TAG; - break; - - case LSM6DSR_ROTATION_TAG: - *val = LSM6DSR_ROTATION_TAG; - break; - case LSM6DSR_SENSORHUB_NACK_TAG: *val = LSM6DSR_SENSORHUB_NACK_TAG; break; @@ -7803,10 +8112,7 @@ int32_t lsm6dsr_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_fifo_cfg, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -7835,10 +8141,7 @@ int32_t lsm6dsr_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, *val = emb_func_fifo_cfg.pedo_fifo_en; } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -7872,10 +8175,7 @@ int32_t lsm6dsr_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -7906,9 +8206,10 @@ int32_t lsm6dsr_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = slv0_config. batch_ext_sens_0_en; - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -7942,10 +8243,7 @@ int32_t lsm6dsr_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -7971,14 +8269,15 @@ int32_t lsm6dsr_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, { ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); - *val = slv1_config. batch_ext_sens_1_en; } if (ret == 0) { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + *val = slv1_config. batch_ext_sens_1_en; } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -8012,10 +8311,7 @@ int32_t lsm6dsr_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -8046,9 +8342,10 @@ int32_t lsm6dsr_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = slv2_config. batch_ext_sens_2_en; - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -8082,10 +8379,7 @@ int32_t lsm6dsr_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -8111,14 +8405,15 @@ int32_t lsm6dsr_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, { ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); - *val = slv3_config. batch_ext_sens_3_en; } if (ret == 0) { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + *val = slv3_config. batch_ext_sens_3_en; } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -8178,6 +8473,10 @@ int32_t lsm6dsr_den_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.den_mode) { @@ -8252,6 +8551,10 @@ int32_t lsm6dsr_den_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_lh) { @@ -8314,6 +8617,10 @@ int32_t lsm6dsr_den_enable_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_xl_g) { @@ -8379,6 +8686,11 @@ int32_t lsm6dsr_den_mark_axis_x_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_z; return ret; @@ -8426,6 +8738,11 @@ int32_t lsm6dsr_den_mark_axis_y_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_y; return ret; @@ -8449,7 +8766,7 @@ int32_t lsm6dsr_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) if (ret == 0) { - ctrl9_xl.den_x = (uint8_t)val; + ctrl9_xl.den_z = (uint8_t)val; ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); } @@ -8473,7 +8790,12 @@ int32_t lsm6dsr_den_mark_axis_z_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - *val = ctrl9_xl.den_x; + if (ret != 0) + { + return ret; + } + + *val = ctrl9_xl.den_z; return ret; } @@ -8518,10 +8840,7 @@ int32_t lsm6dsr_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_a, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -8545,14 +8864,15 @@ int32_t lsm6dsr_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - *val = emb_func_en_a.pedo_en; } if (ret == 0) { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + *val = emb_func_en_a.pedo_en; } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -8601,10 +8921,7 @@ int32_t lsm6dsr_pedo_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); if (ret == 0) { @@ -8642,6 +8959,10 @@ int32_t lsm6dsr_pedo_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg); + if (ret != 0) + { + return ret; + } switch ((pedo_cmd_reg.ad_det_en << 1) | pedo_cmd_reg.fp_rejection_en) @@ -8689,10 +9010,7 @@ int32_t lsm6dsr_pedo_step_detect_get(const stmdev_ctx_t *ctx, *val = emb_func_status.is_step_det; } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -8784,8 +9102,11 @@ int32_t lsm6dsr_pedo_steps_period_get(const stmdev_ctx_t *ctx, { ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -8833,6 +9154,11 @@ int32_t lsm6dsr_pedo_adv_detection_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg); + if (ret != 0) + { + return ret; + } + *val = pedo_cmd_reg.ad_det_en; return ret; @@ -8881,6 +9207,11 @@ int32_t lsm6dsr_pedo_false_step_rejection_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg); + if (ret != 0) + { + return ret; + } + *val = pedo_cmd_reg.fp_rejection_en; return ret; @@ -8931,6 +9262,10 @@ int32_t lsm6dsr_pedo_int_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg); + if (ret != 0) + { + return ret; + } switch (pedo_cmd_reg.carry_count_en) { @@ -8991,10 +9326,7 @@ int32_t lsm6dsr_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_a, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -9023,9 +9355,10 @@ int32_t lsm6dsr_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_en_a.sign_motion_en; - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -9054,9 +9387,10 @@ int32_t lsm6dsr_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_sigmot; - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -9101,10 +9435,7 @@ int32_t lsm6dsr_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_a, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -9133,9 +9464,10 @@ int32_t lsm6dsr_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_en_a.tilt_en; - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -9164,9 +9496,10 @@ int32_t lsm6dsr_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_tilt; - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -9228,14 +9561,16 @@ int32_t lsm6dsr_mag_sensitivity_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SENSITIVITY_L, &buff[0]); - if (ret == 0) + ret += lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SENSITIVITY_H, + &buff[1]); + if (ret != 0) { - ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SENSITIVITY_H, - &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + return ret; } + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + return ret; } @@ -9340,7 +9675,10 @@ int32_t lsm6dsr_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { i++; ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFZ_H, &buff[i]); + } + if (ret == 0) + { val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -9567,18 +9905,21 @@ int32_t lsm6dsr_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) &buff[i]); } - val[0] = buff[1]; - val[0] = (val[0] * 256U) + buff[0]; - val[1] = buff[3]; - val[1] = (val[1] * 256U) + buff[2]; - val[2] = buff[5]; - val[2] = (val[2] * 256U) + buff[4]; - val[3] = buff[7]; - val[3] = (val[3] * 256U) + buff[6]; - val[4] = buff[9]; - val[4] = (val[4] * 256U) + buff[8]; - val[5] = buff[11]; - val[6] = (val[5] * 256U) + buff[10]; + if (ret == 0) + { + val[0] = buff[1]; + val[0] = (val[0] * 256U) + buff[0]; + val[1] = buff[3]; + val[1] = (val[1] * 256U) + buff[2]; + val[2] = buff[5]; + val[2] = (val[2] * 256U) + buff[4]; + val[3] = buff[7]; + val[3] = (val[3] * 256U) + buff[6]; + val[4] = buff[9]; + val[4] = (val[4] * 256U) + buff[8]; + val[5] = buff[11]; + val[6] = (val[5] * 256U) + buff[10]; + } return ret; } @@ -9628,6 +9969,10 @@ int32_t lsm6dsr_mag_z_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A, (uint8_t *)&mag_cfg_a); + if (ret != 0) + { + return ret; + } switch (mag_cfg_a.mag_z_axis) { @@ -9709,6 +10054,10 @@ int32_t lsm6dsr_mag_y_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A, (uint8_t *)&mag_cfg_a); + if (ret != 0) + { + return ret; + } switch (mag_cfg_a.mag_y_axis) { @@ -9789,6 +10138,10 @@ int32_t lsm6dsr_mag_x_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_B, (uint8_t *)&mag_cfg_b); + if (ret != 0) + { + return ret; + } switch (mag_cfg_b.mag_x_axis) { @@ -9863,9 +10216,10 @@ int32_t lsm6dsr_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_fsm_lc; - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -9897,10 +10251,7 @@ int32_t lsm6dsr_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -9933,10 +10284,7 @@ int32_t lsm6dsr_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10009,10 +10357,7 @@ int32_t lsm6dsr_fsm_enable_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10044,10 +10389,7 @@ int32_t lsm6dsr_fsm_enable_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_enable_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10076,10 +10418,7 @@ int32_t lsm6dsr_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) 2); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10104,14 +10443,14 @@ int32_t lsm6dsr_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10146,10 +10485,7 @@ int32_t lsm6dsr_long_clr_set(const stmdev_ctx_t *ctx, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10176,9 +10512,11 @@ int32_t lsm6dsr_long_clr_get(const stmdev_ctx_t *ctx, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + + if (ret != 0) { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } switch (fsm_long_counter_clear.fsm_lc_clr) @@ -10224,10 +10562,7 @@ int32_t lsm6dsr_fsm_out_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_outs1, 16); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10263,10 +10598,7 @@ int32_t lsm6dsr_fsm_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10293,9 +10625,11 @@ int32_t lsm6dsr_fsm_data_rate_get(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + + if (ret != 0) { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } switch (emb_func_odr_cfg_b.fsm_odr) @@ -10352,10 +10686,7 @@ int32_t lsm6dsr_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_init_b, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10384,9 +10715,10 @@ int32_t lsm6dsr_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_init_b.fsm_init; - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -10445,8 +10777,11 @@ int32_t lsm6dsr_long_cnt_int_value_get(const stmdev_ctx_t *ctx, { ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -10467,13 +10802,6 @@ int32_t lsm6dsr_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_PROGRAMS, buff); - if (ret == 0) - { - ret = lsm6dsr_ln_pg_write_byte(ctx, - LSM6DSR_FSM_PROGRAMS + 0x01U, - buff); - } - return ret; } @@ -10546,8 +10874,11 @@ int32_t lsm6dsr_fsm_start_address_get(const stmdev_ctx_t *ctx, { ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_START_ADD_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -10574,8 +10905,7 @@ int32_t lsm6dsr_fsm_start_address_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_read_data_raw_get(const stmdev_ctx_t *ctx, - lsm6dsr_emb_sh_read_t *val, +int32_t lsm6dsr_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len) { int32_t ret; @@ -10588,10 +10918,7 @@ int32_t lsm6dsr_sh_read_data_raw_get(const stmdev_ctx_t *ctx, (uint8_t *)val, len); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10625,10 +10952,7 @@ int32_t lsm6dsr_sh_slave_connected_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10655,9 +10979,11 @@ int32_t lsm6dsr_sh_slave_connected_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + + if (ret != 0) { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } switch (master_config.aux_sens_on) @@ -10714,10 +11040,7 @@ int32_t lsm6dsr_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10746,9 +11069,10 @@ int32_t lsm6dsr_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = master_config.master_on; - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -10781,10 +11105,7 @@ int32_t lsm6dsr_sh_pin_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10811,9 +11132,11 @@ int32_t lsm6dsr_sh_pin_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + + if (ret != 0) { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } switch (master_config.shub_pu_en) @@ -10862,10 +11185,7 @@ int32_t lsm6dsr_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10895,9 +11215,10 @@ int32_t lsm6dsr_sh_pass_through_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = master_config.pass_through_mode; - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } @@ -10930,10 +11251,7 @@ int32_t lsm6dsr_sh_syncro_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -10960,9 +11278,11 @@ int32_t lsm6dsr_sh_syncro_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + + if (ret != 0) { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } switch (master_config.start_config) @@ -11013,10 +11333,7 @@ int32_t lsm6dsr_sh_write_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -11044,10 +11361,7 @@ int32_t lsm6dsr_sh_write_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); switch (master_config.write_once) { @@ -11101,10 +11415,7 @@ int32_t lsm6dsr_sh_reset_set(const stmdev_ctx_t *ctx) (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -11131,10 +11442,7 @@ int32_t lsm6dsr_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) *val = master_config.rst_master_regs; } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -11168,10 +11476,7 @@ int32_t lsm6dsr_sh_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -11198,9 +11503,11 @@ int32_t lsm6dsr_sh_data_rate_get(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + + if (ret != 0) { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); + return ret; } switch (slv0_config.shub_odr) @@ -11268,10 +11575,7 @@ int32_t lsm6dsr_sh_cfg_write(const stmdev_ctx_t *ctx, (uint8_t *) & (val->slv0_data), 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -11323,10 +11627,7 @@ int32_t lsm6dsr_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -11378,10 +11679,7 @@ int32_t lsm6dsr_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -11433,10 +11731,7 @@ int32_t lsm6dsr_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -11488,10 +11783,7 @@ int32_t lsm6dsr_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -11517,10 +11809,7 @@ int32_t lsm6dsr_sh_status_get(const stmdev_ctx_t *ctx, (uint8_t *)val, 1); } - if (ret == 0) - { - ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); - } + ret += lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK); return ret; } @@ -11580,6 +11869,11 @@ int32_t lsm6dsr_s4s_tph_res_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1); + if (ret != 0) + { + return ret; + } + switch (s4s_tph_l.tph_h_sel) { case LSM6DSR_S4S_TPH_7bit: @@ -11654,10 +11948,12 @@ int32_t lsm6dsr_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1); - if (ret == 0) + ret += lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_H, + (uint8_t *)&s4s_tph_h, 1); + + if (ret != 0) { - ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_H, - (uint8_t *)&s4s_tph_h, 1); + return ret; } *val = s4s_tph_h.tph_h; @@ -11708,6 +12004,11 @@ int32_t lsm6dsr_s4s_res_ratio_get(const stmdev_ctx_t *ctx, ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_RR, (uint8_t *)&s4s_rr, 1); + if (ret != 0) + { + return ret; + } + switch (s4s_rr.rr) { case LSM6DSR_S4S_DT_RES_11: @@ -11775,6 +12076,11 @@ int32_t lsm6dsr_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_ST_CMD_CODE, (uint8_t *)&s4s_st_cmd_code, 1); + if (ret != 0) + { + return ret; + } + *val = s4s_st_cmd_code.s4s_st_cmd_code; return ret; @@ -11821,6 +12127,11 @@ int32_t lsm6dsr_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_DT_REG, (uint8_t *)&s4s_dt_reg, 1); + if (ret != 0) + { + return ret; + } + *val = s4s_dt_reg.dt; return ret; @@ -11836,4 +12147,3 @@ int32_t lsm6dsr_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val) * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h index ef39929..c5ece76 100644 --- a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h +++ b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -131,38 +133,6 @@ typedef struct #endif /* MEMS_SHARED_TYPES */ -#ifndef MEMS_UCF_SHARED_TYPES -#define MEMS_UCF_SHARED_TYPES - -/** @defgroup Generic address-data structure definition - * @brief This structure is useful to load a predefined configuration - * of a sensor. - * You can create a sensor configuration by your own or using - * Unico / Unicleo tools available on STMicroelectronics - * web site. - * - * @{ - * - */ - -typedef struct -{ - uint8_t address; - uint8_t data; -} ucf_line_t; - -/** - * @} - * - */ - -#endif /* MEMS_UCF_SHARED_TYPES */ - -/** - * @} - * - */ - /** @defgroup LSM6DSR Infos * @{ * @@ -2642,154 +2612,6 @@ typedef struct #endif /* DRV_BYTE_ORDER */ } lsm6dsr_status_master_t; -/** - * @} - * - */ - -/** - * @defgroup LSM6DSR_Register_Union - * @brief This union group all the registers having a bit-field - * description. - * This union is useful but it's not needed by the driver. - * - * REMOVING this union you are compliant with: - * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " - * - * @{ - * - */ -typedef union -{ - lsm6dsr_func_cfg_access_t func_cfg_access; - lsm6dsr_pin_ctrl_t pin_ctrl; - lsm6dsr_s4s_tph_l_t s4s_tph_l; - lsm6dsr_s4s_tph_h_t s4s_tph_h; - lsm6dsr_s4s_rr_t s4s_rr; - lsm6dsr_fifo_ctrl1_t fifo_ctrl1; - lsm6dsr_fifo_ctrl2_t fifo_ctrl2; - lsm6dsr_fifo_ctrl3_t fifo_ctrl3; - lsm6dsr_fifo_ctrl4_t fifo_ctrl4; - lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1; - lsm6dsr_counter_bdr_reg2_t counter_bdr_reg2; - lsm6dsr_int1_ctrl_t int1_ctrl; - lsm6dsr_int2_ctrl_t int2_ctrl; - lsm6dsr_ctrl1_xl_t ctrl1_xl; - lsm6dsr_ctrl2_g_t ctrl2_g; - lsm6dsr_ctrl3_c_t ctrl3_c; - lsm6dsr_ctrl4_c_t ctrl4_c; - lsm6dsr_ctrl5_c_t ctrl5_c; - lsm6dsr_ctrl6_c_t ctrl6_c; - lsm6dsr_ctrl7_g_t ctrl7_g; - lsm6dsr_ctrl8_xl_t ctrl8_xl; - lsm6dsr_ctrl9_xl_t ctrl9_xl; - lsm6dsr_ctrl10_c_t ctrl10_c; - lsm6dsr_all_int_src_t all_int_src; - lsm6dsr_wake_up_src_t wake_up_src; - lsm6dsr_tap_src_t tap_src; - lsm6dsr_d6d_src_t d6d_src; - lsm6dsr_status_reg_t status_reg; - lsm6dsr_status_spiaux_t status_spiaux; - lsm6dsr_fifo_status1_t fifo_status1; - lsm6dsr_fifo_status2_t fifo_status2; - lsm6dsr_tap_cfg0_t tap_cfg0; - lsm6dsr_tap_cfg1_t tap_cfg1; - lsm6dsr_tap_cfg2_t tap_cfg2; - lsm6dsr_tap_ths_6d_t tap_ths_6d; - lsm6dsr_int_dur2_t int_dur2; - lsm6dsr_wake_up_ths_t wake_up_ths; - lsm6dsr_wake_up_dur_t wake_up_dur; - lsm6dsr_free_fall_t free_fall; - lsm6dsr_md1_cfg_t md1_cfg; - lsm6dsr_md2_cfg_t md2_cfg; - lsm6dsr_s4s_st_cmd_code_t s4s_st_cmd_code; - lsm6dsr_s4s_dt_reg_t s4s_dt_reg; - lsm6dsr_i3c_bus_avb_t i3c_bus_avb; - lsm6dsr_internal_freq_fine_t internal_freq_fine; - lsm6dsr_int_ois_t int_ois; - lsm6dsr_ctrl1_ois_t ctrl1_ois; - lsm6dsr_ctrl2_ois_t ctrl2_ois; - lsm6dsr_ctrl3_ois_t ctrl3_ois; - lsm6dsr_fifo_data_out_tag_t fifo_data_out_tag; - lsm6dsr_page_sel_t page_sel; - lsm6dsr_emb_func_en_a_t emb_func_en_a; - lsm6dsr_emb_func_en_b_t emb_func_en_b; - lsm6dsr_page_address_t page_address; - lsm6dsr_page_value_t page_value; - lsm6dsr_emb_func_int1_t emb_func_int1; - lsm6dsr_fsm_int1_a_t fsm_int1_a; - lsm6dsr_fsm_int1_b_t fsm_int1_b; - lsm6dsr_emb_func_int2_t emb_func_int2; - lsm6dsr_fsm_int2_a_t fsm_int2_a; - lsm6dsr_fsm_int2_b_t fsm_int2_b; - lsm6dsr_emb_func_status_t emb_func_status; - lsm6dsr_fsm_status_a_t fsm_status_a; - lsm6dsr_fsm_status_b_t fsm_status_b; - lsm6dsr_page_rw_t page_rw; - lsm6dsr_emb_func_fifo_cfg_t emb_func_fifo_cfg; - lsm6dsr_fsm_enable_a_t fsm_enable_a; - lsm6dsr_fsm_enable_b_t fsm_enable_b; - lsm6dsr_fsm_long_counter_clear_t fsm_long_counter_clear; - lsm6dsr_fsm_outs1_t fsm_outs1; - lsm6dsr_fsm_outs2_t fsm_outs2; - lsm6dsr_fsm_outs3_t fsm_outs3; - lsm6dsr_fsm_outs4_t fsm_outs4; - lsm6dsr_fsm_outs5_t fsm_outs5; - lsm6dsr_fsm_outs6_t fsm_outs6; - lsm6dsr_fsm_outs7_t fsm_outs7; - lsm6dsr_fsm_outs8_t fsm_outs8; - lsm6dsr_fsm_outs9_t fsm_outs9; - lsm6dsr_fsm_outs10_t fsm_outs10; - lsm6dsr_fsm_outs11_t fsm_outs11; - lsm6dsr_fsm_outs12_t fsm_outs12; - lsm6dsr_fsm_outs13_t fsm_outs13; - lsm6dsr_fsm_outs14_t fsm_outs14; - lsm6dsr_fsm_outs15_t fsm_outs15; - lsm6dsr_fsm_outs16_t fsm_outs16; - lsm6dsr_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; - lsm6dsr_emb_func_src_t emb_func_src; - lsm6dsr_emb_func_init_a_t emb_func_init_a; - lsm6dsr_emb_func_init_b_t emb_func_init_b; - lsm6dsr_mag_cfg_a_t mag_cfg_a; - lsm6dsr_mag_cfg_b_t mag_cfg_b; - lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg; - lsm6dsr_sensor_hub_1_t sensor_hub_1; - lsm6dsr_sensor_hub_2_t sensor_hub_2; - lsm6dsr_sensor_hub_3_t sensor_hub_3; - lsm6dsr_sensor_hub_4_t sensor_hub_4; - lsm6dsr_sensor_hub_5_t sensor_hub_5; - lsm6dsr_sensor_hub_6_t sensor_hub_6; - lsm6dsr_sensor_hub_7_t sensor_hub_7; - lsm6dsr_sensor_hub_8_t sensor_hub_8; - lsm6dsr_sensor_hub_9_t sensor_hub_9; - lsm6dsr_sensor_hub_10_t sensor_hub_10; - lsm6dsr_sensor_hub_11_t sensor_hub_11; - lsm6dsr_sensor_hub_12_t sensor_hub_12; - lsm6dsr_sensor_hub_13_t sensor_hub_13; - lsm6dsr_sensor_hub_14_t sensor_hub_14; - lsm6dsr_sensor_hub_15_t sensor_hub_15; - lsm6dsr_sensor_hub_16_t sensor_hub_16; - lsm6dsr_sensor_hub_17_t sensor_hub_17; - lsm6dsr_sensor_hub_18_t sensor_hub_18; - lsm6dsr_master_config_t master_config; - lsm6dsr_slv0_add_t slv0_add; - lsm6dsr_slv0_subadd_t slv0_subadd; - lsm6dsr_slv0_config_t slv0_config; - lsm6dsr_slv1_add_t slv1_add; - lsm6dsr_slv1_subadd_t slv1_subadd; - lsm6dsr_slv1_config_t slv1_config; - lsm6dsr_slv2_add_t slv2_add; - lsm6dsr_slv2_subadd_t slv2_subadd; - lsm6dsr_slv2_config_t slv2_config; - lsm6dsr_slv3_add_t slv3_add; - lsm6dsr_slv3_subadd_t slv3_subadd; - lsm6dsr_slv3_config_t slv3_config; - lsm6dsr_datawrite_slv0_t datawrite_slv0; - lsm6dsr_status_master_t status_master; - bitwise_t bitwise; - uint8_t byte; -} lsm6dsr_reg_t; - /** * @} * @@ -3001,8 +2823,7 @@ int32_t lsm6dsr_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); int32_t lsm6dsr_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); int32_t lsm6dsr_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); @@ -3077,8 +2898,8 @@ int32_t lsm6dsr_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); int32_t lsm6dsr_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t lsm6dsr_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_drdy_mask_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_drdy_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3761,9 +3582,6 @@ typedef enum LSM6DSR_SENSORHUB_SLAVE2_TAG, LSM6DSR_SENSORHUB_SLAVE3_TAG, LSM6DSR_STEP_CPUNTER_TAG, - LSM6DSR_GAME_ROTATION_TAG, - LSM6DSR_GEOMAG_ROTATION_TAG, - LSM6DSR_ROTATION_TAG, LSM6DSR_SENSORHUB_NACK_TAG = 0x19, } lsm6dsr_fifo_tag_t; int32_t lsm6dsr_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, @@ -4039,29 +3857,7 @@ int32_t lsm6dsr_fsm_start_address_set(const stmdev_ctx_t *ctx, int32_t lsm6dsr_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); -typedef struct -{ - lsm6dsr_sensor_hub_1_t sh_byte_1; - lsm6dsr_sensor_hub_2_t sh_byte_2; - lsm6dsr_sensor_hub_3_t sh_byte_3; - lsm6dsr_sensor_hub_4_t sh_byte_4; - lsm6dsr_sensor_hub_5_t sh_byte_5; - lsm6dsr_sensor_hub_6_t sh_byte_6; - lsm6dsr_sensor_hub_7_t sh_byte_7; - lsm6dsr_sensor_hub_8_t sh_byte_8; - lsm6dsr_sensor_hub_9_t sh_byte_9; - lsm6dsr_sensor_hub_10_t sh_byte_10; - lsm6dsr_sensor_hub_11_t sh_byte_11; - lsm6dsr_sensor_hub_12_t sh_byte_12; - lsm6dsr_sensor_hub_13_t sh_byte_13; - lsm6dsr_sensor_hub_14_t sh_byte_14; - lsm6dsr_sensor_hub_15_t sh_byte_15; - lsm6dsr_sensor_hub_16_t sh_byte_16; - lsm6dsr_sensor_hub_17_t sh_byte_17; - lsm6dsr_sensor_hub_18_t sh_byte_18; -} lsm6dsr_emb_sh_read_t; -int32_t lsm6dsr_sh_read_data_raw_get(const stmdev_ctx_t *ctx, - lsm6dsr_emb_sh_read_t *val, +int32_t lsm6dsr_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len); typedef enum @@ -4198,4 +3994,3 @@ int32_t lsm6dsr_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif /* LSM6DSR_REGS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c index 74cafeb..cd492be 100644 --- a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c +++ b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -214,6 +213,10 @@ int32_t lsm6dsrx_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1_xl.fs_xl) { @@ -387,7 +390,7 @@ int32_t lsm6dsrx_xl_data_rate_set(const stmdev_ctx_t *ctx, if (mlc_enable == PROPERTY_ENABLE) { - ret = lsm6dsrx_mlc_data_rate_get(ctx, &mlc_odr); + ret += lsm6dsrx_mlc_data_rate_get(ctx, &mlc_odr); if (ret == 0) { @@ -514,6 +517,10 @@ int32_t lsm6dsrx_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1_xl.odr_xl) { @@ -614,6 +621,10 @@ int32_t lsm6dsrx_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2_g.fs_g) { @@ -795,7 +806,7 @@ int32_t lsm6dsrx_gy_data_rate_set(const stmdev_ctx_t *ctx, if (mlc_enable == PROPERTY_ENABLE) { - ret = lsm6dsrx_mlc_data_rate_get(ctx, &mlc_odr); + ret += lsm6dsrx_mlc_data_rate_get(ctx, &mlc_odr); if (ret == 0) { @@ -922,6 +933,10 @@ int32_t lsm6dsrx_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2_g.odr_g) { @@ -1018,6 +1033,11 @@ int32_t lsm6dsrx_block_data_update_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.bdu; return ret; @@ -1066,6 +1086,10 @@ int32_t lsm6dsrx_xl_offset_weight_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.usr_off_w) { @@ -1126,6 +1150,10 @@ int32_t lsm6dsrx_xl_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.xl_hm_mode) { @@ -1186,6 +1214,10 @@ int32_t lsm6dsrx_gy_power_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl7_g.g_hm_mode) { @@ -1211,6 +1243,7 @@ int32_t lsm6dsrx_gy_power_mode_get(const stmdev_ctx_t *ctx, * @param ctx Read / write interface definitions.(ptr) * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC; * TAP_SRC; D6D_SRC; STATUS_REG; + * MLC_STATUS_MAINPAGE; * EMB_FUNC_STATUS; FSM_STATUS_A/B * @retval Interface status (MANDATORY: return 0 -> no Error). * @@ -1249,9 +1282,17 @@ int32_t lsm6dsrx_all_sources_get(const stmdev_ctx_t *ctx, if (ret == 0) { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK); + ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_STATUS_MAINPAGE, + (uint8_t *)&val->mlc_status, 1); + } + + if (ret != 0) + { + return ret; } + ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK); + if (ret == 0) { ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS, @@ -1270,10 +1311,7 @@ int32_t lsm6dsrx_all_sources_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_status_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -1312,6 +1350,11 @@ int32_t lsm6dsrx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.xlda; return ret; @@ -1333,6 +1376,11 @@ int32_t lsm6dsrx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.gda; return ret; @@ -1354,6 +1402,11 @@ int32_t lsm6dsrx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) + { + return ret; + } + *val = status_reg.tda; return ret; @@ -1520,6 +1573,11 @@ int32_t lsm6dsrx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7_g.usr_off_on_out; return ret; @@ -1592,6 +1650,11 @@ int32_t lsm6dsrx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl10_c.timestamp_en; return ret; @@ -1613,6 +1676,11 @@ int32_t lsm6dsrx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TIMESTAMP0, buff, 4); + if (ret != 0) + { + return ret; + } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1676,6 +1744,10 @@ int32_t lsm6dsrx_rounding_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.rounding) { @@ -1720,6 +1792,11 @@ int32_t lsm6dsrx_temperature_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUT_TEMP_L, buff, 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1742,6 +1819,11 @@ int32_t lsm6dsrx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUTX_L_G, buff, 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1768,6 +1850,11 @@ int32_t lsm6dsrx_acceleration_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUTX_L_A, buff, 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1818,10 +1905,7 @@ int32_t lsm6dsrx_number_of_steps_get(const stmdev_ctx_t *ctx, *val = (*val * 256U) + buff[0]; } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -1853,10 +1937,7 @@ int32_t lsm6dsrx_steps_reset(const stmdev_ctx_t *ctx) (uint8_t *)&emb_func_src, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -1875,7 +1956,7 @@ int32_t lsm6dsrx_steps_reset(const stmdev_ctx_t *ctx) /** * @brief Difference in percentage of the effective ODR (and timestamp rate) - * with respect to the typical.[set] + * with respect to the typical.[get] * Step: 0.15%. 8-bit format, 2's complement. * * @param ctx Read / write interface definitions.(ptr) @@ -1883,42 +1964,19 @@ int32_t lsm6dsrx_steps_reset(const stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) { lsm6dsrx_internal_freq_fine_t internal_freq_fine; int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INTERNAL_FREQ_FINE, (uint8_t *)&internal_freq_fine, 1); - - if (ret == 0) + if (ret != 0) { - internal_freq_fine.freq_fine = (uint8_t)val; - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INTERNAL_FREQ_FINE, - (uint8_t *)&internal_freq_fine, 1); + return ret; } - return ret; -} - -/** - * @brief Difference in percentage of the effective ODR (and timestamp rate) - * with respect to the typical.[get] - * Step: 0.15%. 8-bit format, 2's complement. - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lsm6dsrx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6dsrx_internal_freq_fine_t internal_freq_fine; - int32_t ret; - - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INTERNAL_FREQ_FINE, - (uint8_t *)&internal_freq_fine, 1); - *val = internal_freq_fine.freq_fine; + *val = (int8_t)internal_freq_fine.freq_fine; return ret; } @@ -1968,6 +2026,10 @@ int32_t lsm6dsrx_mem_bank_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } switch (func_cfg_access.reg_access) { @@ -2003,71 +2065,7 @@ int32_t lsm6dsrx_mem_bank_get(const stmdev_ctx_t *ctx, int32_t lsm6dsrx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { - lsm6dsrx_page_rw_t page_rw; - lsm6dsrx_page_sel_t page_sel; - lsm6dsrx_page_address_t page_address; - int32_t ret; - - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x02U; /* page_write enable */ - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - - if (ret == 0) - { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - - if (ret == 0) - { - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_VALUE, val, 1); - } - - if (ret == 0) - { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } - - return ret; + return lsm6dsrx_ln_pg_write(ctx, add, val, 1); } /** @@ -2091,98 +2089,105 @@ int32_t lsm6dsrx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, int32_t ret; uint8_t i ; - msb = (uint8_t)((add / 256U) & 0x0FU); + msb = (uint8_t)((add >> 8) & 0x0FU); lsb = (uint8_t)(add - (msb * 256U)); - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK); - if (ret == 0) + ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK); + if (ret != 0) { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); + return ret; } - if (ret == 0) + /* set page write */ + ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, + (uint8_t *)&page_rw, 1); + if (ret != 0) { - page_rw.page_rw = 0x02U; /* page_write enable*/ - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } + page_rw.page_rw = 0x02U; /* page_write enable*/ + ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, + (uint8_t *)&page_rw, 1); - if (ret == 0) + /* select page */ + ret += lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - if (ret == 0) + /* set page addr */ + page_address.page_addr = lsb; + ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { - page_address.page_addr = lsb; - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + goto exit; } for (i = 0; i < len; i++) { - if (ret == 0) + ret += lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_VALUE, &buf[i], 1); + goto exit; + } - if (ret == 0) - { - /* Check if page wrap */ - if (lsb == 0x00U) - { - msb++; - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } + lsb++; - lsb++; + /* Check if page wrap */ + if (lsb == 0x00U) + { + msb++; + ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; // Default value + ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } } } - if (ret == 0) + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; // Default value + ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = 0; - page_sel.not_used_01 = 1; - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - if (ret == 0) - { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) + /* unset page write */ + ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, + (uint8_t *)&page_rw, 1); + if (ret != 0) { - page_rw.page_rw = 0x00U; /* page_write disable */ - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } + page_rw.page_rw = 0x00U; /* page_write disable */ + ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, + (uint8_t *)&page_rw, 1); - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } +exit: + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -2205,63 +2210,67 @@ int32_t lsm6dsrx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, int32_t ret; ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } - - if (ret == 0) + if (ret != 0) { - page_rw.page_rw = 0x01U; /* page_read enable*/ - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); + return ret; } - if (ret == 0) + /* set page write */ + ret += lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, + (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } + page_rw.page_rw = 0x01U; /* page_read enable*/ + ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, + (uint8_t *)&page_rw, 1); - if (ret == 0) + /* select page */ + ret += lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); - page_sel.not_used_01 = 1; - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - - if (ret == 0) + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; // Default value + ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + goto exit; } - if (ret == 0) + /* set page addr */ + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_VALUE, val, 2); + goto exit; } - if (ret == 0) + /* read value */ + ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_VALUE, val, 2); + if (ret != 0) { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } - if (ret == 0) + /* unset page read */ + ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, + (uint8_t *)&page_rw, 1); + if (ret != 0) { - page_rw.page_rw = 0x00U; /* page_read disable */ - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); + goto exit; } + page_rw.page_rw = 0x00U; /* page_read disable */ + ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, + (uint8_t *)&page_rw, 1); - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } +exit: + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -2311,6 +2320,10 @@ int32_t lsm6dsrx_data_ready_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } switch (counter_bdr_reg1.dataready_pulsed) { @@ -2388,6 +2401,11 @@ int32_t lsm6dsrx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.sw_reset; return ret; @@ -2436,6 +2454,11 @@ int32_t lsm6dsrx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.if_inc; return ret; @@ -2482,6 +2505,11 @@ int32_t lsm6dsrx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3_c.boot; return ret; @@ -2532,6 +2560,10 @@ int32_t lsm6dsrx_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_xl) { @@ -2598,6 +2630,10 @@ int32_t lsm6dsrx_gy_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl5_c.st_g) { @@ -2675,6 +2711,11 @@ int32_t lsm6dsrx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl1_xl.lpf2_xl_en; return ret; @@ -2723,6 +2764,11 @@ int32_t lsm6dsrx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.lpf1_sel_g; return ret; @@ -2737,8 +2783,7 @@ int32_t lsm6dsrx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_filter_settling_mask_set(const stmdev_ctx_t *ctx, - uint8_t val) +int32_t lsm6dsrx_drdy_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2765,14 +2810,18 @@ int32_t lsm6dsrx_filter_settling_mask_set(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_filter_settling_mask_get(const stmdev_ctx_t *ctx, - uint8_t *val) +int32_t lsm6dsrx_drdy_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl4_c_t ctrl4_c; int32_t ret; ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.drdy_mask; return ret; @@ -2821,6 +2870,10 @@ int32_t lsm6dsrx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.ftype) { @@ -2905,6 +2958,11 @@ int32_t lsm6dsrx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.low_pass_on_6d; return ret; @@ -2957,6 +3015,10 @@ int32_t lsm6dsrx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) + @@ -3109,6 +3171,11 @@ int32_t lsm6dsrx_xl_fast_settling_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8_xl.fastsettl_mode_xl; return ret; @@ -3159,6 +3226,10 @@ int32_t lsm6dsrx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } switch (tap_cfg0.slope_fds) { @@ -3224,6 +3295,10 @@ int32_t lsm6dsrx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g) { @@ -3313,6 +3388,10 @@ int32_t lsm6dsrx_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch (pin_ctrl.ois_pu_dis) { @@ -3376,6 +3455,10 @@ int32_t lsm6dsrx_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret != 0) + { + return ret; + } switch (ctrl7_g.ois_on) { @@ -3430,6 +3513,11 @@ int32_t lsm6dsrx_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX, (uint8_t *)&status_spiaux, 1); + if (ret != 0) + { + return ret; + } + *val = status_spiaux.xlda; return ret; @@ -3451,6 +3539,11 @@ int32_t lsm6dsrx_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX, (uint8_t *)&status_spiaux, 1); + if (ret != 0) + { + return ret; + } + *val = status_spiaux.gda; return ret; @@ -3472,6 +3565,11 @@ int32_t lsm6dsrx_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX, (uint8_t *)&status_spiaux, 1); + if (ret != 0) + { + return ret; + } + *val = status_spiaux.gyro_settling; return ret; @@ -3522,6 +3620,10 @@ int32_t lsm6dsrx_aux_xl_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1); + if (ret != 0) + { + return ret; + } switch (int_ois.st_xl_ois) { @@ -3588,6 +3690,10 @@ int32_t lsm6dsrx_aux_den_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1); + if (ret != 0) + { + return ret; + } switch (int_ois.den_lh_ois) { @@ -3666,10 +3772,12 @@ int32_t lsm6dsrx_aux_den_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1); - if (ret == 0) + ret += lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS, + (uint8_t *)&ctrl1_ois, 1); + + if (ret != 0) { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); + return ret; } switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) @@ -3739,6 +3847,11 @@ int32_t lsm6dsrx_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1); + if (ret != 0) + { + return ret; + } + *val = int_ois.int2_drdy_ois; return ret; @@ -3799,6 +3912,10 @@ int32_t lsm6dsrx_aux_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2)) { @@ -3866,6 +3983,10 @@ int32_t lsm6dsrx_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl1_ois.fs_125_ois << 2) + ctrl1_ois.fs_g_ois) { @@ -3940,6 +4061,10 @@ int32_t lsm6dsrx_aux_spi_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1_ois.sim_ois) { @@ -4002,6 +4127,10 @@ int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2_ois.ftype_ois) { @@ -4073,6 +4202,10 @@ int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1); + if (ret != 0) + { + return ret; + } switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois) { @@ -4151,6 +4284,10 @@ int32_t lsm6dsrx_aux_gy_clamp_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_ois.st_ois_clampdis) { @@ -4213,6 +4350,10 @@ int32_t lsm6dsrx_aux_gy_self_test_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_ois.st_ois) { @@ -4279,6 +4420,10 @@ int32_t lsm6dsrx_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_ois.filter_xl_conf_ois) { @@ -4365,6 +4510,10 @@ int32_t lsm6dsrx_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_ois.fs_xl_ois) { @@ -4448,6 +4597,10 @@ int32_t lsm6dsrx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch (pin_ctrl.sdo_pu_en) { @@ -4510,6 +4663,10 @@ int32_t lsm6dsrx_int1_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); + if (ret != 0) + { + return ret; + } switch (i3c_bus_avb.pd_dis_int1) { @@ -4572,6 +4729,10 @@ int32_t lsm6dsrx_spi_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.sim) { @@ -4634,6 +4795,10 @@ int32_t lsm6dsrx_i2c_interface_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4_c.i2c_disable) { @@ -4710,10 +4875,11 @@ int32_t lsm6dsrx_i3c_disable_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - if (ret == 0) + ret += lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + if (ret != 0) { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); + return ret; } switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel) @@ -4800,10 +4966,7 @@ int32_t lsm6dsrx_pin_int1_route_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int1_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); if (ret == 0) { @@ -4932,10 +5095,7 @@ int32_t lsm6dsrx_pin_int1_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int1_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); if (ret == 0) { @@ -4993,10 +5153,7 @@ int32_t lsm6dsrx_pin_int2_route_set(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int2_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); if (ret == 0) { @@ -5123,10 +5280,7 @@ int32_t lsm6dsrx_pin_int2_route_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_int2_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); if (ret == 0) { @@ -5186,6 +5340,10 @@ int32_t lsm6dsrx_pin_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.pp_od) { @@ -5248,6 +5406,10 @@ int32_t lsm6dsrx_pin_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl3_c.h_lactive) { @@ -5308,6 +5470,11 @@ int32_t lsm6dsrx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.int2_on_int1; return ret; @@ -5342,24 +5509,21 @@ int32_t lsm6dsrx_int_notification_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, + (uint8_t *)&page_rw, 1); + } - if (ret == 0) - { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, + (uint8_t *)&page_rw, 1); + } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } return ret; @@ -5387,17 +5551,19 @@ int32_t lsm6dsrx_int_notification_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK); - } - if (ret == 0) - { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, - (uint8_t *)&page_rw, 1); + if (ret == 0) + { + ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, + (uint8_t *)&page_rw, 1); + } + + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } - if (ret == 0) + if (ret != 0) { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir) @@ -5486,6 +5652,10 @@ int32_t lsm6dsrx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } switch (wake_up_dur.wake_ths_w) { @@ -5548,6 +5718,11 @@ int32_t lsm6dsrx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.wk_ths; return ret; @@ -5596,6 +5771,11 @@ int32_t lsm6dsrx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_ths.usr_off_on_wu; return ret; @@ -5642,6 +5822,11 @@ int32_t lsm6dsrx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.wake_dur; return ret; @@ -5701,6 +5886,11 @@ int32_t lsm6dsrx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl4_c.sleep_g; return ret; @@ -5753,6 +5943,10 @@ int32_t lsm6dsrx_act_pin_notification_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } switch (tap_cfg0. sleep_status_on_int) { @@ -5815,6 +6009,11 @@ int32_t lsm6dsrx_act_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg2.inact_en) { @@ -5883,6 +6082,11 @@ int32_t lsm6dsrx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + *val = wake_up_dur.sleep_dur; return ret; @@ -5944,6 +6148,11 @@ int32_t lsm6dsrx_tap_detection_on_z_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.tap_z_en; return ret; @@ -5992,6 +6201,11 @@ int32_t lsm6dsrx_tap_detection_on_y_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.tap_y_en; return ret; @@ -6040,6 +6254,11 @@ int32_t lsm6dsrx_tap_detection_on_x_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.tap_x_en; return ret; @@ -6087,6 +6306,11 @@ int32_t lsm6dsrx_tap_threshold_x_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg1.tap_ths_x; return ret; @@ -6135,6 +6359,10 @@ int32_t lsm6dsrx_tap_axis_priority_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) + { + return ret; + } switch (tap_cfg1.tap_priority) { @@ -6212,6 +6440,11 @@ int32_t lsm6dsrx_tap_threshold_y_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg2.tap_ths_y; return ret; @@ -6259,6 +6492,11 @@ int32_t lsm6dsrx_tap_threshold_z_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = tap_ths_6d.tap_ths_z; return ret; @@ -6313,6 +6551,11 @@ int32_t lsm6dsrx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1); + if (ret != 0) + { + return ret; + } + *val = int_dur2.shock; return ret; @@ -6367,6 +6610,11 @@ int32_t lsm6dsrx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1); + if (ret != 0) + { + return ret; + } + *val = int_dur2.quiet; return ret; @@ -6423,6 +6671,11 @@ int32_t lsm6dsrx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1); + if (ret != 0) + { + return ret; + } + *val = int_dur2.dur; return ret; @@ -6471,6 +6724,10 @@ int32_t lsm6dsrx_tap_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } switch (wake_up_ths.single_double_tap) { @@ -6546,6 +6803,10 @@ int32_t lsm6dsrx_6d_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } switch (tap_ths_6d.sixd_ths) { @@ -6614,6 +6875,11 @@ int32_t lsm6dsrx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = tap_ths_6d.d4d_en; return ret; @@ -6675,6 +6941,10 @@ int32_t lsm6dsrx_ff_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -6780,6 +7050,10 @@ int32_t lsm6dsrx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL, (uint8_t *)&free_fall, 1); } + if (ret != 0) + { + return ret; + } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -6846,6 +7120,11 @@ int32_t lsm6dsrx_fifo_watermark_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); ret += lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.wtm; *val = (*val * 256U) + fifo_ctrl1.wtm;; @@ -6881,10 +7160,7 @@ int32_t lsm6dsrx_compression_algo_init_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_init_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -6915,9 +7191,10 @@ int32_t lsm6dsrx_compression_algo_init_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_init_b.fifo_compr_init; - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -6951,10 +7228,7 @@ int32_t lsm6dsrx_compression_algo_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); if (ret == 0) { @@ -6993,6 +7267,10 @@ int32_t lsm6dsrx_compression_algo_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } switch ((fifo_ctrl2.fifo_compr_rt_en << 2) + fifo_ctrl2.uncoptr_rate) @@ -7068,6 +7346,11 @@ int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odrchg_en; return ret; @@ -7116,6 +7399,11 @@ int32_t lsm6dsrx_compression_algo_real_time_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.fifo_compr_rt_en; return ret; @@ -7166,6 +7454,11 @@ int32_t lsm6dsrx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -7216,6 +7509,10 @@ int32_t lsm6dsrx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_xl) { @@ -7320,6 +7617,10 @@ int32_t lsm6dsrx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_gy) { @@ -7422,6 +7723,10 @@ int32_t lsm6dsrx_fifo_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.fifo_mode) { @@ -7502,6 +7807,10 @@ int32_t lsm6dsrx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.odr_t_batch) { @@ -7577,6 +7886,10 @@ int32_t lsm6dsrx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.odr_ts_batch) { @@ -7651,6 +7964,10 @@ int32_t lsm6dsrx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } switch (counter_bdr_reg1.trig_counter_bdr) { @@ -7715,6 +8032,11 @@ int32_t lsm6dsrx_rst_batch_counter_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + *val = counter_bdr_reg1.rst_counter_bdr; return ret; @@ -7776,10 +8098,12 @@ int32_t lsm6dsrx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); - if (ret == 0) + ret += lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + + if (ret != 0) { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); + return ret; } *val = counter_bdr_reg1.cnt_bdr_th; @@ -7929,6 +8253,10 @@ int32_t lsm6dsrx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_data_out_tag, 1); + if (ret != 0) + { + return ret; + } switch (fifo_data_out_tag.tag_sensor) { @@ -8004,18 +8332,6 @@ int32_t lsm6dsrx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, *val = LSM6DSRX_STEP_CPUNTER_TAG; break; - case LSM6DSRX_GAME_ROTATION_TAG: - *val = LSM6DSRX_GAME_ROTATION_TAG; - break; - - case LSM6DSRX_GEOMAG_ROTATION_TAG: - *val = LSM6DSRX_GEOMAG_ROTATION_TAG; - break; - - case LSM6DSRX_ROTATION_TAG: - *val = LSM6DSRX_ROTATION_TAG; - break; - case LSM6DSRX_SENSORHUB_NACK_TAG: *val = LSM6DSRX_SENSORHUB_NACK_TAG; break; @@ -8057,10 +8373,7 @@ int32_t lsm6dsrx_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_fifo_cfg, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -8089,10 +8402,7 @@ int32_t lsm6dsrx_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, *val = emb_func_fifo_cfg.pedo_fifo_en; } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -8126,10 +8436,7 @@ int32_t lsm6dsrx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -8160,9 +8467,10 @@ int32_t lsm6dsrx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = slv0_config. batch_ext_sens_0_en; - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -8196,10 +8504,7 @@ int32_t lsm6dsrx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -8225,14 +8530,15 @@ int32_t lsm6dsrx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, { ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV1_CONFIG, (uint8_t *)&slv1_config, 1); - *val = slv1_config. batch_ext_sens_1_en; } if (ret == 0) { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + *val = slv1_config. batch_ext_sens_1_en; } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -8266,10 +8572,7 @@ int32_t lsm6dsrx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -8300,9 +8603,10 @@ int32_t lsm6dsrx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = slv2_config. batch_ext_sens_2_en; - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -8336,10 +8640,7 @@ int32_t lsm6dsrx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -8365,14 +8666,15 @@ int32_t lsm6dsrx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, { ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV3_CONFIG, (uint8_t *)&slv3_config, 1); - *val = slv3_config. batch_ext_sens_3_en; } if (ret == 0) { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + *val = slv3_config. batch_ext_sens_3_en; } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -8432,6 +8734,10 @@ int32_t lsm6dsrx_den_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6_c.den_mode) { @@ -8506,6 +8812,10 @@ int32_t lsm6dsrx_den_polarity_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_lh) { @@ -8568,6 +8878,10 @@ int32_t lsm6dsrx_den_enable_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } switch (ctrl9_xl.den_xl_g) { @@ -8633,6 +8947,11 @@ int32_t lsm6dsrx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_z; return ret; @@ -8680,6 +8999,11 @@ int32_t lsm6dsrx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9_xl.den_y; return ret; @@ -8703,7 +9027,7 @@ int32_t lsm6dsrx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) if (ret == 0) { - ctrl9_xl.den_x = (uint8_t)val; + ctrl9_xl.den_z = (uint8_t)val; ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); } @@ -8727,7 +9051,12 @@ int32_t lsm6dsrx_den_mark_axis_z_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - *val = ctrl9_xl.den_x; + if (ret != 0) + { + return ret; + } + + *val = ctrl9_xl.den_z; return ret; } @@ -8772,10 +9101,7 @@ int32_t lsm6dsrx_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_a, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -8799,14 +9125,15 @@ int32_t lsm6dsrx_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - *val = emb_func_en_a.pedo_en; } if (ret == 0) { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + *val = emb_func_en_a.pedo_en; } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -8833,10 +9160,7 @@ int32_t lsm6dsrx_pedo_step_detect_get(const stmdev_ctx_t *ctx, *val = emb_func_status.is_step_det; } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -8928,8 +9252,11 @@ int32_t lsm6dsrx_pedo_steps_period_get(const stmdev_ctx_t *ctx, { ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -8980,6 +9307,10 @@ int32_t lsm6dsrx_pedo_int_mode_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg); + if (ret != 0) + { + return ret; + } switch (pedo_cmd_reg.carry_count_en) { @@ -9040,10 +9371,7 @@ int32_t lsm6dsrx_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_a, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -9072,9 +9400,10 @@ int32_t lsm6dsrx_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_en_a.sign_motion_en; - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -9103,9 +9432,10 @@ int32_t lsm6dsrx_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_sigmot; - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -9150,10 +9480,7 @@ int32_t lsm6dsrx_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_a, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -9182,9 +9509,10 @@ int32_t lsm6dsrx_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_en_a.tilt_en; - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -9213,9 +9541,10 @@ int32_t lsm6dsrx_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_tilt; - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -9277,14 +9606,16 @@ int32_t lsm6dsrx_mag_sensitivity_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_L, &buff[0]); - if (ret == 0) + ret += lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_H, + &buff[1]); + if (ret != 0) { - ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_H, - &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + return ret; } + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + return ret; } @@ -9389,7 +9720,10 @@ int32_t lsm6dsrx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { i++; ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFZ_H, &buff[i]); + } + if (ret == 0) + { val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -9616,18 +9950,21 @@ int32_t lsm6dsrx_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) &buff[i]); } - val[0] = buff[1]; - val[0] = (val[0] * 256U) + buff[0]; - val[1] = buff[3]; - val[1] = (val[1] * 256U) + buff[2]; - val[2] = buff[5]; - val[2] = (val[2] * 256U) + buff[4]; - val[3] = buff[7]; - val[3] = (val[3] * 256U) + buff[6]; - val[4] = buff[9]; - val[4] = (val[4] * 256U) + buff[8]; - val[5] = buff[11]; - val[6] = (val[5] * 256U) + buff[10]; + if (ret == 0) + { + val[0] = buff[1]; + val[0] = (val[0] * 256U) + buff[0]; + val[1] = buff[3]; + val[1] = (val[1] * 256U) + buff[2]; + val[2] = buff[5]; + val[2] = (val[2] * 256U) + buff[4]; + val[3] = buff[7]; + val[3] = (val[3] * 256U) + buff[6]; + val[4] = buff[9]; + val[4] = (val[4] * 256U) + buff[8]; + val[5] = buff[11]; + val[6] = (val[5] * 256U) + buff[10]; + } return ret; } @@ -9677,6 +10014,10 @@ int32_t lsm6dsrx_mag_z_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A, (uint8_t *)&mag_cfg_a); + if (ret != 0) + { + return ret; + } switch (mag_cfg_a.mag_z_axis) { @@ -9758,6 +10099,10 @@ int32_t lsm6dsrx_mag_y_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A, (uint8_t *)&mag_cfg_a); + if (ret != 0) + { + return ret; + } switch (mag_cfg_a.mag_y_axis) { @@ -9838,6 +10183,10 @@ int32_t lsm6dsrx_mag_x_orient_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_B, (uint8_t *)&mag_cfg_b); + if (ret != 0) + { + return ret; + } switch (mag_cfg_b.mag_x_axis) { @@ -9912,9 +10261,10 @@ int32_t lsm6dsrx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = emb_func_status.is_fsm_lc; - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -9946,10 +10296,7 @@ int32_t lsm6dsrx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -9982,10 +10329,7 @@ int32_t lsm6dsrx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10058,10 +10402,7 @@ int32_t lsm6dsrx_fsm_enable_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_en_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10093,10 +10434,7 @@ int32_t lsm6dsrx_fsm_enable_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_enable_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10125,10 +10463,7 @@ int32_t lsm6dsrx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) 2); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10153,14 +10488,14 @@ int32_t lsm6dsrx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10195,10 +10530,7 @@ int32_t lsm6dsrx_long_clr_set(const stmdev_ctx_t *ctx, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10225,9 +10557,11 @@ int32_t lsm6dsrx_long_clr_get(const stmdev_ctx_t *ctx, (uint8_t *)&fsm_long_counter_clear, 1); } - if (ret == 0) + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + + if (ret != 0) { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } switch (fsm_long_counter_clear.fsm_lc_clr) @@ -10273,10 +10607,7 @@ int32_t lsm6dsrx_fsm_out_get(const stmdev_ctx_t *ctx, (uint8_t *)&val->fsm_outs1, 16); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10312,10 +10643,7 @@ int32_t lsm6dsrx_fsm_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10342,9 +10670,11 @@ int32_t lsm6dsrx_fsm_data_rate_get(const stmdev_ctx_t *ctx, (uint8_t *)&emb_func_odr_cfg_b, 1); } - if (ret == 0) + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + + if (ret != 0) { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } switch (emb_func_odr_cfg_b.fsm_odr) @@ -10401,10 +10731,7 @@ int32_t lsm6dsrx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&emb_func_init_b, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10433,9 +10760,10 @@ int32_t lsm6dsrx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = emb_func_init_b.fsm_init; - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -10494,8 +10822,11 @@ int32_t lsm6dsrx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, { ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -10516,13 +10847,6 @@ int32_t lsm6dsrx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_PROGRAMS, buff); - if (ret == 0) - { - ret = lsm6dsrx_ln_pg_write_byte(ctx, - LSM6DSRX_FSM_PROGRAMS + 0x01U, - buff); - } - return ret; } @@ -10595,8 +10919,11 @@ int32_t lsm6dsrx_fsm_start_address_get(const stmdev_ctx_t *ctx, { ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_START_ADD_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -10657,10 +10984,7 @@ int32_t lsm6dsrx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) } } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10688,10 +11012,11 @@ int32_t lsm6dsrx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - *val = reg.mlc_en; + *val = reg.mlc_en; } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -10738,10 +11063,7 @@ int32_t lsm6dsrx_mlc_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)®, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10793,9 +11115,10 @@ int32_t lsm6dsrx_mlc_data_rate_get(const stmdev_ctx_t *ctx, break; } - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -10817,10 +11140,7 @@ int32_t lsm6dsrx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC0_SRC, buff, 8); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10874,8 +11194,11 @@ int32_t lsm6dsrx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, { ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_H, &buff[1]); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } } return ret; @@ -10902,8 +11225,7 @@ int32_t lsm6dsrx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, - lsm6dsrx_emb_sh_read_t *val, +int32_t lsm6dsrx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len) { int32_t ret; @@ -10916,10 +11238,7 @@ int32_t lsm6dsrx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, (uint8_t *)val, len); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10953,10 +11272,7 @@ int32_t lsm6dsrx_sh_slave_connected_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -10983,9 +11299,11 @@ int32_t lsm6dsrx_sh_slave_connected_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + + if (ret != 0) { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } switch (master_config.aux_sens_on) @@ -11042,10 +11360,7 @@ int32_t lsm6dsrx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11074,9 +11389,10 @@ int32_t lsm6dsrx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { *val = master_config.master_on; - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -11109,10 +11425,7 @@ int32_t lsm6dsrx_sh_pin_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11139,9 +11452,11 @@ int32_t lsm6dsrx_sh_pin_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + + if (ret != 0) { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } switch (master_config.shub_pu_en) @@ -11190,10 +11505,7 @@ int32_t lsm6dsrx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11223,9 +11535,10 @@ int32_t lsm6dsrx_sh_pass_through_get(const stmdev_ctx_t *ctx, if (ret == 0) { *val = master_config.pass_through_mode; - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } @@ -11258,10 +11571,7 @@ int32_t lsm6dsrx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11288,9 +11598,11 @@ int32_t lsm6dsrx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + + if (ret != 0) { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } switch (master_config.start_config) @@ -11341,10 +11653,7 @@ int32_t lsm6dsrx_sh_write_mode_set(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11372,10 +11681,7 @@ int32_t lsm6dsrx_sh_write_mode_get(const stmdev_ctx_t *ctx, (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); switch (master_config.write_once) { @@ -11429,10 +11735,7 @@ int32_t lsm6dsrx_sh_reset_set(const stmdev_ctx_t *ctx) (uint8_t *)&master_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11459,10 +11762,7 @@ int32_t lsm6dsrx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) *val = master_config.rst_master_regs; } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11496,10 +11796,7 @@ int32_t lsm6dsrx_sh_data_rate_set(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11526,9 +11823,11 @@ int32_t lsm6dsrx_sh_data_rate_get(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + + if (ret != 0) { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); + return ret; } switch (slv0_config.shub_odr) @@ -11596,10 +11895,7 @@ int32_t lsm6dsrx_sh_cfg_write(const stmdev_ctx_t *ctx, (uint8_t *) & (val->slv0_data), 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11651,10 +11947,7 @@ int32_t lsm6dsrx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv0_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11706,10 +11999,7 @@ int32_t lsm6dsrx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv1_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11761,10 +12051,7 @@ int32_t lsm6dsrx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv2_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11816,10 +12103,7 @@ int32_t lsm6dsrx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, (uint8_t *)&slv3_config, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11845,10 +12129,7 @@ int32_t lsm6dsrx_sh_status_get(const stmdev_ctx_t *ctx, (uint8_t *)val, 1); } - if (ret == 0) - { - ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); - } + ret += lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK); return ret; } @@ -11908,6 +12189,11 @@ int32_t lsm6dsrx_s4s_tph_res_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1); + if (ret != 0) + { + return ret; + } + switch (s4s_tph_l.tph_h_sel) { case LSM6DSRX_S4S_TPH_7bit: @@ -11982,10 +12268,12 @@ int32_t lsm6dsrx_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1); - if (ret == 0) + ret += lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_H, + (uint8_t *)&s4s_tph_h, 1); + + if (ret != 0) { - ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_H, - (uint8_t *)&s4s_tph_h, 1); + return ret; } *val = s4s_tph_h.tph_h; @@ -12036,6 +12324,11 @@ int32_t lsm6dsrx_s4s_res_ratio_get(const stmdev_ctx_t *ctx, ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t *)&s4s_rr, 1); + if (ret != 0) + { + return ret; + } + switch (s4s_rr.rr) { case LSM6DSRX_S4S_DT_RES_11: @@ -12103,6 +12396,11 @@ int32_t lsm6dsrx_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_ST_CMD_CODE, (uint8_t *)&s4s_st_cmd_code, 1); + if (ret != 0) + { + return ret; + } + *val = s4s_st_cmd_code.s4s_st_cmd_code; return ret; @@ -12149,6 +12447,11 @@ int32_t lsm6dsrx_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_DT_REG, (uint8_t *)&s4s_dt_reg, 1); + if (ret != 0) + { + return ret; + } + *val = s4s_dt_reg.dt; return ret; @@ -12164,4 +12467,3 @@ int32_t lsm6dsrx_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val) * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h index 514126d..12e9bf2 100644 --- a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h +++ b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -131,38 +133,6 @@ typedef struct #endif /* MEMS_SHARED_TYPES */ -#ifndef MEMS_UCF_SHARED_TYPES -#define MEMS_UCF_SHARED_TYPES - -/** @defgroup Generic address-data structure definition - * @brief This structure is useful to load a predefined configuration - * of a sensor. - * You can create a sensor configuration by your own or using - * Unico / Unicleo tools available on STMicroelectronics - * web site. - * - * @{ - * - */ - -typedef struct -{ - uint8_t address; - uint8_t data; -} ucf_line_t; - -/** - * @} - * - */ - -#endif /* MEMS_UCF_SHARED_TYPES */ - -/** - * @} - * - */ - /** @defgroup LSM6DSRX Infos * @{ * @@ -2747,158 +2717,6 @@ typedef struct #endif /* DRV_BYTE_ORDER */ } lsm6dsrx_status_master_t; -/** - * @} - * - */ - -/** - * @defgroup LSM6DSRX_Register_Union - * @brief This union group all the registers having a bit-field - * description. - * This union is useful but it's not needed by the driver. - * - * REMOVING this union you are compliant with: - * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " - * - * @{ - * - */ -typedef union -{ - lsm6dsrx_func_cfg_access_t func_cfg_access; - lsm6dsrx_pin_ctrl_t pin_ctrl; - lsm6dsrx_s4s_tph_l_t s4s_tph_l; - lsm6dsrx_s4s_tph_h_t s4s_tph_h; - lsm6dsrx_s4s_rr_t s4s_rr; - lsm6dsrx_fifo_ctrl1_t fifo_ctrl1; - lsm6dsrx_fifo_ctrl2_t fifo_ctrl2; - lsm6dsrx_fifo_ctrl3_t fifo_ctrl3; - lsm6dsrx_fifo_ctrl4_t fifo_ctrl4; - lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1; - lsm6dsrx_counter_bdr_reg2_t counter_bdr_reg2; - lsm6dsrx_int1_ctrl_t int1_ctrl; - lsm6dsrx_int2_ctrl_t int2_ctrl; - lsm6dsrx_ctrl1_xl_t ctrl1_xl; - lsm6dsrx_ctrl2_g_t ctrl2_g; - lsm6dsrx_ctrl3_c_t ctrl3_c; - lsm6dsrx_ctrl4_c_t ctrl4_c; - lsm6dsrx_ctrl5_c_t ctrl5_c; - lsm6dsrx_ctrl6_c_t ctrl6_c; - lsm6dsrx_ctrl7_g_t ctrl7_g; - lsm6dsrx_ctrl8_xl_t ctrl8_xl; - lsm6dsrx_ctrl9_xl_t ctrl9_xl; - lsm6dsrx_ctrl10_c_t ctrl10_c; - lsm6dsrx_all_int_src_t all_int_src; - lsm6dsrx_wake_up_src_t wake_up_src; - lsm6dsrx_tap_src_t tap_src; - lsm6dsrx_d6d_src_t d6d_src; - lsm6dsrx_status_reg_t status_reg; - lsm6dsrx_status_spiaux_t status_spiaux; - lsm6dsrx_fifo_status1_t fifo_status1; - lsm6dsrx_fifo_status2_t fifo_status2; - lsm6dsrx_tap_cfg0_t tap_cfg0; - lsm6dsrx_tap_cfg1_t tap_cfg1; - lsm6dsrx_tap_cfg2_t tap_cfg2; - lsm6dsrx_tap_ths_6d_t tap_ths_6d; - lsm6dsrx_int_dur2_t int_dur2; - lsm6dsrx_wake_up_ths_t wake_up_ths; - lsm6dsrx_wake_up_dur_t wake_up_dur; - lsm6dsrx_free_fall_t free_fall; - lsm6dsrx_md1_cfg_t md1_cfg; - lsm6dsrx_md2_cfg_t md2_cfg; - lsm6dsrx_s4s_st_cmd_code_t s4s_st_cmd_code; - lsm6dsrx_s4s_dt_reg_t s4s_dt_reg; - lsm6dsrx_i3c_bus_avb_t i3c_bus_avb; - lsm6dsrx_internal_freq_fine_t internal_freq_fine; - lsm6dsrx_int_ois_t int_ois; - lsm6dsrx_ctrl1_ois_t ctrl1_ois; - lsm6dsrx_ctrl2_ois_t ctrl2_ois; - lsm6dsrx_ctrl3_ois_t ctrl3_ois; - lsm6dsrx_fifo_data_out_tag_t fifo_data_out_tag; - lsm6dsrx_page_sel_t page_sel; - lsm6dsrx_emb_func_en_a_t emb_func_en_a; - lsm6dsrx_emb_func_en_b_t emb_func_en_b; - lsm6dsrx_page_address_t page_address; - lsm6dsrx_page_value_t page_value; - lsm6dsrx_emb_func_int1_t emb_func_int1; - lsm6dsrx_fsm_int1_a_t fsm_int1_a; - lsm6dsrx_fsm_int1_b_t fsm_int1_b; - lsm6dsrx_mlc_int1_t mlc_int1; - lsm6dsrx_emb_func_int2_t emb_func_int2; - lsm6dsrx_fsm_int2_a_t fsm_int2_a; - lsm6dsrx_fsm_int2_b_t fsm_int2_b; - lsm6dsrx_mlc_int2_t mlc_int2; - lsm6dsrx_emb_func_status_t emb_func_status; - lsm6dsrx_fsm_status_a_t fsm_status_a; - lsm6dsrx_fsm_status_b_t fsm_status_b; - lsm6dsrx_mlc_status_mainpage_t mlc_status_mainpage; - lsm6dsrx_page_rw_t page_rw; - lsm6dsrx_emb_func_fifo_cfg_t emb_func_fifo_cfg; - lsm6dsrx_fsm_enable_a_t fsm_enable_a; - lsm6dsrx_fsm_enable_b_t fsm_enable_b; - lsm6dsrx_fsm_long_counter_clear_t fsm_long_counter_clear; - lsm6dsrx_fsm_outs1_t fsm_outs1; - lsm6dsrx_fsm_outs2_t fsm_outs2; - lsm6dsrx_fsm_outs3_t fsm_outs3; - lsm6dsrx_fsm_outs4_t fsm_outs4; - lsm6dsrx_fsm_outs5_t fsm_outs5; - lsm6dsrx_fsm_outs6_t fsm_outs6; - lsm6dsrx_fsm_outs7_t fsm_outs7; - lsm6dsrx_fsm_outs8_t fsm_outs8; - lsm6dsrx_fsm_outs9_t fsm_outs9; - lsm6dsrx_fsm_outs10_t fsm_outs10; - lsm6dsrx_fsm_outs11_t fsm_outs11; - lsm6dsrx_fsm_outs12_t fsm_outs12; - lsm6dsrx_fsm_outs13_t fsm_outs13; - lsm6dsrx_fsm_outs14_t fsm_outs14; - lsm6dsrx_fsm_outs15_t fsm_outs15; - lsm6dsrx_fsm_outs16_t fsm_outs16; - lsm6dsrx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; - lsm6dsrx_emb_func_odr_cfg_c_t emb_func_odr_cfg_c_t; - lsm6dsrx_emb_func_src_t emb_func_src; - lsm6dsrx_emb_func_init_a_t emb_func_init_a; - lsm6dsrx_emb_func_init_b_t emb_func_init_b; - lsm6dsrx_mag_cfg_a_t mag_cfg_a; - lsm6dsrx_mag_cfg_b_t mag_cfg_b; - lsm6dsrx_pedo_cmd_reg_t pedo_cmd_reg; - lsm6dsrx_sensor_hub_1_t sensor_hub_1; - lsm6dsrx_sensor_hub_2_t sensor_hub_2; - lsm6dsrx_sensor_hub_3_t sensor_hub_3; - lsm6dsrx_sensor_hub_4_t sensor_hub_4; - lsm6dsrx_sensor_hub_5_t sensor_hub_5; - lsm6dsrx_sensor_hub_6_t sensor_hub_6; - lsm6dsrx_sensor_hub_7_t sensor_hub_7; - lsm6dsrx_sensor_hub_8_t sensor_hub_8; - lsm6dsrx_sensor_hub_9_t sensor_hub_9; - lsm6dsrx_sensor_hub_10_t sensor_hub_10; - lsm6dsrx_sensor_hub_11_t sensor_hub_11; - lsm6dsrx_sensor_hub_12_t sensor_hub_12; - lsm6dsrx_sensor_hub_13_t sensor_hub_13; - lsm6dsrx_sensor_hub_14_t sensor_hub_14; - lsm6dsrx_sensor_hub_15_t sensor_hub_15; - lsm6dsrx_sensor_hub_16_t sensor_hub_16; - lsm6dsrx_sensor_hub_17_t sensor_hub_17; - lsm6dsrx_sensor_hub_18_t sensor_hub_18; - lsm6dsrx_master_config_t master_config; - lsm6dsrx_slv0_add_t slv0_add; - lsm6dsrx_slv0_subadd_t slv0_subadd; - lsm6dsrx_slv0_config_t slv0_config; - lsm6dsrx_slv1_add_t slv1_add; - lsm6dsrx_slv1_subadd_t slv1_subadd; - lsm6dsrx_slv1_config_t slv1_config; - lsm6dsrx_slv2_add_t slv2_add; - lsm6dsrx_slv2_subadd_t slv2_subadd; - lsm6dsrx_slv2_config_t slv2_config; - lsm6dsrx_slv3_add_t slv3_add; - lsm6dsrx_slv3_subadd_t slv3_subadd; - lsm6dsrx_slv3_config_t slv3_config; - lsm6dsrx_datawrite_slv0_t datawrite_slv0; - lsm6dsrx_status_master_t status_master; - bitwise_t bitwise; - uint8_t byte; -} lsm6dsrx_reg_t; - /** * @} * @@ -3113,8 +2931,7 @@ int32_t lsm6dsrx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); int32_t lsm6dsrx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); int32_t lsm6dsrx_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); @@ -3189,8 +3006,8 @@ int32_t lsm6dsrx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); int32_t lsm6dsrx_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t lsm6dsrx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_drdy_mask_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_drdy_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3875,9 +3692,6 @@ typedef enum LSM6DSRX_SENSORHUB_SLAVE2_TAG, LSM6DSRX_SENSORHUB_SLAVE3_TAG, LSM6DSRX_STEP_CPUNTER_TAG, - LSM6DSRX_GAME_ROTATION_TAG, - LSM6DSRX_GEOMAG_ROTATION_TAG, - LSM6DSRX_ROTATION_TAG, LSM6DSRX_SENSORHUB_NACK_TAG = 0x19, } lsm6dsrx_fifo_tag_t; int32_t lsm6dsrx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, @@ -4154,29 +3968,7 @@ int32_t lsm6dsrx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); int32_t lsm6dsrx_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); int32_t lsm6dsrx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -typedef struct -{ - lsm6dsrx_sensor_hub_1_t sh_byte_1; - lsm6dsrx_sensor_hub_2_t sh_byte_2; - lsm6dsrx_sensor_hub_3_t sh_byte_3; - lsm6dsrx_sensor_hub_4_t sh_byte_4; - lsm6dsrx_sensor_hub_5_t sh_byte_5; - lsm6dsrx_sensor_hub_6_t sh_byte_6; - lsm6dsrx_sensor_hub_7_t sh_byte_7; - lsm6dsrx_sensor_hub_8_t sh_byte_8; - lsm6dsrx_sensor_hub_9_t sh_byte_9; - lsm6dsrx_sensor_hub_10_t sh_byte_10; - lsm6dsrx_sensor_hub_11_t sh_byte_11; - lsm6dsrx_sensor_hub_12_t sh_byte_12; - lsm6dsrx_sensor_hub_13_t sh_byte_13; - lsm6dsrx_sensor_hub_14_t sh_byte_14; - lsm6dsrx_sensor_hub_15_t sh_byte_15; - lsm6dsrx_sensor_hub_16_t sh_byte_16; - lsm6dsrx_sensor_hub_17_t sh_byte_17; - lsm6dsrx_sensor_hub_18_t sh_byte_18; -} lsm6dsrx_emb_sh_read_t; -int32_t lsm6dsrx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, - lsm6dsrx_emb_sh_read_t *val, +int32_t lsm6dsrx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len); typedef enum @@ -4313,4 +4105,3 @@ int32_t lsm6dsrx_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif /* LSM6DSRX_REGS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.c b/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.c index e27f907..acbd9fa 100644 --- a/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.c +++ b/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -215,23 +214,19 @@ int32_t lsm6dsv16b_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16b_reset_t val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); - if (ret == 0) + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + return ret; } - ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; - ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; - func_cfg_access.sw_por = (uint8_t)val & 0x01U; + ctrl3.boot = (val == LSM6DSV16B_RESTORE_CAL_PARAM) ? 1 : 0; + ctrl3.sw_reset = (val == LSM6DSV16B_RESTORE_CTRL_REGS) ? 1 : 0; + func_cfg_access.sw_por = (val == LSM6DSV16B_GLOBAL_RST) ? 1 : 0; - if (ret == 0) - { - ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); - } - if (ret == 0) - { - ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - } + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); return ret; } @@ -251,9 +246,11 @@ int32_t lsm6dsv16b_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16b_reset_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); - if (ret == 0) + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + return ret; } switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) @@ -318,6 +315,10 @@ int32_t lsm6dsv16b_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv16b_mem_bank_t * int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } switch (func_cfg_access.emb_func_reg_access) { @@ -350,6 +351,11 @@ int32_t lsm6dsv16b_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WHO_AM_I, (uint8_t *)&who_am_i, 1); + if (ret != 0) + { + return ret; + } + *val = who_am_i.id; return ret; @@ -394,6 +400,10 @@ int32_t lsm6dsv16b_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1.odr_xl) { @@ -494,6 +504,10 @@ int32_t lsm6dsv16b_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_xl_mode_t *va int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1.op_mode_xl) { @@ -564,6 +578,10 @@ int32_t lsm6dsv16b_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2.odr_g) { @@ -659,6 +677,11 @@ int32_t lsm6dsv16b_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_gy_mode_t *va int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2.op_mode_g) { case LSM6DSV16B_GY_HIGH_PERFORMANCE_MD: @@ -717,6 +740,11 @@ int32_t lsm6dsv16b_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.if_inc; @@ -761,6 +789,11 @@ int32_t lsm6dsv16b_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.bdu; return ret; @@ -806,6 +839,10 @@ int32_t lsm6dsv16b_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4.drdy_pulsed) { @@ -864,6 +901,10 @@ int32_t lsm6dsv16b_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6.fs_g) { @@ -938,6 +979,10 @@ int32_t lsm6dsv16b_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } switch (ctrl8.fs_xl) { @@ -1002,6 +1047,11 @@ int32_t lsm6dsv16b_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8.xl_dualc_en; return ret; @@ -1048,6 +1098,10 @@ int32_t lsm6dsv16b_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } //switch (ctrl10.xl_st_offset) switch (ctrl10.st_xl) @@ -1111,6 +1165,10 @@ int32_t lsm6dsv16b_gy_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } switch (ctrl10.st_g) { @@ -1169,6 +1227,12 @@ int32_t lsm6dsv16b_all_sources_get(const stmdev_ctx_t *ctx, { ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_STATUS1, (uint8_t *)&buff, 4); } + + if (ret != 0) + { + return ret; + } + bytecpy((uint8_t *)&fifo_status2, &buff[1]); bytecpy((uint8_t *)&all_int_src, &buff[2]); bytecpy((uint8_t *)&status_reg, &buff[3]); @@ -1250,19 +1314,25 @@ int32_t lsm6dsv16b_all_sources_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, + 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); } - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, - 1); - } - if (ret == 0) + + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + return ret; } - ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); - val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; val->step_count_inc = emb_func_src.stepcounter_bit_set; @@ -1281,6 +1351,11 @@ int32_t lsm6dsv16b_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_STATUS_REG, (uint8_t *)&status, 1); + if (ret != 0) + { + return ret; + } + val->drdy_xl = status.xlda; val->drdy_gy = status.gda; val->drdy_temp = status.tda; @@ -1302,6 +1377,11 @@ int32_t lsm6dsv16b_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_OUT_TEMP_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1322,6 +1402,11 @@ int32_t lsm6dsv16b_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_OUTX_L_G, &buff[0], 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1346,6 +1431,11 @@ int32_t lsm6dsv16b_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_OUTZ_L_A, &buff[0], 6); + if (ret != 0) + { + return ret; + } + val[2] = (int16_t)buff[1]; val[2] = (val[2] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1370,6 +1460,11 @@ int32_t lsm6dsv16b_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *v int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_UI_OUTZ_L_A_DUALC, &buff[0], 6); + if (ret != 0) + { + return ret; + } + val[2] = (int16_t)buff[1]; val[2] = (val[2] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1394,6 +1489,11 @@ int32_t lsm6dsv16b_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + if (ret != 0) + { + return ret; + } + *val = (int8_t)internal_freq.freq_fine; return ret; @@ -1438,6 +1538,11 @@ int32_t lsm6dsv16b_tdm_xl_axis_get(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_xl_ax int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + if (ret != 0) + { + return ret; + } + val->x = tdm_cfg1.tdm_xl_x_en; val->y = tdm_cfg1.tdm_xl_y_en; val->z = tdm_cfg1.tdm_xl_z_en; @@ -1468,57 +1573,95 @@ int32_t lsm6dsv16b_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, lsb = (uint8_t)address & 0xFFU; ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } /* set page write */ - ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_ENABLE; - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); /* select page */ ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } /* set page addr */ page_address.page_addr = lsb; ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_ADDRESS, (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } for (i = 0; ((i < len) && (ret == 0)); i++) { - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_VALUE, &buf[i], 1); + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_VALUE, &buf[i], 1); + if (ret != 0) + { + goto exit; + } lsb++; /* Check if page wrap */ if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) { msb++; - ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1); + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used0 = 1; // Default value - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, - 1); + goto exit; } } } page_sel.page_sel = 0; page_sel.not_used0 = 1;// Default value - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, - 1); + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) + { + goto exit; + } /* unset page write */ - ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); +exit: ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); return ret; @@ -1547,57 +1690,95 @@ int32_t lsm6dsv16b_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, lsb = (uint8_t)address & 0xFFU; ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } /* set page write */ - ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); /* select page */ ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, - 1); + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) + { + goto exit; + } /* set page addr */ page_address.page_addr = lsb; - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } for (i = 0; ((i < len) && (ret == 0)); i++) { - ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_VALUE, &buf[i], 1); + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_VALUE, &buf[i], 1); + if (ret != 0) + { + goto exit; + } lsb++; /* Check if page wrap */ if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) { msb++; - ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1); + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used0 = 1; // Default value - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, - 1); + goto exit; } } } page_sel.page_sel = 0; page_sel.not_used0 = 1;// Default value - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, - 1); + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) + { + goto exit; + } /* unset page write */ - ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); +exit: ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); return ret; @@ -1653,6 +1834,11 @@ int32_t lsm6dsv16b_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + *val = functions_enable.timestamp_en; return ret; @@ -1672,6 +1858,11 @@ int32_t lsm6dsv16b_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TIMESTAMP0, &buff[0], 4); + if (ret != 0) + { + return ret; + } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1733,6 +1924,11 @@ int32_t lsm6dsv16b_filt_anti_spike_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.asf_ctrl) { case LSM6DSV16B_AUTO: @@ -1818,13 +2014,12 @@ int32_t lsm6dsv16b_filt_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); - } - if (ret == 0) + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + return ret; } val->drdy = ctrl4.drdy_mask; @@ -1874,6 +2069,10 @@ int32_t lsm6dsv16b_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6.lpf1_g_bw) { @@ -1954,6 +2153,11 @@ int32_t lsm6dsv16b_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7.lpf1_g_en; return ret; @@ -1998,6 +2202,11 @@ int32_t lsm6dsv16b_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl8.hp_lpf2_xl_bw) { case LSM6DSV16B_XL_ULTRA_LIGHT: @@ -2076,6 +2285,11 @@ int32_t lsm6dsv16b_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.lpf2_xl_en; return ret; @@ -2118,6 +2332,11 @@ int32_t lsm6dsv16b_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.hp_slope_xl_en; return ret; @@ -2160,6 +2379,11 @@ int32_t lsm6dsv16b_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *v int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.xl_fastsettl_mode; return ret; @@ -2204,6 +2428,11 @@ int32_t lsm6dsv16b_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl9.hp_ref_mode_xl) { case LSM6DSV16B_HP_MD_NORMAL: @@ -2237,9 +2466,11 @@ int32_t lsm6dsv16b_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret == 0) + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + return ret; } tap_cfg0.slope_fds = (uint8_t)val & 0x01U; @@ -2275,9 +2506,11 @@ int32_t lsm6dsv16b_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); - if (ret == 0) + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + return ret; } switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) @@ -2339,6 +2572,11 @@ int32_t lsm6dsv16b_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *v int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.hw_func_mask_xl_settl; return ret; @@ -2384,6 +2622,11 @@ int32_t lsm6dsv16b_filt_sixd_feed_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg0.low_pass_on_6d) { case LSM6DSV16B_SIXD_FEED_ODR_DIV_2: @@ -2451,6 +2694,11 @@ int32_t lsm6dsv16b_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.sdo_pu_en; return ret; @@ -2495,6 +2743,11 @@ int32_t lsm6dsv16b_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.i2c_i3c_disable) { case LSM6DSV16B_I2C_I3C_ENABLE: @@ -2549,6 +2802,11 @@ int32_t lsm6dsv16b_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_spi_mode_t * int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.sim) { case LSM6DSV16B_SPI_4_WIRE: @@ -2603,6 +2861,11 @@ int32_t lsm6dsv16b_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.sda_pu_en; return ret; @@ -2647,6 +2910,11 @@ int32_t lsm6dsv16b_i3c_ibi_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5.bus_act_sel) { case LSM6DSV16B_IBI_2us: @@ -2723,6 +2991,11 @@ int32_t lsm6dsv16b_int_pin_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.pp_od) { case LSM6DSV16B_PUSH_PULL: @@ -2779,6 +3052,11 @@ int32_t lsm6dsv16b_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.h_lactive) { case LSM6DSV16B_ACTIVE_HIGH: @@ -3044,11 +3322,12 @@ int32_t lsm6dsv16b_pin_int1_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); } + if (ret == 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; val->timestamp = md2_cfg.int2_timestamp; } } @@ -3056,63 +3335,68 @@ int32_t lsm6dsv16b_pin_int1_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - val->sleep_status = inactivity_dur.sleep_status_on_int; + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD1_CFG, (uint8_t *)&md1_cfg, 1); } if (ret == 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - val->drdy_xl = int1_ctrl.int1_drdy_xl; - val->drdy_gy = int1_ctrl.int1_drdy_g; - val->fifo_th = int1_ctrl.int1_fifo_th; - val->fifo_ovr = int1_ctrl.int1_fifo_ovr; - val->fifo_full = int1_ctrl.int1_fifo_full; - val->fifo_bdr = int1_ctrl.int1_cnt_bdr; - } + val->sleep_status = inactivity_dur.sleep_status_on_int; + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_gy = int1_ctrl.int1_drdy_g; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->fifo_bdr = int1_ctrl.int1_cnt_bdr; - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD1_CFG, (uint8_t *)&md1_cfg, 1); - val->six_d = md1_cfg.int1_6d; - val->double_tap = md1_cfg.int1_double_tap; - val->free_fall = md1_cfg.int1_ff; - val->wake_up = md1_cfg.int1_wu; - val->single_tap = md1_cfg.int1_single_tap; + val->six_d = md1_cfg.int1_6d; + val->double_tap = md1_cfg.int1_double_tap; + val->free_fall = md1_cfg.int1_ff; + val->wake_up = md1_cfg.int1_wu; + val->single_tap = md1_cfg.int1_single_tap; val->sleep_change = md1_cfg.int1_sleep_change; } if (ret == 0) { ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT1, (uint8_t *)&fsm_int1, 1); + } + + if (ret == 0) + { + val->step_detector = emb_func_int1.int1_step_detector; + val->tilt = emb_func_int1.int1_tilt; + val->sig_mot = emb_func_int1.int1_sig_mot; + val->fsm_lc = emb_func_int1.int1_fsm_lc; + + val->fsm1 = fsm_int1.int1_fsm1; + val->fsm2 = fsm_int1.int1_fsm2; + val->fsm3 = fsm_int1.int1_fsm3; + val->fsm4 = fsm_int1.int1_fsm4; + val->fsm5 = fsm_int1.int1_fsm5; + val->fsm6 = fsm_int1.int1_fsm6; + val->fsm7 = fsm_int1.int1_fsm7; + val->fsm8 = fsm_int1.int1_fsm8; + + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); } + if (ret == 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); - val->step_detector = emb_func_int1.int1_step_detector; - val->tilt = emb_func_int1.int1_tilt; - val->sig_mot = emb_func_int1.int1_sig_mot; - val->fsm_lc = emb_func_int1.int1_fsm_lc; - } - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT1, (uint8_t *)&fsm_int1, 1); - val->fsm1 = fsm_int1.int1_fsm1; - val->fsm2 = fsm_int1.int1_fsm2; - val->fsm3 = fsm_int1.int1_fsm3; - val->fsm4 = fsm_int1.int1_fsm4; - val->fsm5 = fsm_int1.int1_fsm5; - val->fsm6 = fsm_int1.int1_fsm6; - val->fsm7 = fsm_int1.int1_fsm7; - val->fsm8 = fsm_int1.int1_fsm8; + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); } - ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); - if (ret == 0) { - ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); val->step_count_overflow = pedo_cmd_reg.carry_count_en; } @@ -3147,10 +3431,7 @@ int32_t lsm6dsv16b_pin_int2_route_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); - } - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT2, (uint8_t *)&fsm_int2, 1); } if (ret == 0) @@ -3334,64 +3615,63 @@ int32_t lsm6dsv16b_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + if (ctrl4.int2_on_int1 == PROPERTY_DISABLE) { - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; - } - if (ret == 0) + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); - val->timestamp = md2_cfg.int2_timestamp; + return ret; } + + val->timestamp = md2_cfg.int2_timestamp; + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; } - if (ret == 0) + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - val->sleep_status = inactivity_dur.sleep_status_on_int; + return ret; } + val->sleep_status = inactivity_dur.sleep_status_on_int; - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->drdy_xl = int2_ctrl.int2_drdy_xl; - val->drdy_gy = int2_ctrl.int2_drdy_g; - val->fifo_th = int2_ctrl.int2_fifo_th; - val->fifo_ovr = int2_ctrl.int2_fifo_ovr; - val->fifo_full = int2_ctrl.int2_fifo_full; - val->fifo_bdr = int2_ctrl.int2_cnt_bdr; - } + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_gy = int2_ctrl.int2_drdy_g; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->fifo_bdr = int2_ctrl.int2_cnt_bdr; - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); - val->six_d = md2_cfg.int2_6d; - val->double_tap = md2_cfg.int2_double_tap; - val->free_fall = md2_cfg.int2_ff; - val->wake_up = md2_cfg.int2_wu; - val->single_tap = md2_cfg.int2_single_tap; - val->sleep_change = md2_cfg.int2_sleep_change; - } + val->six_d = md2_cfg.int2_6d; + val->double_tap = md2_cfg.int2_double_tap; + val->free_fall = md2_cfg.int2_ff; + val->wake_up = md2_cfg.int2_wu; + val->single_tap = md2_cfg.int2_single_tap; + val->sleep_change = md2_cfg.int2_sleep_change; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); if (ret == 0) { - ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT2, (uint8_t *)&fsm_int2, 1); } + if (ret == 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); val->step_detector = emb_func_int2.int2_step_detector; val->tilt = emb_func_int2.int2_tilt; val->sig_mot = emb_func_int2.int2_sig_mot; val->fsm_lc = emb_func_int2.int2_fsm_lc; - } - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT2, (uint8_t *)&fsm_int2, 1); + val->fsm1 = fsm_int2.int2_fsm1; val->fsm2 = fsm_int2.int2_fsm2; val->fsm3 = fsm_int2.int2_fsm3; @@ -3400,6 +3680,7 @@ int32_t lsm6dsv16b_pin_int2_route_get(const stmdev_ctx_t *ctx, val->fsm6 = fsm_int2.int2_fsm6; val->fsm7 = fsm_int2.int2_fsm7; val->fsm8 = fsm_int2.int2_fsm8; + } ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); @@ -3407,6 +3688,10 @@ int32_t lsm6dsv16b_pin_int2_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + if (ret == 0) + { val->step_count_overflow = pedo_cmd_reg.carry_count_en; } @@ -3450,6 +3735,11 @@ int32_t lsm6dsv16b_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl5.int_en_i3c; return ret; @@ -3480,19 +3770,20 @@ int32_t lsm6dsv16b_int_notification_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); - } - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + } - ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + } return ret; } @@ -3516,14 +3807,20 @@ int32_t lsm6dsv16b_int_notification_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); } - if (ret == 0) + + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + return ret; } - ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); - switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir) { case LSM6DSV16B_ALL_INT_PULSED: @@ -3599,6 +3896,11 @@ int32_t lsm6dsv16b_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_act_mode_t * int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + switch (functions_enable.inact_en) { case LSM6DSV16B_XL_AND_GY_NOT_AFFECTED: @@ -3663,6 +3965,11 @@ int32_t lsm6dsv16b_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret != 0) + { + return ret; + } + switch (inactivity_dur.inact_dur) { case LSM6DSV16B_SLEEP_TO_ACT_AT_1ST_SAMPLE: @@ -3727,6 +4034,11 @@ int32_t lsm6dsv16b_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret != 0) + { + return ret; + } + switch (inactivity_dur.xl_inact_odr) { case LSM6DSV16B_1Hz875: @@ -3770,14 +4082,12 @@ int32_t lsm6dsv16b_act_thresholds_set(const stmdev_ctx_t *ctx, float_t tmp; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); - } + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + return ret; } if ((val.wk_ths_mg < (uint32_t)(7.8125f * 63.0f)) @@ -3889,13 +4199,12 @@ int32_t lsm6dsv16b_act_thresholds_get(const stmdev_ctx_t *ctx, float_t tmp; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); - } - if (ret == 0) + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + return ret; } switch (inactivity_dur.wu_inact_ths_w) @@ -3992,6 +4301,11 @@ int32_t lsm6dsv16b_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + val->shock = wake_up_dur.wake_dur; val->quiet = wake_up_dur.sleep_dur; @@ -4052,6 +4366,11 @@ int32_t lsm6dsv16b_tap_detection_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + val->tap_x_en = tap_cfg0.tap_x_en; val->tap_y_en = tap_cfg0.tap_y_en; val->tap_z_en = tap_cfg0.tap_z_en; @@ -4076,13 +4395,11 @@ int32_t lsm6dsv16b_tap_thresholds_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); - } - if (ret == 0) + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + return ret; } tap_cfg1.tap_ths_z = val.z; @@ -4122,13 +4439,11 @@ int32_t lsm6dsv16b_tap_thresholds_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); - } - if (ret == 0) + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + return ret; } val->z = tap_cfg1.tap_ths_z; @@ -4177,6 +4492,11 @@ int32_t lsm6dsv16b_tap_axis_priority_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg1.tap_priority) { case LSM6DSV16B_XYZ : @@ -4252,6 +4572,11 @@ int32_t lsm6dsv16b_tap_time_windows_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret != 0) + { + return ret; + } + val->shock = tap_dur.shock; val->quiet = tap_dur.quiet; val->tap_gap = tap_dur.dur; @@ -4296,6 +4621,11 @@ int32_t lsm6dsv16b_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_tap_mode_t * int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + switch (wake_up_ths.single_double_tap) { case LSM6DSV16B_ONLY_SINGLE: @@ -4365,6 +4695,11 @@ int32_t lsm6dsv16b_6d_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + switch (tap_ths_6d.sixd_ths) { case LSM6DSV16B_DEG_80: @@ -4452,9 +4787,10 @@ int32_t lsm6dsv16b_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret == 0) + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1); + return ret; } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -4501,6 +4837,10 @@ int32_t lsm6dsv16b_ff_thresholds_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -4593,6 +4933,11 @@ int32_t lsm6dsv16b_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl1.wtm; return ret; @@ -4635,6 +4980,11 @@ int32_t lsm6dsv16b_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t * int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; return ret; @@ -4679,6 +5029,10 @@ int32_t lsm6dsv16b_fifo_compress_algo_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl2.uncompr_rate) { @@ -4744,6 +5098,11 @@ int32_t lsm6dsv16b_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odr_chg_en; return ret; @@ -4775,18 +5134,19 @@ int32_t lsm6dsv16b_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); - } - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); - } - if (ret == 0) - { - emb_func_en_b.fifo_compr_en = val; - ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); - } - ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fifo_compr_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + } return ret; } @@ -4806,6 +5166,10 @@ int32_t lsm6dsv16b_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } *val = fifo_ctrl2.fifo_compr_rt_en; @@ -4849,6 +5213,11 @@ int32_t lsm6dsv16b_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -4893,6 +5262,11 @@ int32_t lsm6dsv16b_fifo_xl_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl3.bdr_xl) { case LSM6DSV16B_XL_NOT_BATCHED: @@ -4993,6 +5367,11 @@ int32_t lsm6dsv16b_fifo_gy_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl3.bdr_gy) { case LSM6DSV16B_GY_NOT_BATCHED: @@ -5093,6 +5472,11 @@ int32_t lsm6dsv16b_fifo_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.fifo_mode) { case LSM6DSV16B_BYPASS_MODE: @@ -5169,6 +5553,11 @@ int32_t lsm6dsv16b_fifo_temp_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.odr_t_batch) { case LSM6DSV16B_TEMP_NOT_BATCHED: @@ -5232,7 +5621,12 @@ int32_t lsm6dsv16b_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4; int32_t ret; - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.dec_ts_batch) { case LSM6DSV16B_TMSTMP_NOT_BATCHED: @@ -5301,6 +5695,11 @@ int32_t lsm6dsv16b_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = (uint16_t)buff[0] & 0x3U; *val = (*val * 256U) + (uint16_t)buff[1]; @@ -5347,6 +5746,11 @@ int32_t lsm6dsv16b_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + switch (counter_bdr_reg1.trig_counter_bdr) { case LSM6DSV16B_XL_BATCH_EVENT: @@ -5382,6 +5786,10 @@ int32_t lsm6dsv16b_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; @@ -5412,7 +5820,10 @@ int32_t lsm6dsv16b_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + if (ret == 0) + { val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; @@ -5439,6 +5850,11 @@ int32_t lsm6dsv16b_fifo_status_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + if (ret != 0) + { + return ret; + } + bytecpy((uint8_t *)&status, &buff[1]); val->fifo_bdr = status.counter_bdr_ia; @@ -5468,6 +5884,11 @@ int32_t lsm6dsv16b_fifo_out_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_DATA_OUT_TAG, buff, 7); + if (ret != 0) + { + return ret; + } + bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); switch (fifo_data_out_tag.tag_sensor) @@ -5614,7 +6035,10 @@ int32_t lsm6dsv16b_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); } - *val = emb_func_fifo_en_a.step_counter_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_a.step_counter_fifo_en; + } ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); @@ -5654,10 +6078,7 @@ int32_t lsm6dsv16b_stpcnt_mode_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - } - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } if (ret == 0) { @@ -5707,8 +6128,12 @@ int32_t lsm6dsv16b_stpcnt_mode_get(const stmdev_ctx_t *ctx, { ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); } - val->false_step_rej = pedo_cmd_reg.fp_rejection_en; - val->step_counter_enable = emb_func_en_a.pedo_en; + + if (ret == 0) + { + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + } return ret; } @@ -5734,8 +6159,11 @@ int32_t lsm6dsv16b_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -5789,7 +6217,10 @@ int32_t lsm6dsv16b_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); } - *val = emb_func_src.pedo_rst_step; + if (ret == 0) + { + *val = emb_func_src.pedo_rst_step; + } ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); @@ -5836,7 +6267,10 @@ int32_t lsm6dsv16b_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); - *val = pedo_deb_steps_conf.deb_step; + if (ret == 0) + { + *val = pedo_deb_steps_conf.deb_step; + } return ret; } @@ -5876,8 +6310,12 @@ int32_t lsm6dsv16b_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_SC_DELTAT_L, &buff[0], 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -5943,7 +6381,10 @@ int32_t lsm6dsv16b_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } - *val = emb_func_en_a.sign_motion_en; + if (ret == 0) + { + *val = emb_func_en_a.sign_motion_en; + } ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); @@ -6011,7 +6452,10 @@ int32_t lsm6dsv16b_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } - *val = emb_func_en_a.tilt_en; + if (ret == 0) + { + *val = emb_func_en_a.tilt_en; + } ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); @@ -6047,6 +6491,9 @@ int32_t lsm6dsv16b_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val) if (ret == 0) { ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { emb_func_en_a.sflp_game_en = val; ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); @@ -6074,6 +6521,9 @@ int32_t lsm6dsv16b_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val if (ret == 0) { ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { *val = emb_func_en_a.sflp_game_en; } @@ -6100,6 +6550,9 @@ int32_t lsm6dsv16b_sflp_data_rate_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + } + if (ret == 0) + { sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_SFLP_ODR, (uint8_t *)&sflp_odr, 1); @@ -6125,9 +6578,17 @@ int32_t lsm6dsv16b_sflp_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + } ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (sflp_odr.sflp_game_odr) { case LSM6DSV16B_SFLP_15Hz: @@ -6393,6 +6854,12 @@ int32_t lsm6dsv16b_sflp_game_gbias_set(const stmdev_ctx_t *ctx, ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, conf_saved, 2); ret += lsm6dsv16b_xl_mode_set(ctx, LSM6DSV16B_XL_HIGH_PERFORMANCE_MD); ret += lsm6dsv16b_gy_mode_set(ctx, LSM6DSV16B_GY_HIGH_PERFORMANCE_MD); + + if (ret != 0) + { + return ret; + } + if ((conf_saved[0] & 0x0FU) == LSM6DSV16B_XL_ODR_OFF) { ret += lsm6dsv16b_xl_data_rate_set(ctx, LSM6DSV16B_XL_ODR_AT_120Hz); @@ -6400,29 +6867,59 @@ int32_t lsm6dsv16b_sflp_game_gbias_set(const stmdev_ctx_t *ctx, /* disable algos */ ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, emb_func_en_saved, - 2); - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, reg_zero, 2); - do + + if (ret == 0) + { + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + } + if (ret == 0) + { + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, reg_zero, 2); + } + if (ret == 0) { - ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EXEC_STATUS, - (uint8_t *)&emb_func_sts, 1); - } while (emb_func_sts.emb_func_endop != 1); + do + { + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + } ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + // enable gbias setting ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } ctrl10.emb_func_debug = 1; ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } /* enable algos */ ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); - emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */ - ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, emb_func_en_saved, - 2); + if (ret == 0) + { + emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */ + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + } ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); ret += lsm6dsv16b_xl_full_scale_get(ctx, &xl_fs); + if (ret != 0) + { + return ret; + } /* Read XL data */ do @@ -6430,11 +6927,20 @@ int32_t lsm6dsv16b_sflp_game_gbias_set(const stmdev_ctx_t *ctx, ret += lsm6dsv16b_flag_data_ready_get(ctx, &drdy); } while (drdy.drdy_xl != 1); ret += lsm6dsv16b_acceleration_raw_get(ctx, xl_data); + if (ret != 0) + { + return ret; + } /* force sflp initialization */ master_config = 0x40; ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, &master_config, 1); + if (ret != 0) + { + return ret; + } + for (i = 0; i < 3; i++) { j = 0; @@ -6455,23 +6961,38 @@ int32_t lsm6dsv16b_sflp_game_gbias_set(const stmdev_ctx_t *ctx, master_config = 0x00; ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, &master_config, 1); + if (ret != 0) + { + return ret; + } // wait end_op (and at least 30 us) ctx->mdelay(1); ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); - do + if (ret == 0) { - ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EXEC_STATUS, - (uint8_t *)&emb_func_sts, 1); - } while (emb_func_sts.emb_func_endop != 1); + do + { + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + } ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); /* write gbias in embedded advanced features registers */ ret += lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_SFLP_GAME_GBIASX_L, (uint8_t *)gbias_hf, 6); + if (ret != 0) + { + return ret; + } /* reload previous sensor configuration */ ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL1, conf_saved, 2); + if (ret != 0) + { + return ret; + } // disable gbias setting ctrl10.emb_func_debug = 0; @@ -6549,6 +7070,11 @@ int32_t lsm6dsv16b_fsm_permission_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + switch (func_cfg_access.fsm_wr_ctrl_en) { case LSM6DSV16B_PROTECT_CTRL_REGS: @@ -6581,6 +7107,11 @@ int32_t lsm6dsv16b_fsm_permission_status(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL_STATUS, (uint8_t *)&status, 1); + if (ret != 0) + { + return ret; + } + *val = (status.fsm_wr_ctrl_status == 0) ? LSM6DSV16B_STD_IF_CONTROL : LSM6DSV16B_FSM_CONTROL; return ret; @@ -6661,6 +7192,11 @@ int32_t lsm6dsv16b_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_fsm_mode_t * ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + val->fsm1_en = fsm_enable.fsm1_en; val->fsm2_en = fsm_enable.fsm2_en; val->fsm3_en = fsm_enable.fsm3_en; @@ -6721,6 +7257,11 @@ int32_t lsm6dsv16b_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -6803,6 +7344,11 @@ int32_t lsm6dsv16b_fsm_data_rate_get(const stmdev_ctx_t *ctx, ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (fsm_odr.fsm_odr) { case LSM6DSV16B_FSM_15Hz: @@ -6874,6 +7420,11 @@ int32_t lsm6dsv16b_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *v int32_t ret; ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_FSM_LC_TIMEOUT_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -6917,6 +7468,11 @@ int32_t lsm6dsv16b_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t * int32_t ret; ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + if (ret != 0) + { + return ret; + } + *val = fsm_programs.fsm_n_prog; @@ -6957,6 +7513,11 @@ int32_t lsm6dsv16b_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_FSM_START_ADD_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7013,6 +7574,11 @@ int32_t lsm6dsv16b_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.usr_off_on_out; return ret; @@ -7037,20 +7603,15 @@ int32_t lsm6dsv16b_xl_offset_mg_set(const stmdev_ctx_t *ctx, float_t tmp; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); - } - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); - } - if (ret == 0) + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + return ret; } - if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) && (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f))) @@ -7126,17 +7687,13 @@ int32_t lsm6dsv16b_xl_offset_mg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); - } - if (ret == 0) - { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); - } - if (ret == 0) + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + + if (ret != 0) { - ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + return ret; } if (ctrl9.usr_off_w == PROPERTY_DISABLE) @@ -7207,6 +7764,11 @@ int32_t lsm6dsv16b_i3c_reset_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + switch (pin_ctrl.ibhr_por_en) { case LSM6DSV16B_SW_RST_DYN_ADDRESS_RST: @@ -7274,6 +7836,11 @@ int32_t lsm6dsv16b_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *va int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.tdm_wclk_pu_dis; return ret; @@ -7316,6 +7883,11 @@ int32_t lsm6dsv16b_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.tdm_out_pu_en; return ret; @@ -7361,6 +7933,11 @@ int32_t lsm6dsv16b_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch ((tdm_cfg0.tdm_wclk_bclk_sel << 2) + tdm_cfg0.tdm_wclk) { case LSM6DSV16B_WCLK_16kHZ_BCLK_2048kHz: @@ -7415,6 +7992,11 @@ int32_t lsm6dsv16b_tdm_slot_get(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_slot_t * int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (tdm_cfg0.tdm_slot_sel) { case LSM6DSV16B_SLOT_012: @@ -7471,6 +8053,11 @@ int32_t lsm6dsv16b_tdm_bclk_edge_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (tdm_cfg0.tdm_bclk_edge_sel) { case LSM6DSV16B_BCLK_RISING: @@ -7525,6 +8112,11 @@ int32_t lsm6dsv16b_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tdm_cfg0.tdm_delayed_cfg; return ret; @@ -7570,6 +8162,11 @@ int32_t lsm6dsv16b_tdm_axis_order_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + if (ret != 0) + { + return ret; + } + switch (tdm_cfg1.tdm_axes_ord_sel) { case LSM6DSV16B_TDM_ORDER_ZYX: @@ -7630,6 +8227,11 @@ int32_t lsm6dsv16b_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + if (ret != 0) + { + return ret; + } + switch (tdm_cfg2.tdm_fs_xl) { case LSM6DSV16B_TDM_2g: @@ -7661,4 +8263,3 @@ int32_t lsm6dsv16b_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.h b/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.h index 21d25f4..1d811b6 100644 --- a/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.h +++ b/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -3404,5 +3406,3 @@ int32_t lsm6dsv16b_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, #endif #endif /*LSM6DSV16B_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.c b/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.c index e5bc0eb..b087bf1 100644 --- a/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.c +++ b/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -215,23 +214,19 @@ int32_t lsm6dsv16bx_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + return ret; } - ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; - ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; - func_cfg_access.sw_por = (uint8_t)val & 0x01U; + ctrl3.boot = (val == LSM6DSV16BX_RESTORE_CAL_PARAM) ? 1 : 0; + ctrl3.sw_reset = (val == LSM6DSV16BX_RESTORE_CTRL_REGS) ? 1 : 0; + func_cfg_access.sw_por = (val == LSM6DSV16BX_GLOBAL_RST) ? 1 : 0; - if (ret == 0) - { - ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); - } - if (ret == 0) - { - ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - } + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); return ret; } @@ -251,9 +246,11 @@ int32_t lsm6dsv16bx_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + return ret; } switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) @@ -318,6 +315,10 @@ int32_t lsm6dsv16bx_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } switch (func_cfg_access.emb_func_reg_access) { @@ -350,6 +351,11 @@ int32_t lsm6dsv16bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WHO_AM_I, (uint8_t *)&who_am_i, 1); + if (ret != 0) + { + return ret; + } + *val = who_am_i.id; return ret; @@ -394,6 +400,10 @@ int32_t lsm6dsv16bx_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1.odr_xl) { @@ -494,6 +504,10 @@ int32_t lsm6dsv16bx_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t * int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1.op_mode_xl) { @@ -564,6 +578,10 @@ int32_t lsm6dsv16bx_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2.odr_g) { @@ -659,6 +677,11 @@ int32_t lsm6dsv16bx_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t * int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2.op_mode_g) { case LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD: @@ -717,6 +740,11 @@ int32_t lsm6dsv16bx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.if_inc; @@ -761,6 +789,11 @@ int32_t lsm6dsv16bx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.bdu; return ret; @@ -806,6 +839,10 @@ int32_t lsm6dsv16bx_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4.drdy_pulsed) { @@ -864,6 +901,10 @@ int32_t lsm6dsv16bx_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6.fs_g) { @@ -938,6 +979,10 @@ int32_t lsm6dsv16bx_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } switch (ctrl8.fs_xl) { @@ -1002,6 +1047,11 @@ int32_t lsm6dsv16bx_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8.xl_dualc_en; return ret; @@ -1048,6 +1098,10 @@ int32_t lsm6dsv16bx_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } //switch (ctrl10.xl_st_offset) switch (ctrl10.st_xl) @@ -1111,6 +1165,10 @@ int32_t lsm6dsv16bx_gy_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } switch (ctrl10.st_g) { @@ -1170,6 +1228,12 @@ int32_t lsm6dsv16bx_all_sources_get(const stmdev_ctx_t *ctx, { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_STATUS1, (uint8_t *)&buff, 4); } + + if (ret != 0) + { + return ret; + } + bytecpy((uint8_t *)&fifo_status2, &buff[1]); bytecpy((uint8_t *)&all_int_src, &buff[2]); bytecpy((uint8_t *)&status_reg, &buff[3]); @@ -1257,19 +1321,25 @@ int32_t lsm6dsv16bx_all_sources_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, + 1); + } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); } - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, - 1); - } - if (ret == 0) + + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + return ret; } - ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); - val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; val->step_count_inc = emb_func_src.stepcounter_bit_set; @@ -1288,6 +1358,11 @@ int32_t lsm6dsv16bx_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_STATUS_REG, (uint8_t *)&status, 1); + if (ret != 0) + { + return ret; + } + val->drdy_xl = status.xlda; val->drdy_gy = status.gda; val->drdy_temp = status.tda; @@ -1310,6 +1385,11 @@ int32_t lsm6dsv16bx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_OUT_TEMP_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1330,6 +1410,11 @@ int32_t lsm6dsv16bx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_OUTX_L_G, &buff[0], 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1354,6 +1439,11 @@ int32_t lsm6dsv16bx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_OUTZ_L_A, &buff[0], 6); + if (ret != 0) + { + return ret; + } + val[2] = (int16_t)buff[1]; val[2] = (val[2] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1378,6 +1468,11 @@ int32_t lsm6dsv16bx_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t * int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_UI_OUTZ_L_A_DUALC, &buff[0], 6); + if (ret != 0) + { + return ret; + } + val[2] = (int16_t)buff[1]; val[2] = (val[2] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1402,6 +1497,11 @@ int32_t lsm6dsv16bx_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_AH_QVAR_OUT_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1422,6 +1522,11 @@ int32_t lsm6dsv16bx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + if (ret != 0) + { + return ret; + } + *val = (int8_t)internal_freq.freq_fine; return ret; @@ -1466,6 +1571,11 @@ int32_t lsm6dsv16bx_tdm_xl_axis_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_xl_ int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + if (ret != 0) + { + return ret; + } + val->x = tdm_cfg1.tdm_xl_x_en; val->y = tdm_cfg1.tdm_xl_y_en; val->z = tdm_cfg1.tdm_xl_z_en; @@ -1496,57 +1606,95 @@ int32_t lsm6dsv16bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, lsb = (uint8_t)address & 0xFFU; ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } /* set page write */ - ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_ENABLE; - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); /* select page */ ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } /* set page addr */ page_address.page_addr = lsb; ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_ADDRESS, (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } for (i = 0; ((i < len) && (ret == 0)); i++) { - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_VALUE, &buf[i], 1); + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) + { + goto exit; + } lsb++; /* Check if page wrap */ if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) { msb++; - ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used0 = 1; // Default value - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + goto exit; } } } page_sel.page_sel = 0; page_sel.not_used0 = 1;// Default value - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) + { + goto exit; + } /* unset page write */ - ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); +exit: ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); return ret; @@ -1575,57 +1723,95 @@ int32_t lsm6dsv16bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, lsb = (uint8_t)address & 0xFFU; ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } /* set page write */ - ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); /* select page */ ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) + { + goto exit; + } /* set page addr */ page_address.page_addr = lsb; - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } for (i = 0; ((i < len) && (ret == 0)); i++) { - ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_VALUE, &buf[i], 1); + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) + { + goto exit; + } lsb++; /* Check if page wrap */ if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) { msb++; - ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used0 = 1; // Default value - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + goto exit; } } } page_sel.page_sel = 0; page_sel.not_used0 = 1;// Default value - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) + { + goto exit; + } /* unset page write */ - ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); +exit: ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); return ret; @@ -1681,6 +1867,11 @@ int32_t lsm6dsv16bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + *val = functions_enable.timestamp_en; return ret; @@ -1700,6 +1891,11 @@ int32_t lsm6dsv16bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TIMESTAMP0, &buff[0], 4); + if (ret != 0) + { + return ret; + } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1761,6 +1957,11 @@ int32_t lsm6dsv16bx_filt_anti_spike_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.asf_ctrl) { case LSM6DSV16BX_AUTO: @@ -1846,13 +2047,12 @@ int32_t lsm6dsv16bx_filt_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); - } - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + return ret; } val->drdy = ctrl4.drdy_mask; @@ -1902,6 +2102,10 @@ int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6.lpf1_g_bw) { @@ -1982,6 +2186,11 @@ int32_t lsm6dsv16bx_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7.lpf1_g_en; return ret; @@ -2003,10 +2212,7 @@ int32_t lsm6dsv16bx_filt_ah_qvar_conf_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); - } + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); ctrl8.ah_qvar_hpf = val.hpf; ctrl9.ah_qvar_lpf = val.lpf; @@ -2039,9 +2245,11 @@ int32_t lsm6dsv16bx_filt_ah_qvar_conf_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + return ret; } val->lpf = ctrl9.ah_qvar_lpf; @@ -2089,6 +2297,11 @@ int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl8.hp_lpf2_xl_bw) { case LSM6DSV16BX_XL_ULTRA_LIGHT: @@ -2167,6 +2380,11 @@ int32_t lsm6dsv16bx_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.lpf2_xl_en; return ret; @@ -2209,6 +2427,11 @@ int32_t lsm6dsv16bx_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.hp_slope_xl_en; return ret; @@ -2251,6 +2474,11 @@ int32_t lsm6dsv16bx_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t * int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.xl_fastsettl_mode; return ret; @@ -2295,6 +2523,11 @@ int32_t lsm6dsv16bx_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl9.hp_ref_mode_xl) { case LSM6DSV16BX_HP_MD_NORMAL: @@ -2328,9 +2561,11 @@ int32_t lsm6dsv16bx_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + return ret; } tap_cfg0.slope_fds = (uint8_t)val & 0x01U; @@ -2366,9 +2601,11 @@ int32_t lsm6dsv16bx_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + return ret; } switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) @@ -2430,6 +2667,11 @@ int32_t lsm6dsv16bx_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t * int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.hw_func_mask_xl_settl; return ret; @@ -2475,6 +2717,11 @@ int32_t lsm6dsv16bx_filt_sixd_feed_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg0.low_pass_on_6d) { case LSM6DSV16BX_SIXD_FEED_ODR_DIV_2: @@ -2542,6 +2789,11 @@ int32_t lsm6dsv16bx_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.sdo_pu_en; return ret; @@ -2586,6 +2838,11 @@ int32_t lsm6dsv16bx_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.i2c_i3c_disable) { case LSM6DSV16BX_I2C_I3C_ENABLE: @@ -2640,6 +2897,11 @@ int32_t lsm6dsv16bx_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.sim) { case LSM6DSV16BX_SPI_4_WIRE: @@ -2694,6 +2956,11 @@ int32_t lsm6dsv16bx_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.sda_pu_en; return ret; @@ -2738,6 +3005,11 @@ int32_t lsm6dsv16bx_i3c_ibi_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5.bus_act_sel) { case LSM6DSV16BX_IBI_2us: @@ -2814,6 +3086,11 @@ int32_t lsm6dsv16bx_int_pin_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.pp_od) { case LSM6DSV16BX_PUSH_PULL: @@ -2870,6 +3147,11 @@ int32_t lsm6dsv16bx_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.h_lactive) { case LSM6DSV16BX_ACTIVE_HIGH: @@ -3153,11 +3435,12 @@ int32_t lsm6dsv16bx_pin_int1_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); } + if (ret == 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; val->timestamp = md2_cfg.int2_timestamp; } } @@ -3165,71 +3448,73 @@ int32_t lsm6dsv16bx_pin_int1_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - val->sleep_status = inactivity_dur.sleep_status_on_int; + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD1_CFG, (uint8_t *)&md1_cfg, 1); } if (ret == 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - val->drdy_xl = int1_ctrl.int1_drdy_xl; - val->drdy_gy = int1_ctrl.int1_drdy_g; - val->fifo_th = int1_ctrl.int1_fifo_th; - val->fifo_ovr = int1_ctrl.int1_fifo_ovr; - val->fifo_full = int1_ctrl.int1_fifo_full; - val->fifo_bdr = int1_ctrl.int1_cnt_bdr; - } + val->sleep_status = inactivity_dur.sleep_status_on_int; + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_gy = int1_ctrl.int1_drdy_g; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->fifo_bdr = int1_ctrl.int1_cnt_bdr; - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD1_CFG, (uint8_t *)&md1_cfg, 1); - val->six_d = md1_cfg.int1_6d; - val->double_tap = md1_cfg.int1_double_tap; - val->free_fall = md1_cfg.int1_ff; - val->wake_up = md1_cfg.int1_wu; - val->single_tap = md1_cfg.int1_single_tap; + val->six_d = md1_cfg.int1_6d; + val->double_tap = md1_cfg.int1_double_tap; + val->free_fall = md1_cfg.int1_ff; + val->wake_up = md1_cfg.int1_wu; + val->single_tap = md1_cfg.int1_single_tap; val->sleep_change = md1_cfg.int1_sleep_change; } if (ret == 0) { ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT1, (uint8_t *)&fsm_int1, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT1, (uint8_t *)&mlc_int1, 1); + } + + if (ret == 0) + { + val->step_detector = emb_func_int1.int1_step_detector; + val->tilt = emb_func_int1.int1_tilt; + val->sig_mot = emb_func_int1.int1_sig_mot; + val->fsm_lc = emb_func_int1.int1_fsm_lc; + + val->fsm1 = fsm_int1.int1_fsm1; + val->fsm2 = fsm_int1.int1_fsm2; + val->fsm3 = fsm_int1.int1_fsm3; + val->fsm4 = fsm_int1.int1_fsm4; + val->fsm5 = fsm_int1.int1_fsm5; + val->fsm6 = fsm_int1.int1_fsm6; + val->fsm7 = fsm_int1.int1_fsm7; + val->fsm8 = fsm_int1.int1_fsm8; + + val->mlc1 = mlc_int1.int1_mlc1; + val->mlc2 = mlc_int1.int1_mlc2; + val->mlc3 = mlc_int1.int1_mlc3; + val->mlc4 = mlc_int1.int1_mlc4; + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); } + if (ret == 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); - val->step_detector = emb_func_int1.int1_step_detector; - val->tilt = emb_func_int1.int1_tilt; - val->sig_mot = emb_func_int1.int1_sig_mot; - val->fsm_lc = emb_func_int1.int1_fsm_lc; - } - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT1, (uint8_t *)&fsm_int1, 1); - val->fsm1 = fsm_int1.int1_fsm1; - val->fsm2 = fsm_int1.int1_fsm2; - val->fsm3 = fsm_int1.int1_fsm3; - val->fsm4 = fsm_int1.int1_fsm4; - val->fsm5 = fsm_int1.int1_fsm5; - val->fsm6 = fsm_int1.int1_fsm6; - val->fsm7 = fsm_int1.int1_fsm7; - val->fsm8 = fsm_int1.int1_fsm8; - } - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT1, (uint8_t *)&mlc_int1, 1); - val->mlc1 = mlc_int1.int1_mlc1; - val->mlc2 = mlc_int1.int1_mlc2; - val->mlc3 = mlc_int1.int1_mlc3; - val->mlc4 = mlc_int1.int1_mlc4; + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); } - ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); - if (ret == 0) { - ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); val->step_count_overflow = pedo_cmd_reg.carry_count_en; } @@ -3266,14 +3551,8 @@ int32_t lsm6dsv16bx_pin_int2_route_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); - } - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); - } - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); } if (ret == 0) @@ -3352,6 +3631,10 @@ int32_t lsm6dsv16bx_pin_int2_route_set(const stmdev_ctx_t *ctx, { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); ctrl7.int2_drdy_ah_qvar = val.drdy_ah_qvar; + } + + if (ret == 0) + { ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); } @@ -3478,70 +3761,67 @@ int32_t lsm6dsv16bx_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + if (ctrl4.int2_on_int1 == PROPERTY_DISABLE) { - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; - } - if (ret == 0) + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); - val->timestamp = md2_cfg.int2_timestamp; + return ret; } + + val->timestamp = md2_cfg.int2_timestamp; + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; } - if (ret == 0) + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - val->sleep_status = inactivity_dur.sleep_status_on_int; + return ret; } + val->sleep_status = inactivity_dur.sleep_status_on_int; - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->drdy_xl = int2_ctrl.int2_drdy_xl; - val->drdy_gy = int2_ctrl.int2_drdy_g; - val->fifo_th = int2_ctrl.int2_fifo_th; - val->fifo_ovr = int2_ctrl.int2_fifo_ovr; - val->fifo_full = int2_ctrl.int2_fifo_full; - val->fifo_bdr = int2_ctrl.int2_cnt_bdr; - } + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_gy = int2_ctrl.int2_drdy_g; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->fifo_bdr = int2_ctrl.int2_cnt_bdr; - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); - val->drdy_ah_qvar = ctrl7.int2_drdy_ah_qvar; - } + val->six_d = md2_cfg.int2_6d; + val->double_tap = md2_cfg.int2_double_tap; + val->free_fall = md2_cfg.int2_ff; + val->wake_up = md2_cfg.int2_wu; + val->single_tap = md2_cfg.int2_single_tap; + val->sleep_change = md2_cfg.int2_sleep_change; - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); - val->six_d = md2_cfg.int2_6d; - val->double_tap = md2_cfg.int2_double_tap; - val->free_fall = md2_cfg.int2_ff; - val->wake_up = md2_cfg.int2_wu; - val->single_tap = md2_cfg.int2_single_tap; - val->sleep_change = md2_cfg.int2_sleep_change; - } + val->drdy_ah_qvar = ctrl7.int2_drdy_ah_qvar; + + ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); if (ret == 0) { - ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); } + if (ret == 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); val->step_detector = emb_func_int2.int2_step_detector; val->tilt = emb_func_int2.int2_tilt; val->sig_mot = emb_func_int2.int2_sig_mot; val->fsm_lc = emb_func_int2.int2_fsm_lc; - } - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + val->fsm1 = fsm_int2.int2_fsm1; val->fsm2 = fsm_int2.int2_fsm2; val->fsm3 = fsm_int2.int2_fsm3; @@ -3550,10 +3830,7 @@ int32_t lsm6dsv16bx_pin_int2_route_get(const stmdev_ctx_t *ctx, val->fsm6 = fsm_int2.int2_fsm6; val->fsm7 = fsm_int2.int2_fsm7; val->fsm8 = fsm_int2.int2_fsm8; - } - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + val->mlc1 = mlc_int2.int2_mlc1; val->mlc2 = mlc_int2.int2_mlc2; val->mlc3 = mlc_int2.int2_mlc3; @@ -3565,6 +3842,10 @@ int32_t lsm6dsv16bx_pin_int2_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + if (ret == 0) + { val->step_count_overflow = pedo_cmd_reg.carry_count_en; } @@ -3608,6 +3889,11 @@ int32_t lsm6dsv16bx_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *va int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl5.int_en_i3c; return ret; @@ -3638,19 +3924,20 @@ int32_t lsm6dsv16bx_int_notification_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); - } - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } - ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + } return ret; } @@ -3674,14 +3961,20 @@ int32_t lsm6dsv16bx_int_notification_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); } - if (ret == 0) + + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1); + return ret; } - ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); - switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir) { case LSM6DSV16BX_ALL_INT_PULSED: @@ -3757,6 +4050,11 @@ int32_t lsm6dsv16bx_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + switch (functions_enable.inact_en) { case LSM6DSV16BX_XL_AND_GY_NOT_AFFECTED: @@ -3821,6 +4119,11 @@ int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret != 0) + { + return ret; + } + switch (inactivity_dur.inact_dur) { case LSM6DSV16BX_SLEEP_TO_ACT_AT_1ST_SAMPLE: @@ -3885,6 +4188,11 @@ int32_t lsm6dsv16bx_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret != 0) + { + return ret; + } + switch (inactivity_dur.xl_inact_odr) { case LSM6DSV16BX_1Hz875: @@ -3928,14 +4236,12 @@ int32_t lsm6dsv16bx_act_thresholds_set(const stmdev_ctx_t *ctx, float_t tmp; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); - } + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + return ret; } if ((val.wk_ths_mg < (uint32_t)(7.8125f * 63.0f)) @@ -4047,13 +4353,12 @@ int32_t lsm6dsv16bx_act_thresholds_get(const stmdev_ctx_t *ctx, float_t tmp; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); - } - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + return ret; } switch (inactivity_dur.wu_inact_ths_w) @@ -4150,6 +4455,11 @@ int32_t lsm6dsv16bx_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + val->shock = wake_up_dur.wake_dur; val->quiet = wake_up_dur.sleep_dur; @@ -4210,6 +4520,11 @@ int32_t lsm6dsv16bx_tap_detection_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + val->tap_x_en = tap_cfg0.tap_x_en; val->tap_y_en = tap_cfg0.tap_y_en; val->tap_z_en = tap_cfg0.tap_z_en; @@ -4234,13 +4549,11 @@ int32_t lsm6dsv16bx_tap_thresholds_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); - } - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + return ret; } tap_cfg1.tap_ths_z = val.z; @@ -4280,13 +4593,11 @@ int32_t lsm6dsv16bx_tap_thresholds_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); - } - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + return ret; } val->z = tap_cfg1.tap_ths_z; @@ -4335,6 +4646,11 @@ int32_t lsm6dsv16bx_tap_axis_priority_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg1.tap_priority) { case LSM6DSV16BX_XYZ : @@ -4410,6 +4726,11 @@ int32_t lsm6dsv16bx_tap_time_windows_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret != 0) + { + return ret; + } + val->shock = tap_dur.shock; val->quiet = tap_dur.quiet; val->tap_gap = tap_dur.dur; @@ -4454,6 +4775,11 @@ int32_t lsm6dsv16bx_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + switch (wake_up_ths.single_double_tap) { case LSM6DSV16BX_ONLY_SINGLE: @@ -4523,6 +4849,11 @@ int32_t lsm6dsv16bx_6d_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + switch (tap_ths_6d.sixd_ths) { case LSM6DSV16BX_DEG_80: @@ -4610,9 +4941,10 @@ int32_t lsm6dsv16bx_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1); + return ret; } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -4659,6 +4991,10 @@ int32_t lsm6dsv16bx_ff_thresholds_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -4751,6 +5087,11 @@ int32_t lsm6dsv16bx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl1.wtm; return ret; @@ -4793,6 +5134,11 @@ int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; return ret; @@ -4837,6 +5183,10 @@ int32_t lsm6dsv16bx_fifo_compress_algo_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl2.uncompr_rate) { @@ -4902,6 +5252,11 @@ int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odr_chg_en; return ret; @@ -4933,18 +5288,19 @@ int32_t lsm6dsv16bx_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); - } - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); - } - if (ret == 0) - { - emb_func_en_b.fifo_compr_en = val; - ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); - } - ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fifo_compr_en = val; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + } return ret; } @@ -4964,6 +5320,10 @@ int32_t lsm6dsv16bx_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } *val = fifo_ctrl2.fifo_compr_rt_en; @@ -5007,6 +5367,11 @@ int32_t lsm6dsv16bx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -5051,6 +5416,11 @@ int32_t lsm6dsv16bx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl3.bdr_xl) { case LSM6DSV16BX_XL_NOT_BATCHED: @@ -5151,6 +5521,11 @@ int32_t lsm6dsv16bx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl3.bdr_gy) { case LSM6DSV16BX_GY_NOT_BATCHED: @@ -5251,6 +5626,11 @@ int32_t lsm6dsv16bx_fifo_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.fifo_mode) { case LSM6DSV16BX_BYPASS_MODE: @@ -5327,6 +5707,11 @@ int32_t lsm6dsv16bx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.odr_t_batch) { case LSM6DSV16BX_TEMP_NOT_BATCHED: @@ -5391,6 +5776,11 @@ int32_t lsm6dsv16bx_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.dec_ts_batch) { case LSM6DSV16BX_TMSTMP_NOT_BATCHED: @@ -5459,6 +5849,11 @@ int32_t lsm6dsv16bx_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = (uint16_t)buff[0] & 0x3U; *val = (*val * 256U) + (uint16_t)buff[1]; @@ -5502,6 +5897,11 @@ int32_t lsm6dsv16bx_fifo_batch_ah_qvar_get(const stmdev_ctx_t *ctx, uint8_t *val int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + *val = counter_bdr_reg1.ah_qvar_batch_en; return ret; @@ -5547,6 +5947,11 @@ int32_t lsm6dsv16bx_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + switch (counter_bdr_reg1.trig_counter_bdr) { case LSM6DSV16BX_XL_BATCH_EVENT: @@ -5582,6 +5987,10 @@ int32_t lsm6dsv16bx_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; @@ -5612,7 +6021,10 @@ int32_t lsm6dsv16bx_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + if (ret == 0) + { val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; @@ -5639,6 +6051,11 @@ int32_t lsm6dsv16bx_fifo_status_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + if (ret != 0) + { + return ret; + } + bytecpy((uint8_t *)&status, &buff[1]); val->fifo_bdr = status.counter_bdr_ia; @@ -5668,6 +6085,11 @@ int32_t lsm6dsv16bx_fifo_out_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_DATA_OUT_TAG, buff, 7); + if (ret != 0) + { + return ret; + } + bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); switch (fifo_data_out_tag.tag_sensor) @@ -5830,7 +6252,10 @@ int32_t lsm6dsv16bx_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); } - *val = emb_func_fifo_en_a.step_counter_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_a.step_counter_fifo_en; + } ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); @@ -5887,7 +6312,10 @@ int32_t lsm6dsv16bx_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); } - *val = emb_func_fifo_en_a.mlc_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_a.mlc_fifo_en; + } ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); @@ -5943,7 +6371,10 @@ int32_t lsm6dsv16bx_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *va ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); } - *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + } ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); @@ -5982,10 +6413,7 @@ int32_t lsm6dsv16bx_stpcnt_mode_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - } - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } if ((val.false_step_rej == PROPERTY_ENABLE) && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == @@ -6041,8 +6469,12 @@ int32_t lsm6dsv16bx_stpcnt_mode_get(const stmdev_ctx_t *ctx, { ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); } - val->false_step_rej = pedo_cmd_reg.fp_rejection_en; - val->step_counter_enable = emb_func_en_a.pedo_en; + + if (ret == 0) + { + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + } return ret; } @@ -6068,8 +6500,11 @@ int32_t lsm6dsv16bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -6123,7 +6558,10 @@ int32_t lsm6dsv16bx_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); } - *val = emb_func_src.pedo_rst_step; + if (ret == 0) + { + *val = emb_func_src.pedo_rst_step; + } ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); @@ -6170,7 +6608,10 @@ int32_t lsm6dsv16bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); - *val = pedo_deb_steps_conf.deb_step; + if (ret == 0) + { + *val = pedo_deb_steps_conf.deb_step; + } return ret; } @@ -6210,8 +6651,12 @@ int32_t lsm6dsv16bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_SC_DELTAT_L, &buff[0], 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -6277,7 +6722,10 @@ int32_t lsm6dsv16bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } - *val = emb_func_en_a.sign_motion_en; + if (ret == 0) + { + *val = emb_func_en_a.sign_motion_en; + } ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); @@ -6345,7 +6793,10 @@ int32_t lsm6dsv16bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } - *val = emb_func_en_a.tilt_en; + if (ret == 0) + { + *val = emb_func_en_a.tilt_en; + } ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); @@ -6381,6 +6832,9 @@ int32_t lsm6dsv16bx_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val if (ret == 0) { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { emb_func_en_a.sflp_game_en = val; ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); @@ -6408,6 +6862,9 @@ int32_t lsm6dsv16bx_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *va if (ret == 0) { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { *val = emb_func_en_a.sflp_game_en; } @@ -6434,6 +6891,9 @@ int32_t lsm6dsv16bx_sflp_data_rate_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + } + if (ret == 0) + { sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); @@ -6459,9 +6919,17 @@ int32_t lsm6dsv16bx_sflp_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + } ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (sflp_odr.sflp_game_odr) { case LSM6DSV16BX_SFLP_15Hz: @@ -6727,6 +7195,12 @@ int32_t lsm6dsv16bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, conf_saved, 2); ret += lsm6dsv16bx_xl_mode_set(ctx, LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD); ret += lsm6dsv16bx_gy_mode_set(ctx, LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD); + + if (ret != 0) + { + return ret; + } + if ((conf_saved[0] & 0x0FU) == LSM6DSV16BX_XL_ODR_OFF) { ret += lsm6dsv16bx_xl_data_rate_set(ctx, LSM6DSV16BX_XL_ODR_AT_120Hz); @@ -6734,29 +7208,59 @@ int32_t lsm6dsv16bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, /* disable algos */ ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, emb_func_en_saved, - 2); - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, reg_zero, 2); - do + + if (ret == 0) { - ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, - (uint8_t *)&emb_func_sts, 1); - } while (emb_func_sts.emb_func_endop != 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + } + if (ret == 0) + { + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, reg_zero, 2); + } + if (ret == 0) + { + do + { + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + } ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + // enable gbias setting ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } ctrl10.emb_func_debug = 1; ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } /* enable algos */ ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); - emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */ - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, emb_func_en_saved, - 2); + if (ret == 0) + { + emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */ + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + } ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); ret += lsm6dsv16bx_xl_full_scale_get(ctx, &xl_fs); + if (ret != 0) + { + return ret; + } /* Read XL data */ do @@ -6764,11 +7268,20 @@ int32_t lsm6dsv16bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, ret += lsm6dsv16bx_flag_data_ready_get(ctx, &drdy); } while (drdy.drdy_xl != 1); ret += lsm6dsv16bx_acceleration_raw_get(ctx, xl_data); + if (ret != 0) + { + return ret; + } /* force sflp initialization */ master_config = 0x40; ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, &master_config, 1); + if (ret != 0) + { + return ret; + } + for (i = 0; i < 3; i++) { j = 0; @@ -6789,23 +7302,38 @@ int32_t lsm6dsv16bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, master_config = 0x00; ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, &master_config, 1); + if (ret != 0) + { + return ret; + } // wait end_op (and at least 30 us) ctx->mdelay(1); ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK); - do + if (ret == 0) { - ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, - (uint8_t *)&emb_func_sts, 1); - } while (emb_func_sts.emb_func_endop != 1); + do + { + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + } ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); /* write gbias in embedded advanced features registers */ ret += lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_SFLP_GAME_GBIASX_L, (uint8_t *)gbias_hf, 6); + if (ret != 0) + { + return ret; + } /* reload previous sensor configuration */ ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL1, conf_saved, 2); + if (ret != 0) + { + return ret; + } // disable gbias setting ctrl10.emb_func_debug = 0; @@ -6883,6 +7411,11 @@ int32_t lsm6dsv16bx_fsm_permission_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + switch (func_cfg_access.fsm_wr_ctrl_en) { case LSM6DSV16BX_PROTECT_CTRL_REGS: @@ -6915,6 +7448,11 @@ int32_t lsm6dsv16bx_fsm_permission_status(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL_STATUS, (uint8_t *)&status, 1); + if (ret != 0) + { + return ret; + } + *val = (status.fsm_wr_ctrl_status == 0) ? LSM6DSV16BX_STD_IF_CONTROL : LSM6DSV16BX_FSM_CONTROL; return ret; @@ -6995,6 +7533,11 @@ int32_t lsm6dsv16bx_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + val->fsm1_en = fsm_enable.fsm1_en; val->fsm2_en = fsm_enable.fsm2_en; val->fsm3_en = fsm_enable.fsm3_en; @@ -7055,6 +7598,11 @@ int32_t lsm6dsv16bx_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7137,6 +7685,11 @@ int32_t lsm6dsv16bx_fsm_data_rate_get(const stmdev_ctx_t *ctx, ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (fsm_odr.fsm_odr) { case LSM6DSV16BX_FSM_15Hz: @@ -7208,6 +7761,11 @@ int32_t lsm6dsv16bx_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t * int32_t ret; ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_LC_TIMEOUT_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7251,6 +7809,11 @@ int32_t lsm6dsv16bx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t int32_t ret; ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + if (ret != 0) + { + return ret; + } + *val = fsm_programs.fsm_n_prog; @@ -7291,6 +7854,11 @@ int32_t lsm6dsv16bx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val int32_t ret; ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_START_ADD_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7331,26 +7899,29 @@ int32_t lsm6dsv16bx_mlc_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t val) ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - switch (val) + if (ret == 0) { - case LSM6DSV16BX_MLC_OFF: - emb_en_a.mlc_before_fsm_en = 0; - emb_en_b.mlc_en = 0; - break; - case LSM6DSV16BX_MLC_ON: - emb_en_a.mlc_before_fsm_en = 0; - emb_en_b.mlc_en = 1; - break; - case LSM6DSV16BX_MLC_ON_BEFORE_FSM: - emb_en_a.mlc_before_fsm_en = 1; - emb_en_b.mlc_en = 0; - break; - default: - break; - } + switch (val) + { + case LSM6DSV16BX_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case LSM6DSV16BX_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case LSM6DSV16BX_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + break; + } - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); - ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } } ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); @@ -7379,21 +7950,24 @@ int32_t lsm6dsv16bx_mlc_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t *val ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) - { - *val = LSM6DSV16BX_MLC_OFF; - } - else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) - { - *val = LSM6DSV16BX_MLC_ON; - } - else if (emb_en_a.mlc_before_fsm_en == 1U) - { - *val = LSM6DSV16BX_MLC_ON_BEFORE_FSM; - } - else + if (ret == 0) { - /* Do nothing */ + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = LSM6DSV16BX_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = LSM6DSV16BX_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = LSM6DSV16BX_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } } } @@ -7455,6 +8029,11 @@ int32_t lsm6dsv16bx_mlc_data_rate_get(const stmdev_ctx_t *ctx, ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (mlc_odr.mlc_odr) { case LSM6DSV16BX_MLC_15Hz: @@ -7554,6 +8133,12 @@ int32_t lsm6dsv16bx_mlc_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t * int32_t ret; ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_MLC_QVAR_SENSITIVITY_L, &buff[0], 2); + + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7610,6 +8195,11 @@ int32_t lsm6dsv16bx_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.usr_off_on_out; return ret; @@ -7634,20 +8224,15 @@ int32_t lsm6dsv16bx_xl_offset_mg_set(const stmdev_ctx_t *ctx, float_t tmp; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); - } - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); - } - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + return ret; } - if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) && (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f))) @@ -7723,17 +8308,13 @@ int32_t lsm6dsv16bx_xl_offset_mg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1); - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); - } - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); - } - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + return ret; } if (ctrl9.usr_off_w == PROPERTY_DISABLE) @@ -7783,10 +8364,7 @@ int32_t lsm6dsv16bx_ah_qvar_mode_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); - if (ret == 0) - { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); - } + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); if (ret == 0) { @@ -7828,9 +8406,11 @@ int32_t lsm6dsv16bx_ah_qvar_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); - if (ret == 0) + ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret != 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1); + return ret; } val->ah_qvar1_en = ctrl7.ah_qvar1_en; @@ -7879,6 +8459,11 @@ int32_t lsm6dsv16bx_ah_qvar_zin_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl7.ah_qvar_c_zin) { case LSM6DSV16BX_2400MOhm: @@ -7944,6 +8529,11 @@ int32_t lsm6dsv16bx_fsm_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t * int32_t ret; ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_QVAR_SENSITIVITY_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -8002,6 +8592,11 @@ int32_t lsm6dsv16bx_i3c_reset_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + switch (pin_ctrl.ibhr_por_en) { case LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST: @@ -8069,6 +8664,11 @@ int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *v int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.tdm_wclk_pu_dis; return ret; @@ -8111,6 +8711,11 @@ int32_t lsm6dsv16bx_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.tdm_out_pu_en; return ret; @@ -8156,6 +8761,11 @@ int32_t lsm6dsv16bx_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch ((tdm_cfg0.tdm_wclk_bclk_sel << 2) + tdm_cfg0.tdm_wclk) { case LSM6DSV16BX_WCLK_16kHZ_BCLK_2048kHz: @@ -8210,6 +8820,11 @@ int32_t lsm6dsv16bx_tdm_slot_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (tdm_cfg0.tdm_slot_sel) { case LSM6DSV16BX_SLOT_012: @@ -8266,6 +8881,11 @@ int32_t lsm6dsv16bx_tdm_bclk_edge_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (tdm_cfg0.tdm_bclk_edge_sel) { case LSM6DSV16BX_BCLK_RISING: @@ -8320,6 +8940,11 @@ int32_t lsm6dsv16bx_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tdm_cfg0.tdm_delayed_cfg; return ret; @@ -8365,6 +8990,11 @@ int32_t lsm6dsv16bx_tdm_axis_order_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + if (ret != 0) + { + return ret; + } + switch (tdm_cfg1.tdm_axes_ord_sel) { case LSM6DSV16BX_TDM_ORDER_ZYX: @@ -8425,6 +9055,11 @@ int32_t lsm6dsv16bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + if (ret != 0) + { + return ret; + } + switch (tdm_cfg2.tdm_fs_xl) { case LSM6DSV16BX_TDM_2g: @@ -8456,4 +9091,3 @@ int32_t lsm6dsv16bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.h b/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.h index 4f4fcfc..f2fd68a 100644 --- a/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.h +++ b/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -3739,5 +3741,3 @@ int32_t lsm6dsv16bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, #endif #endif /*LSM6DSV16BX_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.c b/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.c index 83d6cf9..5d9687f 100644 --- a/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.c +++ b/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.c @@ -6,17 +6,17 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ +#include #include "lsm6dsv16x_reg.h" /** @@ -439,9 +439,9 @@ int32_t lsm6dsv16x_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val) return ret; } - ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; - ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; - func_cfg_access.sw_por = (uint8_t)val & 0x01U; + ctrl3.boot = (val == LSM6DSV16X_RESTORE_CAL_PARAM) ? 1 : 0; + ctrl3.sw_reset = (val == LSM6DSV16X_RESTORE_CTRL_REGS) ? 1 : 0; + func_cfg_access.sw_por = (val == LSM6DSV16X_GLOBAL_RST) ? 1 : 0; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1); ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); @@ -1957,12 +1957,6 @@ int32_t lsm6dsv16x_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsv16x_md1_cfg_t md1_cfg; int32_t ret; - /* not available on INT1 */ - if (val->drdy_temp == 1) - { - return -1; - } - ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); if (ret != 0) { @@ -2017,6 +2011,8 @@ int32_t lsm6dsv16x_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsv16x_md1_cfg_t md1_cfg; int32_t ret; + memset(val, 0x0, sizeof(lsm6dsv16x_pin_int_route_t)); + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); if (ret != 0) { @@ -2065,6 +2061,8 @@ int32_t lsm6dsv16x_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsv16x_md2_cfg_t md2_cfg; int32_t ret; + memset(val, 0x0, sizeof(lsm6dsv16x_pin_int_route_t)); + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); if (ret != 0) { @@ -3820,7 +3818,7 @@ int32_t lsm6dsv16x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_event_t val) { lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3828,7 +3826,7 @@ int32_t lsm6dsv16x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) { - fifo_ctrl2.stop_on_wtm = val; + fifo_ctrl2.stop_on_wtm = (val == LSM6DSV16X_FIFO_EV_WTM) ? 1 : 0; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); } @@ -3843,13 +3841,16 @@ int32_t lsm6dsv16x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_event_t *val) { lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - *val = fifo_ctrl2.stop_on_wtm; + if (ret == 0) + { + *val = (fifo_ctrl2.stop_on_wtm == 1) ? LSM6DSV16X_FIFO_EV_WTM : LSM6DSV16X_FIFO_EV_FULL; + } return ret; } diff --git a/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.h b/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.h index 7cf5b7a..6a555ab 100644 --- a/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.h +++ b/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -3916,10 +3918,11 @@ int32_t lsm6dsv16x_xl_offset_mg_get(const stmdev_ctx_t *ctx, typedef enum { - LSM6DSV16X_READY = 0x0, - LSM6DSV16X_GLOBAL_RST = 0x1, - LSM6DSV16X_RESTORE_CAL_PARAM = 0x2, - LSM6DSV16X_RESTORE_CTRL_REGS = 0x4, + LSM6DSV16X_READY = 0x0, /* No active reset in progress */ + LSM6DSV16X_GLOBAL_RST = 0x1, /* Complete reset: boot, software reset, + embedded functions, and internal filters */ + LSM6DSV16X_RESTORE_CAL_PARAM = 0x2, /* Reload trimming parameters */ + LSM6DSV16X_RESTORE_CTRL_REGS = 0x4, /* Reset control registers to default values */ } lsm6dsv16x_reset_t; int32_t lsm6dsv16x_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val); int32_t lsm6dsv16x_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16x_reset_t *val); @@ -4367,8 +4370,14 @@ int32_t lsm6dsv16x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, int32_t lsm6dsv16x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); +typedef enum +{ + LSM6DSV16X_FIFO_EV_WTM = 0x0, + LSM6DSV16X_FIFO_EV_FULL = 0x1, +} lsm6dsv16x_fifo_event_t; + +int32_t lsm6dsv16x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_event_t val); +int32_t lsm6dsv16x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_event_t *val); typedef enum { @@ -5339,5 +5348,3 @@ int32_t lsm6dsv16x_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, #endif #endif /*LSM6DSV16X_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv320x_STdC/driver/lsm6dsv320x_reg.c b/sensor/stmemsc/lsm6dsv320x_STdC/driver/lsm6dsv320x_reg.c index c04648f..9981eb4 100644 --- a/sensor/stmemsc/lsm6dsv320x_STdC/driver/lsm6dsv320x_reg.c +++ b/sensor/stmemsc/lsm6dsv320x_STdC/driver/lsm6dsv320x_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2025 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -169,6 +168,10 @@ float_t lsm6dsv320x_from_fs320_to_mg(int16_t lsb) return ((float_t)lsb) * 10.417f; } +float_t lsm6dsv320x_from_fs125_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 4.375f; +} float_t lsm6dsv320x_from_fs250_to_mdps(int16_t lsb) { return ((float_t)lsb) * 8.750f; @@ -225,6 +228,19 @@ float_t lsm6dsv320x_from_quaternion_lsb_to_float(uint16_t lsb) return npy_half_to_float(lsb); } +static uint32_t npy_halfbits_to_floatbits(uint16_t h); +/** + * @brief Convert from 16-bit to 32-bit float number + * + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +uint32_t lsm6dsv320x_from_f16_to_f32(uint16_t val) +{ + return npy_halfbits_to_floatbits(val); +} + /** * @} * @@ -275,6 +291,10 @@ int32_t lsm6dsv320x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } *val = ctrl9.usr_off_on_out; return ret; @@ -518,9 +538,9 @@ int32_t lsm6dsv320x_reset_set(const stmdev_ctx_t *ctx, lsm6dsv320x_reset_t val) return ret; } - ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; - ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; - func_cfg_access.sw_por = (uint8_t)val & 0x01U; + ctrl3.boot = (val == LSM6DSV320X_RESTORE_CAL_PARAM) ? 1 : 0; + ctrl3.sw_reset = (val == LSM6DSV320X_RESTORE_CTRL_REGS) ? 1 : 0; + func_cfg_access.sw_por = (val == LSM6DSV320X_GLOBAL_RST) ? 1 : 0; ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_CTRL3, (uint8_t *)&ctrl3, 1); ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); @@ -692,6 +712,10 @@ int32_t lsm6dsv320x_xl_data_rate_set(const stmdev_ctx_t *ctx, if (sel != 0U) { ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } haodr.haodr_sel = sel; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_HAODR_CFG, (uint8_t *)&haodr, 1); } @@ -749,7 +773,10 @@ int32_t lsm6dsv320x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_15Hz625; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_13Hz; + *val = LSM6DSV320X_ODR_HA02_AT_12Hz5; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_13Hz; break; } break; @@ -765,7 +792,10 @@ int32_t lsm6dsv320x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_31Hz25; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_26Hz; + *val = LSM6DSV320X_ODR_HA02_AT_25Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_26Hz; break; } break; @@ -781,7 +811,10 @@ int32_t lsm6dsv320x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_62Hz5; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_52Hz; + *val = LSM6DSV320X_ODR_HA02_AT_50Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_52Hz; break; } break; @@ -797,7 +830,10 @@ int32_t lsm6dsv320x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_125Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_104Hz; + *val = LSM6DSV320X_ODR_HA02_AT_100Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_104Hz; break; } break; @@ -813,7 +849,10 @@ int32_t lsm6dsv320x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_250Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_208Hz; + *val = LSM6DSV320X_ODR_HA02_AT_200Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_208Hz; break; } break; @@ -829,7 +868,10 @@ int32_t lsm6dsv320x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_500Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_417Hz; + *val = LSM6DSV320X_ODR_HA02_AT_400Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_417Hz; break; } break; @@ -845,7 +887,10 @@ int32_t lsm6dsv320x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_1000Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_833Hz; + *val = LSM6DSV320X_ODR_HA02_AT_800Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_833Hz; break; } break; @@ -861,7 +906,10 @@ int32_t lsm6dsv320x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_2000Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_1667Hz; + *val = LSM6DSV320X_ODR_HA02_AT_1600Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_1667Hz; break; } break; @@ -877,7 +925,10 @@ int32_t lsm6dsv320x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_4000Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_3333Hz; + *val = LSM6DSV320X_ODR_HA02_AT_3200Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_3333Hz; break; } break; @@ -893,7 +944,10 @@ int32_t lsm6dsv320x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_8000Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_6667Hz; + *val = LSM6DSV320X_ODR_HA02_AT_6400Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_6667Hz; break; } break; @@ -922,6 +976,11 @@ int32_t lsm6dsv320x_hg_xl_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL1_XL_HG, (uint8_t *)&ctrl1_xl_hg, 1); + if (ret != 0) + { + return ret; + } + ctrl1_xl_hg.odr_xl_hg = (uint8_t)val & 0x07U; ctrl1_xl_hg.xl_hg_regout_en = reg_out_en & 0x1U; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_CTRL1_XL_HG, (uint8_t *)&ctrl1_xl_hg, 1); @@ -945,6 +1004,10 @@ int32_t lsm6dsv320x_hg_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL1_XL_HG, (uint8_t *)&ctrl1_xl_hg, 1); + if (ret != 0) + { + return ret; + } *reg_out_en = ctrl1_xl_hg.xl_hg_regout_en; @@ -1080,6 +1143,10 @@ int32_t lsm6dsv320x_gy_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } ctrl2.odr_g = (uint8_t)val & 0x0Fu; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_CTRL2, (uint8_t *)&ctrl2, 1); if (ret != 0) @@ -1091,6 +1158,10 @@ int32_t lsm6dsv320x_gy_data_rate_set(const stmdev_ctx_t *ctx, if (sel != 0U) { ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } haodr.haodr_sel = sel; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_HAODR_CFG, (uint8_t *)&haodr, 1); } @@ -1148,7 +1219,10 @@ int32_t lsm6dsv320x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_15Hz625; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_13Hz; + *val = LSM6DSV320X_ODR_HA02_AT_12Hz5; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_13Hz; break; } break; @@ -1164,7 +1238,10 @@ int32_t lsm6dsv320x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_31Hz25; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_26Hz; + *val = LSM6DSV320X_ODR_HA02_AT_25Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_26Hz; break; } break; @@ -1180,7 +1257,10 @@ int32_t lsm6dsv320x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_62Hz5; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_52Hz; + *val = LSM6DSV320X_ODR_HA02_AT_50Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_52Hz; break; } break; @@ -1196,7 +1276,10 @@ int32_t lsm6dsv320x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_125Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_104Hz; + *val = LSM6DSV320X_ODR_HA02_AT_100Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_104Hz; break; } break; @@ -1212,7 +1295,10 @@ int32_t lsm6dsv320x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_250Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_208Hz; + *val = LSM6DSV320X_ODR_HA02_AT_200Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_208Hz; break; } break; @@ -1228,7 +1314,10 @@ int32_t lsm6dsv320x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_500Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_417Hz; + *val = LSM6DSV320X_ODR_HA02_AT_400Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_417Hz; break; } break; @@ -1244,7 +1333,10 @@ int32_t lsm6dsv320x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_1000Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_833Hz; + *val = LSM6DSV320X_ODR_HA02_AT_800Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_833Hz; break; } break; @@ -1260,7 +1352,10 @@ int32_t lsm6dsv320x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_2000Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_1667Hz; + *val = LSM6DSV320X_ODR_HA02_AT_1600Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_1667Hz; break; } break; @@ -1276,7 +1371,10 @@ int32_t lsm6dsv320x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_4000Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_3333Hz; + *val = LSM6DSV320X_ODR_HA02_AT_3200Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_3333Hz; break; } break; @@ -1292,7 +1390,10 @@ int32_t lsm6dsv320x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV320X_ODR_HA01_AT_8000Hz; break; case 2: - *val = LSM6DSV320X_ODR_HA02_AT_6667Hz; + *val = LSM6DSV320X_ODR_HA02_AT_6400Hz; + break; + case 3: + *val = LSM6DSV320X_ODR_HA03_AT_6667Hz; break; } break; @@ -1302,6 +1403,7 @@ int32_t lsm6dsv320x_gy_data_rate_get(const stmdev_ctx_t *ctx, break; } + return ret; } @@ -1414,6 +1516,11 @@ int32_t lsm6dsv320x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.if_inc; return ret; @@ -1457,6 +1564,11 @@ int32_t lsm6dsv320x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.bdu; return ret; @@ -1505,6 +1617,10 @@ int32_t lsm6dsv320x_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + if (ret != 0) + { + return ret; + } *val = odr_trig.odr_trig_nodr; return ret; @@ -1550,6 +1666,10 @@ int32_t lsm6dsv320x_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4.drdy_pulsed) { @@ -1585,14 +1705,20 @@ int32_t lsm6dsv320x_interrupt_enable_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + if (ret != 0) + { + return ret; + } + func.interrupts_enable = val.enable; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + + ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_TAP_CFG0, (uint8_t *)&cfg, 1); if (ret != 0) { return ret; } - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_TAP_CFG0, (uint8_t *)&cfg, 1); cfg.lir = val.lir; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_TAP_CFG0, (uint8_t *)&cfg, 1); @@ -2425,25 +2551,23 @@ int32_t lsm6dsv320x_hg_event_get(const stmdev_ctx_t *ctx, lsm6dsv320x_hg_event_t val->hg_event = int_src.hg_ia; /* no High-g event */ - if (int_src.hg_ia == 0) + if (int_src.hg_ia != 0) { - return 0; - } + ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_HG_WAKE_UP_SRC, (uint8_t *)&wup_src, 1); + if (ret != 0) + { + return ret; + } - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_HG_WAKE_UP_SRC, (uint8_t *)&wup_src, 1); - if (ret != 0) - { - return ret; + val->hg_wakeup_z = wup_src.hg_z_wu; + val->hg_wakeup_y = wup_src.hg_y_wu; + val->hg_wakeup_x = wup_src.hg_x_wu; + val->hg_wakeup = wup_src.hg_wu_ia; + val->hg_wakeup_chg = wup_src.hg_wu_change_ia; + val->hg_shock = wup_src.hg_shock_state; + val->hg_shock_change = wup_src.hg_shock_change_ia; } - val->hg_wakeup_z = wup_src.hg_z_wu; - val->hg_wakeup_y = wup_src.hg_y_wu; - val->hg_wakeup_x = wup_src.hg_x_wu; - val->hg_wakeup = wup_src.hg_wu_ia; - val->hg_wakeup_chg = wup_src.hg_wu_change_ia; - val->hg_shock = wup_src.hg_shock_state; - val->hg_shock_change = wup_src.hg_shock_change_ia; - return ret; } @@ -2516,10 +2640,6 @@ int32_t lsm6dsv320x_pin_int1_route_set(const stmdev_ctx_t *ctx, md1_cfg.int1_sleep_change = val->sleep_change; ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret != 0) - { - return ret; - } return ret; } @@ -2609,6 +2729,10 @@ int32_t lsm6dsv320x_pin_int2_route_set(const stmdev_ctx_t *ctx, } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } ctrl4.int2_drdy_temp = val->drdy_temp; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_CTRL4, (uint8_t *)&ctrl4, 1); if (ret != 0) @@ -2631,10 +2755,6 @@ int32_t lsm6dsv320x_pin_int2_route_set(const stmdev_ctx_t *ctx, md2_cfg.int2_sleep_change = val->sleep_change; ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret != 0) - { - return ret; - } return ret; } @@ -2900,42 +3020,48 @@ int32_t lsm6dsv320x_pin_int1_route_embedded_set(const stmdev_ctx_t *ctx, lsm6dsv320x_mlc_int1_t mlc_int1; int32_t ret; - /* Embedded Functions */ - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MD1_CFG, (uint8_t *)&md1_cfg, 1); if (ret != 0) { return ret; } - emb_func_int1.int1_step_detector = val->step_detector; - emb_func_int1.int1_tilt = val->tilt; - emb_func_int1.int1_sig_mot = val->sig_mot; + md1_cfg.int1_emb_func = 1; - ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_MD1_CFG, (uint8_t *)&md1_cfg, 1); if (ret != 0) { return ret; } - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + /* Embedded Functions */ + ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } - md1_cfg.int1_emb_func = 1; + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + if (ret != 0) + { + goto exit; + } - ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + emb_func_int1.int1_step_detector = val->step_detector; + emb_func_int1.int1_tilt = val->tilt; + emb_func_int1.int1_sig_mot = val->sig_mot; + + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); if (ret != 0) { - return ret; + goto exit; } /* FSM */ - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_INT1, (uint8_t *)&fsm_int1, 1); + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_INT1, (uint8_t *)&fsm_int1, 1); if (ret != 0) { - return ret; + goto exit; } fsm_int1.int1_fsm1 = val->fsm1; @@ -2947,17 +3073,17 @@ int32_t lsm6dsv320x_pin_int1_route_embedded_set(const stmdev_ctx_t *ctx, fsm_int1.int1_fsm7 = val->fsm7; fsm_int1.int1_fsm8 = val->fsm8; - ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FSM_INT1, (uint8_t *)&fsm_int1, 1); + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FSM_INT1, (uint8_t *)&fsm_int1, 1); if (ret != 0) { - return ret; + goto exit; } /* MLC */ - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MLC_INT1, (uint8_t *)&mlc_int1, 1); + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MLC_INT1, (uint8_t *)&mlc_int1, 1); if (ret != 0) { - return ret; + goto exit; } mlc_int1.int1_mlc1 = val->mlc1; @@ -2969,12 +3095,15 @@ int32_t lsm6dsv320x_pin_int1_route_embedded_set(const stmdev_ctx_t *ctx, mlc_int1.int1_mlc7 = val->mlc7; mlc_int1.int1_mlc8 = val->mlc8; - ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_MLC_INT1, (uint8_t *)&mlc_int1, 1); + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_MLC_INT1, (uint8_t *)&mlc_int1, 1); if (ret != 0) { - return ret; + goto exit; } +exit: + ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); + return ret; } @@ -2996,10 +3125,16 @@ int32_t lsm6dsv320x_pin_int1_route_embedded_get(const stmdev_ctx_t *ctx, int32_t ret; /* Embedded Functions */ - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; + } + + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + if (ret != 0) + { + goto exit; } val->step_detector = emb_func_int1.int1_step_detector; @@ -3007,10 +3142,10 @@ int32_t lsm6dsv320x_pin_int1_route_embedded_get(const stmdev_ctx_t *ctx, val->tilt = emb_func_int1.int1_tilt; /* FSM */ - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_INT1, (uint8_t *)&fsm_int1, 1); + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_INT1, (uint8_t *)&fsm_int1, 1); if (ret != 0) { - return ret; + goto exit; } val->fsm1 = fsm_int1.int1_fsm1; @@ -3023,10 +3158,10 @@ int32_t lsm6dsv320x_pin_int1_route_embedded_get(const stmdev_ctx_t *ctx, val->fsm8 = fsm_int1.int1_fsm8; /* MLC */ - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MLC_INT1, (uint8_t *)&mlc_int1, 1); + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MLC_INT1, (uint8_t *)&mlc_int1, 1); if (ret != 0) { - return ret; + goto exit; } val->mlc1 = mlc_int1.int1_mlc1; @@ -3038,6 +3173,9 @@ int32_t lsm6dsv320x_pin_int1_route_embedded_get(const stmdev_ctx_t *ctx, val->mlc7 = mlc_int1.int1_mlc7; val->mlc8 = mlc_int1.int1_mlc8; +exit: + ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); + return ret; } @@ -3059,42 +3197,48 @@ int32_t lsm6dsv320x_pin_int2_route_embedded_set(const stmdev_ctx_t *ctx, lsm6dsv320x_mlc_int2_t mlc_int2; int32_t ret; - /* Embedded Functions */ - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MD2_CFG, (uint8_t *)&md2_cfg, 1); if (ret != 0) { return ret; } - emb_func_int2.int2_step_detector = val->step_detector; - emb_func_int2.int2_tilt = val->tilt; - emb_func_int2.int2_sig_mot = val->sig_mot; + md2_cfg.int2_emb_func = 1; - ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_MD2_CFG, (uint8_t *)&md2_cfg, 1); if (ret != 0) { return ret; } - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + /* Embedded Functions */ + ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } - md2_cfg.int2_emb_func = 1; + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + if (ret != 0) + { + goto exit; + } - ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + emb_func_int2.int2_step_detector = val->step_detector; + emb_func_int2.int2_tilt = val->tilt; + emb_func_int2.int2_sig_mot = val->sig_mot; + + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); if (ret != 0) { - return ret; + goto exit; } /* FSM */ - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_INT2, (uint8_t *)&fsm_int2, 1); if (ret != 0) { - return ret; + goto exit; } fsm_int2.int2_fsm1 = val->fsm1; @@ -3106,17 +3250,17 @@ int32_t lsm6dsv320x_pin_int2_route_embedded_set(const stmdev_ctx_t *ctx, fsm_int2.int2_fsm7 = val->fsm7; fsm_int2.int2_fsm8 = val->fsm8; - ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FSM_INT2, (uint8_t *)&fsm_int2, 1); if (ret != 0) { - return ret; + goto exit; } /* MLC */ - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MLC_INT2, (uint8_t *)&mlc_int2, 1); + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MLC_INT2, (uint8_t *)&mlc_int2, 1); if (ret != 0) { - return ret; + goto exit; } mlc_int2.int2_mlc1 = val->mlc1; @@ -3128,12 +3272,15 @@ int32_t lsm6dsv320x_pin_int2_route_embedded_set(const stmdev_ctx_t *ctx, mlc_int2.int2_mlc7 = val->mlc7; mlc_int2.int2_mlc8 = val->mlc8; - ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_MLC_INT2, (uint8_t *)&mlc_int2, 1); + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_MLC_INT2, (uint8_t *)&mlc_int2, 1); if (ret != 0) { - return ret; + goto exit; } +exit: + ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); + return ret; } @@ -3155,10 +3302,16 @@ int32_t lsm6dsv320x_pin_int2_route_embedded_get(const stmdev_ctx_t *ctx, int32_t ret; /* Embedded Functions */ - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; + } + + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + if (ret != 0) + { + goto exit; } val->step_detector = emb_func_int2.int2_step_detector; @@ -3166,10 +3319,10 @@ int32_t lsm6dsv320x_pin_int2_route_embedded_get(const stmdev_ctx_t *ctx, val->tilt = emb_func_int2.int2_tilt; /* FSM */ - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_INT2, (uint8_t *)&fsm_int2, 1); if (ret != 0) { - return ret; + goto exit; } val->fsm1 = fsm_int2.int2_fsm1; @@ -3182,10 +3335,10 @@ int32_t lsm6dsv320x_pin_int2_route_embedded_get(const stmdev_ctx_t *ctx, val->fsm8 = fsm_int2.int2_fsm8; /* MLC */ - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MLC_INT2, (uint8_t *)&mlc_int2, 1); + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MLC_INT2, (uint8_t *)&mlc_int2, 1); if (ret != 0) { - return ret; + goto exit; } val->mlc1 = mlc_int2.int2_mlc1; @@ -3197,6 +3350,9 @@ int32_t lsm6dsv320x_pin_int2_route_embedded_get(const stmdev_ctx_t *ctx, val->mlc7 = mlc_int2.int2_mlc7; val->mlc8 = mlc_int2.int2_mlc8; +exit: + ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); + return ret; } @@ -3234,6 +3390,11 @@ int32_t lsm6dsv320x_all_sources_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); if (ret != 0) @@ -3270,6 +3431,11 @@ int32_t lsm6dsv320x_all_sources_get(const stmdev_ctx_t *ctx, val->timestamp = status_reg.timestamp_endcount; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); if (ret != 0) @@ -3404,7 +3570,16 @@ int32_t lsm6dsv320x_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; - ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_INT_ACK_MASK, &val, 1); + ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_INT_ACK_MASK, &val, 1); + +exit: + ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; } @@ -3421,7 +3596,16 @@ int32_t lsm6dsv320x_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_INT_ACK_MASK, val, 1); + ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_INT_ACK_MASK, val, 1); + +exit: + ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; } @@ -3761,6 +3945,11 @@ int32_t lsm6dsv320x_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + if (ret != 0) + { + return ret; + } + *val = (int8_t)internal_freq.freq_fine; return ret; @@ -3787,6 +3976,11 @@ int32_t lsm6dsv320x_disable_embedded_function_set(const stmdev_ctx_t *ctx, uint8 int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } + emb_func_cfg.emb_func_disable = val & 0x1U; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); @@ -3807,6 +4001,11 @@ int32_t lsm6dsv320x_disable_embedded_function_get(const stmdev_ctx_t *ctx, uint8 int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = emb_func_cfg.emb_func_disable; return ret; @@ -3828,16 +4027,21 @@ int32_t lsm6dsv320x_emb_func_conv_set(const stmdev_ctx_t *ctx, lsm6dsv320x_emb_f ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_SENSOR_CONV_EN, (uint8_t *)&conv_reg, 1); + if (ret != 0) + { + goto exit; + } conv_reg.xl_hg_conv_en = val.xl_hg_conv_en; conv_reg.gyro_conv_en = val.gyro_conv_en; conv_reg.temp_conv_en = val.temp_conv_en; conv_reg.ext_sensor_conv_en = val.ext_sensor_conv_en; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_SENSOR_CONV_EN, (uint8_t *)&conv_reg, 1); +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -3859,15 +4063,20 @@ int32_t lsm6dsv320x_emb_func_conv_get(const stmdev_ctx_t *ctx, lsm6dsv320x_emb_f ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_SENSOR_CONV_EN, (uint8_t *)&conv_reg, 1); + if (ret != 0) + { + goto exit; + } val->xl_hg_conv_en = conv_reg.xl_hg_conv_en; val->gyro_conv_en = conv_reg.gyro_conv_en; val->temp_conv_en = conv_reg.temp_conv_en; val->ext_sensor_conv_en = conv_reg.ext_sensor_conv_en; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -3898,21 +4107,25 @@ int32_t lsm6dsv320x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } /* set page write */ ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_PAGE_RW, (uint8_t *)&page_rw, 1); - page_rw.page_read = PROPERTY_DISABLE; - page_rw.page_write = PROPERTY_ENABLE; - ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_PAGE_RW, (uint8_t *)&page_rw, 1); if (ret != 0) { goto exit; } + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_PAGE_RW, (uint8_t *)&page_rw, 1); /* select page */ ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -3970,6 +4183,10 @@ int32_t lsm6dsv320x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, /* unset page write */ ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -4010,6 +4227,10 @@ int32_t lsm6dsv320x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_ /* set page write */ ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -4020,6 +4241,10 @@ int32_t lsm6dsv320x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_ /* select page */ ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -4077,6 +4302,10 @@ int32_t lsm6dsv320x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_ /* unset page write */ ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -4335,6 +4564,11 @@ int32_t lsm6dsv320x_eis_gy_on_if2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl_eis.g_eis_on_g_ois_out_reg; return ret; @@ -4457,6 +4691,11 @@ int32_t lsm6dsv320x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl1.wtm; return ret; @@ -4569,6 +4808,11 @@ int32_t lsm6dsv320x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odr_chg_en; return ret; @@ -4591,6 +4835,10 @@ int32_t lsm6dsv320x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } fifo_ctrl2.fifo_compr_rt_en = val; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); if (ret != 0) @@ -4601,12 +4849,16 @@ int32_t lsm6dsv320x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; + } + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + if (ret != 0) + { + goto exit; } - - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); emb_func_en_b.fifo_compr_en = val; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -4627,6 +4879,10 @@ int32_t lsm6dsv320x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } *val = fifo_ctrl2.fifo_compr_rt_en; @@ -4641,7 +4897,7 @@ int32_t lsm6dsv320x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv320x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv320x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lsm6dsv320x_fifo_event_t val) { lsm6dsv320x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -4649,7 +4905,7 @@ int32_t lsm6dsv320x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) { - fifo_ctrl2.stop_on_wtm = val; + fifo_ctrl2.stop_on_wtm = (val == LSM6DSV320X_FIFO_EV_WTM) ? 1 : 0; ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); } @@ -4664,13 +4920,18 @@ int32_t lsm6dsv320x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv320x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv320x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lsm6dsv320x_fifo_event_t *val) { lsm6dsv320x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - *val = fifo_ctrl2.stop_on_wtm; + if (ret != 0) + { + return ret; + } + + *val = (fifo_ctrl2.stop_on_wtm == 1) ? LSM6DSV320X_FIFO_EV_WTM : LSM6DSV320X_FIFO_EV_FULL; return ret; } @@ -4923,6 +5184,11 @@ int32_t lsm6dsv320x_fifo_hg_xl_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_COUNTER_BDR_REG1, (uint8_t *)&cbdr_reg, 1); + if (ret != 0) + { + return ret; + } + *val = cbdr_reg.xl_hg_batch_en; return ret; @@ -5044,6 +5310,11 @@ int32_t lsm6dsv320x_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl4.g_eis_fifo_en; return ret; @@ -5199,12 +5470,20 @@ int32_t lsm6dsv320x_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, int32_t lsm6dsv320x_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { - uint8_t buff[2]; + lsm6dsv320x_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsv320x_counter_bdr_reg2_t counter_bdr_reg2; int32_t ret; - buff[1] = (uint8_t)(val / 256U); - buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_COUNTER_BDR_REG1, (uint8_t *)&buff[0], 2); + ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU; + counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U; + ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); + } + return ret; } @@ -5229,8 +5508,8 @@ int32_t lsm6dsv320x_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, return ret; } - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + *val = (uint16_t)buff[0] & 0x3U; + *val = (*val * 256U) + (uint16_t)buff[1]; return ret; } @@ -5370,11 +5649,11 @@ int32_t lsm6dsv320x_fifo_out_raw_get(const stmdev_ctx_t *ctx, break; case 3: - val->tag = LSM6DSV320X_TIMESTAMP_TAG; + val->tag = LSM6DSV320X_TEMPERATURE_TAG; break; case 4: - val->tag = LSM6DSV320X_TEMPERATURE_TAG; + val->tag = LSM6DSV320X_TIMESTAMP_TAG; break; case 5: @@ -5510,14 +5789,19 @@ int32_t lsm6dsv320x_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } emb_func_fifo_en_a.step_counter_fifo_en = val; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -5539,12 +5823,17 @@ int32_t lsm6dsv320x_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_fifo_en_a.step_counter_fifo_en; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -5566,14 +5855,19 @@ int32_t lsm6dsv320x_fifo_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_b, 1); + ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret != 0) + { + goto exit; + } emb_func_fifo_en_b.fsm_fifo_en = val; - ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_b, + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -5595,12 +5889,17 @@ int32_t lsm6dsv320x_fifo_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_b, 1); + ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_fifo_en_b.fsm_fifo_en; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -5622,14 +5921,19 @@ int32_t lsm6dsv320x_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } emb_func_fifo_en_a.mlc_fifo_en = val; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -5651,12 +5955,17 @@ int32_t lsm6dsv320x_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_fifo_en_a.mlc_fifo_en; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -5678,14 +5987,19 @@ int32_t lsm6dsv320x_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret != 0) + { + goto exit; + } emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -5707,12 +6021,17 @@ int32_t lsm6dsv320x_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *va ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -5734,13 +6053,18 @@ int32_t lsm6dsv320x_fifo_sh_batch_target_set(const stmdev_ctx_t *ctx, uint8_t id ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_SENSOR_HUB_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_TGT0_CONFIG + idx * 3U, (uint8_t *)&tgt_config, 1); + if (ret != 0) + { + goto exit; + } tgt_config.batch_ext_sens_0_en = val; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_TGT0_CONFIG + idx * 3U, (uint8_t *)&tgt_config, 1); +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -5762,12 +6086,17 @@ int32_t lsm6dsv320x_fifo_sh_batch_target_get(const stmdev_ctx_t *ctx, uint8_t id ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_SENSOR_HUB_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_TGT0_CONFIG + idx * 3U, (uint8_t *)&tgt_config, 1); + if (ret != 0) + { + goto exit; + } *val = tgt_config.batch_ext_sens_0_en; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -5788,16 +6117,23 @@ int32_t lsm6dsv320x_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); - emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; - emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; - emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; - ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, - (uint8_t *)&emb_func_fifo_en_a, 1); + goto exit; } + ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } + emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; + emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; + emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, + (uint8_t *)&emb_func_fifo_en_a, 1); + +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -5818,15 +6154,21 @@ int32_t lsm6dsv320x_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + goto exit; + } - val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; - val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; - val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; + ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; } + val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; + val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; + val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -5925,6 +6267,10 @@ int32_t lsm6dsv320x_filt_settling_mask_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } ctrl4.drdy_mask = val.drdy; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_CTRL4, (uint8_t *)&ctrl4, 1); if (ret != 0) @@ -5933,6 +6279,10 @@ int32_t lsm6dsv320x_filt_settling_mask_set(const stmdev_ctx_t *ctx, } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; emb_func_cfg.emb_func_irq_mask_xl_hg_settl = val.irq_xl_hg; emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; @@ -5943,6 +6293,10 @@ int32_t lsm6dsv320x_filt_settling_mask_set(const stmdev_ctx_t *ctx, } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + if (ret != 0) + { + return ret; + } ui_int_ois.drdy_mask_ois = val.ois_drdy; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); @@ -5968,6 +6322,11 @@ int32_t lsm6dsv320x_filt_settling_mask_get(const stmdev_ctx_t *ctx, ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL4, (uint8_t *)&ctrl4, 1); ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + if (ret != 0) + { + return ret; + } + val->ois_drdy = ui_int_ois.drdy_mask_ois; val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl; val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl; @@ -6017,6 +6376,11 @@ int32_t lsm6dsv320x_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_IF2_INT_OIS, (uint8_t *)&if2_int_ois, 1); + if (ret != 0) + { + return ret; + } + val->ois_drdy = if2_int_ois.drdy_mask_ois; return ret; @@ -6146,6 +6510,11 @@ int32_t lsm6dsv320x_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7.lpf1_g_en; return ret; @@ -6274,6 +6643,11 @@ int32_t lsm6dsv320x_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.lpf2_xl_en; return ret; @@ -6315,7 +6689,12 @@ int32_t lsm6dsv320x_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) lsm6dsv320x_ctrl9_t ctrl9; int32_t ret; - ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL9, (uint8_t *)&ctrl9, 1); + ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.hp_slope_xl_en; return ret; @@ -6358,6 +6737,11 @@ int32_t lsm6dsv320x_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t * int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.xl_fastsettl_mode; return ret; @@ -6542,6 +6926,11 @@ int32_t lsm6dsv320x_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t * int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.hw_func_mask_xl_settl; return ret; @@ -6922,6 +7311,10 @@ int32_t lsm6dsv320x_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CTRL_STATUS, (uint8_t *)&ctrl_status, 1); + if (ret != 0) + { + return ret; + } *val = ctrl_status.fsm_wr_ctrl_status; @@ -6945,7 +7338,7 @@ int32_t lsm6dsv320x_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv320x_fsm_mode_t ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); @@ -6997,7 +7390,14 @@ int32_t lsm6dsv320x_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv320x_fsm_mode_t int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + if (ret != 0) + { + goto exit; + } + + ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); if (ret != 0) { @@ -7033,7 +7433,14 @@ int32_t lsm6dsv320x_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) buff[0] = (uint8_t)(val - (buff[1] * 256U)); ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2); + +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -7053,7 +7460,14 @@ int32_t lsm6dsv320x_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_LONG_COUNTER_L, &buff[0], 2); + +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); if (ret != 0) { @@ -7079,7 +7493,14 @@ int32_t lsm6dsv320x_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv320x_fsm_out_t * int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_OUTS1, (uint8_t *)val, 8); + +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -7100,12 +7521,16 @@ int32_t lsm6dsv320x_fsm_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_ODR, (uint8_t *)&fsm_odr, 1); if (ret != 0) { goto exit; } + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + if (ret != 0) + { + goto exit; + } fsm_odr.fsm_odr = (uint8_t)val & 0x07U; ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FSM_ODR, (uint8_t *)&fsm_odr, 1); @@ -7130,7 +7555,14 @@ int32_t lsm6dsv320x_fsm_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); if (ret != 0) { @@ -7434,7 +7866,14 @@ int32_t lsm6dsv320x_sflp_game_gbias_set(const stmdev_ctx_t *ctx, gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k); ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_SFLP_GBIASX_INIT_L, (uint8_t *)&gbias_hf[0], 6); + +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -7623,8 +8062,12 @@ int32_t lsm6dsv320x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_ln_pg_read(ctx, LSM6DSV320X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret != 0) + { + return ret; + } ext_cfg_a.ext_z_axis = (uint8_t)val & 0x07U; - ret += lsm6dsv320x_ln_pg_write(ctx, LSM6DSV320X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + ret = lsm6dsv320x_ln_pg_write(ctx, LSM6DSV320X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); return ret; } @@ -7855,13 +8298,18 @@ int32_t lsm6dsv320x_xl_hg_peak_tracking_set(const stmdev_ctx_t *ctx, uint8_t val ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); + if (ret != 0) + { + goto exit; + } emb_func_init_b.pt_init = val; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -7883,12 +8331,17 @@ int32_t lsm6dsv320x_xl_hg_peak_tracking_get(const stmdev_ctx_t *ctx, uint8_t *va ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_init_b.pt_init; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -8028,7 +8481,10 @@ int32_t lsm6dsv320x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t ret = lsm6dsv320x_ln_pg_read(ctx, LSM6DSV320X_EMB_ADV_PG_1 + LSM6DSV320X_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); - *val = fsm_programs.fsm_n_prog; + if (ret == 0) + { + *val = fsm_programs.fsm_n_prog; + } return ret; } @@ -8108,6 +8564,10 @@ int32_t lsm6dsv320x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); if (ret != 0) @@ -8116,6 +8576,10 @@ int32_t lsm6dsv320x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } free_fall.ff_dur = (uint8_t)val & 0x1FU; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_FREE_FALL, (uint8_t *)&free_fall, 1); @@ -8138,6 +8602,10 @@ int32_t lsm6dsv320x_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -8258,6 +8726,10 @@ int32_t lsm6dsv320x_mlc_set(const stmdev_ctx_t *ctx, lsm6dsv320x_mlc_mode_t val) int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); if (ret != 0) @@ -8307,6 +8779,10 @@ int32_t lsm6dsv320x_mlc_get(const stmdev_ctx_t *ctx, lsm6dsv320x_mlc_mode_t *val int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); if (ret != 0) @@ -8352,6 +8828,10 @@ int32_t lsm6dsv320x_mlc_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_MLC_ODR, (uint8_t *)&mlc_odr, 1); if (ret != 0) { @@ -8610,6 +9090,10 @@ int32_t lsm6dsv320x_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } *val = (int8_t)func_cfg_access.if2_reset; return ret; @@ -8652,6 +9136,10 @@ int32_t lsm6dsv320x_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t * int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } *val = pin_ctrl.ois_pu_dis; return ret; @@ -8830,6 +9318,10 @@ int32_t lsm6dsv320x_ois_on_if2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } *val = ui_ctrl1_ois.if2_spi_read_en; return ret; @@ -9144,6 +9636,11 @@ int32_t lsm6dsv320x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = tap_ths_6d.d4d_en; return ret; @@ -9314,6 +9811,11 @@ int32_t lsm6dsv320x_sh_controller_interface_pull_up_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.shub_pu_en; return ret; @@ -9333,7 +9835,12 @@ int32_t lsm6dsv320x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_SENSOR_HUB_1, val, len); +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -9354,12 +9861,16 @@ int32_t lsm6dsv320x_sh_target_connected_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_SENSOR_HUB_MEM_BANK); - ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); if (ret != 0) { goto exit; } + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } controller_config.aux_sens_on = (uint8_t)val & 0x3U; ret = lsm6dsv320x_write_reg(ctx, LSM6DSV320X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); @@ -9460,10 +9971,19 @@ int32_t lsm6dsv320x_sh_controller_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } *val = controller_config.controller_on; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -9512,10 +10032,16 @@ int32_t lsm6dsv320x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } *val = controller_config.pass_through_mode; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -9536,6 +10062,7 @@ int32_t lsm6dsv320x_sh_syncro_mode_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); if (ret != 0) { @@ -9705,9 +10232,14 @@ int32_t lsm6dsv320x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv320x_read_reg(ctx, LSM6DSV320X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } *val = controller_config.rst_controller_regs; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -9733,7 +10265,7 @@ int32_t lsm6dsv320x_sh_cfg_write(const stmdev_ctx_t *ctx, ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_SENSOR_HUB_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } reg.target0_add = val->tgt0_add; @@ -9971,6 +10503,11 @@ int32_t lsm6dsv320x_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.sdo_pu_en; return ret; @@ -10013,6 +10550,11 @@ int32_t lsm6dsv320x_pad_strength_get(const stmdev_ctx_t *ctx, lsm6dsv320x_pad_st int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + switch (pin_ctrl.io_pad_strength) { case 0: @@ -10191,6 +10733,11 @@ int32_t lsm6dsv320x_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.sda_pu_en; return ret; @@ -10286,13 +10833,18 @@ int32_t lsm6dsv320x_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret != 0) + { + goto exit; + } emb_func_en_a.sign_motion_en = val; ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -10314,12 +10866,17 @@ int32_t lsm6dsv320x_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_en_a.sign_motion_en; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -10356,7 +10913,7 @@ int32_t lsm6dsv320x_stpcnt_mode_set(const stmdev_ctx_t *ctx, ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); @@ -10383,6 +10940,10 @@ int32_t lsm6dsv320x_stpcnt_mode_set(const stmdev_ctx_t *ctx, { ret = lsm6dsv320x_ln_pg_read(ctx, LSM6DSV320X_EMB_ADV_PG_1 + LSM6DSV320X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + if (ret != 0) + { + return ret; + } pedo_cmd_reg.fp_rejection_en = val.false_step_rej; ret += lsm6dsv320x_ln_pg_write(ctx, LSM6DSV320X_EMB_ADV_PG_1 + LSM6DSV320X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); @@ -10470,7 +11031,7 @@ int32_t lsm6dsv320x_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); @@ -10504,12 +11065,17 @@ int32_t lsm6dsv320x_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_src.pedo_rst_step; +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -10555,6 +11121,10 @@ int32_t lsm6dsv320x_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv320x_ln_pg_read(ctx, LSM6DSV320X_EMB_ADV_PG_1 + LSM6DSV320X_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + if (ret != 0) + { + return ret; + } *val = pedo_deb_steps_conf.deb_step; return ret; @@ -10635,7 +11205,7 @@ int32_t lsm6dsv320x_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); @@ -10670,12 +11240,50 @@ int32_t lsm6dsv320x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_en_a.sflp_game_en; +exit: + ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset SFLP Game Rotation Vector logic (6x). + * + * @param ctx read / write interface definitions + * @param val 1: reset, 0: stop reset procedure + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv320x_sflp_game_rotation_reset(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv320x_emb_func_init_a_t emb_func_init_a; + int32_t ret; + + ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_EMB_FUNC_INIT_A, (uint8_t *)&emb_func_init_a, 1); + if (ret != 0) + { + goto exit; + } + emb_func_init_a.sflp_game_init = val; + ret += lsm6dsv320x_write_reg(ctx, LSM6DSV320X_EMB_FUNC_INIT_A, (uint8_t *)&emb_func_init_a, 1); + +exit: ret += lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_MAIN_MEM_BANK); return ret; @@ -10698,7 +11306,7 @@ int32_t lsm6dsv320x_sflp_data_rate_set(const stmdev_ctx_t *ctx, ret = lsm6dsv320x_mem_bank_set(ctx, LSM6DSV320X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); @@ -11240,6 +11848,11 @@ int32_t lsm6dsv320x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv320x_read_reg(ctx, LSM6DSV320X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + *val = functions_enable.timestamp_en; return ret; diff --git a/sensor/stmemsc/lsm6dsv320x_STdC/driver/lsm6dsv320x_reg.h b/sensor/stmemsc/lsm6dsv320x_STdC/driver/lsm6dsv320x_reg.h index a057cfd..a8a353d 100644 --- a/sensor/stmemsc/lsm6dsv320x_STdC/driver/lsm6dsv320x_reg.h +++ b/sensor/stmemsc/lsm6dsv320x_STdC/driver/lsm6dsv320x_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2025 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -3038,7 +3040,7 @@ typedef struct #endif /* DRV_BYTE_ORDER */ } lsm6dsv320x_emb_func_init_b_t; -#define LSM6DSV320X_EMB_FUNC_SENSOR_CONV_EN 0x67U +#define LSM6DSV320X_EMB_FUNC_SENSOR_CONV_EN 0x6EU typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN @@ -4325,8 +4327,9 @@ float_t lsm6dsv320x_from_fs128_to_mg(int16_t lsb); float_t lsm6dsv320x_from_fs256_to_mg(int16_t lsb); float_t lsm6dsv320x_from_fs320_to_mg(int16_t lsb); -float_t lsm6dsv320x_from_fs500_to_mdps(int16_t lsb); +float_t lsm6dsv320x_from_fs125_to_mdps(int16_t lsb); float_t lsm6dsv320x_from_fs250_to_mdps(int16_t lsb); +float_t lsm6dsv320x_from_fs500_to_mdps(int16_t lsb); float_t lsm6dsv320x_from_fs1000_to_mdps(int16_t lsb); float_t lsm6dsv320x_from_fs2000_to_mdps(int16_t lsb); float_t lsm6dsv320x_from_fs4000_to_mdps(int16_t lsb); @@ -4341,6 +4344,8 @@ float_t lsm6dsv320x_from_gbias_lsb_to_mdps(int16_t lsb); float_t lsm6dsv320x_from_gravity_lsb_to_mg(int16_t lsb); float_t lsm6dsv320x_from_quaternion_lsb_to_float(uint16_t lsb); +uint32_t lsm6dsv320x_from_f16_to_f32(uint16_t val); + int32_t lsm6dsv320x_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t lsm6dsv320x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); @@ -4406,16 +4411,26 @@ typedef enum LSM6DSV320X_ODR_HA01_AT_2000Hz = 0x1A, LSM6DSV320X_ODR_HA01_AT_4000Hz = 0x1B, LSM6DSV320X_ODR_HA01_AT_8000Hz = 0x1C, - LSM6DSV320X_ODR_HA02_AT_13Hz = 0x23, - LSM6DSV320X_ODR_HA02_AT_26Hz = 0x24, - LSM6DSV320X_ODR_HA02_AT_52Hz = 0x25, - LSM6DSV320X_ODR_HA02_AT_104Hz = 0x26, - LSM6DSV320X_ODR_HA02_AT_208Hz = 0x27, - LSM6DSV320X_ODR_HA02_AT_417Hz = 0x28, - LSM6DSV320X_ODR_HA02_AT_833Hz = 0x29, - LSM6DSV320X_ODR_HA02_AT_1667Hz = 0x2A, - LSM6DSV320X_ODR_HA02_AT_3333Hz = 0x2B, - LSM6DSV320X_ODR_HA02_AT_6667Hz = 0x2C, + LSM6DSV320X_ODR_HA02_AT_12Hz5 = 0x23, + LSM6DSV320X_ODR_HA02_AT_25Hz = 0x24, + LSM6DSV320X_ODR_HA02_AT_50Hz = 0x25, + LSM6DSV320X_ODR_HA02_AT_100Hz = 0x26, + LSM6DSV320X_ODR_HA02_AT_200Hz = 0x27, + LSM6DSV320X_ODR_HA02_AT_400Hz = 0x28, + LSM6DSV320X_ODR_HA02_AT_800Hz = 0x29, + LSM6DSV320X_ODR_HA02_AT_1600Hz = 0x2A, + LSM6DSV320X_ODR_HA02_AT_3200Hz = 0x2B, + LSM6DSV320X_ODR_HA02_AT_6400Hz = 0x2C, + LSM6DSV320X_ODR_HA03_AT_13Hz = 0x33, + LSM6DSV320X_ODR_HA03_AT_26Hz = 0x34, + LSM6DSV320X_ODR_HA03_AT_52Hz = 0x35, + LSM6DSV320X_ODR_HA03_AT_104Hz = 0x36, + LSM6DSV320X_ODR_HA03_AT_208Hz = 0x37, + LSM6DSV320X_ODR_HA03_AT_417Hz = 0x38, + LSM6DSV320X_ODR_HA03_AT_833Hz = 0x39, + LSM6DSV320X_ODR_HA03_AT_1667Hz = 0x3A, + LSM6DSV320X_ODR_HA03_AT_3333Hz = 0x3B, + LSM6DSV320X_ODR_HA03_AT_6667Hz = 0x3C, } lsm6dsv320x_data_rate_t; int32_t lsm6dsv320x_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv320x_data_rate_t val); @@ -4857,8 +4872,14 @@ int32_t lsm6dsv320x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, int32_t lsm6dsv320x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv320x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv320x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); +typedef enum +{ + LSM6DSV320X_FIFO_EV_WTM = 0x0, + LSM6DSV320X_FIFO_EV_FULL = 0x1, +} lsm6dsv320x_fifo_event_t; + +int32_t lsm6dsv320x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lsm6dsv320x_fifo_event_t val); +int32_t lsm6dsv320x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lsm6dsv320x_fifo_event_t *val); typedef enum { @@ -5648,6 +5669,8 @@ int32_t lsm6dsv320x_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); int32_t lsm6dsv320x_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t lsm6dsv320x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv320x_sflp_game_rotation_reset(const stmdev_ctx_t *ctx, uint8_t val); + typedef struct { float_t gbias_x; /* dps */ @@ -5809,5 +5832,3 @@ int32_t lsm6dsv320x_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, #endif #endif /*LSM6DSV320X_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.c b/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.c index 86e75d4..25e4020 100644 --- a/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.c +++ b/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.c @@ -6,17 +6,17 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ +#include #include "lsm6dsv32x_reg.h" /** @@ -293,6 +293,11 @@ int32_t lsm6dsv32x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.usr_off_on_out; return ret; @@ -439,9 +444,9 @@ int32_t lsm6dsv32x_reset_set(const stmdev_ctx_t *ctx, lsm6dsv32x_reset_t val) return ret; } - ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; - ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; - func_cfg_access.sw_por = (uint8_t)val & 0x01U; + ctrl3.boot = (val == LSM6DSV32X_RESTORE_CAL_PARAM) ? 1 : 0; + ctrl3.sw_reset = (val == LSM6DSV32X_RESTORE_CTRL_REGS) ? 1 : 0; + func_cfg_access.sw_por = (val == LSM6DSV32X_GLOBAL_RST) ? 1 : 0; ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1); ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); @@ -614,6 +619,11 @@ int32_t lsm6dsv32x_xl_data_rate_set(const stmdev_ctx_t *ctx, if (sel != 0U) { ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } + haodr.haodr_sel = sel; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1); } @@ -926,6 +936,10 @@ int32_t lsm6dsv32x_gy_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } ctrl2.odr_g = (uint8_t)val & 0x0Fu; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1); @@ -938,6 +952,11 @@ int32_t lsm6dsv32x_gy_data_rate_set(const stmdev_ctx_t *ctx, if (sel != 0U) { ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } + haodr.haodr_sel = sel; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1); } @@ -1257,6 +1276,11 @@ int32_t lsm6dsv32x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.if_inc; return ret; @@ -1300,6 +1324,11 @@ int32_t lsm6dsv32x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.bdu; return ret; @@ -1348,6 +1377,11 @@ int32_t lsm6dsv32x_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + if (ret != 0) + { + return ret; + } + *val = odr_trig.odr_trig_nodr; return ret; @@ -1393,6 +1427,10 @@ int32_t lsm6dsv32x_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4.drdy_pulsed) { @@ -1428,14 +1466,18 @@ int32_t lsm6dsv32x_interrupt_enable_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); - func.interrupts_enable = val.enable; - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); if (ret != 0) { return ret; } + func.interrupts_enable = val.enable; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&cfg, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&cfg, 1); + if (ret != 0) + { + return ret; + } cfg.lir = val.lir; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&cfg, 1); @@ -1659,6 +1701,11 @@ int32_t lsm6dsv32x_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8.xl_dualc_en; return ret; @@ -1958,12 +2005,6 @@ int32_t lsm6dsv32x_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsv32x_md1_cfg_t md1_cfg; int32_t ret; - /* not available on INT1 */ - if (val->drdy_temp == 1) - { - return -1; - } - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); if (ret != 0) { @@ -1978,12 +2019,8 @@ int32_t lsm6dsv32x_pin_int1_route_set(const stmdev_ctx_t *ctx, int1_ctrl.int1_cnt_bdr = val->cnt_bdr; ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - if (ret != 0) - { - return ret; - } - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD1_CFG, (uint8_t *)&md1_cfg, 1); if (ret != 0) { return ret; @@ -2018,7 +2055,10 @@ int32_t lsm6dsv32x_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsv32x_md1_cfg_t md1_cfg; int32_t ret; + memset(val, 0x0, sizeof(lsm6dsv32x_pin_int_route_t)); + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD1_CFG, (uint8_t *)&md1_cfg, 1); if (ret != 0) { return ret; @@ -2031,12 +2071,6 @@ int32_t lsm6dsv32x_pin_int1_route_get(const stmdev_ctx_t *ctx, val->fifo_full = int1_ctrl.int1_fifo_full; val->cnt_bdr = int1_ctrl.int1_cnt_bdr; - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret != 0) - { - return ret; - } - val->shub = md1_cfg.int1_shub; val->emb_func = md1_cfg.int1_emb_func; val->sixd = md1_cfg.int1_6d; @@ -2066,6 +2100,8 @@ int32_t lsm6dsv32x_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsv32x_md2_cfg_t md2_cfg; int32_t ret; + memset(val, 0x0, sizeof(lsm6dsv32x_pin_int_route_t)); + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); if (ret != 0) { @@ -2082,12 +2118,12 @@ int32_t lsm6dsv32x_pin_int2_route_set(const stmdev_ctx_t *ctx, int2_ctrl.int2_emb_func_endop = val->emb_func_endop; ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); if (ret != 0) { return ret; } - - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); ctrl4.int2_drdy_temp = val->drdy_temp; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); if (ret != 0) @@ -2096,6 +2132,10 @@ int32_t lsm6dsv32x_pin_int2_route_set(const stmdev_ctx_t *ctx, } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } ctrl7.int2_drdy_ah_qvar = val->drdy_ah_qvar; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); if (ret != 0) @@ -2205,11 +2245,13 @@ int32_t lsm6dsv32x_emb_pin_int1_route_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + return ret; } + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + if (ret == 0) { emb_func_int1.int1_tilt = val->tilt; @@ -2246,11 +2288,13 @@ int32_t lsm6dsv32x_emb_pin_int1_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + return ret; } + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + if (ret == 0) { val->tilt = emb_func_int1.int1_tilt; @@ -2279,11 +2323,13 @@ int32_t lsm6dsv32x_emb_pin_int2_route_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + return ret; } + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + if (ret == 0) { emb_func_int2.int2_tilt = val->tilt; @@ -2320,11 +2366,13 @@ int32_t lsm6dsv32x_emb_pin_int2_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + return ret; } + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + if (ret == 0) { val->tilt = emb_func_int2.int2_tilt; @@ -2352,10 +2400,15 @@ int32_t lsm6dsv32x_embedded_int_cfg_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + return ret; + } + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + + if (ret == 0) + { switch (val) { case LSM6DSV32X_INT_LATCH_DISABLE: @@ -2391,10 +2444,15 @@ int32_t lsm6dsv32x_embedded_int_cfg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret == 0) + { if (page_rw.emb_func_lir == 0U) { *val = LSM6DSV32X_INT_LATCH_DISABLE; @@ -2438,6 +2496,10 @@ int32_t lsm6dsv32x_embedded_status_get(const stmdev_ctx_t *ctx, /* embedded func */ ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) @@ -2487,18 +2549,14 @@ int32_t lsm6dsv32x_all_sources_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); - functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); if (ret != 0) { return ret; } + functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_STATUS1, (uint8_t *)&buff, 4); - if (ret != 0) - { - return ret; - } + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_STATUS1, (uint8_t *)&buff, 4); bytecpy((uint8_t *)&fifo_status2, &buff[1]); bytecpy((uint8_t *)&all_int_src, &buff[2]); @@ -2585,9 +2643,12 @@ int32_t lsm6dsv32x_all_sources_get(const stmdev_ctx_t *ctx, /* embedded func */ ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, - 1); - ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + if (ret == 0) + { + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, + 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) { @@ -2881,6 +2942,11 @@ int32_t lsm6dsv32x_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + if (ret != 0) + { + return ret; + } + *val = (int8_t)internal_freq.freq_fine; return ret; @@ -2916,6 +2982,10 @@ int32_t lsm6dsv32x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, /* set page write */ ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_ENABLE; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -2926,6 +2996,10 @@ int32_t lsm6dsv32x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, /* select page */ ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -2943,7 +3017,7 @@ int32_t lsm6dsv32x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, goto exit; } - for (i = 0; ((i < len) && (ret == 0)); i++) + for (i = 0; i < len; i++) { ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_VALUE, &buf[i], 1); if (ret != 0) @@ -2983,6 +3057,10 @@ int32_t lsm6dsv32x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, /* unset page write */ ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -3030,6 +3108,10 @@ int32_t lsm6dsv32x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* set page write */ ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -3040,6 +3122,10 @@ int32_t lsm6dsv32x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* select page */ ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -3097,6 +3183,10 @@ int32_t lsm6dsv32x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* unset page write */ ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -3478,6 +3568,11 @@ int32_t lsm6dsv32x_eis_gy_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl_eis.g_eis_on_g_ois_out_reg; return ret; @@ -3595,6 +3690,11 @@ int32_t lsm6dsv32x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl1.wtm; return ret; @@ -3637,6 +3737,11 @@ int32_t lsm6dsv32x_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t * int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; return ret; @@ -3749,6 +3854,11 @@ int32_t lsm6dsv32x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odr_chg_en; return ret; @@ -3771,6 +3881,10 @@ int32_t lsm6dsv32x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } fifo_ctrl2.fifo_compr_rt_en = val; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); if (ret != 0) @@ -3785,8 +3899,11 @@ int32_t lsm6dsv32x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); - emb_func_en_b.fifo_compr_en = val; - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + if (ret == 0) + { + emb_func_en_b.fifo_compr_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); return ret; @@ -3807,6 +3924,10 @@ int32_t lsm6dsv32x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } *val = fifo_ctrl2.fifo_compr_rt_en; @@ -3821,7 +3942,7 @@ int32_t lsm6dsv32x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lsm6dsv32x_fifo_event_t val) { lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3829,7 +3950,7 @@ int32_t lsm6dsv32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) { - fifo_ctrl2.stop_on_wtm = val; + fifo_ctrl2.stop_on_wtm = (val == LSM6DSV32X_FIFO_EV_WTM) ? 1 : 0; ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); } @@ -3844,13 +3965,16 @@ int32_t lsm6dsv32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv32x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv32x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lsm6dsv32x_fifo_event_t *val) { lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - *val = fifo_ctrl2.stop_on_wtm; + if (ret == 0) + { + *val = (fifo_ctrl2.stop_on_wtm == 1) ? LSM6DSV32X_FIFO_EV_WTM : LSM6DSV32X_FIFO_EV_FULL; + } return ret; } @@ -4183,6 +4307,11 @@ int32_t lsm6dsv32x_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl4.g_eis_fifo_en; return ret; @@ -4648,8 +4777,11 @@ int32_t lsm6dsv32x_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); - emb_func_fifo_en_a.step_counter_fifo_en = val; - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret == 0) + { + emb_func_fifo_en_a.step_counter_fifo_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -4676,7 +4808,10 @@ int32_t lsm6dsv32x_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) } ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); - *val = emb_func_fifo_en_a.step_counter_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_a.step_counter_fifo_en; + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -4703,8 +4838,11 @@ int32_t lsm6dsv32x_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val) } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); - emb_func_fifo_en_a.mlc_fifo_en = val; - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret == 0) + { + emb_func_fifo_en_a.mlc_fifo_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -4731,7 +4869,10 @@ int32_t lsm6dsv32x_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); - *val = emb_func_fifo_en_a.mlc_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_a.mlc_fifo_en; + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -4758,8 +4899,11 @@ int32_t lsm6dsv32x_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); - emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val; - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret == 0) + { + emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -4786,7 +4930,10 @@ int32_t lsm6dsv32x_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); - *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -4813,8 +4960,11 @@ int32_t lsm6dsv32x_fifo_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); - slv_config.batch_ext_sens_0_en = val; - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); + if (ret == 0) + { + slv_config.batch_ext_sens_0_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -4841,7 +4991,10 @@ int32_t lsm6dsv32x_fifo_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); - *val = slv_config.batch_ext_sens_0_en; + if (ret == 0) + { + *val = slv_config.batch_ext_sens_0_en; + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -4866,6 +5019,9 @@ int32_t lsm6dsv32x_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + if (ret == 0) + { emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; @@ -4896,7 +5052,9 @@ int32_t lsm6dsv32x_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); - + } + if (ret == 0) + { val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; @@ -5000,6 +5158,10 @@ int32_t lsm6dsv32x_filt_settling_mask_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } ctrl4.drdy_mask = val.drdy; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); if (ret != 0) @@ -5008,6 +5170,10 @@ int32_t lsm6dsv32x_filt_settling_mask_set(const stmdev_ctx_t *ctx, } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); @@ -5017,6 +5183,10 @@ int32_t lsm6dsv32x_filt_settling_mask_set(const stmdev_ctx_t *ctx, } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + if (ret != 0) + { + return ret; + } ui_int_ois.drdy_mask_ois = val.ois_drdy; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); @@ -5042,6 +5212,10 @@ int32_t lsm6dsv32x_filt_settling_mask_get(const stmdev_ctx_t *ctx, ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + if (ret != 0) + { + return ret; + } val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl; val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl; @@ -5091,6 +5265,11 @@ int32_t lsm6dsv32x_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + if (ret != 0) + { + return ret; + } + val->ois_drdy = spi2_int_ois.drdy_mask_ois; return ret; @@ -5220,6 +5399,11 @@ int32_t lsm6dsv32x_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7.lpf1_g_en; return ret; @@ -5348,6 +5532,11 @@ int32_t lsm6dsv32x_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.lpf2_xl_en; return ret; @@ -5390,6 +5579,11 @@ int32_t lsm6dsv32x_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.hp_slope_xl_en; return ret; @@ -5432,8 +5626,13 @@ int32_t lsm6dsv32x_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *v int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); - *val = ctrl9.xl_fastsettl_mode; - + if (ret != 0) + { + return ret; + } + + *val = ctrl9.xl_fastsettl_mode; + return ret; } @@ -5616,6 +5815,11 @@ int32_t lsm6dsv32x_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *v int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.hw_func_mask_xl_settl; return ret; @@ -5996,6 +6200,10 @@ int32_t lsm6dsv32x_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_STATUS, (uint8_t *)&ctrl_status, 1); + if (ret != 0) + { + return ret; + } *val = ctrl_status.fsm_wr_ctrl_status; @@ -6071,6 +6279,10 @@ int32_t lsm6dsv32x_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_fsm_mode_t * int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) @@ -6107,6 +6319,10 @@ int32_t lsm6dsv32x_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) buff[0] = (uint8_t)(val - (buff[1] * 256U)); ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2); ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -6127,6 +6343,10 @@ int32_t lsm6dsv32x_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_LONG_COUNTER_L, &buff[0], 2); ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) @@ -6153,6 +6373,10 @@ int32_t lsm6dsv32x_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv32x_fsm_out_t *va int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_OUTS1, (uint8_t *)val, 8); ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -6204,7 +6428,10 @@ int32_t lsm6dsv32x_fsm_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + if (ret == 0) + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) { @@ -6480,41 +6707,90 @@ int32_t lsm6dsv32x_sflp_game_gbias_set(const stmdev_ctx_t *ctx, /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */ ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL1, conf_saved, 2); + if (ret != 0) + { + return ret; + } + ret += lsm6dsv32x_xl_mode_set(ctx, LSM6DSV32X_XL_HIGH_PERFORMANCE_MD); ret += lsm6dsv32x_gy_mode_set(ctx, LSM6DSV32X_GY_HIGH_PERFORMANCE_MD); if (((uint8_t)conf_saved[0] & 0x0FU) == (uint8_t)LSM6DSV32X_ODR_OFF) { ret += lsm6dsv32x_xl_data_rate_set(ctx, LSM6DSV32X_ODR_AT_120Hz); } + if (ret != 0) + { + goto exit; + } /* Make sure to turn the sensor-hub master off */ ret += lsm6dsv32x_sh_master_get(ctx, &master_config); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv32x_sh_master_set(ctx, 0); + if (ret != 0) + { + goto exit; + } /* disable algos */ ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, emb_func_en_saved, 2); - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, reg_zero, 2); - do + if (ret == 0) { - ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EXEC_STATUS, - (uint8_t *)&emb_func_sts, 1); - } while (emb_func_sts.emb_func_endop != 1U); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, reg_zero, 2); + } + if (ret == 0) + { + do + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1U); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + goto exit; + } // enable gbias setting ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); - ctrl10.emb_func_debug = 1; - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret == 0) + { + ctrl10.emb_func_debug = 1; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + } + if (ret != 0) + { + goto exit; + } /* enable algos */ ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); - emb_func_en_saved[0] |= 0x02U; /* force SFLP GAME en */ - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, emb_func_en_saved, - 2); + if (ret == 0) + { + emb_func_en_saved[0] |= 0x02U; /* force SFLP GAME en */ + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv32x_xl_full_scale_get(ctx, &xl_fs); + if (ret != 0) + { + goto exit; + } /* Read XL data */ do @@ -6522,9 +6798,17 @@ int32_t lsm6dsv32x_sflp_game_gbias_set(const stmdev_ctx_t *ctx, ret += lsm6dsv32x_flag_data_ready_get(ctx, &drdy); } while (drdy.drdy_xl != 1U); ret += lsm6dsv32x_acceleration_raw_get(ctx, xl_data); + if (ret != 0) + { + goto exit; + } /* force sflp initialization */ ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + goto exit; + } for (i = 0; i < 3U; i++) { j = 0; @@ -6549,21 +6833,34 @@ int32_t lsm6dsv32x_sflp_game_gbias_set(const stmdev_ctx_t *ctx, 1); } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + goto exit; + } // wait end_op (and at least 30 us) ctx->mdelay(1); ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } do { ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_sts, 1); } while (emb_func_sts.emb_func_endop != 1U); ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + goto exit; + } /* write gbias in embedded advanced features registers */ ret += lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_SFLP_GAME_GBIASX_L, (uint8_t *)gbias_hf, 6); +exit: /* reload previous sensor configuration */ ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL1, conf_saved, 2); @@ -6760,6 +7057,10 @@ int32_t lsm6dsv32x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret != 0) + { + return ret; + } ext_cfg_a.ext_z_axis = (uint8_t)val & 0x07U; ret += lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); @@ -7063,6 +7364,11 @@ int32_t lsm6dsv32x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t * ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + if (ret != 0) + { + return ret; + } + *val = fsm_programs.fsm_n_prog; return ret; @@ -7142,14 +7448,18 @@ int32_t lsm6dsv32x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); if (ret != 0) { return ret; } + wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } free_fall.ff_dur = (uint8_t)val & 0x1FU; ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1); @@ -7172,6 +7482,10 @@ int32_t lsm6dsv32x_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -7420,7 +7734,10 @@ int32_t lsm6dsv32x_mlc_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MLC_ODR, (uint8_t *)&mlc_odr, 1); + if (ret == 0) + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) { @@ -7648,6 +7965,11 @@ int32_t lsm6dsv32x_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + *val = (int8_t)func_cfg_access.spi2_reset; return ret; @@ -7690,6 +8012,11 @@ int32_t lsm6dsv32x_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *v int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.ois_pu_dis; return ret; @@ -7868,6 +8195,11 @@ int32_t lsm6dsv32x_ois_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } + *val = ui_ctrl1_ois.spi2_read_en; return ret; @@ -8187,6 +8519,11 @@ int32_t lsm6dsv32x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = tap_ths_6d.d4d_en; return ret; @@ -8314,6 +8651,11 @@ int32_t lsm6dsv32x_ah_qvar_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + val->ah_qvar_en = ctrl7.ah_qvar_en; return ret; @@ -8431,6 +8773,11 @@ int32_t lsm6dsv32x_i3c_int_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl5.int_en_i3c; return ret; @@ -8558,6 +8905,11 @@ int32_t lsm6dsv32x_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.shub_pu_en; return ret; @@ -8577,7 +8929,10 @@ int32_t lsm6dsv32x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); - ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SENSOR_HUB_1, val, len); + if (ret == 0) + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SENSOR_HUB_1, val, len); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); return ret; @@ -8628,7 +8983,10 @@ int32_t lsm6dsv32x_sh_slave_connected_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); - ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret == 0) + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) { @@ -8704,9 +9062,16 @@ int32_t lsm6dsv32x_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); - *val = master_config.master_on; + if (ret == 0) + { + *val = master_config.master_on; + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -8756,9 +9121,15 @@ int32_t lsm6dsv32x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); - ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret == 0) + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } - *val = master_config.pass_through_mode; + if (ret == 0) + { + *val = master_config.pass_through_mode; + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -8810,6 +9181,10 @@ int32_t lsm6dsv32x_sh_syncro_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) @@ -8880,7 +9255,10 @@ int32_t lsm6dsv32x_sh_write_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); - ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret == 0) + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) { @@ -8948,9 +9326,16 @@ int32_t lsm6dsv32x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); - *val = master_config.rst_master_regs; + if (ret == 0) + { + *val = master_config.rst_master_regs; + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -9049,6 +9434,10 @@ int32_t lsm6dsv32x_sh_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) @@ -9215,6 +9604,11 @@ int32_t lsm6dsv32x_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.sdo_pu_en; return ret; @@ -9379,6 +9773,11 @@ int32_t lsm6dsv32x_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.sda_pu_en; return ret; @@ -9478,8 +9877,11 @@ int32_t lsm6dsv32x_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - emb_func_en_a.sign_motion_en = val; - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret == 0) + { + emb_func_en_a.sign_motion_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -9506,7 +9908,10 @@ int32_t lsm6dsv32x_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - *val = emb_func_en_a.sign_motion_en; + if (ret == 0) + { + *val = emb_func_en_a.sign_motion_en; + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -9571,6 +9976,9 @@ int32_t lsm6dsv32x_stpcnt_mode_set(const stmdev_ctx_t *ctx, { ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + if (ret == 0) + { pedo_cmd_reg.fp_rejection_en = val.false_step_rej; ret += lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); @@ -9595,6 +10003,10 @@ int32_t lsm6dsv32x_stpcnt_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) @@ -9629,6 +10041,10 @@ int32_t lsm6dsv32x_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_STEP_COUNTER_L, &buff[0], 2); ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) @@ -9696,7 +10112,10 @@ int32_t lsm6dsv32x_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); - *val = emb_func_src.pedo_rst_step; + if (ret == 0) + { + *val = emb_func_src.pedo_rst_step; + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -9743,7 +10162,10 @@ int32_t lsm6dsv32x_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); - *val = pedo_deb_steps_conf.deb_step; + if (ret == 0) + { + *val = pedo_deb_steps_conf.deb_step; + } return ret; } @@ -9862,7 +10284,10 @@ int32_t lsm6dsv32x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val) } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - *val = emb_func_en_a.sflp_game_en; + if (ret == 0) + { + *val = emb_func_en_a.sflp_game_en; + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -9919,7 +10344,10 @@ int32_t lsm6dsv32x_sflp_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + if (ret == 0) + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); if (ret != 0) { @@ -10316,8 +10744,11 @@ int32_t lsm6dsv32x_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - emb_func_en_a.tilt_en = val; - ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret == 0) + { + emb_func_en_a.tilt_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -10344,7 +10775,10 @@ int32_t lsm6dsv32x_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) } ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - *val = emb_func_en_a.tilt_en; + if (ret == 0) + { + *val = emb_func_en_a.tilt_en; + } ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); @@ -10428,7 +10862,10 @@ int32_t lsm6dsv32x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); - *val = functions_enable.timestamp_en; + if (ret == 0) + { + *val = functions_enable.timestamp_en; + } return ret; } diff --git a/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.h b/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.h index 358900d..b6b981a 100644 --- a/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.h +++ b/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -3916,10 +3918,11 @@ int32_t lsm6dsv32x_xl_offset_mg_get(const stmdev_ctx_t *ctx, typedef enum { - LSM6DSV32X_READY = 0x0, - LSM6DSV32X_GLOBAL_RST = 0x1, - LSM6DSV32X_RESTORE_CAL_PARAM = 0x2, - LSM6DSV32X_RESTORE_CTRL_REGS = 0x4, + LSM6DSV32X_READY = 0x0, /* No active reset in progress */ + LSM6DSV32X_GLOBAL_RST = 0x1, /* Complete reset: boot, software reset, + embedded functions, and internal filters */ + LSM6DSV32X_RESTORE_CAL_PARAM = 0x2, /* Reload trimming parameters */ + LSM6DSV32X_RESTORE_CTRL_REGS = 0x4, /* Reset control registers to default values */ } lsm6dsv32x_reset_t; int32_t lsm6dsv32x_reset_set(const stmdev_ctx_t *ctx, lsm6dsv32x_reset_t val); int32_t lsm6dsv32x_reset_get(const stmdev_ctx_t *ctx, lsm6dsv32x_reset_t *val); @@ -4367,8 +4370,14 @@ int32_t lsm6dsv32x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, int32_t lsm6dsv32x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv32x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); +typedef enum +{ + LSM6DSV32X_FIFO_EV_WTM = 0x0, + LSM6DSV32X_FIFO_EV_FULL = 0x1, +} lsm6dsv32x_fifo_event_t; + +int32_t lsm6dsv32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lsm6dsv32x_fifo_event_t val); +int32_t lsm6dsv32x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lsm6dsv32x_fifo_event_t *val); typedef enum { @@ -5339,5 +5348,3 @@ int32_t lsm6dsv32x_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, #endif #endif /*LSM6DSV32X_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv80x_STdC/driver/lsm6dsv80x_reg.c b/sensor/stmemsc/lsm6dsv80x_STdC/driver/lsm6dsv80x_reg.c index d8b5e5b..2083079 100644 --- a/sensor/stmemsc/lsm6dsv80x_STdC/driver/lsm6dsv80x_reg.c +++ b/sensor/stmemsc/lsm6dsv80x_STdC/driver/lsm6dsv80x_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -159,6 +158,10 @@ float_t lsm6dsv80x_from_fs80_to_mg(int16_t lsb) return ((float_t)lsb) * 3.904; } +float_t lsm6dsv80x_from_fs125_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 4.375f; +} float_t lsm6dsv80x_from_fs250_to_mdps(int16_t lsb) { return ((float_t)lsb) * 8.750f; @@ -215,6 +218,19 @@ float_t lsm6dsv80x_from_quaternion_lsb_to_float(uint16_t lsb) return npy_half_to_float(lsb); } +static uint32_t npy_halfbits_to_floatbits(uint16_t h); +/** + * @brief Convert from 16-bit to 32-bit float number + * + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +uint32_t lsm6dsv80x_from_f16_to_f32(uint16_t val) +{ + return npy_halfbits_to_floatbits(val); +} + /** * @} * @@ -265,6 +281,10 @@ int32_t lsm6dsv80x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } *val = ctrl9.usr_off_on_out; return ret; @@ -508,9 +528,9 @@ int32_t lsm6dsv80x_reset_set(const stmdev_ctx_t *ctx, lsm6dsv80x_reset_t val) return ret; } - ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; - ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; - func_cfg_access.sw_por = (uint8_t)val & 0x01U; + ctrl3.boot = (val == LSM6DSV80X_RESTORE_CAL_PARAM) ? 1 : 0; + ctrl3.sw_reset = (val == LSM6DSV80X_RESTORE_CTRL_REGS) ? 1 : 0; + func_cfg_access.sw_por = (val == LSM6DSV80X_GLOBAL_RST) ? 1 : 0; ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_CTRL3, (uint8_t *)&ctrl3, 1); ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); @@ -682,6 +702,10 @@ int32_t lsm6dsv80x_xl_data_rate_set(const stmdev_ctx_t *ctx, if (sel != 0U) { ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } haodr.haodr_sel = sel; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_HAODR_CFG, (uint8_t *)&haodr, 1); } @@ -739,7 +763,10 @@ int32_t lsm6dsv80x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_15Hz625; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_13Hz; + *val = LSM6DSV80X_ODR_HA02_AT_12Hz5; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_13Hz; break; } break; @@ -755,7 +782,10 @@ int32_t lsm6dsv80x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_31Hz25; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_26Hz; + *val = LSM6DSV80X_ODR_HA02_AT_25Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_26Hz; break; } break; @@ -771,7 +801,10 @@ int32_t lsm6dsv80x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_62Hz5; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_52Hz; + *val = LSM6DSV80X_ODR_HA02_AT_50Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_52Hz; break; } break; @@ -787,7 +820,10 @@ int32_t lsm6dsv80x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_125Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_104Hz; + *val = LSM6DSV80X_ODR_HA02_AT_100Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_104Hz; break; } break; @@ -803,7 +839,10 @@ int32_t lsm6dsv80x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_250Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_208Hz; + *val = LSM6DSV80X_ODR_HA02_AT_200Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_208Hz; break; } break; @@ -819,7 +858,10 @@ int32_t lsm6dsv80x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_500Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_417Hz; + *val = LSM6DSV80X_ODR_HA02_AT_400Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_417Hz; break; } break; @@ -835,7 +877,10 @@ int32_t lsm6dsv80x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_1000Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_833Hz; + *val = LSM6DSV80X_ODR_HA02_AT_800Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_833Hz; break; } break; @@ -851,7 +896,10 @@ int32_t lsm6dsv80x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_2000Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_1667Hz; + *val = LSM6DSV80X_ODR_HA02_AT_1600Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_1667Hz; break; } break; @@ -867,7 +915,10 @@ int32_t lsm6dsv80x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_4000Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_3333Hz; + *val = LSM6DSV80X_ODR_HA02_AT_3200Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_3333Hz; break; } break; @@ -883,7 +934,10 @@ int32_t lsm6dsv80x_xl_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_8000Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_6667Hz; + *val = LSM6DSV80X_ODR_HA02_AT_6400Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_6667Hz; break; } break; @@ -912,6 +966,11 @@ int32_t lsm6dsv80x_hg_xl_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL1_XL_HG, (uint8_t *)&ctrl1_xl_hg, 1); + if (ret != 0) + { + return ret; + } + ctrl1_xl_hg.odr_xl_hg = (uint8_t)val & 0x07U; ctrl1_xl_hg.xl_hg_regout_en = reg_out_en & 0x1U; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_CTRL1_XL_HG, (uint8_t *)&ctrl1_xl_hg, 1); @@ -935,6 +994,10 @@ int32_t lsm6dsv80x_hg_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL1_XL_HG, (uint8_t *)&ctrl1_xl_hg, 1); + if (ret != 0) + { + return ret; + } *reg_out_en = ctrl1_xl_hg.xl_hg_regout_en; @@ -1070,6 +1133,10 @@ int32_t lsm6dsv80x_gy_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } ctrl2.odr_g = (uint8_t)val & 0x0Fu; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_CTRL2, (uint8_t *)&ctrl2, 1); if (ret != 0) @@ -1081,6 +1148,10 @@ int32_t lsm6dsv80x_gy_data_rate_set(const stmdev_ctx_t *ctx, if (sel != 0U) { ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } haodr.haodr_sel = sel; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_HAODR_CFG, (uint8_t *)&haodr, 1); } @@ -1138,7 +1209,10 @@ int32_t lsm6dsv80x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_15Hz625; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_13Hz; + *val = LSM6DSV80X_ODR_HA02_AT_12Hz5; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_13Hz; break; } break; @@ -1154,7 +1228,10 @@ int32_t lsm6dsv80x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_31Hz25; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_26Hz; + *val = LSM6DSV80X_ODR_HA02_AT_25Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_26Hz; break; } break; @@ -1170,7 +1247,10 @@ int32_t lsm6dsv80x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_62Hz5; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_52Hz; + *val = LSM6DSV80X_ODR_HA02_AT_50Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_52Hz; break; } break; @@ -1186,7 +1266,10 @@ int32_t lsm6dsv80x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_125Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_104Hz; + *val = LSM6DSV80X_ODR_HA02_AT_100Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_104Hz; break; } break; @@ -1202,7 +1285,10 @@ int32_t lsm6dsv80x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_250Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_208Hz; + *val = LSM6DSV80X_ODR_HA02_AT_200Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_208Hz; break; } break; @@ -1218,7 +1304,10 @@ int32_t lsm6dsv80x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_500Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_417Hz; + *val = LSM6DSV80X_ODR_HA02_AT_400Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_417Hz; break; } break; @@ -1234,7 +1323,10 @@ int32_t lsm6dsv80x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_1000Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_833Hz; + *val = LSM6DSV80X_ODR_HA02_AT_800Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_833Hz; break; } break; @@ -1250,7 +1342,10 @@ int32_t lsm6dsv80x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_2000Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_1667Hz; + *val = LSM6DSV80X_ODR_HA02_AT_1600Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_1667Hz; break; } break; @@ -1266,7 +1361,10 @@ int32_t lsm6dsv80x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_4000Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_3333Hz; + *val = LSM6DSV80X_ODR_HA02_AT_3200Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_3333Hz; break; } break; @@ -1282,7 +1380,10 @@ int32_t lsm6dsv80x_gy_data_rate_get(const stmdev_ctx_t *ctx, *val = LSM6DSV80X_ODR_HA01_AT_8000Hz; break; case 2: - *val = LSM6DSV80X_ODR_HA02_AT_6667Hz; + *val = LSM6DSV80X_ODR_HA02_AT_6400Hz; + break; + case 3: + *val = LSM6DSV80X_ODR_HA03_AT_6667Hz; break; } break; @@ -1292,6 +1393,7 @@ int32_t lsm6dsv80x_gy_data_rate_get(const stmdev_ctx_t *ctx, break; } + return ret; } @@ -1404,6 +1506,11 @@ int32_t lsm6dsv80x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.if_inc; return ret; @@ -1447,6 +1554,11 @@ int32_t lsm6dsv80x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.bdu; return ret; @@ -1495,6 +1607,10 @@ int32_t lsm6dsv80x_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + if (ret != 0) + { + return ret; + } *val = odr_trig.odr_trig_nodr; return ret; @@ -1540,6 +1656,10 @@ int32_t lsm6dsv80x_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4.drdy_pulsed) { @@ -1575,14 +1695,20 @@ int32_t lsm6dsv80x_interrupt_enable_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + if (ret != 0) + { + return ret; + } + func.interrupts_enable = val.enable; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + + ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_TAP_CFG0, (uint8_t *)&cfg, 1); if (ret != 0) { return ret; } - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_TAP_CFG0, (uint8_t *)&cfg, 1); cfg.lir = val.lir; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_TAP_CFG0, (uint8_t *)&cfg, 1); @@ -2272,25 +2398,23 @@ int32_t lsm6dsv80x_hg_event_get(const stmdev_ctx_t *ctx, lsm6dsv80x_hg_event_t * val->hg_event = int_src.hg_ia; /* no High-g event */ - if (int_src.hg_ia == 0) + if (int_src.hg_ia != 0) { - return 0; - } + ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_HG_WAKE_UP_SRC, (uint8_t *)&wup_src, 1); + if (ret != 0) + { + return ret; + } - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_HG_WAKE_UP_SRC, (uint8_t *)&wup_src, 1); - if (ret != 0) - { - return ret; + val->hg_wakeup_z = wup_src.hg_z_wu; + val->hg_wakeup_y = wup_src.hg_y_wu; + val->hg_wakeup_x = wup_src.hg_x_wu; + val->hg_wakeup = wup_src.hg_wu_ia; + val->hg_wakeup_chg = wup_src.hg_wu_change_ia; + val->hg_shock = wup_src.hg_shock_state; + val->hg_shock_change = wup_src.hg_shock_change_ia; } - val->hg_wakeup_z = wup_src.hg_z_wu; - val->hg_wakeup_y = wup_src.hg_y_wu; - val->hg_wakeup_x = wup_src.hg_x_wu; - val->hg_wakeup = wup_src.hg_wu_ia; - val->hg_wakeup_chg = wup_src.hg_wu_change_ia; - val->hg_shock = wup_src.hg_shock_state; - val->hg_shock_change = wup_src.hg_shock_change_ia; - return ret; } @@ -2363,10 +2487,6 @@ int32_t lsm6dsv80x_pin_int1_route_set(const stmdev_ctx_t *ctx, md1_cfg.int1_sleep_change = val->sleep_change; ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret != 0) - { - return ret; - } return ret; } @@ -2455,6 +2575,10 @@ int32_t lsm6dsv80x_pin_int2_route_set(const stmdev_ctx_t *ctx, } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } ctrl4.int2_drdy_temp = val->drdy_temp; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_CTRL4, (uint8_t *)&ctrl4, 1); if (ret != 0) @@ -2477,10 +2601,6 @@ int32_t lsm6dsv80x_pin_int2_route_set(const stmdev_ctx_t *ctx, md2_cfg.int2_sleep_change = val->sleep_change; ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret != 0) - { - return ret; - } return ret; } @@ -2745,42 +2865,48 @@ int32_t lsm6dsv80x_pin_int1_route_embedded_set(const stmdev_ctx_t *ctx, lsm6dsv80x_mlc_int1_t mlc_int1; int32_t ret; - /* Embedded Functions */ - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MD1_CFG, (uint8_t *)&md1_cfg, 1); if (ret != 0) { return ret; } - emb_func_int1.int1_step_detector = val->step_detector; - emb_func_int1.int1_tilt = val->tilt; - emb_func_int1.int1_sig_mot = val->sig_mot; + md1_cfg.int1_emb_func = 1; - ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_MD1_CFG, (uint8_t *)&md1_cfg, 1); if (ret != 0) { return ret; } - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + /* Embedded Functions */ + ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } - md1_cfg.int1_emb_func = 1; + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + if (ret != 0) + { + goto exit; + } - ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + emb_func_int1.int1_step_detector = val->step_detector; + emb_func_int1.int1_tilt = val->tilt; + emb_func_int1.int1_sig_mot = val->sig_mot; + + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); if (ret != 0) { - return ret; + goto exit; } /* FSM */ - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_INT1, (uint8_t *)&fsm_int1, 1); + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_INT1, (uint8_t *)&fsm_int1, 1); if (ret != 0) { - return ret; + goto exit; } fsm_int1.int1_fsm1 = val->fsm1; @@ -2792,17 +2918,17 @@ int32_t lsm6dsv80x_pin_int1_route_embedded_set(const stmdev_ctx_t *ctx, fsm_int1.int1_fsm7 = val->fsm7; fsm_int1.int1_fsm8 = val->fsm8; - ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FSM_INT1, (uint8_t *)&fsm_int1, 1); + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FSM_INT1, (uint8_t *)&fsm_int1, 1); if (ret != 0) { - return ret; + goto exit; } /* MLC */ - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MLC_INT1, (uint8_t *)&mlc_int1, 1); + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MLC_INT1, (uint8_t *)&mlc_int1, 1); if (ret != 0) { - return ret; + goto exit; } mlc_int1.int1_mlc1 = val->mlc1; @@ -2814,12 +2940,15 @@ int32_t lsm6dsv80x_pin_int1_route_embedded_set(const stmdev_ctx_t *ctx, mlc_int1.int1_mlc7 = val->mlc7; mlc_int1.int1_mlc8 = val->mlc8; - ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_MLC_INT1, (uint8_t *)&mlc_int1, 1); + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_MLC_INT1, (uint8_t *)&mlc_int1, 1); if (ret != 0) { - return ret; + goto exit; } +exit: + ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); + return ret; } @@ -2841,10 +2970,16 @@ int32_t lsm6dsv80x_pin_int1_route_embedded_get(const stmdev_ctx_t *ctx, int32_t ret; /* Embedded Functions */ - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; + } + + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + if (ret != 0) + { + goto exit; } val->step_detector = emb_func_int1.int1_step_detector; @@ -2852,10 +2987,10 @@ int32_t lsm6dsv80x_pin_int1_route_embedded_get(const stmdev_ctx_t *ctx, val->tilt = emb_func_int1.int1_tilt; /* FSM */ - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_INT1, (uint8_t *)&fsm_int1, 1); + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_INT1, (uint8_t *)&fsm_int1, 1); if (ret != 0) { - return ret; + goto exit; } val->fsm1 = fsm_int1.int1_fsm1; @@ -2868,10 +3003,10 @@ int32_t lsm6dsv80x_pin_int1_route_embedded_get(const stmdev_ctx_t *ctx, val->fsm8 = fsm_int1.int1_fsm8; /* MLC */ - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MLC_INT1, (uint8_t *)&mlc_int1, 1); + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MLC_INT1, (uint8_t *)&mlc_int1, 1); if (ret != 0) { - return ret; + goto exit; } val->mlc1 = mlc_int1.int1_mlc1; @@ -2883,6 +3018,9 @@ int32_t lsm6dsv80x_pin_int1_route_embedded_get(const stmdev_ctx_t *ctx, val->mlc7 = mlc_int1.int1_mlc7; val->mlc8 = mlc_int1.int1_mlc8; +exit: + ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); + return ret; } @@ -2904,42 +3042,48 @@ int32_t lsm6dsv80x_pin_int2_route_embedded_set(const stmdev_ctx_t *ctx, lsm6dsv80x_mlc_int2_t mlc_int2; int32_t ret; - /* Embedded Functions */ - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MD2_CFG, (uint8_t *)&md2_cfg, 1); if (ret != 0) { return ret; } - emb_func_int2.int2_step_detector = val->step_detector; - emb_func_int2.int2_tilt = val->tilt; - emb_func_int2.int2_sig_mot = val->sig_mot; + md2_cfg.int2_emb_func = 1; - ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_MD2_CFG, (uint8_t *)&md2_cfg, 1); if (ret != 0) { return ret; } - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + /* Embedded Functions */ + ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } - md2_cfg.int2_emb_func = 1; + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + if (ret != 0) + { + goto exit; + } - ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + emb_func_int2.int2_step_detector = val->step_detector; + emb_func_int2.int2_tilt = val->tilt; + emb_func_int2.int2_sig_mot = val->sig_mot; + + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); if (ret != 0) { - return ret; + goto exit; } /* FSM */ - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_INT2, (uint8_t *)&fsm_int2, 1); if (ret != 0) { - return ret; + goto exit; } fsm_int2.int2_fsm1 = val->fsm1; @@ -2951,17 +3095,17 @@ int32_t lsm6dsv80x_pin_int2_route_embedded_set(const stmdev_ctx_t *ctx, fsm_int2.int2_fsm7 = val->fsm7; fsm_int2.int2_fsm8 = val->fsm8; - ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FSM_INT2, (uint8_t *)&fsm_int2, 1); if (ret != 0) { - return ret; + goto exit; } /* MLC */ - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MLC_INT2, (uint8_t *)&mlc_int2, 1); + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MLC_INT2, (uint8_t *)&mlc_int2, 1); if (ret != 0) { - return ret; + goto exit; } mlc_int2.int2_mlc1 = val->mlc1; @@ -2973,12 +3117,15 @@ int32_t lsm6dsv80x_pin_int2_route_embedded_set(const stmdev_ctx_t *ctx, mlc_int2.int2_mlc7 = val->mlc7; mlc_int2.int2_mlc8 = val->mlc8; - ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_MLC_INT2, (uint8_t *)&mlc_int2, 1); + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_MLC_INT2, (uint8_t *)&mlc_int2, 1); if (ret != 0) { - return ret; + goto exit; } +exit: + ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); + return ret; } @@ -3000,10 +3147,16 @@ int32_t lsm6dsv80x_pin_int2_route_embedded_get(const stmdev_ctx_t *ctx, int32_t ret; /* Embedded Functions */ - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; + } + + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + if (ret != 0) + { + goto exit; } val->step_detector = emb_func_int2.int2_step_detector; @@ -3011,10 +3164,10 @@ int32_t lsm6dsv80x_pin_int2_route_embedded_get(const stmdev_ctx_t *ctx, val->tilt = emb_func_int2.int2_tilt; /* FSM */ - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_INT2, (uint8_t *)&fsm_int2, 1); if (ret != 0) { - return ret; + goto exit; } val->fsm1 = fsm_int2.int2_fsm1; @@ -3027,10 +3180,10 @@ int32_t lsm6dsv80x_pin_int2_route_embedded_get(const stmdev_ctx_t *ctx, val->fsm8 = fsm_int2.int2_fsm8; /* MLC */ - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MLC_INT2, (uint8_t *)&mlc_int2, 1); + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MLC_INT2, (uint8_t *)&mlc_int2, 1); if (ret != 0) { - return ret; + goto exit; } val->mlc1 = mlc_int2.int2_mlc1; @@ -3042,6 +3195,9 @@ int32_t lsm6dsv80x_pin_int2_route_embedded_get(const stmdev_ctx_t *ctx, val->mlc7 = mlc_int2.int2_mlc7; val->mlc8 = mlc_int2.int2_mlc8; +exit: + ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); + return ret; } @@ -3078,6 +3234,11 @@ int32_t lsm6dsv80x_all_sources_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); if (ret != 0) @@ -3112,6 +3273,11 @@ int32_t lsm6dsv80x_all_sources_get(const stmdev_ctx_t *ctx, val->timestamp = status_reg.timestamp_endcount; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); if (ret != 0) @@ -3244,7 +3410,16 @@ int32_t lsm6dsv80x_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; - ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_INT_ACK_MASK, &val, 1); + ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_INT_ACK_MASK, &val, 1); + +exit: + ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; } @@ -3261,7 +3436,16 @@ int32_t lsm6dsv80x_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_INT_ACK_MASK, val, 1); + ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_INT_ACK_MASK, val, 1); + +exit: + ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; } @@ -3514,6 +3698,11 @@ int32_t lsm6dsv80x_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + if (ret != 0) + { + return ret; + } + *val = (int8_t)internal_freq.freq_fine; return ret; @@ -3540,6 +3729,11 @@ int32_t lsm6dsv80x_disable_embedded_function_set(const stmdev_ctx_t *ctx, uint8_ int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } + emb_func_cfg.emb_func_disable = val & 0x1U; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); @@ -3560,6 +3754,11 @@ int32_t lsm6dsv80x_disable_embedded_function_get(const stmdev_ctx_t *ctx, uint8_ int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = emb_func_cfg.emb_func_disable; return ret; @@ -3581,16 +3780,21 @@ int32_t lsm6dsv80x_emb_func_conv_set(const stmdev_ctx_t *ctx, lsm6dsv80x_emb_fun ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_SENSOR_CONV_EN, (uint8_t *)&conv_reg, 1); + if (ret != 0) + { + goto exit; + } conv_reg.xl_hg_conv_en = val.xl_hg_conv_en; conv_reg.gyro_conv_en = val.gyro_conv_en; conv_reg.temp_conv_en = val.temp_conv_en; conv_reg.ext_sensor_conv_en = val.ext_sensor_conv_en; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_SENSOR_CONV_EN, (uint8_t *)&conv_reg, 1); +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -3612,15 +3816,20 @@ int32_t lsm6dsv80x_emb_func_conv_get(const stmdev_ctx_t *ctx, lsm6dsv80x_emb_fun ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_SENSOR_CONV_EN, (uint8_t *)&conv_reg, 1); + if (ret != 0) + { + goto exit; + } val->xl_hg_conv_en = conv_reg.xl_hg_conv_en; val->gyro_conv_en = conv_reg.gyro_conv_en; val->temp_conv_en = conv_reg.temp_conv_en; val->ext_sensor_conv_en = conv_reg.ext_sensor_conv_en; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -3651,21 +3860,25 @@ int32_t lsm6dsv80x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } /* set page write */ ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_PAGE_RW, (uint8_t *)&page_rw, 1); - page_rw.page_read = PROPERTY_DISABLE; - page_rw.page_write = PROPERTY_ENABLE; - ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_PAGE_RW, (uint8_t *)&page_rw, 1); if (ret != 0) { goto exit; } + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_PAGE_RW, (uint8_t *)&page_rw, 1); /* select page */ ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -3723,6 +3936,10 @@ int32_t lsm6dsv80x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, /* unset page write */ ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -3763,6 +3980,10 @@ int32_t lsm6dsv80x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* set page write */ ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -3773,6 +3994,10 @@ int32_t lsm6dsv80x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* select page */ ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -3830,6 +4055,10 @@ int32_t lsm6dsv80x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t /* unset page write */ ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -4014,6 +4243,11 @@ int32_t lsm6dsv80x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl1.wtm; return ret; @@ -4126,6 +4360,11 @@ int32_t lsm6dsv80x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odr_chg_en; return ret; @@ -4148,6 +4387,10 @@ int32_t lsm6dsv80x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } fifo_ctrl2.fifo_compr_rt_en = val; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); if (ret != 0) @@ -4158,12 +4401,16 @@ int32_t lsm6dsv80x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; + } + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + if (ret != 0) + { + goto exit; } - - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); emb_func_en_b.fifo_compr_en = val; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -4184,6 +4431,10 @@ int32_t lsm6dsv80x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } *val = fifo_ctrl2.fifo_compr_rt_en; @@ -4198,7 +4449,7 @@ int32_t lsm6dsv80x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv80x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv80x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lsm6dsv80x_fifo_event_t val) { lsm6dsv80x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -4206,7 +4457,7 @@ int32_t lsm6dsv80x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) { - fifo_ctrl2.stop_on_wtm = val; + fifo_ctrl2.stop_on_wtm = (val == LSM6DSV80X_FIFO_EV_WTM) ? 1 : 0; ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); } @@ -4221,13 +4472,18 @@ int32_t lsm6dsv80x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv80x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv80x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lsm6dsv80x_fifo_event_t *val) { lsm6dsv80x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - *val = fifo_ctrl2.stop_on_wtm; + if (ret != 0) + { + return ret; + } + + *val = (fifo_ctrl2.stop_on_wtm == 1) ? LSM6DSV80X_FIFO_EV_WTM : LSM6DSV80X_FIFO_EV_FULL; return ret; } @@ -4480,6 +4736,11 @@ int32_t lsm6dsv80x_fifo_hg_xl_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_COUNTER_BDR_REG1, (uint8_t *)&cbdr_reg, 1); + if (ret != 0) + { + return ret; + } + *val = cbdr_reg.xl_hg_batch_en; return ret; @@ -4714,12 +4975,20 @@ int32_t lsm6dsv80x_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, int32_t lsm6dsv80x_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { - uint8_t buff[2]; + lsm6dsv80x_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsv80x_counter_bdr_reg2_t counter_bdr_reg2; int32_t ret; - buff[1] = (uint8_t)(val / 256U); - buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_COUNTER_BDR_REG1, (uint8_t *)&buff[0], 2); + ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU; + counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U; + ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); + } + return ret; } @@ -4744,8 +5013,8 @@ int32_t lsm6dsv80x_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, return ret; } - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + *val = (uint16_t)buff[0] & 0x3U; + *val = (*val * 256U) + (uint16_t)buff[1]; return ret; } @@ -4881,11 +5150,11 @@ int32_t lsm6dsv80x_fifo_out_raw_get(const stmdev_ctx_t *ctx, break; case 3: - val->tag = LSM6DSV80X_TIMESTAMP_TAG; + val->tag = LSM6DSV80X_TEMPERATURE_TAG; break; case 4: - val->tag = LSM6DSV80X_TEMPERATURE_TAG; + val->tag = LSM6DSV80X_TIMESTAMP_TAG; break; case 5: @@ -5017,13 +5286,18 @@ int32_t lsm6dsv80x_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } emb_func_fifo_en_a.step_counter_fifo_en = val; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -5045,12 +5319,17 @@ int32_t lsm6dsv80x_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_fifo_en_a.step_counter_fifo_en; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -5072,13 +5351,18 @@ int32_t lsm6dsv80x_fifo_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_b, 1); + ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret != 0) + { + goto exit; + } emb_func_fifo_en_b.fsm_fifo_en = val; - ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_b, 1); + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -5100,12 +5384,17 @@ int32_t lsm6dsv80x_fifo_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_b, 1); + ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_fifo_en_b.fsm_fifo_en; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -5127,13 +5416,18 @@ int32_t lsm6dsv80x_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } emb_func_fifo_en_a.mlc_fifo_en = val; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -5155,12 +5449,17 @@ int32_t lsm6dsv80x_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_fifo_en_a.mlc_fifo_en; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -5182,13 +5481,18 @@ int32_t lsm6dsv80x_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret != 0) + { + goto exit; + } emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -5210,12 +5514,17 @@ int32_t lsm6dsv80x_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -5237,13 +5546,18 @@ int32_t lsm6dsv80x_fifo_sh_batch_target_set(const stmdev_ctx_t *ctx, uint8_t idx ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_SENSOR_HUB_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_TGT0_CONFIG + idx * 3U, (uint8_t *)&tgt_config, 1); + if (ret != 0) + { + goto exit; + } tgt_config.batch_ext_sens_0_en = val; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_TGT0_CONFIG + idx * 3U, (uint8_t *)&tgt_config, 1); +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -5265,12 +5579,17 @@ int32_t lsm6dsv80x_fifo_sh_batch_target_get(const stmdev_ctx_t *ctx, uint8_t idx ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_SENSOR_HUB_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_TGT0_CONFIG + idx * 3U, (uint8_t *)&tgt_config, 1); + if (ret != 0) + { + goto exit; + } *val = tgt_config.batch_ext_sens_0_en; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -5291,16 +5610,23 @@ int32_t lsm6dsv80x_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) + { + goto exit; + } + + ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) { - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); - emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; - emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; - emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; - ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, - (uint8_t *)&emb_func_fifo_en_a, 1); + goto exit; } + emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; + emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; + emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, + (uint8_t *)&emb_func_fifo_en_a, 1); +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -5321,15 +5647,21 @@ int32_t lsm6dsv80x_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + goto exit; + } - val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; - val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; - val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; + ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret != 0) + { + goto exit; } + val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; + val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; + val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -5427,6 +5759,10 @@ int32_t lsm6dsv80x_filt_settling_mask_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } ctrl4.drdy_mask = val.drdy; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_CTRL4, (uint8_t *)&ctrl4, 1); if (ret != 0) @@ -5435,6 +5771,10 @@ int32_t lsm6dsv80x_filt_settling_mask_set(const stmdev_ctx_t *ctx, } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; emb_func_cfg.emb_func_irq_mask_xl_hg_settl = val.irq_xl_hg; emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; @@ -5464,6 +5804,10 @@ int32_t lsm6dsv80x_filt_settling_mask_get(const stmdev_ctx_t *ctx, ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL4, (uint8_t *)&ctrl4, 1); ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl; val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl; @@ -5595,7 +5939,12 @@ int32_t lsm6dsv80x_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) lsm6dsv80x_ctrl7_t ctrl7; int32_t ret; - ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL7, (uint8_t *)&ctrl7, 1); + ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7.lpf1_g_en; return ret; @@ -5724,6 +6073,11 @@ int32_t lsm6dsv80x_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.lpf2_xl_en; return ret; @@ -5766,6 +6120,11 @@ int32_t lsm6dsv80x_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.hp_slope_xl_en; return ret; @@ -5808,6 +6167,11 @@ int32_t lsm6dsv80x_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *v int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.xl_fastsettl_mode; return ret; @@ -5992,6 +6356,11 @@ int32_t lsm6dsv80x_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *v int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.hw_func_mask_xl_settl; return ret; @@ -6150,6 +6519,10 @@ int32_t lsm6dsv80x_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CTRL_STATUS, (uint8_t *)&ctrl_status, 1); + if (ret != 0) + { + return ret; + } *val = ctrl_status.fsm_wr_ctrl_status; @@ -6173,7 +6546,7 @@ int32_t lsm6dsv80x_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv80x_fsm_mode_t v ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); @@ -6225,7 +6598,14 @@ int32_t lsm6dsv80x_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv80x_fsm_mode_t * int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + if (ret != 0) + { + goto exit; + } + + ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); if (ret != 0) { @@ -6261,7 +6641,14 @@ int32_t lsm6dsv80x_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) buff[0] = (uint8_t)(val - (buff[1] * 256U)); ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2); + +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -6281,7 +6668,14 @@ int32_t lsm6dsv80x_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_LONG_COUNTER_L, &buff[0], 2); + +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); if (ret != 0) { @@ -6307,7 +6701,14 @@ int32_t lsm6dsv80x_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv80x_fsm_out_t *va int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_OUTS1, (uint8_t *)val, 8); + +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -6328,12 +6729,16 @@ int32_t lsm6dsv80x_fsm_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_ODR, (uint8_t *)&fsm_odr, 1); if (ret != 0) { goto exit; } + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + if (ret != 0) + { + goto exit; + } fsm_odr.fsm_odr = (uint8_t)val & 0x07U; ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FSM_ODR, (uint8_t *)&fsm_odr, 1); @@ -6358,7 +6763,14 @@ int32_t lsm6dsv80x_fsm_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); if (ret != 0) { @@ -6662,7 +7074,14 @@ int32_t lsm6dsv80x_sflp_game_gbias_set(const stmdev_ctx_t *ctx, gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k); ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_SFLP_GBIASX_INIT_L, (uint8_t *)&gbias_hf[0], 6); + +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -6851,8 +7270,12 @@ int32_t lsm6dsv80x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_ln_pg_read(ctx, LSM6DSV80X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret != 0) + { + return ret; + } ext_cfg_a.ext_z_axis = (uint8_t)val & 0x07U; - ret += lsm6dsv80x_ln_pg_write(ctx, LSM6DSV80X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + ret = lsm6dsv80x_ln_pg_write(ctx, LSM6DSV80X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); return ret; } @@ -7083,13 +7506,18 @@ int32_t lsm6dsv80x_xl_hg_peak_tracking_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); + if (ret != 0) + { + goto exit; + } emb_func_init_b.pt_init = val; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -7111,12 +7539,17 @@ int32_t lsm6dsv80x_xl_hg_peak_tracking_get(const stmdev_ctx_t *ctx, uint8_t *val ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_init_b.pt_init; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -7256,7 +7689,10 @@ int32_t lsm6dsv80x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t * ret = lsm6dsv80x_ln_pg_read(ctx, LSM6DSV80X_EMB_ADV_PG_1 + LSM6DSV80X_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); - *val = fsm_programs.fsm_n_prog; + if (ret == 0) + { + *val = fsm_programs.fsm_n_prog; + } return ret; } @@ -7335,6 +7771,10 @@ int32_t lsm6dsv80x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); if (ret != 0) @@ -7343,6 +7783,10 @@ int32_t lsm6dsv80x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } free_fall.ff_dur = (uint8_t)val & 0x1FU; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_FREE_FALL, (uint8_t *)&free_fall, 1); @@ -7365,6 +7809,10 @@ int32_t lsm6dsv80x_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -7485,6 +7933,10 @@ int32_t lsm6dsv80x_mlc_set(const stmdev_ctx_t *ctx, lsm6dsv80x_mlc_mode_t val) int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); if (ret != 0) @@ -7534,6 +7986,10 @@ int32_t lsm6dsv80x_mlc_get(const stmdev_ctx_t *ctx, lsm6dsv80x_mlc_mode_t *val) int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); if (ret != 0) @@ -7579,6 +8035,10 @@ int32_t lsm6dsv80x_mlc_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_MLC_ODR, (uint8_t *)&mlc_odr, 1); if (ret != 0) { @@ -7845,6 +8305,11 @@ int32_t lsm6dsv80x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = tap_ths_6d.d4d_en; return ret; @@ -8012,6 +8477,11 @@ int32_t lsm6dsv80x_sh_controller_interface_pull_up_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.shub_pu_en; return ret; @@ -8031,7 +8501,12 @@ int32_t lsm6dsv80x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_SENSOR_HUB_1, val, len); +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -8052,12 +8527,16 @@ int32_t lsm6dsv80x_sh_target_connected_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_SENSOR_HUB_MEM_BANK); - ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); if (ret != 0) { goto exit; } + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } controller_config.aux_sens_on = (uint8_t)val & 0x3U; ret = lsm6dsv80x_write_reg(ctx, LSM6DSV80X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); @@ -8158,10 +8637,19 @@ int32_t lsm6dsv80x_sh_controller_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } *val = controller_config.controller_on; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -8210,10 +8698,16 @@ int32_t lsm6dsv80x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } *val = controller_config.pass_through_mode; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -8234,6 +8728,7 @@ int32_t lsm6dsv80x_sh_syncro_mode_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); if (ret != 0) { @@ -8403,9 +8898,14 @@ int32_t lsm6dsv80x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv80x_read_reg(ctx, LSM6DSV80X_CONTROLLER_CONFIG, (uint8_t *)&controller_config, 1); + if (ret != 0) + { + goto exit; + } *val = controller_config.rst_controller_regs; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -8431,7 +8931,7 @@ int32_t lsm6dsv80x_sh_cfg_write(const stmdev_ctx_t *ctx, ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_SENSOR_HUB_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } reg.target0_add = val->tgt0_add; @@ -8669,6 +9169,11 @@ int32_t lsm6dsv80x_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.sdo_pu_en; return ret; @@ -8711,6 +9216,11 @@ int32_t lsm6dsv80x_pad_strength_get(const stmdev_ctx_t *ctx, lsm6dsv80x_pad_stre int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + switch (pin_ctrl.io_pad_strength) { case 0: @@ -8889,6 +9399,11 @@ int32_t lsm6dsv80x_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.sda_pu_en; return ret; @@ -8924,13 +9439,18 @@ int32_t lsm6dsv80x_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret != 0) + { + goto exit; + } emb_func_en_a.sign_motion_en = val; ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -8952,12 +9472,17 @@ int32_t lsm6dsv80x_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_en_a.sign_motion_en; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -8994,7 +9519,7 @@ int32_t lsm6dsv80x_stpcnt_mode_set(const stmdev_ctx_t *ctx, ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); @@ -9021,6 +9546,10 @@ int32_t lsm6dsv80x_stpcnt_mode_set(const stmdev_ctx_t *ctx, { ret = lsm6dsv80x_ln_pg_read(ctx, LSM6DSV80X_EMB_ADV_PG_1 + LSM6DSV80X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + if (ret != 0) + { + return ret; + } pedo_cmd_reg.fp_rejection_en = val.false_step_rej; ret += lsm6dsv80x_ln_pg_write(ctx, LSM6DSV80X_EMB_ADV_PG_1 + LSM6DSV80X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); @@ -9108,7 +9637,7 @@ int32_t lsm6dsv80x_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); @@ -9142,12 +9671,17 @@ int32_t lsm6dsv80x_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_src.pedo_rst_step; +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -9193,6 +9727,10 @@ int32_t lsm6dsv80x_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv80x_ln_pg_read(ctx, LSM6DSV80X_EMB_ADV_PG_1 + LSM6DSV80X_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + if (ret != 0) + { + return ret; + } *val = pedo_deb_steps_conf.deb_step; return ret; @@ -9273,7 +9811,7 @@ int32_t lsm6dsv80x_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); @@ -9308,12 +9846,50 @@ int32_t lsm6dsv80x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret != 0) + { + goto exit; + } *val = emb_func_en_a.sflp_game_en; +exit: + ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset SFLP Game Rotation Vector logic (6x). + * + * @param ctx read / write interface definitions + * @param val 1: reset, 0: stop reset procedure + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv80x_sflp_game_rotation_reset(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv80x_emb_func_init_a_t emb_func_init_a; + int32_t ret; + + ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } + + ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_EMB_FUNC_INIT_A, (uint8_t *)&emb_func_init_a, 1); + if (ret != 0) + { + goto exit; + } + emb_func_init_a.sflp_game_init = val; + ret += lsm6dsv80x_write_reg(ctx, LSM6DSV80X_EMB_FUNC_INIT_A, (uint8_t *)&emb_func_init_a, 1); + +exit: ret += lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_MAIN_MEM_BANK); return ret; @@ -9336,7 +9912,7 @@ int32_t lsm6dsv80x_sflp_data_rate_set(const stmdev_ctx_t *ctx, ret = lsm6dsv80x_mem_bank_set(ctx, LSM6DSV80X_EMBED_FUNC_MEM_BANK); if (ret != 0) { - return ret; + goto exit; } ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); @@ -9878,6 +10454,11 @@ int32_t lsm6dsv80x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv80x_read_reg(ctx, LSM6DSV80X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + *val = functions_enable.timestamp_en; return ret; diff --git a/sensor/stmemsc/lsm6dsv80x_STdC/driver/lsm6dsv80x_reg.h b/sensor/stmemsc/lsm6dsv80x_STdC/driver/lsm6dsv80x_reg.h index f606153..6805711 100644 --- a/sensor/stmemsc/lsm6dsv80x_STdC/driver/lsm6dsv80x_reg.h +++ b/sensor/stmemsc/lsm6dsv80x_STdC/driver/lsm6dsv80x_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -2548,7 +2550,7 @@ typedef struct #endif /* DRV_BYTE_ORDER */ } lsm6dsv80x_emb_func_init_b_t; -#define LSM6DSV80X_EMB_FUNC_SENSOR_CONV_EN 0x67U +#define LSM6DSV80X_EMB_FUNC_SENSOR_CONV_EN 0x6EU typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN @@ -3792,8 +3794,9 @@ float_t lsm6dsv80x_from_fs32_to_mg(int16_t lsb); float_t lsm6dsv80x_from_fs64_to_mg(int16_t lsb); float_t lsm6dsv80x_from_fs80_to_mg(int16_t lsb); -float_t lsm6dsv80x_from_fs500_to_mdps(int16_t lsb); +float_t lsm6dsv80x_from_fs125_to_mdps(int16_t lsb); float_t lsm6dsv80x_from_fs250_to_mdps(int16_t lsb); +float_t lsm6dsv80x_from_fs500_to_mdps(int16_t lsb); float_t lsm6dsv80x_from_fs1000_to_mdps(int16_t lsb); float_t lsm6dsv80x_from_fs2000_to_mdps(int16_t lsb); float_t lsm6dsv80x_from_fs4000_to_mdps(int16_t lsb); @@ -3808,6 +3811,8 @@ float_t lsm6dsv80x_from_gbias_lsb_to_mdps(int16_t lsb); float_t lsm6dsv80x_from_gravity_lsb_to_mg(int16_t lsb); float_t lsm6dsv80x_from_quaternion_lsb_to_float(uint16_t lsb); +uint32_t lsm6dsv80x_from_f16_to_f32(uint16_t val); + int32_t lsm6dsv80x_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t lsm6dsv80x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); @@ -3873,16 +3878,26 @@ typedef enum LSM6DSV80X_ODR_HA01_AT_2000Hz = 0x1A, LSM6DSV80X_ODR_HA01_AT_4000Hz = 0x1B, LSM6DSV80X_ODR_HA01_AT_8000Hz = 0x1C, - LSM6DSV80X_ODR_HA02_AT_13Hz = 0x23, - LSM6DSV80X_ODR_HA02_AT_26Hz = 0x24, - LSM6DSV80X_ODR_HA02_AT_52Hz = 0x25, - LSM6DSV80X_ODR_HA02_AT_104Hz = 0x26, - LSM6DSV80X_ODR_HA02_AT_208Hz = 0x27, - LSM6DSV80X_ODR_HA02_AT_417Hz = 0x28, - LSM6DSV80X_ODR_HA02_AT_833Hz = 0x29, - LSM6DSV80X_ODR_HA02_AT_1667Hz = 0x2A, - LSM6DSV80X_ODR_HA02_AT_3333Hz = 0x2B, - LSM6DSV80X_ODR_HA02_AT_6667Hz = 0x2C, + LSM6DSV80X_ODR_HA02_AT_12Hz5 = 0x23, + LSM6DSV80X_ODR_HA02_AT_25Hz = 0x24, + LSM6DSV80X_ODR_HA02_AT_50Hz = 0x25, + LSM6DSV80X_ODR_HA02_AT_100Hz = 0x26, + LSM6DSV80X_ODR_HA02_AT_200Hz = 0x27, + LSM6DSV80X_ODR_HA02_AT_400Hz = 0x28, + LSM6DSV80X_ODR_HA02_AT_800Hz = 0x29, + LSM6DSV80X_ODR_HA02_AT_1600Hz = 0x2A, + LSM6DSV80X_ODR_HA02_AT_3200Hz = 0x2B, + LSM6DSV80X_ODR_HA02_AT_6400Hz = 0x2C, + LSM6DSV80X_ODR_HA03_AT_13Hz = 0x33, + LSM6DSV80X_ODR_HA03_AT_26Hz = 0x34, + LSM6DSV80X_ODR_HA03_AT_52Hz = 0x35, + LSM6DSV80X_ODR_HA03_AT_104Hz = 0x36, + LSM6DSV80X_ODR_HA03_AT_208Hz = 0x37, + LSM6DSV80X_ODR_HA03_AT_417Hz = 0x38, + LSM6DSV80X_ODR_HA03_AT_833Hz = 0x39, + LSM6DSV80X_ODR_HA03_AT_1667Hz = 0x3A, + LSM6DSV80X_ODR_HA03_AT_3333Hz = 0x3B, + LSM6DSV80X_ODR_HA03_AT_6667Hz = 0x3C, } lsm6dsv80x_data_rate_t; int32_t lsm6dsv80x_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv80x_data_rate_t val); @@ -4264,8 +4279,14 @@ int32_t lsm6dsv80x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, int32_t lsm6dsv80x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv80x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv80x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); +typedef enum +{ + LSM6DSV80X_FIFO_EV_WTM = 0x0, + LSM6DSV80X_FIFO_EV_FULL = 0x1, +} lsm6dsv80x_fifo_event_t; + +int32_t lsm6dsv80x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lsm6dsv80x_fifo_event_t val); +int32_t lsm6dsv80x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lsm6dsv80x_fifo_event_t *val); typedef enum { @@ -4932,6 +4953,8 @@ int32_t lsm6dsv80x_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); int32_t lsm6dsv80x_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val); int32_t lsm6dsv80x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv80x_sflp_game_rotation_reset(const stmdev_ctx_t *ctx, uint8_t val); + typedef struct { float_t gbias_x; /* dps */ @@ -5093,5 +5116,3 @@ int32_t lsm6dsv80x_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, #endif #endif /*LSM6DSV80X_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.c b/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.c index 5fd09c1..92fdb33 100644 --- a/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.c +++ b/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.c @@ -6,17 +6,17 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ +#include #include "lsm6dsv_reg.h" /** @@ -288,6 +288,11 @@ int32_t lsm6dsv_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.usr_off_on_out; return ret; @@ -434,9 +439,9 @@ int32_t lsm6dsv_reset_set(const stmdev_ctx_t *ctx, lsm6dsv_reset_t val) return ret; } - ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; - ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; - func_cfg_access.sw_por = (uint8_t)val & 0x01U; + ctrl3.boot = (val == LSM6DSV_RESTORE_CAL_PARAM) ? 1 : 0; + ctrl3.sw_reset = (val == LSM6DSV_RESTORE_CTRL_REGS) ? 1 : 0; + func_cfg_access.sw_por = (val == LSM6DSV_GLOBAL_RST) ? 1 : 0; ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); ret += lsm6dsv_write_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); @@ -609,6 +614,11 @@ int32_t lsm6dsv_xl_data_rate_set(const stmdev_ctx_t *ctx, if (sel != 0U) { ret += lsm6dsv_read_reg(ctx, LSM6DSV_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } + haodr.haodr_sel = sel; ret += lsm6dsv_write_reg(ctx, LSM6DSV_HAODR_CFG, (uint8_t *)&haodr, 1); } @@ -921,6 +931,10 @@ int32_t lsm6dsv_gy_data_rate_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } ctrl2.odr_g = (uint8_t)val & 0x0Fu; ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1); @@ -933,6 +947,11 @@ int32_t lsm6dsv_gy_data_rate_set(const stmdev_ctx_t *ctx, if (sel != 0U) { ret += lsm6dsv_read_reg(ctx, LSM6DSV_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } + haodr.haodr_sel = sel; ret += lsm6dsv_write_reg(ctx, LSM6DSV_HAODR_CFG, (uint8_t *)&haodr, 1); } @@ -1252,6 +1271,11 @@ int32_t lsm6dsv_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.if_inc; return ret; @@ -1295,6 +1319,11 @@ int32_t lsm6dsv_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.bdu; return ret; @@ -1343,6 +1372,11 @@ int32_t lsm6dsv_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + if (ret != 0) + { + return ret; + } + *val = odr_trig.odr_trig_nodr; return ret; @@ -1388,6 +1422,10 @@ int32_t lsm6dsv_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4.drdy_pulsed) { @@ -1423,14 +1461,18 @@ int32_t lsm6dsv_interrupt_enable_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); - func.interrupts_enable = val.enable; - ret += lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); if (ret != 0) { return ret; } + func.interrupts_enable = val.enable; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); - ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&cfg, 1); + ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&cfg, 1); + if (ret != 0) + { + return ret; + } cfg.lir = val.lir; ret += lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&cfg, 1); @@ -1653,6 +1695,11 @@ int32_t lsm6dsv_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8.xl_dualc_en; return ret; @@ -1952,12 +1999,6 @@ int32_t lsm6dsv_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsv_md1_cfg_t md1_cfg; int32_t ret; - /* not available on INT1 */ - if (val->drdy_temp == 1) - { - return -1; - } - ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); if (ret != 0) { @@ -1972,12 +2013,8 @@ int32_t lsm6dsv_pin_int1_route_set(const stmdev_ctx_t *ctx, int1_ctrl.int1_cnt_bdr = val->cnt_bdr; ret = lsm6dsv_write_reg(ctx, LSM6DSV_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - if (ret != 0) - { - return ret; - } - ret = lsm6dsv_read_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1); + ret += lsm6dsv_read_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1); if (ret != 0) { return ret; @@ -2012,7 +2049,10 @@ int32_t lsm6dsv_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsv_md1_cfg_t md1_cfg; int32_t ret; + memset(val, 0x0, sizeof(lsm6dsv_pin_int_route_t)); + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + ret += lsm6dsv_read_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1); if (ret != 0) { return ret; @@ -2025,12 +2065,6 @@ int32_t lsm6dsv_pin_int1_route_get(const stmdev_ctx_t *ctx, val->fifo_full = int1_ctrl.int1_fifo_full; val->cnt_bdr = int1_ctrl.int1_cnt_bdr; - ret = lsm6dsv_read_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret != 0) - { - return ret; - } - val->shub = md1_cfg.int1_shub; val->emb_func = md1_cfg.int1_emb_func; val->sixd = md1_cfg.int1_6d; @@ -2059,6 +2093,8 @@ int32_t lsm6dsv_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsv_md2_cfg_t md2_cfg; int32_t ret; + memset(val, 0x0, sizeof(lsm6dsv_pin_int_route_t)); + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); if (ret != 0) { @@ -2075,12 +2111,12 @@ int32_t lsm6dsv_pin_int2_route_set(const stmdev_ctx_t *ctx, int2_ctrl.int2_emb_func_endop = val->emb_func_endop; ret = lsm6dsv_write_reg(ctx, LSM6DSV_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + + ret += lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); if (ret != 0) { return ret; } - - ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); ctrl4.int2_drdy_temp = val->drdy_temp; ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); if (ret != 0) @@ -2181,11 +2217,13 @@ int32_t lsm6dsv_emb_pin_int1_route_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + return ret; } + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + if (ret == 0) { emb_func_int1.int1_tilt = val->tilt; @@ -2222,11 +2260,13 @@ int32_t lsm6dsv_emb_pin_int1_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + return ret; } + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + if (ret == 0) { val->tilt = emb_func_int1.int1_tilt; @@ -2255,11 +2295,13 @@ int32_t lsm6dsv_emb_pin_int2_route_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + return ret; } + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + if (ret == 0) { emb_func_int2.int2_tilt = val->tilt; @@ -2296,11 +2338,13 @@ int32_t lsm6dsv_emb_pin_int2_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + return ret; } + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + if (ret == 0) { val->tilt = emb_func_int2.int2_tilt; @@ -2327,10 +2371,15 @@ int32_t lsm6dsv_embedded_int_cfg_set(const stmdev_ctx_t *ctx, lsm6dsv_embedded_i int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + return ret; + } + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret == 0) + { switch (val) { case LSM6DSV_INT_LATCH_DISABLE: @@ -2366,10 +2415,15 @@ int32_t lsm6dsv_embedded_int_cfg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret == 0) + if (ret != 0) { - ret = lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + return ret; + } + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret == 0) + { if (page_rw.emb_func_lir == 0U) { *val = LSM6DSV_INT_LATCH_DISABLE; @@ -2413,6 +2467,10 @@ int32_t lsm6dsv_embedded_status_get(const stmdev_ctx_t *ctx, /* embedded func */ ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); if (ret != 0) @@ -2461,18 +2519,14 @@ int32_t lsm6dsv_all_sources_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); - functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; - ret += lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); if (ret != 0) { return ret; } + functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); - ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_STATUS1, (uint8_t *)&buff, 4); - if (ret != 0) - { - return ret; - } + ret += lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_STATUS1, (uint8_t *)&buff, 4); bytecpy((uint8_t *)&fifo_status2, &buff[1]); bytecpy((uint8_t *)&all_int_src, &buff[2]); @@ -2552,8 +2606,11 @@ int32_t lsm6dsv_all_sources_get(const stmdev_ctx_t *ctx, /* embedded func */ ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, 1); - ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + if (ret == 0) + { + ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, 1); + ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); if (ret != 0) { @@ -2822,6 +2879,11 @@ int32_t lsm6dsv_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + if (ret != 0) + { + return ret; + } + *val = (int8_t)internal_freq.freq_fine; return ret; @@ -2857,6 +2919,10 @@ int32_t lsm6dsv_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, /* set page write */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_ENABLE; ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -2867,6 +2933,10 @@ int32_t lsm6dsv_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, /* select page */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -2884,7 +2954,7 @@ int32_t lsm6dsv_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, goto exit; } - for (i = 0; ((i < len) && (ret == 0)); i++) + for (i = 0; i < len; i++) { ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_VALUE, &buf[i], 1); if (ret != 0) @@ -2924,6 +2994,10 @@ int32_t lsm6dsv_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, /* unset page write */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -2971,6 +3045,10 @@ int32_t lsm6dsv_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *b /* set page write */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -2981,6 +3059,10 @@ int32_t lsm6dsv_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *b /* select page */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); @@ -3038,6 +3120,10 @@ int32_t lsm6dsv_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *b /* unset page write */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -3419,6 +3505,11 @@ int32_t lsm6dsv_eis_gy_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl_eis.g_eis_on_g_ois_out_reg; return ret; @@ -3536,6 +3627,11 @@ int32_t lsm6dsv_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl1.wtm; return ret; @@ -3578,6 +3674,11 @@ int32_t lsm6dsv_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; return ret; @@ -3690,6 +3791,11 @@ int32_t lsm6dsv_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odr_chg_en; return ret; @@ -3712,6 +3818,10 @@ int32_t lsm6dsv_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } fifo_ctrl2.fifo_compr_rt_en = val; ret += lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); if (ret != 0) @@ -3726,8 +3836,11 @@ int32_t lsm6dsv_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); - emb_func_en_b.fifo_compr_en = val; - ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + if (ret == 0) + { + emb_func_en_b.fifo_compr_en = val; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); return ret; @@ -3748,6 +3861,10 @@ int32_t lsm6dsv_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } *val = fifo_ctrl2.fifo_compr_rt_en; @@ -3762,7 +3879,7 @@ int32_t lsm6dsv_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_event_t val) { lsm6dsv_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3770,7 +3887,7 @@ int32_t lsm6dsv_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) { - fifo_ctrl2.stop_on_wtm = val; + fifo_ctrl2.stop_on_wtm = (val == LSM6DSV_FIFO_EV_WTM) ? 1 : 0; ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); } @@ -3785,13 +3902,16 @@ int32_t lsm6dsv_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_event_t *val) { lsm6dsv_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - *val = fifo_ctrl2.stop_on_wtm; + if (ret == 0) + { + *val = (fifo_ctrl2.stop_on_wtm == 1) ? LSM6DSV_FIFO_EV_WTM : LSM6DSV_FIFO_EV_FULL; + } return ret; } @@ -4124,6 +4244,11 @@ int32_t lsm6dsv_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl4.g_eis_fifo_en; return ret; @@ -4577,8 +4702,11 @@ int32_t lsm6dsv_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); - emb_func_fifo_en_a.step_counter_fifo_en = val; - ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + if (ret == 0) + { + emb_func_fifo_en_a.step_counter_fifo_en = val; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -4605,7 +4733,10 @@ int32_t lsm6dsv_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) } ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); - *val = emb_func_fifo_en_a.step_counter_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_a.step_counter_fifo_en; + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -4632,8 +4763,11 @@ int32_t lsm6dsv_fifo_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, ui } ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); - slv_config.batch_ext_sens_0_en = val; - ret += lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); + if (ret == 0) + { + slv_config.batch_ext_sens_0_en = val; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -4660,7 +4794,10 @@ int32_t lsm6dsv_fifo_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, ui } ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); - *val = slv_config.batch_ext_sens_0_en; + if (ret == 0) + { + *val = slv_config.batch_ext_sens_0_en; + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -4685,6 +4822,9 @@ int32_t lsm6dsv_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + if (ret == 0) + { emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; @@ -4715,7 +4855,9 @@ int32_t lsm6dsv_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); - + } + if (ret == 0) + { val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; @@ -4819,6 +4961,10 @@ int32_t lsm6dsv_filt_settling_mask_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } ctrl4.drdy_mask = val.drdy; ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); if (ret != 0) @@ -4827,6 +4973,10 @@ int32_t lsm6dsv_filt_settling_mask_set(const stmdev_ctx_t *ctx, } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); @@ -4836,6 +4986,10 @@ int32_t lsm6dsv_filt_settling_mask_set(const stmdev_ctx_t *ctx, } ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + if (ret != 0) + { + return ret; + } ui_int_ois.drdy_mask_ois = val.ois_drdy; ret += lsm6dsv_write_reg(ctx, LSM6DSV_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); @@ -4861,6 +5015,10 @@ int32_t lsm6dsv_filt_settling_mask_get(const stmdev_ctx_t *ctx, ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + if (ret != 0) + { + return ret; + } val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl; val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl; @@ -4910,6 +5068,11 @@ int32_t lsm6dsv_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + if (ret != 0) + { + return ret; + } + val->ois_drdy = spi2_int_ois.drdy_mask_ois; return ret; @@ -5039,6 +5202,11 @@ int32_t lsm6dsv_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7.lpf1_g_en; return ret; @@ -5167,6 +5335,11 @@ int32_t lsm6dsv_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.lpf2_xl_en; return ret; @@ -5209,6 +5382,11 @@ int32_t lsm6dsv_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.hp_slope_xl_en; return ret; @@ -5251,6 +5429,11 @@ int32_t lsm6dsv_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.xl_fastsettl_mode; return ret; @@ -5435,6 +5618,11 @@ int32_t lsm6dsv_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.hw_func_mask_xl_settl; return ret; @@ -5815,6 +6003,10 @@ int32_t lsm6dsv_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_STATUS, (uint8_t *)&ctrl_status, 1); + if (ret != 0) + { + return ret; + } *val = ctrl_status.fsm_wr_ctrl_status; @@ -5890,6 +6082,10 @@ int32_t lsm6dsv_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t *val) int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); if (ret != 0) @@ -5926,6 +6122,10 @@ int32_t lsm6dsv_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) buff[0] = (uint8_t)(val - (buff[1] * 256U)); ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv_write_reg(ctx, LSM6DSV_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -5946,6 +6146,10 @@ int32_t lsm6dsv_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_LONG_COUNTER_L, &buff[0], 2); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); if (ret != 0) @@ -5972,6 +6176,10 @@ int32_t lsm6dsv_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_out_t *val) int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_OUTS1, (uint8_t *)val, 8); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -6023,7 +6231,10 @@ int32_t lsm6dsv_fsm_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ODR, (uint8_t *)&fsm_odr, 1); + if (ret == 0) + { + ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); if (ret != 0) { @@ -6299,41 +6510,90 @@ int32_t lsm6dsv_sflp_game_gbias_set(const stmdev_ctx_t *ctx, /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, conf_saved, 2); + if (ret != 0) + { + return ret; + } + ret += lsm6dsv_xl_mode_set(ctx, LSM6DSV_XL_HIGH_PERFORMANCE_MD); ret += lsm6dsv_gy_mode_set(ctx, LSM6DSV_GY_HIGH_PERFORMANCE_MD); if (((uint8_t)conf_saved[0] & 0x0FU) == (uint8_t)LSM6DSV_ODR_OFF) { ret += lsm6dsv_xl_data_rate_set(ctx, LSM6DSV_ODR_AT_120Hz); } + if (ret != 0) + { + goto exit; + } /* Make sure to turn the sensor-hub master off */ ret += lsm6dsv_sh_master_get(ctx, &master_config); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv_sh_master_set(ctx, 0); + if (ret != 0) + { + goto exit; + } /* disable algos */ ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, emb_func_en_saved, 2); - ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, reg_zero, 2); - do + if (ret == 0) { - ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EXEC_STATUS, - (uint8_t *)&emb_func_sts, 1); - } while (emb_func_sts.emb_func_endop != 1U); + ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, reg_zero, 2); + } + if (ret == 0) + { + do + { + ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1U); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + if (ret != 0) + { + goto exit; + } // enable gbias setting ret += lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); - ctrl10.emb_func_debug = 1; - ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret == 0) + { + ctrl10.emb_func_debug = 1; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); + } + if (ret != 0) + { + goto exit; + } /* enable algos */ ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - emb_func_en_saved[0] |= 0x02U; /* force SFLP GAME en */ - ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, emb_func_en_saved, - 2); + if (ret == 0) + { + emb_func_en_saved[0] |= 0x02U; /* force SFLP GAME en */ + ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + if (ret != 0) + { + goto exit; + } ret += lsm6dsv_xl_full_scale_get(ctx, &xl_fs); + if (ret != 0) + { + goto exit; + } /* Read XL data */ do @@ -6341,9 +6601,17 @@ int32_t lsm6dsv_sflp_game_gbias_set(const stmdev_ctx_t *ctx, ret += lsm6dsv_flag_data_ready_get(ctx, &drdy); } while (drdy.drdy_xl != 1U); ret += lsm6dsv_acceleration_raw_get(ctx, xl_data); + if (ret != 0) + { + goto exit; + } /* force sflp initialization */ ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + goto exit; + } for (i = 0; i < 3U; i++) { j = 0; @@ -6368,21 +6636,34 @@ int32_t lsm6dsv_sflp_game_gbias_set(const stmdev_ctx_t *ctx, 1); } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + if (ret != 0) + { + goto exit; + } // wait end_op (and at least 30 us) ctx->mdelay(1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + goto exit; + } do { ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_sts, 1); } while (emb_func_sts.emb_func_endop != 1U); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); + if (ret != 0) + { + goto exit; + } /* write gbias in embedded advanced features registers */ ret += lsm6dsv_ln_pg_write(ctx, LSM6DSV_SFLP_GAME_GBIASX_L, (uint8_t *)gbias_hf, 6); +exit: /* reload previous sensor configuration */ ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL1, conf_saved, 2); @@ -6579,6 +6860,10 @@ int32_t lsm6dsv_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret != 0) + { + return ret; + } ext_cfg_a.ext_z_axis = (uint8_t)val & 0x07U; ret += lsm6dsv_ln_pg_write(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); @@ -6881,6 +7166,11 @@ int32_t lsm6dsv_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + if (ret != 0) + { + return ret; + } + *val = fsm_programs.fsm_n_prog; return ret; @@ -6960,14 +7250,18 @@ int32_t lsm6dsv_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; - ret += lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); if (ret != 0) { return ret; } + wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - ret = lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1); + ret += lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } free_fall.ff_dur = (uint8_t)val & 0x1FU; ret += lsm6dsv_write_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1); @@ -6990,6 +7284,10 @@ int32_t lsm6dsv_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -7194,6 +7492,11 @@ int32_t lsm6dsv_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + *val = (int8_t)func_cfg_access.spi2_reset; return ret; @@ -7236,6 +7539,11 @@ int32_t lsm6dsv_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.ois_pu_dis; return ret; @@ -7414,6 +7722,11 @@ int32_t lsm6dsv_ois_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } + *val = ui_ctrl1_ois.spi2_read_en; return ret; @@ -7732,6 +8045,11 @@ int32_t lsm6dsv_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + *val = tap_ths_6d.d4d_en; return ret; @@ -7849,6 +8167,11 @@ int32_t lsm6dsv_i3c_int_en_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl5.int_en_i3c; return ret; @@ -7976,6 +8299,11 @@ int32_t lsm6dsv_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.shub_pu_en; return ret; @@ -7995,7 +8323,10 @@ int32_t lsm6dsv_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); - ret += lsm6dsv_read_reg(ctx, LSM6DSV_SENSOR_HUB_1, val, len); + if (ret == 0) + { + ret += lsm6dsv_read_reg(ctx, LSM6DSV_SENSOR_HUB_1, val, len); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); return ret; @@ -8046,7 +8377,10 @@ int32_t lsm6dsv_sh_slave_connected_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); - ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret == 0) + { + ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); if (ret != 0) { @@ -8122,9 +8456,16 @@ int32_t lsm6dsv_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); - *val = master_config.master_on; + if (ret == 0) + { + *val = master_config.master_on; + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -8174,9 +8515,15 @@ int32_t lsm6dsv_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); - ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret == 0) + { + ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } - *val = master_config.pass_through_mode; + if (ret == 0) + { + *val = master_config.pass_through_mode; + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -8228,6 +8575,10 @@ int32_t lsm6dsv_sh_syncro_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); if (ret != 0) @@ -8298,7 +8649,10 @@ int32_t lsm6dsv_sh_write_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); - ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret == 0) + { + ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); if (ret != 0) { @@ -8366,9 +8720,16 @@ int32_t lsm6dsv_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); - *val = master_config.rst_master_regs; + if (ret == 0) + { + *val = master_config.rst_master_regs; + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -8467,6 +8828,10 @@ int32_t lsm6dsv_sh_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); if (ret != 0) @@ -8633,6 +8998,11 @@ int32_t lsm6dsv_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.sdo_pu_en; return ret; @@ -8797,6 +9167,11 @@ int32_t lsm6dsv_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.sda_pu_en; return ret; @@ -8896,8 +9271,11 @@ int32_t lsm6dsv_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - emb_func_en_a.sign_motion_en = val; - ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret == 0) + { + emb_func_en_a.sign_motion_en = val; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -8924,7 +9302,10 @@ int32_t lsm6dsv_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - *val = emb_func_en_a.sign_motion_en; + if (ret == 0) + { + *val = emb_func_en_a.sign_motion_en; + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -8993,6 +9374,10 @@ int32_t lsm6dsv_stpcnt_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); if (ret != 0) @@ -9017,6 +9402,10 @@ int32_t lsm6dsv_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } ret += lsm6dsv_read_reg(ctx, LSM6DSV_STEP_COUNTER_L, &buff[0], 2); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); if (ret != 0) @@ -9084,7 +9473,10 @@ int32_t lsm6dsv_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); - *val = emb_func_src.pedo_rst_step; + if (ret == 0) + { + *val = emb_func_src.pedo_rst_step; + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -9131,7 +9523,10 @@ int32_t lsm6dsv_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); - *val = pedo_deb_steps_conf.deb_step; + if (ret == 0) + { + *val = pedo_deb_steps_conf.deb_step; + } return ret; } @@ -9249,7 +9644,10 @@ int32_t lsm6dsv_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val) } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - *val = emb_func_en_a.sflp_game_en; + if (ret == 0) + { + *val = emb_func_en_a.sflp_game_en; + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -9306,7 +9704,10 @@ int32_t lsm6dsv_sflp_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv_read_reg(ctx, LSM6DSV_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + if (ret == 0) + { + ret += lsm6dsv_read_reg(ctx, LSM6DSV_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); if (ret != 0) { @@ -9703,8 +10104,11 @@ int32_t lsm6dsv_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - emb_func_en_a.tilt_en = val; - ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret == 0) + { + emb_func_en_a.tilt_en = val; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -9731,7 +10135,10 @@ int32_t lsm6dsv_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - *val = emb_func_en_a.tilt_en; + if (ret == 0) + { + *val = emb_func_en_a.tilt_en; + } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -9815,7 +10222,10 @@ int32_t lsm6dsv_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); - *val = functions_enable.timestamp_en; + if (ret == 0) + { + *val = functions_enable.timestamp_en; + } return ret; } diff --git a/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.h b/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.h index 727cd1a..8b9829a 100644 --- a/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.h +++ b/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -3704,10 +3706,11 @@ int32_t lsm6dsv_xl_offset_mg_get(const stmdev_ctx_t *ctx, typedef enum { - LSM6DSV_READY = 0x0, - LSM6DSV_GLOBAL_RST = 0x1, - LSM6DSV_RESTORE_CAL_PARAM = 0x2, - LSM6DSV_RESTORE_CTRL_REGS = 0x4, + LSM6DSV_READY = 0x0, /* No active reset in progress */ + LSM6DSV_GLOBAL_RST = 0x1, /* Complete reset: boot, software reset, + embedded functions, and internal filters */ + LSM6DSV_RESTORE_CAL_PARAM = 0x2, /* Reload trimming parameters */ + LSM6DSV_RESTORE_CTRL_REGS = 0x4, /* Reset control registers to default values */ } lsm6dsv_reset_t; int32_t lsm6dsv_reset_set(const stmdev_ctx_t *ctx, lsm6dsv_reset_t val); int32_t lsm6dsv_reset_get(const stmdev_ctx_t *ctx, lsm6dsv_reset_t *val); @@ -4147,8 +4150,14 @@ int32_t lsm6dsv_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, int32_t lsm6dsv_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); +typedef enum +{ + LSM6DSV_FIFO_EV_WTM = 0x0, + LSM6DSV_FIFO_EV_FULL = 0x1, +} lsm6dsv_fifo_event_t; + +int32_t lsm6dsv_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_event_t val); +int32_t lsm6dsv_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_event_t *val); typedef enum { @@ -5050,5 +5059,3 @@ int32_t lsm6dsv_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, #endif #endif /*LSM6DSV_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c index 0b98dee..5042dfd 100644 --- a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c +++ b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -217,6 +216,8 @@ int32_t lsm9ds1_gy_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G, (uint8_t *)&ctrl_reg1_g, 1); + if (ret != 0) { return ret; } + switch (ctrl_reg1_g.fs_g) { case LSM9DS1_245dps: @@ -314,18 +315,12 @@ int32_t lsm9ds1_imu_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G, (uint8_t *)&ctrl_reg1_g, 1); + ret += lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL, + (uint8_t *)&ctrl_reg6_xl, 1); + ret += lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G, + (uint8_t *)&ctrl_reg3_g, 1); - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL, - (uint8_t *)&ctrl_reg6_xl, 1); - } - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G, - (uint8_t *)&ctrl_reg3_g, 1); - } + if (ret != 0) { return ret; } switch ((ctrl_reg3_g.lp_mode << 7) | (ctrl_reg6_xl.odr_xl << 4) | ctrl_reg1_g.odr_g) @@ -484,6 +479,8 @@ int32_t lsm9ds1_gy_orient_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_ORIENT_CFG_G, (uint8_t *)&orient_cfg_g, 1); + if (ret != 0) { return ret; } + val->orient = orient_cfg_g.orient; val->signz_g = orient_cfg_g.signz_g; val->signy_g = orient_cfg_g.signy_g; @@ -508,6 +505,8 @@ int32_t lsm9ds1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.xlda; return ret; @@ -529,6 +528,8 @@ int32_t lsm9ds1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.gda; return ret; @@ -550,6 +551,8 @@ int32_t lsm9ds1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } + *val = status_reg.tda; return ret; @@ -595,6 +598,8 @@ int32_t lsm9ds1_gy_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } + val->xen_g = ctrl_reg4.xen_g; val->yen_g = ctrl_reg4.yen_g; val->zen_g = ctrl_reg4.zen_g; @@ -645,6 +650,8 @@ int32_t lsm9ds1_xl_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t *val) ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG5_XL, (uint8_t *)&ctrl_reg5_xl, 1); + if (ret != 0) { return ret; } + val->xen_xl = ctrl_reg5_xl.xen_xl; val->yen_xl = ctrl_reg5_xl.yen_xl; val->zen_xl = ctrl_reg5_xl.zen_xl; @@ -695,6 +702,7 @@ int32_t lsm9ds1_xl_decimation_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG5_XL, (uint8_t *)&ctrl_reg5_xl, 1); + if (ret != 0) { return ret; } switch (ctrl_reg5_xl.dec) { @@ -765,6 +773,7 @@ int32_t lsm9ds1_xl_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL, (uint8_t *)&ctrl_reg6_xl, 1); + if (ret != 0) { return ret; } switch (ctrl_reg6_xl.fs_xl) { @@ -853,13 +862,11 @@ int32_t lsm9ds1_block_data_update_get(const stmdev_ctx_t *ctx_mag, ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1); + ret += lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG5_M, + (uint8_t *)&ctrl_reg5_m, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG5_M, - (uint8_t *)&ctrl_reg5_m, 1); - *val = (uint8_t)(ctrl_reg5_m.bdu & ctrl_reg8.bdu); - } + *val = (uint8_t)(ctrl_reg5_m.bdu & ctrl_reg8.bdu); return ret; } @@ -867,7 +874,7 @@ int32_t lsm9ds1_block_data_update_get(const stmdev_ctx_t *ctx_mag, /** * @brief This register is a 16-bit register and represents the X offset * used to compensate environmental effects (data is expressed as - * two’s complement).[set] + * two's complement).[set] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data to be write.(ptr) @@ -893,7 +900,7 @@ int32_t lsm9ds1_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief This register is a 16-bit register and represents the X offset * used to compensate environmental effects (data is expressed as - * two’s complement).[get] + * two's complement).[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores data read.(ptr) @@ -906,6 +913,8 @@ int32_t lsm9ds1_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_OFFSET_X_REG_L_M, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -991,12 +1000,10 @@ int32_t lsm9ds1_mag_data_rate_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M, (uint8_t *)&ctrl_reg1_m, 1); + ret += lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_M, + (uint8_t *)&ctrl_reg3_m, 1); - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_M, - (uint8_t *)&ctrl_reg3_m, 1); - } + if (ret != 0) { return ret; } switch ((ctrl_reg3_m.md << 6) | (ctrl_reg1_m.om << 4) | (ctrl_reg1_m.fast_odr << 3) | ctrl_reg1_m._do) @@ -1204,6 +1211,7 @@ int32_t lsm9ds1_mag_full_scale_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_M, (uint8_t *)&ctrl_reg2_m, 1); + if (ret != 0) { return ret; } switch (ctrl_reg2_m.fs) { @@ -1247,6 +1255,8 @@ int32_t lsm9ds1_mag_flag_data_ready_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG_M, (uint8_t *)&status_reg_m, 1); + if (ret != 0) { return ret; } + *val = status_reg_m.zyxda; return ret; @@ -1266,7 +1276,7 @@ int32_t lsm9ds1_mag_flag_data_ready_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register (r). L and H registers - * together express a 16-bit word in two’s complement.[get] + * together express a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores the data read.(ptr) @@ -1279,6 +1289,8 @@ int32_t lsm9ds1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_OUT_TEMP_L, buff, 2); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -1287,7 +1299,7 @@ int32_t lsm9ds1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Angular rate sensor. The value is expressed as a 16-bit word in - * two’s complement.[get] + * two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores the data read.(ptr) @@ -1300,6 +1312,8 @@ int32_t lsm9ds1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_OUT_X_L_G, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1312,7 +1326,7 @@ int32_t lsm9ds1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Linear acceleration output register. The value is expressed as - * a 16-bit word in two’s complement.[get] + * a 16-bit word in two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores the data read.(ptr) @@ -1325,6 +1339,8 @@ int32_t lsm9ds1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_OUT_X_L_XL, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1337,7 +1353,7 @@ int32_t lsm9ds1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) /** * @brief Magnetic sensor. The value is expressed as a 16-bit word in - * two’s complement.[get] + * two's complement.[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores the data read.(ptr) @@ -1350,6 +1366,8 @@ int32_t lsm9ds1_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_OUT_X_L_M, buff, 6); + if (ret != 0) { return ret; } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1374,6 +1392,8 @@ int32_t lsm9ds1_magnetic_overflow_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_SRC_M, (uint8_t *)&int_src_m, 1); + if (ret != 0) { return ret; } + *val = int_src_m.mroi; return ret; @@ -1507,13 +1527,11 @@ int32_t lsm9ds1_dev_reset_get(const stmdev_ctx_t *ctx_mag, ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1); + ret += lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M, + (uint8_t *)&ctrl_reg2_m, 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M, - (uint8_t *)&ctrl_reg2_m, 1); - *val = (uint8_t)(ctrl_reg2_m.soft_rst | ctrl_reg8.sw_reset); - } + *val = (uint8_t)(ctrl_reg2_m.soft_rst | ctrl_reg8.sw_reset); return ret; } @@ -1580,12 +1598,9 @@ int32_t lsm9ds1_dev_data_format_get(const stmdev_ctx_t *ctx_mag, ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG4_M, - (uint8_t *)&ctrl_reg4_m, 1); - } + ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG4_M, + (uint8_t *)&ctrl_reg4_m, 1); + if (ret != 0) { return ret; } switch (ctrl_reg8.ble & ctrl_reg4_m.ble) { @@ -1667,13 +1682,11 @@ int32_t lsm9ds1_dev_boot_get(const stmdev_ctx_t *ctx_mag, ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1); + ret += lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M, + (uint8_t *)&ctrl_reg2_m, 1); - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M, - (uint8_t *)&ctrl_reg2_m, 1); - *val = (uint8_t)ctrl_reg2_m.reboot & ctrl_reg8.boot; - } + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg2_m.reboot & ctrl_reg8.boot; return ret; } @@ -1770,6 +1783,7 @@ int32_t lsm9ds1_gy_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G, (uint8_t *)&ctrl_reg1_g, 1); + if (ret != 0) { return ret; } switch (ctrl_reg1_g.bw_g) { @@ -1855,12 +1869,9 @@ int32_t lsm9ds1_gy_filter_out_path_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_G, (uint8_t *)&ctrl_reg2_g, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G, - (uint8_t *)&ctrl_reg3_g, 1); - } + ret += lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G, + (uint8_t *)&ctrl_reg3_g, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg3_g.hp_en << 4) | ctrl_reg2_g.out_sel) { @@ -1946,12 +1957,9 @@ int32_t lsm9ds1_gy_filter_int_path_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_G, (uint8_t *)&ctrl_reg2_g, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G, - (uint8_t *)&ctrl_reg3_g, 1); - } + ret += lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G, + (uint8_t *)&ctrl_reg3_g, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg3_g.hp_en << 4) | ctrl_reg2_g.int_sel) { @@ -2022,6 +2030,7 @@ int32_t lsm9ds1_gy_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G, (uint8_t *)&ctrl_reg3_g, 1); + if (ret != 0) { return ret; } switch (ctrl_reg3_g.hpcf_g) { @@ -2117,6 +2126,7 @@ int32_t lsm9ds1_xl_filter_aalias_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL, (uint8_t *)&ctrl_reg6_xl, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg6_xl.bw_scal_odr << 4) | ctrl_reg6_xl.bw_xl) { @@ -2191,6 +2201,7 @@ int32_t lsm9ds1_xl_filter_int_path_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL, (uint8_t *)&ctrl_reg7_xl, 1); + if (ret != 0) { return ret; } switch (ctrl_reg7_xl.hpis1) { @@ -2253,6 +2264,7 @@ int32_t lsm9ds1_xl_filter_out_path_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL, (uint8_t *)&ctrl_reg7_xl, 1); + if (ret != 0) { return ret; } switch (ctrl_reg7_xl.fds) { @@ -2318,6 +2330,7 @@ int32_t lsm9ds1_xl_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL, (uint8_t *)&ctrl_reg7_xl, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg7_xl.hr << 4) + ctrl_reg7_xl.dcf) { @@ -2394,6 +2407,7 @@ int32_t lsm9ds1_xl_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL, (uint8_t *)&ctrl_reg7_xl, 1); + if (ret != 0) { return ret; } switch (ctrl_reg7_xl.dcf) { @@ -2461,6 +2475,8 @@ int32_t lsm9ds1_filter_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg9.drdy_mask_bit; return ret; @@ -2519,6 +2535,8 @@ int32_t lsm9ds1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg8.if_add_inc; return ret; @@ -2586,12 +2604,9 @@ int32_t lsm9ds1_spi_mode_get(const stmdev_ctx_t *ctx_mag, ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M, - (uint8_t *)&ctrl_reg3_m, 1); - } + ret += lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M, + (uint8_t *)&ctrl_reg3_m, 1); + if (ret != 0) { return ret; } switch (ctrl_reg8.sim & ctrl_reg3_m.sim) { @@ -2673,12 +2688,9 @@ int32_t lsm9ds1_i2c_interface_get(const stmdev_ctx_t *ctx_mag, ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M, - (uint8_t *)&ctrl_reg3_m, 1); - } + ret += lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M, + (uint8_t *)&ctrl_reg3_m, 1); + if (ret != 0) { return ret; } switch (ctrl_reg9.i2c_disable & ctrl_reg3_m.i2c_disable) { @@ -2769,12 +2781,9 @@ int32_t lsm9ds1_pin_logic_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL, (uint8_t *)&int_gen_cfg_xl, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_G, - (uint8_t *)&int_gen_cfg_g, 1); - } + ret += lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_G, + (uint8_t *)&int_gen_cfg_g, 1); + if (ret != 0) { return ret; } switch (int_gen_cfg_xl.aoi_xl & int_gen_cfg_g.aoi_g) { @@ -2841,6 +2850,8 @@ int32_t lsm9ds1_pin_int1_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) { return ret; } + val->int1_drdy_xl = int1_ctrl.int1_drdy_xl; val->int1_drdy_g = int1_ctrl.int1_drdy_g; val->int1_boot = int1_ctrl.int1_boot; @@ -2899,6 +2910,8 @@ int32_t lsm9ds1_pin_int2_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) { return ret; } + val->int2_drdy_xl = int2_ctrl.int2_drdy_xl; val->int2_inact = int2_ctrl.int2_inact; val->int2_fss5 = int2_ctrl.int2_fss5; @@ -2987,18 +3000,11 @@ int32_t lsm9ds1_pin_notification_get(const stmdev_ctx_t *ctx_mag, ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_INT_GEN_CFG_G, - (uint8_t *)&int_gen_cfg_g, 1); - } - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_INT_CFG_M, - (uint8_t *)&int_cfg_m, 1); - } + ret += lsm9ds1_read_reg(ctx_imu, LSM9DS1_INT_GEN_CFG_G, + (uint8_t *)&int_gen_cfg_g, 1); + ret += lsm9ds1_read_reg(ctx_mag, LSM9DS1_INT_CFG_M, + (uint8_t *)&int_cfg_m, 1); + if (ret != 0) { return ret; } switch (~int_cfg_m.iel & int_gen_cfg_g.lir_g & ctrl_reg4.lir_xl1) { @@ -3055,6 +3061,7 @@ int32_t lsm9ds1_pin_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_pp_od_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1); + if (ret != 0) { return ret; } switch (ctrl_reg8.pp_od) { @@ -3114,6 +3121,8 @@ int32_t lsm9ds1_pin_int_m_route_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1); + if (ret != 0) { return ret; } + val->ien = int_cfg_m.ien; return ret; @@ -3181,12 +3190,9 @@ int32_t lsm9ds1_pin_polarity_get(const stmdev_ctx_t *ctx_mag, ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, - (uint8_t *)&ctrl_reg8, 1); - } + ret += lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8, + (uint8_t *)&ctrl_reg8, 1); + if (ret != 0) { return ret; } switch (int_cfg_m.iea & (~ctrl_reg8.h_lactive)) { @@ -3269,6 +3275,8 @@ int32_t lsm9ds1_xl_trshld_axis_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL, (uint8_t *)&int_gen_cfg_xl, 1); + if (ret != 0) { return ret; } + val->xlie_xl = int_gen_cfg_xl.xlie_xl; val->xhie_xl = int_gen_cfg_xl.xhie_xl; val->ylie_xl = int_gen_cfg_xl.ylie_xl; @@ -3367,6 +3375,8 @@ int32_t lsm9ds1_xl_trshld_min_sample_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_DUR_XL, (uint8_t *)&int_gen_dur_xl, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)int_gen_dur_xl.dur_xl; return ret; @@ -3388,6 +3398,8 @@ int32_t lsm9ds1_gy_trshld_src_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_SRC_G, (uint8_t *)&int_gen_src_g, 1); + if (ret != 0) { return ret; } + val->xl_g = int_gen_src_g.xl_g; val->xh_g = int_gen_src_g.xh_g; val->yl_g = int_gen_src_g.yl_g; @@ -3415,6 +3427,8 @@ int32_t lsm9ds1_xl_trshld_src_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_SRC_XL, (uint8_t *)&int_gen_src_xl, 1); + if (ret != 0) { return ret; } + val->xl_xl = int_gen_src_xl.xl_xl; val->xh_xl = int_gen_src_xl.xh_xl; val->yl_xl = int_gen_src_xl.yl_xl; @@ -3476,6 +3490,8 @@ int32_t lsm9ds1_gy_trshld_axis_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_G, (uint8_t *)&int_gen_cfg_g, 1); + if (ret != 0) { return ret; } + val->xlie_g = int_gen_cfg_g.xlie_g; val->xhie_g = int_gen_cfg_g.xhie_g; val->ylie_g = int_gen_cfg_g.ylie_g; @@ -3529,6 +3545,7 @@ int32_t lsm9ds1_gy_trshld_mode_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G, (uint8_t *)&int_gen_ths_xh_g, 1); + if (ret != 0) { return ret; } switch (int_gen_ths_xh_g.dcrm_g) { @@ -3604,12 +3621,9 @@ int32_t lsm9ds1_gy_trshld_x_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G, (uint8_t *)&int_gen_ths_xh_g, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XL_G, - (uint8_t *)&int_gen_ths_xl_g, 1); - } + ret += lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XL_G, + (uint8_t *)&int_gen_ths_xl_g, 1); + if (ret != 0) { return ret; } *val = int_gen_ths_xh_g.ths_g_x; *val = *val << 8; @@ -3675,12 +3689,9 @@ int32_t lsm9ds1_gy_trshld_y_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_YH_G, (uint8_t *)&int_gen_ths_yh_g, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_YL_G, - (uint8_t *)&int_gen_ths_yl_g, 1); - } + ret += lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_YL_G, + (uint8_t *)&int_gen_ths_yl_g, 1); + if (ret != 0) { return ret; } *val = (uint8_t)int_gen_ths_yh_g.ths_g_y; *val = *val << 8; @@ -3745,12 +3756,9 @@ int32_t lsm9ds1_gy_trshld_z_get(const stmdev_ctx_t *ctx, uint16_t *val) ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_ZH_G, (uint8_t *)&int_gen_ths_zh_g, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_ZL_G, - (uint8_t *)&int_gen_ths_zl_g, 1); - } + ret += lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_ZL_G, + (uint8_t *)&int_gen_ths_zl_g, 1); + if (ret != 0) { return ret; } *val = int_gen_ths_zh_g.ths_g_z; *val = *val << 8; @@ -3812,6 +3820,8 @@ int32_t lsm9ds1_gy_trshld_min_sample_get(const stmdev_ctx_t *ctx, ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_DUR_G, (uint8_t *)&int_gen_dur_g, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)int_gen_dur_g.dur_g; return ret; @@ -3859,6 +3869,8 @@ int32_t lsm9ds1_mag_trshld_axis_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1); + if (ret != 0) { return ret; } + val->zien = int_cfg_m.zien; val->yien = int_cfg_m.yien; val->xien = int_cfg_m.xien; @@ -3881,6 +3893,8 @@ int32_t lsm9ds1_mag_trshld_src_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_SRC_M, (uint8_t *)&int_src_m, 1); + if (ret != 0) { return ret; } + val->_int = int_src_m._int; val->nth_z = int_src_m.nth_z; val->nth_y = int_src_m.nth_y; @@ -3908,12 +3922,9 @@ int32_t lsm9ds1_mag_trshld_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_THS_L_M, (uint8_t *)&int_ths_l_m, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_THS_H_M, - (uint8_t *)&int_ths_h_m, 1); - } + ret += lsm9ds1_read_reg(ctx, LSM9DS1_INT_THS_H_M, + (uint8_t *)&int_ths_h_m, 1); + if (ret != 0) { return ret; } *val = int_ths_h_m.ths; *val = *val << 8; @@ -3973,6 +3984,8 @@ int32_t lsm9ds1_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)act_ths.act_ths; return ret; @@ -4031,11 +4044,8 @@ int32_t lsm9ds1_act_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1); - } + ret += lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1); + if (ret != 0) { return ret; } switch (act_ths.sleep_on_inact_en & ctrl_reg9.sleep_g) { @@ -4104,6 +4114,7 @@ int32_t lsm9ds1_act_src_get(const stmdev_ctx_t *ctx, lsm9ds1_inact_t *val) ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG, (uint8_t *)&status_reg, 1); + if (ret != 0) { return ret; } switch (status_reg.inact) { @@ -4193,12 +4204,9 @@ int32_t lsm9ds1_6d_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t *val) ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL, (uint8_t *)&int_gen_cfg_xl, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - } + ret += lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4, + (uint8_t *)&ctrl_reg4, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg4._4d_xl1 << 2) | (int_gen_cfg_xl.aoi_xl << 1) | int_gen_cfg_xl.aoi_xl) @@ -4280,6 +4288,8 @@ int32_t lsm9ds1_6d_src_get(const stmdev_ctx_t *ctx, lsm9ds1_6d_src_t *val) ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_SRC_XL, (uint8_t *)&int_gen_src_xl, 1); + if (ret != 0) { return ret; } + val->xl_xl = int_gen_src_xl.xl_xl; val->xh_xl = int_gen_src_xl.xh_xl; val->yl_xl = int_gen_src_xl.yl_xl; @@ -4344,6 +4354,8 @@ int32_t lsm9ds1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg9.stop_on_fth; return ret; @@ -4402,11 +4414,8 @@ int32_t lsm9ds1_fifo_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1); - - if (ret == 0) - { - ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - } + ret += lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret != 0) { return ret; } switch ((ctrl_reg9.fifo_en << 4) | ctrl_reg9.fifo_en) { @@ -4480,6 +4489,8 @@ int32_t lsm9ds1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg9.fifo_temp_en; return ret; @@ -4523,6 +4534,8 @@ int32_t lsm9ds1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)fifo_ctrl.fth; return ret; @@ -4542,6 +4555,8 @@ int32_t lsm9ds1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t *)&fifo_src, 1); + if (ret != 0) { return ret; } + *val = fifo_src.fss; return ret; @@ -4561,6 +4576,8 @@ int32_t lsm9ds1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t *)&fifo_src, 1); + if (ret != 0) { return ret; } + *val = fifo_src.fss; return ret; @@ -4580,6 +4597,8 @@ int32_t lsm9ds1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t *)&fifo_src, 1); + if (ret != 0) { return ret; } + *val = fifo_src.ovrn; return ret; @@ -4599,6 +4618,8 @@ int32_t lsm9ds1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t *)&fifo_src, 1); + if (ret != 0) { return ret; } + *val = fifo_src.fth; return ret; @@ -4658,6 +4679,8 @@ int32_t lsm9ds1_xl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10, (uint8_t *)&ctrl_reg10, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg10.st_xl; return ret; @@ -4704,6 +4727,8 @@ int32_t lsm9ds1_gy_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10, (uint8_t *)&ctrl_reg10, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg10.st_g; return ret; @@ -4750,6 +4775,8 @@ int32_t lsm9ds1_mag_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M, (uint8_t *)&ctrl_reg1_m, 1); + if (ret != 0) { return ret; } + *val = (uint8_t)ctrl_reg1_m.st; return ret; @@ -4759,5 +4786,3 @@ int32_t lsm9ds1_mag_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h index 2dba240..6891fb4 100644 --- a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h +++ b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -1652,5 +1654,3 @@ int32_t lsm9ds1_mag_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); #endif #endif /* LSM9DS1_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/st1vafe3bx_STdC/driver/st1vafe3bx_reg.c b/sensor/stmemsc/st1vafe3bx_STdC/driver/st1vafe3bx_reg.c index 0ded721..b308cb7 100644 --- a/sensor/stmemsc/st1vafe3bx_STdC/driver/st1vafe3bx_reg.c +++ b/sensor/stmemsc/st1vafe3bx_STdC/driver/st1vafe3bx_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -46,7 +45,7 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak st1vafe3bx_read_reg(const st1vafe3bx_ctx_t *ctx, uint8_t reg, +int32_t __weak st1vafe3bx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { if (ctx == NULL) @@ -67,7 +66,7 @@ int32_t __weak st1vafe3bx_read_reg(const st1vafe3bx_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak st1vafe3bx_write_reg(const st1vafe3bx_ctx_t *ctx, uint8_t reg, +int32_t __weak st1vafe3bx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { if (ctx == NULL) @@ -134,7 +133,7 @@ float_t st1vafe3bx_from_lsb_to_mv(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_device_id_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -151,7 +150,7 @@ int32_t st1vafe3bx_device_id_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_init_set(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_init_t val) +int32_t st1vafe3bx_init_set(const stmdev_ctx_t *ctx, st1vafe3bx_init_t val) { st1vafe3bx_ctrl1_t ctrl1; st1vafe3bx_ctrl4_t ctrl4; @@ -170,6 +169,11 @@ int32_t st1vafe3bx_init_set(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_init_t val) (uint8_t *)&ah_bio_cfg3, 1); ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (val) { case ST1VAFE3BX_BOOT: @@ -315,7 +319,7 @@ int32_t st1vafe3bx_init_set(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_init_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_smart_power_set(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_smart_power_t val) +int32_t st1vafe3bx_smart_power_set(const stmdev_ctx_t *ctx, st1vafe3bx_smart_power_t val) { st1vafe3bx_ctrl1_t ctrl1; st1vafe3bx_smart_power_ctrl_t pwr_ctrl; @@ -346,7 +350,7 @@ int32_t st1vafe3bx_smart_power_set(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_smart * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_smart_power_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_smart_power_t *val) +int32_t st1vafe3bx_smart_power_get(const stmdev_ctx_t *ctx, st1vafe3bx_smart_power_t *val) { st1vafe3bx_ctrl1_t ctrl1; st1vafe3bx_smart_power_ctrl_t pwr_ctrl; @@ -374,7 +378,7 @@ int32_t st1vafe3bx_smart_power_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_smart * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_status_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_status_t *val) +int32_t st1vafe3bx_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_status_t *val) { st1vafe3bx_status_register_t status_register; st1vafe3bx_ctrl1_t ctrl1; @@ -386,6 +390,11 @@ int32_t st1vafe3bx_status_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_status_t * ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1); ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + val->sw_reset = ctrl1.sw_reset; val->boot = ctrl4.boot; val->drdy = status_register.drdy; @@ -401,12 +410,18 @@ int32_t st1vafe3bx_status_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_status_t * * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_drdy_status_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_status_t *val) +int32_t st1vafe3bx_drdy_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_status_t *val) { st1vafe3bx_status_register_t status_register; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_STATUS, (uint8_t *)&status_register, 1); + + if (ret != 0) + { + return ret; + } + val->drdy = status_register.drdy; return ret; @@ -420,17 +435,27 @@ int32_t st1vafe3bx_drdy_status_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_statu * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_embedded_status_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_embedded_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_embedded_status_t *val) { st1vafe3bx_emb_func_status_t status; int32_t ret; ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK); - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_STATUS, - (uint8_t *)&status, 1); + + if (ret == 0) + { + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_STATUS, + (uint8_t *)&status, 1); + } + ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + val->is_step_det = status.is_step_det; val->is_tilt = status.is_tilt; val->is_sigmot = status.is_sigmot; @@ -447,7 +472,7 @@ int32_t st1vafe3bx_embedded_status_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_data_ready_mode_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_data_ready_mode_set(const stmdev_ctx_t *ctx, st1vafe3bx_data_ready_mode_t val) { st1vafe3bx_ctrl1_t ctrl1; @@ -472,7 +497,7 @@ int32_t st1vafe3bx_data_ready_mode_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_data_ready_mode_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_data_ready_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_data_ready_mode_t *val) { st1vafe3bx_ctrl1_t ctrl1; @@ -480,6 +505,11 @@ int32_t st1vafe3bx_data_ready_mode_get(const st1vafe3bx_ctx_t *ctx, ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } + switch ((ctrl1.drdy_pulsed)) { case ST1VAFE3BX_DRDY_LATCHED: @@ -505,94 +535,232 @@ int32_t st1vafe3bx_data_ready_mode_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_mode_set(const st1vafe3bx_ctx_t *ctx, const st1vafe3bx_md_t *val) +int32_t st1vafe3bx_mode_set(const stmdev_ctx_t *ctx, const st1vafe3bx_md_t *val) { st1vafe3bx_ctrl3_t ctrl3; st1vafe3bx_ctrl5_t ctrl5; int32_t ret; + uint8_t hp_en_change = 0U; - ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL5, (uint8_t *)&ctrl5, 1); - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1); + ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1); + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL5, (uint8_t *)&ctrl5, 1); - ctrl5.odr = (uint8_t)val->odr & 0xFU; - ctrl5.fs = (uint8_t)val->fs; + if (ret != 0) + { + return ret; + } - /* select high performance mode */ - switch (val->odr & 0x30U) + if (ctrl3.hp_en != val->hp_en) { - case 0x30U: - case 0x10U: - /* high performance mode */ - ctrl3.hp_en = 1U; - break; - case 0x00U: - case 0x20U: - default: - /* low power mode */ - ctrl3.hp_en = 0U; - break; + hp_en_change = 1U; } - /* set the bandwidth */ - switch (val->odr) + /* Set the power mode */ + ctrl3.hp_en = val->hp_en; + + if (hp_en_change == 1U && ctrl5.odr != 0x00) { - /* no anti-aliasing filter present */ - default: - case ST1VAFE3BX_OFF: - case ST1VAFE3BX_1Hz6_ULP: - case ST1VAFE3BX_3Hz_ULP: - case ST1VAFE3BX_25Hz_ULP: - ctrl5.bw = 0x0; - break; + /* Power down to allow HP_EN change (see: ST1VAFE3BX datasheet) */ + uint32_t timeout = (ctrl5.odr == 0x01U) ? 625U /* 1.6 Hz */ + : (ctrl5.odr == 0x02U) ? 335U /* 3.0 Hz */ + : (ctrl5.odr == 0x03U) ? 40U /* 25.0 Hz */ + : (ctrl5.odr == 0x04U) ? 170U /* 6.0 Hz */ + : (ctrl5.odr == 0x05U) ? 80U /* 12.5 Hz */ + : (ctrl5.odr == 0x06U) ? 40U /* 25.0 Hz */ + : 25U; /* >= 50.0 Hz */ + + ctrl5.odr = 0x00U; + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL5, (uint8_t *)&ctrl5, 1); - /* low-power mode with ODR < 50 Hz */ - case ST1VAFE3BX_6Hz_LP: - case ST1VAFE3BX_12Hz5_LP: - case ST1VAFE3BX_25Hz_LP: - switch (val->bw) - { - default: - /* value not allowed */ - ret = -1; - break; - case ST1VAFE3BX_BW_LP_12Hz5: - ctrl5.bw = 0x1; - break; - case ST1VAFE3BX_BW_LP_6Hz: - ctrl5.bw = 0x2; - break; - case ST1VAFE3BX_BW_LP_3Hz: - ctrl5.bw = 0x3; - break; - } - break; + /* Wait one ODR period (see AN6160 Section 3.1) */ + if (ctx->mdelay != NULL) + { + ctx->mdelay(timeout); + } + } - /* High Performance cases */ - case ST1VAFE3BX_800Hz_VAFE_HP: - case ST1VAFE3BX_3200Hz_VAFE_LP: - case ST1VAFE3BX_50Hz_LP: - case ST1VAFE3BX_100Hz_LP: - case ST1VAFE3BX_200Hz_LP: - case ST1VAFE3BX_400Hz_LP: - case ST1VAFE3BX_800Hz_LP: - case ST1VAFE3BX_TRIG_PIN: - case ST1VAFE3BX_TRIG_SW: - case ST1VAFE3BX_6Hz_HP: - case ST1VAFE3BX_12Hz5_HP: - case ST1VAFE3BX_25Hz_HP: - case ST1VAFE3BX_50Hz_HP: - case ST1VAFE3BX_100Hz_HP: - case ST1VAFE3BX_200Hz_HP: - case ST1VAFE3BX_400Hz_HP: - case ST1VAFE3BX_800Hz_HP: - ctrl5.bw = (uint8_t)val->bw; - break; + /* Set the ODR, full scale */ + ctrl5.odr = (val->odr == ST1VAFE3BX_TRIG_PIN) ? 0x0FU : (uint8_t)val->odr & 0x0FU; + ctrl5.fs = (uint8_t)val->fs; + + /* Set the bandwidth */ + if (ctx->priv_data && ((st1vafe3bx_priv_t *)(ctx->priv_data))->vafe_only == 1) + { + switch (val->odr) + { + case ST1VAFE3BX_800Hz_VAFE_HP: + switch (val->bw) + { + case ST1VAFE3BX_BW_VAFE_360Hz: + ctrl5.bw = 0x00U; + break; + + case ST1VAFE3BX_BW_VAFE_180Hz: + ctrl5.bw = 0x01U; + break; + + case ST1VAFE3BX_BW_VAFE_90Hz: + ctrl5.bw = 0x02U; + break; + + case ST1VAFE3BX_BW_VAFE_45Hz: + ctrl5.bw = 0x03U; + break; + + default: + /* Value not allowed */ + ret += 1; + break; + } + break; + + case ST1VAFE3BX_3200Hz_VAFE_LP: + switch (val->bw) + { + case ST1VAFE3BX_BW_VAFE_1600Hz: + ctrl5.bw = 0x00U; + break; + + case ST1VAFE3BX_BW_VAFE_700Hz: + ctrl5.bw = 0x01U; + break; + + case ST1VAFE3BX_BW_VAFE_360Hz: + ctrl5.bw = 0x02U; + break; + + case ST1VAFE3BX_BW_VAFE_180Hz: + ctrl5.bw = 0x03U; + break; + + default: + /* Value not allowed */ + ret += 1; + break; + } + break; + + default: + /* Value not allowed */ + ret += 1; + break; + } + } + else + { + switch (val->odr) + { + /* No anti-aliasing filter present */ + default: + case ST1VAFE3BX_OFF: + case ST1VAFE3BX_1Hz6_ULP: + case ST1VAFE3BX_3Hz_ULP: + case ST1VAFE3BX_25Hz_ULP: + case ST1VAFE3BX_TRIG_PIN: + case ST1VAFE3BX_TRIG_SW: + ctrl5.bw = 0x00U; + break; + + /* The low-power mode with ODR < 50 Hz */ + case ST1VAFE3BX_6Hz_LP: + switch (val->bw) + { + case ST1VAFE3BX_BW_LP_3Hz: + ctrl5.bw = 0x03U; + break; + + default: + /* Value not allowed */ + ret += 1; + break; + } + break; + + case ST1VAFE3BX_12Hz5_LP: + switch (val->bw) + { + case ST1VAFE3BX_BW_LP_6Hz: + ctrl5.bw = 0x02U; + break; + + case ST1VAFE3BX_BW_LP_3Hz: + ctrl5.bw = 0x03U; + break; + + default: + /* Value not allowed */ + ret += 1; + break; + } + break; + + case ST1VAFE3BX_25Hz_LP: + switch (val->bw) + { + case ST1VAFE3BX_BW_LP_12Hz5: + ctrl5.bw = 0x01U; + break; + + case ST1VAFE3BX_BW_LP_6Hz: + ctrl5.bw = 0x02U; + break; + + case ST1VAFE3BX_BW_LP_3Hz: + ctrl5.bw = 0x03U; + break; + + default: + /* Value not allowed */ + ret += 1; + break; + } + break; + + /* The low-power mode with ODR >= 50 Hz, High Performance cases */ + case ST1VAFE3BX_50Hz_LP: + case ST1VAFE3BX_100Hz_LP: + case ST1VAFE3BX_200Hz_LP: + case ST1VAFE3BX_400Hz_LP: + case ST1VAFE3BX_800Hz_LP: + case ST1VAFE3BX_6Hz_HP: + case ST1VAFE3BX_12Hz5_HP: + case ST1VAFE3BX_25Hz_HP: + case ST1VAFE3BX_50Hz_HP: + case ST1VAFE3BX_100Hz_HP: + case ST1VAFE3BX_200Hz_HP: + case ST1VAFE3BX_400Hz_HP: + case ST1VAFE3BX_800Hz_HP: + switch (val->bw) + { + case ST1VAFE3BX_BW_ODR_div_2: + ctrl5.bw = 0x00U; + break; + + case ST1VAFE3BX_BW_ODR_div_4: + ctrl5.bw = 0x01U; + break; + + case ST1VAFE3BX_BW_ODR_div_8: + ctrl5.bw = 0x02U; + break; + + case ST1VAFE3BX_BW_ODR_div_16: + ctrl5.bw = 0x03U; + break; + + default: + /* Value not allowed */ + ret += 1; + break; + } + break; + } } if (ret == 0) { - ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL5, (uint8_t *)&ctrl5, 1); - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1); + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1); + ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL5, (uint8_t *)&ctrl5, 1); } return ret; @@ -606,7 +774,7 @@ int32_t st1vafe3bx_mode_set(const st1vafe3bx_ctx_t *ctx, const st1vafe3bx_md_t * * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_mode_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_md_t *val) +int32_t st1vafe3bx_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_md_t *val) { st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2; st1vafe3bx_ctrl3_t ctrl3; @@ -619,6 +787,11 @@ int32_t st1vafe3bx_mode_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_md_t *val) val->hp_en = ctrl3.hp_en; + if (ret != 0) + { + return ret; + } + switch (ctrl5.odr) { case 0x00: @@ -634,7 +807,7 @@ int32_t st1vafe3bx_mode_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_md_t *val) val->odr = ST1VAFE3BX_25Hz_ULP; break; case 0x04: - val->odr = ST1VAFE3BX_6Hz_LP; + val->odr = (ctrl3.hp_en == 0x1U) ? ST1VAFE3BX_6Hz_HP : ST1VAFE3BX_6Hz_LP; break; case 0x05: val->odr = (ctrl3.hp_en == 0x1U) ? ST1VAFE3BX_12Hz5_HP : ST1VAFE3BX_12Hz5_LP; @@ -724,8 +897,8 @@ int32_t st1vafe3bx_mode_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_md_t *val) } else { - if (ctrl5.odr == ST1VAFE3BX_6Hz_LP || ctrl5.odr == ST1VAFE3BX_12Hz5_LP - || ctrl5.odr == ST1VAFE3BX_25Hz_LP) + if (val->odr == ST1VAFE3BX_6Hz_LP || val->odr == ST1VAFE3BX_12Hz5_LP + || val->odr == ST1VAFE3BX_25Hz_LP) { switch (ctrl5.bw) { @@ -779,7 +952,7 @@ int32_t st1vafe3bx_mode_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_exit_deep_power_down(const st1vafe3bx_ctx_t *ctx) +int32_t st1vafe3bx_exit_deep_power_down(const stmdev_ctx_t *ctx) { st1vafe3bx_en_device_config_t en_device_config = {0}; int32_t ret; @@ -804,7 +977,7 @@ int32_t st1vafe3bx_exit_deep_power_down(const st1vafe3bx_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_trigger_sw(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_trigger_sw(const stmdev_ctx_t *ctx, const st1vafe3bx_md_t *md) { st1vafe3bx_ctrl4_t ctrl4; @@ -822,13 +995,19 @@ int32_t st1vafe3bx_trigger_sw(const st1vafe3bx_ctx_t *ctx, return ret; } -int32_t st1vafe3bx_all_sources_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_all_sources_get(const stmdev_ctx_t *ctx, st1vafe3bx_all_sources_t *val) { st1vafe3bx_status_register_t status; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_STATUS, (uint8_t *)&status, 1); + + if (ret != 0) + { + return ret; + } + val->drdy = status.drdy; if (ret == 0 && status.int_global == 0x1U) @@ -843,6 +1022,10 @@ int32_t st1vafe3bx_all_sources_get(const st1vafe3bx_ctx_t *ctx, (uint8_t *)&wu_src, 1); ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_SRC, (uint8_t *)&tap_src, 1); + if (ret != 0) + { + return ret; + } val->six_d = sixd_src.d6d_ia; val->six_d_xl = sixd_src.xl; @@ -877,7 +1060,7 @@ int32_t st1vafe3bx_all_sources_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_xl_data_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_xl_data_get(const stmdev_ctx_t *ctx, const st1vafe3bx_md_t *md, st1vafe3bx_xl_data_t *data) { @@ -888,6 +1071,11 @@ int32_t st1vafe3bx_xl_data_get(const st1vafe3bx_ctx_t *ctx, ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_OUT_X_L, buff, 6); + if (ret != 0) + { + return ret; + } + /* acceleration conversion */ j = 0U; for (i = 0U; i < 3U; i++) @@ -926,15 +1114,20 @@ int32_t st1vafe3bx_xl_data_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_ah_bio_data_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_ah_bio_data_get(const stmdev_ctx_t *ctx, st1vafe3bx_ah_bio_data_t *data) { uint8_t buff[3]; int32_t ret; - if (ctx->vafe_only == 1) + if (ctx->priv_data && + ((st1vafe3bx_priv_t *)(ctx->priv_data))->vafe_only == 1) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_OUT_AH_BIO_L, buff, 2); + if (ret != 0) + { + return ret; + } data->raw = (int16_t)buff[1]; data->raw = (data->raw * 256U) + (int16_t)buff[0]; @@ -945,6 +1138,10 @@ int32_t st1vafe3bx_ah_bio_data_get(const st1vafe3bx_ctx_t *ctx, { /* Read and discard also OUT_Z_H reg to clear drdy */ ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_OUT_AH_BIO_L - 1, buff, 3); + if (ret != 0) + { + return ret; + } data->raw = (int16_t)buff[2]; data->raw = (data->raw * 256U) + (int16_t)buff[1]; @@ -963,7 +1160,7 @@ int32_t st1vafe3bx_ah_bio_data_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_self_test_sign_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_self_test_sign_set(const stmdev_ctx_t *ctx, st1vafe3bx_xl_self_test_t val) { st1vafe3bx_ctrl3_t ctrl3; @@ -974,6 +1171,11 @@ int32_t st1vafe3bx_self_test_sign_set(const st1vafe3bx_ctx_t *ctx, ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1); + if (ret != 0) + { + return ret; + } + switch (val) { case ST1VAFE3BX_XL_ST_POSITIVE: @@ -1010,7 +1212,7 @@ int32_t st1vafe3bx_self_test_sign_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_self_test_start(const st1vafe3bx_ctx_t *ctx, uint8_t val) +int32_t st1vafe3bx_self_test_start(const stmdev_ctx_t *ctx, uint8_t val) { st1vafe3bx_ah_bio_cfg3_t ah_bio_cfg3; int32_t ret; @@ -1038,7 +1240,7 @@ int32_t st1vafe3bx_self_test_start(const st1vafe3bx_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_self_test_stop(const st1vafe3bx_ctx_t *ctx) +int32_t st1vafe3bx_self_test_stop(const stmdev_ctx_t *ctx) { st1vafe3bx_ah_bio_cfg3_t ah_bio_cfg3; int32_t ret; @@ -1062,7 +1264,7 @@ int32_t st1vafe3bx_self_test_stop(const st1vafe3bx_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_i3c_configure_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_i3c_configure_set(const stmdev_ctx_t *ctx, const st1vafe3bx_i3c_cfg_t *val) { st1vafe3bx_i3c_if_ctrl_t i3c_cfg; @@ -1090,7 +1292,7 @@ int32_t st1vafe3bx_i3c_configure_set(const st1vafe3bx_ctx_t *ctx, * @param val configuration params * @retval interface status (MANDATORY: return 0 -> no Error) * - */int32_t st1vafe3bx_i3c_configure_get(const st1vafe3bx_ctx_t *ctx, + */int32_t st1vafe3bx_i3c_configure_get(const stmdev_ctx_t *ctx, st1vafe3bx_i3c_cfg_t *val) { st1vafe3bx_i3c_if_ctrl_t i3c_cfg; @@ -1099,6 +1301,11 @@ int32_t st1vafe3bx_i3c_configure_set(const st1vafe3bx_ctx_t *ctx, ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1); + if (ret != 0) + { + return ret; + } + val->drstdaa_en = i3c_cfg.dis_drstdaa; val->asf_on = i3c_cfg.asf_on; @@ -1134,7 +1341,7 @@ int32_t st1vafe3bx_i3c_configure_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_mem_bank_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_mem_bank_set(const stmdev_ctx_t *ctx, st1vafe3bx_mem_bank_t val) { st1vafe3bx_func_cfg_access_t func_cfg_access; @@ -1162,7 +1369,7 @@ int32_t st1vafe3bx_mem_bank_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_mem_bank_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_mem_bank_get(const stmdev_ctx_t *ctx, st1vafe3bx_mem_bank_t *val) { st1vafe3bx_func_cfg_access_t func_cfg_access; @@ -1171,6 +1378,11 @@ int32_t st1vafe3bx_mem_bank_get(const st1vafe3bx_ctx_t *ctx, ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + switch ((func_cfg_access.emb_func_reg_access)) { case 0x0: @@ -1199,7 +1411,7 @@ int32_t st1vafe3bx_mem_bank_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_ln_pg_write(const st1vafe3bx_ctx_t *ctx, uint16_t address, +int32_t st1vafe3bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { st1vafe3bx_page_address_t page_address; @@ -1214,61 +1426,94 @@ int32_t st1vafe3bx_ln_pg_write(const st1vafe3bx_ctx_t *ctx, uint16_t address, lsb = (uint8_t)address & 0xFFU; ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } - if (ret == 0) + /* set page write */ + ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1); - page_rw.page_read = PROPERTY_DISABLE; - page_rw.page_write = PROPERTY_ENABLE; - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW, - (uint8_t *)&page_rw, 1); - - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - page_sel.page_sel = msb; - page_sel.not_used0 = 1; // Default value - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; + } + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW, + (uint8_t *)&page_rw, 1); + + /* select page */ + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } - page_address.page_addr = lsb; - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + /* set page addr */ + page_address.page_addr = lsb; + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } - for (i = 0; i < len; i++) + for (i = 0; i < len; i++) + { + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_VALUE, &buf[i], 1); - lsb++; + goto exit; + } + lsb++; - /* Check if page wrap */ - if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - msb++; - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - page_sel.page_sel = msb; - page_sel.not_used0 = 1; // Default value - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL, + (uint8_t *)&page_sel, 1); if (ret != 0) { - break; + goto exit; } } + } - page_sel.page_sel = 0; - page_sel.not_used0 = 1;// Default value - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL, + (uint8_t *)&page_sel, 1); - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1); - page_rw.page_read = PROPERTY_DISABLE; - page_rw.page_write = PROPERTY_DISABLE; - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW, - (uint8_t *)&page_rw, 1); + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; } + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW, + (uint8_t *)&page_rw, 1); +exit: ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK); return ret; @@ -1285,7 +1530,7 @@ int32_t st1vafe3bx_ln_pg_write(const st1vafe3bx_ctx_t *ctx, uint16_t address, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_ln_pg_read(const st1vafe3bx_ctx_t *ctx, uint16_t address, +int32_t st1vafe3bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { st1vafe3bx_page_address_t page_address; @@ -1300,61 +1545,98 @@ int32_t st1vafe3bx_ln_pg_read(const st1vafe3bx_ctx_t *ctx, uint16_t address, lsb = (uint8_t)address & 0xFFU; ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } - if (ret == 0) + /* set page read */ + ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { - ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1); - page_rw.page_read = PROPERTY_ENABLE; - page_rw.page_write = PROPERTY_DISABLE; - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW, - (uint8_t *)&page_rw, 1); - - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - page_sel.page_sel = msb; - page_sel.not_used0 = 1; // Default value - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; + } + page_rw.page_read = PROPERTY_ENABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW, + (uint8_t *)&page_rw, 1); + + /* select page */ + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + page_rw.page_read = PROPERTY_ENABLE; + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } - page_address.page_addr = lsb; - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + /* set page addr */ + page_address.page_addr = lsb; + ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } - for (i = 0; i < len; i++) + for (i = 0; i < len; i++) + { + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_VALUE, &buf[i], 1); - lsb++; + goto exit; + } + lsb++; - /* Check if page wrap */ - if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) { - msb++; - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_SEL, - (uint8_t *)&page_sel, 1); - page_sel.page_sel = msb; - page_sel.not_used0 = 1; // Default value - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + goto exit; } - + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL, + (uint8_t *)&page_sel, 1); if (ret != 0) { - break; + goto exit; } } + } - page_sel.page_sel = 0; - page_sel.not_used0 = 1;// Default value - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL, - (uint8_t *)&page_sel, 1); + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL, + (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1); - page_rw.page_read = PROPERTY_DISABLE; - page_rw.page_write = PROPERTY_DISABLE; - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW, - (uint8_t *)&page_rw, 1); + ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; } + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW, + (uint8_t *)&page_rw, 1); +exit: ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK); return ret; @@ -1380,12 +1662,17 @@ int32_t st1vafe3bx_ln_pg_read(const st1vafe3bx_ctx_t *ctx, uint16_t address, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_ext_clk_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) +int32_t st1vafe3bx_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val) { st1vafe3bx_ext_clk_cfg_t clk; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EXT_CLK_CFG, (uint8_t *)&clk, 1); + if (ret != 0) + { + return ret; + } + clk.ext_clk_en = val; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EXT_CLK_CFG, (uint8_t *)&clk, 1); @@ -1400,12 +1687,17 @@ int32_t st1vafe3bx_ext_clk_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_ext_clk_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { st1vafe3bx_ext_clk_cfg_t clk; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EXT_CLK_CFG, (uint8_t *)&clk, 1); + if (ret != 0) + { + return ret; + } + *val = clk.ext_clk_en; return ret; @@ -1419,7 +1711,7 @@ int32_t st1vafe3bx_ext_clk_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_pin_conf_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_pin_conf_set(const stmdev_ctx_t *ctx, const st1vafe3bx_pin_conf_t *val) { st1vafe3bx_pin_ctrl_t pin_ctrl; @@ -1449,13 +1741,17 @@ int32_t st1vafe3bx_pin_conf_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_pin_conf_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_pin_conf_get(const stmdev_ctx_t *ctx, st1vafe3bx_pin_conf_t *val) { st1vafe3bx_pin_ctrl_t pin_ctrl; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } val->cs_pull_up = ~pin_ctrl.cs_pu_dis; val->sda_pull_up = pin_ctrl.sda_pu_en; @@ -1473,7 +1769,7 @@ int32_t st1vafe3bx_pin_conf_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_int_pin_polarity_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_int_pin_polarity_set(const stmdev_ctx_t *ctx, st1vafe3bx_int_pin_polarity_t val) { st1vafe3bx_pin_ctrl_t pin_ctrl; @@ -1499,13 +1795,17 @@ int32_t st1vafe3bx_int_pin_polarity_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_int_pin_polarity_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_int_pin_polarity_get(const stmdev_ctx_t *ctx, st1vafe3bx_int_pin_polarity_t *val) { st1vafe3bx_pin_ctrl_t pin_ctrl; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch ((pin_ctrl.h_lactive)) { @@ -1533,7 +1833,7 @@ int32_t st1vafe3bx_int_pin_polarity_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_spi_mode_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_spi_mode_set(const stmdev_ctx_t *ctx, st1vafe3bx_spi_mode val) { st1vafe3bx_pin_ctrl_t pin_ctrl; @@ -1559,13 +1859,17 @@ int32_t st1vafe3bx_spi_mode_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_spi_mode_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_spi_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_spi_mode *val) { st1vafe3bx_pin_ctrl_t pin_ctrl; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } switch ((pin_ctrl.sim)) { @@ -1592,7 +1896,7 @@ int32_t st1vafe3bx_spi_mode_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_pin_int_route_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_pin_int_route_set(const stmdev_ctx_t *ctx, const st1vafe3bx_pin_int_route_t *val) { st1vafe3bx_ctrl1_t ctrl1; @@ -1601,6 +1905,11 @@ int32_t st1vafe3bx_pin_int_route_set(const st1vafe3bx_ctx_t *ctx, int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } + ctrl1.int_pin_en = PROPERTY_ENABLE; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1); @@ -1650,7 +1959,7 @@ int32_t st1vafe3bx_pin_int_route_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_pin_int_route_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_pin_int_route_get(const stmdev_ctx_t *ctx, st1vafe3bx_pin_int_route_t *val) { st1vafe3bx_ctrl2_t ctrl2; @@ -1688,7 +1997,7 @@ int32_t st1vafe3bx_pin_int_route_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_emb_pin_int_route_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_emb_pin_int_route_set(const stmdev_ctx_t *ctx, const st1vafe3bx_emb_pin_int_route_t *val) { st1vafe3bx_emb_func_int_t emb_func_int; @@ -1732,7 +2041,7 @@ int32_t st1vafe3bx_emb_pin_int_route_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_emb_pin_int_route_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_emb_pin_int_route_get(const stmdev_ctx_t *ctx, st1vafe3bx_emb_pin_int_route_t *val) { st1vafe3bx_emb_func_int_t emb_func_int; @@ -1752,7 +2061,7 @@ int32_t st1vafe3bx_emb_pin_int_route_get(const st1vafe3bx_ctx_t *ctx, val->step_det = emb_func_int.int_step_det; val->fsm_lc = emb_func_int.int_fsm_lc; } - ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK); + ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK); return ret; } @@ -1765,7 +2074,7 @@ int32_t st1vafe3bx_emb_pin_int_route_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_int_config_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_int_config_set(const stmdev_ctx_t *ctx, const st1vafe3bx_int_config_t *val) { st1vafe3bx_interrupt_cfg_t interrupt_cfg; @@ -1812,7 +2121,7 @@ int32_t st1vafe3bx_int_config_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_int_config_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_int_config_get(const stmdev_ctx_t *ctx, st1vafe3bx_int_config_t *val) { st1vafe3bx_interrupt_cfg_t interrupt_cfg; @@ -1851,7 +2160,7 @@ int32_t st1vafe3bx_int_config_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_embedded_int_cfg_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_embedded_int_cfg_set(const stmdev_ctx_t *ctx, st1vafe3bx_embedded_int_config_t val) { st1vafe3bx_page_rw_t page_rw; @@ -1861,6 +2170,10 @@ int32_t st1vafe3bx_embedded_int_cfg_set(const st1vafe3bx_ctx_t *ctx, if (ret == 0) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + if (ret == 0) + { switch (val) { @@ -1874,8 +2187,8 @@ int32_t st1vafe3bx_embedded_int_cfg_set(const st1vafe3bx_ctx_t *ctx, break; } - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW, - (uint8_t *)&page_rw, 1); + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW, + (uint8_t *)&page_rw, 1); } ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK); @@ -1891,7 +2204,7 @@ int32_t st1vafe3bx_embedded_int_cfg_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_embedded_int_cfg_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_embedded_int_cfg_get(const stmdev_ctx_t *ctx, st1vafe3bx_embedded_int_config_t *val) { st1vafe3bx_page_rw_t page_rw; @@ -1901,6 +2214,9 @@ int32_t st1vafe3bx_embedded_int_cfg_get(const st1vafe3bx_ctx_t *ctx, if (ret == 0) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { if (page_rw.emb_func_lir == 0U) { @@ -1938,7 +2254,7 @@ int32_t st1vafe3bx_embedded_int_cfg_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_fifo_mode_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fifo_mode_set(const stmdev_ctx_t *ctx, st1vafe3bx_fifo_mode_t val) { st1vafe3bx_ctrl4_t ctrl4; @@ -2024,7 +2340,7 @@ int32_t st1vafe3bx_fifo_mode_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_fifo_mode_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fifo_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_fifo_mode_t *val) { st1vafe3bx_ctrl4_t ctrl4; @@ -2078,31 +2394,39 @@ int32_t st1vafe3bx_fifo_mode_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_fifo_data_level_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val) +int32_t st1vafe3bx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_STATUS2, &buff, 1); + if (ret != 0) + { + return ret; + } *val = buff; return ret; } -int32_t st1vafe3bx_fifo_wtm_flag_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { st1vafe3bx_fifo_status1_t fifo_status1; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1); + if (ret != 0) + { + return ret; + } *val = fifo_status1.fifo_wtm_ia; return ret; } -int32_t st1vafe3bx_fifo_sensor_tag_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, st1vafe3bx_fifo_sensor_tag_t *val) { st1vafe3bx_fifo_data_out_tag_t fifo_tag; @@ -2110,13 +2434,17 @@ int32_t st1vafe3bx_fifo_sensor_tag_get(const st1vafe3bx_ctx_t *ctx, ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); + if (ret != 0) + { + return ret; + } *val = (st1vafe3bx_fifo_sensor_tag_t) fifo_tag.tag_sensor; return ret; } -int32_t st1vafe3bx_fifo_out_raw_get(const st1vafe3bx_ctx_t *ctx, uint8_t *buff) +int32_t st1vafe3bx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -2125,7 +2453,7 @@ int32_t st1vafe3bx_fifo_out_raw_get(const st1vafe3bx_ctx_t *ctx, uint8_t *buff) return ret; } -int32_t st1vafe3bx_fifo_data_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fifo_data_get(const stmdev_ctx_t *ctx, const st1vafe3bx_md_t *md, const st1vafe3bx_fifo_mode_t *fmd, st1vafe3bx_fifo_data_t *data) @@ -2136,6 +2464,11 @@ int32_t st1vafe3bx_fifo_data_get(const st1vafe3bx_ctx_t *ctx, ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); + if (ret != 0) + { + return ret; + } + data->tag = fifo_tag.tag_sensor; switch (fifo_tag.tag_sensor) @@ -2143,6 +2476,11 @@ int32_t st1vafe3bx_fifo_data_get(const st1vafe3bx_ctx_t *ctx, case ST1VAFE3BX_TIMESTAMP_CFG_CHG_TAG: ret = st1vafe3bx_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } + data->cfg_chg.cfg_change = fifo_raw[0] >> 7; data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU; data->cfg_chg.bw = (fifo_raw[0] >> 1) & 0x3U; @@ -2163,6 +2501,12 @@ int32_t st1vafe3bx_fifo_data_get(const st1vafe3bx_ctx_t *ctx, * of 2 x 8-bits 3-axis XL at ODR/2 */ ret = st1vafe3bx_fifo_out_raw_get(ctx, fifo_raw); + + if (ret != 0) + { + return ret; + } + for (i = 0; i < 3; i++) { data->xl[0].raw[i] = (int16_t)fifo_raw[i] * 256U; @@ -2173,6 +2517,11 @@ int32_t st1vafe3bx_fifo_data_get(const st1vafe3bx_ctx_t *ctx, /* step counted + timestamp */ ret = st1vafe3bx_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } + data->pedo.steps = fifo_raw[1]; data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0]; @@ -2185,6 +2534,11 @@ int32_t st1vafe3bx_fifo_data_get(const st1vafe3bx_ctx_t *ctx, /* vAFE data (16 bit) if vafe_only mode is enabled */ ret = st1vafe3bx_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } + data->ah_bio.raw = (int16_t)fifo_raw[0] + (int16_t)fifo_raw[1] * 256U; data->ah_bio.mv = st1vafe3bx_from_lsb_to_mv(data->ah_bio.raw); break; @@ -2192,6 +2546,11 @@ int32_t st1vafe3bx_fifo_data_get(const st1vafe3bx_ctx_t *ctx, case ST1VAFE3BX_XL_AND_AH_VAFE1_TAG: ret = st1vafe3bx_fifo_out_raw_get(ctx, fifo_raw); + if (ret != 0) + { + return ret; + } + /* * XL data(12bit) + vAFE(12bit) if xl_only bit in FIFO WTM * is set else XL data only(16 bit) @@ -2281,7 +2640,7 @@ int32_t st1vafe3bx_fifo_data_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_ah_bio_config_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_ah_bio_config_set(const stmdev_ctx_t *ctx, st1vafe3bx_ah_bio_config_t val) { st1vafe3bx_ah_bio_cfg1_t cfg1; @@ -2371,7 +2730,7 @@ int32_t st1vafe3bx_ah_bio_config_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_ah_bio_config_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_ah_bio_config_get(const stmdev_ctx_t *ctx, st1vafe3bx_ah_bio_config_t *val) { st1vafe3bx_ah_bio_cfg1_t cfg1; @@ -2457,18 +2816,27 @@ int32_t st1vafe3bx_ah_bio_config_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_enter_vafe_only(st1vafe3bx_ctx_t *ctx) +int32_t st1vafe3bx_enter_vafe_only(const stmdev_ctx_t *ctx) { st1vafe3bx_ah_bio_cfg2_t cfg2; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&cfg2, 1); + if (ret != 0) + { + return ret; + } + cfg2.ah_bio_en = 1; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&cfg2, 1); - if (ret == 0) + if (ret == 0 && ctx->priv_data != NULL) + { + ((st1vafe3bx_priv_t *)(ctx->priv_data))->vafe_only = 1; + } + else { - ctx->vafe_only = 1; + ret = -1; } return ret; @@ -2481,18 +2849,27 @@ int32_t st1vafe3bx_enter_vafe_only(st1vafe3bx_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_exit_vafe_only(st1vafe3bx_ctx_t *ctx) +int32_t st1vafe3bx_exit_vafe_only(const stmdev_ctx_t *ctx) { st1vafe3bx_ah_bio_cfg2_t cfg2; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&cfg2, 1); + if (ret != 0) + { + return ret; + } + cfg2.ah_bio_en = 0; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&cfg2, 1); - if (ret == 0) + if (ret == 0 && ctx->priv_data != NULL) + { + ((st1vafe3bx_priv_t *)(ctx->priv_data))->vafe_only = 0; + } + else { - ctx->vafe_only = 0; + ret = -1; } return ret; @@ -2506,13 +2883,17 @@ int32_t st1vafe3bx_exit_vafe_only(st1vafe3bx_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_ah_bio_active(const st1vafe3bx_ctx_t *ctx, uint8_t filter_on) +int32_t st1vafe3bx_ah_bio_active(const stmdev_ctx_t *ctx, uint8_t filter_on) { st1vafe3bx_ah_bio_cfg3_t cfg3; st1vafe3bx_ctrl3_t ctrl3; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3, (uint8_t *)&cfg3, 1); + if (ret != 0) + { + return ret; + } cfg3.ah_bio_active = 0; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3, (uint8_t *)&cfg3, 1); @@ -2522,6 +2903,10 @@ int32_t st1vafe3bx_ah_bio_active(const st1vafe3bx_ctx_t *ctx, uint8_t filter_on) } ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } ctrl3.hp_en = filter_on; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1); @@ -2550,7 +2935,7 @@ int32_t st1vafe3bx_ah_bio_active(const st1vafe3bx_ctx_t *ctx, uint8_t filter_on) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_stpcnt_mode_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_stpcnt_mode_set(const stmdev_ctx_t *ctx, st1vafe3bx_stpcnt_mode_t val) { st1vafe3bx_emb_func_en_a_t emb_func_en_a; @@ -2560,29 +2945,41 @@ int32_t st1vafe3bx_stpcnt_mode_set(const st1vafe3bx_ctx_t *ctx, int32_t ret; ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK); - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A, - (uint8_t *)&emb_func_en_a, 1); - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN, - (uint8_t *)&emb_func_fifo_en, 1); - - if ((val.false_step_rej == PROPERTY_ENABLE) - && ((emb_func_en_a.mlc_before_fsm_en & - emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) + if (ret == 0) { - emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN, + (uint8_t *)&emb_func_fifo_en, 1); } - emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo; - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN, - (uint8_t *)&emb_func_fifo_en, 1); + if (ret == 0) + { + if ((val.false_step_rej == PROPERTY_ENABLE) + && ((emb_func_en_a.mlc_before_fsm_en & + emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) + { + emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + } - emb_func_en_a.pedo_en = val.step_counter_enable; - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A, - (uint8_t *)&emb_func_en_a, 1); + emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo; + ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN, + (uint8_t *)&emb_func_fifo_en, 1); + + emb_func_en_a.pedo_en = val.step_counter_enable; + ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + } ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK); + + if (ret != 0) + { + return ret; + } + ret += st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_EMB_ADV_PG_0 + ST1VAFE3BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); @@ -2606,7 +3003,7 @@ int32_t st1vafe3bx_stpcnt_mode_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_stpcnt_mode_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_stpcnt_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_stpcnt_mode_t *val) { st1vafe3bx_emb_func_en_a_t emb_func_en_a; @@ -2614,15 +3011,26 @@ int32_t st1vafe3bx_stpcnt_mode_get(const st1vafe3bx_ctx_t *ctx, int32_t ret; ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK); - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A, - (uint8_t *)&emb_func_en_a, 1); + if (ret == 0) + { + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + } ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + ret += st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_EMB_ADV_PG_0 + ST1VAFE3BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); - val->false_step_rej = pedo_cmd_reg.fp_rejection_en; - val->step_counter_enable = emb_func_en_a.pedo_en; + if (ret == 0) + { + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + } return ret; } @@ -2635,15 +3043,23 @@ int32_t st1vafe3bx_stpcnt_mode_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_stpcnt_steps_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val) +int32_t st1vafe3bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK); - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_STEP_COUNTER_L, &buff[0], 2); + if (ret == 0) + { + ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_STEP_COUNTER_L, &buff[0], 2); + } ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -2658,7 +3074,7 @@ int32_t st1vafe3bx_stpcnt_steps_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_stpcnt_rst_step_set(const st1vafe3bx_ctx_t *ctx) +int32_t st1vafe3bx_stpcnt_rst_step_set(const stmdev_ctx_t *ctx) { st1vafe3bx_emb_func_src_t emb_func_src; int32_t ret; @@ -2668,6 +3084,9 @@ int32_t st1vafe3bx_stpcnt_rst_step_set(const st1vafe3bx_ctx_t *ctx) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + if (ret == 0) + { emb_func_src.pedo_rst_step = 1; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); @@ -2686,7 +3105,7 @@ int32_t st1vafe3bx_stpcnt_rst_step_set(const st1vafe3bx_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_stpcnt_debounce_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) +int32_t st1vafe3bx_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val) { st1vafe3bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; int32_t ret; @@ -2707,7 +3126,7 @@ int32_t st1vafe3bx_stpcnt_debounce_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_stpcnt_debounce_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) { st1vafe3bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; int32_t ret; @@ -2715,7 +3134,10 @@ int32_t st1vafe3bx_stpcnt_debounce_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val ret = st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_EMB_ADV_PG_0 + ST1VAFE3BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); - *val = pedo_deb_steps_conf.deb_step; + if (ret == 0) + { + *val = pedo_deb_steps_conf.deb_step; + } return ret; } @@ -2728,7 +3150,7 @@ int32_t st1vafe3bx_stpcnt_debounce_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_stpcnt_period_set(const st1vafe3bx_ctx_t *ctx, uint16_t val) +int32_t st1vafe3bx_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -2751,7 +3173,7 @@ int32_t st1vafe3bx_stpcnt_period_set(const st1vafe3bx_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_stpcnt_period_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val) +int32_t st1vafe3bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -2759,6 +3181,11 @@ int32_t st1vafe3bx_stpcnt_period_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val) ret = st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_EMB_ADV_PG_0 + ST1VAFE3BX_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -2784,7 +3211,7 @@ int32_t st1vafe3bx_stpcnt_period_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_tilt_mode_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) +int32_t st1vafe3bx_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { st1vafe3bx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -2794,6 +3221,9 @@ int32_t st1vafe3bx_tilt_mode_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { emb_func_en_a.tilt_en = val; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); @@ -2812,7 +3242,7 @@ int32_t st1vafe3bx_tilt_mode_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_tilt_mode_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { st1vafe3bx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -2822,6 +3252,9 @@ int32_t st1vafe3bx_tilt_mode_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { *val = emb_func_en_a.tilt_en; } @@ -2849,7 +3282,7 @@ int32_t st1vafe3bx_tilt_mode_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_sigmot_mode_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) +int32_t st1vafe3bx_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { st1vafe3bx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -2859,6 +3292,9 @@ int32_t st1vafe3bx_sigmot_mode_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { emb_func_en_a.sign_motion_en = val; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); @@ -2877,7 +3313,7 @@ int32_t st1vafe3bx_sigmot_mode_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_sigmot_mode_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { st1vafe3bx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -2887,6 +3323,9 @@ int32_t st1vafe3bx_sigmot_mode_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { *val = emb_func_en_a.sign_motion_en; } @@ -2917,7 +3356,7 @@ int32_t st1vafe3bx_sigmot_mode_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_ff_duration_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) +int32_t st1vafe3bx_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { st1vafe3bx_wake_up_dur_t wake_up_dur; st1vafe3bx_free_fall_t free_fall; @@ -2925,22 +3364,20 @@ int32_t st1vafe3bx_ff_duration_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - - if (ret == 0) + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FREE_FALL, + (uint8_t *)&free_fall, 1); + if (ret != 0) { - wake_up_dur.ff_dur = (val >> 5) & 0x1U; - ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + return ret; } - if (ret == 0) - { - ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FREE_FALL, + wake_up_dur.ff_dur = (val >> 5) & 0x1U; + free_fall.ff_dur = val & 0x1FU; + + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FREE_FALL, (uint8_t *)&free_fall, 1); - free_fall.ff_dur = val & 0x1FU; - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FREE_FALL, - (uint8_t *)&free_fall, 1); - } return ret; } @@ -2955,7 +3392,7 @@ int32_t st1vafe3bx_ff_duration_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_ff_duration_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { st1vafe3bx_wake_up_dur_t wake_up_dur; st1vafe3bx_free_fall_t free_fall; @@ -2966,6 +3403,11 @@ int32_t st1vafe3bx_ff_duration_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } + *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur; return ret; @@ -2980,7 +3422,7 @@ int32_t st1vafe3bx_ff_duration_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_ff_thresholds_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_ff_thresholds_set(const stmdev_ctx_t *ctx, st1vafe3bx_ff_thresholds_t val) { st1vafe3bx_free_fall_t free_fall; @@ -2988,6 +3430,12 @@ int32_t st1vafe3bx_ff_thresholds_set(const st1vafe3bx_ctx_t *ctx, ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FREE_FALL, (uint8_t *)&free_fall, 1); + + if (ret != 0) + { + return ret; + } + free_fall.ff_ths = ((uint8_t)val & 0x7U); ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FREE_FALL, (uint8_t *)&free_fall, 1); @@ -3004,7 +3452,7 @@ int32_t st1vafe3bx_ff_thresholds_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_ff_thresholds_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_ff_thresholds_get(const stmdev_ctx_t *ctx, st1vafe3bx_ff_thresholds_t *val) { st1vafe3bx_free_fall_t free_fall; @@ -3013,6 +3461,11 @@ int32_t st1vafe3bx_ff_thresholds_get(const st1vafe3bx_ctx_t *ctx, ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } + switch (free_fall.ff_ths) { case 0x0: @@ -3075,7 +3528,7 @@ int32_t st1vafe3bx_ff_thresholds_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_sixd_config_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_sixd_config_set(const stmdev_ctx_t *ctx, st1vafe3bx_sixd_config_t val) { st1vafe3bx_sixd_t sixd; @@ -3101,7 +3554,7 @@ int32_t st1vafe3bx_sixd_config_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_sixd_config_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_sixd_config_get(const stmdev_ctx_t *ctx, st1vafe3bx_sixd_config_t *val) { st1vafe3bx_sixd_t sixd; @@ -3109,6 +3562,11 @@ int32_t st1vafe3bx_sixd_config_get(const st1vafe3bx_ctx_t *ctx, ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_SIXD, (uint8_t *)&sixd, 1); + if (ret != 0) + { + return ret; + } + val->mode = (st1vafe3bx_mode_t)sixd.d4d_en; switch ((sixd.d6d_ths)) @@ -3157,7 +3615,7 @@ int32_t st1vafe3bx_sixd_config_get(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_wakeup_config_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_wakeup_config_set(const stmdev_ctx_t *ctx, st1vafe3bx_wakeup_config_t val) { st1vafe3bx_wake_up_ths_t wup_ths; @@ -3226,7 +3684,7 @@ int32_t st1vafe3bx_wakeup_config_set(const st1vafe3bx_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t st1vafe3bx_wakeup_config_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_wakeup_config_get(const stmdev_ctx_t *ctx, st1vafe3bx_wakeup_config_t *val) { st1vafe3bx_wake_up_ths_t wup_ths; @@ -3244,41 +3702,42 @@ int32_t st1vafe3bx_wakeup_config_get(const st1vafe3bx_ctx_t *ctx, (uint8_t *)&wup_dur_ext, 1); ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1); + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1); - if (ret == 0) + if (ret != 0) { - switch (wup_dur.wake_dur) - { - case 0x0: - val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? - ST1VAFE3BX_3_ODR : ST1VAFE3BX_0_ODR; - break; - - case 0x1: - val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? - ST1VAFE3BX_7_ODR : ST1VAFE3BX_1_ODR; - break; + return ret; + } - case 0x2: - val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? - ST1VAFE3BX_11_ODR : ST1VAFE3BX_2_ODR; - break; + switch (wup_dur.wake_dur) + { + case 0x0: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + ST1VAFE3BX_3_ODR : ST1VAFE3BX_0_ODR; + break; - case 0x3: - default: - val->wake_dur = ST1VAFE3BX_15_ODR; - break; - } + case 0x1: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + ST1VAFE3BX_7_ODR : ST1VAFE3BX_1_ODR; + break; - val->sleep_dur = wup_dur.sleep_dur; + case 0x2: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + ST1VAFE3BX_11_ODR : ST1VAFE3BX_2_ODR; + break; - val->wake_ths_weight = int_cfg.wake_ths_w; - val->wake_ths = wup_ths.wk_ths; - val->wake_enable = (st1vafe3bx_wake_enable_t)wup_ths.sleep_on; - val->inact_odr = (st1vafe3bx_inact_odr_t)ctrl4.inact_odr; + case 0x3: + default: + val->wake_dur = ST1VAFE3BX_15_ODR; + break; } + val->sleep_dur = wup_dur.sleep_dur; + val->wake_ths_weight = int_cfg.wake_ths_w; + val->wake_ths = wup_ths.wk_ths; + val->wake_enable = (st1vafe3bx_wake_enable_t)wup_ths.sleep_on; + val->inact_odr = (st1vafe3bx_inact_odr_t)ctrl4.inact_odr; + return ret; } @@ -3287,7 +3746,7 @@ int32_t st1vafe3bx_wakeup_config_get(const st1vafe3bx_ctx_t *ctx, * */ -int32_t st1vafe3bx_tap_config_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_tap_config_set(const stmdev_ctx_t *ctx, st1vafe3bx_tap_config_t val) { st1vafe3bx_tap_cfg0_t tap_cfg0; @@ -3345,7 +3804,7 @@ int32_t st1vafe3bx_tap_config_set(const st1vafe3bx_ctx_t *ctx, return ret; } -int32_t st1vafe3bx_tap_config_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_tap_config_get(const stmdev_ctx_t *ctx, st1vafe3bx_tap_config_t *val) { st1vafe3bx_tap_cfg0_t tap_cfg0; @@ -3408,7 +3867,7 @@ int32_t st1vafe3bx_tap_config_get(const st1vafe3bx_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_timestamp_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) +int32_t st1vafe3bx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { st1vafe3bx_interrupt_cfg_t int_cfg; int32_t ret; @@ -3434,13 +3893,19 @@ int32_t st1vafe3bx_timestamp_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_timestamp_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { st1vafe3bx_interrupt_cfg_t int_cfg; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1); + + if (ret != 0) + { + return ret; + } + *val = int_cfg.timestamp_en; return ret; @@ -3456,12 +3921,18 @@ int32_t st1vafe3bx_timestamp_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_timestamp_raw_get(const st1vafe3bx_ctx_t *ctx, uint32_t *val) +int32_t st1vafe3bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TIMESTAMP0, buff, 4); + + if (ret != 0) + { + return ret; + } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -3492,7 +3963,7 @@ int32_t st1vafe3bx_timestamp_raw_get(const st1vafe3bx_ctx_t *ctx, uint32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_long_cnt_flag_data_ready_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { st1vafe3bx_emb_func_status_t emb_func_status; @@ -3504,7 +3975,10 @@ int32_t st1vafe3bx_long_cnt_flag_data_ready_get(const st1vafe3bx_ctx_t *ctx, { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_STATUS, (uint8_t *)&emb_func_status, 1); + } + if (ret == 0) + { *val = emb_func_status.is_fsm_lc; } @@ -3521,7 +3995,7 @@ int32_t st1vafe3bx_long_cnt_flag_data_ready_get(const st1vafe3bx_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_emb_fsm_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) +int32_t st1vafe3bx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -3532,7 +4006,10 @@ int32_t st1vafe3bx_emb_fsm_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { emb_func_en_b.fsm_en = (uint8_t)val; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B, @@ -3552,7 +4029,7 @@ int32_t st1vafe3bx_emb_fsm_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_emb_fsm_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -3563,11 +4040,12 @@ int32_t st1vafe3bx_emb_fsm_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } - *val = emb_func_en_b.fsm_en; + if (ret == 0) + { - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + *val = emb_func_en_b.fsm_en; } ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK); @@ -3583,7 +4061,7 @@ int32_t st1vafe3bx_emb_fsm_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_enable_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_enable_set(const stmdev_ctx_t *ctx, st1vafe3bx_emb_fsm_enable_t *val) { st1vafe3bx_emb_func_en_b_t emb_func_en_b; @@ -3601,7 +4079,10 @@ int32_t st1vafe3bx_fsm_enable_set(const st1vafe3bx_ctx_t *ctx, { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { if ((val->fsm_enable.fsm1_en | val->fsm_enable.fsm2_en | val->fsm_enable.fsm3_en | @@ -3635,7 +4116,7 @@ int32_t st1vafe3bx_fsm_enable_set(const st1vafe3bx_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_enable_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_enable_get(const stmdev_ctx_t *ctx, st1vafe3bx_emb_fsm_enable_t *val) { int32_t ret; @@ -3662,7 +4143,7 @@ int32_t st1vafe3bx_fsm_enable_get(const st1vafe3bx_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_long_cnt_set(const st1vafe3bx_ctx_t *ctx, uint16_t val) +int32_t st1vafe3bx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -3690,7 +4171,7 @@ int32_t st1vafe3bx_long_cnt_set(const st1vafe3bx_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_long_cnt_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val) +int32_t st1vafe3bx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -3700,6 +4181,10 @@ int32_t st1vafe3bx_long_cnt_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FSM_LONG_COUNTER_L, buff, 2); + } + + if (ret == 0) + { *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -3716,7 +4201,7 @@ int32_t st1vafe3bx_long_cnt_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val) * @param val register FSM_STATUS_MAINPAGE * */ -int32_t st1vafe3bx_fsm_status_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_fsm_status_mainpage_t *val) { return st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FSM_STATUS_MAINPAGE, @@ -3731,7 +4216,7 @@ int32_t st1vafe3bx_fsm_status_get(const st1vafe3bx_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_out_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -3755,7 +4240,7 @@ int32_t st1vafe3bx_fsm_out_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_data_rate_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_data_rate_set(const stmdev_ctx_t *ctx, st1vafe3bx_fsm_val_odr_t val) { st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2; @@ -3765,16 +4250,24 @@ int32_t st1vafe3bx_fsm_data_rate_set(const st1vafe3bx_ctx_t *ctx, ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&ah_bio_cfg2, 1); + if (ret != 0) + { + return ret; + } + ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK); if (ret == 0) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FSM_ODR, (uint8_t *)&fsm_odr_reg, 1); + } + if (ret == 0) + { fsm_odr_reg.fsm_odr = (uint8_t)val & 0xfU; - ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FSM_ODR, - (uint8_t *)&fsm_odr_reg, 1); + ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FSM_ODR, + (uint8_t *)&fsm_odr_reg, 1); } ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK); @@ -3790,7 +4283,7 @@ int32_t st1vafe3bx_fsm_data_rate_set(const st1vafe3bx_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_data_rate_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_data_rate_get(const stmdev_ctx_t *ctx, st1vafe3bx_fsm_val_odr_t *val) { st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2; @@ -3798,9 +4291,15 @@ int32_t st1vafe3bx_fsm_data_rate_get(const st1vafe3bx_ctx_t *ctx, int32_t ret; ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK); - ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FSM_ODR, - (uint8_t *)&fsm_odr_reg, 1); + + if (ret == 0) + { + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FSM_ODR, + (uint8_t *)&fsm_odr_reg, 1); + } + ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK); + ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&ah_bio_cfg2, 1); @@ -3879,7 +4378,7 @@ int32_t st1vafe3bx_fsm_data_rate_get(const st1vafe3bx_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_init_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) +int32_t st1vafe3bx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { st1vafe3bx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -3890,7 +4389,10 @@ int32_t st1vafe3bx_fsm_init_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { emb_func_init_b.fsm_init = (uint8_t)val; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_INIT_B, @@ -3910,7 +4412,7 @@ int32_t st1vafe3bx_fsm_init_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_init_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { st1vafe3bx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -3921,7 +4423,10 @@ int32_t st1vafe3bx_fsm_init_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { *val = emb_func_init_b.fsm_init; } @@ -3938,7 +4443,7 @@ int32_t st1vafe3bx_fsm_init_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_fifo_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) +int32_t st1vafe3bx_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val) { st1vafe3bx_emb_func_fifo_en_t fifo_reg; int32_t ret; @@ -3949,6 +4454,10 @@ int32_t st1vafe3bx_fsm_fifo_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); + } + + if (ret == 0) + { fifo_reg.fsm_fifo_en = val; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); @@ -3967,7 +4476,7 @@ int32_t st1vafe3bx_fsm_fifo_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_fifo_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { st1vafe3bx_emb_func_fifo_en_t fifo_reg; int32_t ret; @@ -3978,6 +4487,10 @@ int32_t st1vafe3bx_fsm_fifo_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); + } + + if (ret == 0) + { *val = fifo_reg.fsm_fifo_en; } @@ -3997,7 +4510,7 @@ int32_t st1vafe3bx_fsm_fifo_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_long_cnt_int_value_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -4021,13 +4534,19 @@ int32_t st1vafe3bx_long_cnt_int_value_set(const st1vafe3bx_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_long_cnt_int_value_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; ret = st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_FSM_LC_TIMEOUT_L, buff, 2); + + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -4042,7 +4561,7 @@ int32_t st1vafe3bx_long_cnt_int_value_get(const st1vafe3bx_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_programs_num_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) +int32_t st1vafe3bx_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -4059,7 +4578,7 @@ int32_t st1vafe3bx_fsm_programs_num_set(const st1vafe3bx_ctx_t *ctx, uint8_t val * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_programs_num_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -4077,7 +4596,7 @@ int32_t st1vafe3bx_fsm_programs_num_get(const st1vafe3bx_ctx_t *ctx, uint8_t *va * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_start_address_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -4099,13 +4618,18 @@ int32_t st1vafe3bx_fsm_start_address_set(const st1vafe3bx_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_fsm_start_address_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; ret = st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_FSM_START_ADD_L, buff, 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -4134,7 +4658,7 @@ int32_t st1vafe3bx_fsm_start_address_get(const st1vafe3bx_ctx_t *ctx, * in EMB_FUNC_INIT_A * */ -int32_t st1vafe3bx_mlc_set(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_mlc_mode_t val) +int32_t st1vafe3bx_mlc_set(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_mode_t val) { st1vafe3bx_emb_func_en_a_t emb_en_a; st1vafe3bx_emb_func_en_b_t emb_en_b; @@ -4148,7 +4672,10 @@ int32_t st1vafe3bx_mlc_set(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_mlc_mode_t va (uint8_t *)&emb_en_a, 1); ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } + if (ret == 0) + { switch (val) { case ST1VAFE3BX_MLC_OFF: @@ -4188,7 +4715,7 @@ int32_t st1vafe3bx_mlc_set(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_mlc_mode_t va * in EMB_FUNC_INIT_A * */ -int32_t st1vafe3bx_mlc_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_mlc_mode_t *val) +int32_t st1vafe3bx_mlc_get(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_mode_t *val) { st1vafe3bx_emb_func_en_a_t emb_en_a; st1vafe3bx_emb_func_en_b_t emb_en_b; @@ -4202,7 +4729,10 @@ int32_t st1vafe3bx_mlc_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_mlc_mode_t *v (uint8_t *)&emb_en_a, 1); ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } + if (ret == 0) + { if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) { *val = ST1VAFE3BX_MLC_OFF; @@ -4233,7 +4763,7 @@ int32_t st1vafe3bx_mlc_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_mlc_mode_t *v * @param val register MLC_STATUS_MAINPAGE * */ -int32_t st1vafe3bx_mlc_status_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_mlc_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_status_mainpage_t *val) { return st1vafe3bx_read_reg(ctx, ST1VAFE3BX_MLC_STATUS_MAINPAGE, @@ -4247,7 +4777,7 @@ int32_t st1vafe3bx_mlc_status_get(const st1vafe3bx_ctx_t *ctx, * @param uint8_t * : buffer that stores data read * */ -int32_t st1vafe3bx_mlc_out_get(const st1vafe3bx_ctx_t *ctx, uint8_t *buff) +int32_t st1vafe3bx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -4271,7 +4801,7 @@ int32_t st1vafe3bx_mlc_out_get(const st1vafe3bx_ctx_t *ctx, uint8_t *buff) * reg EMB_FUNC_ODR_CFG_C * */ -int32_t st1vafe3bx_mlc_data_rate_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_mlc_data_rate_set(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_odr_val_t val) { st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2; @@ -4280,12 +4810,21 @@ int32_t st1vafe3bx_mlc_data_rate_set(const st1vafe3bx_ctx_t *ctx, ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&ah_bio_cfg2, 1); + + if (ret != 0) + { + return ret; + } + ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK); if (ret == 0) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_MLC_ODR, (uint8_t *)®, 1); + } + if (ret == 0) + { reg.mlc_odr = (uint8_t)val & 0xfU; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_MLC_ODR, (uint8_t *)®, 1); } @@ -4303,7 +4842,7 @@ int32_t st1vafe3bx_mlc_data_rate_set(const st1vafe3bx_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t st1vafe3bx_mlc_data_rate_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_mlc_data_rate_get(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_odr_val_t *val) { st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2; @@ -4312,12 +4851,21 @@ int32_t st1vafe3bx_mlc_data_rate_get(const st1vafe3bx_ctx_t *ctx, ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&ah_bio_cfg2, 1); + + if (ret != 0) + { + return ret; + } + ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK); if (ret == 0) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_MLC_ODR, (uint8_t *)®, 1); + } + if (ret == 0) + { /* depends on vAFE mode only enabled */ if (ah_bio_cfg2.ah_bio_en == 0x1U) { @@ -4385,7 +4933,7 @@ int32_t st1vafe3bx_mlc_data_rate_get(const st1vafe3bx_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_mlc_fifo_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) +int32_t st1vafe3bx_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val) { st1vafe3bx_emb_func_fifo_en_t fifo_reg; int32_t ret; @@ -4396,6 +4944,10 @@ int32_t st1vafe3bx_mlc_fifo_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); + } + + if (ret == 0) + { fifo_reg.mlc_fifo_en = val; ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); @@ -4414,7 +4966,7 @@ int32_t st1vafe3bx_mlc_fifo_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t st1vafe3bx_mlc_fifo_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) +int32_t st1vafe3bx_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { st1vafe3bx_emb_func_fifo_en_t fifo_reg; int32_t ret; @@ -4425,6 +4977,10 @@ int32_t st1vafe3bx_mlc_fifo_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) { ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1); + } + + if (ret == 0) + { *val = fifo_reg.mlc_fifo_en; } @@ -4437,5 +4993,3 @@ int32_t st1vafe3bx_mlc_fifo_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/st1vafe3bx_STdC/driver/st1vafe3bx_reg.h b/sensor/stmemsc/st1vafe3bx_STdC/driver/st1vafe3bx_reg.h index 4c16733..21adf1b 100644 --- a/sensor/stmemsc/st1vafe3bx_STdC/driver/st1vafe3bx_reg.h +++ b/sensor/stmemsc/st1vafe3bx_STdC/driver/st1vafe3bx_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -115,13 +114,6 @@ typedef int32_t (*stmdev_read_ptr)(void *ctx, uint8_t reg, uint8_t *data, uint16_t len); typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); -/** - * @} - * - */ - -#endif /* MEMS_SHARED_TYPES */ - /* * Proprietary read/write device context structure */ @@ -136,8 +128,15 @@ typedef struct void *handle; /** private data **/ - uint8_t vafe_only; -} st1vafe3bx_ctx_t; + void *priv_data; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ #ifndef MEMS_UCF_SHARED_TYPES #define MEMS_UCF_SHARED_TYPES @@ -1995,10 +1994,10 @@ typedef union * them with a custom implementation. */ -int32_t st1vafe3bx_read_reg(const st1vafe3bx_ctx_t *ctx, uint8_t reg, +int32_t st1vafe3bx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t st1vafe3bx_write_reg(const st1vafe3bx_ctx_t *ctx, uint8_t reg, +int32_t st1vafe3bx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -2009,7 +2008,7 @@ float_t st1vafe3bx_from_fs16g_to_mg(int16_t lsb); float_t st1vafe3bx_from_lsb_to_celsius(int16_t lsb); float_t st1vafe3bx_from_lsb_to_mv(int16_t lsb); -int32_t st1vafe3bx_device_id_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2021,7 +2020,7 @@ typedef enum ST1VAFE3BX_VAFE_ONLY_LP = 0x04, /* Enable sensor in vAFE only mode - low performance */ ST1VAFE3BX_VAFE_ONLY_HP = 0x05, /* Enable sensor in vAFE only mode - high performance */ } st1vafe3bx_init_t; -int32_t st1vafe3bx_init_set(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_init_t val); +int32_t st1vafe3bx_init_set(const stmdev_ctx_t *ctx, st1vafe3bx_init_t val); typedef struct { @@ -2029,8 +2028,8 @@ typedef struct uint8_t pwr_ctrl_win : 4; /* Number of consecutive windows */ uint8_t pwr_ctrl_dur : 4; /* Duration threshold */ } st1vafe3bx_smart_power_t; -int32_t st1vafe3bx_smart_power_set(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_smart_power_t val); -int32_t st1vafe3bx_smart_power_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_smart_power_t *val); +int32_t st1vafe3bx_smart_power_set(const stmdev_ctx_t *ctx, st1vafe3bx_smart_power_t val); +int32_t st1vafe3bx_smart_power_get(const stmdev_ctx_t *ctx, st1vafe3bx_smart_power_t *val); typedef struct { @@ -2039,8 +2038,8 @@ typedef struct uint8_t drdy : 1; /* Accelerometer data ready */ uint8_t power_down : 1; /* Monitors power-down. */ } st1vafe3bx_status_t; -int32_t st1vafe3bx_status_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_status_t *val); -int32_t st1vafe3bx_drdy_status_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_status_t *val); +int32_t st1vafe3bx_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_status_t *val); +int32_t st1vafe3bx_drdy_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_status_t *val); typedef struct { @@ -2049,18 +2048,15 @@ typedef struct uint8_t is_sigmot : 1; /* Significant motion detected */ uint8_t is_fsm_lc : 1; /* FSM long counter timeout */ } st1vafe3bx_embedded_status_t; -int32_t st1vafe3bx_embedded_status_get(const st1vafe3bx_ctx_t *ctx, - st1vafe3bx_embedded_status_t *val); +int32_t st1vafe3bx_embedded_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_embedded_status_t *val); typedef enum { ST1VAFE3BX_DRDY_LATCHED = 0x0, ST1VAFE3BX_DRDY_PULSED = 0x1, } st1vafe3bx_data_ready_mode_t; -int32_t st1vafe3bx_data_ready_mode_set(const st1vafe3bx_ctx_t *ctx, - st1vafe3bx_data_ready_mode_t val); -int32_t st1vafe3bx_data_ready_mode_get(const st1vafe3bx_ctx_t *ctx, - st1vafe3bx_data_ready_mode_t *val); +int32_t st1vafe3bx_data_ready_mode_set(const stmdev_ctx_t *ctx, st1vafe3bx_data_ready_mode_t val); +int32_t st1vafe3bx_data_ready_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_data_ready_mode_t *val); typedef enum { @@ -2123,11 +2119,11 @@ typedef struct st1vafe3bx_odr_t odr; st1vafe3bx_bw_t bw; } st1vafe3bx_md_t; -int32_t st1vafe3bx_mode_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_mode_set(const stmdev_ctx_t *ctx, const st1vafe3bx_md_t *val); -int32_t st1vafe3bx_mode_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_md_t *val); +int32_t st1vafe3bx_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_md_t *val); -int32_t st1vafe3bx_trigger_sw(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_trigger_sw(const stmdev_ctx_t *ctx, const st1vafe3bx_md_t *md); typedef struct @@ -2157,7 +2153,7 @@ typedef struct uint8_t fifo_ovr : 1; uint8_t fifo_th : 1; } st1vafe3bx_all_sources_t; -int32_t st1vafe3bx_all_sources_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_all_sources_get(const stmdev_ctx_t *ctx, st1vafe3bx_all_sources_t *val); typedef struct @@ -2165,7 +2161,7 @@ typedef struct float_t mg[3]; int16_t raw[3]; } st1vafe3bx_xl_data_t; -int32_t st1vafe3bx_xl_data_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_xl_data_get(const stmdev_ctx_t *ctx, const st1vafe3bx_md_t *md, st1vafe3bx_xl_data_t *data); @@ -2174,7 +2170,7 @@ typedef struct float_t mv; int16_t raw; } st1vafe3bx_ah_bio_data_t; -int32_t st1vafe3bx_ah_bio_data_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_ah_bio_data_get(const stmdev_ctx_t *ctx, st1vafe3bx_ah_bio_data_t *data); typedef enum @@ -2183,13 +2179,13 @@ typedef enum ST1VAFE3BX_XL_ST_POSITIVE = 0x1, ST1VAFE3BX_XL_ST_NEGATIVE = 0x2, } st1vafe3bx_xl_self_test_t; -int32_t st1vafe3bx_self_test_sign_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_self_test_sign_set(const stmdev_ctx_t *ctx, st1vafe3bx_xl_self_test_t val); -int32_t st1vafe3bx_self_test_start(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_self_test_stop(const st1vafe3bx_ctx_t *ctx); +int32_t st1vafe3bx_self_test_start(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_self_test_stop(const stmdev_ctx_t *ctx); -int32_t st1vafe3bx_enter_deep_power_down(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_exit_deep_power_down(const st1vafe3bx_ctx_t *ctx); +int32_t st1vafe3bx_enter_deep_power_down(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_exit_deep_power_down(const stmdev_ctx_t *ctx); typedef struct { @@ -2203,9 +2199,9 @@ typedef struct uint8_t asf_on : 1; uint8_t drstdaa_en : 1; } st1vafe3bx_i3c_cfg_t; -int32_t st1vafe3bx_i3c_configure_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_i3c_configure_set(const stmdev_ctx_t *ctx, const st1vafe3bx_i3c_cfg_t *val); -int32_t st1vafe3bx_i3c_configure_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_i3c_configure_get(const stmdev_ctx_t *ctx, st1vafe3bx_i3c_cfg_t *val); typedef enum @@ -2213,18 +2209,18 @@ typedef enum ST1VAFE3BX_MAIN_MEM_BANK = 0x0, ST1VAFE3BX_EMBED_FUNC_MEM_BANK = 0x1, } st1vafe3bx_mem_bank_t; -int32_t st1vafe3bx_mem_bank_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_mem_bank_set(const stmdev_ctx_t *ctx, st1vafe3bx_mem_bank_t val); -int32_t st1vafe3bx_mem_bank_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_mem_bank_get(const stmdev_ctx_t *ctx, st1vafe3bx_mem_bank_t *val); -int32_t st1vafe3bx_ln_pg_write(const st1vafe3bx_ctx_t *ctx, uint16_t address, +int32_t st1vafe3bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t st1vafe3bx_ln_pg_read(const st1vafe3bx_ctx_t *ctx, uint16_t address, +int32_t st1vafe3bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t st1vafe3bx_ext_clk_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_ext_clk_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -2233,9 +2229,9 @@ typedef struct uint8_t cs_pull_up : 1; /* 1 = pull up enable */ uint8_t int_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ } st1vafe3bx_pin_conf_t; -int32_t st1vafe3bx_pin_conf_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_pin_conf_set(const stmdev_ctx_t *ctx, const st1vafe3bx_pin_conf_t *val); -int32_t st1vafe3bx_pin_conf_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_pin_conf_get(const stmdev_ctx_t *ctx, st1vafe3bx_pin_conf_t *val); typedef enum @@ -2243,9 +2239,9 @@ typedef enum ST1VAFE3BX_ACTIVE_HIGH = 0x0, ST1VAFE3BX_ACTIVE_LOW = 0x1, } st1vafe3bx_int_pin_polarity_t; -int32_t st1vafe3bx_int_pin_polarity_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_int_pin_polarity_set(const stmdev_ctx_t *ctx, st1vafe3bx_int_pin_polarity_t val); -int32_t st1vafe3bx_int_pin_polarity_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_int_pin_polarity_get(const stmdev_ctx_t *ctx, st1vafe3bx_int_pin_polarity_t *val); typedef enum @@ -2253,9 +2249,9 @@ typedef enum ST1VAFE3BX_SPI_4_WIRE = 0x0, /* SPI 4 wires */ ST1VAFE3BX_SPI_3_WIRE = 0x1, /* SPI 3 wires */ } st1vafe3bx_spi_mode; -int32_t st1vafe3bx_spi_mode_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_spi_mode_set(const stmdev_ctx_t *ctx, st1vafe3bx_spi_mode val); -int32_t st1vafe3bx_spi_mode_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_spi_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_spi_mode *val); typedef struct @@ -2273,9 +2269,9 @@ typedef struct uint8_t emb_function : 1; /* Embedded Function */ uint8_t timestamp : 1; /* Timestamp */ } st1vafe3bx_pin_int_route_t; -int32_t st1vafe3bx_pin_int_route_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_pin_int_route_set(const stmdev_ctx_t *ctx, const st1vafe3bx_pin_int_route_t *val); -int32_t st1vafe3bx_pin_int_route_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_pin_int_route_get(const stmdev_ctx_t *ctx, st1vafe3bx_pin_int_route_t *val); typedef struct @@ -2285,9 +2281,9 @@ typedef struct uint8_t sig_mot : 1; /* route significant motion event on INT pad */ uint8_t fsm_lc : 1; /* route FSM long counter event on INT pad */ } st1vafe3bx_emb_pin_int_route_t; -int32_t st1vafe3bx_emb_pin_int_route_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_emb_pin_int_route_set(const stmdev_ctx_t *ctx, const st1vafe3bx_emb_pin_int_route_t *val); -int32_t st1vafe3bx_emb_pin_int_route_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_emb_pin_int_route_get(const stmdev_ctx_t *ctx, st1vafe3bx_emb_pin_int_route_t *val); typedef enum @@ -2303,9 +2299,9 @@ typedef struct uint8_t sleep_status_on_int : 1; /* route sleep_status on interrupt */ uint8_t dis_rst_lir_all_int : 1; /* disable LIR reset when reading ALL_INT_SRC */ } st1vafe3bx_int_config_t; -int32_t st1vafe3bx_int_config_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_int_config_set(const stmdev_ctx_t *ctx, const st1vafe3bx_int_config_t *val); -int32_t st1vafe3bx_int_config_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_int_config_get(const stmdev_ctx_t *ctx, st1vafe3bx_int_config_t *val); typedef enum @@ -2313,9 +2309,9 @@ typedef enum ST1VAFE3BX_EMBEDDED_INT_LEVEL = 0x0, ST1VAFE3BX_EMBEDDED_INT_LATCHED = 0x1, } st1vafe3bx_embedded_int_config_t; -int32_t st1vafe3bx_embedded_int_cfg_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_embedded_int_cfg_set(const stmdev_ctx_t *ctx, st1vafe3bx_embedded_int_config_t val); -int32_t st1vafe3bx_embedded_int_cfg_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_embedded_int_cfg_get(const stmdev_ctx_t *ctx, st1vafe3bx_embedded_int_config_t *val); typedef struct @@ -2364,13 +2360,13 @@ typedef struct } bdr_xl; /* accelerometer batch data rate*/ } batch; } st1vafe3bx_fifo_mode_t; -int32_t st1vafe3bx_fifo_mode_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fifo_mode_set(const stmdev_ctx_t *ctx, st1vafe3bx_fifo_mode_t val); -int32_t st1vafe3bx_fifo_mode_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fifo_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_fifo_mode_t *val); -int32_t st1vafe3bx_fifo_data_level_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val); -int32_t st1vafe3bx_fifo_wtm_flag_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t st1vafe3bx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2386,10 +2382,10 @@ typedef enum ST1VAFE3BX_AH_VAFE_ONLY_TAG = 0x1E, ST1VAFE3BX_XL_AND_AH_VAFE1_TAG = 0x1F, } st1vafe3bx_fifo_sensor_tag_t; -int32_t st1vafe3bx_fifo_sensor_tag_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, st1vafe3bx_fifo_sensor_tag_t *val); -int32_t st1vafe3bx_fifo_out_raw_get(const st1vafe3bx_ctx_t *ctx, uint8_t *buff); +int32_t st1vafe3bx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef struct { @@ -2423,7 +2419,7 @@ typedef struct uint32_t timestamp; } cfg_chg; } st1vafe3bx_fifo_data_t; -int32_t st1vafe3bx_fifo_data_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fifo_data_get(const stmdev_ctx_t *ctx, const st1vafe3bx_md_t *md, const st1vafe3bx_fifo_mode_t *fmd, st1vafe3bx_fifo_data_t *data); @@ -2458,14 +2454,19 @@ typedef struct ST1VAFE3BX_GAIN_16 = 0x3, } gain; } st1vafe3bx_ah_bio_config_t; -int32_t st1vafe3bx_ah_bio_config_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_ah_bio_config_set(const stmdev_ctx_t *ctx, st1vafe3bx_ah_bio_config_t val); -int32_t st1vafe3bx_ah_bio_config_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_ah_bio_config_get(const stmdev_ctx_t *ctx, st1vafe3bx_ah_bio_config_t *val); -int32_t st1vafe3bx_enter_vafe_only(st1vafe3bx_ctx_t *ctx); -int32_t st1vafe3bx_exit_vafe_only(st1vafe3bx_ctx_t *ctx); -int32_t st1vafe3bx_ah_bio_active(const st1vafe3bx_ctx_t *ctx, uint8_t filter_on); +typedef struct +{ + uint8_t vafe_only; +} st1vafe3bx_priv_t; + +int32_t st1vafe3bx_enter_vafe_only(const stmdev_ctx_t *ctx); +int32_t st1vafe3bx_exit_vafe_only(const stmdev_ctx_t *ctx); +int32_t st1vafe3bx_ah_bio_active(const stmdev_ctx_t *ctx, uint8_t filter_on); typedef struct { @@ -2473,29 +2474,29 @@ typedef struct uint8_t step_counter_enable : 1; uint8_t step_counter_in_fifo : 1; } st1vafe3bx_stpcnt_mode_t; -int32_t st1vafe3bx_stpcnt_mode_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_stpcnt_mode_set(const stmdev_ctx_t *ctx, st1vafe3bx_stpcnt_mode_t val); -int32_t st1vafe3bx_stpcnt_mode_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_stpcnt_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_stpcnt_mode_t *val); -int32_t st1vafe3bx_stpcnt_steps_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val); +int32_t st1vafe3bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t st1vafe3bx_stpcnt_rst_step_set(const st1vafe3bx_ctx_t *ctx); +int32_t st1vafe3bx_stpcnt_rst_step_set(const stmdev_ctx_t *ctx); -int32_t st1vafe3bx_stpcnt_debounce_set(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_stpcnt_debounce_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t st1vafe3bx_stpcnt_period_set(const st1vafe3bx_ctx_t *ctx, uint16_t val); -int32_t st1vafe3bx_stpcnt_period_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val); +int32_t st1vafe3bx_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t st1vafe3bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t st1vafe3bx_tilt_mode_set(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_tilt_mode_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); -int32_t st1vafe3bx_sigmot_mode_set(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_sigmot_mode_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t st1vafe3bx_ff_duration_set(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_ff_duration_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2508,9 +2509,9 @@ typedef enum ST1VAFE3BX_469_mg = 0x6, ST1VAFE3BX_500_mg = 0x7, } st1vafe3bx_ff_thresholds_t; -int32_t st1vafe3bx_ff_thresholds_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_ff_thresholds_set(const stmdev_ctx_t *ctx, st1vafe3bx_ff_thresholds_t val); -int32_t st1vafe3bx_ff_thresholds_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_ff_thresholds_get(const stmdev_ctx_t *ctx, st1vafe3bx_ff_thresholds_t *val); typedef enum @@ -2533,9 +2534,9 @@ typedef struct st1vafe3bx_mode_t mode; } st1vafe3bx_sixd_config_t; -int32_t st1vafe3bx_sixd_config_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_sixd_config_set(const stmdev_ctx_t *ctx, st1vafe3bx_sixd_config_t val); -int32_t st1vafe3bx_sixd_config_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_sixd_config_get(const stmdev_ctx_t *ctx, st1vafe3bx_sixd_config_t *val); typedef enum @@ -2573,9 +2574,9 @@ typedef struct st1vafe3bx_inact_odr_t inact_odr; } st1vafe3bx_wakeup_config_t; -int32_t st1vafe3bx_wakeup_config_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_wakeup_config_set(const stmdev_ctx_t *ctx, st1vafe3bx_wakeup_config_t val); -int32_t st1vafe3bx_wakeup_config_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_wakeup_config_get(const stmdev_ctx_t *ctx, st1vafe3bx_wakeup_config_t *val); typedef enum @@ -2605,37 +2606,37 @@ typedef struct uint8_t triple_tap_on : 1; /* enable triple tap */ } st1vafe3bx_tap_config_t; -int32_t st1vafe3bx_tap_config_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_tap_config_set(const stmdev_ctx_t *ctx, st1vafe3bx_tap_config_t val); -int32_t st1vafe3bx_tap_config_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_tap_config_get(const stmdev_ctx_t *ctx, st1vafe3bx_tap_config_t *val); -int32_t st1vafe3bx_timestamp_set(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_timestamp_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t st1vafe3bx_timestamp_raw_get(const st1vafe3bx_ctx_t *ctx, uint32_t *val); +int32_t st1vafe3bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); -int32_t st1vafe3bx_long_cnt_flag_data_ready_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t st1vafe3bx_emb_fsm_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_emb_fsm_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { st1vafe3bx_fsm_enable_t fsm_enable; } st1vafe3bx_emb_fsm_enable_t; -int32_t st1vafe3bx_fsm_enable_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_enable_set(const stmdev_ctx_t *ctx, st1vafe3bx_emb_fsm_enable_t *val); -int32_t st1vafe3bx_fsm_enable_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_enable_get(const stmdev_ctx_t *ctx, st1vafe3bx_emb_fsm_enable_t *val); -int32_t st1vafe3bx_long_cnt_set(const st1vafe3bx_ctx_t *ctx, uint16_t val); -int32_t st1vafe3bx_long_cnt_get(const st1vafe3bx_ctx_t *ctx, uint16_t *val); +int32_t st1vafe3bx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t st1vafe3bx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t st1vafe3bx_fsm_status_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_fsm_status_mainpage_t *val); -int32_t st1vafe3bx_fsm_out_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2653,28 +2654,28 @@ typedef enum ST1VAFE3BX_ODR_FSM_VAFE_800Hz = 0x14, ST1VAFE3BX_ODR_FSM_VAFE_1600Hz = 0x15, } st1vafe3bx_fsm_val_odr_t; -int32_t st1vafe3bx_fsm_data_rate_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_data_rate_set(const stmdev_ctx_t *ctx, st1vafe3bx_fsm_val_odr_t val); -int32_t st1vafe3bx_fsm_data_rate_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_data_rate_get(const stmdev_ctx_t *ctx, st1vafe3bx_fsm_val_odr_t *val); -int32_t st1vafe3bx_fsm_init_set(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_fsm_init_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t st1vafe3bx_fsm_fifo_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_fsm_fifo_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t st1vafe3bx_long_cnt_int_value_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t st1vafe3bx_long_cnt_int_value_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t st1vafe3bx_fsm_programs_num_set(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_fsm_programs_num_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t st1vafe3bx_fsm_start_address_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t st1vafe3bx_fsm_start_address_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum @@ -2683,13 +2684,13 @@ typedef enum ST1VAFE3BX_MLC_ON = 1, ST1VAFE3BX_MLC_ON_BEFORE_FSM = 2, } st1vafe3bx_mlc_mode_t; -int32_t st1vafe3bx_mlc_set(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_mlc_mode_t val); -int32_t st1vafe3bx_mlc_get(const st1vafe3bx_ctx_t *ctx, st1vafe3bx_mlc_mode_t *val); +int32_t st1vafe3bx_mlc_set(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_mode_t val); +int32_t st1vafe3bx_mlc_get(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_mode_t *val); -int32_t st1vafe3bx_mlc_status_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_mlc_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_status_mainpage_t *val); -int32_t st1vafe3bx_mlc_out_get(const st1vafe3bx_ctx_t *ctx, uint8_t *buff); +int32_t st1vafe3bx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { @@ -2705,18 +2706,16 @@ typedef enum ST1VAFE3BX_ODR_PRGS_VAFE_800Hz = 0x14, ST1VAFE3BX_ODR_PRGS_VAFE_1600Hz = 0x15, } st1vafe3bx_mlc_odr_val_t; -int32_t st1vafe3bx_mlc_data_rate_set(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_mlc_data_rate_set(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_odr_val_t val); -int32_t st1vafe3bx_mlc_data_rate_get(const st1vafe3bx_ctx_t *ctx, +int32_t st1vafe3bx_mlc_data_rate_get(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_odr_val_t *val); -int32_t st1vafe3bx_mlc_fifo_en_set(const st1vafe3bx_ctx_t *ctx, uint8_t val); -int32_t st1vafe3bx_mlc_fifo_en_get(const st1vafe3bx_ctx_t *ctx, uint8_t *val); +int32_t st1vafe3bx_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe3bx_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); #ifdef __cplusplus } #endif #endif /* ST1VAFE3BX_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.c b/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.c index 04cf351..443535c 100644 --- a/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.c +++ b/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -215,23 +214,19 @@ int32_t st1vafe6ax_reset_set(const stmdev_ctx_t *ctx, st1vafe6ax_reset_t val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + return ret; } - ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; - ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; - func_cfg_access.sw_por = (uint8_t)val & 0x01U; + ctrl3.boot = (val == ST1VAFE6AX_RESTORE_CAL_PARAM) ? 1 : 0; + ctrl3.sw_reset = (val == ST1VAFE6AX_RESTORE_CTRL_REGS) ? 1 : 0; + func_cfg_access.sw_por = (val == ST1VAFE6AX_GLOBAL_RST) ? 1 : 0; - if (ret == 0) - { - ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); - } - if (ret == 0) - { - ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - } + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); return ret; } @@ -251,9 +246,11 @@ int32_t st1vafe6ax_reset_get(const stmdev_ctx_t *ctx, st1vafe6ax_reset_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + return ret; } switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) @@ -318,6 +315,10 @@ int32_t st1vafe6ax_mem_bank_get(const stmdev_ctx_t *ctx, st1vafe6ax_mem_bank_t * int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } switch (func_cfg_access.emb_func_reg_access) { @@ -350,6 +351,11 @@ int32_t st1vafe6ax_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WHO_AM_I, (uint8_t *)&who_am_i, 1); + if (ret != 0) + { + return ret; + } + *val = who_am_i.id; return ret; @@ -394,6 +400,10 @@ int32_t st1vafe6ax_xl_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1.odr_xl) { @@ -490,6 +500,10 @@ int32_t st1vafe6ax_xl_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_xl_mode_t *va int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } switch (ctrl1.op_mode_xl) { @@ -560,6 +574,10 @@ int32_t st1vafe6ax_gy_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } switch (ctrl2.odr_g) { @@ -651,6 +669,11 @@ int32_t st1vafe6ax_gy_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_gy_mode_t *va int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl2.op_mode_g) { case ST1VAFE6AX_GY_HIGH_PERFORMANCE_MD: @@ -709,6 +732,11 @@ int32_t st1vafe6ax_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.if_inc; @@ -753,6 +781,11 @@ int32_t st1vafe6ax_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl3.bdu; return ret; @@ -798,6 +831,10 @@ int32_t st1vafe6ax_data_ready_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } switch (ctrl4.drdy_pulsed) { @@ -856,6 +893,10 @@ int32_t st1vafe6ax_gy_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6.fs_g) { @@ -930,6 +971,10 @@ int32_t st1vafe6ax_xl_full_scale_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } switch (ctrl8.fs_xl) { @@ -990,6 +1035,11 @@ int32_t st1vafe6ax_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl8.xl_dualc_en; return ret; @@ -1036,6 +1086,10 @@ int32_t st1vafe6ax_xl_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } //switch (ctrl10.xl_st_offset) switch (ctrl10.st_xl) @@ -1099,6 +1153,10 @@ int32_t st1vafe6ax_gy_self_test_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } switch (ctrl10.st_g) { @@ -1158,6 +1216,12 @@ int32_t st1vafe6ax_all_sources_get(const stmdev_ctx_t *ctx, { ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_STATUS1, (uint8_t *)&buff, 4); } + + if (ret != 0) + { + return ret; + } + bytecpy((uint8_t *)&fifo_status2, &buff[1]); bytecpy((uint8_t *)&all_int_src, &buff[2]); bytecpy((uint8_t *)&status_reg, &buff[3]); @@ -1245,19 +1309,25 @@ int32_t st1vafe6ax_all_sources_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, + 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); } - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, - 1); - } - if (ret == 0) + + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + return ret; } - ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); - val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; val->step_count_inc = emb_func_src.stepcounter_bit_set; @@ -1276,6 +1346,11 @@ int32_t st1vafe6ax_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_STATUS_REG, (uint8_t *)&status, 1); + if (ret != 0) + { + return ret; + } + val->drdy_xl = status.xlda; val->drdy_gy = status.gda; val->drdy_temp = status.tda; @@ -1298,6 +1373,11 @@ int32_t st1vafe6ax_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_OUT_TEMP_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1318,6 +1398,11 @@ int32_t st1vafe6ax_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_OUTX_L_G, &buff[0], 6); + if (ret != 0) + { + return ret; + } + val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1342,6 +1427,11 @@ int32_t st1vafe6ax_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_OUTZ_L_A, &buff[0], 6); + if (ret != 0) + { + return ret; + } + val[2] = (int16_t)buff[1]; val[2] = (val[2] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1366,6 +1456,11 @@ int32_t st1vafe6ax_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *v int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_UI_OUTZ_L_A_DUALC, &buff[0], 6); + if (ret != 0) + { + return ret; + } + val[2] = (int16_t)buff[1]; val[2] = (val[2] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1390,6 +1485,11 @@ int32_t st1vafe6ax_ah_bio_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_AH_BIO_OUT_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -1410,6 +1510,11 @@ int32_t st1vafe6ax_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + if (ret != 0) + { + return ret; + } + *val = (int8_t)internal_freq.freq_fine; return ret; @@ -1438,57 +1543,95 @@ int32_t st1vafe6ax_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, lsb = (uint8_t)address & 0xFFU; ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } /* set page write */ - ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_ENABLE; - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); /* select page */ ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } /* set page addr */ page_address.page_addr = lsb; ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_ADDRESS, (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } for (i = 0; ((i < len) && (ret == 0)); i++) { - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_VALUE, &buf[i], 1); + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) + { + goto exit; + } lsb++; /* Check if page wrap */ if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) { msb++; - ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, 1); + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used0 = 1; // Default value - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + goto exit; } } } page_sel.page_sel = 0; page_sel.not_used0 = 1;// Default value - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) + { + goto exit; + } /* unset page write */ - ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); +exit: ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); return ret; @@ -1517,57 +1660,95 @@ int32_t st1vafe6ax_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, lsb = (uint8_t)address & 0xFFU; ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } /* set page write */ - ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); /* select page */ ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) + { + goto exit; + } /* set page addr */ page_address.page_addr = lsb; - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } for (i = 0; ((i < len) && (ret == 0)); i++) { - ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_VALUE, &buf[i], 1); + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_VALUE, &buf[i], 1); + if (ret != 0) + { + goto exit; + } lsb++; /* Check if page wrap */ if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) { msb++; - ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, 1); + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } - if (ret == 0) + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) { - page_sel.page_sel = msb; - page_sel.not_used0 = 1; // Default value - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + goto exit; } } } page_sel.page_sel = 0; page_sel.not_used0 = 1;// Default value - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, - 1); + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + if (ret != 0) + { + goto exit; + } /* unset page write */ - ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_DISABLE; - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); +exit: ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); return ret; @@ -1623,6 +1804,11 @@ int32_t st1vafe6ax_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + *val = functions_enable.timestamp_en; return ret; @@ -1642,6 +1828,11 @@ int32_t st1vafe6ax_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TIMESTAMP0, &buff[0], 4); + if (ret != 0) + { + return ret; + } + *val = buff[3]; *val = (*val * 256U) + buff[2]; *val = (*val * 256U) + buff[1]; @@ -1703,6 +1894,11 @@ int32_t st1vafe6ax_filt_anti_spike_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.asf_ctrl) { case ST1VAFE6AX_AUTO: @@ -1775,9 +1971,11 @@ int32_t st1vafe6ax_filt_settling_mask_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + return ret; } val->drdy = ctrl4.drdy_mask; @@ -1826,6 +2024,10 @@ int32_t st1vafe6ax_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret != 0) + { + return ret; + } switch (ctrl6.lpf1_g_bw) { @@ -1906,6 +2108,11 @@ int32_t st1vafe6ax_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl7.lpf1_g_en; return ret; @@ -1927,10 +2134,7 @@ int32_t st1vafe6ax_filt_ah_bio_conf_set(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); - } + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); ctrl8.ah_bio_hpf = val.hpf; ctrl9.ah_bio_lpf = val.lpf; @@ -1963,9 +2167,11 @@ int32_t st1vafe6ax_filt_ah_bio_conf_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + return ret; } val->lpf = ctrl9.ah_bio_lpf; @@ -2013,6 +2219,11 @@ int32_t st1vafe6ax_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl8.hp_lpf2_xl_bw) { case ST1VAFE6AX_XL_ULTRA_LIGHT: @@ -2091,6 +2302,11 @@ int32_t st1vafe6ax_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.lpf2_xl_en; return ret; @@ -2133,6 +2349,11 @@ int32_t st1vafe6ax_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.hp_slope_xl_en; return ret; @@ -2175,6 +2396,11 @@ int32_t st1vafe6ax_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *v int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.xl_fastsettl_mode; return ret; @@ -2219,6 +2445,11 @@ int32_t st1vafe6ax_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl9.hp_ref_mode_xl) { case ST1VAFE6AX_HP_MD_NORMAL: @@ -2252,9 +2483,11 @@ int32_t st1vafe6ax_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + return ret; } tap_cfg0.slope_fds = (uint8_t)val & 0x01U; @@ -2290,9 +2523,11 @@ int32_t st1vafe6ax_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + return ret; } switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) @@ -2354,6 +2589,11 @@ int32_t st1vafe6ax_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *v int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + *val = tap_cfg0.hw_func_mask_xl_settl; return ret; @@ -2399,6 +2639,11 @@ int32_t st1vafe6ax_filt_sixd_feed_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg0.low_pass_on_6d) { case ST1VAFE6AX_SIXD_FEED_ODR_DIV_2: @@ -2466,6 +2711,11 @@ int32_t st1vafe6ax_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + *val = pin_ctrl.sdo_pu_en; return ret; @@ -2510,6 +2760,11 @@ int32_t st1vafe6ax_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.i2c_i3c_disable) { case ST1VAFE6AX_I2C_I3C_ENABLE: @@ -2564,6 +2819,11 @@ int32_t st1vafe6ax_spi_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_spi_mode_t * int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.sim) { case ST1VAFE6AX_SPI_4_WIRE: @@ -2618,6 +2878,11 @@ int32_t st1vafe6ax_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + *val = if_cfg.sda_pu_en; return ret; @@ -2662,6 +2927,11 @@ int32_t st1vafe6ax_i3c_ibi_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl5.bus_act_sel) { case ST1VAFE6AX_IBI_2us: @@ -2738,6 +3008,11 @@ int32_t st1vafe6ax_int_pin_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.pp_od) { case ST1VAFE6AX_PUSH_PULL: @@ -2794,6 +3069,11 @@ int32_t st1vafe6ax_pin_polarity_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + switch (if_cfg.h_lactive) { case ST1VAFE6AX_ACTIVE_HIGH: @@ -3077,11 +3357,12 @@ int32_t st1vafe6ax_pin_int1_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); } + if (ret == 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; val->timestamp = md2_cfg.int2_timestamp; } } @@ -3089,71 +3370,73 @@ int32_t st1vafe6ax_pin_int1_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - val->sleep_status = inactivity_dur.sleep_status_on_int; + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD1_CFG, (uint8_t *)&md1_cfg, 1); } if (ret == 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - val->drdy_xl = int1_ctrl.int1_drdy_xl; - val->drdy_gy = int1_ctrl.int1_drdy_g; - val->fifo_th = int1_ctrl.int1_fifo_th; - val->fifo_ovr = int1_ctrl.int1_fifo_ovr; - val->fifo_full = int1_ctrl.int1_fifo_full; - val->fifo_bdr = int1_ctrl.int1_cnt_bdr; - } + val->sleep_status = inactivity_dur.sleep_status_on_int; + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_gy = int1_ctrl.int1_drdy_g; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->fifo_bdr = int1_ctrl.int1_cnt_bdr; - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD1_CFG, (uint8_t *)&md1_cfg, 1); - val->six_d = md1_cfg.int1_6d; - val->double_tap = md1_cfg.int1_double_tap; - val->free_fall = md1_cfg.int1_ff; - val->wake_up = md1_cfg.int1_wu; - val->single_tap = md1_cfg.int1_single_tap; + val->six_d = md1_cfg.int1_6d; + val->double_tap = md1_cfg.int1_double_tap; + val->free_fall = md1_cfg.int1_ff; + val->wake_up = md1_cfg.int1_wu; + val->single_tap = md1_cfg.int1_single_tap; val->sleep_change = md1_cfg.int1_sleep_change; } if (ret == 0) { ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_INT1, (uint8_t *)&fsm_int1, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC_INT1, (uint8_t *)&mlc_int1, 1); + } + + if (ret == 0) + { + val->step_detector = emb_func_int1.int1_step_detector; + val->tilt = emb_func_int1.int1_tilt; + val->sig_mot = emb_func_int1.int1_sig_mot; + val->fsm_lc = emb_func_int1.int1_fsm_lc; + + val->fsm1 = fsm_int1.int1_fsm1; + val->fsm2 = fsm_int1.int1_fsm2; + val->fsm3 = fsm_int1.int1_fsm3; + val->fsm4 = fsm_int1.int1_fsm4; + val->fsm5 = fsm_int1.int1_fsm5; + val->fsm6 = fsm_int1.int1_fsm6; + val->fsm7 = fsm_int1.int1_fsm7; + val->fsm8 = fsm_int1.int1_fsm8; + + val->mlc1 = mlc_int1.int1_mlc1; + val->mlc2 = mlc_int1.int1_mlc2; + val->mlc3 = mlc_int1.int1_mlc3; + val->mlc4 = mlc_int1.int1_mlc4; + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); } + if (ret == 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); - val->step_detector = emb_func_int1.int1_step_detector; - val->tilt = emb_func_int1.int1_tilt; - val->sig_mot = emb_func_int1.int1_sig_mot; - val->fsm_lc = emb_func_int1.int1_fsm_lc; - } - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_INT1, (uint8_t *)&fsm_int1, 1); - val->fsm1 = fsm_int1.int1_fsm1; - val->fsm2 = fsm_int1.int1_fsm2; - val->fsm3 = fsm_int1.int1_fsm3; - val->fsm4 = fsm_int1.int1_fsm4; - val->fsm5 = fsm_int1.int1_fsm5; - val->fsm6 = fsm_int1.int1_fsm6; - val->fsm7 = fsm_int1.int1_fsm7; - val->fsm8 = fsm_int1.int1_fsm8; - } - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC_INT1, (uint8_t *)&mlc_int1, 1); - val->mlc1 = mlc_int1.int1_mlc1; - val->mlc2 = mlc_int1.int1_mlc2; - val->mlc3 = mlc_int1.int1_mlc3; - val->mlc4 = mlc_int1.int1_mlc4; + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); } - ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); - if (ret == 0) { - ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); val->step_count_overflow = pedo_cmd_reg.carry_count_en; } @@ -3186,18 +3469,12 @@ int32_t st1vafe6ax_pin_int2_route_set(const stmdev_ctx_t *ctx, int32_t ret; - ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); - } - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_INT2, (uint8_t *)&fsm_int2, 1); - } + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); if (ret == 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC_INT2, (uint8_t *)&mlc_int2, 1); } if (ret == 0) @@ -3276,6 +3553,10 @@ int32_t st1vafe6ax_pin_int2_route_set(const stmdev_ctx_t *ctx, { ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); ctrl7.int2_drdy_ah_bio = val.drdy_ah_bio; + } + + if (ret == 0) + { ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); } @@ -3402,70 +3683,67 @@ int32_t st1vafe6ax_pin_int2_route_get(const stmdev_ctx_t *ctx, ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + if (ctrl4.int2_on_int1 == PROPERTY_DISABLE) { - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; - } - if (ret == 0) + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); - val->timestamp = md2_cfg.int2_timestamp; + return ret; } + + val->timestamp = md2_cfg.int2_timestamp; + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; } - if (ret == 0) + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - val->sleep_status = inactivity_dur.sleep_status_on_int; + return ret; } + val->sleep_status = inactivity_dur.sleep_status_on_int; - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - val->drdy_xl = int2_ctrl.int2_drdy_xl; - val->drdy_gy = int2_ctrl.int2_drdy_g; - val->fifo_th = int2_ctrl.int2_fifo_th; - val->fifo_ovr = int2_ctrl.int2_fifo_ovr; - val->fifo_full = int2_ctrl.int2_fifo_full; - val->fifo_bdr = int2_ctrl.int2_cnt_bdr; - } + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_gy = int2_ctrl.int2_drdy_g; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->fifo_bdr = int2_ctrl.int2_cnt_bdr; - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); - val->drdy_ah_bio = ctrl7.int2_drdy_ah_bio; - } + val->six_d = md2_cfg.int2_6d; + val->double_tap = md2_cfg.int2_double_tap; + val->free_fall = md2_cfg.int2_ff; + val->wake_up = md2_cfg.int2_wu; + val->single_tap = md2_cfg.int2_single_tap; + val->sleep_change = md2_cfg.int2_sleep_change; - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); - val->six_d = md2_cfg.int2_6d; - val->double_tap = md2_cfg.int2_double_tap; - val->free_fall = md2_cfg.int2_ff; - val->wake_up = md2_cfg.int2_wu; - val->single_tap = md2_cfg.int2_single_tap; - val->sleep_change = md2_cfg.int2_sleep_change; - } + val->drdy_ah_bio = ctrl7.int2_drdy_ah_bio; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); if (ret == 0) { - ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC_INT2, (uint8_t *)&mlc_int2, 1); } + if (ret == 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); val->step_detector = emb_func_int2.int2_step_detector; val->tilt = emb_func_int2.int2_tilt; val->sig_mot = emb_func_int2.int2_sig_mot; val->fsm_lc = emb_func_int2.int2_fsm_lc; - } - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + val->fsm1 = fsm_int2.int2_fsm1; val->fsm2 = fsm_int2.int2_fsm2; val->fsm3 = fsm_int2.int2_fsm3; @@ -3474,10 +3752,7 @@ int32_t st1vafe6ax_pin_int2_route_get(const stmdev_ctx_t *ctx, val->fsm6 = fsm_int2.int2_fsm6; val->fsm7 = fsm_int2.int2_fsm7; val->fsm8 = fsm_int2.int2_fsm8; - } - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + val->mlc1 = mlc_int2.int2_mlc1; val->mlc2 = mlc_int2.int2_mlc2; val->mlc3 = mlc_int2.int2_mlc3; @@ -3489,6 +3764,10 @@ int32_t st1vafe6ax_pin_int2_route_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + if (ret == 0) + { val->step_count_overflow = pedo_cmd_reg.carry_count_en; } @@ -3532,6 +3811,11 @@ int32_t st1vafe6ax_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl5.int_en_i3c; return ret; @@ -3562,19 +3846,20 @@ int32_t st1vafe6ax_int_notification_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); - } - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); - } - if (ret == 0) - { - page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; - ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); - } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + } - ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + } return ret; } @@ -3598,14 +3883,20 @@ int32_t st1vafe6ax_int_notification_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); } - if (ret == 0) + + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + return ret; } - ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); - switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir) { case ST1VAFE6AX_ALL_INT_PULSED: @@ -3681,6 +3972,11 @@ int32_t st1vafe6ax_act_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_act_mode_t * int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + switch (functions_enable.inact_en) { case ST1VAFE6AX_XL_AND_GY_NOT_AFFECTED: @@ -3745,6 +4041,11 @@ int32_t st1vafe6ax_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret != 0) + { + return ret; + } + switch (inactivity_dur.inact_dur) { case ST1VAFE6AX_SLEEP_TO_ACT_AT_1ST_SAMPLE: @@ -3809,6 +4110,11 @@ int32_t st1vafe6ax_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret != 0) + { + return ret; + } + switch (inactivity_dur.xl_inact_odr) { case ST1VAFE6AX_1Hz875: @@ -3852,14 +4158,12 @@ int32_t st1vafe6ax_act_thresholds_set(const stmdev_ctx_t *ctx, float_t tmp; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); - } + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); - if (ret == 0) + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + return ret; } if ((val.wk_ths_mg < (uint32_t)(7.8125f * 63.0f)) @@ -3971,13 +4275,12 @@ int32_t st1vafe6ax_act_thresholds_get(const stmdev_ctx_t *ctx, float_t tmp; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); - } - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + return ret; } switch (inactivity_dur.wu_inact_ths_w) @@ -4074,6 +4377,11 @@ int32_t st1vafe6ax_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + val->shock = wake_up_dur.wake_dur; val->quiet = wake_up_dur.sleep_dur; @@ -4134,6 +4442,11 @@ int32_t st1vafe6ax_tap_detection_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + val->tap_x_en = tap_cfg0.tap_x_en; val->tap_y_en = tap_cfg0.tap_y_en; val->tap_z_en = tap_cfg0.tap_z_en; @@ -4158,13 +4471,11 @@ int32_t st1vafe6ax_tap_thresholds_set(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); - } - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + return ret; } tap_cfg1.tap_ths_z = val.z; @@ -4204,13 +4515,11 @@ int32_t st1vafe6ax_tap_thresholds_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); - } - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + return ret; } val->z = tap_cfg1.tap_ths_z; @@ -4259,6 +4568,11 @@ int32_t st1vafe6ax_tap_axis_priority_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) + { + return ret; + } + switch (tap_cfg1.tap_priority) { case ST1VAFE6AX_XYZ : @@ -4334,6 +4648,11 @@ int32_t st1vafe6ax_tap_time_windows_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret != 0) + { + return ret; + } + val->shock = tap_dur.shock; val->quiet = tap_dur.quiet; val->tap_gap = tap_dur.dur; @@ -4378,6 +4697,11 @@ int32_t st1vafe6ax_tap_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_tap_mode_t * int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + switch (wake_up_ths.single_double_tap) { case ST1VAFE6AX_ONLY_SINGLE: @@ -4447,6 +4771,11 @@ int32_t st1vafe6ax_6d_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + switch (tap_ths_6d.sixd_ths) { case ST1VAFE6AX_DEG_80: @@ -4534,9 +4863,10 @@ int32_t st1vafe6ax_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FREE_FALL, (uint8_t *)&free_fall, 1); + return ret; } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -4583,6 +4913,10 @@ int32_t st1vafe6ax_ff_thresholds_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -4675,6 +5009,11 @@ int32_t st1vafe6ax_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl1.wtm; return ret; @@ -4717,6 +5056,11 @@ int32_t st1vafe6ax_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t * int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; return ret; @@ -4761,6 +5105,10 @@ int32_t st1vafe6ax_fifo_compress_algo_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } switch (fifo_ctrl2.uncompr_rate) { @@ -4826,6 +5174,11 @@ int32_t st1vafe6ax_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.odr_chg_en; return ret; @@ -4857,18 +5210,19 @@ int32_t st1vafe6ax_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); - } - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); - } - if (ret == 0) - { - emb_func_en_b.fifo_compr_en = val; - ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); - } - ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fifo_compr_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + } return ret; } @@ -4888,6 +5242,10 @@ int32_t st1vafe6ax_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } *val = fifo_ctrl2.fifo_compr_rt_en; @@ -4931,6 +5289,11 @@ int32_t st1vafe6ax_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -4975,6 +5338,11 @@ int32_t st1vafe6ax_fifo_xl_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl3.bdr_xl) { case ST1VAFE6AX_XL_NOT_BATCHED: @@ -5071,6 +5439,11 @@ int32_t st1vafe6ax_fifo_gy_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl3.bdr_gy) { case ST1VAFE6AX_GY_NOT_BATCHED: @@ -5167,6 +5540,11 @@ int32_t st1vafe6ax_fifo_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.fifo_mode) { case ST1VAFE6AX_BYPASS_MODE: @@ -5243,6 +5621,11 @@ int32_t st1vafe6ax_fifo_temp_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.odr_t_batch) { case ST1VAFE6AX_TEMP_NOT_BATCHED: @@ -5307,6 +5690,11 @@ int32_t st1vafe6ax_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + switch (fifo_ctrl4.dec_ts_batch) { case ST1VAFE6AX_TMSTMP_NOT_BATCHED: @@ -5375,6 +5763,11 @@ int32_t st1vafe6ax_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG1, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = (uint16_t)buff[0] & 0x3U; *val = (*val * 256U) + (uint16_t)buff[1]; @@ -5418,6 +5811,11 @@ int32_t st1vafe6ax_fifo_batch_ah_bio_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + *val = counter_bdr_reg1.ah_bio_batch_en; return ret; @@ -5463,6 +5861,11 @@ int32_t st1vafe6ax_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + switch (counter_bdr_reg1.trig_counter_bdr) { case ST1VAFE6AX_XL_BATCH_EVENT: @@ -5498,6 +5901,10 @@ int32_t st1vafe6ax_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; @@ -5528,7 +5935,10 @@ int32_t st1vafe6ax_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, if (ret == 0) { ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + if (ret == 0) + { val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; @@ -5555,6 +5965,11 @@ int32_t st1vafe6ax_fifo_status_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + if (ret != 0) + { + return ret; + } + bytecpy((uint8_t *)&status, &buff[1]); val->fifo_bdr = status.counter_bdr_ia; @@ -5584,6 +5999,11 @@ int32_t st1vafe6ax_fifo_out_raw_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_DATA_OUT_TAG, buff, 7); + if (ret != 0) + { + return ret; + } + bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); switch (fifo_data_out_tag.tag_sensor) @@ -5746,7 +6166,10 @@ int32_t st1vafe6ax_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); } - *val = emb_func_fifo_en_a.step_counter_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_a.step_counter_fifo_en; + } ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); @@ -5803,7 +6226,10 @@ int32_t st1vafe6ax_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); } - *val = emb_func_fifo_en_a.mlc_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_a.mlc_fifo_en; + } ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); @@ -5859,7 +6285,10 @@ int32_t st1vafe6ax_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); } - *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + if (ret == 0) + { + *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + } ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); @@ -5898,10 +6327,7 @@ int32_t st1vafe6ax_stpcnt_mode_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - } - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); } if ((val.false_step_rej == PROPERTY_ENABLE) && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == @@ -5957,8 +6383,12 @@ int32_t st1vafe6ax_stpcnt_mode_get(const stmdev_ctx_t *ctx, { ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); } - val->false_step_rej = pedo_cmd_reg.fp_rejection_en; - val->step_counter_enable = emb_func_en_a.pedo_en; + + if (ret == 0) + { + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + } return ret; } @@ -5984,8 +6414,11 @@ int32_t st1vafe6ax_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -6039,7 +6472,10 @@ int32_t st1vafe6ax_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); } - *val = emb_func_src.pedo_rst_step; + if (ret == 0) + { + *val = emb_func_src.pedo_rst_step; + } ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); @@ -6086,7 +6522,10 @@ int32_t st1vafe6ax_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); - *val = pedo_deb_steps_conf.deb_step; + if (ret == 0) + { + *val = pedo_deb_steps_conf.deb_step; + } return ret; } @@ -6126,8 +6565,12 @@ int32_t st1vafe6ax_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_SC_DELTAT_L, &buff[0], 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + + if (ret == 0) + { + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } return ret; } @@ -6193,7 +6636,10 @@ int32_t st1vafe6ax_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } - *val = emb_func_en_a.sign_motion_en; + if (ret == 0) + { + *val = emb_func_en_a.sign_motion_en; + } ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); @@ -6261,7 +6707,10 @@ int32_t st1vafe6ax_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); } - *val = emb_func_en_a.tilt_en; + if (ret == 0) + { + *val = emb_func_en_a.tilt_en; + } ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); @@ -6297,6 +6746,9 @@ int32_t st1vafe6ax_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val) if (ret == 0) { ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { emb_func_en_a.sflp_game_en = val; ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); @@ -6324,6 +6776,9 @@ int32_t st1vafe6ax_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val if (ret == 0) { ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { *val = emb_func_en_a.sflp_game_en; } @@ -6350,6 +6805,9 @@ int32_t st1vafe6ax_sflp_data_rate_set(const stmdev_ctx_t *ctx, if (ret == 0) { ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + } + if (ret == 0) + { sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); @@ -6375,9 +6833,17 @@ int32_t st1vafe6ax_sflp_data_rate_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); - ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + } ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (sflp_odr.sflp_game_odr) { case ST1VAFE6AX_SFLP_15Hz: @@ -6643,6 +7109,12 @@ int32_t st1vafe6ax_sflp_game_gbias_set(const stmdev_ctx_t *ctx, ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL1, conf_saved, 2); ret += st1vafe6ax_xl_mode_set(ctx, ST1VAFE6AX_XL_HIGH_PERFORMANCE_MD); ret += st1vafe6ax_gy_mode_set(ctx, ST1VAFE6AX_GY_HIGH_PERFORMANCE_MD); + + if (ret != 0) + { + return ret; + } + if ((conf_saved[0] & 0x0FU) == ST1VAFE6AX_XL_ODR_OFF) { ret += st1vafe6ax_xl_data_rate_set(ctx, ST1VAFE6AX_XL_ODR_AT_120Hz); @@ -6650,29 +7122,59 @@ int32_t st1vafe6ax_sflp_game_gbias_set(const stmdev_ctx_t *ctx, /* disable algos */ ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); - ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, emb_func_en_saved, - 2); - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, reg_zero, 2); - do + + if (ret == 0) { - ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EXEC_STATUS, - (uint8_t *)&emb_func_sts, 1); - } while (emb_func_sts.emb_func_endop != 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + } + if (ret == 0) + { + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, reg_zero, 2); + } + if (ret == 0) + { + do + { + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + } ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + // enable gbias setting ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } ctrl10.emb_func_debug = 1; ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } /* enable algos */ ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); - emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */ - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, emb_func_en_saved, - 2); + if (ret == 0) + { + emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */ + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + } ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); ret += st1vafe6ax_xl_full_scale_get(ctx, &xl_fs); + if (ret != 0) + { + return ret; + } /* Read XL data */ do @@ -6680,11 +7182,20 @@ int32_t st1vafe6ax_sflp_game_gbias_set(const stmdev_ctx_t *ctx, ret += st1vafe6ax_flag_data_ready_get(ctx, &drdy); } while (drdy.drdy_xl != 1); ret += st1vafe6ax_acceleration_raw_get(ctx, xl_data); + if (ret != 0) + { + return ret; + } /* force sflp initialization */ master_config = 0x40; ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, &master_config, 1); + if (ret != 0) + { + return ret; + } + for (i = 0; i < 3; i++) { j = 0; @@ -6705,23 +7216,38 @@ int32_t st1vafe6ax_sflp_game_gbias_set(const stmdev_ctx_t *ctx, master_config = 0x00; ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, &master_config, 1); + if (ret != 0) + { + return ret; + } // wait end_op (and at least 30 us) ctx->mdelay(1); ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); - do + if (ret == 0) { - ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EXEC_STATUS, - (uint8_t *)&emb_func_sts, 1); - } while (emb_func_sts.emb_func_endop != 1); + do + { + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + } ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); /* write gbias in embedded advanced features registers */ ret += st1vafe6ax_ln_pg_write(ctx, ST1VAFE6AX_SFLP_GAME_GBIASX_L, (uint8_t *)gbias_hf, 6); + if (ret != 0) + { + return ret; + } /* reload previous sensor configuration */ ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL1, conf_saved, 2); + if (ret != 0) + { + return ret; + } // disable gbias setting ctrl10.emb_func_debug = 0; @@ -6799,6 +7325,11 @@ int32_t st1vafe6ax_fsm_permission_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + switch (func_cfg_access.fsm_wr_ctrl_en) { case ST1VAFE6AX_PROTECT_CTRL_REGS: @@ -6831,6 +7362,11 @@ int32_t st1vafe6ax_fsm_permission_status(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL_STATUS, (uint8_t *)&status, 1); + if (ret != 0) + { + return ret; + } + *val = (status.fsm_wr_ctrl_status == 0) ? ST1VAFE6AX_STD_IF_CONTROL : ST1VAFE6AX_FSM_CONTROL; return ret; @@ -6911,6 +7447,11 @@ int32_t st1vafe6ax_fsm_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_fsm_mode_t * ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + val->fsm1_en = fsm_enable.fsm1_en; val->fsm2_en = fsm_enable.fsm2_en; val->fsm3_en = fsm_enable.fsm3_en; @@ -6971,6 +7512,11 @@ int32_t st1vafe6ax_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7053,6 +7599,11 @@ int32_t st1vafe6ax_fsm_data_rate_get(const stmdev_ctx_t *ctx, ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (fsm_odr.fsm_odr) { case ST1VAFE6AX_FSM_15Hz: @@ -7124,6 +7675,11 @@ int32_t st1vafe6ax_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *v int32_t ret; ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_FSM_LC_TIMEOUT_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7167,6 +7723,11 @@ int32_t st1vafe6ax_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t * int32_t ret; ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + if (ret != 0) + { + return ret; + } + *val = fsm_programs.fsm_n_prog; @@ -7207,6 +7768,11 @@ int32_t st1vafe6ax_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_FSM_START_ADD_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7247,26 +7813,29 @@ int32_t st1vafe6ax_mlc_set(const stmdev_ctx_t *ctx, st1vafe6ax_mlc_mode_t val) ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - switch (val) + if (ret == 0) { - case ST1VAFE6AX_MLC_OFF: - emb_en_a.mlc_before_fsm_en = 0; - emb_en_b.mlc_en = 0; - break; - case ST1VAFE6AX_MLC_ON: - emb_en_a.mlc_before_fsm_en = 0; - emb_en_b.mlc_en = 1; - break; - case ST1VAFE6AX_MLC_ON_BEFORE_FSM: - emb_en_a.mlc_before_fsm_en = 1; - emb_en_b.mlc_en = 0; - break; - default: - break; - } + switch (val) + { + case ST1VAFE6AX_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case ST1VAFE6AX_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case ST1VAFE6AX_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + break; + } - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); - ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } } ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); @@ -7295,21 +7864,24 @@ int32_t st1vafe6ax_mlc_get(const stmdev_ctx_t *ctx, st1vafe6ax_mlc_mode_t *val) ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) - { - *val = ST1VAFE6AX_MLC_OFF; - } - else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) - { - *val = ST1VAFE6AX_MLC_ON; - } - else if (emb_en_a.mlc_before_fsm_en == 1U) - { - *val = ST1VAFE6AX_MLC_ON_BEFORE_FSM; - } - else + if (ret == 0) { - /* Do nothing */ + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = ST1VAFE6AX_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = ST1VAFE6AX_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = ST1VAFE6AX_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } } } @@ -7371,6 +7943,11 @@ int32_t st1vafe6ax_mlc_data_rate_get(const stmdev_ctx_t *ctx, ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + switch (mlc_odr.mlc_odr) { case ST1VAFE6AX_MLC_15Hz: @@ -7470,6 +8047,12 @@ int32_t st1vafe6ax_mlc_bio_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *va int32_t ret; ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_MLC_BIO_SENSITIVITY_L, &buff[0], 2); + + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7526,6 +8109,11 @@ int32_t st1vafe6ax_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + *val = ctrl9.usr_off_on_out; return ret; @@ -7550,20 +8138,15 @@ int32_t st1vafe6ax_xl_offset_mg_set(const stmdev_ctx_t *ctx, float_t tmp; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); - } - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); - } - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + return ret; } - if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) && (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f))) @@ -7639,17 +8222,13 @@ int32_t st1vafe6ax_xl_offset_mg_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); - } - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); - } - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + return ret; } if (ctrl9.usr_off_w == PROPERTY_DISABLE) @@ -7699,10 +8278,7 @@ int32_t st1vafe6ax_ah_bio_mode_set(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); - if (ret == 0) - { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); - } + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); if (ret == 0) { @@ -7744,9 +8320,11 @@ int32_t st1vafe6ax_ah_bio_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); - if (ret == 0) + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret != 0) { - ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + return ret; } val->ah_bio1_en = ctrl7.ah_bio1_en; @@ -7795,6 +8373,11 @@ int32_t st1vafe6ax_ah_bio_zin_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + switch (ctrl7.ah_bio_c_zin) { case ST1VAFE6AX_2400MOhm: @@ -7860,6 +8443,11 @@ int32_t st1vafe6ax_fsm_bio_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *va int32_t ret; ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_FSM_BIO_SENSITIVITY_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -7918,6 +8506,11 @@ int32_t st1vafe6ax_i3c_reset_mode_get(const stmdev_ctx_t *ctx, int32_t ret; ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + switch (pin_ctrl.ibhr_por_en) { case ST1VAFE6AX_SW_RST_DYN_ADDRESS_RST: @@ -7945,4 +8538,3 @@ int32_t st1vafe6ax_i3c_reset_mode_get(const stmdev_ctx_t *ctx, * */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.h b/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.h index ce269a9..34d2a9a 100644 --- a/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.h +++ b/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2024 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -3605,5 +3607,3 @@ int32_t st1vafe6ax_i3c_reset_mode_get(const stmdev_ctx_t *ctx, #endif #endif /*ST1VAFE6AX_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.c b/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.c index 79a2e4a..574fd8a 100644 --- a/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.c +++ b/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -177,6 +176,7 @@ int32_t sths34pf80_avg_tobject_num_get(const stmdev_ctx_t *ctx, sths34pf80_avg_t int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1); + if (ret != 0) { return ret; } switch (avg_trim.avg_tmos) { @@ -257,6 +257,7 @@ int32_t sths34pf80_avg_tambient_num_get(const stmdev_ctx_t *ctx, sths34pf80_avg_ int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1); + if (ret != 0) { return ret; } switch (avg_trim.avg_t) { @@ -321,6 +322,7 @@ int32_t sths34pf80_gain_mode_get(const stmdev_ctx_t *ctx, sths34pf80_gain_mode_t int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL0, (uint8_t *)&ctrl0, 1); + if (ret != 0) { return ret; } switch (ctrl0.gain) { @@ -377,6 +379,8 @@ int32_t sths34pf80_tobject_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *va int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_SENS_DATA, (uint8_t *)&data, 1); + if (ret != 0) { return ret; } + *val = (int8_t)data.sens * 16 + 2048; return ret; @@ -404,6 +408,7 @@ static int32_t sths34pf80_safe_power_down(const stmdev_ctx_t *ctx, sths34pf80_ct /* reset the DRDY bit */ ret = sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1); + if (ret != 0) { return ret; } /* wait DRDY bit go to '1'. Maximum wait may be up to 4 sec (0.25 Hz) */ uint16_t retry = 0U; @@ -421,6 +426,7 @@ static int32_t sths34pf80_safe_power_down(const stmdev_ctx_t *ctx, sths34pf80_ct /* perform power-down */ ctrl1->odr = 0U; ret += sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)ctrl1, 1); + if (ret != 0) { return ret; } /* reset the DRDY bit */ ret += sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1); @@ -445,6 +451,7 @@ static int32_t sths34pf80_odr_safe_set(const stmdev_ctx_t *ctx, /* perform power-down transition in a safe way. */ ret = sths34pf80_safe_power_down(ctx, ctrl1); + if (ret != 0) { return ret; } if (odr_new > 0U) { @@ -453,6 +460,7 @@ static int32_t sths34pf80_odr_safe_set(const stmdev_ctx_t *ctx, * operative state. */ ret += sths34pf80_reset_algo_bit_set(ctx); + if (ret != 0) { return ret; } /* set new odr */ ctrl1->odr = (odr_new & 0xfU); @@ -478,47 +486,42 @@ int32_t sths34pf80_odr_set(const stmdev_ctx_t *ctx, sths34pf80_odr_t val) int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + ret += sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1); - if (ret == 0) - { - ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1); + if (ret != 0) { return ret; } - switch (avg_trim.avg_tmos) - { - default: - case STHS34PF80_AVG_TMOS_2: - case STHS34PF80_AVG_TMOS_8: - case STHS34PF80_AVG_TMOS_32: - max_odr = STHS34PF80_ODR_AT_30Hz; - break; - case STHS34PF80_AVG_TMOS_128: - max_odr = STHS34PF80_ODR_AT_8Hz; - break; - case STHS34PF80_AVG_TMOS_256: - max_odr = STHS34PF80_ODR_AT_4Hz; - break; - case STHS34PF80_AVG_TMOS_512: - max_odr = STHS34PF80_ODR_AT_2Hz; - break; - case STHS34PF80_AVG_TMOS_1024: - max_odr = STHS34PF80_ODR_AT_1Hz; - break; - case STHS34PF80_AVG_TMOS_2048: - max_odr = STHS34PF80_ODR_AT_0Hz50; - break; - } + switch (avg_trim.avg_tmos) + { + default: + case STHS34PF80_AVG_TMOS_2: + case STHS34PF80_AVG_TMOS_8: + case STHS34PF80_AVG_TMOS_32: + max_odr = STHS34PF80_ODR_AT_30Hz; + break; + case STHS34PF80_AVG_TMOS_128: + max_odr = STHS34PF80_ODR_AT_8Hz; + break; + case STHS34PF80_AVG_TMOS_256: + max_odr = STHS34PF80_ODR_AT_4Hz; + break; + case STHS34PF80_AVG_TMOS_512: + max_odr = STHS34PF80_ODR_AT_2Hz; + break; + case STHS34PF80_AVG_TMOS_1024: + max_odr = STHS34PF80_ODR_AT_1Hz; + break; + case STHS34PF80_AVG_TMOS_2048: + max_odr = STHS34PF80_ODR_AT_0Hz50; + break; } - if (ret == 0) + if (val > max_odr) { - if (val > max_odr) - { - return -1; - } - - ret = sths34pf80_odr_safe_set(ctx, &ctrl1, (uint8_t)val); + return -1; } + ret = sths34pf80_odr_safe_set(ctx, &ctrl1, (uint8_t)val); + return ret; } @@ -536,6 +539,7 @@ int32_t sths34pf80_odr_get(const stmdev_ctx_t *ctx, sths34pf80_odr_t *val) int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if(ret != 0) { return ret; } switch (ctrl1.odr) { @@ -620,6 +624,7 @@ int32_t sths34pf80_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if(ret != 0) { return ret; } *val = ctrl1.bdu; @@ -665,6 +670,7 @@ int32_t sths34pf80_one_shot_get(const stmdev_ctx_t *ctx, sths34pf80_one_shot_t * int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1); + if(ret != 0) { return ret; } switch (ctrl2.one_shot) { @@ -721,6 +727,7 @@ int32_t sths34pf80_mem_bank_get(const stmdev_ctx_t *ctx, sths34pf80_mem_bank_t * int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1); + if(ret != 0) { return ret; } switch (ctrl2.func_cfg_access) { @@ -777,6 +784,8 @@ int32_t sths34pf80_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1); + if(ret != 0) { return ret; } + *val = ctrl2.boot; return ret; @@ -796,6 +805,7 @@ int32_t sths34pf80_drdy_status_get(const stmdev_ctx_t *ctx, sths34pf80_drdy_stat int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_STATUS, (uint8_t *)&status, 1); + if(ret != 0) { return ret; } val->drdy = status.drdy; @@ -816,6 +826,7 @@ int32_t sths34pf80_func_status_get(const stmdev_ctx_t *ctx, sths34pf80_func_stat int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1); + if(ret != 0) { return ret; } val->tamb_shock_flag = func_status.tamb_shock_flag; val->mot_flag = func_status.mot_flag; @@ -838,6 +849,7 @@ int32_t sths34pf80_tobject_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_TOBJECT_L, &buff[0], 2); + if(ret != 0) { return ret; } *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -859,6 +871,7 @@ int32_t sths34pf80_tambient_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_TAMBIENT_L, &buff[0], 2); + if(ret != 0) { return ret; } *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -880,6 +893,7 @@ int32_t sths34pf80_tobj_comp_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_TOBJ_COMP_L, &buff[0], 2); + if(ret != 0) { return ret; } *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -901,6 +915,7 @@ int32_t sths34pf80_tpresence_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_TPRESENCE_L, &buff[0], 2); + if(ret != 0) { return ret; } *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -922,6 +937,7 @@ int32_t sths34pf80_tmotion_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_TMOTION_L, &buff[0], 2); + if(ret != 0) { return ret; } *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -943,6 +959,7 @@ int32_t sths34pf80_tamb_shock_raw_get(const stmdev_ctx_t *ctx, int16_t *val) int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_TAMB_SHOCK_L, &buff[0], 2); + if(ret != 0) { return ret; } *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -999,6 +1016,7 @@ int32_t sths34pf80_lpf_m_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_b int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF1, (uint8_t *)&lpf1, 1); + if(ret != 0) { return ret; } switch ((lpf1.lpf_m)) { @@ -1075,6 +1093,7 @@ int32_t sths34pf80_lpf_p_m_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF1, (uint8_t *)&lpf1, 1); + if(ret != 0) { return ret; } switch ((lpf1.lpf_p_m)) { @@ -1151,6 +1170,7 @@ int32_t sths34pf80_lpf_a_t_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF2, (uint8_t *)&lpf2, 1); + if(ret != 0) { return ret; } switch ((lpf2.lpf_a_t)) { @@ -1227,6 +1247,7 @@ int32_t sths34pf80_lpf_p_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_b int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF2, (uint8_t *)&lpf2, 1); + if(ret != 0) { return ret; } switch ((lpf2.lpf_p)) { @@ -1318,6 +1339,7 @@ int32_t sths34pf80_route_int_get(const stmdev_ctx_t *ctx, sths34pf80_route_int_t int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1); + if(ret != 0) { return ret; } switch ((ctrl3.ien)) { @@ -1378,6 +1400,7 @@ int32_t sths34pf80_int_or_get(const stmdev_ctx_t *ctx, sths34pf80_int_or_t *val) int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1); + if(ret != 0) { return ret; } switch ((ctrl3.int_msk)) { @@ -1459,6 +1482,7 @@ int32_t sths34pf80_int_mode_get(const stmdev_ctx_t *ctx, sths34pf80_int_mode_t * int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1); + if(ret != 0) { return ret; } switch (ctrl3.pp_od) { @@ -1531,6 +1555,7 @@ int32_t sths34pf80_drdy_mode_get(const stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1); + if(ret != 0) { return ret; } switch (ctrl3.int_latched) { @@ -1580,29 +1605,35 @@ int32_t sths34pf80_func_cfg_write(const stmdev_ctx_t *ctx, uint8_t addr, uint8_t /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if(ret != 0) { return ret; } odr = ctrl1.odr; ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); /* Enable access to embedded functions register */ ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_EMBED_FUNC_MEM_BANK); + if(ret != 0) { return ret; } /* Enable write mode */ page_rw.func_cfg_write = 1; ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1); + if(ret != 0) { goto exit; } /* Select register address (it will autoincrement when writing) */ ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_ADDR, &addr, 1); + if(ret != 0) { goto exit; } for (i = 0; i < len; i++) { /* Write data */ ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_DATA, &data[i], 1); + if(ret != 0) { goto exit; } } /* Disable write mode */ page_rw.func_cfg_write = 0; ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1); +exit: /* Disable access to embedded functions register */ ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_MAIN_MEM_BANK); @@ -1633,30 +1664,37 @@ int32_t sths34pf80_func_cfg_read(const stmdev_ctx_t *ctx, uint8_t addr, uint8_t /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) { return ret; } odr = ctrl1.odr; ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); + if (ret != 0) { return ret; } /* Enable access to embedded functions register */ ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_EMBED_FUNC_MEM_BANK); + if (ret != 0) { return ret; } /* Enable read mode */ page_rw.func_cfg_read = 1; ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1); + if(ret != 0) { goto exit; } for (i = 0; i < len; i++) { /* Select register address */ reg_addr = addr + i; ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_ADDR, ®_addr, 1); + if(ret != 0) { goto exit; } /* Read data */ ret += sths34pf80_read_reg(ctx, STHS34PF80_FUNC_CFG_DATA, &data[i], 1); + if(ret != 0) { goto exit; } } /* Disable read mode */ page_rw.func_cfg_read = 0; ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1); +exit: /* Disable access to embedded functions register */ ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_MAIN_MEM_BANK); @@ -1689,12 +1727,15 @@ int32_t sths34pf80_presence_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if(ret != 0) { return ret; } odr = ctrl1.odr; ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); + if(ret != 0) { return ret; } buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_PRESENCE_THS, &buff[0], 2); + if(ret != 0) { return ret; } ret += sths34pf80_reset_algo_bit_set(ctx); @@ -1718,6 +1759,7 @@ int32_t sths34pf80_presence_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val int32_t ret; ret = sths34pf80_func_cfg_read(ctx, STHS34PF80_PRESENCE_THS, &buff[0], 2); + if(ret != 0) { return ret; } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -1748,15 +1790,19 @@ int32_t sths34pf80_motion_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if(ret != 0) { return ret; } odr = ctrl1.odr; ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); + if(ret != 0) { return ret; } buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_MOTION_THS, &buff[0], 2); + if(ret != 0) { goto exit; } ret += sths34pf80_reset_algo_bit_set(ctx); +exit: /* Set saved odr back */ ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); @@ -1777,6 +1823,7 @@ int32_t sths34pf80_motion_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) int32_t ret; ret = sths34pf80_func_cfg_read(ctx, STHS34PF80_MOTION_THS, &buff[0], 2); + if(ret != 0) { return ret; } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -1807,15 +1854,19 @@ int32_t sths34pf80_tambient_shock_threshold_set(const stmdev_ctx_t *ctx, uint16_ /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if(ret != 0) { return ret; } odr = ctrl1.odr; ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); + if(ret != 0) { return ret; } buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_TAMB_SHOCK_THS, &buff[0], 2); + if(ret != 0) { goto exit; } ret += sths34pf80_reset_algo_bit_set(ctx); +exit: /* Set saved odr back */ ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); @@ -1836,6 +1887,7 @@ int32_t sths34pf80_tambient_shock_threshold_get(const stmdev_ctx_t *ctx, uint16_ int32_t ret; ret = sths34pf80_func_cfg_read(ctx, STHS34PF80_TAMB_SHOCK_THS, &buff[0], 2); + if(ret != 0) { return ret; } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -1859,13 +1911,17 @@ int32_t sths34pf80_motion_hysteresis_set(const stmdev_ctx_t *ctx, uint8_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if(ret != 0) { return ret; } odr = ctrl1.odr; ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); + if(ret != 0) { return ret; } ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_HYST_MOTION, &val, 1); + if(ret != 0) { goto exit; } ret += sths34pf80_reset_algo_bit_set(ctx); +exit: /* Set saved odr back */ ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); @@ -1905,13 +1961,17 @@ int32_t sths34pf80_presence_hysteresis_set(const stmdev_ctx_t *ctx, uint8_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if(ret != 0) { return ret; } odr = ctrl1.odr; ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); + if(ret != 0) { return ret; } ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_HYST_PRESENCE, &val, 1); + if(ret != 0) { goto exit; } ret += sths34pf80_reset_algo_bit_set(ctx); +exit: /* Set saved odr back */ ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); @@ -1951,13 +2011,17 @@ int32_t sths34pf80_tambient_shock_hysteresis_set(const stmdev_ctx_t *ctx, uint8_ /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if(ret != 0) { return ret; } odr = ctrl1.odr; ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); + if(ret != 0) { return ret; } ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_HYST_TAMB_SHOCK, &val, 1); + if(ret != 0) { goto exit; } ret += sths34pf80_reset_algo_bit_set(ctx); +exit: /* Set saved odr back */ ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); @@ -2014,6 +2078,8 @@ static int32_t sths34pf80_algo_config_get(const stmdev_ctx_t *ctx, sths34pf80_al int32_t ret; ret = sths34pf80_func_cfg_read(ctx, STHS34PF80_ALGO_CONFIG, &tmp, 1); + if (ret != 0) { return ret; } + val->sel_abs = (tmp >> 1) & 0x1U; val->comp_type = (tmp >> 2) & 0x1U; val->int_pulsed = (tmp >> 3) & 0x1U; @@ -2038,18 +2104,19 @@ int32_t sths34pf80_tobject_algo_compensation_set(const stmdev_ctx_t *ctx, uint8_ /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) { return ret; } odr = ctrl1.odr; ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); - if (ret != 0) - { - return ret; - } + if (ret != 0) { return ret; } ret = sths34pf80_algo_config_get(ctx, &config); + if (ret != 0) { goto exit; } config.comp_type = val; ret += sths34pf80_algo_config_set(ctx, config); + if (ret != 0) { goto exit; } ret += sths34pf80_reset_algo_bit_set(ctx); +exit: /* Set saved odr back */ ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); @@ -2070,6 +2137,8 @@ int32_t sths34pf80_tobject_algo_compensation_get(const stmdev_ctx_t *ctx, uint8_ int32_t ret; ret = sths34pf80_algo_config_get(ctx, &config); + if (ret != 0) { return ret; } + *val = config.comp_type; return ret; @@ -2092,18 +2161,19 @@ int32_t sths34pf80_presence_abs_value_set(const stmdev_ctx_t *ctx, uint8_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) { return ret; } odr = ctrl1.odr; ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); - if (ret != 0) - { - return ret; - } + if (ret != 0) { return ret; } ret = sths34pf80_algo_config_get(ctx, &config); + if (ret != 0) { goto exit; } config.sel_abs = val; ret += sths34pf80_algo_config_set(ctx, config); + if (ret != 0) { goto exit; } ret += sths34pf80_reset_algo_bit_set(ctx); +exit: /* Set saved odr back */ ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); @@ -2124,6 +2194,8 @@ int32_t sths34pf80_presence_abs_value_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = sths34pf80_algo_config_get(ctx, &config); + if (ret != 0) { return ret; } + *val = config.sel_abs; return ret; @@ -2143,6 +2215,7 @@ int32_t sths34pf80_int_or_pulsed_set(const stmdev_ctx_t *ctx, uint8_t val) int32_t ret; ret = sths34pf80_algo_config_get(ctx, &config); + if (ret != 0) { return ret; } config.int_pulsed = val; ret += sths34pf80_algo_config_set(ctx, config); @@ -2163,6 +2236,8 @@ int32_t sths34pf80_int_or_pulsed_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = sths34pf80_algo_config_get(ctx, &config); + if (ret != 0) { return ret; } + *val = config.int_pulsed; return ret; @@ -2178,23 +2253,28 @@ static int32_t sths34pf80_reset_algo_bit_set(const stmdev_ctx_t *ctx) /* Enable access to embedded functions register */ ret = sths34pf80_mem_bank_set(ctx, STHS34PF80_EMBED_FUNC_MEM_BANK); + if (ret != 0) { return ret; } /* Enable write mode */ page_rw.func_cfg_write = 1; ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) { goto exit; } /* Select register address (it will autoincrement when writing) */ uint8_t addr = STHS34PF80_RESET_ALGO; ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_ADDR, &addr, 1); + if (ret != 0) { goto exit; } /* Write data */ uint8_t data = 0x01; ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_DATA, &data, 1); + if (ret != 0) { goto exit; } /* Disable write mode */ page_rw.func_cfg_write = 0; ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1); +exit: /* Disable access to embedded functions register */ ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_MAIN_MEM_BANK); @@ -2217,8 +2297,10 @@ int32_t sths34pf80_algo_reset(const stmdev_ctx_t *ctx) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) { return ret; } odr = ctrl1.odr; ret += sths34pf80_safe_power_down(ctx, &ctrl1); + if (ret != 0) { return ret; } ret += sths34pf80_reset_algo_bit_set(ctx); diff --git a/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.h b/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.h index c1c4227..b96b46a 100644 --- a/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.h +++ b/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -774,5 +776,3 @@ int32_t sths34pf80_algo_reset(const stmdev_ctx_t *ctx); #endif #endif /*STHS34PF80_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c index 393db49..78cd3d5 100644 --- a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c +++ b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -162,6 +161,7 @@ int32_t stts22h_temp_data_rate_get(const stmdev_ctx_t *ctx, ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1); + if (ret != 0) { return ret; } switch (ctrl.one_shot | (ctrl.freerun << 1) | (ctrl.low_odr_start << 2) | @@ -259,6 +259,7 @@ int32_t stts22h_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, int32_t ret; ret = stts22h_read_reg(ctx, STTS22H_STATUS, (uint8_t *)&status, 1); + if (ret != 0) { return ret; } if (status.busy == PROPERTY_DISABLE) { @@ -287,7 +288,7 @@ int32_t stts22h_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, /** * @brief Temperature data output register(r). L and H registers - * together express a 16-bit word in two’s complement..[get] + * together express a 16-bit word in two's complement..[get] * * @param ctx Read / write interface definitions.(ptr) * @param buff Buffer that stores the data read.(ptr) @@ -299,7 +300,20 @@ int32_t stts22h_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) uint8_t buff[2]; int32_t ret; - ret = stts22h_read_reg(ctx, STTS22H_TEMP_L_OUT, buff, 2); + int has_autoincrement = (ctx->priv_data && + ((stts22h_priv_t *)(ctx->priv_data))->has_autoincrement == 1); + + if (has_autoincrement == 1) { + ret = stts22h_read_reg(ctx, STTS22H_TEMP_L_OUT, buff, 2); + } + else + { + ret = stts22h_read_reg(ctx, STTS22H_TEMP_L_OUT, &buff[0], 1); + ret = stts22h_read_reg(ctx, STTS22H_TEMP_H_OUT, &buff[1], 1); + } + + if (ret != 0) { return ret; } + *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -350,6 +364,8 @@ int32_t stts22h_dev_status_get(const stmdev_ctx_t *ctx, int32_t ret; ret = stts22h_read_reg(ctx, STTS22H_STATUS, (uint8_t *)&status, 1); + if (ret != 0) { return ret; } + val->busy = status.busy; return ret; @@ -409,6 +425,7 @@ int32_t stts22h_smbus_interface_get(const stmdev_ctx_t *ctx, ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1); + if (ret != 0) { return ret; } switch (ctrl.time_out_dis) { @@ -448,6 +465,10 @@ int32_t stts22h_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { ctrl.if_add_inc = (uint8_t)val; ret = stts22h_write_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1); + if (ret == 0 && ctx->priv_data != NULL) + { + ((stts22h_priv_t *)(ctx->priv_data))->has_autoincrement = val; + } } return ret; @@ -464,9 +485,13 @@ int32_t stts22h_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) */ int32_t stts22h_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { + stts22h_ctrl_t ctrl; int32_t ret; - ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t *)&val, 1); + ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1); + if (ret != 0) { return ret; } + + *val = ctrl.if_add_inc; return ret; } @@ -525,6 +550,8 @@ int32_t stts22h_temp_trshld_high_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = stts22h_read_reg(ctx, STTS22H_TEMP_H_LIMIT, (uint8_t *)&temp_h_limit, 1); + if (ret != 0) { return ret; } + *val = temp_h_limit.thl; return ret; @@ -571,6 +598,8 @@ int32_t stts22h_temp_trshld_low_get(const stmdev_ctx_t *ctx, uint8_t *val) ret = stts22h_read_reg(ctx, STTS22H_TEMP_L_LIMIT, (uint8_t *)&temp_l_limit, 1); + if (ret != 0) { return ret; } + *val = temp_l_limit.tll; return ret; @@ -591,6 +620,8 @@ int32_t stts22h_temp_trshld_src_get(const stmdev_ctx_t *ctx, int32_t ret; ret = stts22h_read_reg(ctx, STTS22H_STATUS, (uint8_t *)&status, 1); + if (ret != 0) { return ret; } + val->under_thl = status.under_thl; val->over_thh = status.over_thh; @@ -606,5 +637,3 @@ int32_t stts22h_temp_trshld_src_get(const stmdev_ctx_t *ctx, * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h index 2616f19..7469fbe 100644 --- a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h +++ b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -143,6 +145,8 @@ typedef struct /** I2C Device Address 8 bit format **/ #define STTS22H_I2C_ADD_H 0x71U +#define STTS22H_I2C_ADD_15K_OHM 0x79U +#define STTS22H_I2C_ADD_56K_OHM 0x7DU #define STTS22H_I2C_ADD_L 0x7FU /** Device Identification (Who am I) **/ @@ -207,6 +211,33 @@ typedef struct #define STTS22H_TEMP_L_OUT 0x06U #define STTS22H_TEMP_H_OUT 0x07U +/** + * @defgroup STTS22H_Register_Union + * @brief This union group all the registers having a bit-field + * description. + * This union is useful but it's not needed by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + stts22h_temp_h_limit_t temp_h_limit; + stts22h_temp_l_limit_t temp_l_limit; + stts22h_ctrl_t ctrl; + stts22h_status_t status; + bitwise_t bitwise; + uint8_t byte; +} stts22h_reg_t; + +/** + * @} + * + */ + #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -250,6 +281,10 @@ int32_t stts22h_block_data_update_get(const stmdev_ctx_t *ctx, int32_t stts22h_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); +typedef struct +{ + uint8_t has_autoincrement; +} stts22h_priv_t; int32_t stts22h_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); @@ -299,5 +334,3 @@ int32_t stts22h_temp_trshld_src_get(const stmdev_ctx_t *ctx, #endif #endif /* STTS22H_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c index e5a1e10..ec0cb0d 100644 --- a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c +++ b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -205,12 +204,9 @@ int32_t stts751_temp_data_rate_get(const stmdev_ctx_t *ctx, ret = stts751_read_reg(ctx, STTS751_CONVERSION_RATE, (uint8_t *)&conversion_rate, 1); - - if (ret == 0) - { - ret = stts751_read_reg(ctx, STTS751_CONFIGURATION, - (uint8_t *)&configuration, 1); - } + ret += stts751_read_reg(ctx, STTS751_CONFIGURATION, + (uint8_t *)&configuration, 1); + if (ret != 0) { return ret; } switch ((configuration.stop << 7) + conversion_rate.conv) { @@ -308,6 +304,7 @@ int32_t stts751_resolution_get(const stmdev_ctx_t *ctx, stts751_tres_t *val) int32_t ret; ret = stts751_read_reg(ctx, STTS751_CONFIGURATION, (uint8_t *) ®, 1); + if (ret != 0) { return ret; } switch (reg.tres) { @@ -367,6 +364,8 @@ int32_t stts751_flag_busy_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = stts751_read_reg(ctx, STTS751_STATUS, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.busy; return ret; @@ -386,7 +385,7 @@ int32_t stts751_flag_busy_get(const stmdev_ctx_t *ctx, uint8_t *val) /** * @brief Temperature data output register (r). L and H registers - * together express a 16-bit word in two’s complement.[get] + * together express a 16-bit word in two's complement.[get] * * @param ctx read / write interface definitions * @param buff buffer that stores data read @@ -400,14 +399,12 @@ int32_t stts751_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_HIGH, (uint8_t *)&buff[1], 1); + ret += stts751_read_reg(ctx, STTS751_TEMPERATURE_LOW, + &buff[0], 1); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_LOW, - &buff[0], 1); - *val = (int16_t)buff[1]; - *val = (*val * 256) + (int16_t)buff[0]; - } + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; return ret; } @@ -462,6 +459,8 @@ int32_t stts751_pin_event_route_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = stts751_read_reg(ctx, STTS751_CONFIGURATION, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.mask1; return ret; @@ -518,6 +517,8 @@ int32_t stts751_high_temperature_threshold_get(const stmdev_ctx_t *ctx, ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_HIGH_LIMIT_HIGH, buff, 2); + if (ret != 0) { return ret; } + *val = (int16_t)buff[0]; *val = (*val * 256) + (int16_t)buff[1]; @@ -562,6 +563,8 @@ int32_t stts751_low_temperature_threshold_get(const stmdev_ctx_t *ctx, ret = stts751_read_reg(ctx, STTS751_TEMPERATURE_LOW_LIMIT_HIGH, buff, 2); + if (ret != 0) { return ret; } + *val = (int16_t)buff[0]; *val = (*val * 256) + (int16_t)buff[1]; @@ -704,6 +707,8 @@ int32_t stts751_smbus_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) int32_t ret; ret = stts751_read_reg(ctx, STTS751_SMBUS_TIMEOUT, (uint8_t *)®, 1); + if (ret != 0) { return ret; } + *val = reg.timeout; return ret; @@ -748,5 +753,3 @@ int32_t stts751_device_id_get(const stmdev_ctx_t *ctx, stts751_id_t *buff) * @} * */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h index 58b225b..ab77f20 100644 --- a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h +++ b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,6 +121,9 @@ typedef struct stmdev_mdelay_ptr mdelay; /** Customizable optional pointer **/ void *handle; + + /** private data **/ + void *priv_data; } stmdev_ctx_t; /** @@ -395,5 +397,3 @@ int32_t stts751_device_id_get(const stmdev_ctx_t *ctx, stts751_id_t *buff); #endif #endif /*STTS751_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/