stm32cube: stm32mp13xx: update hal / ll to STM32MP13 HAL tag v1.2.0

Sync all the stm32mp13xx drivers (include/src) to the STM32CubeMP13
tag v1.2.0 from
   https://github.com/STMicroelectronics/STM32CubeMP13.git

Update done by performing copy of all files AS IS from the STM32CubeMP13
directory except for the two following points:

  - do not override back the PAGE_SIZE line and keep it disabled to
    avoid conflict with POSIX PAGE_SIZE
  - avoid copy of the file drivers/include/stm32_assert_template.h

Signed-off-by: Alain Volmat <[email protected]>

Author: Alain Volmat

stm32cube/stm32mp13xx/drivers/include/Legacy/stm32_hal_legacy.h

@@ -139,7 +139,7 @@ extern "C" {
 #define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
 #define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
 #if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM 
                                                                        input 1 for COMP1, LPTIM input 2 for COMP2 */
 #endif
 #define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
@@ -241,9 +241,9 @@ extern "C" {
   */
 #if defined(STM32H5) || defined(STM32C0)
 #else
-#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
+#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for 
                                                                           inter STM32 series compatibility  */
-#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
+#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for 
                                                                           inter STM32 series compatibility */
 #endif
 /**
@@ -1558,35 +1558,35 @@ extern "C" {
 #define ETH_MAC_TXFIFONOT_EMPTY                       0x01000000U  /* Tx FIFO not empty */
 #define ETH_MAC_TXFIFO_WRITE_ACTIVE                   0x00400000U  /* Tx FIFO write active */
 #define ETH_MAC_TXFIFO_IDLE                           0x00000000U  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ                           0x00100000U  /* Tx FIFO read status: Read (transferring data to
+#define ETH_MAC_TXFIFO_READ                           0x00100000U  /* Tx FIFO read status: Read (transferring data to 
                                                                       the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING                        0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from
+#define ETH_MAC_TXFIFO_WAITING                        0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from 
                                                                       MAC transmitter */
 #define ETH_MAC_TXFIFO_WRITING                        0x00300000U  /* Tx FIFO read status: Writing the received TxStatus
                                                                       or flushing the TxFIFO */
 #define ETH_MAC_TRANSMISSION_PAUSE                    0x00080000U  /* MAC transmitter in pause */
 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE          0x00000000U  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING       0x00020000U  /* MAC transmit frame controller: Waiting for Status
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING       0x00020000U  /* MAC transmit frame controller: Waiting for Status 
                                                                    of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U  /* MAC transmit frame controller: Generating and
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U  /* MAC transmit frame controller: Generating and 
                                                              transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING  0x00060000U  /* MAC transmit frame controller: Transferring input
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING  0x00060000U  /* MAC transmit frame controller: Transferring input 
                                                                       frame for transmission */
 #define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
 #define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control 
                                                               de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control 
                                                               activate threshold */
 #define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
 #if defined(STM32F1)
 #else
 #define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
 #define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status 
                                                              (or time-stamp) */
 #endif
-#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and 
                                                               status */
 #define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
 #define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
@@ -2454,9 +2454,9 @@ extern "C" {
 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
   * @{
   */
-#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is 
                                                   done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is 
                                                   done into HAL_COMP_Init() */
 /**
   * @}

stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_adc_ex.h

@@ -758,7 +758,16 @@ typedef struct
   * @param __HANDLE__ ADC handle.
   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
   */
+#if defined(ADC1) & !defined(ADC2)
+#define ADC_VREFINT_INSTANCE(__HANDLE__)  ((__HANDLE__)->Instance == ADC1)
+#endif
+#if defined(ADC2) & !defined(ADC1)
+#define ADC_VREFINT_INSTANCE(__HANDLE__)  ((__HANDLE__)->Instance == ADC2)
+#endif
+#if defined(ADC1) & defined(ADC2)
 #define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2))
+#endif
+
 /**
   * @brief Verify the ADC instance connected to the internal voltage reference VDDCORE.
   * @param __HANDLE__ ADC handle.

stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_cryp.h

@@ -420,7 +420,7 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< point
 
 #define CRYP_FLAG_WRERR    (SAES_SR_WRERR | 0x80000000U) /*!< SAES peripheral Write Error flag */
 #define CRYP_FLAG_RDERR    (SAES_SR_RDERR | 0x80000000U) /*!< SAES peripheral Read error flag */
-#define CRYP_FLAG_CCF      SAES_SR_CCF                   /*!< SAES peripheral Computation completed flag
+#define CRYP_FLAG_CCF      SAES_SR_CCF                   /*!< SAES peripheral Computation completed flag 
                                                               as AES_ISR_CCF */
 #define CRYP_FLAG_KEIF     SAES_ISR_KEIF                 /*!< SAES peripheral Key error interrupt flag */
 #define CRYP_FLAG_RWEIF    SAES_ISR_RWEIF                /*!< SAES peripheral Read or Write error Interrupt flag */
@@ -447,7 +447,7 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< point
   * @{
   */
 
-#define CRYP_KEYIVCONFIG_ALWAYS        0x00000000U            /*!< Peripheral Key and IV configuration
+#define CRYP_KEYIVCONFIG_ALWAYS        0x00000000U            /*!< Peripheral Key and IV configuration 
                                                                    to do systematically */
 #define CRYP_KEYIVCONFIG_ONCE          0x00000001U            /*!< Peripheral Key and IV configuration
                                                                    to do only once */
@@ -462,7 +462,7 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< point
   */
 
 #define CRYP_KEYMODE_NORMAL         0x00000000U         /*!< Normal key usage, Key registers are freely usable */
-#define CRYP_KEYMODE_WRAPPED        SAES_CR_KMOD_0      /*!< Only for SAES, Wrapped key: to encrypt
+#define CRYP_KEYMODE_WRAPPED        SAES_CR_KMOD_0      /*!< Only for SAES, Wrapped key: to encrypt 
                                                              or decrypt AES keys */
 #define CRYP_KEYMODE_SHARED         SAES_CR_KMOD_1      /*!< Key shared by SAES peripheral */
 /**
@@ -474,16 +474,16 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< point
   */
 
 #define CRYP_KEYSEL_NORMAL       0x00000000U            /*!< Normal key, key registers SAES_KEYx or CRYP_KEYx */
-#define CRYP_KEYSEL_HW           SAES_CR_KEYSEL_0       /*!< Only for SAES, Hardware key : derived hardware
+#define CRYP_KEYSEL_HW           SAES_CR_KEYSEL_0       /*!< Only for SAES, Hardware key : derived hardware 
                                                              unique key (DHUK 256-bit) */
-#define CRYP_KEYSEL_SW           SAES_CR_KEYSEL_1       /*!< Only for SAES, Software key : boot hardware
+#define CRYP_KEYSEL_SW           SAES_CR_KEYSEL_1       /*!< Only for SAES, Software key : boot hardware 
                                                              key BHK (256-bit) */
-#define CRYP_KEYSEL_HSW          SAES_CR_KEYSEL_2       /*!< Only for SAES, DHUK XOR BHK Hardware unique
+#define CRYP_KEYSEL_HSW          SAES_CR_KEYSEL_2       /*!< Only for SAES, DHUK XOR BHK Hardware unique 
                                                              key XOR software key */
-#define CRYP_KEYSEL_AHK          (SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0)  /*!< Only for SAES, Software key :
+#define CRYP_KEYSEL_AHK          (SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0)  /*!< Only for SAES, Software key : 
                                                                       application hardware key AHK (128- or 256-bit) */
 #define CRYP_KEYSEL_DUK_AHK      (SAES_CR_KEYSEL_2|SAES_CR_KEYSEL_0)   /*!< Only for SAES, DHUK XOR AHK */
-#define CRYP_KEYSEL_TEST_KEY     (SAES_CR_KEYSEL_2|SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0) /*!< Test mode key (256-bit
+#define CRYP_KEYSEL_TEST_KEY     (SAES_CR_KEYSEL_2|SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0) /*!< Test mode key (256-bit 
                                                                                hardware constant key 0xA5A5...A5A5) */
 /**
   * @}
@@ -494,9 +494,9 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< point
   * @{
   */
 
-#define CRYP_KEYPROT_ENABLE         SAES_CR_KEYPROT     /*!< Only for SAES, Key can't be shared between
+#define CRYP_KEYPROT_ENABLE         SAES_CR_KEYPROT     /*!< Only for SAES, Key can't be shared between 
                                                              two applications with different security contexts */
-#define CRYP_KEYPROT_DISABLE        0x00000000U         /*!< Only for SAES, Key can be shared between
+#define CRYP_KEYPROT_DISABLE        0x00000000U         /*!< Only for SAES, Key can be shared between 
                                                              two applications with different security contexts */
 
 /**