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stm32cube: update stm32l0 to cube version V1.12.3
Update Cube version for STM32L0xx series on https://github.com/STMicroelectronics from version v1.12.2 to version v1.12.3 Signed-off-by: Fabrice DJIATSA <[email protected]>
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‎stm32cube/stm32l0xx/drivers/include/Legacy/stm32_hal_legacy.h‎

Lines changed: 121 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
* @attention
99
*
1010
* Copyright (c) 2021 STMicroelectronics.
11+
* Copyright (c) 2021 STMicroelectronics.
1112
* All rights reserved.
1213
*
1314
* This software is licensed under terms that can be found in the LICENSE file
@@ -38,11 +39,13 @@ extern "C" {
3839
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
3940
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
4041
#if defined(STM32H7) || defined(STM32MP1)
42+
#if defined(STM32H7) || defined(STM32MP1)
4143
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
4244
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
4345
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
4446
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
4547
#endif /* STM32H7 || STM32MP1 */
48+
#endif /* STM32H7 || STM32MP1 */
4649
/**
4750
* @}
4851
*/
@@ -275,6 +278,7 @@ extern "C" {
275278
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
276279
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
277280

281+
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
278282
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
279283
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
280284
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
@@ -473,7 +477,7 @@ extern "C" {
473477
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
474478
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
475479
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
476-
#define PAGESIZE FLASH_PAGE_SIZE
480+
/* #define PAGESIZE FLASH_PAGE_SIZE */
477481
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */
478482
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
479483
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
@@ -542,6 +546,10 @@ extern "C" {
542546
#define FLASH_OPTKEY1 FLASH_OPT_KEY1
543547
#define FLASH_OPTKEY2 FLASH_OPT_KEY2
544548
#endif /* STM32H7RS */
549+
#if defined(STM32H7RS)
550+
#define FLASH_OPTKEY1 FLASH_OPT_KEY1
551+
#define FLASH_OPTKEY2 FLASH_OPT_KEY2
552+
#endif /* STM32H7RS */
545553
#if defined(STM32U5)
546554
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
547555
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
@@ -564,6 +572,16 @@ extern "C" {
564572
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
565573
#define OB_nBOOT0_SET OB_NBOOT0_SET
566574
#endif /* STM32U0 */
575+
#if defined(STM32U0)
576+
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
577+
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
578+
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
579+
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
580+
#define OB_USER_nBOOT0 OB_USER_NBOOT0
581+
#define OB_USER_nBOOT1 OB_USER_NBOOT1
582+
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
583+
#define OB_nBOOT0_SET OB_NBOOT0_SET
584+
#endif /* STM32U0 */
567585

568586
/**
569587
* @}
@@ -616,6 +634,15 @@ extern "C" {
616634

617635
#endif /* STM32U5 */
618636

637+
#if defined(STM32U5)
638+
639+
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
640+
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
641+
#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
642+
#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection
643+
644+
#endif /* STM32U5 */
645+
619646
#if defined(STM32H5)
620647
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
621648
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
@@ -822,6 +849,21 @@ extern "C" {
822849
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
823850
#endif /* STM32U5 */
824851

852+
#if defined(STM32WBA)
853+
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
854+
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
855+
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
856+
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
857+
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
858+
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
859+
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
860+
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
861+
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
862+
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
863+
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
864+
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
865+
#endif /* STM32WBA */
866+
825867
#if defined(STM32WBA)
826868
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
827869
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
@@ -894,6 +936,10 @@ extern "C" {
894936
#define HRTIMInterruptResquests HRTIMInterruptRequests
895937
#endif /* STM32F3 || STM32G4 || STM32H7 */
896938

939+
#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
940+
#define HRTIMInterruptResquests HRTIMInterruptRequests
941+
#endif /* STM32F3 || STM32G4 || STM32H7 */
942+
897943
#if defined(STM32G4)
898944
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
899945
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
@@ -1033,6 +1079,7 @@ extern "C" {
10331079
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
10341080
#endif /* STM32F3 */
10351081

1082+
10361083
/**
10371084
* @}
10381085
*/
@@ -1283,10 +1330,12 @@ extern "C" {
12831330
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
12841331
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
12851332

1333+
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
12861334
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
12871335
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
12881336
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
12891337
#endif /* STM32H5 || STM32H7RS || STM32N6 */
1338+
#endif /* STM32H5 || STM32H7RS || STM32N6 */
12901339

12911340
#if defined(STM32WBA)
12921341
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1298,27 +1347,33 @@ extern "C" {
12981347
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
12991348
#endif /* STM32WBA */
13001349

1350+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
13011351
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
13021352
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
13031353
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
13041354
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
1355+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
13051356

1357+
#if defined(STM32F7) || defined(STM32WB)
13061358
#if defined(STM32F7) || defined(STM32WB)
13071359
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
13081360
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
13091361
#endif /* STM32F7 || STM32WB */
1362+
#endif /* STM32F7 || STM32WB */
13101363

13111364
#if defined(STM32H7)
13121365
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
13131366
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
13141367
#endif /* STM32H7 */
13151368

1369+
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
13161370
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
13171371
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
13181372
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
13191373
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
13201374
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
13211375
#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
1376+
#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
13221377

13231378
/**
13241379
* @}
@@ -1485,6 +1540,7 @@ extern "C" {
14851540
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
14861541
#endif
14871542

1543+
#if defined(STM32U5) || defined(STM32MP2)
14881544
#if defined(STM32U5) || defined(STM32MP2)
14891545
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
14901546
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
@@ -1641,6 +1697,8 @@ extern "C" {
16411697

16421698
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
16431699

1700+
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
1701+
16441702
/**
16451703
* @}
16461704
*/
@@ -1851,6 +1909,7 @@ extern "C" {
18511909
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
18521910
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
18531911

1912+
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
18541913
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
18551914
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
18561915
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
@@ -2034,11 +2093,13 @@ extern "C" {
20342093
* @{
20352094
*/
20362095
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
2096+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
20372097
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
20382098
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
20392099
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
20402100
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
20412101
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
2102+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
20422103

20432104
/**
20442105
* @}
@@ -2355,6 +2416,8 @@ extern "C" {
23552416
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
23562417
#endif
23572418
#if defined(STM32F302xE) || defined(STM32F302xC)
2419+
#endif
2420+
#if defined(STM32F302xE) || defined(STM32F302xC)
23582421
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
23592422
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
23602423
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -2389,6 +2452,8 @@ extern "C" {
23892452
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
23902453
#endif
23912454
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
2455+
#endif
2456+
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
23922457
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
23932458
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
23942459
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -2447,6 +2512,8 @@ extern "C" {
24472512
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
24482513
#endif
24492514
#if defined(STM32F373xC) ||defined(STM32F378xx)
2515+
#endif
2516+
#if defined(STM32F373xC) ||defined(STM32F378xx)
24502517
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
24512518
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
24522519
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2464,6 +2531,7 @@ extern "C" {
24642531
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
24652532
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
24662533
#endif
2534+
#endif
24672535
#else
24682536
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
24692537
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -2771,6 +2839,12 @@ extern "C" {
27712839
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
27722840
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
27732841
#endif /* STM32C0 */
2842+
#if defined(STM32C0)
2843+
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
2844+
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
2845+
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
2846+
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
2847+
#endif /* STM32C0 */
27742848
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
27752849
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
27762850
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@@ -3698,8 +3772,13 @@ extern "C" {
36983772
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
36993773
#endif
37003774

3775+
#if defined(STM32U0)
3776+
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
3777+
#endif
3778+
37013779
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
37023780
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0)
3781+
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0)
37033782
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
37043783
#else
37053784
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3802,9 +3881,11 @@ extern "C" {
38023881
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
38033882
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
38043883
#if !defined(STM32U0)
3884+
#if !defined(STM32U0)
38053885
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
38063886
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
38073887
#endif
3888+
#endif
38083889

38093890
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
38103891
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3952,6 +4033,8 @@ extern "C" {
39524033
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
39534034
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \
39544035
defined (STM32U0) || defined (STM32U3)
4036+
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \
4037+
defined (STM32U0) || defined (STM32U3)
39554038
#else
39564039
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39574040
#endif
@@ -3993,6 +4076,13 @@ extern "C" {
39934076
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
39944077
#endif
39954078

4079+
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
4080+
defined (STM32H7) || \
4081+
defined (STM32L0) || defined (STM32L1) || \
4082+
defined (STM32WB)
4083+
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
4084+
#endif
4085+
39964086
#define IS_ALARM IS_RTC_ALARM
39974087
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
39984088
#define IS_TAMPER IS_RTC_TAMPER
@@ -4272,6 +4362,33 @@ extern "C" {
42724362
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
42734363
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
42744364
#endif
4365+
#if defined(STM32U5)
4366+
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD
4367+
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK
4368+
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC
4369+
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST
4370+
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF
4371+
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT
4372+
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
4373+
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM
4374+
#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
4375+
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ
4376+
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT
4377+
#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0
4378+
#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1
4379+
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM
4380+
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG
4381+
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM
4382+
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM
4383+
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT
4384+
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM
4385+
#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM
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#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID
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#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0
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#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1
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#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
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#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
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#endif
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/**
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* @}
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*/
@@ -4302,6 +4419,9 @@ extern "C" {
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#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
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#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
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#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
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#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
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#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
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/**

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