lib/stm32: update stm32wba to cube version V1.5.0

Update Cube version for STM32WBAxx series
on https://github.com/STMicroelectronics
from version v1.4.1
to version v1.5.0

Signed-off-by: Alessandro Manganaro <[email protected]>

Author: asm5878

lib/stm32wba/BLE_TransparentMode/Core/Inc/app_common.h

@@ -30,6 +30,7 @@ extern "C"{
 #include <stdio.h>
 #include <stdlib.h>
 #include <stdarg.h>
+#include <inttypes.h>
 
 #include "app_conf.h"
 #include "hw.h"

lib/stm32wba/BLE_TransparentMode/Core/Inc/app_conf.h

@@ -65,12 +65,12 @@
 #define CFG_BLE_OPTIONS             (0 | \
                                      0 | \
                                      0 | \
-              BLE_OPTIONS_EXTENDED_ADV | \
+                                     BLE_OPTIONS_EXTENDED_ADV | \
                                      0 | \
+                                     BLE_OPTIONS_GATT_CACHING | \
                                      0 | \
                                      0 | \
-                                     0 | \
-                                     0)
+                                     BLE_OPTIONS_ENHANCED_ATT)
 
 /**
  * Maximum number of simultaneous connections and advertising that the device will support.
@@ -196,9 +196,6 @@ typedef enum
 /******************************************************************************
  * RTC
  ******************************************************************************/
-#define RTC_N_PREDIV_S (10)
-#define RTC_PREDIV_S ((1<<RTC_N_PREDIV_S)-1)
-#define RTC_PREDIV_A ((1<<(15-RTC_N_PREDIV_S))-1)
 
 /* USER CODE BEGIN RTC */
 
@@ -221,6 +218,8 @@ typedef enum
  */
 #define CFG_LOG_SUPPORTED           (0U)
 
+/* Usart used by LOG */
+
 /* Configure Log display settings */
 #define CFG_LOG_INSERT_COLOR_INSIDE_THE_TRACE       (0U)
 #define CFG_LOG_INSERT_TIME_STAMP_INSIDE_THE_TRACE  (0U)
@@ -241,7 +240,7 @@ typedef enum
  * Configure Log level for Application
  ******************************************************************************/
 #define APPLI_CONFIG_LOG_LEVEL      LOG_VERBOSE_INFO
-
+#define APPLI_CONFIG_LOG_REGION     (LOG_REGION_ALL_REGIONS)
 /* USER CODE BEGIN Log_level */
 
 /* USER CODE END Log_level */
@@ -320,7 +319,7 @@ typedef enum
  * NVM configuration
  ******************************************************************************/
 
-#define CFG_SNVMA_START_SECTOR_ID     (FLASH_PAGE_NB - 2u)
+#define CFG_SNVMA_START_SECTOR_ID     ((FLASH_SIZE / FLASH_PAGE_SIZE) - 2u)
 
 #define CFG_SNVMA_START_ADDRESS       (FLASH_BASE + (FLASH_PAGE_SIZE * (CFG_SNVMA_START_SECTOR_ID)))
 
@@ -347,20 +346,20 @@ typedef enum
  *   - 2 : Debugger available in low power mode.
  *
  ******************************************************************************/
-#define CFG_DEBUGGER_LEVEL           (2)
+#define CFG_DEBUGGER_LEVEL                  (2)
 
 /******************************************************************************
  * RealTime GPIO debug module configuration
  ******************************************************************************/
 
-#define CFG_RT_DEBUG_GPIO_MODULE         (0)
-#define CFG_RT_DEBUG_DTB                 (0)
+#define CFG_RT_DEBUG_GPIO_MODULE            (0)
+#define CFG_RT_DEBUG_DTB                    (0)
 
 /******************************************************************************
  * System Clock Manager module configuration
  ******************************************************************************/
 
-#define CFG_SCM_SUPPORTED            (1)
+#define CFG_SCM_SUPPORTED                   (1)
 
 /******************************************************************************
  * HW RADIO configuration
@@ -391,9 +390,14 @@ typedef enum
 /* RF TX power table ID selection:
  *   0 -> RF TX output level from -20 dBm to +10 dBm
  *   1 -> RF TX output level from -20 dBm to +3 dBm
+ *   2 -> RF TX output level at +20 dBm with an external PA
  */
 #define CFG_RF_TX_POWER_TABLE_ID            (0)
 
+#define CFG_EXTERNAL_PA_ENABLE              (0)
+
+#define CFG_BLE_AOA_AOD_ENABLE              (0)
+
 /* Custom LSE sleep clock accuracy to use if both conditions are met:
  * - LSE is selected as Link Layer sleep clock source
  * - the LSE used is different from the default one.
@@ -425,8 +429,8 @@ typedef enum
 #define CFG_AMM_VIRTUAL_STACK_BLE_BUFFER_SIZE     (400U)  /* words (32 bits) */
 #define CFG_AMM_VIRTUAL_APP_BLE                           (2U)
 #define CFG_AMM_VIRTUAL_APP_BLE_BUFFER_SIZE     (200U)  /* words (32 bits) */
-#define CFG_AMM_POOL_SIZE                                 DIVC(CFG_MM_POOL_SIZE, sizeof (uint32_t)) \
-                                                          + (AMM_VIRTUAL_INFO_ELEMENT_SIZE * CFG_AMM_VIRTUAL_MEMORY_NUMBER)
+#define CFG_AMM_POOL_SIZE                                 ( DIVC(CFG_MM_POOL_SIZE, sizeof (uint32_t)) \
+                                                          + (AMM_VIRTUAL_INFO_ELEMENT_SIZE * CFG_AMM_VIRTUAL_MEMORY_NUMBER) )
 
 /* USER CODE BEGIN MEMORY_MANAGER_Configuration */
 

lib/stm32wba/BLE_TransparentMode/Core/Inc/app_entry.h

@@ -56,7 +56,7 @@ extern "C" {
 #define CFG_FW_BUILD              (0)
 #define CFG_FW_BRANCH             (0)
 #define CFG_FW_SUBVERSION         (0)
-#define CFG_FW_MINOR_VERSION      (4)
+#define CFG_FW_MINOR_VERSION      (5)
 #define CFG_FW_MAJOR_VERSION      (1)
 
 /* USER CODE BEGIN EC */

lib/stm32wba/BLE_TransparentMode/Core/Inc/main.h

@@ -29,9 +29,22 @@ extern "C" {
 /* Includes ------------------------------------------------------------------*/
 #include "stm32wbaxx_hal.h"
 #include "app_conf.h"
-/* #include "app_entry.h" */
+#include "app_entry.h"
 #include "app_common.h"
-/* #include "app_debug.h" */
+#include "app_debug.h"
+
+#include "stm32wbaxx_ll_icache.h"
+#include "stm32wbaxx_ll_tim.h"
+#include "stm32wbaxx_ll_bus.h"
+#include "stm32wbaxx_ll_cortex.h"
+#include "stm32wbaxx_ll_rcc.h"
+#include "stm32wbaxx_ll_system.h"
+#include "stm32wbaxx_ll_utils.h"
+#include "stm32wbaxx_ll_pwr.h"
+#include "stm32wbaxx_ll_gpio.h"
+#include "stm32wbaxx_ll_dma.h"
+
+#include "stm32wbaxx_ll_exti.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */

lib/stm32wba/BLE_TransparentMode/STM32_WPAN/Target/linklayer_plat.c

@@ -1,11 +1,21 @@
-/*
- * Copyright (c) 2023 STMicroelectronics
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-
-
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    linklayer_plat.c
+  * @author  MCD Application Team
+  * @brief   Source file for the linklayer plateform adaptation layer
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
 /* USER CODE END Header */
 
 #ifndef __ZEPHYR__
@@ -27,6 +37,8 @@
 #endif /* (CFG_LPM_LEVEL != 0) */
 /* USER CODE BEGIN Includes */
 
+/* USER CODE END Includes */
+
 #else
 #include "scm.h"
 #endif
@@ -104,6 +116,44 @@ void LINKLAYER_PLAT_WaitHclkRdy(void)
   while(HAL_RCCEx_GetRadioBusClockReadiness() != RCC_RADIO_BUS_CLOCK_READY);
 }
 
+/**
+  * @brief  Notify the Link Layer platform layer the system will enter in WFI
+  *         and AHB5 clock may be turned of regarding the 2.4Ghz radio state.
+  * @param  None
+  * @retval None
+  */
+void LINKLAYER_PLAT_NotifyWFIEnter(void)
+{
+  /* Check if Radio state will allow the AHB5 clock to be cut */
+
+  /* AHB5 clock will be cut in the following cases:
+   * - 2.4GHz radio is not in ACTIVE mode (in SLEEP or DEEPSLEEP mode).
+   * - RADIOSMEN and STRADIOCLKON bits are at 0.
+   */
+  if((LL_PWR_GetRadioMode() != LL_PWR_RADIO_ACTIVE_MODE) ||
+     ((__HAL_RCC_RADIO_IS_CLK_SLEEP_ENABLED() == 0) && (LL_RCC_RADIO_IsEnabledSleepTimerClock() == 0)))
+  {
+    AHB5_SwitchedOff = 1;
+  }
+}
+
+/**
+  * @brief  Notify the Link Layer platform layer the system exited WFI and AHB5
+  *         clock may be resynchronized as is may have been turned of during
+  *         low power mode entry.
+  * @param  None
+  * @retval None
+  */
+void LINKLAYER_PLAT_NotifyWFIExit(void)
+{
+  /* Check if AHB5 clock has been turned of and needs resynchronisation */
+  if (AHB5_SwitchedOff)
+  {
+    /* Read sleep register as earlier as possible */
+    radio_sleep_timer_val = ll_intf_cmn_get_slptmr_value();
+  }
+}
+
 /**
   * @brief  Active wait on bus clock readiness.
   * @param  None
@@ -273,9 +323,9 @@ void LINKLAYER_PLAT_EnableSpecificIRQ(uint8_t isr_type)
     {
       /* When specific counter for link layer high ISR reaches 0, interrupt is enabled */
       HAL_NVIC_EnableIRQ(RADIO_INTR_NUM);
-      /* USER CODE BEGIN LINKLAYER_PLAT_EnableSpecificIRQ_1*/
+      /* USER CODE BEGIN LINKLAYER_PLAT_EnableSpecificIRQ_1 */
 
-      /* USER CODE END LINKLAYER_PLAT_EnableSpecificIRQ_1*/
+      /* USER CODE END LINKLAYER_PLAT_EnableSpecificIRQ_1 */
     }
   }
 
@@ -318,9 +368,9 @@ void LINKLAYER_PLAT_DisableSpecificIRQ(uint8_t isr_type)
     prio_high_isr_counter++;
     if(prio_high_isr_counter == 1)
     {
-      /* USER CODE BEGIN LINKLAYER_PLAT_DisableSpecificIRQ_1*/
+      /* USER CODE BEGIN LINKLAYER_PLAT_DisableSpecificIRQ_1 */
 
-      /* USER CODE END LINKLAYER_PLAT_DisableSpecificIRQ_1*/
+      /* USER CODE END LINKLAYER_PLAT_DisableSpecificIRQ_1 */
       /* When specific counter for link layer high ISR value is 1, interrupt is disabled */
       HAL_NVIC_DisableIRQ(RADIO_INTR_NUM);
     }
@@ -358,15 +408,15 @@ void LINKLAYER_PLAT_DisableSpecificIRQ(uint8_t isr_type)
   */
 void LINKLAYER_PLAT_EnableRadioIT(void)
 {
-  /* USER CODE BEGIN LINKLAYER_PLAT_EnableRadioIT_1*/
+  /* USER CODE BEGIN LINKLAYER_PLAT_EnableRadioIT_1 */
 
-  /* USER CODE END LINKLAYER_PLAT_EnableRadioIT_1*/
+  /* USER CODE END LINKLAYER_PLAT_EnableRadioIT_1 */
 
   HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_INTR_NUM);
 
-  /* USER CODE BEGIN LINKLAYER_PLAT_EnableRadioIT_2*/
+  /* USER CODE BEGIN LINKLAYER_PLAT_EnableRadioIT_2 */
 
-  /* USER CODE END LINKLAYER_PLAT_EnableRadioIT_2*/
+  /* USER CODE END LINKLAYER_PLAT_EnableRadioIT_2 */
 }
 
 /**
@@ -376,15 +426,15 @@ void LINKLAYER_PLAT_EnableRadioIT(void)
   */
 void LINKLAYER_PLAT_DisableRadioIT(void)
 {
-  /* USER CODE BEGIN LINKLAYER_PLAT_DisableRadioIT_1*/
+  /* USER CODE BEGIN LINKLAYER_PLAT_DisableRadioIT_1 */
 
-  /* USER CODE END LINKLAYER_PLAT_DisableRadioIT_1*/
+  /* USER CODE END LINKLAYER_PLAT_DisableRadioIT_1 */
 
   HAL_NVIC_DisableIRQ((IRQn_Type) RADIO_INTR_NUM);
 
-  /* USER CODE BEGIN LINKLAYER_PLAT_DisableRadioIT_2*/
+  /* USER CODE BEGIN LINKLAYER_PLAT_DisableRadioIT_2 */
 
-  /* USER CODE END LINKLAYER_PLAT_DisableRadioIT_2*/
+  /* USER CODE END LINKLAYER_PLAT_DisableRadioIT_2 */
 }
 
 #ifndef __ZEPHYR__
@@ -473,6 +523,12 @@ void LINKLAYER_PLAT_RequestTemperature(void)
   */
 void LINKLAYER_PLAT_EnableOSContextSwitch(void)
 {
+  /* USER CODE BEGIN LINKLAYER_PLAT_EnableOSContextSwitch_0 */
+
+  /* USER CODE END LINKLAYER_PLAT_EnableOSContextSwitch_0 */
+  /* USER CODE BEGIN LINKLAYER_PLAT_EnableOSContextSwitch_1 */
+
+  /* USER CODE END LINKLAYER_PLAT_EnableOSContextSwitch_1 */
 }
 
 /**
@@ -482,6 +538,12 @@ void LINKLAYER_PLAT_EnableOSContextSwitch(void)
   */
 void LINKLAYER_PLAT_DisableOSContextSwitch(void)
 {
+  /* USER CODE BEGIN LINKLAYER_PLAT_DisableOSContextSwitch_0 */
+
+  /* USER CODE END LINKLAYER_PLAT_DisableOSContextSwitch_0 */
+  /* USER CODE BEGIN LINKLAYER_PLAT_DisableOSContextSwitch_1 */
+
+  /* USER CODE END LINKLAYER_PLAT_DisableOSContextSwitch_1 */
 }
 
 /**
@@ -515,50 +577,7 @@ uint32_t LINKLAYER_PLAT_GetUDN(void)
 {
   return LL_FLASH_GetUDN();
 }
-
-/* USER CODE BEGIN LINKLAYER_PLAT 0 */
-
-/* Radio bus clock control variables */
-uint8_t AHB5_SwitchedOff = 0;
-uint32_t radio_sleep_timer_val = 0;
 #endif
-
-/**
-  * @brief  Notify the Link Layer platform layer the system will enter in WFI 
-  *         and AHB5 clock may be turned of regarding the 2.4Ghz radio state. 
-  * @param  None
-  * @retval None
-  */
-void LINKLAYER_PLAT_NotifyWFIEnter(void)
-{
-  /* Check if Radio state will allow the AHB5 clock to be cut */
-  
-  /* AHB5 clock will be cut in the following cases:
-   * - 2.4GHz radio is not in ACTIVE mode (in SLEEP or DEEPSLEEP mode).
-   * - RADIOSMEN and STRADIOCLKON bits are at 0.
-   */
-  if((LL_PWR_GetRadioMode() != LL_PWR_RADIO_ACTIVE_MODE) ||
-     ((__HAL_RCC_RADIO_IS_CLK_SLEEP_ENABLED() == 0) && (LL_RCC_RADIO_IsEnabledSleepTimerClock() == 0)))
-  {
-    AHB5_SwitchedOff = 1;
-  }
-}
-
-/**
-  * @brief  Notify the Link Layer platform layer the system exited WFI and AHB5 
-  *         clock may be resynchronized as is may have been turned of during
-  *         low power mode entry.
-  * @param  None
-  * @retval None
-  */
-void LINKLAYER_PLAT_NotifyWFIExit(void)
-{
- /* Check if AHB5 clock has been turned of and needs resynchronisation */
-  if (AHB5_SwitchedOff)
-  {
-    /* Read sleep register as earlier as possible */
-    radio_sleep_timer_val = ll_intf_cmn_get_slptmr_value();
-  }
-}
+/* USER CODE BEGIN LINKLAYER_PLAT 0 */
 
 /* USER CODE END LINKLAYER_PLAT 0 */