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| 1 | +/* |
| 2 | + * Copyright (c) 2015-2022, Verisilicon Inc. - All Rights Reserved |
| 3 | + * Copyright (c) 2011-2014, Google Inc. - All Rights Reserved |
| 4 | + * |
| 5 | + * |
| 6 | + ******************************************************************************** |
| 7 | + * |
| 8 | + * This software is distributed under the terms of |
| 9 | + * BSD-3-Clause. The following provisions apply : |
| 10 | + * |
| 11 | + ******************************************************************************** |
| 12 | + * |
| 13 | + * Redistribution and use in source and binary forms, with or without |
| 14 | + * modification, are permitted provided that the following conditions are met: |
| 15 | + * |
| 16 | + * 1. Redistributions of source code must retain the above copyright notice, this |
| 17 | + * list of conditions and the following disclaimer. |
| 18 | + * |
| 19 | + * 2. Redistributions in binary form must reproduce the above copyright notice, |
| 20 | + * this list of conditions and the following disclaimer in the documentation |
| 21 | + * and/or other materials provided with the distribution. |
| 22 | + * |
| 23 | + * 3. Neither the name of the copyright holder nor the names of its contributors |
| 24 | + * may be used to endorse or promote products derived from this software without |
| 25 | + * specific prior written permission. |
| 26 | + * |
| 27 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 28 | + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 29 | + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 30 | + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| 31 | + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 32 | + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 33 | + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| 34 | + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 35 | + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 36 | + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 37 | + * |
| 38 | + ******************************************************************************** |
| 39 | + * |
| 40 | + * Abstract : For test/fpga_verification/example purpose. operations on Input |
| 41 | + * line buffer. |
| 42 | + * |
| 43 | + ******************************************************************************** |
| 44 | + */ |
| 45 | + |
| 46 | +#ifndef ENC_INPUTLINEBUFREGISTER_H |
| 47 | +#define ENC_INPUTLINEBUFREGISTER_H |
| 48 | + |
| 49 | +#include "basetype.h" |
| 50 | + |
| 51 | +typedef u32 (*getHEncRdMbLines)(const void *inst); |
| 52 | +typedef i32 (*setHEncWrMbLines)(const void *inst, u32 lines); |
| 53 | + |
| 54 | +typedef struct |
| 55 | +{ |
| 56 | + u8 *buf; |
| 57 | + ptr_t busAddress; |
| 58 | +} lineBufMem; |
| 59 | + |
| 60 | +/* struct for input mb line buffer */ |
| 61 | +typedef struct |
| 62 | +{ |
| 63 | + /* src picture related pointers */ |
| 64 | + u8 *src; /* source buffer */ |
| 65 | + u8 *lumSrc; |
| 66 | + u8 *cbSrc; |
| 67 | + u8 *crSrc; |
| 68 | + |
| 69 | + /* line buffer related pointers */ |
| 70 | + u8 *buf; /* line buffer virtual address */ |
| 71 | + u32 *reg; /* virtual address of registers in line buffer, only for fpga verification purpose */ |
| 72 | + ptr_t busAddress; /* line buffer bus address */ |
| 73 | + lineBufMem lumBuf; /*luma address in line buffer */ |
| 74 | + lineBufMem cbBuf; /*cb address in line buffer */ |
| 75 | + lineBufMem crBuf; /*cr address in line buffer */ |
| 76 | + |
| 77 | + /* encoding parameters */ |
| 78 | + u32 inputFormat; /* format of input video */ |
| 79 | + u32 pixOnRow; /* pixels in one line */ |
| 80 | + u32 encWidth; |
| 81 | + u32 encHeight; |
| 82 | + u32 srcHeight; |
| 83 | + u32 srcVerOffset; |
| 84 | + |
| 85 | + /* parameters of line buffer mode */ |
| 86 | + i32 wrCnt; |
| 87 | + u32 depth; /* number of MB_row lines in the input line buffer */ |
| 88 | + u32 loopBackEn; |
| 89 | + u32 hwHandShake; |
| 90 | + |
| 91 | + /*functions */ |
| 92 | + getHEncRdMbLines getMbLines; /* get read mb lines from encoder register */ |
| 93 | + setHEncWrMbLines setMbLines; /* set written mb lines to encoder register */ |
| 94 | + |
| 95 | + /* encoder instance */ |
| 96 | + void *inst; |
| 97 | +}inputLineBufferCfg; |
| 98 | + |
| 99 | +#ifdef PCIE_FPGA_VERI_LINEBUF |
| 100 | +#include "encswhwregisters.h" |
| 101 | +/* HW Register field names */ |
| 102 | +typedef enum { |
| 103 | + InputlineBufWrCntr, |
| 104 | + InputlineBufDepth, |
| 105 | + InputlineBufHwHandshake, |
| 106 | + InputlineBufPicHeight, |
| 107 | + InputlineBufRdCntr, |
| 108 | +} lineBufRegName; |
| 109 | + |
| 110 | +#define LINE_BUF_SWREG_AMOUNT 4 /*4x 32-bit*/ |
| 111 | + |
| 112 | +static const regField_s lineBufRegisterDesc[] = { |
| 113 | +/* HW ID register, read-only */ |
| 114 | + {InputlineBufWrCntr , 0x000, 0x000001ff, 0, 0, RW, "slice_wr_cntr. +slice_depth when one slice is filled into slice_fifo"}, |
| 115 | + {InputlineBufDepth , 0x000, 0x0003fe00, 9, 0, RW, "slice_depth. unit is MB line"}, |
| 116 | + {InputlineBufHwHandshake , 0x000, 0x00040000, 18, 0, RW, "slice_hw_mode_en. active high. enable bit of slice_fifo hardware mode. should be disabled before the start of next frame."}, |
| 117 | + {InputlineBufPicHeight , 0x000, 0x0ff80000, 19, 0, RW, "pic_height. same value of swreg14[18:10] in H1."}, |
| 118 | + {InputlineBufRdCntr , 0x008, 0x000001ff, 0, 0, RO, "slice_rd_cntr. read only"}, |
| 119 | +}; |
| 120 | +#endif |
| 121 | + |
| 122 | +void HEncInitInputLineBufSrcPtr (inputLineBufferCfg *lineBufCfg); |
| 123 | +void HEncInitInputLineBufPtr (inputLineBufferCfg *lineBufCfg); |
| 124 | +i32 HEncInitInputLineBuffer(inputLineBufferCfg *lineBufCfg, const void *ewl); |
| 125 | +void HEncStartInputLineBuffer(inputLineBufferCfg * lineBufCfg); |
| 126 | +void HEncInputMBLineBufDone (void *pAppData); |
| 127 | + |
| 128 | +#endif |
| 129 | + |
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