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lib/stm32wba/hci Moving HAL based funcs into stm32wba hci part
Moving HAL based funcs from zephyr to hal stm32wba hci part. In this way we separate zephyr based adaptation from pure HAL code. Signed-off-by: Alessandro Manganaro <[email protected]>
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‎lib/CMakeLists.txt‎

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@@ -39,6 +39,8 @@ if(CONFIG_HAS_STM32LIB)
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zephyr_sources(stm32wba/hci/power_table.c)
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zephyr_sources(stm32wba/hci/scm.c)
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zephyr_sources(stm32wba/hci/log_module.c)
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zephyr_sources(stm32wba/hci/linklayer_plat.c)
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zephyr_sources(stm32wba/hci/ll_sys_if.c)
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if(CONFIG_FLASH)
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zephyr_sources(stm32wba/hci/flash_manager.c)
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zephyr_sources(stm32wba/hci/flash_driver.c)

‎lib/stm32wba/hci/README‎

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@@ -117,6 +117,8 @@ Patch List:
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app_conf.h
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scm.c
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ll_intf_cmn.h
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ll_sys_if.c
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linklayer_plat.c
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* Changes from official delivery:
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- dos2unix applied

‎lib/stm32wba/hci/linklayer_plat.c‎

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/*
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* Copyright (c) 2023 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/logging/log.h>
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#include "scm.h"
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(linklayer_plat);
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/* Radio bus clock control variables */
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uint8_t AHB5_SwitchedOff;
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uint32_t radio_sleep_timer_val;
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void LINKLAYER_PLAT_ClockInit(void)
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{
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AHB5_SwitchedOff = 0;
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radio_sleep_timer_val = 0;
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LL_PWR_EnableBkUpAccess();
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/* Select LSE as Sleep CLK */
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__HAL_RCC_RADIOSLPTIM_CONFIG(RCC_RADIOSTCLKSOURCE_LSE);
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LL_PWR_DisableBkUpAccess();
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/* Enable AHB5ENR peripheral clock (bus CLK) */
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__HAL_RCC_RADIO_CLK_ENABLE();
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}
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void LINKLAYER_PLAT_WaitHclkRdy(void)
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{
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while (HAL_RCCEx_GetRadioBusClockReadiness() != RCC_RADIO_BUS_CLOCK_READY) {
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}
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}
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void LINKLAYER_PLAT_AclkCtrl(uint8_t enable)
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{
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LOG_DBG("enable: %d", enable);
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if (enable) {
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/* Enable RADIO baseband clock (active CLK) */
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HAL_RCCEx_EnableRadioBBClock();
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/* Polling on HSE32 activation */
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while (LL_RCC_HSE_IsReady() == 0) {
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}
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} else {
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/* Disable RADIO baseband clock (active CLK) */
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HAL_RCCEx_DisableRadioBBClock();
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}
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}
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void LINKLAYER_PLAT_NotifyWFIEnter(void)
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{
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/* Check if Radio state will allow the AHB5 clock to be cut */
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/* AHB5 clock will be cut in the following cases:
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* - 2.4GHz radio is not in ACTIVE mode (in SLEEP or DEEPSLEEP mode).
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* - RADIOSMEN and STRADIOCLKON bits are at 0.
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*/
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if ((LL_PWR_GetRadioMode() != LL_PWR_RADIO_ACTIVE_MODE) ||
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((__HAL_RCC_RADIO_IS_CLK_SLEEP_ENABLED() == 0) &&
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(LL_RCC_RADIO_IsEnabledSleepTimerClock() == 0))) {
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AHB5_SwitchedOff = 1;
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}
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}
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void LINKLAYER_PLAT_NotifyWFIExit(void)
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{
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/* Check if AHB5 clock has been turned of and needs resynchronisation */
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if (AHB5_SwitchedOff) {
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/* Read sleep register as earlier as possible */
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radio_sleep_timer_val = ll_intf_cmn_get_slptmr_value();
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}
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}

‎lib/stm32wba/hci/ll_sys_if.c‎

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/*
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* Copyright (c) 2023 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/logging/log.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(ll_sys_if);
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#include "ll_intf.h"
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#include "ll_intf_cmn.h"
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#include "utilities_common.h"
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static void ll_sys_sleep_clock_source_selection(void);
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void ll_sys_reset(void);
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void ll_sys_config_params(void)
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{
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ll_intf_config_ll_ctx_params(USE_RADIO_LOW_ISR, NEXT_EVENT_SCHEDULING_FROM_ISR);
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}
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#if (CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE == 0)
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uint8_t ll_sys_BLE_sleep_clock_accuracy_selection(void)
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{
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uint8_t BLE_sleep_clock_accuracy = 0;
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uint32_t RevID = LL_DBGMCU_GetRevisionID();
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uint32_t linklayer_slp_clk_src = LL_RCC_RADIO_GetSleepTimerClockSource();
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if (linklayer_slp_clk_src == LL_RCC_RADIOSLEEPSOURCE_LSE) {
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/* LSE selected as Link Layer sleep clock source. */
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/* Sleep clock accuracy is different regarding the WBA device ID and revision */
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#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx)
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if (RevID == REV_ID_A) {
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BLE_sleep_clock_accuracy = STM32WBA5x_REV_ID_A_SCA_RANGE;
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} else if (RevID == REV_ID_B) {
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BLE_sleep_clock_accuracy = STM32WBA5x_REV_ID_B_SCA_RANGE;
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} else {
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/* Revision ID not supported, default value of 500ppm applied */
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BLE_sleep_clock_accuracy = STM32WBA5x_DEFAULT_SCA_RANGE;
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}
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#else
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UNUSED(RevID);
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#endif
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/* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */
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} else {
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/* LSE is not the Link Layer sleep clock source, */
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/* sleep clock accuracy default value is 500 ppm */
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BLE_sleep_clock_accuracy = STM32WBA5x_DEFAULT_SCA_RANGE;
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}
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return BLE_sleep_clock_accuracy;
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}
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#endif /* CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE */
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void ll_sys_sleep_clock_source_selection(void)
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{
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uint16_t freq_value = 0;
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uint32_t linklayer_slp_clk_src = LL_RCC_RADIOSLEEPSOURCE_NONE;
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linklayer_slp_clk_src = LL_RCC_RADIO_GetSleepTimerClockSource();
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switch (linklayer_slp_clk_src) {
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case LL_RCC_RADIOSLEEPSOURCE_LSE:
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linklayer_slp_clk_src = RTC_SLPTMR;
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break;
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case LL_RCC_RADIOSLEEPSOURCE_LSI:
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linklayer_slp_clk_src = RCO_SLPTMR;
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break;
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case LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000:
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linklayer_slp_clk_src = CRYSTAL_OSCILLATOR_SLPTMR;
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break;
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case LL_RCC_RADIOSLEEPSOURCE_NONE:
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/* No Link Layer sleep clock source selected */
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assert_param(0);
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break;
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}
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ll_intf_cmn_le_select_slp_clk_src((uint8_t)linklayer_slp_clk_src, &freq_value);
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}
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void ll_sys_reset(void)
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{
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#if (CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE == 0)
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uint8_t bsca = 0;
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#endif /* CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE */
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/* Apply the selected link layer sleep timer source */
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ll_sys_sleep_clock_source_selection();
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/* Configure the link layer sleep clock accuracy if different from the default one */
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#if (CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE != 0)
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ll_intf_le_set_sleep_clock_accuracy(CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE);
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#else
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bsca = ll_sys_BLE_sleep_clock_accuracy_selection();
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if (bsca != STM32WBA5x_DEFAULT_SCA_RANGE) {
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ll_intf_le_set_sleep_clock_accuracy(bsca);
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}
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#endif /* CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE */
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}

‎scripts/ble_library.py‎

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ble_heartrate_app_path + "/STM32_WPAN/Target/power_table.c",
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ble_heartrate_app_path + "/STM32_WPAN/Target/bpka.c",
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ble_heartrate_app_path + "/STM32_WPAN/Target/bpka.h",
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ble_heartrate_app_path + "/STM32_WPAN/Target/linklayer_plat.c",
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ble_heartrate_app_path + "/STM32_WPAN/Target/ll_sys_if.c",
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"Utilities/trace/adv_trace/stm32_adv_trace.h",
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"Utilities/misc/stm32_mem.h",
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"Utilities/tim_serv/stm32_timer.h",

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