stm32cube: update stm32wba to cube version V1.6.0

Update Cube version for STM32WBAxx series
on https://github.com/STMicroelectronics
from version v1.5.0
to version v1.6.0

Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <[email protected]>

Author: marwaiehm-st

stm32cube/stm32wbaxx/CMakeLists.txt

@@ -22,13 +22,16 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_FLASH_EX drivers/src/stm32wbax
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_GPIO drivers/src/stm32wbaxx_hal_gpio.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_GTZC drivers/src/stm32wbaxx_hal_gtzc.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_HASH drivers/src/stm32wbaxx_hal_hash.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_HCD drivers/src/stm32wbaxx_hal_hcd.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_HSEM drivers/src/stm32wbaxx_hal_hsem.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I2C drivers/src/stm32wbaxx_hal_i2c.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I2C_EX drivers/src/stm32wbaxx_hal_i2c_ex.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_ICACHE drivers/src/stm32wbaxx_hal_icache.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_IRDA drivers/src/stm32wbaxx_hal_irda.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_IWDG drivers/src/stm32wbaxx_hal_iwdg.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_LPTIM drivers/src/stm32wbaxx_hal_lptim.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PCD drivers/src/stm32wbaxx_hal_pcd.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PCD_EX drivers/src/stm32wbaxx_hal_pcd_ex.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PKA drivers/src/stm32wbaxx_hal_pka.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PWR drivers/src/stm32wbaxx_hal_pwr.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PWR_EX drivers/src/stm32wbaxx_hal_pwr_ex.c)
@@ -71,4 +74,5 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_RTC drivers/src/stm32wbaxx_ll_r
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_SPI drivers/src/stm32wbaxx_ll_spi.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_TIM drivers/src/stm32wbaxx_ll_tim.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_USART drivers/src/stm32wbaxx_ll_usart.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_USB drivers/src/stm32wbaxx_ll_usb.c)
 zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_UTILS drivers/src/stm32wbaxx_ll_utils.c)

stm32cube/stm32wbaxx/README

@@ -6,7 +6,7 @@ Origin:
    http://www.st.com/en/embedded-software/stm32cubewba.html
 
 Status:
-   version v1.5.0
+   version v1.6.0
 
 Purpose:
    ST Microelectronics official MCU package for STM32WBA series.
@@ -23,7 +23,7 @@ URL:
    https://github.com/STMicroelectronics/STM32CubeWBA
 
 Commit:
-   06402010bb3e1eb4d49ee22cbe45d3408ce413c5
+   e7d27c496416aae8f4ba8b3e84f963f0c5a0b69f
 
 Maintained-by:
    External

stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h

@@ -472,7 +472,9 @@ extern "C" {
 #define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
 #define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
 #define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
+#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
 /* #define PAGESIZE                      FLASH_PAGE_SIZE */
+#endif /* STM32F2 && STM32F4 && STM32F7 &&  STM32H7 && STM32H5 */
 #define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
 #define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
 #define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
@@ -536,6 +538,10 @@ extern "C" {
 #define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
 #define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
 #endif /* STM32H7 */
+#if defined(STM32H7RS)
+#define FLASH_OPTKEY1                 FLASH_OPT_KEY1
+#define FLASH_OPTKEY2                 FLASH_OPT_KEY2
+#endif /* STM32H7RS */
 #if defined(STM32U5)
 #define OB_USER_nRST_STOP             OB_USER_NRST_STOP
 #define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
@@ -1297,22 +1303,22 @@ extern "C" {
 #define TAMP_SECRETDEVICE_ERASE_ENABLE      TAMP_SECRETDEVICE_ERASE_ALL
 #endif /* STM32H5 || STM32WBA || STM32H7RS */
 
-#if defined(STM32F7)
+#if defined(STM32F7) || defined(STM32WB)
 #define RTC_TAMPCR_TAMPXE          RTC_TAMPER_ENABLE_BITS_MASK
 #define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_IT_ENABLE_BITS_MASK
-#endif /* STM32F7 */
+#endif /* STM32F7 || STM32WB */
 
 #if defined(STM32H7)
 #define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
 #define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
 #endif /* STM32H7 */
 
-#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
 #define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
 #define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
 #define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
 #define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMP
-#endif /* STM32F7 || STM32H7 || STM32L0 */
+#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
 
 /**
   * @}

stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h

@@ -79,7 +79,7 @@ extern HAL_TickFreqTypeDef      uwTickFreq;
   * @brief STM32WBAxx HAL Driver version number
   */
 #define __STM32WBAxx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32WBAxx_HAL_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32WBAxx_HAL_VERSION_SUB1   (0x06U) /*!< [23:16] sub1 version */
 #define __STM32WBAxx_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32WBAxx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32WBAxx_HAL_VERSION    ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\
@@ -150,6 +150,27 @@ extern HAL_TickFreqTypeDef      uwTickFreq;
   * @}
   */
 
+#if defined(VREFBUF)
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+  * @{
+  */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+  * @{
+  */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U     /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE  VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
+/**
+  * @}
+  */
+#endif /* VREFBUF */
 
 /** @defgroup SYSCFG_Flags_Definition Flags
   * @{
@@ -524,6 +545,17 @@ extern HAL_TickFreqTypeDef      uwTickFreq;
                                             ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY)  || \
                                             ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
 
+#if defined(VREFBUF)
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+                                                    ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
+                                                    ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
+                                                    ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+                                                     ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+#endif /* VREFBUF */
 
 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_ALL) != 0x00U) && \
                                          (((__PIN__) & ~SYSCFG_FASTMODEPLUS_ALL) == 0x00U))
@@ -646,6 +678,13 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
 void HAL_SYSCFG_EnableIOAnalogSwitchVdd(void);
 void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void);
 
+#ifdef VREFBUF
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+#endif /* VREFBUF */
 
 #ifdef SYSCFG_OTGHSPHYCR_EN
 void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClockSelection);

stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_conf.h

@@ -45,12 +45,14 @@ extern "C" {
 #define HAL_GPIO_MODULE_ENABLED
 #define HAL_GTZC_MODULE_ENABLED
 #define HAL_HASH_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
 #define HAL_HSEM_MODULE_ENABLED
 #define HAL_I2C_MODULE_ENABLED
 #define HAL_ICACHE_MODULE_ENABLED
 #define HAL_IRDA_MODULE_ENABLED
 #define HAL_IWDG_MODULE_ENABLED
 #define HAL_LPTIM_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
 #define HAL_PKA_MODULE_ENABLED
 #define HAL_PWR_MODULE_ENABLED
 #define HAL_RAMCFG_MODULE_ENABLED
@@ -159,10 +161,12 @@ extern "C" {
 #define  USE_HAL_COMP_REGISTER_CALLBACKS       0U /* COMP register callback disabled      */
 #define  USE_HAL_CRYP_REGISTER_CALLBACKS       0U /* CRYP register callback disabled      */
 #define  USE_HAL_HASH_REGISTER_CALLBACKS       0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS        0U /* HCD register callback disabled       */
 #define  USE_HAL_I2C_REGISTER_CALLBACKS        0U /* I2C register callback disabled       */
 #define  USE_HAL_IRDA_REGISTER_CALLBACKS       0U /* IRDA register callback disabled      */
 #define  USE_HAL_IWDG_REGISTER_CALLBACKS       0U /* IWDG register callback disabled      */
 #define  USE_HAL_LPTIM_REGISTER_CALLBACKS      0U /* LPTIM register callback disabled     */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS        0U /* PCD register callback disabled       */
 #define  USE_HAL_PKA_REGISTER_CALLBACKS        0U /* PKA register callback disabled       */
 #define  USE_HAL_RAMCFG_REGISTER_CALLBACKS     0U /* RAMCFG register callback disabled    */
 #define  USE_HAL_RNG_REGISTER_CALLBACKS        0U /* RNG register callback disabled       */
@@ -241,6 +245,10 @@ extern "C" {
 #include "stm32wbaxx_hal_hash.h"
 #endif /* HAL_HASH_MODULE_ENABLED */
 
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32wbaxx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
 #ifdef HAL_HSEM_MODULE_ENABLED
 #include "stm32wbaxx_hal_hsem.h"
 #endif /* HAL_HSEM_MODULE_ENABLED */
@@ -265,6 +273,10 @@ extern "C" {
 #include "stm32wbaxx_hal_lptim.h"
 #endif /* HAL_LPTIM_MODULE_ENABLED */
 
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32wbaxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
 #ifdef HAL_PKA_MODULE_ENABLED
 #include "stm32wbaxx_hal_pka.h"
 #endif /* HAL_PKA_MODULE_ENABLED */

stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma.h

@@ -250,6 +250,48 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA Request Selection
   * @{
   */
+#if defined (LPDMA1)
+/* LPDMA1 requests */
+#define LPDMA1_REQUEST_ADC4           0U      /*!< LPDMA1 HW request is ADC4          */
+
+#define LPDMA1_REQUEST_SPI3_RX        3U      /*!< LPDMA1 HW request is SPI3_RX       */
+#define LPDMA1_REQUEST_SPI3_TX        4U      /*!< LPDMA1 HW request is SPI3_TX       */
+#define LPDMA1_REQUEST_I2C1_RX        5U      /*!< LPDMA1 HW request is I2C1_RX       */
+#define LPDMA1_REQUEST_I2C1_TX        6U      /*!< LPDMA1 HW request is I2C1_TX       */
+#define LPDMA1_REQUEST_I2C1_EVC       7U      /*!< LPDMA1 HW request is I2C1_EVC      */
+#define LPDMA1_REQUEST_I2C3_RX        8U      /*!< LPDMA1 HW request is I2C3_RX       */
+#define LPDMA1_REQUEST_I2C3_TX        9U      /*!< LPDMA1 HW request is I2C3_TX       */
+#define LPDMA1_REQUEST_I2C3_EVC       10U     /*!< LPDMA1 HW request is I2C3_EVC      */
+#define LPDMA1_REQUEST_USART1_RX      11U     /*!< LPDMA1 HW request is USART1_RX     */
+#define LPDMA1_REQUEST_USART1_TX      12U     /*!< LPDMA1 HW request is USART1_TX     */
+
+#define LPDMA1_REQUEST_LPUART1_RX     15U     /*!< LPDMA1 HW request is LPUART1_RX    */
+#define LPDMA1_REQUEST_LPUART1_TX     16U     /*!< LPDMA1 HW request is LPUART1_TX    */
+#define LPDMA1_REQUEST_SAI1_A         17U     /*!< LPDMA1 HW request is SAI1_A        */
+#define LPDMA1_REQUEST_SAI1_B         18U     /*!< LPDMA1 HW request is SAI1_B        */
+
+#define LPDMA1_REQUEST_TIM2_CH1       26U     /*!< LPDMA1 HW request is TIM2_CH1      */
+#define LPDMA1_REQUEST_TIM2_CH2       27U     /*!< LPDMA1 HW request is TIM2_CH2      */
+#define LPDMA1_REQUEST_TIM2_CH3       28U     /*!< LPDMA1 HW request is TIM2_CH3      */
+#define LPDMA1_REQUEST_TIM2_CH4       29U     /*!< LPDMA1 HW request is TIM2_CH4      */
+#define LPDMA1_REQUEST_TIM2_UP        30U     /*!< LPDMA1 HW request is TIM2_UP       */
+#define LPDMA1_REQUEST_TIM16_CH1      31U     /*!< LPDMA1 HW request is TIM16_CH1     */
+#define LPDMA1_REQUEST_TIM16_UP       32U     /*!< LPDMA1 HW request is TIM16_UP      */
+#define LPDMA1_REQUEST_TIM17_CH1      33U     /*!< LPDMA1 HW request is TIM17_CH1     */
+#define LPDMA1_REQUEST_TIM17_UP       34U     /*!< LPDMA1 HW request is TIM17_UP      */
+
+#define LPDMA1_REQUEST_AES_IN         35U     /*!< LPDMA1 HW request is AES_IN        */
+#define LPDMA1_REQUEST_AES_OUT        36U     /*!< LPDMA1 HW request is AES_OUT       */
+#define LPDMA1_REQUEST_HASH_IN        37U     /*!< LPDMA1 HW request is HASH_IN       */
+#define LPDMA1_REQUEST_LPTIM1_IC1     38U     /*!< LPDMA1 HW request is LPTIM1_IC1    */
+#define LPDMA1_REQUEST_LPTIM1_IC2     39U     /*!< LPDMA1 HW request is LPTIM1_IC2    */
+#define LPDMA1_REQUEST_LPTIM1_UE      40U     /*!< LPDMA1 HW request is LPTIM1_UE     */
+#define LPDMA1_REQUEST_LPTIM2_IC1     41U     /*!< LPDMA1 HW request is LPTIM2_IC1    */
+#define LPDMA1_REQUEST_LPTIM2_IC2     42U     /*!< LPDMA1 HW request is LPTIM2_IC2    */
+#define LPDMA1_REQUEST_LPTIM2_UE      46U     /*!< LPDMA1 HW request is LPTIM2_UE     */
+
+#define LPDMA1_REQUEST_XSPI1          44U     /*!< LPDMA1 HW request is XSPI1         */
+#else
 /* GPDMA1 requests */
 #define GPDMA1_REQUEST_ADC4           0U      /*!< GPDMA1 HW request is ADC4          */
 #if defined (SPI1)
@@ -321,6 +363,32 @@ typedef struct __DMA_HandleTypeDef
 #define GPDMA1_REQUEST_LPTIM2_IC2     50U     /*!< GPDMA1 HW request is LPTIM2_IC2    */
 #define GPDMA1_REQUEST_LPTIM2_UE      51U     /*!< GPDMA1 HW request is LPTIM2_UE     */
 #endif /* LPTIM2 */
+#if defined (SPI2)
+#define GPDMA1_REQUEST_SPI2_RX        52U     /*!< GPDMA1 HW request is SPI2_RX       */
+#define GPDMA1_REQUEST_SPI2_TX        53U     /*!< GPDMA1 HW request is SPI2_TX       */
+#endif /* SPI2 */
+#if defined (I2C2)
+#define GPDMA1_REQUEST_I2C2_RX        54U     /*!< GPDMA1 HW request is I2C2_RX       */
+#define GPDMA1_REQUEST_I2C2_TX        55U     /*!< GPDMA1 HW request is I2C2_TX       */
+#define GPDMA1_REQUEST_I2C2_EVC       56U     /*!< GPDMA1 HW request is I2C2_EVC      */
+#endif /* I2C2 */
+#if defined (I2C4)
+#define GPDMA1_REQUEST_I2C4_RX        57U     /*!< GPDMA1 HW request is I2C4_RX       */
+#define GPDMA1_REQUEST_I2C4_TX        58U     /*!< GPDMA1 HW request is I2C4_TX       */
+#define GPDMA1_REQUEST_I2C4_EVC       59U     /*!< GPDMA1 HW request is I2C4_EVC      */
+#endif /* I2C4 */
+#if defined (TIM4)
+#define GPDMA1_REQUEST_TIM4_CH1       60U     /*!< GPDMA1 HW request is TIM4_CH1      */
+#define GPDMA1_REQUEST_TIM4_CH2       61U     /*!< GPDMA1 HW request is TIM4_CH2      */
+#define GPDMA1_REQUEST_TIM4_CH3       62U     /*!< GPDMA1 HW request is TIM4_CH3      */
+#define GPDMA1_REQUEST_TIM4_CH4       63U     /*!< GPDMA1 HW request is TIM4_CH4      */
+#define GPDMA1_REQUEST_TIM4_UP        64U     /*!< GPDMA1 HW request is TIM4_UP       */
+#endif /* TIM4 */
+#if defined (USART3)
+#define GPDMA1_REQUEST_USART3_RX      65U     /*!< GPDMA1 HW request is USART3_RX     */
+#define GPDMA1_REQUEST_USART3_TX      66U     /*!< GPDMA1 HW request is USART3_TX     */
+#endif /* USART3 */
+#endif /* LPDMA1 */
 
 /* Software request */
 #define DMA_REQUEST_SW                DMA_CTR2_SWREQ /*!< DMA SW request              */
@@ -342,9 +410,16 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA transfer direction
   * @{
   */
+#if defined(GPDMA1)
 #define DMA_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
 #define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ           /*!< Memory to peripheral direction */
 #define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ          /*!< Memory to memory direction     */
+#endif /* GPDMA1 */
+#if defined(LPDMA1)
+#define DMA_PERIPH_TO_MEMORY 0x00000000U             /*!< Kept for porting purpose       */
+#define DMA_MEMORY_TO_PERIPH DMA_PERIPH_TO_MEMORY    /*!< Kept for porting purpose       */
+#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ          /*!< Memory to memory direction     */
+#endif /* LPDMA1 */
 /**
   * @}
   */
@@ -408,10 +483,18 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA Transfer Allocated Port
   * @{
   */
+#if defined(GPDMA1)
 #define DMA_SRC_ALLOCATED_PORT0  0x00000000U  /*!< Source allocated Port 0      */
 #define DMA_SRC_ALLOCATED_PORT1  DMA_CTR1_SAP /*!< Source allocated Port 1      */
 #define DMA_DEST_ALLOCATED_PORT0 0x00000000U  /*!< Destination allocated Port 0 */
 #define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */
+#endif /* GPDMA1 */
+#if defined(LPDMA1)
+#define DMA_SRC_ALLOCATED_PORT0  0x00000000U              /*!< Kept for porting purpose     */
+#define DMA_SRC_ALLOCATED_PORT1  DMA_SRC_ALLOCATED_PORT0  /*!< Kept for porting purpose     */
+#define DMA_DEST_ALLOCATED_PORT0 0x00000000U              /*!< Kept for porting purpose     */
+#define DMA_DEST_ALLOCATED_PORT1 DMA_DEST_ALLOCATED_PORT0 /*!< Kept for porting purpose     */
+#endif /* LPDMA1 */
 
 /**
   * @}
@@ -660,11 +743,11 @@ uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma);
   * @}
   */
 
+#if defined (DMA_PRIVCFGR_PRIV0)
 /** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions
   * @brief    DMA Attributes Functions
   * @{
   */
-#if defined (DMA_PRIVCFGR_PRIV0)
 HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma,
                                                   uint32_t ChannelAttributes);
 HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
@@ -677,10 +760,10 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
                                                    uint32_t *const pLockState);
 
 #endif /* DMA_RCFGLOCKR_LOCK0 */
-#endif /* DMA_PRIVCFGR_PRIV0 */
 /**
   * @}
   */
+#endif /* DMA_PRIVCFGR_PRIV0 */
 
 /**
   * @}
@@ -723,10 +806,17 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
 #define IS_DMA_MODE(MODE) \
   ((MODE) == DMA_NORMAL)
 
+#if defined(GPDMA1)
 #define IS_DMA_DIRECTION(DIRECTION)         \
   (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \
    ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
    ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+#endif /* GPDMA1 */
+#if defined(LPDMA1)
+#define IS_DMA_DIRECTION(DIRECTION)         \
+  (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \
+   ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+#endif /* LPDMA1 */
 
 #define IS_DMA_LEVEL_COMPLETE(LEVEL)     \
   (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \
@@ -763,6 +853,12 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
 #define  IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \
   (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U)
 
+#if defined (GPDMA1)
+#if defined (USART3)
+#define IS_DMA_REQUEST(REQUEST)     \
+  (((REQUEST) == DMA_REQUEST_SW) || \
+   ((REQUEST) <= GPDMA1_REQUEST_USART3_TX))
+#else
 #if defined (LPTIM2)
 #define IS_DMA_REQUEST(REQUEST)     \
   (((REQUEST) == DMA_REQUEST_SW) || \
@@ -772,6 +868,13 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
   (((REQUEST) == DMA_REQUEST_SW) || \
    ((REQUEST) <= GPDMA1_REQUEST_LPTIM1_UE))
 #endif /* LPTIM2 */
+#endif /* USART3 */
+#endif /* GPDMA1 */
+#if defined (LPDMA1)
+#define IS_DMA_REQUEST(REQUEST)     \
+  (((REQUEST) == DMA_REQUEST_SW) || \
+   ((REQUEST) <= LPDMA1_REQUEST_XSPI1))
+#endif /* LPDMA1 */
 
 #define IS_DMA_BLOCK_HW_REQUEST(MODE)   \
   (((MODE) == DMA_BREQ_SINGLE_BURST) || \