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stm32cube: update stm32l1 to cube version V1.10.5
Update Cube version for STM32L1xx series on https://github.com/STMicroelectronics from version v1.10.4 to version v1.10.5 Signed-off-by: Fabrice DJIATSA <[email protected]>
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‎stm32cube/stm32l1xx/drivers/include/Legacy/stm32_hal_legacy.h‎

Lines changed: 117 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,11 +38,13 @@ extern "C" {
3838
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
3939
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
4040
#if defined(STM32H7) || defined(STM32MP1)
41+
#if defined(STM32H7) || defined(STM32MP1)
4142
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
4243
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
4344
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
4445
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
4546
#endif /* STM32H7 || STM32MP1 */
47+
#endif /* STM32H7 || STM32MP1 */
4648
/**
4749
* @}
4850
*/
@@ -275,6 +277,7 @@ extern "C" {
275277
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
276278
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
277279

280+
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
278281
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
279282
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
280283
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
@@ -473,7 +476,7 @@ extern "C" {
473476
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
474477
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
475478
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
476-
#define PAGESIZE FLASH_PAGE_SIZE
479+
/* #define PAGESIZE FLASH_PAGE_SIZE */
477480
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */
478481
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
479482
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
@@ -542,6 +545,10 @@ extern "C" {
542545
#define FLASH_OPTKEY1 FLASH_OPT_KEY1
543546
#define FLASH_OPTKEY2 FLASH_OPT_KEY2
544547
#endif /* STM32H7RS */
548+
#if defined(STM32H7RS)
549+
#define FLASH_OPTKEY1 FLASH_OPT_KEY1
550+
#define FLASH_OPTKEY2 FLASH_OPT_KEY2
551+
#endif /* STM32H7RS */
545552
#if defined(STM32U5)
546553
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
547554
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
@@ -564,6 +571,16 @@ extern "C" {
564571
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
565572
#define OB_nBOOT0_SET OB_NBOOT0_SET
566573
#endif /* STM32U0 */
574+
#if defined(STM32U0)
575+
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
576+
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
577+
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
578+
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
579+
#define OB_USER_nBOOT0 OB_USER_NBOOT0
580+
#define OB_USER_nBOOT1 OB_USER_NBOOT1
581+
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
582+
#define OB_nBOOT0_SET OB_NBOOT0_SET
583+
#endif /* STM32U0 */
567584

568585
/**
569586
* @}
@@ -616,6 +633,15 @@ extern "C" {
616633

617634
#endif /* STM32U5 */
618635

636+
#if defined(STM32U5)
637+
638+
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
639+
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
640+
#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
641+
#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection
642+
643+
#endif /* STM32U5 */
644+
619645
#if defined(STM32H5)
620646
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
621647
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
@@ -822,6 +848,21 @@ extern "C" {
822848
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
823849
#endif /* STM32U5 */
824850

851+
#if defined(STM32WBA)
852+
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
853+
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
854+
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
855+
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
856+
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
857+
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
858+
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
859+
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
860+
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
861+
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
862+
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
863+
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
864+
#endif /* STM32WBA */
865+
825866
#if defined(STM32WBA)
826867
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
827868
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
@@ -894,6 +935,10 @@ extern "C" {
894935
#define HRTIMInterruptResquests HRTIMInterruptRequests
895936
#endif /* STM32F3 || STM32G4 || STM32H7 */
896937

938+
#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
939+
#define HRTIMInterruptResquests HRTIMInterruptRequests
940+
#endif /* STM32F3 || STM32G4 || STM32H7 */
941+
897942
#if defined(STM32G4)
898943
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
899944
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
@@ -1033,6 +1078,7 @@ extern "C" {
10331078
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
10341079
#endif /* STM32F3 */
10351080

1081+
10361082
/**
10371083
* @}
10381084
*/
@@ -1283,10 +1329,12 @@ extern "C" {
12831329
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
12841330
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
12851331

1332+
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
12861333
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
12871334
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
12881335
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
12891336
#endif /* STM32H5 || STM32H7RS || STM32N6 */
1337+
#endif /* STM32H5 || STM32H7RS || STM32N6 */
12901338

12911339
#if defined(STM32WBA)
12921340
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1298,27 +1346,33 @@ extern "C" {
12981346
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
12991347
#endif /* STM32WBA */
13001348

1349+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
13011350
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
13021351
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
13031352
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
13041353
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
1354+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
13051355

1356+
#if defined(STM32F7) || defined(STM32WB)
13061357
#if defined(STM32F7) || defined(STM32WB)
13071358
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
13081359
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
13091360
#endif /* STM32F7 || STM32WB */
1361+
#endif /* STM32F7 || STM32WB */
13101362

13111363
#if defined(STM32H7)
13121364
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
13131365
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
13141366
#endif /* STM32H7 */
13151367

1368+
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
13161369
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
13171370
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
13181371
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
13191372
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
13201373
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
13211374
#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
1375+
#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
13221376

13231377
/**
13241378
* @}
@@ -1485,6 +1539,7 @@ extern "C" {
14851539
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
14861540
#endif
14871541

1542+
#if defined(STM32U5) || defined(STM32MP2)
14881543
#if defined(STM32U5) || defined(STM32MP2)
14891544
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
14901545
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
@@ -1641,6 +1696,8 @@ extern "C" {
16411696

16421697
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
16431698

1699+
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
1700+
16441701
/**
16451702
* @}
16461703
*/
@@ -1851,6 +1908,7 @@ extern "C" {
18511908
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
18521909
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
18531910

1911+
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
18541912
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
18551913
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
18561914
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
@@ -2034,11 +2092,13 @@ extern "C" {
20342092
* @{
20352093
*/
20362094
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
2095+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
20372096
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
20382097
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
20392098
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
20402099
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
20412100
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
2101+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
20422102

20432103
/**
20442104
* @}
@@ -2355,6 +2415,8 @@ extern "C" {
23552415
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
23562416
#endif
23572417
#if defined(STM32F302xE) || defined(STM32F302xC)
2418+
#endif
2419+
#if defined(STM32F302xE) || defined(STM32F302xC)
23582420
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
23592421
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
23602422
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -2389,6 +2451,8 @@ extern "C" {
23892451
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
23902452
#endif
23912453
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
2454+
#endif
2455+
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
23922456
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
23932457
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
23942458
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -2447,6 +2511,8 @@ extern "C" {
24472511
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
24482512
#endif
24492513
#if defined(STM32F373xC) ||defined(STM32F378xx)
2514+
#endif
2515+
#if defined(STM32F373xC) ||defined(STM32F378xx)
24502516
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
24512517
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
24522518
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2464,6 +2530,7 @@ extern "C" {
24642530
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
24652531
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
24662532
#endif
2533+
#endif
24672534
#else
24682535
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
24692536
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -2771,6 +2838,12 @@ extern "C" {
27712838
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
27722839
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
27732840
#endif /* STM32C0 */
2841+
#if defined(STM32C0)
2842+
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
2843+
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
2844+
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
2845+
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
2846+
#endif /* STM32C0 */
27742847
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
27752848
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
27762849
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@@ -3698,9 +3771,15 @@ extern "C" {
36983771
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
36993772
#endif
37003773

3774+
#if defined(STM32U0)
3775+
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
3776+
#endif
3777+
37013778
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
37023779
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
37033780
defined(STM32U0)
3781+
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
3782+
defined(STM32U0)
37043783
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
37053784
#else
37063785
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3803,9 +3882,11 @@ extern "C" {
38033882
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
38043883
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
38053884
#if !defined(STM32U0)
3885+
#if !defined(STM32U0)
38063886
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
38073887
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
38083888
#endif
3889+
#endif
38093890

38103891
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
38113892
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3953,6 +4034,8 @@ extern "C" {
39534034
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
39544035
defined (STM32WBA) || defined (STM32H5) || \
39554036
defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
4037+
defined (STM32WBA) || defined (STM32H5) || \
4038+
defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
39564039
#else
39574040
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39584041
#endif
@@ -3991,6 +4074,9 @@ extern "C" {
39914074
defined (STM32H7) || \
39924075
defined (STM32L0) || defined (STM32L1) || \
39934076
defined (STM32WB)
4077+
defined (STM32H7) || \
4078+
defined (STM32L0) || defined (STM32L1) || \
4079+
defined (STM32WB)
39944080
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
39954081
#endif
39964082

@@ -4273,6 +4359,33 @@ extern "C" {
42734359
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
42744360
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
42754361
#endif
4362+
#if defined(STM32U5)
4363+
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD
4364+
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK
4365+
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC
4366+
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST
4367+
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF
4368+
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT
4369+
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
4370+
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM
4371+
#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
4372+
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ
4373+
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT
4374+
#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0
4375+
#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1
4376+
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM
4377+
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG
4378+
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM
4379+
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM
4380+
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT
4381+
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM
4382+
#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM
4383+
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID
4384+
#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0
4385+
#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1
4386+
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
4387+
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
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#endif
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/**
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* @}
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*/
@@ -4303,6 +4416,9 @@ extern "C" {
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#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
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#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
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#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
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#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
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#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
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/**

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