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djiatsaf-sterwango
djiatsaf-st
authored and
erwango
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stm32cube: update stm32mp1 to cube version 1.7.0
Update Cube version for STM32MP1xx series on https://github.com/STMicroelectronics from version 1.6.0 to version 1.7.0 Signed-off-by: Fabrice DJIATSA <[email protected]>
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‎stm32cube/stm32mp1xx/README‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ Origin:
66
https://github.com/STMicroelectronics/STM32CubeMP1
77

88
Status:
9-
version 1.6.0
9+
version 1.7.0
1010

1111
Purpose:
1212
ST Microelectronics official MCU package for STM32MP1 series.
@@ -23,7 +23,7 @@ URL:
2323
https://github.com/STMicroelectronics/STM32CubeMP1
2424

2525
Commit:
26-
b9a31179d5bf80b3958c3653153bfd4c3a7fc5d5
26+
525d2499658d817a9e669eb17e66390906954895
2727

2828
Maintained-by:
2929
External

‎stm32cube/stm32mp1xx/drivers/include/Legacy/stm32_hal_legacy.h‎

Lines changed: 483 additions & 67 deletions
Large diffs are not rendered by default.

‎stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -145,10 +145,10 @@ typedef enum
145145
(((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1))
146146

147147

148-
#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCSETR_ANA0_SEL_SEL /*!< PA0 analog switch opened */
149-
#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */
150-
#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCSETR_ANA1_SEL_SEL /*!< PA1 analog switch opened */
151-
#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/
148+
#define SYSCFG_SWITCH_PA0_OPEN ((uint32_t)0x00000000) /*!< PA0 analog switch opened */
149+
#define SYSCFG_SWITCH_PA0_CLOSE SYSCFG_PMCSETR_ANA0_SEL_SEL /*!< PA0 analog switch closed */
150+
#define SYSCFG_SWITCH_PA1_OPEN ((uint32_t)0x00000000) /*!< PA1 analog switch opened */
151+
#define SYSCFG_SWITCH_PA1_CLOSE SYSCFG_PMCSETR_ANA1_SEL_SEL /*!< PA1 analog switch closed */
152152

153153
#define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \
154154
(((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \

‎stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_adc_ex.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -682,7 +682,7 @@ typedef struct
682682
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
683683
ADC_CCR_PRESC | \
684684
ADC_CCR_VBATEN | \
685-
ADC_CCR_VSENSEEN | \
685+
ADC_CCR_TSEN | \
686686
ADC_CCR_VREFEN | \
687687
ADC_CCR_DAMDF | \
688688
ADC_CCR_DELAY | \

‎stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_def.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@
3030
#if defined(USE_HAL_LEGACY)
3131
#include "Legacy/stm32_hal_legacy.h"
3232
#endif
33-
#include <stdio.h>
33+
#include <stddef.h>
3434

3535
/* Exported types ------------------------------------------------------------*/
3636

‎stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_i2c.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -223,6 +223,10 @@ typedef struct __I2C_HandleTypeDef
223223

224224
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
225225

226+
__IO uint32_t Devaddress; /*!< I2C Target device address */
227+
228+
__IO uint32_t Memaddress; /*!< I2C Target memory address */
229+
226230
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
227231
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
228232
/*!< I2C Master Tx Transfer completed callback */

‎stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_hal_tim.h‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1913,6 +1913,8 @@ mode.
19131913
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
19141914
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
19151915

1916+
#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
1917+
19161918
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
19171919

19181920
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
@@ -2117,10 +2119,16 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
21172119
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
21182120
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
21192121
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2120-
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2122+
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2123+
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2124+
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
2125+
uint32_t DataLength);
21212126
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
21222127
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2123-
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2128+
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2129+
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2130+
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
2131+
uint32_t DataLength);
21242132
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
21252133
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
21262134
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);

‎stm32cube/stm32mp1xx/drivers/include/stm32mp1xx_ll_adc.h‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -706,7 +706,7 @@ typedef struct
706706
/* only by selecting the corresponding ADC internal channel. */
707707
#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
708708
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
709-
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSEEN) /*!< ADC measurement path to internal channel temperature sensor */
709+
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
710710
#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
711711
#define LL_ADC_PATH_INTERNAL_VDDCORE (ADC2_OR_VDDCOREEN) /*!< ADC measurement path to internal channel Vddcore */
712712
/**
@@ -2390,7 +2390,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO
23902390
}
23912391
else
23922392
{
2393-
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN, PathInternal);
2393+
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
23942394
}
23952395
}
23962396

@@ -2506,7 +2506,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy
25062506
*/
25072507
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
25082508
{
2509-
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN));
2509+
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
25102510
}
25112511

25122512
/**
@@ -5109,7 +5109,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
51095109
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
51105110
+ (AWDThresholdsHighLow));
51115111

5112-
MODIFY_REG(*preg, ADC_LTR1_LT1, AWDThresholdValue);
5112+
MODIFY_REG(*preg, ADC_LTR1_LTR1, AWDThresholdValue);
51135113
}
51145114

51155115
/**
@@ -5141,7 +5141,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_
51415141
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
51425142
+ (AWDThresholdsHighLow));
51435143

5144-
return (uint32_t)(READ_BIT(*preg, ADC_LTR1_LT1));
5144+
return (uint32_t)(READ_BIT(*preg, ADC_LTR1_LTR1));
51455145
}
51465146

51475147
/**
@@ -5284,7 +5284,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
52845284
*/
52855285
__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
52865286
{
5287-
MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OSR_Pos))));
5287+
MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OSVR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OSVR_Pos))));
52885288
}
52895289

52905290
/**
@@ -5296,7 +5296,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint
52965296
*/
52975297
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
52985298
{
5299-
return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OSR))+(1UL << ADC_CFGR2_OSR_Pos)) >> ADC_CFGR2_OSR_Pos);
5299+
return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OSVR))+(1UL << ADC_CFGR2_OSVR_Pos)) >> ADC_CFGR2_OSVR_Pos);
53005300
}
53015301

53025302
/**

‎stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal.c‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@
5454
* @brief STM32MP1xx HAL Driver version number
5555
*/
5656
#define __STM32MP1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
57-
#define __STM32MP1xx_HAL_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
57+
#define __STM32MP1xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
5858
#define __STM32MP1xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
5959
#define __STM32MP1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
6060
#define __STM32MP1xx_HAL_VERSION ((__STM32MP1xx_HAL_VERSION_MAIN << 24)\
@@ -367,7 +367,14 @@ __weak uint32_t HAL_GetTick(void)
367367
return uwTick;
368368
#else
369369
/* tick value directly got from 64bits CA7 register*/
370-
return ( PL1_GetCurrentPhysicalValue() / (HSI_VALUE/1000));
370+
if ((RCC->STGENCKSELR & RCC_STGENCKSELR_STGENSRC) == RCC_STGENCLKSOURCE_HSE)
371+
{
372+
return ((uint32_t)PL1_GetCurrentPhysicalValue() / (HSE_VALUE / 1000UL));
373+
}
374+
else
375+
{
376+
return ((uint32_t)PL1_GetCurrentPhysicalValue() / (HSI_VALUE / 1000UL));
377+
}
371378
#endif
372379

373380
#endif /* CORE_CA7 */

‎stm32cube/stm32mp1xx/drivers/src/stm32mp1xx_hal_adc.c‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -315,7 +315,7 @@
315315
ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
316316
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */
317317

318-
#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSR |\
318+
#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSVR |\
319319
ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
320320
ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going */
321321

@@ -626,7 +626,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
626626
/* - Oversampling mode (continued/resumed) */
627627
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
628628
ADC_CFGR2_ROVSE |
629-
((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OSR_Pos) |
629+
((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OSVR_Pos) |
630630
hadc->Init.Oversampling.RightBitShift |
631631
hadc->Init.Oversampling.TriggeredMode |
632632
hadc->Init.Oversampling.OversamplingStopReset);
@@ -778,7 +778,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
778778

779779
/* Reset register CFGR2 */
780780
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
781-
ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
781+
ADC_CFGR2_OSVR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
782782

783783
/* Reset register SMPR1 */
784784
CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
@@ -789,16 +789,16 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
789789
ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
790790

791791
/* Reset register LTR1 and HTR1 */
792-
CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR1_LT1);
793-
CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR1_HT1);
792+
CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR1_LTR1);
793+
CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR1_HTR1);
794794

795795
/* Reset register LTR2 and HTR2*/
796-
CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR2_LT2);
797-
CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR2_HT2);
796+
CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR2_LTR2);
797+
CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR2_HTR2);
798798

799799
/* Reset register LTR3 and HTR3 */
800-
CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR2_LT2);
801-
CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR2_HT2);
800+
CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR2_LTR2);
801+
CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR2_HTR2);
802802

803803
/* Reset register SQR1 */
804804
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
@@ -3028,8 +3028,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
30283028
tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
30293029

30303030
/* Set the high and low thresholds */
3031-
MODIFY_REG(hadc->Instance->LTR1, ADC_LTR1_LT1 , tmp_awd_low_threshold_shifted);
3032-
MODIFY_REG(hadc->Instance->HTR1, ADC_HTR1_HT1 , tmp_awd_high_threshold_shifted);
3031+
MODIFY_REG(hadc->Instance->LTR1, ADC_LTR1_LTR1 , tmp_awd_low_threshold_shifted);
3032+
MODIFY_REG(hadc->Instance->HTR1, ADC_HTR1_HTR1 , tmp_awd_high_threshold_shifted);
30333033

30343034
/* Update state, clear previous result related to AWD1 */
30353035
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
@@ -3098,14 +3098,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
30983098
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
30993099
{
31003100
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
3101-
MODIFY_REG(hadc->Instance->LTR2, ADC_LTR2_LT2 , tmp_awd_low_threshold_shifted);
3102-
MODIFY_REG(hadc->Instance->HTR2, ADC_HTR2_HT2 , tmp_awd_high_threshold_shifted);
3101+
MODIFY_REG(hadc->Instance->LTR2, ADC_LTR2_LTR2 , tmp_awd_low_threshold_shifted);
3102+
MODIFY_REG(hadc->Instance->HTR2, ADC_HTR2_HTR2 , tmp_awd_high_threshold_shifted);
31033103
}
31043104
else
31053105
{
31063106
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
3107-
MODIFY_REG(hadc->Instance->LTR3, ADC_LTR3_LT3 , tmp_awd_low_threshold_shifted);
3108-
MODIFY_REG(hadc->Instance->HTR3, ADC_HTR3_HT3 , tmp_awd_high_threshold_shifted);
3107+
MODIFY_REG(hadc->Instance->LTR3, ADC_LTR3_LTR3 , tmp_awd_low_threshold_shifted);
3108+
MODIFY_REG(hadc->Instance->HTR3, ADC_HTR3_HTR3 , tmp_awd_high_threshold_shifted);
31093109
}
31103110

31113111
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)

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