diff --git a/lib/CMakeLists.txt b/lib/CMakeLists.txt index df782938d..8a3d92307 100644 --- a/lib/CMakeLists.txt +++ b/lib/CMakeLists.txt @@ -39,6 +39,8 @@ if(CONFIG_HAS_STM32LIB) zephyr_sources(stm32wba/hci/power_table.c) zephyr_sources(stm32wba/hci/scm.c) zephyr_sources(stm32wba/hci/log_module.c) + zephyr_sources(stm32wba/hci/linklayer_plat.c) + zephyr_sources(stm32wba/hci/ll_sys_if.c) if(CONFIG_FLASH) zephyr_sources(stm32wba/hci/flash_manager.c) zephyr_sources(stm32wba/hci/flash_driver.c) diff --git a/lib/stm32wba/hci/README b/lib/stm32wba/hci/README index 16be36ef5..38836f979 100644 --- a/lib/stm32wba/hci/README +++ b/lib/stm32wba/hci/README @@ -6,7 +6,7 @@ Origin: https://github.com/STMicroelectronics/STM32CubeWBA Status: - version v1.3.1 + version v1.4.1 Purpose: This library is used on STM32WBA series to port BLE controller library in @@ -33,6 +33,7 @@ Description: Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/inc/os_wrapper.h Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/inc/power_table.h Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/inc/pta.h + Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_intf_cmn.h Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/ble_full/ll_fw_config.h Middlewares/ST/STM32_WPAN/link_layer/ll_sys/inc/linklayer_plat.h Middlewares/ST/STM32_WPAN/link_layer/ll_sys/inc/ll_sys.h @@ -74,6 +75,8 @@ Description: Projects/NUCLEO-WBA55CG/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/power_table.c Projects/NUCLEO-WBA55CG/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/bpka.c Projects/NUCLEO-WBA55CG/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/bpka.h + Projects/NUCLEO-WBA55CG/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/linklayer_plat.c + Projects/NUCLEO-WBA55CG/Applications/BLE/BLE_HeartRate/STM32_WPAN/Target/ll_sys_if.c Utilities/trace/adv_trace/stm32_adv_trace.h Utilities/misc/stm32_mem.h Utilities/tim_serv/stm32_timer.h @@ -87,7 +90,7 @@ URL: https://github.com/STMicroelectronics/STM32CubeWBA Commit: - 8d1d0ffef7a3a25d8ee8f589a614bc5da65c9300 + 3820501e7e128592290861c9cc0f7189246bf00d Maintained-by: External @@ -116,6 +119,13 @@ Patch List: main.h app_conf.h scm.c + ll_intf_cmn.h + ll_sys_if.c + linklayer_plat.c + + * #ifndef __ZEPHYR__ applied to remove Cube specific implementation + Impacted files: ll_sys_if.c + linklayer_plat.c * Changes from official delivery: - dos2unix applied diff --git a/lib/stm32wba/hci/app_conf.h b/lib/stm32wba/hci/app_conf.h index 78ea70b68..d19be4663 100644 --- a/lib/stm32wba/hci/app_conf.h +++ b/lib/stm32wba/hci/app_conf.h @@ -25,8 +25,6 @@ /* Includes ------------------------------------------------------------------*/ #include "hw_if.h" #include "utilities_conf.h" -#include "blestack.h" -/* #include "log_module.h" */ /* USER CODE BEGIN Includes */ @@ -51,7 +49,7 @@ /** * Define BD_ADDR type: define proper address. Can only be GAP_PUBLIC_ADDR (0x00) or GAP_STATIC_RANDOM_ADDR (0x01) */ -#define CFG_BD_ADDRESS_TYPE (GAP_PUBLIC_ADDR) +#define CFG_BD_ADDRESS_DEVICE (GAP_PUBLIC_ADDR) /** * Define privacy: PRIVACY_DISABLED or PRIVACY_ENABLED @@ -64,7 +62,7 @@ * if CFG_PRIVACY equals PRIVACY_DISABLED, CFG_BLE_ADDRESS_TYPE has 2 allowed values: GAP_PUBLIC_ADDR or GAP_STATIC_RANDOM_ADDR * if CFG_PRIVACY equals PRIVACY_ENABLED, CFG_BLE_ADDRESS_TYPE has 2 allowed values: GAP_RESOLVABLE_PRIVATE_ADDR or GAP_NON_RESOLVABLE_PRIVATE_ADDR */ -#define CFG_BLE_ADDRESS_TYPE (GAP_PUBLIC_ADDR) +#define CFG_BD_ADDRESS_TYPE (GAP_PUBLIC_ADDR) #define ADV_INTERVAL_MIN (0x0080) #define ADV_INTERVAL_MAX (0x00A0) @@ -76,31 +74,31 @@ /** * Define IO Authentication */ -#define CFG_BONDING_MODE (1) -#define CFG_USED_FIXED_PIN (0) /* 0->fixed pin is used ; 1->No fixed pin used*/ -#define CFG_FIXED_PIN (111111) -#define CFG_ENCRYPTION_KEY_SIZE_MAX (16) -#define CFG_ENCRYPTION_KEY_SIZE_MIN (8) +#define CFG_BONDING_MODE (1) +#define CFG_USED_FIXED_PIN (0) /* 0->fixed pin is used ; 1->No fixed pin used*/ +#define CFG_FIXED_PIN (111111) +#define CFG_ENCRYPTION_KEY_SIZE_MAX (16) +#define CFG_ENCRYPTION_KEY_SIZE_MIN (8) /** * Define Input Output capabilities */ -#define CFG_IO_CAPABILITY (IO_CAP_DISPLAY_YES_NO) +#define CFG_IO_CAPABILITY (IO_CAP_DISPLAY_YES_NO) /** * Define Man In The Middle modes */ -#define CFG_MITM_PROTECTION (MITM_PROTECTION_REQUIRED) +#define CFG_MITM_PROTECTION (MITM_PROTECTION_REQUIRED) /** * Define Secure Connections Support */ -#define CFG_SC_SUPPORT (SC_PAIRING_OPTIONAL) +#define CFG_SC_SUPPORT (SC_PAIRING_OPTIONAL) /** * Define Keypress Notification Support */ -#define CFG_KEYPRESS_NOTIFICATION_SUPPORT (KEYPRESS_NOT_SUPPORTED) +#define CFG_KEYPRESS_NOTIFICATION_SUPPORT (KEYPRESS_NOT_SUPPORTED) /** * Identity root key used to derive IRK and DHK(Legacy) @@ -233,6 +231,9 @@ #define CFG_LPM_LEVEL (2) #define CFG_LPM_STDBY_SUPPORTED (1) +/* Defines time to wake up from standby before radio event to meet timings */ +#define CFG_LPM_STDBY_WAKEUP_TIME (1500) + /* USER CODE BEGIN Low_Power 0 */ /* USER CODE END Low_Power 0 */ @@ -245,6 +246,8 @@ typedef enum { CFG_LPM_APP, CFG_LPM_LOG, + CFG_LPM_LL_DEEPSLEEP, + CFG_LPM_LL_HW_RCO_CLBR, /* USER CODE BEGIN CFG_LPM_Id_t */ /* USER CODE END CFG_LPM_Id_t */ @@ -287,6 +290,9 @@ typedef enum #define CFG_LOG_INSERT_TIME_STAMP_INSIDE_THE_TRACE (0U) #define CFG_LOG_INSERT_EOL_INSIDE_THE_TRACE (0U) +#define CFG_LOG_TRACE_FIFO_SIZE (4096U) +#define CFG_LOG_TRACE_BUF_SIZE (256U) + /* macro ensuring retrocompatibility with old applications */ #define APP_DBG LOG_INFO_APP #define APP_DBG_MSG LOG_INFO_APP @@ -314,14 +320,14 @@ typedef enum */ typedef enum { - CFG_TASK_HW_RNG, /* Task linked to chip internal peripheral. */ - CFG_TASK_LINK_LAYER, /* Tasks linked to Communications Layers. */ + CFG_TASK_HW_RNG, + CFG_TASK_LINK_LAYER, CFG_TASK_HCI_ASYNCH_EVT_ID, - CFG_TASK_LINK_LAYER_TEMP_MEAS, + CFG_TASK_TEMP_MEAS, CFG_TASK_BLE_HOST, + CFG_TASK_AMM, CFG_TASK_BPKA, - CFG_TASK_AMM_BCKGND, - CFG_TASK_FLASH_MANAGER_BCKGND, + CFG_TASK_FLASH_MANAGER, CFG_TASK_BLE_TIMER_BCKGND, /* USER CODE BEGIN CFG_Task_Id_t */ TASK_BUTTON_1, @@ -351,6 +357,9 @@ typedef enum CFG_SEQ_PRIO_NBR /* Shall be LAST in the list */ } CFG_SEQ_Prio_Id_t; +/* Sequencer configuration */ +#define UTIL_SEQ_CONF_PRIO_NBR CFG_SEQ_PRIO_NBR + /** * This is a bit mapping over 32bits listing all events id supported in the application */ @@ -362,16 +371,6 @@ typedef enum /* USER CODE END CFG_IdleEvt_Id_t */ } CFG_IdleEvt_Id_t; -/* Sequencer priorities by default */ -#define CFG_TASK_PRIO_HW_RNG CFG_SEQ_PRIO_0 -#define CFG_TASK_PRIO_LINK_LAYER CFG_SEQ_PRIO_0 -/* USER CODE BEGIN TASK_Priority_Define */ - -/* USER CODE END TASK_Priority_Define */ - -/* Used by Sequencer */ -#define UTIL_SEQ_CONF_PRIO_NBR CFG_SEQ_PRIO_NBR - /** * These are the lists of events id registered to the sequencer * Each event id shall be in the range [0:31] @@ -385,6 +384,9 @@ typedef enum } CFG_Event_Id_t; /**< Events defines */ +/* USER CODE BEGIN EVENT_ID_Define */ + +/* USER CODE END EVENT_ID_Define */ /****************************************************************************** * NVM configuration @@ -464,6 +466,12 @@ typedef enum */ #define CFG_RF_TX_POWER_TABLE_ID (1) +/* Custom LSE sleep clock accuracy to use if both conditions are met: + * - LSE is selected as Link Layer sleep clock source + * - the LSE used is different from the default one. + */ +#define CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE (0) + /* USER CODE BEGIN Radio_Configuration */ /* USER CODE END Radio_Configuration */ diff --git a/lib/stm32wba/hci/app_entry.h b/lib/stm32wba/hci/app_entry.h index 510e20f24..bd1a7754e 100644 --- a/lib/stm32wba/hci/app_entry.h +++ b/lib/stm32wba/hci/app_entry.h @@ -43,7 +43,22 @@ extern "C" { #define WPAN_SUCCESS 0u /* USER CODE BEGIN EC */ - +/****************************************************************************** + * Information Table + * + * Version + * [0:3] = Build - 0: Untracked - 15:Released - x: Tracked version + * [4:7] = branch - 0: Mass Market - x: ... + * [8:15] = Subversion + * [16:23] = Version minor + * [24:31] = Version major + * + ******************************************************************************/ +#define CFG_FW_BUILD (0) +#define CFG_FW_BRANCH (0) +#define CFG_FW_SUBVERSION (1) +#define CFG_FW_MINOR_VERSION (4) +#define CFG_FW_MAJOR_VERSION (1) /* USER CODE END EC */ /* Exported variables --------------------------------------------------------*/ diff --git a/lib/stm32wba/hci/auto/ble_types.h b/lib/stm32wba/hci/auto/ble_types.h index c1f8bc34d..ca5f3a157 100644 --- a/lib/stm32wba/hci/auto/ble_types.h +++ b/lib/stm32wba/hci/auto/ble_types.h @@ -2497,6 +2497,22 @@ typedef __PACKED_STRUCT uint8_t Status; } aci_hal_continuous_tx_start_rp0; +typedef __PACKED_STRUCT +{ + uint8_t Mode; + uint8_t Key[16]; + uint8_t IV[8]; + uint16_t In_Data_Length; + uint8_t In_Data[BLE_CMD_MAX_PARAM_LEN - 27]; +} aci_hal_ead_encrypt_decrypt_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Out_Data_Length; + uint8_t Out_Data[(BLE_EVT_MAX_PARAM_LEN - 3) - 3]; +} aci_hal_ead_encrypt_decrypt_rp0; + typedef __PACKED_STRUCT { uint8_t Status; diff --git a/lib/stm32wba/hci/ble_bufsize.h b/lib/stm32wba/hci/ble_bufsize.h index 437f27e3f..e3e3d7f7e 100644 --- a/lib/stm32wba/hci/ble_bufsize.h +++ b/lib/stm32wba/hci/ble_bufsize.h @@ -1,6 +1,5 @@ /***************************************************************************** * @file ble_bufsize.h - * @author MDG * @brief Definition of BLE stack buffers size ***************************************************************************** * @attention @@ -49,7 +48,7 @@ */ #define BLE_MEM_BLOCK_SIZE 32 -#if (BASIC_FEATURES != 0) +#if ((BASIC_FEATURES != 0)||(PERIPHERAL_ONLY != 0)) #define BLE_MEM_BLOCK_X_PTX(n_link) 0 #else #define BLE_MEM_BLOCK_X_PTX(n_link) (n_link) @@ -96,19 +95,24 @@ * - a part, that may be considered "fixed", i.e. independent from the above * mentioned parameters. */ -#if (BASIC_FEATURES != 0) -#define BLE_FIXED_BUFFER_SIZE_BYTES 244 /* Basic Features */ +#if (PERIPHERAL_ONLY != 0) +#define BLE_FIXED_BUFFER_SIZE_BYTES 4 /* Peripheral Only */ +#elif (BASIC_FEATURES != 0) +#define BLE_FIXED_BUFFER_SIZE_BYTES 260 /* Basic Features */ #else -#define BLE_FIXED_BUFFER_SIZE_BYTES 660 /* Full stack */ +#define BLE_FIXED_BUFFER_SIZE_BYTES 676 /* Full stack / Basic Plus */ #endif /* * BLE_PER_LINK_SIZE_BYTES: additional memory size used per link */ -#if (BASIC_FEATURES != 0) + +#if (PERIPHERAL_ONLY != 0) +#define BLE_PER_LINK_SIZE_BYTES 148 /* Peripheral Only */ +#elif (BASIC_FEATURES != 0) #define BLE_PER_LINK_SIZE_BYTES 176 /* Basic Features */ #else -#define BLE_PER_LINK_SIZE_BYTES 188 /* Full stack */ +#define BLE_PER_LINK_SIZE_BYTES 188 /* Full stack / Basic Plus */ #endif /* diff --git a/lib/stm32wba/hci/ble_const.h b/lib/stm32wba/hci/ble_const.h index fa93730ba..58001e503 100644 --- a/lib/stm32wba/hci/ble_const.h +++ b/lib/stm32wba/hci/ble_const.h @@ -1,6 +1,6 @@ /***************************************************************************** * @file ble_const.h - * @author MDG + * * @brief This file contains the definitions which are compiler dependent. ***************************************************************************** * @attention @@ -32,6 +32,9 @@ #ifndef BASIC_PLUS #define BASIC_PLUS 0 #endif +#ifndef PERIPHERAL_ONLY +#define PERIPHERAL_ONLY 0 +#endif #ifndef LL_ONLY #define LL_ONLY 0 #endif diff --git a/lib/stm32wba/hci/ble_defs.h b/lib/stm32wba/hci/ble_defs.h index b5cfa0743..05abb1d5b 100644 --- a/lib/stm32wba/hci/ble_defs.h +++ b/lib/stm32wba/hci/ble_defs.h @@ -1,6 +1,6 @@ /***************************************************************************** * @file ble_defs.h - * @author MDG + * * @brief This file contains definitions used for BLE Stack interface. ***************************************************************************** * @attention diff --git a/lib/stm32wba/hci/ble_std.h b/lib/stm32wba/hci/ble_std.h index c9177bf3a..739f8ab4b 100644 --- a/lib/stm32wba/hci/ble_std.h +++ b/lib/stm32wba/hci/ble_std.h @@ -1,6 +1,6 @@ /****************************************************************************** * @file ble_std.h - * @author MDG + * * @brief BLE standard definitions ****************************************************************************** * @attention diff --git a/lib/stm32wba/hci/bleplat.h b/lib/stm32wba/hci/bleplat.h index e0265311f..1d4ffe3d1 100644 --- a/lib/stm32wba/hci/bleplat.h +++ b/lib/stm32wba/hci/bleplat.h @@ -1,6 +1,6 @@ /***************************************************************************** * @file bleplat.h - * @author MDG + * * @brief This file contains the interface of the BLE platform layer * (lower interface of the BLE stack library). * It is included by the STM32WBX BLE stack library. @@ -222,6 +222,34 @@ extern void BLEPLAT_AesCmacCompute( const uint8_t* input, uint32_t input_length, uint8_t* output_tag ); +/** + * @brief CCM computation + * + * @param mode: CCM mode (0=encryption, 1=decryption) + * @param key: AES encryption key (16 bytes) + * @param iv_length: IV length (in bytes) + * @param iv: IV data + * @param add_length: add length (in bytes) + * @param add: add data + * @param input_length: input data length (in bytes) + * @param inputL: original data (to be encrypted or decrypted) + * @param tag_length: CCM tag length (in bytes) + * @param tag: CCM tag + * @param output: result data (encrypted or decrypted) + * @retval status (BLEPLAT_XX) + */ +extern int BLEPLAT_AesCcmCrypt( uint8_t mode, + const uint8_t* key, + uint8_t iv_length, + const uint8_t* iv, + uint16_t add_length, + const uint8_t* add, + uint32_t input_length, + const uint8_t* input, + uint8_t tag_length, + uint8_t* tag, + uint8_t* output ); + /* Random Number Generation (RNG) interface: */ diff --git a/lib/stm32wba/hci/blestack.h b/lib/stm32wba/hci/blestack.h index 8166ce05c..b313a84d3 100644 --- a/lib/stm32wba/hci/blestack.h +++ b/lib/stm32wba/hci/blestack.h @@ -1,6 +1,6 @@ /***************************************************************************** * @file blestack.h - * @author MDG + * * @brief Header file for BLE stack ***************************************************************************** * @attention diff --git a/lib/stm32wba/hci/flash_driver.c b/lib/stm32wba/hci/flash_driver.c index 8d705c09a..e3a4bf175 100644 --- a/lib/stm32wba/hci/flash_driver.c +++ b/lib/stm32wba/hci/flash_driver.c @@ -109,6 +109,15 @@ FD_FlashOp_Status_t FD_EraseSectors(uint32_t Sect) uint32_t page_error; FLASH_EraseInitTypeDef p_erase_init; +#ifndef FLASH_DBANK_SUPPORT + if (FLASH_PAGE_NB < Sect) +#else + if ((FLASH_PAGE_NB * 2u) < Sect) +#endif + { + return status; + } + /* Check if LL allows flash access */ if ((FD_Flash_Control_status & (1u << FD_FLASHACCESS_RFTS)) && (FD_Flash_Control_status & (1u << FD_FLASHACCESS_RFTS_BYPASS))) @@ -120,9 +129,21 @@ FD_FlashOp_Status_t FD_EraseSectors(uint32_t Sect) while (FD_Flash_Control_status & (1u << FD_FLASHACCESS_SYSTEM)); p_erase_init.TypeErase = FLASH_TYPEERASE_PAGES; - p_erase_init.Page = Sect; + p_erase_init.Page = (Sect & (FLASH_PAGE_NB - 1u)); p_erase_init.NbPages = 1; +#if defined(FLASH_DBANK_SUPPORT) + /* Verify which Bank is impacted */ + if ((FLASH_PAGE_NB <= Sect) ^ (OB_SWAP_BANK_ENABLE == READ_BIT (FLASH->OPTR, FLASH_OPTR_SWAP_BANK_Msk))) + { + p_erase_init.Banks = FLASH_BANK_2; + } + else + { + p_erase_init.Banks = FLASH_BANK_1; + } +#endif + if (HAL_FLASHEx_Erase(&p_erase_init, &page_error) == HAL_OK) { status = FD_FLASHOP_SUCCESS; diff --git a/lib/stm32wba/hci/flash_manager.c b/lib/stm32wba/hci/flash_manager.c index d92ef06ca..108dd388a 100644 --- a/lib/stm32wba/hci/flash_manager.c +++ b/lib/stm32wba/hci/flash_manager.c @@ -61,7 +61,7 @@ typedef struct FM_FlashOpConfig }FM_FlashOpConfig_t; /* Private defines -----------------------------------------------------------*/ - +#define FLASH_PAGE_NBR (FLASH_SIZE / FLASH_PAGE_SIZE) #define FLASH_WRITE_BLOCK_SIZE 4U #define ALIGNMENT_32 0x00000003 #define ALIGNMENT_128 0x0000000F @@ -134,8 +134,8 @@ FM_Cmd_Status_t FM_Write(uint32_t *Src, uint32_t *Dest, int32_t Size, FM_Callbac { FM_Cmd_Status_t status; - if (((uint32_t)Dest < FLASH_BASE) || ((uint32_t)Dest > (FLASH_BASE + FLASH_BANK_SIZE)) - || (((uint32_t)Dest + Size) > (FLASH_BASE + FLASH_BANK_SIZE))) + if (((uint32_t)Dest < FLASH_BASE) || ((uint32_t)Dest > (FLASH_BASE + FLASH_SIZE)) + || (((uint32_t)Dest + Size) > (FLASH_BASE + FLASH_SIZE))) { LOG_ERROR_SYSTEM("\r\nFM_Write - Destination address not part of the flash"); @@ -185,7 +185,7 @@ FM_Cmd_Status_t FM_Erase(uint32_t FirstSect, uint32_t NbrSect, FM_CallbackNode_t { FM_Cmd_Status_t status; - if ((FirstSect > FLASH_PAGE_NB) || ((FirstSect + NbrSect) > FLASH_PAGE_NB)) + if ((FirstSect > FLASH_PAGE_NBR) || ((FirstSect + NbrSect) > FLASH_PAGE_NBR)) { LOG_ERROR_SYSTEM("\r\nFM_Erase - Inconsistent request"); diff --git a/lib/stm32wba/hci/hw.h b/lib/stm32wba/hci/hw.h index 417b9a6cf..76aaa831c 100644 --- a/lib/stm32wba/hci/hw.h +++ b/lib/stm32wba/hci/hw.h @@ -122,6 +122,36 @@ extern void HW_AES_Crypt( const uint32_t* input, */ extern void HW_AES_Disable( void ); +/* + * HW_AES_InitCcm + * + * Initilaizes AES for CCM encryption (decrypt = 0) or decryption (decrypt = 1) + * Note: B0 and B1 4-word blocks must be provided by user. + * + */ +extern void HW_AES_InitCcm( uint8_t decrypt, + const uint8_t* key, + const uint32_t* b0, + const uint32_t* b1 ); + +/* + * HW_AES_EndCcm + * + * Completes CCM processing by computing the authentication tag + * + */ +extern void HW_AES_EndCcm( uint8_t tag_length, + uint8_t* tag ); + +/* + * HW_AES_SetLast + * + * Function used in CCM processing to indicate the last block of data in + * case of decryption + * + */ +extern void HW_AES_SetLast( uint8_t left_length ); + /* --------------------------------------------------------------------------- * PKA * --------------------------------------------------------------------------- diff --git a/lib/stm32wba/hci/hw_aes.c b/lib/stm32wba/hci/hw_aes.c index cad739801..fef4fc169 100644 --- a/lib/stm32wba/hci/hw_aes.c +++ b/lib/stm32wba/hci/hw_aes.c @@ -177,3 +177,92 @@ void HW_AES_Disable( void ) } /*****************************************************************************/ + +void HW_AES_InitCcm( uint8_t decrypt, + const uint8_t* key, + const uint32_t* b0, + const uint32_t* b1 ) +{ + uint32_t tmp[4], mode = decrypt ? AES_CR_MODE_1 : 0; + + /* CCM init phase */ + HW_AESX->CR = AES_CR_CHMOD_2 | mode; + + /* Copy key bytes to the AES registers */ + memcpy( tmp, key, 16 ); + HW_AESX->KEYR0 = tmp[0]; + HW_AESX->KEYR1 = tmp[1]; + HW_AESX->KEYR2 = tmp[2]; + HW_AESX->KEYR3 = tmp[3]; + + /* Copy B0 bytes to the AES registers */ + HW_AESX->IVR3 = __REV( b0[0] ); + HW_AESX->IVR2 = __REV( b0[1] ); + HW_AESX->IVR1 = __REV( b0[2] ); + HW_AESX->IVR0 = __REV( b0[3] ); + + /* Enable AES processing */ + HW_AESX->CR |= AES_CR_EN; + + /* Wait for CCF flag to be raised */ + while ( ! (HW_AESX->SR & AES_SR_CCF) ); + + /* Clear CCF Flag */ + HW_AESX->ICR |= AES_ICR_CCF; + + /* CCM header phase */ + HW_AESX->CR = AES_CR_CHMOD_2 | AES_CR_GCMPH_0 | AES_CR_DATATYPE_1; + + /* Enable AES processing */ + HW_AESX->CR |= AES_CR_EN; + + /* Write the header block B1 into the input FIFO */ + HW_AESX->DINR = b1[0]; + HW_AESX->DINR = b1[1]; + HW_AESX->DINR = b1[2]; + HW_AESX->DINR = b1[3]; + + /* Wait for CCF flag to be raised */ + while ( !(HW_AESX->SR & AES_SR_CCF) ); + + /* Clear CCF Flag */ + HW_AESX->ICR |= AES_ICR_CCF; + + /* CCM payload phase */ + HW_AESX->CR = (AES_CR_EN | AES_CR_CHMOD_2 | + AES_CR_GCMPH_1 | AES_CR_DATATYPE_1 | mode); +} + +/*****************************************************************************/ + +void HW_AES_EndCcm( uint8_t tag_length, + uint8_t* tag ) +{ + uint32_t tmp[4]; + + /* CCM final phase */ + HW_AESX->CR = (AES_CR_EN | AES_CR_CHMOD_2 | + AES_CR_GCMPH_0 | AES_CR_GCMPH_1 | AES_CR_DATATYPE_1); + + /* Wait for CCF flag to be raised */ + while ( !(HW_AESX->SR & AES_SR_CCF) ); + + /* Read the output block from the output FIFO */ + tmp[0] = HW_AESX->DOUTR; + tmp[1] = HW_AESX->DOUTR; + tmp[2] = HW_AESX->DOUTR; + tmp[3] = HW_AESX->DOUTR; + memcpy( tag, tmp, tag_length ); + + /* Clear CCF Flag */ + HW_AESX->ICR |= AES_ICR_CCF; +} + +/*****************************************************************************/ + +void HW_AES_SetLast( uint8_t left_length ) +{ + HW_AESX->CR |= (16UL - left_length) << AES_CR_NPBLB_Pos; +} + +/*****************************************************************************/ diff --git a/lib/stm32wba/hci/linklayer_plat.c b/lib/stm32wba/hci/linklayer_plat.c new file mode 100644 index 000000000..138487b18 --- /dev/null +++ b/lib/stm32wba/hci/linklayer_plat.c @@ -0,0 +1,564 @@ +/* + * Copyright (c) 2023 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + + + +/* USER CODE END Header */ + +#ifndef __ZEPHYR__ +#include "stm32wbaxx_hal.h" +#include "stm32wbaxx_hal_conf.h" +#include "stm32wbaxx_ll_rcc.h" + +#include "app_common.h" +#include "app_conf.h" +#include "linklayer_plat.h" +#include "scm.h" +#include "log_module.h" +#if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) +#include "adc_ctrl.h" +#endif /* (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) */ + +#if (CFG_LPM_LEVEL != 0) +#include "stm32_lpm.h" +#endif /* (CFG_LPM_LEVEL != 0) */ +/* USER CODE BEGIN Includes */ + +#else +#include "scm.h" +#endif +#define max(a,b) ((a) > (b) ? a : b) + +/* 2.4GHz RADIO ISR callbacks */ +typedef void (*radio_isr_cb_t) (void); + + + +/* Radio critical sections */ +static uint32_t primask_bit = 0; +volatile int32_t irq_counter; + +/* Radio bus clock control variables */ +uint8_t AHB5_SwitchedOff; +uint32_t radio_sleep_timer_val; + +/** + * @brief Configure the necessary clock sources for the radio. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_ClockInit(void) +{ + AHB5_SwitchedOff = 0; + radio_sleep_timer_val = 0; + + LL_PWR_EnableBkUpAccess(); + + /* Select LSE as Sleep CLK */ + __HAL_RCC_RADIOSLPTIM_CONFIG(RCC_RADIOSTCLKSOURCE_LSE); + + LL_PWR_DisableBkUpAccess(); + + /* Enable AHB5ENR peripheral clock (bus CLK) */ + __HAL_RCC_RADIO_CLK_ENABLE(); +} + +#ifndef __ZEPHYR__ +/** + * @brief Link Layer active waiting loop. + * @param delay: delay in us + * @retval None + */ +void LINKLAYER_PLAT_DelayUs(uint32_t delay) +{ +__IO register uint32_t Delay = delay * (SystemCoreClock / 1000000U); + do + { + __NOP(); + } + while (Delay --); +} + +/** + * @brief Link Layer assertion API + * @param condition: conditional statement to be checked. + * @retval None + */ +void LINKLAYER_PLAT_Assert(uint8_t condition) +{ + assert_param(condition); +} +#endif + +/** + * @brief Enable/disable the Link Layer active clock (baseband clock). + * @param enable: boolean value to enable (1) or disable (0) the clock. + * @retval None + */ +void LINKLAYER_PLAT_WaitHclkRdy(void) +{ + /* Wait on radio bus clock readiness */ + while(HAL_RCCEx_GetRadioBusClockReadiness() != RCC_RADIO_BUS_CLOCK_READY); +} + +/** + * @brief Active wait on bus clock readiness. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_AclkCtrl(uint8_t enable) +{ + if(enable){ + /* Enable RADIO baseband clock (active CLK) */ + HAL_RCCEx_EnableRadioBBClock(); + + /* Polling on HSE32 activation */ + while ( LL_RCC_HSE_IsReady() == 0); + } + else + { + /* Disable RADIO baseband clock (active CLK) */ + HAL_RCCEx_DisableRadioBBClock(); + } +} + +#ifndef __ZEPHYR__ +/** + * @brief Link Layer RNG request. + * @param ptr_rnd: pointer to the variable that hosts the number. + * @param len: number of byte of anthropy to get. + * @retval None + */ +void LINKLAYER_PLAT_GetRNG(uint8_t *ptr_rnd, uint32_t len) +{ + uint32_t nb_remaining_rng = len; + uint32_t generated_rng; + + /* Get the requested RNGs (4 bytes by 4bytes) */ + while(nb_remaining_rng >= 4) + { + generated_rng = 0; + HW_RNG_Get(1, &generated_rng); + memcpy((ptr_rnd+(len-nb_remaining_rng)), &generated_rng, 4); + nb_remaining_rng -=4; + } + + /* Get the remaining number of RNGs */ + if(nb_remaining_rng>0){ + generated_rng = 0; + HW_RNG_Get(1, &generated_rng); + memcpy((ptr_rnd+(len-nb_remaining_rng)), &generated_rng, nb_remaining_rng); + } +} + +/** + * @brief Initialize Link Layer radio high priority interrupt. + * @param intr_cb: function pointer to assign for the radio high priority ISR routine. + * @retval None + */ +void LINKLAYER_PLAT_SetupRadioIT(void (*intr_cb)()) +{ + radio_callback = intr_cb; + HAL_NVIC_SetPriority((IRQn_Type) RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH, 0); + HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_INTR_NUM); +} + +/** + * @brief Initialize Link Layer SW low priority interrupt. + * @param intr_cb: function pointer to assign for the SW low priority ISR routine. + * @retval None + */ +void LINKLAYER_PLAT_SetupSwLowIT(void (*intr_cb)()) +{ + low_isr_callback = intr_cb; + + HAL_NVIC_SetPriority((IRQn_Type) RADIO_SW_LOW_INTR_NUM, RADIO_SW_LOW_INTR_PRIO, 0); + HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_SW_LOW_INTR_NUM); +} + +/** + * @brief Trigger the link layer SW low interrupt. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_TriggerSwLowIT(uint8_t priority) +{ + uint8_t low_isr_priority = RADIO_INTR_PRIO_LOW; + + /* Check if a SW low interrupt as already been raised. + * Nested call far radio low isr are not supported + **/ + + if(NVIC_GetActive(RADIO_SW_LOW_INTR_NUM) == 0) + { + /* No nested SW low ISR, default behavior */ + + if(priority == 0) + { + low_isr_priority = RADIO_SW_LOW_INTR_PRIO; + } + + HAL_NVIC_SetPriority((IRQn_Type) RADIO_SW_LOW_INTR_NUM, low_isr_priority, 0); + } + else + { + /* Nested call detected */ + /* No change for SW radio low interrupt priority for the moment */ + + if(priority != 0) + { + /* At the end of current SW radio low ISR, this pending SW low interrupt + * will run with RADIO_INTR_PRIO_LOW priority + **/ + radio_sw_low_isr_is_running_high_prio = 1; + } + } + + HAL_NVIC_SetPendingIRQ((IRQn_Type) RADIO_SW_LOW_INTR_NUM); +} +#endif + +/** + * @brief Enable interrupts. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_EnableIRQ(void) +{ + irq_counter = max(0,irq_counter-1); + + if(irq_counter == 0) + { + /* When irq_counter reaches 0, restore primask bit */ + __set_PRIMASK(primask_bit); + } +} + +/** + * @brief Disable interrupts. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_DisableIRQ(void) +{ + if(irq_counter == 0) + { + /* Save primask bit at first interrupt disablement */ + primask_bit= __get_PRIMASK(); + } + __disable_irq(); + irq_counter ++; +} + +#ifndef __ZEPHYR__ +/** + * @brief Enable specific interrupt group. + * @param isr_type: mask for interrupt group to enable. + * This parameter can be one of the following: + * @arg LL_HIGH_ISR_ONLY: enable link layer high priority ISR. + * @arg LL_LOW_ISR_ONLY: enable link layer SW low priority ISR. + * @arg SYS_LOW_ISR: mask interrupts for all the other system ISR with + * lower priority that link layer SW low interrupt. + * @retval None + */ +void LINKLAYER_PLAT_EnableSpecificIRQ(uint8_t isr_type) +{ + if( (isr_type & LL_HIGH_ISR_ONLY) != 0 ) + { + prio_high_isr_counter--; + if(prio_high_isr_counter == 0) + { + /* When specific counter for link layer high ISR reaches 0, interrupt is enabled */ + HAL_NVIC_EnableIRQ(RADIO_INTR_NUM); + /* USER CODE BEGIN LINKLAYER_PLAT_EnableSpecificIRQ_1*/ + + /* USER CODE END LINKLAYER_PLAT_EnableSpecificIRQ_1*/ + } + } + + if( (isr_type & LL_LOW_ISR_ONLY) != 0 ) + { + prio_low_isr_counter--; + if(prio_low_isr_counter == 0) + { + /* When specific counter for link layer SW low ISR reaches 0, interrupt is enabled */ + HAL_NVIC_EnableIRQ(RADIO_SW_LOW_INTR_NUM); + } + + } + + if( (isr_type & SYS_LOW_ISR) != 0 ) + { + prio_sys_isr_counter--; + if(prio_sys_isr_counter == 0) + { + /* Restore basepri value */ + __set_BASEPRI(local_basepri_value); + } + } +} + +/** + * @brief Disable specific interrupt group. + * @param isr_type: mask for interrupt group to disable. + * This parameter can be one of the following: + * @arg LL_HIGH_ISR_ONLY: disable link layer high priority ISR. + * @arg LL_LOW_ISR_ONLY: disable link layer SW low priority ISR. + * @arg SYS_LOW_ISR: unmask interrupts for all the other system ISR with + * lower priority that link layer SW low interrupt. + * @retval None + */ +void LINKLAYER_PLAT_DisableSpecificIRQ(uint8_t isr_type) +{ + if( (isr_type & LL_HIGH_ISR_ONLY) != 0 ) + { + prio_high_isr_counter++; + if(prio_high_isr_counter == 1) + { + /* USER CODE BEGIN LINKLAYER_PLAT_DisableSpecificIRQ_1*/ + + /* USER CODE END LINKLAYER_PLAT_DisableSpecificIRQ_1*/ + /* When specific counter for link layer high ISR value is 1, interrupt is disabled */ + HAL_NVIC_DisableIRQ(RADIO_INTR_NUM); + } + } + + if( (isr_type & LL_LOW_ISR_ONLY) != 0 ) + { + prio_low_isr_counter++; + if(prio_low_isr_counter == 1) + { + /* When specific counter for link layer SW low ISR value is 1, interrupt is disabled */ + HAL_NVIC_DisableIRQ(RADIO_SW_LOW_INTR_NUM); + } + } + + if( (isr_type & SYS_LOW_ISR) != 0 ) + { + prio_sys_isr_counter++; + if(prio_sys_isr_counter == 1) + { + /* Save basepri register value */ + local_basepri_value = __get_BASEPRI(); + + /* Mask all other interrupts with lower priority that link layer SW low ISR */ + __set_BASEPRI_MAX(RADIO_INTR_PRIO_LOW<<4); + } + } +} +#endif + +/** + * @brief Enable link layer high priority ISR only. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_EnableRadioIT(void) +{ + /* USER CODE BEGIN LINKLAYER_PLAT_EnableRadioIT_1*/ + + /* USER CODE END LINKLAYER_PLAT_EnableRadioIT_1*/ + + HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_INTR_NUM); + + /* USER CODE BEGIN LINKLAYER_PLAT_EnableRadioIT_2*/ + + /* USER CODE END LINKLAYER_PLAT_EnableRadioIT_2*/ +} + +/** + * @brief Disable link layer high priority ISR only. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_DisableRadioIT(void) +{ + /* USER CODE BEGIN LINKLAYER_PLAT_DisableRadioIT_1*/ + + /* USER CODE END LINKLAYER_PLAT_DisableRadioIT_1*/ + + HAL_NVIC_DisableIRQ((IRQn_Type) RADIO_INTR_NUM); + + /* USER CODE BEGIN LINKLAYER_PLAT_DisableRadioIT_2*/ + + /* USER CODE END LINKLAYER_PLAT_DisableRadioIT_2*/ +} + +#ifndef __ZEPHYR__ +/** + * @brief Link Layer notification for radio activity start. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_StartRadioEvt(void) +{ + __HAL_RCC_RADIO_CLK_SLEEP_ENABLE(); + NVIC_SetPriority(RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH); +#if (CFG_SCM_SUPPORTED == 1) + scm_notifyradiostate(SCM_RADIO_ACTIVE); +#endif /* CFG_SCM_SUPPORTED */ +} + +/** + * @brief Link Layer notification for radio activity end. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_StopRadioEvt(void) +{ + __HAL_RCC_RADIO_CLK_SLEEP_DISABLE(); + NVIC_SetPriority(RADIO_INTR_NUM, RADIO_INTR_PRIO_LOW); +#if (CFG_SCM_SUPPORTED == 1) + scm_notifyradiostate(SCM_RADIO_NOT_ACTIVE); +#endif /* CFG_SCM_SUPPORTED */ +} + +/** + * @brief Link Layer notification for RCO calibration start. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_RCOStartClbr(void) +{ +#if (CFG_SCM_SUPPORTED == 1) +#if (CFG_LPM_LEVEL != 0) +#if (CFG_LPM_STDBY_SUPPORTED == 1) + UTIL_LPM_SetOffMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_DISABLE); +#endif /* (CFG_LPM_STDBY_SUPPORTED == 1) */ + UTIL_LPM_SetStopMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_DISABLE); +#endif /* (CFG_LPM_LEVEL != 0) */ + scm_setsystemclock(SCM_USER_LL_HW_RCO_CLBR, HSE_32MHZ); + while (LL_PWR_IsActiveFlag_VOS() == 0); +#endif /* CFG_SCM_SUPPORTED */ +} + +/** + * @brief Link Layer notification for RCO calibration end. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_RCOStopClbr(void) +{ +#if (CFG_SCM_SUPPORTED == 1) +#if (CFG_LPM_LEVEL != 0) +#if (CFG_LPM_STDBY_SUPPORTED == 1) + UTIL_LPM_SetOffMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_ENABLE); +#endif /* (CFG_LPM_STDBY_SUPPORTED == 1) */ + UTIL_LPM_SetStopMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_ENABLE); +#endif /* (CFG_LPM_LEVEL != 0) */ + scm_setsystemclock(SCM_USER_LL_HW_RCO_CLBR, HSE_16MHZ); + while (LL_PWR_IsActiveFlag_VOS() == 0); +#endif /* CFG_SCM_SUPPORTED */ +} + +/** + * @brief Link Layer requests temperature. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_RequestTemperature(void) +{ +#if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) + ll_sys_bg_temperature_measurement(); +#endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */ +} + +/** + * @brief Enable RTOS context switch. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_EnableOSContextSwitch(void) +{ +} + +/** + * @brief Disable RTOS context switch. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_DisableOSContextSwitch(void) +{ +} + +/** + * @brief Notify the upper layer that new Link Layer timings have been applied. + * @param evnt_timing[in]: Evnt_timing_t pointer to structure contains drift time , execution time and scheduling time + * @retval None. + */ +void LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT(Evnt_timing_t * p_evnt_timing) +{ + /* USER CODE BEGIN LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT_0 */ + + /* USER CODE END LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT_0 */ +} + +/** + * @brief Get the ST company ID. + * @param None + * @retval Company ID + */ +uint32_t LINKLAYER_PLAT_GetSTCompanyID(void) +{ + return LL_FLASH_GetSTCompanyID(); +} + +/** + * @brief Get the Unique Device Number (UDN). + * @param None + * @retval UDN + */ +uint32_t LINKLAYER_PLAT_GetUDN(void) +{ + return LL_FLASH_GetUDN(); +} + +/* USER CODE BEGIN LINKLAYER_PLAT 0 */ + +/* Radio bus clock control variables */ +uint8_t AHB5_SwitchedOff = 0; +uint32_t radio_sleep_timer_val = 0; +#endif + +/** + * @brief Notify the Link Layer platform layer the system will enter in WFI + * and AHB5 clock may be turned of regarding the 2.4Ghz radio state. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_NotifyWFIEnter(void) +{ + /* Check if Radio state will allow the AHB5 clock to be cut */ + + /* AHB5 clock will be cut in the following cases: + * - 2.4GHz radio is not in ACTIVE mode (in SLEEP or DEEPSLEEP mode). + * - RADIOSMEN and STRADIOCLKON bits are at 0. + */ + if((LL_PWR_GetRadioMode() != LL_PWR_RADIO_ACTIVE_MODE) || + ((__HAL_RCC_RADIO_IS_CLK_SLEEP_ENABLED() == 0) && (LL_RCC_RADIO_IsEnabledSleepTimerClock() == 0))) + { + AHB5_SwitchedOff = 1; + } +} + +/** + * @brief Notify the Link Layer platform layer the system exited WFI and AHB5 + * clock may be resynchronized as is may have been turned of during + * low power mode entry. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_NotifyWFIExit(void) +{ + /* Check if AHB5 clock has been turned of and needs resynchronisation */ + if (AHB5_SwitchedOff) + { + /* Read sleep register as earlier as possible */ + radio_sleep_timer_val = ll_intf_cmn_get_slptmr_value(); + } +} + +/* USER CODE END LINKLAYER_PLAT 0 */ diff --git a/lib/stm32wba/hci/linklayer_plat.h b/lib/stm32wba/hci/linklayer_plat.h index 16b82ba3f..e0cf6f643 100644 --- a/lib/stm32wba/hci/linklayer_plat.h +++ b/lib/stm32wba/hci/linklayer_plat.h @@ -50,6 +50,24 @@ extern void LINKLAYER_PLAT_Assert(uint8_t condition); */ extern void LINKLAYER_PLAT_AclkCtrl(uint8_t enable); +/** + * @brief Notify the Link Layer platform layer the system will enter in WFI + * and AHB5 clock may be turned of regarding the 2.4Ghz radio state. + * @param None + * @retval None + */ +extern void LINKLAYER_PLAT_NotifyWFIEnter(void); + +/** + * @brief Notify the Link Layer platform layer the system exited WFI and AHB5 + * clock may be resynchronized as is may have been turned of during + * low power mode entry. + * @param None + * @retval None + */ +extern void LINKLAYER_PLAT_NotifyWFIExit(void); + + /** * @brief Active wait on bus clock readiness. * @param None @@ -194,4 +212,18 @@ extern void LINKLAYER_PLAT_DisableOSContextSwitch(void); */ extern void LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT(Evnt_timing_t * p_evnt_timing); -#endif /* LINKLAYER_PLAT_H */ +/** + * @brief Get the ST company ID. + * @param None + * @retval Company ID + */ +extern uint32_t LINKLAYER_PLAT_GetSTCompanyID(void); + +/** + * @brief Get the Unique Device Number (UDN). + * @param None + * @retval UDN + */ +extern uint32_t LINKLAYER_PLAT_GetUDN(void); + +#endif /* LINKLAYER_PLAT_H */ \ No newline at end of file diff --git a/lib/stm32wba/hci/ll/_40nm_reg_files/DWC_ble154combo.h b/lib/stm32wba/hci/ll/_40nm_reg_files/DWC_ble154combo.h index 46151833c..8fe39ebf8 100644 --- a/lib/stm32wba/hci/ll/_40nm_reg_files/DWC_ble154combo.h +++ b/lib/stm32wba/hci/ll/_40nm_reg_files/DWC_ble154combo.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.30a-SOW05Patchv6_2/firmware/public_inc/_40nm_reg_files/DWC_ble154combo.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-LCA00/firmware/public_inc/_40nm_reg_files/DWC_ble154combo.h#1 $*/ /** ******************************************************************************** * @brief diff --git a/lib/stm32wba/hci/ll/bsp.h b/lib/stm32wba/hci/ll/bsp.h index 2f0f0b587..1eef01f43 100644 --- a/lib/stm32wba/hci/ll/bsp.h +++ b/lib/stm32wba/hci/ll/bsp.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.30a-SOW05Patchv6_2/firmware/public_inc/bsp.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-LCA00/firmware/public_inc/bsp.h#1 $*/ /** ******************************************************************************** @@ -55,6 +55,9 @@ #define LL_LOW_ISR_ONLY 0x02 // Specify only LL LOW ISR to be enabled or disabled #define SYS_LOW_ISR 0x04 // Specify only system low ISR to be enabled or disabled +#ifndef EBQ_BUILD +#define EBQ_BUILD 0 +#endif /** * @brief InterruptPriorities Enum. * it is used to define the different ISR priorities in the controller @@ -267,6 +270,7 @@ typedef enum Debug_GPIO_e{ DBG_IO_CONN_MNGR_PROCESS_EVNT_CLBK , DBG_IO_CONN_MNGR_UPDT_CONN_PARAM_CBK , + DBG_IO_CONN_MNGR_DATA_LEN_UPDT_CBK , DBG_IO_EVNT_SCHDLR_HW_EVNT_CMPLT , DBG_IO_HCI_EVENT_HNDLR , @@ -281,9 +285,7 @@ typedef enum Debug_GPIO_e{ DBG_IO_PROFILE_MARKER_PHY_WAKEUP_TIME , DBG_IO_PROFILE_END_DRIFT_TIME , DBG_IO_PROC_RADIO_RCV , - DBG_IO_EVNT_TIME_UPDT , - DBG_IO_MAC_RECEIVE_DONE , DBG_IO_MAC_TX_DONE , DBG_IO_RADIO_APPLY_CSMA , @@ -612,6 +614,7 @@ void bsp_debug_gpio_toggle(Debug_GPIO_t gpio); * @retval None. */ void bsp_set_phy_clbr_state(PhyClbrState state); + /** * @brief a function to notify the upper layer to switch the clock. * diff --git a/lib/stm32wba/hci/ll/common_types.h b/lib/stm32wba/hci/ll/common_types.h index c04421fa6..e1489a7b8 100644 --- a/lib/stm32wba/hci/ll/common_types.h +++ b/lib/stm32wba/hci/ll/common_types.h @@ -1,8 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/branches/P10164613/issue_2029/firmware/public_inc/common_types.h#2 $*/ -/*Version_INFO -V2 --> Original version is 1.30a-SOW05PatchV6_2 -V2 --> combined patch case 01641860 -*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-LCA00/firmware/public_inc/common_types.h#1 $*/ /** ******************************************************************************** * @file common_types.h @@ -141,6 +137,9 @@ V2 --> combined patch case 01641860 #define NULL ((void *)0) #endif /* NULL */ +#define UNUSED_VALUE 0 +#define UNUSED_PTR NULL + #define MEMSET(ptr_memory, value, memory_size) ble_memset(ptr_memory, value, memory_size) #define MEMCPY(ptr_destination, ptr_source, memory_size) ble_memcpy(ptr_destination, ptr_source, memory_size) #define MEMCMP(ptr_destination, ptr_source, memory_size) ble_memcmp(ptr_destination, ptr_source, memory_size) @@ -177,6 +176,9 @@ extern os_mutex_id g_ll_lock; /* end of radio activity custom command flag */ #define END_OF_RADIO_ACTIVITY_REPORTING 1 /* Enable\Disable end of radio activity reporting feature. Enable:1 - Disable:0 */ +#if SUPPORT_MAC && SUPPORT_ANT_DIV +#define EXT_ADDRESS_LENGTH 8 +#endif /* SUPPORT_MAC && SUPPORT_ANT_DIV */ /* Supported PHYs*/ typedef enum { LE_NO_CHANGE = 0x00, @@ -286,7 +288,27 @@ typedef enum _slptmr_src_type_e { #endif /* USE_NON_ACCURATE_32K_SLEEP_CLK */ }slptmr_src_type_e; +/** + * @brief Enumeration of the antenna diversity interval type. + */ +#if SUPPORT_MAC && SUPPORT_ANT_DIV +typedef enum ant_intrv_type_enum { + NO_TYPE, + FIXED_TIME, + PACKETS_NUMBER +} ant_intrv_type_enum_t; +/* + * @brief structure that hold antenna diversity parameters information. + */ +typedef struct _antenna_diversity_st{ + ant_intrv_type_enum_t ant_intrv_type; /* antenna interval type: FIXED_TIME(us) or PACKETS_NUMBER(n) */ + uint32_t ant_intrv_value; /* antenna interval value based on type; us for FIXED_TIME, n for PACKETS_NUMBER */ + uint16_t wntd_coord_shrt_addr; /* wanted coordinator/router short address */ + uint8_t wntd_coord_ext_addr[EXT_ADDRESS_LENGTH]; /* wanted coordinator/router extended address */ + uint8_t max_rx_ack_retries; /* max number of retries to receive ack in case of ack error reception*/ +} antenna_diversity_st; +#endif /* SUPPORT_MAC && SUPPORT_ANT_DIV */ /* * @brief structure that hold some information about the data transmitted across layers. @@ -341,14 +363,6 @@ typedef struct _sdu_buf_hdr_st { } iso_sdu_buf_hdr_st, *iso_sdu_buf_hdr_p; #endif /* (SUPPORT_BRD_ISOCHRONOUS || SUPPORT_SYNC_ISOCHRONOUSs || (SUPPORT_CONNECTED_ISOCHRONOUS && ( SUPPORT_MASTER_CONNECTION || SUPPORT_SLAVE_CONNECTION))) */ -/** - * brief: PAWR host buffer struct - */ -typedef struct _pawr_host_buffer { - uint8_t buffer[257]; - uint8_t total_data_lenth; - uint8_t number_of_reports; -}pawr_host_buffer; /* * @brief Transport layer event @@ -412,6 +426,11 @@ typedef enum { */ #define DEFAULT_PHY_CALIBRATION_PERIOD 10 /* Time period for PHY calibration = 10s */ +#ifdef PHY_40nm_3_00_a +#define SUPPORT_MAC_PHY_CONT_TESTING_CMDS 1 +#else +#define SUPPORT_MAC_PHY_CONT_TESTING_CMDS 0 +#endif /*end of PHY_40nm_3_00_a && SUPPORT_MAC_PHY_CONT_TESTING_CMDS */ #ifndef EXTERNAL_CUSTOM_CMDS #define EXTERNAL_CUSTOM_CMDS 0 /* Indicates that an external custom HCI commands module exists */ @@ -425,9 +444,11 @@ typedef enum { -Allow host to register callback to refuse current controller event and receive it later with another callback*/ #define SUPPORT_HCI_EVENT_ONLY 1 +#else +#define SUPPORT_HCI_EVENT_ONLY 0 #endif/* (!USE_HCI_TRANSPORT) && (SUPPORT_BLE) */ #define SUPPORT_HW_AUDIO_SYNC_SIGNAL 0 - +#define SUPPORT_TIM_UPDT 1 #endif /*COMMON_TYPES_H_*/ diff --git a/lib/stm32wba/hci/ll/event_manager.h b/lib/stm32wba/hci/ll/event_manager.h index accd970d9..35cc2bdae 100644 --- a/lib/stm32wba/hci/ll/event_manager.h +++ b/lib/stm32wba/hci/ll/event_manager.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.30a-SOW05Patchv6_2/firmware/public_inc/event_manager.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-LCA00/firmware/public_inc/event_manager.h#1 $*/ /** ******************************************************************************** * @file event_manager.h @@ -72,6 +72,9 @@ typedef enum { #if ((SUPPORT_MASTER_CONNECTION) || (SUPPORT_SLAVE_CONNECTION)) CONN_EVENT, /*connection event handler ID*/ CONN_PARAM_UPDATE_EVENT, /* handler for connection parameter update initiated by link layer */ +#if ((SUPPORT_CONNECTED_ISOCHRONOUS) && (SUPPORT_MASTER_CONNECTION)) + CONN_DATA_LEN_UPDATE_EVENT, /* handler for connection data length update initiated by link layer */ +#endif /*SUPPORT_CONNECTED_ISOCHRONOUS && SUPPORT_MASTER_CONNECTION*/ #if(SUPPORT_CONNECTED_ISOCHRONOUS &&( SUPPORT_MASTER_CONNECTION || SUPPORT_SLAVE_CONNECTION)) CIS_EVENT, #endif /*SUPPORT_CONNECTED_ISOCHRONOUS*/ @@ -101,6 +104,7 @@ typedef enum { COEX_TIMER_EVENT, #endif #if SUPPORT_MAC + RADIO_MAC_TX_DONE_EVENT, RAL_SM_DONE_EVENT, MAC_SM_DONE_EVENT, ED_TMR_EVENT, @@ -153,7 +157,6 @@ typedef enum { #if (NUM_OF_CTSM_EMNGR_HNDLS >= 3) CUSTOM_HANDLE_3, #endif - MAX_EM_HANDLE } handler_t; /* Exported functions ------------------------------------------------------- */ diff --git a/lib/stm32wba/hci/ll/evnt_schdlr_gnrc_if.h b/lib/stm32wba/hci/ll/evnt_schdlr_gnrc_if.h index a728c94df..ae5d7e9c2 100644 --- a/lib/stm32wba/hci/ll/evnt_schdlr_gnrc_if.h +++ b/lib/stm32wba/hci/ll/evnt_schdlr_gnrc_if.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.30a-SOW05Patchv6_2/firmware/public_inc/evnt_schdlr_gnrc_if.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-LCA00/firmware/public_inc/evnt_schdlr_gnrc_if.h#1 $*/ /** ******************************************************************************** * @file evnt_schdlr_gnrc_if.h diff --git a/lib/stm32wba/hci/ll/hci.h b/lib/stm32wba/hci/ll/hci.h index 08d945f57..302121f0c 100644 --- a/lib/stm32wba/hci/ll/hci.h +++ b/lib/stm32wba/hci/ll/hci.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.30a-SOW05Patchv6_2/firmware/public_inc/hci.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-LCA00/firmware/public_inc/hci.h#1 $*/ /** ******************************************************************************** * @file hci.h diff --git a/lib/stm32wba/hci/ll/ll_fw_config.h b/lib/stm32wba/hci/ll/ll_fw_config.h index 621dd1f22..a0a7ce06e 100644 --- a/lib/stm32wba/hci/ll/ll_fw_config.h +++ b/lib/stm32wba/hci/ll/ll_fw_config.h @@ -16,7 +16,7 @@ * THE ENTIRE NOTICE ABOVE MUST BE REPRODUCED ON ALL AUTHORIZED COPIES. * *

© (C) COPYRIGHT 2022 SYNOPSYS, INC.

- *

© ALL RIGHTS RESERVED

+ *

© ALL RIGHTS RESERVED

* * \n\nReferences\n * -Documents folder . @@ -41,61 +41,56 @@ /*************************** BLE Configuration *************************************/ /*Configurations of BLE will apply only when BLE is enabled*/ /* Roles configurations */ -#define SUPPORT_EXPLCT_OBSERVER_ROLE 1 /* Enable\Disable Explicit observer role. Enable:1 - Disable:0 */ -#define SUPPORT_EXPLCT_BROADCASTER_ROLE 1 /* Enable\Disable Explicit broadcaster role. Enable:1 - Disable:0 */ -#define SUPPORT_MASTER_CONNECTION 1 /* Enable\Disable Master connection role. Enable:1 - Disable:0 */ -#define SUPPORT_SLAVE_CONNECTION 1 /* Enable\Disable Slave connection role. Enable:1 - Disable:0 */ +#define SUPPORT_EXPLCT_OBSERVER_ROLE 1 /* Enable\Disable Explicit observer role. Enable:1 - Disable:0 */ +#define SUPPORT_EXPLCT_BROADCASTER_ROLE 1 /* Enable\Disable Explicit broadcaster role. Enable:1 - Disable:0 */ +#define SUPPORT_MASTER_CONNECTION 1 /* Enable\Disable Master connection role. Enable:1 - Disable:0 */ +#define SUPPORT_SLAVE_CONNECTION 1 /* Enable\Disable Slave connection role. Enable:1 - Disable:0 */ /* Standard features configurations */ -#define SUPPORT_LE_ENCRYPTION 1 /* Enable\Disable Encryption feature. Enable:1 - Disable:0 */ -#define SUPPORT_PRIVACY 1 /* Enable\Disable Privacy feature. Enable:1 - Disable:0 */ +#define SUPPORT_LE_ENCRYPTION 1 /* Enable\Disable Encryption feature. Enable:1 - Disable:0 */ +#define SUPPORT_PRIVACY 1 /* Enable\Disable Privacy feature. Enable:1 - Disable:0 */ /* Capabilities configurations */ -#define MAX_NUM_CNCRT_STAT_MCHNS 8 /* Set maximum number of states the controller can support */ -#define USE_NON_ACCURATE_32K_SLEEP_CLK 1 /* Allow to drive the sleep clock by sources other than the default crystal oscillator source.*/ - /*LL can use crystal oscillator or RTC or RCO to drive the sleep clock.This selection is done via "DEFAULT_SLEEP_CLOCK_SOURCE" macro. */ -#define SUPPORT_LE_EXTENDED_ADVERTISING 1 /* Enable\Disable Extended advertising feature. Enable:1 - Disable:0 */ -#define SUPPORT_LE_PERIODIC_ADVERTISING 1 /* Enable\Disable Periodic advertising feature. Enable:1 - Disable:0 */ -#define SUPPORT_LE_POWER_CLASS_1 1 /* Enable\Disable Low power class 1 feature. Enable:1 - Disable:0 */ -#define SUPPORT_AOA_AOD 1 /* Enable\Disable AOA_AOD feature. Enable:1 - Disable:0 */ -#define SUPPORT_PERIODIC_SYNC_TRANSFER 1 /* Enable\Disable PAST feature. Enable:1 - Disable:0 */ +#define MAX_NUM_CNCRT_STAT_MCHNS 8 /* Set maximum number of states the controller can support */ +#define USE_NON_ACCURATE_32K_SLEEP_CLK 1 /* Allow to drive the sleep clock by sources other than the default crystal oscillator source.*/ + /*LL can use crystal oscillator or RTC or RCO to drive the sleep clock.This selection is done via "DEFAULT_SLEEP_CLOCK_SOURCE" macro. */ +#define SUPPORT_LE_EXTENDED_ADVERTISING 1 /* Enable\Disable Extended advertising feature. Enable:1 - Disable:0 */ +#define SUPPORT_LE_PERIODIC_ADVERTISING 1 /* Enable\Disable Periodic advertising feature. Enable:1 - Disable:0 */ +#define SUPPORT_LE_POWER_CLASS_1 1 /* Enable\Disable Low power class 1 feature. Enable:1 - Disable:0 */ +#define SUPPORT_AOA_AOD 1 /* Enable\Disable AOA_AOD feature. Enable:1 - Disable:0 */ +#define SUPPORT_PERIODIC_SYNC_TRANSFER 1 /* Enable\Disable PAST feature. Enable:1 - Disable:0 */ #define SUPPORT_SLEEP_CLOCK_ACCURCY_UPDATES 1 /* Enable\Disable Sleep Clock Accuracy Updates Feature. Enable:1 - Disable:0 */ #define SUPPORT_CONNECTED_ISOCHRONOUS 1 /* Enable\Disable Connected Isochronous Channel Feature. Enable:1 - Disable:0 */ -#define SUPPORT_BRD_ISOCHRONOUS 1 /* Enable\Disable Broadcast Isochronous Channel Feature. Enable:1 - Disable:0 */ -#define SUPPORT_SYNC_ISOCHRONOUS 1 /* Enable\Disable Broadcast Isochronous Synchronizer Channel Feature. Enable:1 - Disable:0 */ -#define SUPPORT_LE_POWER_CONTROL 1 /* Enable\Disable LE Power Control Feature. Enable:1 - Disable:0 */ +#define SUPPORT_BRD_ISOCHRONOUS 1 /* Enable\Disable Broadcast Isochronous Channel Feature. Enable:1 - Disable:0 */ +#define SUPPORT_SYNC_ISOCHRONOUS 1 /* Enable\Disable Broadcast Isochronous Synchronizer Channel Feature. Enable:1 - Disable:0 */ +#define SUPPORT_LE_POWER_CONTROL 1 /* Enable\Disable LE Power Control Feature. Enable:1 - Disable:0 */ /* 5.3 features */ -#define SUPPORT_PERIODIC_ADV_ADI 1 -#define SUPPORT_CHANNEL_CLASSIFICATION 1 -#define SUPPORT_LE_ENHANCED_CONN_UPDATE 1 - -/* Capabilities configurations */ -#define MAX_NUM_CNCRT_STAT_MCHNS 8 /* Set maximum number of states the controller can support */ -#define USE_NON_ACCURATE_32K_SLEEP_CLK 1 /* Allow to drive the sleep clock by sources other than the default crystal oscillator source.*/ - /*LL can use crystal oscillator or RTC or RCO to drive the sleep clock.This selection is done via "DEFAULT_SLEEP_CLOCK_SOURCE" macro. */ +#define SUPPORT_PERIODIC_ADV_ADI 1 +#define SUPPORT_CHANNEL_CLASSIFICATION 1 +#define SUPPORT_LE_ENHANCED_CONN_UPDATE 1 /* Non-standard features configurations */ -#define NUM_OF_CTSM_EMNGR_HNDLS 1 /* Number of custom handles in event manager to be used for app specific needs */ -#define SUPPORT_AUGMENTED_BLE_MODE 1 /* Enable\Disable Augmented BLE Support. Enable:1 - Disable:0 */ -#define SUPPORT_PTA 1 /* Enable\Disable PTA Feature. Enable:1 - Disable:0 */ +#define NUM_OF_CTSM_EMNGR_HNDLS 1 /* Number of custom handles in event manager to be used for app specific needs */ +#define SUPPORT_AUGMENTED_BLE_MODE 1 /* Enable\Disable Augmented BLE Support. Enable:1 - Disable:0 */ +#define SUPPORT_PTA 1 /* Enable\Disable PTA Feature. Enable:1 - Disable:0 */ -#define SUPPORT_AUTONOMOUS_POWER_CONTROL_REQ (1) +#define SUPPORT_AUTONOMOUS_POWER_CONTROL_REQ 1 #define LL_BASIC 0 /*************************** MAC Configuration *************************************/ /*Configurations of MAC will apply only when MAC is enabled*/ -#define FFD_DEVICE_CONFIG 0 /* Enable\Disable FFD:1 - RFD:0 */ +#define FFD_DEVICE_CONFIG 0 /* Enable\Disable FFD:1 - RFD:0 */ #ifdef SUPPORT_AUG_MAC_HCI_UART -#define RAL_NUMBER_OF_INSTANCE 0 /* The Number of RAL instances supported */ +#define RAL_NUMBER_OF_INSTANCE 0 /* The Number of RAL instances supported */ #else -#define RAL_NUMBER_OF_INSTANCE 0 /* The Number of RAL instances supported */ +#define RAL_NUMBER_OF_INSTANCE 0 /* The Number of RAL instances supported */ #endif -#define MAX_NUMBER_OF_INDIRECT_DATA 0 /* The maximum number of supported indirect data buffers */ -#define SUPPORT_OPENTHREAD_1_2 0 /* Enable / disable FW parts related to new features introduced in openthread 1.2*/ -#define SUPPORT_SEC 0 /* The MAC Security Supported : 1 - Not Supported:0 */ -#define RADIO_CSMA 0 /* Enable\Disable CSMA Algorithm in Radio Layer, Must be Enabled if MAC_LAYER_BUILD */ -#define SUPPORT_A_MAC 0 -#define SMPL_PRTCL_TEST_ENABLE 0 +#define MAX_NUMBER_OF_INDIRECT_DATA 0 /* The maximum number of supported indirect data buffers */ +#define SUPPORT_OPENTHREAD_1_2 0 /* Enable / disable FW parts related to new features introduced in openthread 1.2*/ +#define SUPPORT_SEC 0 /* The MAC Security Supported : 1 - Not Supported:0 */ +#define RADIO_CSMA 0 /* Enable\Disable CSMA Algorithm in Radio Layer, Must be Enabled if MAC_LAYER_BUILD */ +#define SUPPORT_A_MAC 0 +#define SMPL_PRTCL_TEST_ENABLE 0 #endif /* INCLUDE_LL_FW_CONFIG_H */ diff --git a/lib/stm32wba/hci/ll/ll_intf.h b/lib/stm32wba/hci/ll/ll_intf.h index ef6f324cf..86c36c07f 100644 --- a/lib/stm32wba/hci/ll/ll_intf.h +++ b/lib/stm32wba/hci/ll/ll_intf.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.30a-SOW05Patchv6_2/firmware/public_inc/ll_intf.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-LCA00/firmware/public_inc/ll_intf.h#1 $*/ /** ******************************************************************************** * @file ll_intf_cmds.h @@ -4438,7 +4438,7 @@ ble_stat_t ll_intf_get_num_of_antennas(uint8_t *ptr_num_of_antennas); * @retval status : [out] 0:SUCCESS, 0xXX:ERROR_CODE. */ ble_stat_t ll_intf_set_dtm_with_spcfc_pckt_count(uint16_t pckt_count); - +#if SUPPORT_TIM_UPDT /** * @brief used to update the event timing. * @@ -4447,6 +4447,7 @@ ble_stat_t ll_intf_set_dtm_with_spcfc_pckt_count(uint16_t pckt_count); * @retval None */ void ll_intf_config_schdling_time(Evnt_timing_t * p_evnt_timing); +#endif /* SUPPORT_TIM_UPDT */ /**@} */ diff --git a/lib/stm32wba/hci/ll/mem_intf.h b/lib/stm32wba/hci/ll/mem_intf.h index 1f3e07b62..ddf9b5c9e 100644 --- a/lib/stm32wba/hci/ll/mem_intf.h +++ b/lib/stm32wba/hci/ll/mem_intf.h @@ -1,8 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/branches/P10164613/issue_2029/firmware/public_inc/mem_intf.h#2 $*/ -/*Version_INFO -V2 --> Original version is 1.30a-SOW05PatchV6_2 -V2 --> combined patch case 01641860 -*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-LCA00/firmware/public_inc/mem_intf.h#1 $*/ /** ******************************************************************************** * @file mem_intf.h diff --git a/lib/stm32wba/hci/ll/os_wrapper.h b/lib/stm32wba/hci/ll/os_wrapper.h index 3606a3990..89fe0ae01 100644 --- a/lib/stm32wba/hci/ll/os_wrapper.h +++ b/lib/stm32wba/hci/ll/os_wrapper.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.30a-SOW05Patchv6_2/firmware/public_inc/os_wrapper.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-LCA00/firmware/public_inc/os_wrapper.h#1 $*/ /** ******************************************************************************** * @file os_wrapper.h diff --git a/lib/stm32wba/hci/ll/power_table.h b/lib/stm32wba/hci/ll/power_table.h index b9ca599d4..e032f7fb4 100644 --- a/lib/stm32wba/hci/ll/power_table.h +++ b/lib/stm32wba/hci/ll/power_table.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.30a-SOW05Patchv6_2/firmware/public_inc/power_table.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-LCA00/firmware/public_inc/power_table.h#1 $*/ /** ****************************************************************************** * @file power_table.h diff --git a/lib/stm32wba/hci/ll_intf_cmn.h b/lib/stm32wba/hci/ll_intf_cmn.h new file mode 100644 index 000000000..540dce6d3 --- /dev/null +++ b/lib/stm32wba/hci/ll_intf_cmn.h @@ -0,0 +1,169 @@ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-LCA00/firmware/public_inc/ll_intf_cmn.h#1 $*/ +/** + ******************************************************************************** + * @file ll_intf_cmn.h + * @brief This file includes declaration of common interfaces of MAC only and BLE/COEXISTENCE APIs. + ****************************************************************************** + * @copy + * This Synopsys DWC Bluetooth Low Energy Combo Link Layer/MAC software and + * associated documentation ( hereinafter the "Software") is an unsupported + * proprietary work of Synopsys, Inc. unless otherwise expressly agreed to in + * writing between Synopsys and you. The Software IS NOT an item of Licensed + * Software or a Licensed Product under any End User Software License Agreement + * or Agreement for Licensed Products with Synopsys or any supplement thereto. + * Synopsys is a registered trademark of Synopsys, Inc. Other names included in + * the SOFTWARE may be the trademarks of their respective owners. + * + * Synopsys MIT License: + * Copyright (c) 2020-Present Synopsys, Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * the Software), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT, OR OTHERWISE ARISING FROM, + * OUT OF, OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * */ + +#ifndef INCLUDE_LL_INTF_CMN_H_ +#define INCLUDE_LL_INTF_CMN_H_ + +#include "common_types.h" + + +/*========================================================================================================*/ +/*================================ Configure LL Context Control Command =================================*/ +/*========================================================================================================*/ + +/** + * @brief Used to configure the LL contexts, where: + * 1. For bare-metal: + * - High ISR is executed in the ISR context + * - Low ISR can be executed in the high ISR context, or switched to low ISR context + * 2. For RTOS: + * - High ISR is executed in the ISR context + * - Low ISR is executed in the thread of the "linkLayerHighPrioTask" + * + * @param allow_low_isr : [in] Configuration parameter for the context of the low ISR in the bare-metal model. Range is [0,1]. + * 0: Low ISR code is executed in the same context of the high ISR. + * 1: Low ISR code is executed in the context of the low ISR (by configuring a low priority interrupt that is triggered by FW). + * @param run_post_evnt_frm_isr : [in] Configuration parameter to decide whether the scheduling of the next BLE event is done in the low ISR context or to be handled by the LL main thread. Range is [0,1]. + * 0: BLE next event scheduling is handled in the LL main thread. + * 1: BLE next event scheduling is handled in the low ISR context. + * + * @retval ble_state_t : Command status + */ +ble_stat_t ll_intf_cmn_config_ll_ctx_params(uint8_t allow_low_isr, uint8_t run_post_evnt_frm_isr); + + +/*========================================================================================================*/ +/*================================== LE Select Sleep Clock Source =======================================*/ +/*========================================================================================================*/ + +#if (USE_NON_ACCURATE_32K_SLEEP_CLK) +/** + * @brief Used to select the source that drives the sleep clock, whether to use an external crystal oscillator or an integrated RC oscillator (RCO). + * + * @param slp_clk_src : [in] Indicate which source to drive the sleep clock. 0: Crystal Oscillator (default). 1: RC0 + * @param ptr_slp_clk_freq_value : [out] Indicate the nominal frequency value of the sleep clock. + * + * @retval ble_stat_t : Command status to be sent to the Host. + */ +ble_stat_t ll_intf_cmn_le_select_slp_clk_src(uint8_t slp_clk_src, uint16_t *ptr_slp_clk_freq_value); + +/*========================================================================================================*/ +/*=============================== LE Set RCO Calibration Event Parameters ===============================*/ +/*========================================================================================================*/ + +/** + * @brief Used to configure the runtime RCO calibration event parameters. + * + * @param rco_clbr_event_duration : [in] Indicate the number of sleep clock cycles for performing the RCO calibration process. + * @param rco_clbr_event_interval : [in] Indicate the periodicity of running the runtime RCO calibration event. + * + * @retval None. + */ + +ble_stat_t ll_intf_cmn_le_set_rco_clbr_evnt_params(uint8_t rco_clbr_event_duration, uint32_t rco_clbr_event_interval); + +#endif + +/*========================================================================================================*/ +/*====================================== LE Select TX_Power Table =======================================*/ +/*========================================================================================================*/ + +/** + * @brief Used to specify the used power table and its size based on the selected TX_Power table ID. + * + * @param tx_power_table_id : [in] Selected TX_Power table ID. + * + * @retval Status : 0: SUCCESS. Otherwise: Error code. + */ +uint8_t ll_intf_cmn_select_tx_power_table(uint8_t tx_power_table_id); + + +/** + * @brief flag to the LL the existence of a temperature sensor + * @retval None + */ +void ll_intf_cmn_set_temperature_sensor_state(void); + +/** + * @brief set the current temperature + * @param temperature : The current temperature + * @retval None + */ +uint32_t ll_intf_cmn_set_temperature_value(uint32_t temperature); + +/*========================================================================================================*/ +/*==================================== Random Number Generation Group ===================================*/ +/*========================================================================================================*/ + + /** + * @brief Request new random number. + * + * @param ptr_rnd : Pointer to the output random bytes . + * @param len : Number of required random bytes. + * + * @retval Status. + */ + +uint32_t ll_intf_cmn_gen_rnd_num(uint8_t *ptr_rnd, uint32_t len); + +/** + * + * @brief A common wrapper for BLE-ECB and MAC-CCM security modes + * + * @param ptr_pckt : Pointer to the data buffer (variable length + * in case of CCM mode, 16 bytes in case of ECB mode). The resulting + * Encrypted/Decrypted data overwrites this buffer. + * @param ptr_key[in] : Pointer to the security key buffer (16 bytes). + * @param ptr_nonce[in] : Pointer to the security nonce buffer (13 bytes + * in case of CCM mode, a Null pointer in case of ECB mode). + * @param mic_len[in] : Length of MIC, supported values are 0, 4, 6, + * 8, 10, 12, 14, and 16 in case of CCM, 0 only in case of ECB. + * @param ad_len[in] : Length of Data to be authenticated. + * @param md_len[in] : Length of Data to be encrypted. + * @param key_endian[in] : Represents the format of the security key. + * @param data_endian[in] : Represents the endian format of the data. + * @param security_mode[in]: Hardware security mode. + * @retval Status + */ +uint32_t ll_intf_cmn_crypto(uint8_t *ptr_pckt, const uint8_t *ptr_key, + uint8_t *ptr_nonce, uint32_t mic_len, uint32_t ad_len, uint32_t md_len, + crypto_endian_enum_t key_endian, crypto_endian_enum_t data_endian, + security_mode_enum_t security_mode); + +ble_stat_t ll_intf_cmn_le_set_dp_slp_mode(uint8_t dp_slp_mode); + +#endif /* INCLUDE_LL_INTF_CMN_H_ */ diff --git a/lib/stm32wba/hci/ll_sys.h b/lib/stm32wba/hci/ll_sys.h index 8a489cd1c..4418212b8 100644 --- a/lib/stm32wba/hci/ll_sys.h +++ b/lib/stm32wba/hci/ll_sys.h @@ -60,6 +60,7 @@ typedef enum /* Link Layer system interface general module functions ************************************************/ void ll_sys_init(void); +void ll_sys_reset(void); void ll_sys_delay_us(uint32_t delay); void ll_sys_assert(uint8_t condition); void ll_sys_get_rng(uint8_t *ptr_rnd, uint32_t len); @@ -105,4 +106,19 @@ void ll_sys_dp_slp_wakeup_evt_clbk(void const *ptr_arg); */ uint8_t ll_sys_get_concurrent_state_machines_num(void); -#endif /* LL_SYS_H */ +#if BLE +/** + * @brief Updating Link Layer BLE timings + * @param drift_time[in]: number of Link Layer sleep timer cycles (1 cycle = 31us) for the DRIFT TIME timing. + * @param exec_time[in]: number of Link Layer sleep timer cycles (1 cycle = 31us) for the EXEC TIME timing. + * @note This interface needs to be called after system initialization + * and before starting any radio activity. + * @retval None + */ +void ll_sys_config_BLE_schldr_timings(uint8_t drift_time, uint8_t exec_time); +#endif /* BLE */ + +uint32_t ll_intf_cmn_get_slptmr_value(void); + + +#endif /* LL_SYS_H */ \ No newline at end of file diff --git a/lib/stm32wba/hci/ll_sys_cs.c b/lib/stm32wba/hci/ll_sys_cs.c index aab59dfb5..93f424d95 100644 --- a/lib/stm32wba/hci/ll_sys_cs.c +++ b/lib/stm32wba/hci/ll_sys_cs.c @@ -67,4 +67,4 @@ void ll_sys_enable_os_context_switch(void) void ll_sys_disable_os_context_switch(void) { LINKLAYER_PLAT_DisableOSContextSwitch(); -} +} \ No newline at end of file diff --git a/lib/stm32wba/hci/ll_sys_dp_slp.c b/lib/stm32wba/hci/ll_sys_dp_slp.c index 396316da7..891d40755 100644 --- a/lib/stm32wba/hci/ll_sys_dp_slp.c +++ b/lib/stm32wba/hci/ll_sys_dp_slp.c @@ -18,10 +18,7 @@ #include "linklayer_plat.h" #include "ll_sys.h" -#include "ll_intf.h" -#if defined(MAC) -#include "platform.h" -#endif +#include "ll_intf_cmn.h" /* Link Layer deep sleep status */ uint8_t is_Radio_DeepSleep = 0U; @@ -44,6 +41,9 @@ ll_sys_status_t ll_sys_dp_slp_init(void) /* Create link layer timer for handling IP DEEP SLEEP mode */ radio_dp_slp_tmr_id = os_timer_create((t_timer_callbk)ll_sys_dp_slp_wakeup_evt_clbk, os_timer_once, NULL); + /* Set priority of deep sleep timer */ + os_timer_set_prio(radio_dp_slp_tmr_id, hg_prio_tmr); + if (radio_dp_slp_tmr_id != NULL) { return_status = LL_SYS_OK; @@ -68,7 +68,7 @@ ll_sys_dp_slp_state_t ll_sys_dp_slp_get_state(void) * @retval LL_SYS status */ ll_sys_status_t ll_sys_dp_slp_enter(uint32_t dp_slp_duration){ - ble_stat_t cmd_status = GENERAL_FAILURE; + ble_stat_t cmd_status; int32_t os_status = GENERAL_FAILURE; ll_sys_status_t return_status = LL_SYS_ERROR; @@ -88,17 +88,7 @@ ll_sys_status_t ll_sys_dp_slp_enter(uint32_t dp_slp_duration){ if(os_status == SUCCESS) { /* Switch Link Layer IP to DEEP SLEEP mode */ -#if defined(BLE) - /* BLE & Concurrent use case */ - cmd_status = ll_intf_le_set_dp_slp_mode(DEEP_SLEEP_ENABLE); -#elif defined(MAC) - if (radio_set_dp_slp_mode(DEEP_SLEEP_ENABLE) == OT_ERROR_NONE) - { - cmd_status = SUCCESS; - } -#else - #error "neither MAC not BLE defined" -#endif + cmd_status = ll_intf_cmn_le_set_dp_slp_mode(DEEP_SLEEP_ENABLE); if(cmd_status == SUCCESS){ linklayer_dp_slp_state = LL_SYS_DP_SLP_ENABLED; return_status = LL_SYS_OK; @@ -114,7 +104,7 @@ ll_sys_status_t ll_sys_dp_slp_enter(uint32_t dp_slp_duration){ * @retval LL_SYS status */ ll_sys_status_t ll_sys_dp_slp_exit(void){ - ble_stat_t cmd_status = GENERAL_FAILURE; + ble_stat_t cmd_status; ll_sys_status_t return_status = LL_SYS_ERROR; /* Disable radio interrupt */ @@ -134,17 +124,7 @@ ll_sys_status_t ll_sys_dp_slp_exit(void){ } /* Switch Link Layer IP to SLEEP mode (by deactivate DEEP SLEEP mode) */ -#if defined(BLE) - /* BLE & Concurrent use case */ - cmd_status = ll_intf_le_set_dp_slp_mode(DEEP_SLEEP_DISABLE); -#elif defined(MAC) - if (radio_set_dp_slp_mode(DEEP_SLEEP_DISABLE) == OT_ERROR_NONE) - { - cmd_status = SUCCESS; - } -#else - #error "neither MAC not BLE defined" -#endif + cmd_status = ll_intf_cmn_le_set_dp_slp_mode(DEEP_SLEEP_DISABLE); if(cmd_status == SUCCESS) { linklayer_dp_slp_state = LL_SYS_DP_SLP_DISABLED; @@ -164,7 +144,7 @@ ll_sys_status_t ll_sys_dp_slp_exit(void){ * @retval LL_SYS status */ void ll_sys_dp_slp_wakeup_evt_clbk(void const *ptr_arg){ - int32_t os_status = GENERAL_FAILURE; + int32_t os_status; /* Stop the Link Layer IP DEEP SLEEP wake-up timer */ os_status = os_timer_stop(radio_dp_slp_tmr_id); diff --git a/lib/stm32wba/hci/ll_sys_if.c b/lib/stm32wba/hci/ll_sys_if.c new file mode 100644 index 000000000..317cd0a20 --- /dev/null +++ b/lib/stm32wba/hci/ll_sys_if.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2023 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include "ll_intf.h" +#include "ll_intf_cmn.h" +#include "utilities_common.h" + +static void ll_sys_sleep_clock_source_selection(void); + +void ll_sys_reset(void); + +#ifndef __ZEPHYR__ +void ll_sys_bg_process_init(void) +{ + /* Register Link Layer task */ + UTIL_SEQ_RegTask(1U << CFG_TASK_LINK_LAYER, UTIL_SEQ_RFU, ll_sys_bg_process); +} + +void ll_sys_schedule_bg_process(void) +{ + UTIL_SEQ_SetTask(1U << CFG_TASK_LINK_LAYER, TASK_PRIO_LINK_LAYER); +} + +void ll_sys_schedule_bg_process_isr(void) +{ + UTIL_SEQ_SetTask(1U << CFG_TASK_LINK_LAYER, TASK_PRIO_LINK_LAYER); +} +#endif + +void ll_sys_config_params(void) +{ + ll_intf_config_ll_ctx_params(USE_RADIO_LOW_ISR, NEXT_EVENT_SCHEDULING_FROM_ISR); +} + +#ifndef __ZEPHYR__ +#if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) +void ll_sys_bg_temperature_measurement_init(void) +{ + /* Register Temperature Measurement task */ + UTIL_SEQ_RegTask(1U << CFG_TASK_TEMP_MEAS, UTIL_SEQ_RFU, TEMPMEAS_RequestTemperatureMeasurement); +} + +void ll_sys_bg_temperature_measurement(void) +{ + static uint8_t initial_temperature_acquisition = 0; + + if (initial_temperature_acquisition == 0) { + TEMPMEAS_RequestTemperatureMeasurement(); + initial_temperature_acquisition = 1; + } else { + UTIL_SEQ_SetTask(1U << CFG_TASK_TEMP_MEAS, CFG_SEQ_PRIO_0); + } +} +#endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */ +#endif + +#if (CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE == 0) +uint8_t ll_sys_BLE_sleep_clock_accuracy_selection(void) +{ + uint8_t BLE_sleep_clock_accuracy = 0; + uint32_t RevID = LL_DBGMCU_GetRevisionID(); + uint32_t linklayer_slp_clk_src = LL_RCC_RADIO_GetSleepTimerClockSource(); + + if (linklayer_slp_clk_src == LL_RCC_RADIOSLEEPSOURCE_LSE) { + /* LSE selected as Link Layer sleep clock source. */ + /* Sleep clock accuracy is different regarding the WBA device ID and revision */ +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) + if (RevID == REV_ID_A) { + BLE_sleep_clock_accuracy = STM32WBA5x_REV_ID_A_SCA_RANGE; + } else if (RevID == REV_ID_B) { + BLE_sleep_clock_accuracy = STM32WBA5x_REV_ID_B_SCA_RANGE; + } else { + /* Revision ID not supported, default value of 500ppm applied */ + BLE_sleep_clock_accuracy = STM32WBA5x_DEFAULT_SCA_RANGE; + } +#else + UNUSED(RevID); +#endif + /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ + } else { + /* LSE is not the Link Layer sleep clock source, */ + /* sleep clock accuracy default value is 500 ppm */ + BLE_sleep_clock_accuracy = STM32WBA5x_DEFAULT_SCA_RANGE; + } + + return BLE_sleep_clock_accuracy; +} +#endif /* CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE */ + +void ll_sys_sleep_clock_source_selection(void) +{ + uint16_t freq_value = 0; + uint32_t linklayer_slp_clk_src = LL_RCC_RADIOSLEEPSOURCE_NONE; + + linklayer_slp_clk_src = LL_RCC_RADIO_GetSleepTimerClockSource(); + switch (linklayer_slp_clk_src) { + case LL_RCC_RADIOSLEEPSOURCE_LSE: + linklayer_slp_clk_src = RTC_SLPTMR; + break; + + case LL_RCC_RADIOSLEEPSOURCE_LSI: + linklayer_slp_clk_src = RCO_SLPTMR; + break; + + case LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000: + linklayer_slp_clk_src = CRYSTAL_OSCILLATOR_SLPTMR; + break; + + case LL_RCC_RADIOSLEEPSOURCE_NONE: + /* No Link Layer sleep clock source selected */ + assert_param(0); + break; + } + ll_intf_cmn_le_select_slp_clk_src((uint8_t)linklayer_slp_clk_src, &freq_value); +} + +void ll_sys_reset(void) +{ +#if (CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE == 0) + uint8_t bsca = 0; +#endif /* CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE */ + + /* Apply the selected link layer sleep timer source */ + ll_sys_sleep_clock_source_selection(); + + /* Configure the link layer sleep clock accuracy if different from the default one */ +#if (CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE != 0) + ll_intf_le_set_sleep_clock_accuracy(CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE); +#else + bsca = ll_sys_BLE_sleep_clock_accuracy_selection(); + if (bsca != STM32WBA5x_DEFAULT_SCA_RANGE) { + ll_intf_le_set_sleep_clock_accuracy(bsca); + } +#endif /* CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE */ +} diff --git a/lib/stm32wba/hci/ll_sys_intf.c b/lib/stm32wba/hci/ll_sys_intf.c index e8151693d..2b4634035 100644 --- a/lib/stm32wba/hci/ll_sys_intf.c +++ b/lib/stm32wba/hci/ll_sys_intf.c @@ -21,6 +21,9 @@ #include "event_manager.h" #include "ll_intf.h" +extern uint8_t AHB5_SwitchedOff; +extern uint32_t radio_sleep_timer_val; + /** * @brief Initialize the Link Layer SoC dependencies * @param None @@ -68,9 +71,15 @@ void ll_sys_radio_ack_ctrl(uint8_t enable) */ void ll_sys_radio_wait_for_busclkrdy(void) { - LINKLAYER_PLAT_WaitHclkRdy(); + /* Wait on radio bus clock readiness if it has been turned of */ + if (AHB5_SwitchedOff == 1) + { + AHB5_SwitchedOff = 0; + while (radio_sleep_timer_val == ll_intf_cmn_get_slptmr_value()); + } } + /** * @brief Get RNG number for the Link Layer IP * @param None diff --git a/lib/stm32wba/hci/ll_sys_startup.c b/lib/stm32wba/hci/ll_sys_startup.c index d2e6fad36..4c8f071dc 100644 --- a/lib/stm32wba/hci/ll_sys_startup.c +++ b/lib/stm32wba/hci/ll_sys_startup.c @@ -26,11 +26,16 @@ #include "st_mac_802_15_4_sap.h" #endif /* MAC */ +/** + * @brief Missed HCI event flag + */ +uint8_t missed_hci_event_flag = 0; + static void ll_sys_dependencies_init(void); #ifdef BLE static void ll_sys_event_missed_cb( ble_buff_hdr_t* ptr_evnt_hdr ) { - + missed_hci_event_flag = 1; } /** @@ -40,7 +45,8 @@ static void ll_sys_event_missed_cb( ble_buff_hdr_t* ptr_evnt_hdr ) */ void ll_sys_ble_cntrl_init(hst_cbk hostCallback) { - const struct hci_dispatch_tbl* p_hci_dis_tbl; + const struct hci_dispatch_tbl* p_hci_dis_tbl = NULL; + hci_get_dis_tbl( &p_hci_dis_tbl ); ll_intf_init(p_hci_dis_tbl); @@ -84,7 +90,14 @@ void ll_sys_thread_init(void) */ static void ll_sys_dependencies_init(void) { - ll_sys_status_t dp_slp_status = LL_SYS_ERROR; + static uint8_t is_ll_initialized = 0; + ll_sys_status_t dp_slp_status; + + /* Ensure Link Layer resources are created only once */ + if (is_ll_initialized == 1) { + return; + } + is_ll_initialized = 1; /* Deep sleep feature initialization */ dp_slp_status = ll_sys_dp_slp_init(); @@ -95,4 +108,4 @@ static void ll_sys_dependencies_init(void) /* Link Layer user parameters application */ ll_sys_config_params(); -} +} \ No newline at end of file diff --git a/lib/stm32wba/hci/ll_sys_startup.h b/lib/stm32wba/hci/ll_sys_startup.h index a4e7d2b44..c9018f760 100644 --- a/lib/stm32wba/hci/ll_sys_startup.h +++ b/lib/stm32wba/hci/ll_sys_startup.h @@ -26,4 +26,4 @@ void ll_sys_ble_cntrl_init(hst_cbk hostCallback); void ll_sys_mac_cntrl_init(void); void ll_sys_thread_init(void); -#endif /* LL_SYS_STARTUP_H */ +#endif /* LL_SYS_STARTUP_H */ \ No newline at end of file diff --git a/lib/stm32wba/hci/log_module.c b/lib/stm32wba/hci/log_module.c index 74b5c48f3..3fde2be7a 100644 --- a/lib/stm32wba/hci/log_module.c +++ b/lib/stm32wba/hci/log_module.c @@ -181,7 +181,7 @@ void Log_Module_PrintWithArg( Log_Verbose_Level_t eVerboseLevel, Log_Region_t eR if ( pLogTimeStampFunc != NULL ) { iTempSize = UTIL_ADV_TRACE_TMP_BUF_SIZE - iBuffSize; - pLogTimeStampFunc( &szFullText[iBuffSize], &iTempSize ); + pLogTimeStampFunc( &szFullText[iBuffSize], iTempSize, &iTempSize ); iBuffSize += iTempSize; } #endif /* LOG_INSERT_TIME_STAMP_INSIDE_THE_TRACE */ diff --git a/lib/stm32wba/hci/log_module.h b/lib/stm32wba/hci/log_module.h index 1220b829b..9dfb0a71e 100644 --- a/lib/stm32wba/hci/log_module.h +++ b/lib/stm32wba/hci/log_module.h @@ -30,6 +30,7 @@ extern "C" { #include #include #include +#include "app_conf.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ @@ -288,12 +289,24 @@ void Log_Module_PrintWithArg( Log_Verbose_Level_t eVerboseLevel, Log_Region_t eR /* USER CODE END EFP */ /* Exported macro ------------------------------------------------------------*/ +/* Display 64 bits number for all compiler. */ +/* Example : LOG_INFO_APP( "New Device : " LOG_DISPLAY64() " installed in %d seconds", LOG_NUMBER64( dlDevice ), iTime ); */ +#define LOG_DISPLAY64() "0x%08X%08X" +#define LOG_NUMBER64( number ) (uint32_t)( number >> 32u ), (uint32_t)( number ) + /* Module API - Log macros for each region */ /* LOG_REGION_BLE */ +#if (CFG_LOG_SUPPORTED != 0) #define LOG_INFO_BLE(...) Log_Module_Print( LOG_VERBOSE_INFO, LOG_REGION_BLE, __VA_ARGS__) #define LOG_ERROR_BLE(...) Log_Module_Print( LOG_VERBOSE_ERROR, LOG_REGION_BLE, __VA_ARGS__) #define LOG_WARNING_BLE(...) Log_Module_Print( LOG_VERBOSE_WARNING, LOG_REGION_BLE, __VA_ARGS__) #define LOG_DEBUG_BLE(...) Log_Module_Print( LOG_VERBOSE_DEBUG, LOG_REGION_BLE, __VA_ARGS__) +#else /* (CFG_LOG_SUPPORTED != 0) */ +#define LOG_INFO_BLE(...) do {} while(0) +#define LOG_ERROR_BLE(...) do {} while(0) +#define LOG_WARNING_BLE(...) do {} while(0) +#define LOG_DEBUG_BLE(...) do {} while(0) +#endif /* (CFG_LOG_SUPPORTED != 0) */ /* USER CODE BEGIN LOG_REGION_BLE */ /** @@ -310,10 +323,17 @@ void Log_Module_PrintWithArg( Log_Verbose_Level_t eVerboseLevel, Log_Region_t eR /* USER CODE END LOG_REGION_BLE */ /* LOG_REGION_SYSTEM */ +#if (CFG_LOG_SUPPORTED != 0) #define LOG_INFO_SYSTEM(...) Log_Module_Print( LOG_VERBOSE_INFO, LOG_REGION_SYSTEM, __VA_ARGS__) #define LOG_ERROR_SYSTEM(...) Log_Module_Print( LOG_VERBOSE_ERROR, LOG_REGION_SYSTEM, __VA_ARGS__) #define LOG_WARNING_SYSTEM(...) Log_Module_Print( LOG_VERBOSE_WARNING, LOG_REGION_SYSTEM, __VA_ARGS__) #define LOG_DEBUG_SYSTEM(...) Log_Module_Print( LOG_VERBOSE_DEBUG, LOG_REGION_SYSTEM, __VA_ARGS__) +#else /* (CFG_LOG_SUPPORTED != 0) */ +#define LOG_INFO_SYSTEM(...) do {} while(0) +#define LOG_ERROR_SYSTEM(...) do {} while(0) +#define LOG_WARNING_SYSTEM(...) do {} while(0) +#define LOG_DEBUG_SYSTEM(...) do {} while(0) +#endif /* (CFG_LOG_SUPPORTED != 0) */ /* USER CODE BEGIN LOG_REGION_SYSTEM */ /** @@ -330,10 +350,17 @@ void Log_Module_PrintWithArg( Log_Verbose_Level_t eVerboseLevel, Log_Region_t eR /* USER CODE END LOG_REGION_SYSTEM */ /* LOG_REGION_APP */ +#if (CFG_LOG_SUPPORTED != 0) #define LOG_INFO_APP(...) Log_Module_Print( LOG_VERBOSE_INFO, LOG_REGION_APP, __VA_ARGS__) #define LOG_ERROR_APP(...) Log_Module_Print( LOG_VERBOSE_ERROR, LOG_REGION_APP, __VA_ARGS__) #define LOG_WARNING_APP(...) Log_Module_Print( LOG_VERBOSE_WARNING, LOG_REGION_APP, __VA_ARGS__) #define LOG_DEBUG_APP(...) Log_Module_Print( LOG_VERBOSE_DEBUG, LOG_REGION_APP, __VA_ARGS__) +#else /* (CFG_LOG_SUPPORTED != 0) */ +#define LOG_INFO_APP(...) do {} while(0) +#define LOG_ERROR_APP(...) do {} while(0) +#define LOG_WARNING_APP(...) do {} while(0) +#define LOG_DEBUG_APP(...) do {} while(0) +#endif /* (CFG_LOG_SUPPORTED != 0) */ /* USER CODE BEGIN LOG_REGION_APP */ /** @@ -354,10 +381,17 @@ void Log_Module_PrintWithArg( Log_Verbose_Level_t eVerboseLevel, Log_Region_t eR * Add inside this user section your defines to match the new regions you * created into Log_Region_t. * Example : + * #if (CFG_LOG_SUPPORTED != 0) * #define LOG_INFO_CUSTOM(...) Log_Module_Print( LOG_VERBOSE_INFO, LOG_REGION_CUSTOM, __VA_ARGS__) * #define LOG_ERROR_CUSTOM(...) Log_Module_Print( LOG_VERBOSE_ERROR, LOG_REGION_CUSTOM, __VA_ARGS__) * #define LOG_WARNING_CUSTOM(...) Log_Module_Print( LOG_VERBOSE_WARNING, LOG_REGION_CUSTOM, __VA_ARGS__) * #define LOG_DEBUG_CUSTOM(...) Log_Module_Print( LOG_VERBOSE_DEBUG, LOG_REGION_CUSTOM, __VA_ARGS__) + * #else + * #define LOG_INFO_CUSTOM(...) do {} while(0) + * #define LOG_ERROR_CUSTOM(...) do {} while(0) + * #define LOG_WARNING_CUSTOM(...) do {} while(0) + * #define LOG_DEBUG_CUSTOM(...) do {} while(0) + * #endif */ /* USER CODE END APP_LOG_USER_DEFINES */ diff --git a/lib/stm32wba/hci/pta.h b/lib/stm32wba/hci/pta.h index 7df639abd..afbed1c55 100644 --- a/lib/stm32wba/hci/pta.h +++ b/lib/stm32wba/hci/pta.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.30a-SOW05Patchv6_2/firmware/public_inc/pta.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-LCA00/firmware/public_inc/pta.h#1 $*/ /** ****************************************************************************** * @file pta.h diff --git a/lib/stm32wba/hci/scm.c b/lib/stm32wba/hci/scm.c index 5024e5df2..599725ac0 100644 --- a/lib/stm32wba/hci/scm.c +++ b/lib/stm32wba/hci/scm.c @@ -20,11 +20,10 @@ /* Includes ------------------------------------------------------------------*/ #include "scm.h" -#if (RT_DEBUG_GPIO_MODULE==1) #include "RTDebug.h" -#endif +#include "utilities_common.h" -#if (CFG_SCM_SUPPORTED==1) +#if (CFG_SCM_SUPPORTED == 1) __weak void SCM_HSI_CLK_ON(void) { @@ -73,7 +72,7 @@ static void SwitchHse32toHse16(void); static void SwitchPlltoHse32(void); /* Private functions ---------------------------------------------------------*/ -static scm_clockconfig_t scm_getmaxfreq(void) +OPTIMIZED static scm_clockconfig_t scm_getmaxfreq(void) { uint8_t idx = 0; scm_clockconfig_t max = NO_CLOCK_CONFIG; @@ -89,11 +88,10 @@ static scm_clockconfig_t scm_getmaxfreq(void) return max; } -static void scm_systemclockconfig(void) +OPTIMIZED static void scm_systemclockconfig(void) { -#if (RT_DEBUG_GPIO_MODULE==1) SYSTEM_DEBUG_SIGNAL_SET(SCM_SYSTEM_CLOCK_CONFIG); -#endif + switch (scm_system_clock_config.targeted_clock_freq) { case HSE_16MHZ: @@ -168,12 +166,11 @@ static void scm_systemclockconfig(void) default: break; } -#if (RT_DEBUG_GPIO_MODULE==1) + SYSTEM_DEBUG_SIGNAL_RESET(SCM_SYSTEM_CLOCK_CONFIG); -#endif } -static void SwitchHsePre(scm_hse_hsepre_t hse_pre) +OPTIMIZED static void SwitchHsePre(scm_hse_hsepre_t hse_pre) { /* Start HSI */ SCM_HSI_CLK_ON(); @@ -204,7 +201,7 @@ static void SwitchHsePre(scm_hse_hsepre_t hse_pre) SCM_HSI_CLK_OFF(); } -static void SwitchHse16toHse32(void) +OPTIMIZED static void SwitchHse16toHse32(void) { /** * Switch from HSE_16MHz to HSE_32MHz @@ -228,7 +225,7 @@ static void SwitchHse16toHse32(void) LL_RCC_SetAHB5Divider(LL_RCC_AHB5_DIVIDER_1); /* divided by 1 */ } -static void SwitchHse32toHse16(void) +OPTIMIZED static void SwitchHse32toHse16(void) { /** * Switch from HSE_16MHz to HSE_32MHz @@ -250,7 +247,7 @@ static void SwitchHse32toHse16(void) LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2); } -static void SwitchPlltoHse32(void) +OPTIMIZED static void SwitchPlltoHse32(void) { /** * Switch from PLL to HSE_32MHz @@ -270,7 +267,7 @@ static void SwitchPlltoHse32(void) scm_setwaitstates(HSE32); } -static void ConfigStartPll(void) +OPTIMIZED static void ConfigStartPll(void) { /* Enable PLL1 output for SYSCLK (PLL1R) */ LL_RCC_PLL1_EnableDomain_PLL1R(); @@ -335,7 +332,7 @@ static void ConfigHwPll(scm_pll_config_t *p_hw_config) * @param None * @retval None */ -void scm_init() +OPTIMIZED void scm_init() { /* init scm_system_clock_config with LP config * scm_system_clock_config SHALL BE UPDATED BY READING HW CONFIG FROM HAL APIs @@ -426,11 +423,10 @@ void scm_init() * @param None * @retval None */ -void scm_setup(void) +OPTIMIZED void scm_setup(void) { - #if (RT_DEBUG_GPIO_MODULE==1) SYSTEM_DEBUG_SIGNAL_SET(SCM_SETUP); -#endif + /* System clock is now on HSI 16Mhz, as it exits from stop mode */ /* Start HSE */ @@ -495,7 +491,7 @@ void scm_setup(void) * @retval None * @note scm_pll_setconfig to be called before PLL activation (PLL set as system core clock) */ -void scm_pll_setconfig(const scm_pll_config_t *p_pll_config) +OPTIMIZED void scm_pll_setconfig(const scm_pll_config_t *p_pll_config) { /* Initial PLL configuration */ scm_system_clock_config.pll.PLLM = p_pll_config->PLLM; @@ -518,7 +514,7 @@ void scm_pll_setconfig(const scm_pll_config_t *p_pll_config) * running on the PLL with a different configuration that the * one required */ -void scm_pll_fractional_update(uint32_t pll_frac) +OPTIMIZED void scm_pll_fractional_update(uint32_t pll_frac) { /* PLL1FRACEN set to 0 */ LL_RCC_PLL1FRACN_Disable(); @@ -544,7 +540,7 @@ void scm_pll_fractional_update(uint32_t pll_frac) * @arg SYS_PLL * @retval None */ -void scm_setsystemclock(scm_user_id_t user_id, scm_clockconfig_t sysclockconfig) +OPTIMIZED void scm_setsystemclock(scm_user_id_t user_id, scm_clockconfig_t sysclockconfig) { scm_clockconfig_t max_freq_requested; @@ -655,7 +651,7 @@ __WEAK void scm_pllready(void) * @arg PLL * @retval None */ -void scm_setwaitstates(const scm_ws_lp_t ws_lp_config) +OPTIMIZED void scm_setwaitstates(const scm_ws_lp_t ws_lp_config) { /* Configure flash and SRAMs */ switch (ws_lp_config) { @@ -715,11 +711,10 @@ void scm_setwaitstates(const scm_ws_lp_t ws_lp_config) * @param None * @retval None */ -void scm_hserdy_isr(void) +OPTIMIZED void scm_hserdy_isr(void) { - #if (RT_DEBUG_GPIO_MODULE==1) SYSTEM_DEBUG_SIGNAL_SET(SCM_HSERDY_ISR); -#endif + if(LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI) { /* Wait until VOS has changed */ @@ -783,7 +778,7 @@ void scm_hserdy_isr(void) * @param None * @retval None */ -void scm_pllrdy_isr(void) +OPTIMIZED void scm_pllrdy_isr(void) { if(scm_system_clock_config.targeted_clock_freq == SYS_PLL) { @@ -821,7 +816,7 @@ void scm_pllrdy_isr(void) * @arg SCM_RADIO_NOT_ACTIVE * @retval None */ -void scm_notifyradiostate(const scm_radio_state_t radio_state) +OPTIMIZED void scm_notifyradiostate(const scm_radio_state_t radio_state) { if(radio_state != SCM_RADIO_NOT_ACTIVE) { @@ -840,7 +835,7 @@ void scm_notifyradiostate(const scm_radio_state_t radio_state) * @param None * @retval None */ -void scm_standbyexit(void) +OPTIMIZED void scm_standbyexit(void) { if(scm_system_clock_config.pll.are_pll_params_initialized == 1) { diff --git a/lib/stm32wba/hci/utilities_common.h b/lib/stm32wba/hci/utilities_common.h index 46a7e75ff..85e42ad3b 100644 --- a/lib/stm32wba/hci/utilities_common.h +++ b/lib/stm32wba/hci/utilities_common.h @@ -140,4 +140,22 @@ extern "C" { for(volatile unsigned int cpt = 178 ; cpt!=0 ; --cpt);\ } while(0) +#define STM32WBA5x_DEFAULT_SCA_RANGE (0) +#define STM32WBA5x_REV_ID_A_SCA_RANGE (STM32WBA5x_DEFAULT_SCA_RANGE) +#define STM32WBA5x_REV_ID_B_SCA_RANGE (4) + +/* Macro helper for optimizing by speed specific functions. + * For IAR only: The functions with this definition will be optimized + * by speed only if the project uses a High optimisation level. + */ +#if defined(__IAR_SYSTEMS_ICC__) +#define OPTIMIZED _Pragma("optimize=speed") +#elif defined(__clang__) +#define OPTIMIZED _Pragma("pragma Ofast") +#elif defined(__GNUC__) +#define OPTIMIZED __attribute__((optimize("Ofast"))) +#endif + +#define UTIL_UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + #endif /* UTILITIES_COMMON_H */ diff --git a/lib/stm32wba/hci/utilities_conf.h b/lib/stm32wba/hci/utilities_conf.h index 56d7d6718..8365e3bdb 100644 --- a/lib/stm32wba/hci/utilities_conf.h +++ b/lib/stm32wba/hci/utilities_conf.h @@ -28,7 +28,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "cmsis_compiler.h" - +#include "app_conf.h" /* definitions to be provided to "sequencer" utility */ #include "stm32_mem.h" /* definition and callback for tiny_vsnprintf */ @@ -148,9 +148,9 @@ extern "C" { #define UTIL_ADV_TRACE_INIT_CRITICAL_SECTION( ) UTILS_INIT_CRITICAL_SECTION() /*!< init the critical section in trace feature */ #define UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION( ) UTILS_ENTER_CRITICAL_SECTION() /*!< enter the critical section in trace feature */ #define UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION( ) UTILS_EXIT_CRITICAL_SECTION() /*!< exit the critical section in trace feature */ -#define UTIL_ADV_TRACE_TMP_BUF_SIZE (256U) /*!< default trace buffer size */ -#define UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE (15U) /*!< default trace timestamp size */ -#define UTIL_ADV_TRACE_FIFO_SIZE (4096U) /*!< default trace fifo size */ +#define UTIL_ADV_TRACE_TMP_BUF_SIZE (CFG_LOG_TRACE_BUF_SIZE) /*!< trace buffer size */ +#define UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE (15U) /*!< trace timestamp size */ +#define UTIL_ADV_TRACE_FIFO_SIZE (CFG_LOG_TRACE_FIFO_SIZE) /*!< trace fifo size */ #define UTIL_ADV_TRACE_MEMSET8( dest, value, size) UTIL_MEM_set_8((dest),(value),(size)) /*!< memset utilities interface to trace feature */ #define UTIL_ADV_TRACE_VSNPRINTF(...) vsnprintf(__VA_ARGS__) /*!< vsnprintf utilities interface to trace feature */ diff --git a/scripts/ble_library.py b/scripts/ble_library.py index 4a908ffa8..618e73fe9 100644 --- a/scripts/ble_library.py +++ b/scripts/ble_library.py @@ -74,6 +74,7 @@ "Middlewares/ST/STM32_WPAN/link_layer/ll_sys/src/ll_sys_startup.c", "Middlewares/ST/STM32_WPAN/link_layer/ll_sys/inc/ll_sys_startup.h", "Middlewares/ST/STM32_WPAN/stm32_wpan_common.h", + "Middlewares/ST/STM32_WPAN/ll_intf_cmn.h", ble_heartrate_app_path + "/Core/Inc/app_common.h", ble_heartrate_app_path + "/Core/Inc/app_conf.h", ble_heartrate_app_path + "/Core/Inc/app_entry.h", @@ -106,6 +107,8 @@ ble_heartrate_app_path + "/STM32_WPAN/Target/power_table.c", ble_heartrate_app_path + "/STM32_WPAN/Target/bpka.c", ble_heartrate_app_path + "/STM32_WPAN/Target/bpka.h", + ble_heartrate_app_path + "/STM32_WPAN/Target/linklayer_plat.c", + ble_heartrate_app_path + "/STM32_WPAN/Target/ll_sys_if.c", "Utilities/trace/adv_trace/stm32_adv_trace.h", "Utilities/misc/stm32_mem.h", "Utilities/tim_serv/stm32_timer.h", diff --git a/stm32cube/common_ll/README.rst b/stm32cube/common_ll/README.rst index da5f63ada..150496706 100644 --- a/stm32cube/common_ll/README.rst +++ b/stm32cube/common_ll/README.rst @@ -30,7 +30,7 @@ stm32mp1xx 1.6.0 stm32u0xx 1.1.0 stm32u5xx 1.6.0 stm32wb0x 1.0.0 -stm32wbaxx 1.3.1 -stm32wbxx 1.19.1 +stm32wbaxx 1.4.1 +stm32wbxx 1.20.0 stm32wlxx 1.3.0 =============== =============== \ No newline at end of file diff --git a/stm32cube/stm32wbaxx/CMakeLists.txt b/stm32cube/stm32wbaxx/CMakeLists.txt index 23aa11d4c..49d5c523f 100644 --- a/stm32cube/stm32wbaxx/CMakeLists.txt +++ b/stm32cube/stm32wbaxx/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2023 STMicroelectronics +# Copyright (c) 2020 STMicroelectronics # # SPDX-License-Identifier: Apache-2.0 diff --git a/stm32cube/stm32wbaxx/README b/stm32cube/stm32wbaxx/README index f6ab0f43a..98f15ddf9 100644 --- a/stm32cube/stm32wbaxx/README +++ b/stm32cube/stm32wbaxx/README @@ -6,7 +6,7 @@ Origin: http://www.st.com/en/embedded-software/stm32cubewba.html Status: - version v1.3.1 + version v1.4.1 Purpose: ST Microelectronics official MCU package for STM32WBA series. @@ -23,7 +23,7 @@ URL: https://github.com/STMicroelectronics/STM32CubeWBA Commit: - 8d1d0ffef7a3a25d8ee8f589a614bc5da65c9300 + 3820501e7e128592290861c9cc0f7189246bf00d Maintained-by: External diff --git a/stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h index d1f4f7e67..73ae9eedd 100644 --- a/stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h +++ b/stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h @@ -806,6 +806,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -1817,7 +1832,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -2731,6 +2746,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3910,7 +3931,7 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h index 761782c32..173884887 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h @@ -79,7 +79,7 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @brief STM32WBAxx HAL Driver version number */ #define __STM32WBAxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBAxx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ +#define __STM32WBAxx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ #define __STM32WBAxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBAxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBAxx_HAL_VERSION ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\ @@ -119,6 +119,38 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @} */ +/** @defgroup SYSCFG_Compensation_Cell_Selection Compensation Cell Selection + * @{ + */ +#define SYSCFG_IO_CELL SYSCFG_CCCSR_EN1 /*!< Compensation cell for the VDD I/O power rail */ +#ifdef SYSCFG_CCCSR_EN2 +#define SYSCFG_IO2_CELL SYSCFG_CCCSR_EN2 /*!< Compensation cell for the VDDIO2 I/O power rail */ +#endif /* SYSCFG_CCCSR_EN2 */ +/** + * @} + */ + +/** @defgroup SYSCFG_Compensation_Cell_Ready_Selection Compensation Cell Ready Selection + * @{ + */ +#define SYSCFG_IO_CELL_READY SYSCFG_CCCSR_RDY1 /*!< Ready flag of compensation cell for the VDD I/O power rail */ +#ifdef SYSCFG_CCCSR_EN2 +#define SYSCFG_IO2_CELL_READY SYSCFG_CCCSR_RDY2 /*!< Ready flag of compensation cell for the VDDIO2 I/O power rail */ +#endif /* SYSCFG_CCCSR_EN2 */ +/** + * @} + */ + +/** @defgroup SYSCFG_IO_Compensation_Code_Config IO Compensation Code config + * @{ + */ +#define SYSCFG_IO_CELL_CODE 0UL /*!< Code from the cell */ +#define SYSCFG_IO_REGISTER_CODE 1UL /*!< Code from the values in the cell code register */ +/** + * @} + */ + + /** @defgroup SYSCFG_Flags_Definition Flags * @{ */ @@ -188,6 +220,83 @@ extern HAL_TickFreqTypeDef uwTickFreq; * @} */ +#ifdef SYSCFG_OTGHSPHYCR_EN +/** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection + * @{ + */ + +/** @brief OTG HS PHY reference clock frequency selection + */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */ +#define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */ +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down + * @{ + */ + +/** @brief OTG HS PHY Power Down config + */ +#define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */ +#define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */ +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable + * @{ + */ +#define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */ +#define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */ +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current + * @{ + */ + +/** @brief High-speed (HS) transmitter preemphasis current control + */ +#define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ +#define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ +#define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ +#define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold + * @{ + */ + +/** @brief Squelch threshold adjustment + */ +#define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ +#define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ +/** + * @} + */ + +/** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold + * @{ + */ + +/** @brief Disconnect threshold adjustment + */ +#define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ +#define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYCR_EN */ + /** * @} */ @@ -391,11 +500,31 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_ALL) != 0x00U) && \ (((__INTERRUPT__) & ~SYSCFG_IT_FPU_ALL) == 0x00U)) +#ifdef SYSCFG_CCCSR_EN2 +#define IS_SYSCFG_COMPENSATION_CELL(__CELL__) (((__CELL__) == SYSCFG_IO_CELL) || \ + ((__CELL__) == SYSCFG_IO2_CELL)) + +#define IS_SYSCFG_COMPENSATION_CELL_READY(__CELL__) (((__CELL__) == SYSCFG_IO_CELL_READY) || \ + ((__CELL__) == SYSCFG_IO2_CELL_READY)) +#else +#define IS_SYSCFG_COMPENSATION_CELL(__CELL__) (((__CELL__) == SYSCFG_IO_CELL)) + +#define IS_SYSCFG_COMPENSATION_CELL_READY(__CELL__) (((__CELL__) == SYSCFG_IO_CELL_READY)) +#endif /* SYSCFG_CCCSR_EN2 */ + +#define IS_SYSCFG_COMPENSATION_CELL_CODE(__VALUE__) (((__VALUE__) == SYSCFG_IO_CELL_CODE) || \ + ((__VALUE__) == SYSCFG_IO_REGISTER_CODE)) + +#define IS_SYSCFG_COMPENSATION_CELL_PMOS_VALUE(__VALUE__) (((__VALUE__) < 16U)) + +#define IS_SYSCFG_COMPENSATION_CELL_NMOS_VALUE(__VALUE__) (((__VALUE__) < 16U)) + #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) + #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_ALL) != 0x00U) && \ (((__PIN__) & ~SYSCFG_FASTMODEPLUS_ALL) == 0x00U)) @@ -418,6 +547,31 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_LOCK_ALL) != 0x00U) && \ (((__ITEM__) & ~SYSCFG_LOCK_ALL) == 0x00U)) +#ifdef SYSCFG_OTGHSPHYCR_EN +#define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6)) + +#define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON)) + +#define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE)) + +#define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT)) + +#define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT)) + +#define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \ + ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X)) +#endif /* SYSCFG_OTGHSPHYCR_EN */ /** * @} @@ -487,10 +641,28 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); */ /* SYSCFG Control functions ****************************************************/ -void HAL_SYSCFG_SRAM2Erase(void); void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); - +void HAL_SYSCFG_EnableIOAnalogSwitchVdd(void); +void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void); + + +#ifdef SYSCFG_OTGHSPHYCR_EN +void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClockSelection); +void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig); +void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig); +void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); +void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); +void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); +#endif /* SYSCFG_OTGHSPHYCR_EN */ + +void HAL_SYSCFG_EnableCompensationCell(uint32_t Selection); +void HAL_SYSCFG_DisableCompensationCell(uint32_t Selection); +uint32_t HAL_SYSCFG_GetCompensationCellReadyStatus(uint32_t Selection); +void HAL_SYSCFG_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue, + uint32_t PmosValue); +HAL_StatusTypeDef HAL_SYSCFG_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue, + uint32_t *pPmosValue); /** * @} */ @@ -500,7 +672,7 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); */ /* SYSCFG Lock functions ********************************************/ -void HAL_SYSCFG_Lock(uint32_t Item); +void HAL_SYSCFG_Lock(uint32_t Item); HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); /** @@ -514,7 +686,7 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); #if defined (SYSCFG_SECCFGR_SYSCFGSEC) /* SYSCFG Attributes functions ********************************************/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); +void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); #endif /* __ARM_FEATURE_CMSE */ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); #endif /* SYSCFG_SECCFGR_SYSCFGSEC */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cortex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cortex.h index 8d0f9ac34..2c6ff0507 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cortex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cortex.h @@ -121,10 +121,10 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE 0U -#define MPU_HARDFAULT_NMI 2U -#define MPU_PRIVILEGED_DEFAULT 4U -#define MPU_HFNMI_PRIVDEF 6U +#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -132,8 +132,8 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ -#define MPU_REGION_ENABLE 1U -#define MPU_REGION_DISABLE 0U +#define MPU_REGION_ENABLE 1U /*!< Enable region */ +#define MPU_REGION_DISABLE 0U /*!< Disable region */ /** * @} */ @@ -141,8 +141,8 @@ typedef struct /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ -#define MPU_INSTRUCTION_ACCESS_ENABLE 0U -#define MPU_INSTRUCTION_ACCESS_DISABLE 1U +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */ +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */ /** * @} */ @@ -150,9 +150,9 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ -#define MPU_ACCESS_NOT_SHAREABLE 0U -#define MPU_ACCESS_OUTER_SHAREABLE 2U -#define MPU_ACCESS_INNER_SHAREABLE 3U +#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */ +#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */ +#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */ /** * @} */ @@ -160,10 +160,10 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_PRIV_RW 0U -#define MPU_REGION_ALL_RW 1U -#define MPU_REGION_PRIV_RO 2U -#define MPU_REGION_ALL_RO 3U +#define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */ +#define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */ +#define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */ +#define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */ /** * @} */ @@ -201,22 +201,30 @@ typedef struct /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes * @{ */ -#define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ - -#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ -#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - -#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ -#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - -#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ -#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ -#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ -#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/* Device memory attributes */ +#define MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* To set with INNER_OUTER() macro for both inner/outer cache attributes */ + +/* Non-cacheable memory attribute */ +#define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ +#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ +/* - transient mode attribute */ +#define MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ +#define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ +/* - allocation attribute */ +#define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ +#define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ +#define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ +#define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio_ex.h index 735a5b393..a4dc06bb3 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio_ex.h @@ -44,9 +44,7 @@ extern "C" { * @{ */ -/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection - * @{ - */ + #if defined(STM32WBA54xx) || defined(STM32WBA55xx) /** @@ -117,18 +115,7 @@ extern "C" { /** * @brief AF 11 selection */ -#define GPIO_AF11_RF_ANTSW0 ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ -#define GPIO_AF11_RF_ANTSW1 ((uint8_t)0x0B) /*!< RF_ANTSW1 Alternate Function mapping */ -#define GPIO_AF11_RF_ANTSW2 ((uint8_t)0x0B) /*!< RF_ANTSW2 Alternate Function mapping */ -#define GPIO_AF11_RF_IO1 ((uint8_t)0x0B) /*!< RF_IO1 Alternate Function mapping */ -#define GPIO_AF11_RF_IO2 ((uint8_t)0x0B) /*!< RF_IO2 Alternate Function mapping */ -#define GPIO_AF11_RF_IO3 ((uint8_t)0x0B) /*!< RF_IO3 Alternate Function mapping */ -#define GPIO_AF11_RF_IO4 ((uint8_t)0x0B) /*!< RF_IO4 Alternate Function mapping */ -#define GPIO_AF11_RF_IO5 ((uint8_t)0x0B) /*!< RF_IO5 Alternate Function mapping */ -#define GPIO_AF11_RF_IO6 ((uint8_t)0x0B) /*!< RF_IO6 Alternate Function mapping */ -#define GPIO_AF11_RF_IO7 ((uint8_t)0x0B) /*!< RF_IO7 Alternate Function mapping */ -#define GPIO_AF11_RF_IO8 ((uint8_t)0x0B) /*!< RF_IO8 Alternate Function mapping */ -#define GPIO_AF11_RF_IO9 ((uint8_t)0x0B) /*!< RF_IO9 Alternate Function mapping */ +#define GPIO_AF11_RF ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ /** * @brief AF 12 selection @@ -228,18 +215,7 @@ extern "C" { /** * @brief AF 11 selection */ -#define GPIO_AF11_RF_ANTSW0 ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ -#define GPIO_AF11_RF_ANTSW1 ((uint8_t)0x0B) /*!< RF_ANTSW1 Alternate Function mapping */ -#define GPIO_AF11_RF_ANTSW2 ((uint8_t)0x0B) /*!< RF_ANTSW2 Alternate Function mapping */ -#define GPIO_AF11_RF_IO1 ((uint8_t)0x0B) /*!< RF_IO1 Alternate Function mapping */ -#define GPIO_AF11_RF_IO2 ((uint8_t)0x0B) /*!< RF_IO2 Alternate Function mapping */ -#define GPIO_AF11_RF_IO3 ((uint8_t)0x0B) /*!< RF_IO3 Alternate Function mapping */ -#define GPIO_AF11_RF_IO4 ((uint8_t)0x0B) /*!< RF_IO4 Alternate Function mapping */ -#define GPIO_AF11_RF_IO5 ((uint8_t)0x0B) /*!< RF_IO5 Alternate Function mapping */ -#define GPIO_AF11_RF_IO6 ((uint8_t)0x0B) /*!< RF_IO6 Alternate Function mapping */ -#define GPIO_AF11_RF_IO7 ((uint8_t)0x0B) /*!< RF_IO7 Alternate Function mapping */ -#define GPIO_AF11_RF_IO8 ((uint8_t)0x0B) /*!< RF_IO8 Alternate Function mapping */ -#define GPIO_AF11_RF_IO9 ((uint8_t)0x0B) /*!< RF_IO9 Alternate Function mapping */ +#define GPIO_AF11_RF ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ /** * @brief AF 13 selection @@ -316,18 +292,7 @@ extern "C" { /** * @brief AF 11 selection */ -#define GPIO_AF11_RF_ANTSW0 ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ -#define GPIO_AF11_RF_ANTSW1 ((uint8_t)0x0B) /*!< RF_ANTSW1 Alternate Function mapping */ -#define GPIO_AF11_RF_ANTSW2 ((uint8_t)0x0B) /*!< RF_ANTSW2 Alternate Function mapping */ -#define GPIO_AF11_RF_IO1 ((uint8_t)0x0B) /*!< RF_IO1 Alternate Function mapping */ -#define GPIO_AF11_RF_IO2 ((uint8_t)0x0B) /*!< RF_IO2 Alternate Function mapping */ -#define GPIO_AF11_RF_IO3 ((uint8_t)0x0B) /*!< RF_IO3 Alternate Function mapping */ -#define GPIO_AF11_RF_IO4 ((uint8_t)0x0B) /*!< RF_IO4 Alternate Function mapping */ -#define GPIO_AF11_RF_IO5 ((uint8_t)0x0B) /*!< RF_IO5 Alternate Function mapping */ -#define GPIO_AF11_RF_IO6 ((uint8_t)0x0B) /*!< RF_IO6 Alternate Function mapping */ -#define GPIO_AF11_RF_IO7 ((uint8_t)0x0B) /*!< RF_IO7 Alternate Function mapping */ -#define GPIO_AF11_RF_IO8 ((uint8_t)0x0B) /*!< RF_IO8 Alternate Function mapping */ -#define GPIO_AF11_RF_IO9 ((uint8_t)0x0B) /*!< RF_IO9 Alternate Function mapping */ +#define GPIO_AF11_RF ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ /** * @brief AF 14 selection @@ -352,10 +317,6 @@ extern "C" { #endif /* defined(STM32WBA50xx) */ -/** - * @} - */ - /** * @} */ @@ -378,6 +339,10 @@ extern "C" { * @} */ +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gtzc.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gtzc.h index 0d756f4de..60d9584a9 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gtzc.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gtzc.h @@ -152,14 +152,22 @@ typedef struct */ /* GTZC */ #define GTZC_PERIPH_TIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) +#if defined (TIM3) #define GTZC_PERIPH_TIM3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) +#endif /* TIM3 */ +#if defined (WWDG) #define GTZC_PERIPH_WWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) +#endif /* WWDG */ #define GTZC_PERIPH_IWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) +#if defined (USART2) #define GTZC_PERIPH_USART2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) +#endif /* USART2 */ #define GTZC_PERIPH_I2C1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) #define GTZC_PERIPH_LPTIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) +#if defined (TIM1) #define GTZC_PERIPH_TIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) +#endif /* TIM1 */ #define GTZC_PERIPH_SPI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) #define GTZC_PERIPH_USART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) #define GTZC_PERIPH_TIM16 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) @@ -167,7 +175,9 @@ typedef struct #if defined (SAI1) #define GTZC_PERIPH_SAI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) #endif /* SAI1 */ +#if defined (SPI3) #define GTZC_PERIPH_SPI3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI3_Pos) +#endif /* SPI3 */ #define GTZC_PERIPH_LPUART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPUART1_Pos) #define GTZC_PERIPH_I2C3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_I2C3_Pos) #define GTZC_PERIPH_LPTIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPTIM1_Pos) @@ -177,13 +187,19 @@ typedef struct #define GTZC_PERIPH_ADC4 (GTZC_PERIPH_REG2 | GTZC_CFGR2_ADC4_Pos) #define GTZC_PERIPH_CRC (GTZC_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) +#if defined (TSC) #define GTZC_PERIPH_TSC (GTZC_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) +#endif /* TSC */ #define GTZC_PERIPH_ICACHE_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) #define GTZC_PERIPH_AES (GTZC_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) #define GTZC_PERIPH_HASH (GTZC_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) #define GTZC_PERIPH_RNG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) +#if defined (SAES) #define GTZC_PERIPH_SAES (GTZC_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) +#endif /* SAES */ +#if defined (HSEM) #define GTZC_PERIPH_HSEM (GTZC_PERIPH_REG3 | GTZC_CFGR3_HSEM_Pos) +#endif /* HSEM */ #define GTZC_PERIPH_PKA (GTZC_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) #define GTZC_PERIPH_RAMCFG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) #define GTZC_PERIPH_RADIO (GTZC_PERIPH_REG3 | GTZC_CFGR3_RADIO_Pos) @@ -191,7 +207,9 @@ typedef struct #define GTZC_PERIPH_PTACONV (GTZC_PERIPH_REG3 | GTZC_CFGR3_PTACONV_Pos) #endif /* PTACONV */ +#if defined (GPDMA1) #define GTZC_PERIPH_GPDMA1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) +#endif /* GPDMA1 */ #define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) #define GTZC_PERIPH_FLASH_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) #define GTZC_PERIPH_SYSCFG (GTZC_PERIPH_REG4 | GTZC_CFGR4_SYSCFG_Pos) @@ -206,8 +224,10 @@ typedef struct #define GTZC_PERIPH_MPCBB1_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) #define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) #define GTZC_PERIPH_MPCBB2_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) +#if defined (SRAM6_BASE) #define GTZC_PERIPH_SRAM6 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos) #define GTZC_PERIPH_MPCBB6_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos) +#endif /* SRAM6 */ #define GTZC_PERIPH_ALL (0x00000020U) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_i2c_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_i2c_ex.h index 4309ee25a..cc84e89e0 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_i2c_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_i2c_ex.h @@ -100,9 +100,9 @@ typedef struct * @{ */ #if defined(I2C1) -#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 */ -#endif /* I2C1, I2C2 */ -#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3, I2C4 */ +#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ +#endif /* I2C1 */ +#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ #if defined(I2C_TRIG_GRP1) #define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U)) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc.h index e39bca307..4c71368f8 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc.h @@ -477,7 +477,9 @@ typedef struct #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ +#if defined(WWDG) #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#endif /* WWDG */ #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ /** * @} @@ -501,11 +503,18 @@ typedef struct #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#if defined(WWDG) #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#endif /* WWDG */ #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ +#if defined(WWDG) #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ RCC_RESET_FLAG_LPWR) +#else +#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ + RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_LPWR) +#endif /* WWDG */ /** * @} */ @@ -534,7 +543,7 @@ typedef struct */ #define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ #define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ #define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ #endif @@ -555,6 +564,8 @@ typedef struct * using it. * @{ */ + +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ @@ -562,6 +573,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -579,6 +591,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(TSC) #define __HAL_RCC_TSC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ @@ -586,6 +599,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* TSC */ #define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -613,14 +627,16 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) #if defined(GTZC_TZSC) #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) -#endif +#endif /* GTZC_TZSC */ #define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) /** @@ -703,6 +719,7 @@ typedef struct } while(0) #endif /* SAES */ +#if defined(HSEM) #define __HAL_RCC_HSEM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN); \ @@ -710,6 +727,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* HSEM */ #define __HAL_RCC_PKA_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -719,6 +737,8 @@ typedef struct UNUSED(tmpreg); \ } while(0) + + #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ @@ -736,8 +756,10 @@ typedef struct #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) #if defined(SAES) #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) -#endif +#endif /* SAES */ +#if defined(HSEM) #define __HAL_RCC_HSEM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN) +#endif /* HSEM */ #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) /** @@ -802,7 +824,7 @@ typedef struct #if defined(PTACONV) #define __HAL_RCC_PTACONV_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN) -#endif +#endif /* PTACONV */ /** * @} */ @@ -834,6 +856,7 @@ typedef struct #endif /* TIM3 */ +#if defined(WWDG) #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ @@ -841,6 +864,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ UNUSED(tmpreg); \ } while(0) +#endif /* WWDG */ #if defined(USART2) @@ -879,16 +903,16 @@ typedef struct #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) #if defined(TIM3) #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) -#endif +#endif /* TIM3 */ #if defined(USART2) #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) -#endif +#endif /* LPTIM2 */ /** * @} */ @@ -900,6 +924,7 @@ typedef struct * using it. * @{ */ +#if defined(TIM1) #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ @@ -907,6 +932,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ UNUSED(tmpreg); \ } while(0) +#endif /* TIM1 */ #if defined(SPI1) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ @@ -954,18 +980,21 @@ typedef struct } while(0) #endif /* SAI1 */ + +#if defined(TIM1) #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) +#endif /* TIM1 */ #if defined(SPI1) #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) #if defined(TIM17) #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) -#endif +#endif /* SAI1 */ /** * @} */ @@ -1049,14 +1078,16 @@ typedef struct * @brief Check whether the AHB1 peripheral clock is enabled or not. * @{ */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) #if defined(GTZC_TZSC) #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U) -#endif +#endif /* GTZC_TZSC */ #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) /** * @} @@ -1075,8 +1106,10 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) #if defined(SAES) #define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) != 0U) -#endif +#endif /* SAES */ +#if defined(HSEM) #define __HAL_RCC_HSEM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN) != 0U) +#endif /* HSEM */ #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U) /** @@ -1112,17 +1145,19 @@ typedef struct #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) #if defined(TIM3) #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) -#endif +#endif /* TIM3 */ +#if defined(WWDG) #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) +#endif /* WWDG */ #if defined(USART2) #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) -#endif +#endif /* LPTIM2 */ /** * @} */ @@ -1131,18 +1166,20 @@ typedef struct * @brief Check whether the APB2 peripheral clock is enabled or not. * @{ */ + #if defined(TIM1) #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) +#endif /* TIM1 */ #if defined(SPI1) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) #if defined(TIM17) #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) -#endif +#endif /* SAI1 */ /** * @} */ @@ -1167,12 +1204,16 @@ typedef struct * @{ */ #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#endif /* GPDMA1 */ #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#endif /* GPDMA1 */ #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) /** @@ -1193,10 +1234,11 @@ typedef struct #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) #if defined(SAES) #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) -#endif +#endif /* SAES */ +#if defined(HSEM) #define __HAL_RCC_HSEM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HSEMRST) +#endif /* HSEM */ #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) - #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) @@ -1207,8 +1249,10 @@ typedef struct #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) #if defined(SAES) #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) -#endif +#endif /* SAES */ +#if defined(HSEM) #define __HAL_RCC_HSEM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HSEMRST) +#endif /* HSEM */ #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) /** * @} @@ -1235,13 +1279,13 @@ typedef struct #define __HAL_RCC_RADIO_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_RADIORST) #if defined(PTACONV) #define __HAL_RCC_PTACONV_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_PTACONVRST) -#endif +#endif /* PTACONV */ #define __HAL_RCC_AHB5_RELEASE_RESET() WRITE_REG(RCC->AHB5RSTR, 0x00000000U) #define __HAL_RCC_RADIO_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_RADIORST) #if defined(PTACONV) #define __HAL_RCC_PTACONV_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_PTACONVRST) -#endif +#endif /* PTACONV */ /** * @} */ @@ -1257,16 +1301,16 @@ typedef struct #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) #if defined(TIM3) #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) -#endif +#endif /* TIM3 */ #if defined(USART2) #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) -#endif +#endif /* LPTIM2 */ #define __HAL_RCC_APB1_RELEASE_RESET() do { \ WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \ @@ -1275,16 +1319,16 @@ typedef struct #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) #if defined(TIM3) #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) -#endif +#endif /* TIM3 */ #if defined(USART2) #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) -#endif +#endif /* LPTIM2 */ /** * @} */ @@ -1294,32 +1338,34 @@ typedef struct * @{ */ #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) +#if defined(TIM1) #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) +#endif /* TIM1 */ #if defined(SPI1) #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) #if defined(TIM17) #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) -#endif +#endif /* SAI1 */ #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) #if defined(SPI1) #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) #if defined(TIM17) #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) -#endif +#endif /* SAI1 */ /** * @} */ @@ -1356,25 +1402,29 @@ typedef struct * is enabled only when a peripheral requests AHB clock. * @{ */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) #if defined(GTZC_TZSC) #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) -#endif +#endif /* GTZC_TZSC */ #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) #if defined(GTZC_TZSC) #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) -#endif +#endif /* GTZC_TZSC */ #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) /** @@ -1399,7 +1449,7 @@ typedef struct #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) #if defined(SAES) #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) -#endif +#endif /* SAES */ #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) @@ -1412,7 +1462,7 @@ typedef struct #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) #if defined(SAES) #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) -#endif +#endif /* SAES */ #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) /** @@ -1452,7 +1502,7 @@ typedef struct #if defined(PTACONV) #define __HAL_RCC_PTACONV_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_PTACONVSMEN) #define __HAL_RCC_PTACONV_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_PTACONVSMEN) -#endif +#endif /* PTACONV */ /** * @} */ @@ -1469,32 +1519,36 @@ typedef struct #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) #if defined(TIM3) #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) -#endif +#endif /* TIM3 */ +#if defined(WWDG) #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) +#endif /* WWDG */ #if defined(USART2) #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) -#endif +#endif /* LPTIM2 */ #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) #if defined(TIM3) #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) -#endif +#endif /* TIM3 */ +#if defined(WWDG) #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) +#endif /* WWDG */ #if defined(USART2) #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) -#endif +#endif /* LPTIM2 */ /** * @} */ @@ -1508,31 +1562,33 @@ typedef struct * is enabled only when a peripheral requests APB clock. * @{ */ +#if defined(TIM1) #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) +#endif /* TIM1 */ #if defined(SPI1) #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) #if defined(TIM17) #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) -#endif +#endif /* SAI1 */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) #if defined(SPI1) #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) #if defined(TIM17) #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) -#endif +#endif /* SAI1 */ /** * @} */ @@ -1569,14 +1625,16 @@ typedef struct * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) is enabled or not. * @{ */ +#if defined(GPDMA1) #define __HAL_RCC_GPDMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) != 0U) +#endif /* GPDMA1 */ #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) #define __HAL_RCC_RAMCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) != 0U) #if defined(GTZC_TZSC) #define __HAL_RCC_GTZC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) != 0U) -#endif +#endif /* GTZC_TZSC */ #define __HAL_RCC_ICACHE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) != 0U) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) /** @@ -1596,7 +1654,7 @@ typedef struct #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) #if defined(SAES) #define __HAL_RCC_SAES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) != 0U) -#endif +#endif /* SAES */ #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) != 0U) #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) /** @@ -1620,7 +1678,7 @@ typedef struct #define __HAL_RCC_RADIO_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_RADIOSMEN) != 0U) #if defined(PTACONV) #define __HAL_RCC_PTACONV_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_PTACONVSMEN) != 0U) -#endif +#endif /* PTACONV */ /** * @} */ @@ -1632,17 +1690,19 @@ typedef struct #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) #if defined(TIM3) #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) -#endif +#endif /* TIM3 */ +#if defined(WWDG) #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) +#endif /* WWDG */ #if defined(USART2) #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) -#endif +#endif /* USART2 */ #if defined(I2C1) #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) -#endif +#endif /* I2C1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) -#endif +#endif /* LPTIM2 */ /** * @} */ @@ -1651,18 +1711,20 @@ typedef struct * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. * @{ */ +#if defined(TIM1) #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) +#endif /* TIM1 */ #if defined(SPI1) #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) -#endif +#endif /* SPI1 */ #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) #if defined(TIM17) #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) -#endif +#endif /* TIM17 */ #if defined(SAI1) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) -#endif +#endif /* SAI1 */ /** * @} */ @@ -2231,7 +2293,7 @@ typedef struct * @arg @ref RCC_FLAG_PINRST Pin reset * @arg @ref RCC_FLAG_SFTRST Software reset * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset - * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset(*) * @arg @ref RCC_FLAG_LPWRRST Low Power reset * (*) Feature not available on all devices of the family * @retval The new state of __FLAG__ (TRUE or FALSE). @@ -2370,7 +2432,7 @@ typedef struct #define IS_RCC_ITEM_ATTRIBUTES(__ITEM__) (((__ITEM__) != 0x00U) && (((__ITEM__) & ~RCC_ALL) == 0x00U)) -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_RCC_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == RCC_SEC_PRIV) || \ ((__ATTRIBUTES__) == RCC_SEC_NPRIV) || \ ((__ATTRIBUTES__) == RCC_NSEC_PRIV) || \ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc_ex.h index c20abb2b8..73b7be4e0 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc_ex.h @@ -844,7 +844,7 @@ uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void); * @{ */ /* Define used for IS_RCC_* macros below */ -#if defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if defined (STM32WBA54xx) || defined (STM32WBA55xx) #if !defined (STM32WBAXX_SI_CUT1_0) #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1 | \ RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SYSTICK | \ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smbus_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smbus_ex.h index 3447d277b..bf8ff2b2c 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smbus_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smbus_ex.h @@ -92,9 +92,9 @@ typedef struct * @{ */ #if defined(I2C1) -#define SMBUS_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 */ -#endif /* I2C1, I2C2 */ -#define SMBUS_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3, I2C4 */ +#define SMBUS_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ +#endif /* I2C1 */ +#define SMBUS_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ #if defined(SMBUS_TRIG_GRP1) #define SMBUS_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000U)) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim_ex.h index 2a13e1557..d4f95b7c9 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim_ex.h @@ -529,7 +529,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR8)))) #endif /* TIM3 */ -#if defined(TIM3) +#if defined(TIM3) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tsc.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tsc.h index 256362df2..39eacb4d9 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tsc.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tsc.h @@ -139,6 +139,9 @@ enum #if defined(TSC_IOCCR_G7_IO1) TSC_GROUP7_IDX, #endif /* TSC_IOCCR_G7_IO1 */ +#if defined(TSC_IOCCR_G8_IO1) + TSC_GROUP8_IDX, +#endif /* TSC_IOCCR_G8_IO1 */ TSC_NB_OF_GROUPS }; @@ -360,6 +363,9 @@ when the selected signal is detected on the SYNC input pin) */ #if defined(TSC_IOCCR_G7_IO1) #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) #endif /* TSC_IOCCR_G7_IO1 */ +#if defined(TSC_IOCCR_G8_IO1) +#define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) +#endif /* TSC_IOCCR_G8_IO1 */ #define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */ @@ -390,6 +396,13 @@ when the selected signal is detected on the SYNC input pin) */ #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ +#if defined(TSC_IOCCR_G6_IO3) +#define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ +#define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ +#else +#define TSC_GROUP6_IO3 TSC_GROUPX_NOT_SUPPORTED /*!< TSC Group6 IO3 not supported */ +#define TSC_GROUP6_IO4 TSC_GROUPX_NOT_SUPPORTED /*!< TSC Group6 IO4 not supported */ +#endif /* TSC_IOCCR_G6_IO3 */ #if defined(TSC_IOCCR_G7_IO1) #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ @@ -403,6 +416,19 @@ when the selected signal is detected on the SYNC input pin) */ #define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */ #define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */ #endif /* TSC_IOCCR_G7_IO1 */ +#if defined(TSC_IOCCR_G8_IO1) + +#define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ +#define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ +#define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ +#define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ +#else + +#define TSC_GROUP8_IO1 (uint32_t)(0x00000080UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ +#define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ +#define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ +#define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ +#endif /* TSC_IOCCR_G8_IO1 */ /** * @} */ @@ -711,7 +737,9 @@ when the selected signal is detected on the SYNC input pin) */ #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) -#define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\ + +#define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ + (((__VALUE__) == 0UL) ||\ (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ @@ -734,10 +762,17 @@ when the selected signal is detected on the SYNC input pin) */ (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ + (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ + (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ - (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4)) + (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ + (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ + (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ + (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ + (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) + /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_uart.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_uart.h index ba1294159..8bff8fe9c 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_uart.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_uart.h @@ -1231,7 +1231,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1246,8 +1246,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_usart.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_usart.h index 555a47bf1..0f9fdb883 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_usart.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_usart.h @@ -708,8 +708,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_bus.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_bus.h index 27c5bde17..1165674c3 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_bus.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_bus.h @@ -70,7 +70,9 @@ extern "C" { * @{ */ #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(GPDMA1) #define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN +#endif #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN @@ -134,7 +136,9 @@ extern "C" { #if defined(TIM3) #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN #endif /* TIM3 */ +#if defined(WWDG) #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN +#endif /* WWDG */ #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN #if defined(I2C1) #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN @@ -159,7 +163,9 @@ extern "C" { * @{ */ #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(TIM1) #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#endif /* TIM1 */ #if defined(SPI1) #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN #endif /* SPI1 */ @@ -207,7 +213,9 @@ extern "C" { */ /** * @brief Enable AHB1 peripherals clock. +#if defined(GPDMA1) * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n +#endif * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n @@ -216,10 +224,12 @@ extern "C" { * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 @@ -238,7 +248,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) /** * @brief Check if AHB1 peripheral clock is enabled or not - * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n +#if defined(GPDMA1) + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock +#endif * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n @@ -247,10 +259,12 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 @@ -265,7 +279,9 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) /** * @brief Disable AHB1 peripherals clock. - * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n +#if defined(GPDMA1) + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock +#endif * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n @@ -274,10 +290,12 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 @@ -292,15 +310,20 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) /** * @brief Force AHB1 peripherals reset. +#if defined(GPDMA1) * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ForceReset\n +#endif * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ForceReset\n * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @retval None */ @@ -311,15 +334,20 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) /** * @brief Release AHB1 peripherals reset. +#if defined(GPDMA1) * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n +#endif * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @retval None */ @@ -330,7 +358,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) /** * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes +#if defined(GPDMA1) * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n +#endif * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n @@ -339,10 +369,13 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 @@ -361,7 +394,9 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) /** * @brief Check if AHB1 peripheral clocks in Sleep and Stop modes is enabled or not +#if defined(GPDMA1) * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n +#endif * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n @@ -370,10 +405,13 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 @@ -388,7 +426,9 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) /** * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes +#if defined(GPDMA1) * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n +#endif * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n @@ -397,10 +437,13 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 +#if defined(GPDMA1) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 (*) +#endif + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 @@ -990,14 +1033,18 @@ __STATIC_INLINE void LL_AHB5_GRP1_DisableClockStopSleep(uint32_t Periphs) * @brief Enable APB1 peripherals clock. * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n +#if defined(WWDG) * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n +#endif * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +#if defined(WWDG) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * @@ -1034,14 +1081,18 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) * @brief Check if APB1 peripheral clock is enabled or not * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n +#if defined(WWDG) * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n +#endif * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +#if defined(WWDG) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * @@ -1077,7 +1128,9 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +#if defined(WWDG) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * @@ -1174,14 +1227,18 @@ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) * @brief Enable APB1 peripheral clocks in Sleep and Stop modes * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n +#if defined(WWDG) * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n +#endif * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +#if defined(WWDG) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * @@ -1201,14 +1258,18 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n +#if defined(WWDG) * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n +#endif * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +#if defined(WWDG) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * @@ -1224,14 +1285,18 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) * @brief Disable APB1 peripheral clocks in Sleep and Stop modes * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n +#if defined(WWDG) * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n +#endif * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +#if defined(WWDG) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG (*) +#endif * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) * diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_cortex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_cortex.h index edb4f86e1..aa1db7a06 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_cortex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_cortex.h @@ -106,10 +106,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control * @{ */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U -#define LL_MPU_CTRL_HARDFAULT_NMI 2U -#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U -#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -117,22 +117,28 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes * @{ */ -#define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ - -#define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ -#define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - -#define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */ -#define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - -#define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ -#define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ -#define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ -#define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/* Device memory attributes */ +#define LL_MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define LL_MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* Non-cacheable memory attribute */ +#define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ +#define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ +/* - transient mode attribute */ +#define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ +#define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ +/* - allocation attribute */ +#define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ +#define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ +#define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ +#define LL_MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ /** * @} */ @@ -149,8 +155,8 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access * @{ */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) -#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */ /** * @} */ @@ -158,9 +164,9 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable * @{ */ -#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */ +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */ +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */ /** * @} */ @@ -168,10 +174,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes * @{ */ -#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */ +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */ +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */ +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */ /** * @} */ @@ -793,9 +799,6 @@ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, u /* Set region index */ WRITE_REG(MPU->RNR, Region); - /* Set base address */ - MPU->RBAR |= Attributes; - /* Set region base address and region access attributes */ WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_hsem.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_hsem.h index 9f61e76ed..9f6923db6 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_hsem.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_hsem.h @@ -92,23 +92,7 @@ extern "C" { #define LL_HSEM_SEMAPHORE_13 HSEM_IER_ISE13 #define LL_HSEM_SEMAPHORE_14 HSEM_IER_ISE14 #define LL_HSEM_SEMAPHORE_15 HSEM_IER_ISE15 -#define LL_HSEM_SEMAPHORE_16 HSEM_IER_ISE16 -#define LL_HSEM_SEMAPHORE_17 HSEM_IER_ISE17 -#define LL_HSEM_SEMAPHORE_18 HSEM_IER_ISE18 -#define LL_HSEM_SEMAPHORE_19 HSEM_IER_ISE19 -#define LL_HSEM_SEMAPHORE_20 HSEM_IER_ISE20 -#define LL_HSEM_SEMAPHORE_21 HSEM_IER_ISE21 -#define LL_HSEM_SEMAPHORE_22 HSEM_IER_ISE22 -#define LL_HSEM_SEMAPHORE_23 HSEM_IER_ISE23 -#define LL_HSEM_SEMAPHORE_24 HSEM_IER_ISE24 -#define LL_HSEM_SEMAPHORE_25 HSEM_IER_ISE25 -#define LL_HSEM_SEMAPHORE_26 HSEM_IER_ISE26 -#define LL_HSEM_SEMAPHORE_27 HSEM_IER_ISE27 -#define LL_HSEM_SEMAPHORE_28 HSEM_IER_ISE28 -#define LL_HSEM_SEMAPHORE_29 HSEM_IER_ISE29 -#define LL_HSEM_SEMAPHORE_30 HSEM_IER_ISE30 -#define LL_HSEM_SEMAPHORE_31 HSEM_IER_ISE31 -#define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU +#define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU /** * @} */ @@ -361,7 +345,6 @@ __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uin * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -391,7 +374,6 @@ __STATIC_INLINE void LL_HSEM_SetSemaphoreSecure(HSEM_TypeDef *HSEMx, uint32_t Se * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -432,7 +414,6 @@ __STATIC_INLINE uint32_t LL_HSEM_GetSemaphoreSecure(const HSEM_TypeDef *HSEMx) * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -462,7 +443,6 @@ __STATIC_INLINE void LL_HSEM_SetSemaphorePrivilege(HSEM_TypeDef *HSEMx, uint32_t * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -512,22 +492,6 @@ __STATIC_INLINE uint32_t LL_HSEM_GetSemaphorePrivilege(const HSEM_TypeDef *HSEMx * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -561,22 +525,6 @@ __STATIC_INLINE void LL_HSEM_EnableIT_IER(HSEM_TypeDef *HSEMx, uint32_t Semaphor * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -610,22 +558,6 @@ __STATIC_INLINE void LL_HSEM_DisableIT_IER(HSEM_TypeDef *HSEMx, uint32_t Semapho * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ @@ -668,22 +600,6 @@ __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_IER(const HSEM_TypeDef *HSEMx, uint * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -717,22 +633,6 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_ICR(HSEM_TypeDef *HSEMx, uint32_t Semapho * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ @@ -766,22 +666,6 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_ISR(const HSEM_TypeDef *HSEMx, uin * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_i2c.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_i2c.h index 243499614..fec55e843 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_i2c.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_i2c.h @@ -356,9 +356,9 @@ typedef struct * @{ */ #if defined(I2C1) -#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 */ -#endif /* I2C1, I2C2 */ -#define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3, I2C4 */ +#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ +#endif /* I2C1 */ +#define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ #if defined(I2C_TRIG_GRP1) #define LL_I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U)) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rcc.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rcc.h index 1e7393e4c..766dc2055 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rcc.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rcc.h @@ -159,7 +159,9 @@ typedef struct #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software reset flag */ #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent watchdog reset flag */ +#if defined(WWDG) #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#endif /* defined(WWDG) */ #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-power reset flag */ /** * @} @@ -2927,6 +2929,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL); } +#if defined(WWDG) /** * @brief Check if RCC flag Window Watchdog reset is set or not. * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST @@ -2936,6 +2939,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) { return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL); } +#endif /* WWDG */ /** * @brief Check if RCC flag BOR reset is set or not. diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rng.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rng.h index 65bf8bf5d..fc4241354 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rng.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rng.h @@ -230,7 +230,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) { - CLEAR_BIT(RNGx->CR, RNG_CR_CED); + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -241,7 +242,8 @@ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) { - SET_BIT(RNGx->CR, RNG_CR_CED); + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -331,7 +333,7 @@ __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) { MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST); - CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);; + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -442,7 +444,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) { - MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, (Divider << RNG_CR_CLKDIV_Pos) | RNG_CR_CONDRST); + MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST); CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } @@ -672,6 +674,9 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) { +#if defined(RNG_HTCR_NIST_VALUE) + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ +#endif /* defined(RNG_HTCR_NIST_VALUE) */ WRITE_REG(RNGx->HTCR, HTCFG); } @@ -693,7 +698,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_system.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_system.h index 09aff21e0..151776369 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_system.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_system.h @@ -84,6 +84,17 @@ extern "C" { * @} */ +#ifdef SYSCFG_CCCSR_EN2 +/** @defgroup SYSTEM_LL_EC_CS2 SYSCFG SYSCFG VddIO2 compensation cell Code selection + * @{ + */ +#define LL_SYSCFG_VDDIO2_CELL_CODE 0U /*VDDIO2 I/Os code from the cell (available in the SYSCFG_CCVR)*/ +#define LL_SYSCFG_VDDIO2_REGISTER_CODE SYSCFG_CCCSR_CS2 /*VDDIO2 I/Os code from the SYSCFG compensation cell code register (SYSCFG_CCCR)*/ +/** + * @} + */ +#endif /* SYSCFG_CCCSR_EN2 */ + /** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE * @{ */ @@ -634,7 +645,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void) * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS1 bit of the - * SYSCFG_CMPCR is set + * SYSCFG_CCCSR is set * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode) @@ -654,10 +665,10 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void) /** * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD - * @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode + * @rmtoll CCCR NCC1 LL_SYSCFG_SetNMOSVddCompensationCode * @param NMOSCode NMOS compensation code - * This code is applied to the NMOS compensation cell when the CS2 bit of the - * SYSCFG_CMPCR is set + * This code is applied to the NMOS compensation cell when the CS1 bit of the + * SYSCFG_CCCSR is set * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode) @@ -730,7 +741,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void) */ __STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode) { - SET_BIT(SYSCFG->CCCSR, CompCode); + MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1, CompCode); } /** @@ -745,6 +756,145 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void) return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1)); } +#ifdef SYSCFG_CCCSR_EN2 +/** + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2 + * @rmtoll CCVR PCV2 LL_SYSCFG_GetPMOSVddIO2CompensationValue + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV2)); +} + +/** + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2 + * @rmtoll CCVR NCV2 LL_SYSCFG_GetNMOSVddIO2CompensationValue + * @retval Returned value is the NMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV2)); +} + + +/** + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2 + * @rmtoll CCCR PCC2 LL_SYSCFG_SetPMOSVddIO2CompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the PMOS compensation cell when the CS2 bit of the + * SYSCFG_CCCSR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC2, PMOSCode << SYSCFG_CCCR_PCC2_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2 + * @rmtoll CCCR PCC2 LL_SYSCFG_GetPMOSVddIO2CompensationCode + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC2)); +} + +/** + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2 + * @rmtoll CCCR NCC2 LL_SYSCFG_SetNMOSVddIO2CompensationCode + * @param NMOSCode NMOS compensation code + * This code is applied to the NMOS compensation cell when the CS2 bit of the + * SYSCFG_CCCSR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC2, NMOSCode << SYSCFG_CCCR_NCC2_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2 + * @rmtoll CCCR NCC2 LL_SYSCFG_GetNMOSVddIO2CompensationCode + * @retval Returned value is the VddIO2 compensation cell code for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC2)); +} + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2 + * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell + * @note The VddIO2 compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); +} + +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2 + * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell + * @note The VddIO2 compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); +} + +/** + * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enable + * @rmtoll CCCSR EN2 LL_SYSCFG_IsEnabled_VddIO2CompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2) == SYSCFG_CCCSR_EN2) ? 1UL : 0UL); +} + +/** + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2 + * @rmtoll CCCSR RDY2 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY2) == (SYSCFG_CCCSR_RDY2)) ? 1UL : 0UL); +} + +/** + * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2 + * @rmtoll CCCSR CS2 LL_SYSCFG_SetVddIO2CellCompensationCode + * @param CompCode: Selects the code to be applied for the VddIO2 compensation cell + * This parameter can be one of the following values: + * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode) +{ + MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2, CompCode); +} + +/** + * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2 + * @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIO2CellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2)); +} +#endif /* SYSCFG_CCCSR_EN2 */ + /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_tim.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_tim.h index b54be94dd..6f7c5aff8 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_tim.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_tim.h @@ -6098,7 +6098,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T * @} */ -#endif /* TIM1 || TIM2 || TIM3 || TIM6 || TIM7 */ +#endif /* TIM1 || TIM2 || TIM3 || TIM16 || TIM17 */ /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_utils.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_utils.h index 3e99dc55c..a70265baf 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_utils.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_utils.h @@ -157,12 +157,11 @@ typedef struct /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE * @{ */ -#define LL_UTILS_PACKAGETYPE_UQFN32 0x00000000U /*!< UQFN32 package type */ -#define LL_UTILS_PACKAGETYPE_UQFN48 0x00000001U /*!< UQFN48 package type */ -#define LL_UTILS_PACKAGETYPE_BGA59 0x00000002U /*!< BGA59 package type */ -#define LL_UTILS_PACKAGETYPE_UQFN32_SMPS 0x00000003U /*!< UQFN32 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UQFN48_SMPS 0x00000004U /*!< UQFN48 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_BGA59_SMPS 0x00000005U /*!< BGA59 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000000U /*!< UFQFPN32 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x00000002U /*!< UFQFPN48 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP41_SMPS 0x00000009U /*!< WLCSP41 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS 0x0000000AU /*!< UFQFPN48 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA59 0x0000000BU /*!< UFBGA59 package type */ /** * @} */ @@ -223,12 +222,11 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) /** * @brief Get Package type * @retval Returned value can be one of the following values: - * @arg @ref LL_UTILS_PACKAGETYPE_UQFN32 - * @arg @ref LL_UTILS_PACKAGETYPE_UQFN48 - * @arg @ref LL_UTILS_PACKAGETYPE_BGA59 - * @arg @ref LL_UTILS_PACKAGETYPE_UQFN32_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_UQFN48_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_BGA59_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32 + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP41_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA59 */ __STATIC_INLINE uint32_t LL_GetPackageType(void) { diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal.c index 1d5b8c19c..e6e673641 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal.c @@ -48,6 +48,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -559,6 +560,16 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void) =============================================================================== [..] This section provides functions allowing to: (+) Enable/Disable the I/O analog switch voltage booster + (+) Configure the Voltage reference buffer + (+) Enable/Disable the Voltage reference buffer + (+) Enable/Disbale the OTG PHY + (+) Configure the OTG PHY power down + (+) Select the OTG PHY reference clock + (+) Configure the OTG PHY disconnect/squelch threshold + (+) Configure the OTG PHY transmitter pre-emphasis current + (+) Enable/Disable the compensation cell + (+) Get the compensation cell ready status + (+) Configure/Get the code selection for the compensation cell @endverbatim * @{ @@ -571,7 +582,7 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void) */ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) { - SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); + MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_BOOSTEN | SYSCFG_CFGR1_ANASWVDD), SYSCFG_CFGR1_BOOSTEN); } /** @@ -584,6 +595,237 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } +/** + * @brief Enable the I/O analog switch supplied by VDD + * @note To be used when I/O analog switch voltage booster is not enabled + * @retval None + */ +void HAL_SYSCFG_EnableIOAnalogSwitchVdd(void) +{ + MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_BOOSTEN | SYSCFG_CFGR1_ANASWVDD), SYSCFG_CFGR1_ANASWVDD); +} + +/** + * @brief Disable the I/O analog switch supplied by VDD + * @retval None + */ +void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); +} + + +#ifdef SYSCFG_OTGHSPHYCR_EN +/** + * @brief Enable the OTG PHY . + * @param OTGPHYConfig Defines the OTG PHY configuration. + This parameter can be one of @ref SYSCFG_OTG_PHY_Enable + * @retval None + */ +void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_CONFIG(OTGPHYConfig)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN, OTGPHYConfig); +} + +/** + * @brief Set the OTG PHY Power Down config. + * @param PowerDownConfig Defines the OTG PHY Power down configuration. + This parameter can be one of @ref SYSCFG_OTG_PHY_PowerDown + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(PowerDownConfig)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL, PowerDownConfig); +} + +/** + * @brief Set the OTG PHY reference clock selection. + * @param RefClkSelection Defines the OTG PHY reference clock selection. + This parameter can be one of the @ref SYSCFG_OTG_PHY_RefenceClockSelection + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(RefClkSelection)); + + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, RefClkSelection); +} + +/** + * @brief Set the OTG PHY Disconnect Threshold. + * @param DisconnectThreshold Defines the voltage level for the threshold used to detect a disconnect event. + This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_DisconnectThreshold + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_DISCONNECT(DisconnectThreshold)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold); +} + +/** + * @brief Set the OTG PHY Squelch Threshold. + * @param SquelchThreshold Defines the voltage level. + This parameter can be onez of the @ref SYSCFG_OTG_PHYTUNER_SquelchThreshold + + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_SQUELCH(SquelchThreshold)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold); +} + +/** + * @brief Set the OTG PHY transmitter pre-emphasis current. + * @param PreemphasisCurrent Defines the current configuration. + This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_PreemphasisCurrent + + * @retval None + */ +void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_OTGPHY_PREEMPHASIS(PreemphasisCurrent)); + + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent); +} +#endif /* SYSCFG_OTGHSPHYCR_EN */ + +/** + * @brief Enable the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can the combination of the following values: + * @arg SYSCFG_IO_CELL Compensation cell for the VDD I/O power rail + * @arg SYSCFG_IO2_CELL Compensation cell for the VDDIO2 I/O power rail + * @retval None + */ +void HAL_SYSCFG_EnableCompensationCell(uint32_t Selection) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection)); + + SET_BIT(SYSCFG->CCCSR, Selection); +} + +/** + * @brief Disable the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can the combination of the following values: + * @arg SYSCFG_IO_CELL Compensation cell for the VDD I/O power rail + * @arg SYSCFG_IO2_CELL Compensation cell for the VDDIO2 I/O power rail + * @retval None + */ +void HAL_SYSCFG_DisableCompensationCell(uint32_t Selection) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection)); + + MODIFY_REG(SYSCFG->CCCSR, Selection, 0U); +} + +/** + * @brief Get the compensation cell ready status + * @param Selection specifies the concerned compensation cell + * This parameter can one of the following values: + * @arg SYSCFG_IO_CELL_READY Compensation cell for the VDD I/O power rail + * @arg SYSCFG_IO2_CELL_READY Compensation cell for the VDDIO2 I/O power rail + * @retval Ready status (1 or 0) + */ +uint32_t HAL_SYSCFG_GetCompensationCellReadyStatus(uint32_t Selection) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_COMPENSATION_CELL_READY(Selection)); + + return (((SYSCFG->CCCSR & Selection) == 0U) ? 0UL : 1UL); +} + +/** + * @brief Configure the code selection for the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can one of the following values: + * @arg SYSCFG_IO_CELL Compensation cell for the VDD I/O power rail + * @arg SYSCFG_IO2_CELL Compensation cell for the VDDIO2 I/O power rail + * @param Code code selection to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_CCVR) + * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register (SYSCFG_CCCR) + * @param NmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Nmos value + * to apply in range 0 to 15 else this parameter is not used + * @param PmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Pmos value + * to apply in range 0 to 15 else this parameter is not used + * @retval None + */ +void HAL_SYSCFG_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue, uint32_t PmosValue) +{ + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection)); + assert_param(IS_SYSCFG_COMPENSATION_CELL_CODE(Code)); + + if (Code == SYSCFG_IO_REGISTER_CODE) + { + /* Check the parameters */ + assert_param(IS_SYSCFG_COMPENSATION_CELL_NMOS_VALUE(NmosValue)); + assert_param(IS_SYSCFG_COMPENSATION_CELL_PMOS_VALUE(PmosValue)); + + offset = ((Selection == SYSCFG_IO_CELL) ? 0U : 8U); + + MODIFY_REG(SYSCFG->CCCR, (0xFFU << offset), ((NmosValue << offset) | (PmosValue << (offset + 4U)))); + } + + MODIFY_REG(SYSCFG->CCCSR, (Selection << 1U), (Code << (POSITION_VAL(Selection) + 1U))); +} + +/** + * @brief Get the code selection for the compensation cell + * @param Selection specifies the concerned compensation cell + * This parameter can one of the following values: + * @arg SYSCFG_IO_CELL Compensation cell for the VDD I/O power rail + * @arg SYSCFG_IO2_CELL Compensation cell for the VDDIO2 I/O power rail + * @param pCode pointer code selection + * This parameter can be one of the following values: + * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_CCVR) + * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register (SYSCFG_CCCR) + * @param pNmosValue pointer to the Nmos value in range 0 to 15 + * @param pPmosValue pointer to the Pmos value in range 0 to 15 + * @retval HAL_OK (all values available) or HAL_ERROR (check parameters) + */ +HAL_StatusTypeDef HAL_SYSCFG_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue, + uint32_t *pPmosValue) +{ + uint32_t reg; + uint32_t offset; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check parameters */ + if ((pCode != NULL) && (pNmosValue != NULL) && (pPmosValue != NULL)) + { + *pCode = ((SYSCFG->CCCSR & (Selection << 1U)) == 0U) ? SYSCFG_IO_CELL_CODE : SYSCFG_IO_REGISTER_CODE; + + reg = (*pCode == SYSCFG_IO_CELL_CODE) ? (SYSCFG->CCVR) : (SYSCFG->CCCR); + offset = ((Selection == SYSCFG_IO_CELL) ? 0U : 8U); + + *pNmosValue = ((reg >> offset) & 0xFU); + *pPmosValue = ((reg >> (offset + 4U)) & 0xFU); + + status = HAL_OK; + } + return status; +} + /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cortex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cortex.c index cfad3c53e..c8654c2d8 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cortex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cortex.c @@ -48,25 +48,44 @@ [..] Setup SysTick Timer for time base. - (+) The SysTick clock source shall be configured with HAL_SYSTICK_CLKSourceConfig(). + (+) The SysTick clock source shall be configured with HAL_SYSTICK_CLKSourceConfig(). - (+) The SysTick IRQ priority shall be configured with HAL_NVIC_SetPriority(SysTick_IRQn,...). - The HAL_NVIC_SetPriority() calls the CMSIS NVIC_SetPriority() function. + (+) The SysTick IRQ priority shall be configured with HAL_NVIC_SetPriority(SysTick_IRQn,...). + The HAL_NVIC_SetPriority() calls the CMSIS NVIC_SetPriority() function. - (+) The HAL_SYSTICK_Config() function: + (+) The HAL_SYSTICK_Config() function: (++) Configures the SysTick Reload register with the value passed as function parameter. (++) Resets the SysTick Counter register. (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. - (+) To adjust the SysTick time base, use the following formula: + (+) To adjust the SysTick time base, use the following formula: - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF - (+) In case the HAL time base is the SysTick Timer, the HAL time base configuration must be completed - by calling the HAL_InitTick() function. + (+) In case the HAL time base is the SysTick Timer, the HAL time base configuration must be completed + by calling the HAL_InitTick() function. + + [..] + *** How to configure MPU regions using CORTEX HAL driver *** + ============================================================ + [..] + This section provides functions allowing to configure the Memory Protection Unit (MPU). + + (#) Disable the MPU using HAL_MPU_Disable(). + (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes(). + (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration link to + the right MPU attributes number. + (#) Enable the MPU using HAL_MPU_Enable() function. + + -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter the memory + management fault handler MemManage_Handler() when an illegal memory access is performed. + -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region configuration + from affecting the new MPU configuration. + -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the secure context + and the same sequence as above applies to configure the non-secure MPU. @endverbatim ****************************************************************************** diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_crc.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_crc.c index f5c7641f6..1e4fb3d82 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_crc.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_crc.c @@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) __HAL_CRC_DR_RESET(hcrc); /* Reset IDR register content */ - CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + CLEAR_REG(hcrc->Instance->IDR); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_crc_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_crc_ex.c index 3678b1b5c..ce816079c 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_crc_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gtzc.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gtzc.c index ae65a395a..c0cf9910f 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gtzc.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gtzc.c @@ -560,12 +560,14 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, mpcbb_ptr = GTZC_MPCBB2; mem_size = GTZC_MEM_SIZE(SRAM2); } +#if defined(GTZC_MPCBB6) else { /* Here MemBaseAddress is inside SRAM6 (parameter already checked) */ mpcbb_ptr = GTZC_MPCBB6; mem_size = GTZC_MEM_SIZE(SRAM6); } +#endif /* GTZC_MPCBB6 */ /* translate mem_size in number of super-blocks */ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); @@ -631,11 +633,13 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, mpcbb_ptr = GTZC_MPCBB2; mem_size = GTZC_MEM_SIZE(SRAM2); } +#if defined(GTZC_MPCBB6) else { mpcbb_ptr = GTZC_MPCBB6; mem_size = GTZC_MEM_SIZE(SRAM6); } +#endif /* GTZC_MPCBB6 */ /* translate mem_size in number of super-blocks */ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); @@ -725,6 +729,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, base_address = SRAM2_BASE_S; } #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined(GTZC_MPCBB6) else if (((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM6, end_address))) != 0U) { @@ -739,6 +744,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, base_address = SRAM6_BASE_S; } #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -870,6 +876,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, base_address = SRAM2_BASE_S; } #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined(GTZC_MPCBB6) else if ((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM6, end_address))) { @@ -884,6 +891,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, base_address = SRAM6_BASE_S; } #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -963,6 +971,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCK; } +#if defined(GTZC_MPCBB6) else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) && (IS_ADDRESS_IN(SRAM6, (MemAddress + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) @@ -972,6 +981,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, /* limitation: code not portable with memory > 512K */ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCK; } +#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -1056,6 +1066,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, /* limitation: code not portable with memory > 512K */ reg_mpcbb = GTZC_MPCBB2_S->CFGLOCK; } +#if defined(GTZC_MPCBB6) else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) && (IS_ADDRESS_IN(SRAM6, (MemAddress + (NbSuperBlocks @@ -1066,6 +1077,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, /* limitation: code not portable with memory > 512K */ reg_mpcbb = GTZC_MPCBB6_S->CFGLOCK; } +#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -1102,10 +1114,12 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress) { SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#if defined(GTZC_MPCBB6) else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) { SET_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -1132,10 +1146,12 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, { *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#if defined(GTZC_MPCBB6) else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) { *pLockState = READ_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); } +#endif /* GTZC_MPCBB6 */ else { return HAL_ERROR; @@ -1287,7 +1303,7 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag) } reg_value = READ_REG(GTZC_TZIC->SR4); - for (i = 96U; i < 128U; i++) + for (i = 96U; i < GTZC_TZIC_PERIPH_NUMBER; i++) { pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U); } diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rcc_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rcc_ex.c index 53076faf4..eb5248f48 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rcc_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rcc_ex.c @@ -239,6 +239,20 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *Peri /* Configure the AS clock source */ __HAL_RCC_AUDIOSYNC_CONFIG(PeriphClkInit->AudioSyncClockSelection); + + if (PeriphClkInit->AudioSyncClockSelection == RCC_ASCLKSOURCE_PLL1P) + { + /* Enable PLL1 PCLK output */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_PCLK); + } + else if (PeriphClkInit->AudioSyncClockSelection == RCC_ASCLKSOURCE_PLL1Q) + { + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_QCLK); + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } } #endif @@ -340,15 +354,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *Peri /* Check if a backup domain reset is required */ if (tmpreg2 != RCC_RTCCLKSOURCE_DISABLE) { +#if defined(RCC_LSI2_SUPPORT) /* Save BDCR2 content */ tmpreg2 = RCC->BDCR2; - +#endif /* RCC_LSI2_SUPPORT */ /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); __HAL_RCC_BACKUPRESET_RELEASE(); - +#if defined(RCC_LSI2_SUPPORT) /* Restore previously saved BDCR2 */ RCC->BDCR2 = tmpreg2; +#endif /* RCC_LSI2_SUPPORT */ } /* Apply new RTC clock source selection */ @@ -627,6 +643,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) + #if defined(LPTIM2) case RCC_PERIPHCLK_LPTIM2: /* Get the current LPTIM2 source */ diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rng.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rng.c index de09cc24a..f3e8864fc 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rng.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rng.c @@ -200,6 +200,14 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST | RNG_CR_RNG_CONFIG2, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST | (1U << RNG_CR_RNG_CONFIG2_Pos)); +#if defined(RNG_CR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE); +#endif /* defined(RNG_CR_NIST_VALUE) */ +#if defined(RNG_HTCR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); +#endif /* defined(RNG_HTCR_NIST_VALUE) */ /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -234,12 +242,12 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Get tick */ tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ - while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { hrng->State = HAL_RNG_STATE_ERROR; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; @@ -675,8 +683,6 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Update the error code and status */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; status = HAL_ERROR; - /* Clear bit DRDY */ - CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY); } else /* No seed error */ { diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart.c index e0e87bfde..9d21bba41 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart.c @@ -2525,6 +2525,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -4599,6 +4621,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4763,6 +4786,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart_ex.c index b0114e203..49d92c7e2 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart_ex.c @@ -555,7 +555,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_usart.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_usart.c index 284d76912..ca4a40eba 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_usart.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_usart.c @@ -144,7 +144,7 @@ */ /** @defgroup USART USART - * @brief HAL USART Synchronous module driver + * @brief HAL USART Synchronous SPI module driver * @{ */ @@ -227,8 +227,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit @@ -240,7 +240,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous SPI configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -318,7 +318,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) return HAL_ERROR; } - /* In Synchronous mode, the following bits must be kept cleared: + /* In Synchronous SPI mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ @@ -659,11 +659,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI data transfers. - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). [..] @@ -3150,7 +3149,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_usart_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_usart_ex.c index c8409a170..1543f347c 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_usart_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_usart_ex.c @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) /* Disable USART */ __HAL_USART_DISABLE(husart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_exti.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_exti.c index 03c72fe75..236bd1e39 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_exti.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_exti.c @@ -91,14 +91,6 @@ ErrorStatus LL_EXTI_DeInit(void) /* Pending register set to default reset values */ LL_EXTI_WriteReg(RPR1, 0xFFFFFFFFU); LL_EXTI_WriteReg(FPR1, 0xFFFFFFFFU); -#if defined(EXTI_PRIVCFGR1_PRIV0) - /* Privilege register set to default reset values */ - LL_EXTI_WriteReg(PRIVCFGR1, 0x00000000U); -#endif /* EXTI_PRIVCFGR1_PRIV0 */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Secure register set to default reset values */ - LL_EXTI_WriteReg(SECCFGR1, 0x00000000U); -#endif /* __ARM_FEATURE_CMSE */ return SUCCESS; } diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rcc.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rcc.c index 7d95afada..e4c6221b5 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rcc.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rcc.c @@ -557,7 +557,7 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) { case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ #if defined(RCC_LSI2_SUPPORT) - if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) + if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) #else if (LL_RCC_LSI1_IsReady() != 0U) #endif @@ -597,7 +597,7 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) { case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */ #if defined(RCC_LSI2_SUPPORT) - if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) + if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) #else if (LL_RCC_LSI1_IsReady() != 0U) #endif @@ -733,7 +733,7 @@ uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) case LL_RCC_RNG_CLKSOURCE_LSI: /* LSI clock used as RNG clock source */ #if defined(RCC_LSI2_SUPPORT) - if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) + if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) #else if (LL_RCC_LSI1_IsReady() != 0U) #endif diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rng.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rng.c index 9bddf5283..5ab9f795e 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rng.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rng.c @@ -110,7 +110,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content * - ERROR: not applicable */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_tim.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_tim.c index e448b26da..a7f913879 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_tim.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_tim.c @@ -1337,7 +1337,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM * @} */ -#endif /* TIM1 || TIM2 || TIM3 || TIM6 || TIM7 */ +#endif /* TIM1 || TIM2 || TIM3 || TIM16 || TIM17 */ /** * @} diff --git a/stm32cube/stm32wbaxx/release_note.html b/stm32cube/stm32wbaxx/release_note.html index d060ba4ea..2d5ad1ae5 100644 --- a/stm32cube/stm32wbaxx/release_note.html +++ b/stm32cube/stm32wbaxx/release_note.html @@ -52,7 +52,7 @@

Purpose

For quick getting started with the STM32CubeWBA firmware package, you can refer to UM3131 and download firmware updates and all the latest documentation from www.st.com/stm32cubefw

Here is the list of references to user documents:

    -
  • UM3131: Getting started with STM32CubeWBA for STM32WBA Series
    • +
  • UM3131: Getting started with STM32CubeWBA for STM32WBA Series
  • AN5928: How to build a short range wireless application with STM32WBA MCUs
  • UM3140: Description of STM32WBAxx HAL and LL drivers
  • AN5929: STM32Cube MCU Package examples for STM32WBA series
    • @@ -63,17 +63,862 @@

    Purpose

    Update History

    - +

    Main Changes

    +

    Patch Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

    +


    +

    +

    Patch Release for Security, BLE, 802.15.4, Thread and Zigbee.

    +

    This patch release has to be applied on top of v1.4.0 release

    +


    +

    +

    Connectivity

    +

    Introduction of the following new features:

    +
      +

    • Productive PHY settings including AoA/AoD support.

      • +

    • WIFI Packet Traffic Arbiter (via PTACONV) support on 802.15.4 applications.

      • +
    +


    +

    +

    Contents

    +
      +
    • Projects updates +
        +
      • NUCLEO-WBA55CG +
          +
        • Update Applications demonstrating BLE capabilities
          • +
        • Update Applications demonstrating Zigbee capabilities
          • +
        • Update Applications demonstrating Thread capabilities
          • +
        • Update Applications demonstrating MAC and PHY capabilities
          • +
        • Add new application demonstrating Thread capabilities +
            +
          • Thread_Udp
            +
            • +
          • +
        • +
      • NUCLEO-WBA52CG +
          +
        • None
          +
          • +
        • +
      • STM32WBA55G-DK1 +
          +
        • Update applications demonstrating BLE, Zigbee capabilities
          +
          • +
        • +
      • +
    +

    Projects

    +
      +
    • The STM32CubeWBA Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.
      • +
    • The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).
      • +
    • The STM32CubeWBA Firmware offers full scope of Examples & Applications targeted, developed using STM32CubeMx and ported on 3 toolchains.
      • +
    + + + + + + + + + + + + + + + +
    NameVersionRelease notes
    ProjectsV1.4.1 release notes
    +


    +

    +

    Components

    +

    The components flagged by “” have changed since the previous release. “” are new.

    +


    +

    +

    Drivers

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    NameVersionRelease notes
    CMSISV5.9.0release notes
    STM32WBAxx CMSISV1.4.0release notes
    STM32WBAxx_HAL_DriverV1.4.0release notes
    +


    +

    +

    BSP Drivers

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NameVersionRelease notes
    STM32WBAxx_NucleoV1.0.2release notes
    STM32WBA55G-DK1V1.0.0release notes
    CommonV7.2.1release notes
    cs42l51V2.0.7release notes
    ssd1315V2.1.0release notes
    +


    +

    +

    Middlewares

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NameVersionRelease notes
    STM32_WPANV2.4.1.2 release notes
    mbed-cryptoV2.28.8release notes
    ST release notes
    mcubootV1.7.2.24ST release notes
    trustedfirmwareV1.3.0.12release notes
    ST release notes
    STM32 TouchSensing LibraryV2.2.11release notes
    STM32 OpenBootloaderV6.1.0release notes
    ThreadXV6.2.1release notes
    ST modified 221223ST release notes
    NetXduoV6.2.0release notes
    ST modified 221223ST release notes
    LevelXV6.2.0release notes
    ST modified 221223ST release notes
    FileXV6.2.0release notes
    ST modified 221223ST release notes
    USBXV6.2.0release notes
    ST modified 221223ST release notes
    CMSIS RTOS ThreadXV1.2.0release notes
    STM32_Audio PDMV3.4.0release notes
    +


    +

    +

    Utilities

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NameVersionRelease note
    CPUV1.1.3release notes
    FontsV2.0.4release notes
    confV1.6.1release notes
    tiny_lpmV1.4.2release notes
    sequencerV1.7.0release notes
    LCDV2.0.3release notes
    Lcd_TraceV2.0.2release notes
    adv_traceV1.3.0release notes
    miscV1.1.1release notes
    tim_servV1.3.1release notes
    +


    +

    +

    Development Toolchains and Compilers

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    Toolchain + ST-LinkVersionPatch (if available)
    IAR Embedded Workbench for ARM (EWARM)V9.20.1Patch EWARM
    RealView Microcontroller Development Kit (MDK-ARM)V5.38Patch MDK-ARM
    STM32CubeIDE V1.15.1 (GCC12)V1.15.1
    +
      +
    • Support of ARM Compiler 6 (AC-5 like warnings) for HAL/LL/BSP drivers and STMicroelectronics Middleware components
      • +
    +


    +

    +

    Supported Devices and boards

    +
      +
    • STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices
      • +
    • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
      • +
    +


    +

    +

    Known Limitations

    +
      +
    • External PA (+20dbm) is not supported.
      • +
    • LSI2 is not supported.
      • +
    • BLE Applications: +
        +
      • Applications based on ThreadX do not currently support Standby mode.
        • +
      • +
    • BLE Audio applications: +
        +
      • Codec Capability Settings 48_6, specified as Mandatory in TMAP, is only supported with one Channel per CIS.
        • +
      • +
    • Zigbee Applications: +
        +
      • Applications based on ThreadX do not currently support Standby mode.
        • +
      • +
    • ICache IP is not informed of the powering down of the SRAM when going to stop1 low power mode, as a consequence ICache configuration for stop mode has to be set to full retention.
      • +
    +


    +

    +

    Dependencies

    +
      +
    • STM32CubeMX V6.12.0 +
        +
      • Projects (Applications and Examples) are generated using STM32CubeMX version V6.12.0.
        • +
      • +
    +


    +

    +

    Backward compatibility

    +
      +
    • Connectivity applications are available for NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
      • +
    • Connectivity applications are not supported on this release for NUCLEO-WBA52CG board
      • +
    +


    +

    +

    Notes

    +
      +
    • None
      • +
    +


    +

    +
    +
    +
    + +
    +

    Main Changes

    +

    Official Release of STM32CubeWBA Firmware package supporting STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices

    +


    +

    +

    Official Release for Security, BLE, 802.15.4, Thread and Zigbee.

    +


    +

    +

    Security

    +

    Introduction of the following new features:

    +
      +

    • Imgtool in STM32CubeProgrammer

      • +

    • AppliCfg script

      • +
    +

    Update of the following features:

    +
      +

    • mbed-crypto for security improvements

      • +

    • mcuboot for security improvements

      • +

    • TrustedFirmware for security improvements

      • +
    +


    +

    +

    Connectivity

    +

    Introduction of the following new features:

    +
      +

    • STM32WBA50xx is now supported.

      • +

    • 802.15.4 Antenna Diversity.

      • +

    • BLE Audio Hearing Access Profile support added.

      • +

    • Applications based on ThreadX are delivered on MDK-ARM (Keil) toolchain.

      • +

    • WIFI PTA(via PTACONV) support on BLE applications.

      • +

    • Adding of new Zigbee Applications (including NVM and OTA)

      • +

    • Adding of two new BLE stack configurations: Basic Plus and Peripheral Only

      • +

    • Adding of BLE wrapper : pre and post command handling

      • +

    • A new command ACI_HAL_EAD_ENCRYPT_DECRYPT is added to ease implementation of Encrypted Advertising Data feature.

      • +

    • 802.15.4 Long term robustness improvement

      • +
    +


    +

    +

    Contents

    +
      +
    • CMSIS Devices Drivers updates +
        +
      • Support of STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices
        • +
      • Update CMSIS devices to include latest corrections
        • +
      • +
    • HAL/LL Drivers updates +
        +
      • HAL and LL drivers are available for all peripherals: +
          +
        • HAL: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
          • +
        • LL: ADC, COMP, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
          • +
        • +
      • Update HAL/LL drivers to include latest corrections
        • +
      • +
    • BSP Drivers +
        +
      • Update STM32WBAxx_Nucleo BSP drivers to include latest corrections
        • +
      • +
    +


    +

    +
      +
    • Projects updates +
        +
      • NUCLEO-WBA55CG +
          +
        • Update Applications demonstrating BLE capabilities
          • +
        • Update Applications demonstrating Zigbee capabilities
          • +
        • Update Applications demonstrating Thread capabilities
          • +
        • +
      • NUCLEO-WBA52CG +
          +
        • Update Applications demonstrating SBSFU/TFM capabilities
          • +
        • +
      • STM32WBA55G-DK1 +
          +
        • Update applications demonstrating BLE, Zigbee capabilities
          +
          • +
        • +
      • +
    +

    Projects

    +
      +
    • The STM32CubeWBA Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.
      • +
    • The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).
      • +
    • The STM32CubeWBA Firmware offers full scope of Examples & Applications targeted, developed using STM32CubeMx and ported on 3 toolchains.
      • +
    + + + + + + + + + + + + + + + +
    NameVersionRelease notes
    ProjectsV1.4.0 release notes
    +


    +

    +

    Components

    +

    The components flagged by “” have changed since the previous release. “” are new.

    +


    +

    +

    Drivers

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    NameVersionRelease notes
    CMSISV5.9.0release notes
    STM32WBAxx CMSISV1.4.0 release notes
    STM32WBAxx_HAL_DriverV1.4.0 release notes
    +


    +

    +

    BSP Drivers

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NameVersionRelease notes
    STM32WBAxx_NucleoV1.0.2release notes
    STM32WBA55G-DK1V1.0.0release notes
    CommonV7.2.1release notes
    cs42l51V2.0.7release notes
    ssd1315V2.1.0release notes
    +


    +

    +

    Middlewares

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NameVersionRelease notes
    STM32_WPANV2.4.0.5 release notes
    mbed-cryptoV2.28.8 release notes
    ST release notes
    mcubootV1.7.2.24 ST release notes
    trustedfirmwareV1.3.0.12 release notes
    ST release notes
    STM32 TouchSensing LibraryV2.2.11release notes
    STM32 OpenBootloaderV6.1.0release notes
    ThreadXV6.2.1release notes
    ST modified 221223ST release notes
    NetXduoV6.2.0release notes
    ST modified 221223ST release notes
    LevelXV6.2.0release notes
    ST modified 221223ST release notes
    FileXV6.2.0release notes
    ST modified 221223ST release notes
    USBXV6.2.0release notes
    ST modified 221223ST release notes
    CMSIS RTOS ThreadXV1.2.0release notes
    STM32_Audio PDMV3.4.0release notes
    +


    +

    +

    Utilities

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NameVersionRelease note
    CPUV1.1.3release notes
    FontsV2.0.4release notes
    confV1.6.1release notes
    tiny_lpmV1.4.2release notes
    sequencerV1.7.0release notes
    LCDV2.0.3release notes
    Lcd_TraceV2.0.2release notes
    adv_traceV1.3.0release notes
    miscV1.1.1release notes
    tim_servV1.3.1release notes
    +


    +

    +

    Development Toolchains and Compilers

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    Toolchain + ST-LinkVersionPatch (if available)
    IAR Embedded Workbench for ARM (EWARM)V9.20.1Patch EWARM
    RealView Microcontroller Development Kit (MDK-ARM)V5.38Patch MDK-ARM
    STM32CubeIDE V1.15.1 (GCC12)V1.15.1
    +
      +
    • Support of ARM Compiler 6 (AC-5 like warnings) for HAL/LL/BSP drivers and STMicroelectronics Middleware components
      • +
    +


    +

    +

    Supported Devices and boards

    +
      +
    • STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx devices
      • +
    • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
      • +
    +


    +

    +

    Known Limitations

    +
      +
    • External PA (+20dbm) is not supported.
      • +
    • LSI2 is not supported.
      • +
    • AoA/AoD is not supported.
      • +
    • BLE Applications: +
        +
      • Applications based on ThreadX do not currently support Standby mode.
        • +
      • +
    • BLE Audio applications: +
        +
      • Codec Capability Settings 48_6, specified as Mandatory in TMAP, is only supported with one Channel per CIS.
        • +
      • +
    • Zigbee Applications: +
        +
      • Applications based on ThreadX do not currently support Standby mode.
        • +
      • +
    • PTA not supported for 802.15.4 applications.
      • +
    +


    +

    +

    Dependencies

    +
      +
    • STM32CubeMX V6.12.0 +
        +
      • Projects (Applications and Examples) are generated using STM32CubeMX version V6.12.0.
        • +
      • +
    +


    +

    +

    Backward compatibility

    +
      +
    • Connectivity applications are available for NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
      • +
    • Connectivity applications are not supported on this release for NUCLEO-WBA52CG board
      • +
    +


    +

    +

    Notes

    +
      +
    • None
      • +
    +


    +

    +
    +
    +
    + +
    +

    Main Changes

    Official Patch Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices


    -

    Patch Release for Security, BLE, 802.15.4, Thread and Zigbee.

    +

    Patch Release for Security, BLE, 802.15.4, Thread and Zigbee.


    -

    Connectivity

    -

    Introduction of the following new features:

    +

    Connectivity

    +

    Introduction of the following new features:

    • Productive RF-PHY settings.
    • Zigbee: @@ -82,7 +927,7 @@

      Introduction of the followin

-

Contents

+

Contents

  • Middlewares Third Party updates
      @@ -105,7 +950,7 @@

      Contents


    -

    Projects

    +

    Projects

    • The STM32CubeWBA Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.
    • The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).
      • @@ -129,7 +974,7 @@

      Projects


      -

      Components

      +

      Components

      The components flagged by “” have changed since the previous release. “” are new.


      @@ -384,7 +1229,7 @@

      Components


      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      @@ -416,14 +1261,14 @@

      Development Toolchains and Compile


      -

      Supported Devices and boards

      +

      Supported Devices and boards

      • STM32WBA52xx and STM32WBA55xx devices
      • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards


      -

      Known Limitations

      +

      Known Limitations

      • External PA (+20dbm) is not supported.
      • LSI2 is not supported.
        • @@ -450,7 +1295,7 @@

        Known Limitations


      -

      Dependencies

      +

      Dependencies

      • STM32CubeMX V6.11.0
          @@ -459,14 +1304,14 @@

          Dependencies


        -

        Backward compatibility

        +

        Backward compatibility

        • Connectivity applications are available for NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
        • Connectivity applications are not supported on this release for NUCLEO-WBA52CG board


        -

        Notes

        +

        Notes

        • None
        @@ -477,12 +1322,12 @@

        Notes

        -

        Main Changes

        +

        Main Changes

        Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices


        -

        Connectivity

        -

        Introduction of the following new features:

        +

        Connectivity

        +

        Introduction of the following new features:

        • Adding support of BLE/Thread and BLE/Zigbee Concurrent Modes.
        • Bluetooth Low Energy new features : @@ -511,7 +1356,7 @@

          Introduction of the follow
        • Applications: BLE and Zigbee project are now supporting SMPS power supply by default.

        -

        Contents

        +

        Contents

        • CMSIS Devices Drivers updates
            @@ -562,7 +1407,7 @@

            Contents


          -

          Projects

          +

          Projects

          • The STM32CubeWBA Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.
          • The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).
            • @@ -586,7 +1431,7 @@

            Projects


      -

      Components

      +

      Components

      The components flagged by “” have changed since the previous release. “” are new.


      @@ -841,7 +1686,7 @@

      Components


      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      @@ -873,14 +1718,14 @@

      Development Toolchains and Compi


      -

      Supported Devices and boards

      +

      Supported Devices and boards

      • STM32WBA52xx and STM32WBA55xx devices
      • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards


      -

      Known Limitations

      +

      Known Limitations

      • External PA is not supported.
      • Ext PA and AoA/AoD are not supported.
        • @@ -913,7 +1758,7 @@

        Known Limitations


      -

      Dependencies

      +

      Dependencies

      • STM32CubeMX V6.11.0
          @@ -922,14 +1767,14 @@

          Dependencies


        -

        Backward compatibility

        +

        Backward compatibility

        • Connectivity applications are available for NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
        • Connectivity applications are not supported on this release for NUCLEO-WBA52CG board


        -

        Notes

        +

        Notes

        • None
        @@ -940,12 +1785,12 @@

        Notes

        -

        Main Changes

        +

        Main Changes

        Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices


        -

        Connectivity

        -

        Introduction of the following new features:

        +

        Connectivity

        +

        Introduction of the following new features:

        • Bluetooth Low Energy 5.4 with :
            @@ -967,7 +1812,7 @@

            Introduction of the follow


          -

          Contents

          +

          Contents

          • CMSIS Devices Drivers updates
              @@ -1014,7 +1859,7 @@

              Contents


            -

            Projects

            +

            Projects

            • The STM32CubeWBA Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.
            • The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).
              • @@ -1038,7 +1883,7 @@

              Projects


      -

      Components

      +

      Components

      The components flagged by “” have changed since the previous release. “” are new.


      @@ -1293,7 +2138,7 @@

      Components


      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      @@ -1326,14 +2171,14 @@

      Development Toolchains and Compi


      -

      Supported Devices and boards

      +

      Supported Devices and boards

      • STM32WBA52xx and STM32WBA55xx devices
      • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards


      -

      Known Limitations

      +

      Known Limitations

      • External PA is not supported
      • BLE Applications: @@ -1348,7 +2193,7 @@

        Known Limitations


      -

      Dependencies

      +

      Dependencies

      • STM32CubeMX V6.10.0
          @@ -1357,14 +2202,14 @@

          Dependencies


        -

        Backward compatibility

        +

        Backward compatibility

        • Connectivity applications are available for NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
        • Connectivity applications are not supported on this release for NUCLEO-WBA52CG board


        -

        Notes

        +

        Notes

        • None
        @@ -1375,12 +2220,12 @@

        Notes

        -

        Main Changes

        +

        Main Changes

        Official Patch Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

        In the STM32CubeWBA MCU Package, examples and applications projects are generated with the STM32CubeMX tool to initialize the system, peripherals and middleware stacks. User can open the provided ioc file in STM32CubeMX to modify the settings, add additional peripherals and/or middleware, to build his final application.


        -

        Connectivity

        +

        Connectivity

        • This patch targets 2 issues related to the sleep timer overflow:
            @@ -1390,7 +2235,7 @@

            Connectivity


          -

          Contents

          +

          Contents

          • Projects updates
              @@ -1403,7 +2248,7 @@

              Contents


            -

            Projects

            +

            Projects

            • The STM32CubeWBA Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.
            • The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).
              • @@ -1427,7 +2272,7 @@

              Projects


      -

      Components

      +

      Components

      The components flagged by “” have changed since the previous release. “” are new.


      @@ -1643,7 +2488,7 @@

      Components


      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      @@ -1676,14 +2521,14 @@

      Development Toolchains and Compi


      -

      Supported Devices and boards

      +

      Supported Devices and boards

      • STM32WBA52xx devices
      • NUCLEO-WBA52CG board


      -

      Known Limitations

      +

      Known Limitations

      • BLE Applications:
          @@ -1693,7 +2538,7 @@

          Known Limitations


        -

        Dependencies

        +

        Dependencies

        • STM32CubeMX V6.9.0
            @@ -1706,11 +2551,11 @@

            Dependencies


          -

          Backward compatibility

          +

          Backward compatibility

          • Not applicable
          -

          Notes

          +

          Notes

          • None
          @@ -1721,12 +2566,12 @@

          Notes

          -

          Main Changes

          +

          Main Changes

          Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

          In the STM32CubeWBA MCU Package, examples and applications projects are generated with the STM32CubeMX tool to initialize the system, peripherals and middleware stacks. User can open the provided ioc file in STM32CubeMX to modify the settings, add additional peripherals and/or middleware, to build his final application.


          -

          Connectivity

          +

          Connectivity

          • Maximum number of simultaneous connections supported by the device is now 20.
          • PHY Calibration improvements: @@ -1738,7 +2583,7 @@

            Connectivity


          -

          Contents

          +

          Contents

          • CMSIS updates
              @@ -1793,7 +2638,7 @@

              Contents


            -

            Projects

            +

            Projects

            • The STM32CubeWBA Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.
            • The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).
              • @@ -1817,7 +2662,7 @@

              Projects


      -

      Components

      +

      Components

      The components flagged by “” have changed since the previous release. “” are new.


      @@ -2033,7 +2878,7 @@

      Components


      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      @@ -2066,14 +2911,14 @@

      Development Toolchains and Compi


      -

      Supported Devices and boards

      +

      Supported Devices and boards

      • STM32WBA52xx devices
      • NUCLEO-WBA52CG board


      -

      Known Limitations

      +

      Known Limitations

      • BLE Applications:
          @@ -2083,7 +2928,7 @@

          Known Limitations


        -

        Dependencies

        +

        Dependencies

        • STM32CubeMX V6.9.0
            @@ -2092,11 +2937,11 @@

            Dependencies


          -

          Backward compatibility

          +

          Backward compatibility

          • Not applicable
          -

          Notes

          +

          Notes

          • None
          @@ -2107,12 +2952,12 @@

          Notes

          -

          Main Changes

          +

          Main Changes

          First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

          In the STM32CubeWBA MCU Package, examples and applications projects are generated with the STM32CubeMX tool to initialize the system, peripherals and middleware stacks. User can open the provided ioc file in STM32CubeMX to modify the settings, add additional peripherals and/or middleware, to build his final application.


          -

          Connectivity

          +

          Connectivity

          • The Bluetooth Low Energy is 5.3 compliant and supports the following features:
              @@ -2140,7 +2985,7 @@

              Connectivity


            -

            Contents

            +

            Contents

            • CMSIS Devices Drivers
                @@ -2200,7 +3045,7 @@

                Contents


              -

              Projects

              +

              Projects

              • The STM32CubeWBA Firmware package comes with a rich set of examples running on STMicroelectronics boards, organized by board and provided with preconfigured projects for the main supported toolchains.
              • The exhaustive list of projects and their short description is provided in this table (STM32CubeProjectsList.html).
                • @@ -2224,7 +3069,7 @@

                Projects


      -

      Components

      +

      Components

      The components flagged by “” have changed since the previous release. “” are new.


      @@ -2440,7 +3285,7 @@

      Components


      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      @@ -2473,14 +3318,14 @@

      Development Toolchains and Compi


      -

      Supported Devices and boards

      +

      Supported Devices and boards

      • STM32WBA52xx devices
      • NUCLEO-WBA52CG board


      -

      Known Limitations

      +

      Known Limitations

      • BLE Applications:
          @@ -2492,7 +3337,7 @@

          Known Limitations


        -

        Dependencies

        +

        Dependencies

        • STM32CubeMX V6.8.0
            @@ -2501,11 +3346,11 @@

            Dependencies


          -

          Backward compatibility

          +

          Backward compatibility

          • Not applicable
          -

          Notes

          +

          Notes

          • None
          diff --git a/stm32cube/stm32wbaxx/soc/stm32wba50xx.h b/stm32cube/stm32wbaxx/soc/stm32wba50xx.h index be17f15ce..4ff08c947 100644 --- a/stm32cube/stm32wbaxx/soc/stm32wba50xx.h +++ b/stm32cube/stm32wbaxx/soc/stm32wba50xx.h @@ -253,14 +253,14 @@ typedef struct */ typedef struct { - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ - __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ - uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */ - __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ - __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ } DBGMCU_TypeDef; /** @@ -617,11 +617,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ uint32_t RESERVED; - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /* @@ -693,18 +693,18 @@ typedef struct */ typedef struct { - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ } SYSCFG_TypeDef; /** @@ -4256,7 +4256,7 @@ typedef struct #define I2C_CR1_ADDRACLR_Pos (30U) #define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ #define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ -#define I2C_CR1_STOPFACLR_Pos (30U) +#define I2C_CR1_STOPFACLR_Pos (31U) #define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ #define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ @@ -4942,7 +4942,6 @@ typedef struct #define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ #define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */ - /******************************************************************************/ /* */ /* Public Key Accelerator (PKA) */ @@ -6669,6 +6668,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F02D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ @@ -10293,7 +10295,8 @@ typedef struct /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ - ((INSTANCE) == TIM2_NS)) + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM16_NS)) /********* TIM Instances : supporting bitfield OCCS in SMCR register **********/ #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ diff --git a/stm32cube/stm32wbaxx/soc/stm32wba52xx.h b/stm32cube/stm32wbaxx/soc/stm32wba52xx.h index f741aa67d..92ec46b5b 100644 --- a/stm32cube/stm32wbaxx/soc/stm32wba52xx.h +++ b/stm32cube/stm32wbaxx/soc/stm32wba52xx.h @@ -267,14 +267,14 @@ typedef struct */ typedef struct { - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ - __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ - uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */ - __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ - __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ } DBGMCU_TypeDef; /** @@ -710,11 +710,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ uint32_t RESERVED; - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /* @@ -787,18 +787,18 @@ typedef struct */ typedef struct { - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ } SYSCFG_TypeDef; /** @@ -7856,7 +7856,7 @@ typedef struct #define I2C_CR1_ADDRACLR_Pos (30U) #define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ #define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ -#define I2C_CR1_STOPFACLR_Pos (30U) +#define I2C_CR1_STOPFACLR_Pos (31U) #define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ #define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ @@ -8542,7 +8542,6 @@ typedef struct #define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ #define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */ - /******************************************************************************/ /* */ /* Public Key Accelerator (PKA) */ @@ -10570,6 +10569,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F02D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ @@ -14527,7 +14529,9 @@ typedef struct /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ diff --git a/stm32cube/stm32wbaxx/soc/stm32wba54xx.h b/stm32cube/stm32wbaxx/soc/stm32wba54xx.h index 3874e6cee..ce6b6a595 100644 --- a/stm32cube/stm32wbaxx/soc/stm32wba54xx.h +++ b/stm32cube/stm32wbaxx/soc/stm32wba54xx.h @@ -284,14 +284,14 @@ typedef struct */ typedef struct { - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ - __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ - uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */ - __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ - __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ } DBGMCU_TypeDef; /** @@ -749,11 +749,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ uint32_t RESERVED; - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /* @@ -804,7 +804,7 @@ typedef struct typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -849,18 +849,18 @@ typedef struct */ typedef struct { - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ } SYSCFG_TypeDef; /** @@ -8090,7 +8090,7 @@ typedef struct #define I2C_CR1_ADDRACLR_Pos (30U) #define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ #define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ -#define I2C_CR1_STOPFACLR_Pos (30U) +#define I2C_CR1_STOPFACLR_Pos (31U) #define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ #define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ @@ -8776,7 +8776,6 @@ typedef struct #define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ #define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */ - /******************************************************************************/ /* */ /* Public Key Accelerator (PKA) */ @@ -10964,6 +10963,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F02D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ @@ -15235,7 +15237,9 @@ typedef struct /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ diff --git a/stm32cube/stm32wbaxx/soc/stm32wba55xx.h b/stm32cube/stm32wbaxx/soc/stm32wba55xx.h index 99c650d87..9cf8772db 100644 --- a/stm32cube/stm32wbaxx/soc/stm32wba55xx.h +++ b/stm32cube/stm32wbaxx/soc/stm32wba55xx.h @@ -284,14 +284,14 @@ typedef struct */ typedef struct { - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ - __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ - uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */ - __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ - __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ } DBGMCU_TypeDef; /** @@ -749,11 +749,11 @@ typedef struct */ typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ uint32_t RESERVED; - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /* @@ -804,7 +804,7 @@ typedef struct typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -849,18 +849,18 @@ typedef struct */ typedef struct { - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ } SYSCFG_TypeDef; /** @@ -8090,7 +8090,7 @@ typedef struct #define I2C_CR1_ADDRACLR_Pos (30U) #define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ #define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ -#define I2C_CR1_STOPFACLR_Pos (30U) +#define I2C_CR1_STOPFACLR_Pos (31U) #define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ #define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ @@ -8776,7 +8776,6 @@ typedef struct #define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ #define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */ - /******************************************************************************/ /* */ /* Public Key Accelerator (PKA) */ @@ -10982,6 +10981,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F02D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ @@ -15253,7 +15255,9 @@ typedef struct /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ diff --git a/stm32cube/stm32wbaxx/soc/stm32wbaxx.h b/stm32cube/stm32wbaxx/soc/stm32wbaxx.h index ecb4c99ce..fa18328de 100644 --- a/stm32cube/stm32wbaxx/soc/stm32wbaxx.h +++ b/stm32cube/stm32wbaxx/soc/stm32wbaxx.h @@ -79,7 +79,7 @@ * @brief CMSIS Device version number */ #define __STM32WBA_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBA_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ +#define __STM32WBA_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ #define __STM32WBA_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBA_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBA_CMSIS_VERSION ((__STM32WBA_CMSIS_VERSION_MAIN << 24U)\ diff --git a/zephyr/module.yml b/zephyr/module.yml index 9118f3cdb..5c09d1d24 100644 --- a/zephyr/module.yml +++ b/zephyr/module.yml @@ -5,16 +5,16 @@ build: dts_root: . blobs: - path: stm32wba/lib/LinkLayer_BLE_Full_lib.a - sha256: 28e351fb2c64ae9ddc15b3e29aa80bd5ce265a6fb9b03a9c604b54554c5c068b + sha256: 733fb35f978080e6e39ddaa18e37fc6ab1c694550c5b3c863f30457fa6d3968a type: lib - version: '1.3.1' + version: '1.4.1' license-path: zephyr/blobs/stm32wba/lib/license.md - url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.3.1/Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/lib/LinkLayer_BLE_Full_lib.a + url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.4.1/Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/lib/LinkLayer_BLE_Full_lib.a description: "Binary Link Layer library for the STM32WBA Bluetooth subsystem" - path: stm32wba/lib/stm32wba_ble_stack_llo.a - sha256: 8f0fb725f1c3facf0b53a67af5c001f16eb2e056f3d319f64c7f94799065e358 + sha256: 1fb1287b04105ee6de2709a0239ffb849aa55f577b5234fdfff401b9dec9fcb7 type: lib - version: '1.3.1' + version: '1.4.1' license-path: zephyr/blobs/stm32wba/lib/license.md - url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.3.1/Middlewares/ST/STM32_WPAN/ble/stack/lib/stm32wba_ble_stack_llo.a + url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.4.1/Middlewares/ST/STM32_WPAN/ble/stack/lib/stm32wba_ble_stack_llo.a description: "Binary Stack library for the STM32WBA Bluetooth subsystem"