diff --git a/stm32cube/common_ll/README.rst b/stm32cube/common_ll/README.rst index 150496706..598bbc252 100644 --- a/stm32cube/common_ll/README.rst +++ b/stm32cube/common_ll/README.rst @@ -18,19 +18,19 @@ stm32f3xx 1.11.5 stm32f4xx 1.28.1 stm32f7xx 1.17.2 stm32g0xx 1.6.2 -stm32g4xx 1.6.0 -stm32h5xx 1.3.0 +stm32g4xx 1.6.1 +stm32h5xx 1.4.0 stm32h7rsxx 1.1.0 -stm32h7xx 1.11.2 +stm32h7xx 1.12.0 stm32l0xx 1.12.2 stm32l1xx 1.10.4 stm32l4xx 1.18.1 stm32l5xx 1.5.1 stm32mp1xx 1.6.0 -stm32u0xx 1.1.0 -stm32u5xx 1.6.0 +stm32u0xx 1.2.0 +stm32u5xx 1.7.0 stm32wb0x 1.0.0 stm32wbaxx 1.4.1 -stm32wbxx 1.20.0 +stm32wbxx 1.21.0 stm32wlxx 1.3.0 =============== =============== \ No newline at end of file diff --git a/stm32cube/stm32g4xx/README b/stm32cube/stm32g4xx/README index 761bf4ced..7edaa36e2 100644 --- a/stm32cube/stm32g4xx/README +++ b/stm32cube/stm32g4xx/README @@ -6,7 +6,7 @@ Origin: http://www.st.com/en/embedded-software/stm32cubeg4.html Status: - version v1.6.0 + version v1.6.1 Purpose: ST Microelectronics official MCU package for STM32G4 series. @@ -23,7 +23,7 @@ URL: https://github.com/STMicroelectronics/STM32CubeG4 Commit: - 98f52ec7cdbbbfe1650b351bde2efb037815886d + 1e6984e6cdeb9e5c01f5badbfd18e5cf4345d02f Maintained-by: External @@ -44,4 +44,8 @@ Patch List: -Added stm32cube/stm32g4xx/drivers/include/stm32_assert.h -Removed unused stm32cube/stm32g4xx/drivers/include/stm32_assert_template.h + *Fix to remove PAGESIZE definition which conflicts with POSIX + Impacted files: + drivers/include/Legacy/stm32_hal_legacy.h + See release_note.html from STM32Cube diff --git a/stm32cube/stm32g4xx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32g4xx/drivers/include/Legacy/stm32_hal_legacy.h index f0204c4b0..d68f04c5f 100644 --- a/stm32cube/stm32g4xx/drivers/include/Legacy/stm32_hal_legacy.h +++ b/stm32cube/stm32g4xx/drivers/include/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -/* #define PAGESIZE FLASH_PAGE_SIZE */ +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) +/* define PAGESIZE FLASH_PAGE_SIZE */ +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -875,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -1012,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -3680,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal.h index e67a2033b..eb407537c 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal.h @@ -460,9 +460,13 @@ extern "C" { ((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY) || \ ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) -#if (CCMSRAM_SIZE == 0x00008000UL) || (CCMSRAM_SIZE == 0x00004000UL) +#if (CCMSRAM_SIZE == 0x00008000UL) /* STM32G4 devices with CCMSRAM_SIZE = 32 Kbytes */ #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) ((__PAGE__) > 0U) -#elif (CCMSRAM_SIZE == 0x00002800UL) +#elif (CCMSRAM_SIZE == 0x00005000UL) /* STM32G4 devices with CCMSRAM_SIZE = 20 Kbytes */ +#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FFFFFU)) +#elif (CCMSRAM_SIZE == 0x00004000UL) /* STM32G4 devices with CCMSRAM_SIZE = 16 Kbytes */ +#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x0000FFFFU)) +#elif (CCMSRAM_SIZE == 0x00002800UL) /* STM32G4 devices with CCMSRAM_SIZE = 10 Kbytes */ #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU)) #endif /* CCMSRAM_SIZE */ @@ -600,10 +604,7 @@ void HAL_SYSCFG_EnableIOSwitchBooster(void); void HAL_SYSCFG_DisableIOSwitchBooster(void); void HAL_SYSCFG_EnableIOSwitchVDD(void); void HAL_SYSCFG_DisableIOSwitchVDD(void); - -#if defined(CCMSRAM_BASE) void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page); -#endif /* CCMSRAM_BASE */ /** * @} diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_adc.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_adc.h index 81622aae4..bcddc5fc9 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_adc.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_adc.h @@ -1305,7 +1305,7 @@ out-of-window sample to raise flag or interrupt */ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) -#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ @@ -1325,7 +1325,7 @@ out-of-window sample to raise flag or interrupt */ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) -#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_adc_ex.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_adc_ex.h index d893d33b6..440c223a8 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_adc_ex.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_adc_ex.h @@ -623,7 +623,7 @@ typedef struct : \ RESET \ ) -#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC) #define ADC_IS_INDEPENDENT(__HANDLE__) \ ( ( ( ((__HANDLE__)->Instance) == ADC3) \ )? \ @@ -631,7 +631,7 @@ typedef struct : \ RESET \ ) -#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ @@ -790,7 +790,7 @@ typedef struct : \ ((__HANDLE_SLAVE__)->Instance = NULL) \ ) -#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) +#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. @@ -816,7 +816,7 @@ typedef struct #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) \ ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5)) -#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) +#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ @@ -828,7 +828,7 @@ typedef struct #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \ ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4)) -#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) @@ -947,7 +947,7 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) -#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \ ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ @@ -1051,7 +1051,7 @@ typedef struct (((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_15))) ) -#elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) +#elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ (((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ @@ -1069,7 +1069,7 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_13))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ ((__CHANNEL__) == ADC_CHANNEL_15))) ) -#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ @@ -1239,7 +1239,7 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) -#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ @@ -1260,7 +1260,7 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) -#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_comp.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_comp.h index 2aecfde90..3480b280e 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_comp.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_comp.h @@ -953,10 +953,16 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_ExtiLine COMP EXTI Lines * @{ */ +#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP1 output. Note: For COMPx instance availability, please refer to datasheet */ #define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output. Note: For COMPx instance availability, please refer to datasheet */ #define COMP_EXTI_LINE_COMP3 (LL_EXTI_LINE_29) /*!< EXTI line 29 connected to COMP3 output. Note: For COMPx instance availability, please refer to datasheet */ #define COMP_EXTI_LINE_COMP4 (LL_EXTI_LINE_30) /*!< EXTI line 30 connected to COMP4 output. Note: For COMPx instance availability, please refer to datasheet */ +#elif defined(STM32G411xB) || defined(STM32G411xC) +#define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP1 output. Note: For COMPx instance availability, please refer to datasheet */ +#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output. Note: For COMPx instance availability, please refer to datasheet */ +#define COMP_EXTI_LINE_COMP3 (LL_EXTI_LINE_29) /*!< EXTI line 29 connected to COMP3 output. Note: For COMPx instance availability, please refer to datasheet */ +#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx || STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G491xx || STM32G4A1xx */ #if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define COMP_EXTI_LINE_COMP5 (LL_EXTI_LINE_31) /*!< EXTI line 31 connected to COMP5 output. Note: For COMPx instance availability, please refer to datasheet */ #define COMP_EXTI_LINE_COMP6 (LL_EXTI_LINE_32) /*!< EXTI line 32 connected to COMP6 output. Note: For COMPx instance availability, please refer to datasheet */ @@ -1007,6 +1013,10 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \ :((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \ : COMP_EXTI_LINE_COMP4) +#elif defined(STM32G411xB) || defined(STM32G411xC) +#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ + :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \ + : COMP_EXTI_LINE_COMP3) #endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */ /** * @} @@ -1076,6 +1086,25 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ )) +#elif defined(STM32G411xB) || defined(STM32G411xC) +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \ + (((__COMP_INSTANCE__) == COMP1) && \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP2) && \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP3) && \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ + )) #endif @@ -1250,6 +1279,32 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ ) +#elif defined(STM32G411xB) || defined(STM32G411xC) +#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + ((((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ + || \ + (((__INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ + || \ + (((__INSTANCE__) == COMP3) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ + ) #endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */ #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_dac.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_dac.h index d196be0f0..8049f97e2 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_dac.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_dac.h @@ -307,10 +307,13 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) -#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) -#define DAC_CHIPCONNECT_BOTH (1UL << 2) - +#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/ +#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. */ +#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. + Note: this connection is not available in mode normal + with buffer disabled. */ /** * @} */ @@ -506,6 +509,13 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); : \ (((CHANNEL) == DAC_CHANNEL_1) || \ ((CHANNEL) == DAC_CHANNEL_2))) +#elif defined(STM32G411xB) || defined(STM32G411xC) +#define IS_DAC_CHANNEL(DACX, CHANNEL) \ + (((DACX) == DAC1) ? \ + ((CHANNEL) == DAC_CHANNEL_1) \ + : \ + (((CHANNEL) == DAC_CHANNEL_1) || \ + ((CHANNEL) == DAC_CHANNEL_2))) #else #define IS_DAC_CHANNEL(DACX, CHANNEL) \ (((CHANNEL) == DAC_CHANNEL_1) || \ diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_flash.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_flash.h index 9db749119..8ad7d0cc4 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_flash.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_flash.h @@ -410,7 +410,6 @@ typedef struct /** * @} */ - /** @defgroup FLASH_OB_USER_CCMSRAM_RST FLASH Option Bytes User CCMSRAM Erase On Reset Type * @{ */ @@ -419,7 +418,6 @@ typedef struct /** * @} */ - /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 * @{ */ @@ -975,6 +973,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE)) + #define IS_OB_USER_CCMSRAM_RST(VALUE) (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE)) #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_hrtim.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_hrtim.h index 8210cdbee..2deb9d853 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_hrtim.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_hrtim.h @@ -21,7 +21,7 @@ #define STM32G4xx_HAL_HRTIM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -60,7 +60,7 @@ */ typedef struct { - uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. + uint32_t HRTIMInterruptRequests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */ uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals. The HRTIM instance can be configured to act as a slave (waiting for a trigger @@ -119,7 +119,7 @@ typedef struct __HRTIM_HandleTypeDef typedef struct #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ { - HRTIM_TypeDef * Instance; /*!< Register base address */ + HRTIM_TypeDef *Instance; /*!< Register base address */ HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */ @@ -129,13 +129,13 @@ typedef struct __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */ - DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerF; /*!< Timer F DMA handle parameters */ + DMA_HandleTypeDef *hdmaMaster; /*!< Master timer DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerA; /*!< Timer A DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerB; /*!< Timer B DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerC; /*!< Timer C DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerD; /*!< Timer D DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerE; /*!< Timer E DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerF; /*!< Timer F DMA handle parameters */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 1 interrupt callback function pointer */ @@ -555,7 +555,8 @@ typedef struct /** * @brief HAL HRTIM Callback ID enumeration definition */ -typedef enum { +typedef enum +{ HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /*!< Fault 1 interrupt callback ID */ HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /*!< Fault 2 interrupt callback ID */ HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /*!< Fault 3 interrupt callback ID */ @@ -586,7 +587,7 @@ typedef enum { HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /*!< HRTIM MspInit callback ID */ HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /*!< HRTIM MspInit callback ID */ HAL_HRTIM_FAULT6CALLBACK_CB_ID = 0x22U, /*!< Fault 6 interrupt callback ID */ -}HAL_HRTIM_CallbackIDTypeDef; +} HAL_HRTIM_CallbackIDTypeDef; /** * @brief HAL HRTIM Callback function pointer definitions @@ -634,8 +635,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */ #define HRTIM_TIMERID_TIMER_F (HRTIM_MCR_TFCEN) /*!< Timer F identifier */ /** - * @} - */ + * @} + */ /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit * @{ @@ -645,9 +646,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */ #define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */ #define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit * @{ @@ -703,23 +704,23 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_ADCTRIGGER_10 0x00000200U /*!< ADC trigger 10 identifier */ #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ - (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_5) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_6) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_7) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_8) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_9) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_10)) + (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_5) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_6) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_7) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_8) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_9) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_10)) #define IS_HRTIM_ADCEXTTRIGGER(ADCTRIGGER)\ - (((ADCTRIGGER) == HRTIM_ADCTRIGGER_5) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_6) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_7) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_8) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_9) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_10)) + (((ADCTRIGGER) == HRTIM_ADCTRIGGER_5) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_6) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_7) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_8) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_9) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_10)) /** * @} */ @@ -758,10 +759,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ - /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio +/** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio * @{ * @brief Constants defining timer high-resolution clock prescaler ratio. - */ + */ #define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */ @@ -1144,11 +1145,11 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_TIM_ROM_VALLEY (HRTIM_TIMCR2_ROM_0) /*!< repetition counter decrement and External Event filtering */ #define IS_HRTIM_ROLLOVERMODE(ROLLOVER)\ - ((((ROLLOVER) == HRTIM_TIM_FEROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_FEROM_CREST) || ((ROLLOVER) == HRTIM_TIM_FEROM_VALLEY)) ||\ - (((ROLLOVER) == HRTIM_TIM_ADROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_ADROM_CREST) || ((ROLLOVER) == HRTIM_TIM_ADROM_VALLEY)) ||\ - (((ROLLOVER) == HRTIM_TIM_BMROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_BMROM_CREST) || ((ROLLOVER) == HRTIM_TIM_BMROM_VALLEY)) ||\ - (((ROLLOVER) == HRTIM_TIM_OUTROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_OUTROM_CREST) || ((ROLLOVER) == HRTIM_TIM_OUTROM_VALLEY)) ||\ - (((ROLLOVER) == HRTIM_TIM_ROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_ROM_CREST) || ((ROLLOVER) == HRTIM_TIM_ROM_VALLEY))) + ((((ROLLOVER) == HRTIM_TIM_FEROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_FEROM_CREST) || ((ROLLOVER) == HRTIM_TIM_FEROM_VALLEY)) ||\ + (((ROLLOVER) == HRTIM_TIM_ADROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_ADROM_CREST) || ((ROLLOVER) == HRTIM_TIM_ADROM_VALLEY)) ||\ + (((ROLLOVER) == HRTIM_TIM_BMROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_BMROM_CREST) || ((ROLLOVER) == HRTIM_TIM_BMROM_VALLEY)) ||\ + (((ROLLOVER) == HRTIM_TIM_OUTROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_OUTROM_CREST) || ((ROLLOVER) == HRTIM_TIM_OUTROM_VALLEY)) ||\ + (((ROLLOVER) == HRTIM_TIM_ROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_ROM_CREST) || ((ROLLOVER) == HRTIM_TIM_ROM_VALLEY))) /** * @} */ @@ -1177,9 +1178,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */ #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ - (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) + (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) /** * @} */ @@ -1385,9 +1386,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level * @{ @@ -1566,7 +1567,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_TIMEEVFLT_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */ #define HRTIM_TIMEEVFLT_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */ #define HRTIM_TIMEEVFLT_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\ - | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ + | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ /** * @} */ @@ -1717,9 +1718,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle * @{ @@ -2446,8 +2447,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Force the output to its inactive state */ #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ - (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ - ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) + (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ + ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) /** * @} */ @@ -2654,236 +2655,236 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_CAPTUREFTRIGGER_TF1_RESET (HRTIM_CPT1CR_TF1RST) /*!< 32bit value Capture is triggered by TF1 output active to inactive transition */ #define HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1 (HRTIM_CPT1CR_TIMFCMP1) /*!< 32bit value Timer F Compare 1 triggers Capture */ #define HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2 (HRTIM_CPT1CR_TIMFCMP2) /*!< 32bit value Timer F Compare 2 triggers Capture */ - /** +/** * @} - */ + */ - /* Private macros --------------------------------------------------------*/ +/* Private macros --------------------------------------------------------*/ /** @addtogroup HRTIM_Private_Macros * @{ */ #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F)) + (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F)) #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F)) + (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F)) #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFF80FFFFU) == 0x00000000U) #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) + (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ - (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ - ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) + (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ + ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFF000U) == 0x00000000U) #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ - ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TE2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \ - (((OUTPUT) == HRTIM_OUTPUT_TF1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TF2)))) + ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ + (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ + (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ + (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ + (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ + (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TE2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \ + (((OUTPUT) == HRTIM_OUTPUT_TF1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TF2)))) #define IS_HRTIM_TIMEEVENT(EVENT)\ - (((EVENT) == HRTIM_EVENTCOUNTER_A) || \ - ((EVENT) == HRTIM_EVENTCOUNTER_B)) + (((EVENT) == HRTIM_EVENTCOUNTER_A) || \ + ((EVENT) == HRTIM_EVENTCOUNTER_B)) #define IS_HRTIM_TIMEEVENT_RESETMODE(EVENT)\ - (((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL) || \ - ((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL)) + (((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL) || \ + ((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL)) #define IS_HRTIM_TIMSYNCUPDATE(EVENT)\ - (((EVENT) == HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL) || \ - ((EVENT) == HRTIM_TIMERESYNC_UPDATE_CONDITIONAL)) + (((EVENT) == HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL) || \ + ((EVENT) == HRTIM_TIMERESYNC_UPDATE_CONDITIONAL)) #define IS_HRTIM_TIMEEVENT_COUNTER(COUNTER)\ - ((((COUNTER) > (uint32_t)0x00U) && ((COUNTER) <= (uint32_t)0x3FU)) ||\ - ((COUNTER) == (uint32_t)0x00U)) + ((((COUNTER) > (uint32_t)0x00U) && ((COUNTER) <= (uint32_t)0x3FU)) ||\ + ((COUNTER) == (uint32_t)0x00U)) #define IS_HRTIM_TIMEEVENT_SOURCE(SOURCE)\ - (((SOURCE) >= (uint32_t)0x00U) && ((SOURCE) <= (uint32_t)0x9U)) + (((SOURCE) >= (uint32_t)0x00U) && ((SOURCE) <= (uint32_t)0x9U)) #define IS_HRTIM_EVENT(EVENT)\ - (((EVENT) == HRTIM_EVENT_NONE)|| \ - ((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5) || \ - ((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) + (((EVENT) == HRTIM_EVENT_NONE)|| \ + ((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5) || \ + ((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10)) #define IS_HRTIM_FAULT(FAULT)\ - (((FAULT) == HRTIM_FAULT_1) || \ - ((FAULT) == HRTIM_FAULT_2) || \ - ((FAULT) == HRTIM_FAULT_3) || \ - ((FAULT) == HRTIM_FAULT_4) || \ - ((FAULT) == HRTIM_FAULT_5) || \ - ((FAULT) == HRTIM_FAULT_6)) + (((FAULT) == HRTIM_FAULT_1) || \ + ((FAULT) == HRTIM_FAULT_2) || \ + ((FAULT) == HRTIM_FAULT_3) || \ + ((FAULT) == HRTIM_FAULT_4) || \ + ((FAULT) == HRTIM_FAULT_5) || \ + ((FAULT) == HRTIM_FAULT_6)) #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) + (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) #define IS_HRTIM_MODE(MODE)\ - (((MODE) == HRTIM_MODE_CONTINUOUS) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) + (((MODE) == HRTIM_MODE_CONTINUOUS) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) #define IS_HRTIM_MODE_ONEPULSE(MODE)\ - (((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) + (((MODE) == HRTIM_MODE_SINGLESHOT) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) #define IS_HRTIM_HALFMODE(HALFMODE)\ - (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ - ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) + (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ + ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) #define IS_HRTIM_INTERLEAVEDMODE(INTLVDMODE)\ - (((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ - ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DUAL) || \ - ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ - ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_TRIPLE) || \ - ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ - ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_QUAD)) + (((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ + ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DUAL) || \ + ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ + ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_TRIPLE) || \ + ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ + ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_QUAD)) #define IS_HRTIM_SYNCSTART(SYNCSTART)\ - (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ - ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) + (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ + ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) #define IS_HRTIM_SYNCRESET(SYNCRESET)\ - (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ - ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) + (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ + ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) #define IS_HRTIM_DACSYNC(DACSYNC)\ - (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) + (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) #define IS_HRTIM_PRELOAD(PRELOAD)\ - (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ - ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) + (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ + ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) + (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) + (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) #define IS_HRTIM_TIMERBURSTMODE(MODE) \ - (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ - ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) + (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ + ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) #define IS_HRTIM_TIMERUPDOWNMODE(MODE) \ - (((MODE) == HRTIM_TIMERUPDOWNMODE_UP) || \ - ((MODE) == HRTIM_TIMERUPDOWNMODE_UPDOWN)) + (((MODE) == HRTIM_TIMERUPDOWNMODE_UP) || \ + ((MODE) == HRTIM_TIMERUPDOWNMODE_UPDOWN)) #define IS_HRTIM_TIMERTRGHLFMODE(MODE) \ - (((MODE) == HRTIM_TIMERTRIGHALF_DISABLED) || \ - ((MODE) == HRTIM_TIMERTRIGHALF_ENABLED)) + (((MODE) == HRTIM_TIMERTRIGHALF_DISABLED) || \ + ((MODE) == HRTIM_TIMERTRIGHALF_ENABLED)) #define IS_HRTIM_TIMERGTCMP3(MODE) \ - (((MODE) == HRTIM_TIMERGTCMP3_EQUAL) || \ - ((MODE) == HRTIM_TIMERGTCMP3_GREATER)) + (((MODE) == HRTIM_TIMERGTCMP3_EQUAL) || \ + ((MODE) == HRTIM_TIMERGTCMP3_GREATER)) #define IS_HRTIM_TIMERGTCMP1(MODE) \ - (((MODE) == HRTIM_TIMERGTCMP1_EQUAL) || \ - ((MODE) == HRTIM_TIMERGTCMP1_GREATER)) + (((MODE) == HRTIM_TIMERGTCMP1_EQUAL) || \ + ((MODE) == HRTIM_TIMERGTCMP1_GREATER)) #define IS_HRTIM_DUALDAC_RESET(DUALCHANNELDAC) \ - (((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_COUNTER) || \ - ((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_OUT1SET)) + (((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_COUNTER) || \ + ((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_OUT1SET)) #define IS_HRTIM_DUALDAC_STEP(DUALCHANNELDAC) \ - (((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_CMP2) || \ - ((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_OUT1RST)) + (((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_CMP2) || \ + ((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_OUT1RST)) #define IS_HRTIM_DUALDAC_ENABLE(DUALCHANNELDAC) \ - (((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_DISABLED) || \ - ((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_ENABLED )) + (((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_DISABLED) || \ + ((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_ENABLED )) #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ - (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ - ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) + (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ + ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ - ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ + ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFC0U) == 0x00000000U) #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ - (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ - ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) + (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ + ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\ - (((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ - ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)) + (((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ + ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)) #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\ - ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ - || \ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ - (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) + ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ + || \ + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ + (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE06FFFFU) == 0x00000000U) @@ -2891,131 +2892,131 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ - (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ - ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) + (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ + ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) /* Auto delayed mode is only available for compare units 2 and 4U */ #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \ - ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ - || \ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) + ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ + || \ + (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\ - (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ - ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) + (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ + ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU) #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ - (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) + (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ - (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) + (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ - (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ - ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) + (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ + ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\ - (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ - ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) + (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ + ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\ - (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) + (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\ - (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ - ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) + (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ + ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\ - (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ - ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) + (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ + ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) #define IS_HRTIM_OUTPUTBALANCEDIDLE(OUTPUTBIAR)\ - (((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_DISABLED) || \ - ((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_ENABLED)) + (((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_DISABLED) || \ + ((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_ENABLED)) #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \ @@ -3029,597 +3030,597 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \ || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))) + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))) #define IS_HRTIM_TIMER_CAPTUREFTRIGGER(TIMER, CAPTUREFTRIGGER) \ - ( ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_NONE) || \ - ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_SET) || \ - ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_RESET) || \ - ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1) || \ - ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2)) + ( ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_NONE) || \ + ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_SET) || \ + ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_RESET) || \ + ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1) || \ + ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2)) #define IS_HRTIM_TIMEVENTFILTER(TIMER,TIMEVENTFILTER)\ - (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_NONE) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGTIM) \ - || \ + (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_NONE) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGTIM) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2))) \ - || \ + (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1))) \ - || \ + (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4))) \ - || \ + (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4))) \ - || \ + (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2))) \ - || \ + (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \ - (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2)))) + (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2)))) #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ - (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ - ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) + (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ + ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) + (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ - (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ - ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) + (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ + ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ - (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ - ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) + (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ + ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\ - (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ - ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) + (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ + ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\ - (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ - ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) + (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ + ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\ - (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ - ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) + (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ + ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\ - (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ - ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) + (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ + ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) + (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\ - (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) + (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\ - (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) + (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\ - (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) + (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ + ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ + ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\ - (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) + (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\ - (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) + (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ + ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ + ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) #define IS_HRTIM_EVENTSRC(EVENT, EVENTSRC) \ - ((((EVENT) == HRTIM_EVENT_1) && \ - (((EVENTSRC) == HRTIM_EEV1SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO ) || \ - ((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 ))) \ - || \ - (((EVENT) == HRTIM_EVENT_2) && \ - (((EVENTSRC) == HRTIM_EEV2SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO ) || \ - ((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 ))) \ - || \ - (((EVENT) == HRTIM_EVENT_3) && \ - (((EVENTSRC) == HRTIM_EEV3SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO ) || \ - ((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 ))) \ - || \ - (((EVENT) == HRTIM_EVENT_4) && \ - (((EVENTSRC) == HRTIM_EEV4SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 ))) \ - || \ - (((EVENT) == HRTIM_EVENT_5) && \ - (((EVENTSRC) == HRTIM_EEV5SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 ))) \ - || \ - (((EVENT) == HRTIM_EVENT_6) && \ - (((EVENTSRC) == HRTIM_EEV6SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 ))) \ - || \ - (((EVENT) == HRTIM_EVENT_7) && \ - (((EVENTSRC) == HRTIM_EEV7SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO ) || \ - ((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 ))) \ - || \ - (((EVENT) == HRTIM_EVENT_8) && \ - (((EVENTSRC) == HRTIM_EEV8SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 ))) \ - || \ - (((EVENT) == HRTIM_EVENT_9) && \ - (((EVENTSRC) == HRTIM_EEV9SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO) || \ - ((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT ))) \ - || \ - (((EVENT) == HRTIM_EVENT_10) && \ - (((EVENTSRC) == HRTIM_EEV10SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT) || \ - ((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO) || \ - ((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1)))) + ((((EVENT) == HRTIM_EVENT_1) && \ + (((EVENTSRC) == HRTIM_EEV1SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO ) || \ + ((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_2) && \ + (((EVENTSRC) == HRTIM_EEV2SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO ) || \ + ((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_3) && \ + (((EVENTSRC) == HRTIM_EEV3SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO ) || \ + ((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_4) && \ + (((EVENTSRC) == HRTIM_EEV4SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_5) && \ + (((EVENTSRC) == HRTIM_EEV5SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_6) && \ + (((EVENTSRC) == HRTIM_EEV6SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_7) && \ + (((EVENTSRC) == HRTIM_EEV7SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO ) || \ + ((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_8) && \ + (((EVENTSRC) == HRTIM_EEV8SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_9) && \ + (((EVENTSRC) == HRTIM_EEV9SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO) || \ + ((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT ))) \ + || \ + (((EVENT) == HRTIM_EVENT_10) && \ + (((EVENTSRC) == HRTIM_EEV10SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT) || \ + ((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO) || \ + ((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1)))) #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\ - ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ - (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ - ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ - || \ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) + ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ + (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ + ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ + || \ + (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) + (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\ - (((((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) && \ - (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ - ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ - || \ - (((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10))) + (((((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5)) && \ + (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ + ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ + || \ + (((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10))) #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\ - ((((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) \ - || \ - ((((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) && \ - (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ - ((FILTER) == HRTIM_EVENTFILTER_1) || \ - ((FILTER) == HRTIM_EVENTFILTER_2) || \ - ((FILTER) == HRTIM_EVENTFILTER_3) || \ - ((FILTER) == HRTIM_EVENTFILTER_4) || \ - ((FILTER) == HRTIM_EVENTFILTER_5) || \ - ((FILTER) == HRTIM_EVENTFILTER_6) || \ - ((FILTER) == HRTIM_EVENTFILTER_7) || \ - ((FILTER) == HRTIM_EVENTFILTER_8) || \ - ((FILTER) == HRTIM_EVENTFILTER_9) || \ - ((FILTER) == HRTIM_EVENTFILTER_10) || \ - ((FILTER) == HRTIM_EVENTFILTER_11) || \ - ((FILTER) == HRTIM_EVENTFILTER_12) || \ - ((FILTER) == HRTIM_EVENTFILTER_13) || \ - ((FILTER) == HRTIM_EVENTFILTER_14) || \ - ((FILTER) == HRTIM_EVENTFILTER_15)))) + ((((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5)) \ + || \ + ((((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10)) && \ + (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ + ((FILTER) == HRTIM_EVENTFILTER_1) || \ + ((FILTER) == HRTIM_EVENTFILTER_2) || \ + ((FILTER) == HRTIM_EVENTFILTER_3) || \ + ((FILTER) == HRTIM_EVENTFILTER_4) || \ + ((FILTER) == HRTIM_EVENTFILTER_5) || \ + ((FILTER) == HRTIM_EVENTFILTER_6) || \ + ((FILTER) == HRTIM_EVENTFILTER_7) || \ + ((FILTER) == HRTIM_EVENTFILTER_8) || \ + ((FILTER) == HRTIM_EVENTFILTER_9) || \ + ((FILTER) == HRTIM_EVENTFILTER_10) || \ + ((FILTER) == HRTIM_EVENTFILTER_11) || \ + ((FILTER) == HRTIM_EVENTFILTER_12) || \ + ((FILTER) == HRTIM_EVENTFILTER_13) || \ + ((FILTER) == HRTIM_EVENTFILTER_14) || \ + ((FILTER) == HRTIM_EVENTFILTER_15)))) #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ - (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) + (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ - (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ - ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL) || \ - ((FAULTSOURCE) == HRTIM_FAULTSOURCE_EEVINPUT)) + (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ + ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL) || \ + ((FAULTSOURCE) == HRTIM_FAULTSOURCE_EEVINPUT)) #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ - (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ - ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) + (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ + ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ - (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ - ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) + (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ + ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) #define IS_HRTIM_FAULTBLANKNGMODE(FAULTBLANKINGMODE)\ - (((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_RSTALIGNED) || \ - ((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_MOVING)) + (((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_RSTALIGNED) || \ + ((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_MOVING)) #define IS_HRTIM_FAULTBLANKING(FAULTBLANKINGCTL)\ - (((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_DISABLED) || \ - ((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_ENABLED)) + (((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_DISABLED) || \ + ((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_ENABLED)) #define IS_HRTIM_FAULTCOUNTERRST(HRTIM_FAULTCOUNTERRST)\ - (((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_UNCONDITIONAL) || \ - ((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_CONDITIONAL)) + (((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_UNCONDITIONAL) || \ + ((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_CONDITIONAL)) #define IS_HRTIM_FAULTBLANKINGCTL(FAULTBLANKINGCTL)\ - (((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_DISABLED) || \ - ((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_ENABLED)) + (((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_DISABLED) || \ + ((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_ENABLED)) #define IS_HRTIM_FAULTCOUNTER(FAULTCOUNTER)\ - (((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_NONE) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_1) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_2) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_3) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_4) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_5) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_6) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_7) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_8) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_9) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_10) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_11) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_12) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_13) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_14) || \ - ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_15)) + (((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_NONE) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_1) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_2) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_3) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_4) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_5) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_6) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_7) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_8) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_9) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_10) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_11) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_12) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_13) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_14) || \ + ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_15)) #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ - (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) + (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\ - (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ - ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) + (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ + ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\ - (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) + (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) #define IS_HRTIM_BURSTMODE(BURSTMODE)\ - (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ - ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) + (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ + ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\ - (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_F) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) + (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_F) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\ - (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) + (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\ - (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ - ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) + (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ + ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\ - (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) + (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\ - (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_F)) + (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_F)) #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ - (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_1) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_2) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_3)) + (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_1) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_2) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_3)) #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ - ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U))) + ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U))) #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ - (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ - ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) + (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ + ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFF80U) == 0x00000000U) @@ -3663,29 +3664,29 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_COUNTER_MODE_UP(__HANDLE__, __TIMERS__)\ do {\ if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ - {\ - CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ - }\ + {\ + CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ - {\ - CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ - }\ + {\ + CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ - {\ - CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ - }\ + {\ + CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ - {\ - CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ - }\ + {\ + CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ - {\ - CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ - }\ + {\ + CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ - {\ - CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ - }\ + {\ + CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ + }\ } while(0U) /** @@ -3704,32 +3705,32 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_COUNTER_MODE_UPDOWN(__HANDLE__, __TIMERS__)\ do {\ if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ - {\ - SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ - }\ + {\ + SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ - {\ - SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ - }\ + {\ + SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ - {\ - SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ - }\ + {\ + SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ - {\ - SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ - }\ + {\ + SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ - {\ - SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ - }\ + {\ + SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ - {\ - SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ - }\ + {\ + SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ + }\ } while(0U) - /** +/** * @brief swap the output of the timer * HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2, * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1 @@ -3743,33 +3744,33 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval none - */ + */ #define __HAL_HRTIM_TIMER_OUTPUT_SWAP(__HANDLE__, __TIMERS__)\ do {\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ - {\ - SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \ - }\ + {\ + SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ - {\ - SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \ - }\ + {\ + SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ - {\ - SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \ - }\ + {\ + SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ - {\ - SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \ - }\ + {\ + SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ - {\ - SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \ - }\ + {\ + SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\ - {\ - SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \ - }\ + {\ + SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \ + }\ } while(0U) /** @@ -3791,29 +3792,29 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_TIMER_OUTPUT_NOSWAP(__HANDLE__, __TIMERS__)\ do {\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ - {\ - CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \ - }\ + {\ + CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ - {\ - CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \ - }\ + {\ + CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ - {\ - CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \ - }\ + {\ + CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ - {\ - CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \ - }\ + {\ + CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ - {\ - CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \ - }\ + {\ + CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\ - {\ - CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \ - }\ + {\ + CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \ + }\ } while(0U) /** @brief Reset HRTIM handle state @@ -3822,10 +3823,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET) #endif @@ -3856,51 +3857,51 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\ do {\ if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ - }\ + {\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TFOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TFOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_F);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_F);\ }\ + }\ } while(0U) /** @brief Enables the External Event counter @@ -3924,68 +3925,68 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ + }\ if (((__EVENT__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ + }\ }\ } while(0U) @@ -4010,68 +4011,68 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ + }\ }\ } while(0U) @@ -4096,68 +4097,68 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ + }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ {\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ + }\ if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ - {\ - ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ - }\ + {\ + ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ + }\ }\ } while(0U) @@ -4193,8 +4194,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable * @retval None */ -#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__)) -#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ + |= (__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ + &= ~(__INTERRUPT__)) /** @brief Enables or disables the specified HRTIM Timerx interrupts. * @param __HANDLE__ specifies the HRTIM Handle. @@ -4235,7 +4238,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled. * @param __HANDLE__ specifies the HRTIM Handle. @@ -4250,7 +4254,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled. * @param __HANDLE__ specifies the HRTIM Handle. @@ -4280,7 +4285,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clears the specified HRTIM common pending flag. * @param __HANDLE__ specifies the HRTIM Handle. @@ -4312,7 +4318,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag * @retval None */ -#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR\ + = (__INTERRUPT__)) /** @brief Clears the specified HRTIM Timerx pending flag. * @param __HANDLE__ specifies the HRTIM Handle. @@ -4335,7 +4342,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag * @retval None */ -#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__)) +#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ + = (__INTERRUPT__)) /* DMA HANDLING */ /** @brief Enables or disables the specified HRTIM Master timer DMA requests. @@ -4378,14 +4386,18 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__)) #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__)) -#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR &\ + (__FLAG__)) == (__FLAG__)) #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__)) -#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR &\ + (__FLAG__)) == (__FLAG__)) #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__)) -#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__)) -#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__)) +#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR &\ + (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ + = (__FLAG__)) /** @brief Sets the HRTIM timer Counter Register value on runtime * @param __HANDLE__ HRTIM Handle. @@ -4486,16 +4498,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @retval None */ #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \ - (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ - : \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) + (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ + : \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) /** @brief Gets the HRTIM timer Compare Register value on runtime * @param __HANDLE__ HRTIM Handle. @@ -4511,16 +4523,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @retval Compare value */ #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \ - (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ - ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ - : \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ - ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) + (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ + ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ + : \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ + ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) /** * @brief Enables the Fault Counter @@ -4540,27 +4552,27 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< do {\ if (((__FAULT__) & HRTIM_FAULT_1) == HRTIM_FAULT_1)\ {\ - ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT1BLKE;\ + ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT1BLKE;\ }\ if (((__FAULT__) & HRTIM_FAULT_2) == HRTIM_FAULT_2)\ {\ - ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT2BLKE;\ + ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT2BLKE;\ }\ if (((__FAULT__) & HRTIM_FAULT_3) == HRTIM_FAULT_3)\ {\ - ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT3BLKE;\ + ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT3BLKE;\ }\ if (((__FAULT__) & HRTIM_FAULT_4) == HRTIM_FAULT_4)\ {\ - ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT4BLKE;\ + ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT4BLKE;\ }\ if (((__FAULT__) & HRTIM_FAULT_5) == HRTIM_FAULT_5)\ {\ - ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT5BLKE;\ + ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT5BLKE;\ }\ if (((__FAULT__) & HRTIM_FAULT_6) == HRTIM_FAULT_6)\ {\ - ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT6BLKE;\ + ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT6BLKE;\ }\ } while(0U) @@ -4581,27 +4593,27 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< do {\ if (((__FAULT__) & HRTIM_FAULT_1) == HRTIM_FAULT_1)\ {\ - ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT1BLKE;\ + ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT1BLKE;\ }\ if (((__FAULT__) & HRTIM_FAULT_2) == HRTIM_FAULT_2)\ {\ - ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT2BLKE;\ + ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT2BLKE;\ }\ if (((__FAULT__) & HRTIM_FAULT_3) == HRTIM_FAULT_3)\ {\ - ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT3BLKE;\ + ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT3BLKE;\ }\ if (((__FAULT__) & HRTIM_FAULT_4) == HRTIM_FAULT_4)\ {\ - ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT4BLKE;\ + ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT4BLKE;\ }\ if (((__FAULT__) & HRTIM_FAULT_5) == HRTIM_FAULT_5)\ {\ - ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT5BLKE;\ + ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT5BLKE;\ }\ if (((__FAULT__) & HRTIM_FAULT_6) == HRTIM_FAULT_6)\ {\ - ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT6BLKE;\ + ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT6BLKE;\ }\ } while(0U) @@ -4611,17 +4623,17 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< /* Exported functions --------------------------------------------------------*/ /** @addtogroup HRTIM_Exported_Functions -* @{ -*/ + * @{ + */ /** @addtogroup HRTIM_Exported_Functions_Group1 -* @{ -*/ + * @{ + */ /* Initialization and Configuration functions ********************************/ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim); -HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim); +HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim); void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim); @@ -4629,7 +4641,7 @@ void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim, uint32_t CalibrationRate); @@ -4645,272 +4657,272 @@ HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group2 -* @{ -*/ + * @{ + */ /* Simple time base related functions *****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group3 -* @{ -*/ + * @{ + */ /* Simple output compare related functions ************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); + uint32_t TimerIdx, + uint32_t OCChannel, + const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t OCChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group4 -* @{ -*/ + * @{ + */ /* Simple PWM output related functions ****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); + uint32_t TimerIdx, + uint32_t PWMChannel, + const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t PWMChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group5 -* @{ -*/ + * @{ + */ /* Simple capture related functions *******************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); + uint32_t TimerIdx, + uint32_t CaptureChannel, + const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t CaptureChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group6 -* @{ -*/ + * @{ + */ /* Simple one pulse related functions *****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); + uint32_t TimerIdx, + uint32_t OnePulseChannel, + const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group7 -* @{ -*/ + * @{ + */ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, - const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); + const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg); HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef* pEventCfg); + const HRTIM_EventCfgTypeDef *pEventCfg); HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultCfgTypeDef* pFaultCfg); + const HRTIM_FaultCfgTypeDef *pFaultCfg); HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); -HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * hhrtim, - uint32_t Fault, - const HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg); +HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef *hhrtim, + uint32_t Fault, + const HRTIM_FaultBlankingCfgTypeDef *pFaultBlkCfg); -HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg); + const HRTIM_FaultBlankingCfgTypeDef *pFaultBlkCfg); -HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault); -HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers); -void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers); +void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, uint32_t Faults, uint32_t Enable); HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); + const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg); -HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t ADCTrigger, - uint32_t Postscaler); +HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t ADCTrigger, + uint32_t Postscaler); -HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t RollOverCfg); +HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t RollOverCfg); -HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers); +HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers); -HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers); +HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group8 -* @{ -*/ + * @{ + */ /* Waveform related functions *************************************************/ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef *pTimerCfg); -HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - const HRTIM_TimerCtlTypeDef * pTimerCtl); +HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + const HRTIM_TimerCtlTypeDef *pTimerCtl); -HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - const HRTIM_TimerCtlTypeDef * pTimerCtl); +HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + const HRTIM_TimerCtlTypeDef *pTimerCtl); HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - const HRTIM_CompareCfgTypeDef* pCompareCfg); + const HRTIM_CompareCfgTypeDef *pCompareCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - const HRTIM_CaptureCfgTypeDef* pCaptureCfg); + const HRTIM_CaptureCfgTypeDef *pCaptureCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg); + const HRTIM_OutputCfgTypeDef *pOutputCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -4920,32 +4932,32 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); + const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg); -HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t EventCounter, - const HRTIM_ExternalEventCfgTypeDef* pTimerExternalEventCfg); +HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t EventCounter, + const HRTIM_ExternalEventCfgTypeDef *pTimerExternalEventCfg); -HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t EventCounter); +HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t EventCounter); -HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t EventCounter); +HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t EventCounter); -HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t EventCounter); +HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t EventCounter); HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); + const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg); HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); + const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg); HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -4953,22 +4965,22 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart); @@ -4997,7 +5009,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, uint32_t BurstBufferLength); HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); @@ -5007,28 +5019,28 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group9 -* @{ -*/ + * @{ + */ /* HRTIM peripheral state functions */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim); +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim); -uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit); -uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureUnit); +uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureUnit); -HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureUnit); +HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureUnit); uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); -uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); @@ -5049,8 +5061,8 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group10 -* @{ -*/ + * @{ + */ /* IRQ handler */ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); @@ -5069,50 +5081,50 @@ void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim); /* Timer events related callback functions */ void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim); #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_TIMxCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_nand.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_nand.h index 6206a559e..de078405b 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_nand.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_nand.h @@ -194,7 +194,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig); HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_opamp_ex.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_opamp_ex.h index 72d48cf90..7e9fea644 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_opamp_ex.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_opamp_ex.h @@ -59,7 +59,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA #elif defined(STM32G491xx) || defined(STM32G4A1xx) HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp6); -#endif +#elif defined(STM32G411xB) || defined(STM32G411xC) +HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1); +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /** * @} diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_rcc_ex.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_rcc_ex.h index 10206ee17..ec456f38b 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_rcc_ex.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_rcc_ex.h @@ -1431,6 +1431,20 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined(STM32G411xB) || defined(STM32G411xC) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32G414xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_spi.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_spi.h index fbfb757b9..ac61371f2 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_spi.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_spi.h @@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_tim.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_tim.h index 034b6ad42..df1ba620c 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_tim.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_hal_tim.h @@ -1992,9 +1992,11 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ - (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ - ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + ((READ_BIT((__HANDLE__)->Instance->CR1, TIM_CR1_DITHEN) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x000FFFEFU))) : \ + ((__PERIOD__) > 0U )) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_adc.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_adc.h index 5621f09d3..72c7104aa 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_adc.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_adc.h @@ -2873,7 +2873,7 @@ Refer to device datasheet for ADC5 & OPAMP5 availability */ ) \ ) \ ) -#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ @@ -2891,7 +2891,7 @@ Refer to device datasheet for ADC5 & OPAMP5 availability */ ) \ ) \ ) -#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_dac.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_dac.h index 7bad679f7..47f496402 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_dac.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_dac.h @@ -1297,8 +1297,8 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, { MODIFY_REG(DACx->STMODR, DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), - (((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos) - << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); + ( ((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos) + << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) )); } /** @@ -1396,7 +1396,7 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, { MODIFY_REG(DACx->STMODR, DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), - (((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos) + ( ((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) )); } diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_fmc.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_fmc.h index bddf9677d..9a4d75dc4 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_fmc.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_fmc.h @@ -156,74 +156,75 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device + by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ + This parameter can be a value of @ref FMC_Write_FIFO */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ + This parameter can be a value of @ref FMC_Page_Size */ uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number - This parameter can be a value of @ref FMC_Byte_Lane */ + This parameter can be a value of @ref FMC_Byte_Lane */ FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank for PSRAM refresh. - This parameter can be set to ENABLE or DISABLE */ + This parameter can be set to ENABLE or DISABLE */ uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous accesses, valid only if MaxChipSelectPulse is ENABLE. This parameter can be a value between Min_Data = 1 and Max_Data = 65535. - @note: This parameter is common to all NSBank. */ + @note: This parameter is common to all NSBank. */ } FMC_NORSRAM_InitTypeDef; /** @@ -272,7 +273,7 @@ typedef struct in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ + This parameter can be a value of @ref FMC_Access_Mode */ } FMC_NORSRAM_TimingTypeDef; #endif /* FMC_BANK1 */ @@ -779,11 +780,11 @@ typedef struct * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); + const FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); @@ -811,11 +812,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -826,7 +827,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); /** * @} @@ -837,7 +838,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u #endif /* FMC_BANK3 */ - /** * @} */ diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_hrtim.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_hrtim.h index 7b2a7dbec..22dceb4dd 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_hrtim.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_hrtim.h @@ -1256,7 +1256,7 @@ static const uint32_t REG_MASK_TAB_CPT[] = #define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */ #define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */ #define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\ - | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ + | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ /** * @} */ @@ -2839,9 +2839,9 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef *HRTIMx, __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src) { __IO uint32_t *padcur = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) + - REG_OFFSET_TAB_ADCUR[ADCTrig])); + REG_OFFSET_TAB_ADCUR[ADCTrig])); __IO uint32_t *padcer = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCER[ADCTrig])); + REG_OFFSET_TAB_ADCER[ADCTrig])); MODIFY_REG(*padcur, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig])); MODIFY_REG(*padcer, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig])); } @@ -2886,7 +2886,7 @@ __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCT __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update) { __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) + - REG_OFFSET_TAB_ADCUR[ADCTrig])); + REG_OFFSET_TAB_ADCUR[ADCTrig])); MODIFY_REG(*preg, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig])); } @@ -2926,7 +2926,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t A __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) + - REG_OFFSET_TAB_ADCUR[ADCTrig])); + REG_OFFSET_TAB_ADCUR[ADCTrig])); return (READ_BIT(*preg, (REG_MASK_TAB_ADCUR[ADCTrig])) >> REG_SHIFT_TAB_ADCUR[ADCTrig]); } @@ -3225,7 +3225,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) { __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCER[ADCTrig])); + REG_OFFSET_TAB_ADCER[ADCTrig])); MODIFY_REG(*preg, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig])); } @@ -3525,7 +3525,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCER[ADCTrig])); + REG_OFFSET_TAB_ADCER[ADCTrig])); return (READ_BIT(*preg, (REG_MASK_TAB_ADCER[ADCTrig])) >> REG_SHIFT_TAB_ADCER[ADCTrig]); } @@ -3936,7 +3936,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_RSYNCU); /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */ } @@ -3960,7 +3960,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef *HRTIMx, uin { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_RSYNCU); /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */ @@ -3985,7 +3985,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResyncUpdate(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMCR_RSYNCU) == (HRTIM_TIMCR_RSYNCU)) ? 1UL : 0UL); /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */ @@ -4499,7 +4499,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -4520,7 +4520,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -4541,7 +4541,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL); } @@ -4573,7 +4573,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); } @@ -4603,7 +4603,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift); } @@ -4634,7 +4634,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); } @@ -4657,7 +4657,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); } @@ -4681,7 +4681,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); } @@ -4704,7 +4704,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uin { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MPER_MPER)); } @@ -4728,7 +4728,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); } @@ -4751,7 +4751,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MREP_MREP)); } @@ -4777,7 +4777,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); } @@ -4802,7 +4802,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); } @@ -4828,7 +4828,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); } @@ -4853,7 +4853,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); } @@ -4879,7 +4879,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); } @@ -4904,7 +4904,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); } @@ -4930,7 +4930,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); } @@ -4955,7 +4955,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); } @@ -5047,7 +5047,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); WRITE_REG(*pReg, ResetTrig); } @@ -5132,7 +5132,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -5153,7 +5153,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -5176,7 +5176,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(const HRTIM_TypeDef * { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_CPT1R_DIR) >> HRTIM_CPT1R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos); } @@ -5197,7 +5197,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -5220,7 +5220,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2Direction(const HRTIM_TypeDef * { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_CPT2R_DIR) >> HRTIM_CPT2R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos); } @@ -5318,7 +5318,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); uint32_t cfg1 = (uint32_t)(CaptureTrig & 0x0000000000000FFFU); uint32_t cfg2 = (uint32_t)((CaptureTrig & 0xFFFFF00F00000000U) >> 32U); @@ -5421,7 +5421,7 @@ __STATIC_INLINE uint64_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - (uint32_t)REG_OFFSET_TAB_TIMER[iTimer & 0x7U] + (CaptureUnit * 4U))); + (uint32_t)REG_OFFSET_TAB_TIMER[iTimer & 0x7U] + (CaptureUnit * 4U))); uint64_t cfg; uint32_t CaptureTrig = READ_REG(*pReg); @@ -5448,7 +5448,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -5469,7 +5469,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -5490,7 +5490,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRT { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL); } @@ -5536,7 +5536,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); } @@ -5578,7 +5578,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); } @@ -5600,7 +5600,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -5622,7 +5622,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -5643,7 +5643,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL); } @@ -5665,7 +5665,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_BIAR); } @@ -5687,7 +5687,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_BIAR); } @@ -5708,7 +5708,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledBIAR(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_BIAR) == (HRTIM_OUTR_BIAR)) ? 1UL : 0UL); } @@ -5742,7 +5742,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, Faults); } @@ -5775,7 +5775,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, Faults); } @@ -5808,7 +5808,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL); } @@ -5831,7 +5831,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); } @@ -6014,7 +6014,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeD { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); } @@ -6037,7 +6037,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); } @@ -6138,7 +6138,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6236,7 +6236,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6283,7 +6283,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6327,7 +6327,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *H uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6354,7 +6354,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, ui { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_TRGHLF, Mode); } @@ -6380,7 +6380,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetTriggeredHalfMode(const HRTIM_TypeDef * { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(* pReg, HRTIM_TIMCR2_TRGHLF)); } @@ -6407,7 +6407,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP1, Mode); } @@ -6433,7 +6433,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp1Mode(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP1)); } @@ -6460,7 +6460,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP3, (Mode)); } @@ -6486,7 +6486,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp3Mode(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP3)); } @@ -6514,7 +6514,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_ROM, (Mode << HRTIM_TIMCR2_ROM_Pos)); } @@ -6538,7 +6538,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRollOverMode(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_ROM) >> HRTIM_TIMCR2_ROM_Pos); } @@ -6565,7 +6565,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_FEROM, (Mode << HRTIM_TIMCR2_FEROM_Pos)); } @@ -6589,7 +6589,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetFaultEventRollOverMode(const HRTIM_Type { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_FEROM) >> HRTIM_TIMCR2_FEROM_Pos); } @@ -6616,7 +6616,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint3 { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_BMROM, (Mode << HRTIM_TIMCR2_BMROM_Pos)); } @@ -6640,7 +6640,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBMRollOverMode(const HRTIM_TypeDef *HRT { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_BMROM) >> HRTIM_TIMCR2_BMROM_Pos); } @@ -6667,7 +6667,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_ADROM, (Mode << HRTIM_TIMCR2_ADROM_Pos)); } @@ -6691,7 +6691,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_ADROM) >> HRTIM_TIMCR2_ADROM_Pos); } @@ -6720,7 +6720,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_OUTROM, (Mode << HRTIM_TIMCR2_OUTROM_Pos)); } @@ -6744,7 +6744,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetOutputRollOverMode(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_OUTROM) >> HRTIM_TIMCR2_OUTROM_Pos); } @@ -6774,7 +6774,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_UDM, Mode); } @@ -6798,7 +6798,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCountingMode(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_UDM)); } @@ -6824,7 +6824,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDR, Mode); } @@ -6847,7 +6847,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacResetTrigger(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDR)); } @@ -6871,7 +6871,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDS, Mode); } @@ -6894,7 +6894,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacStepTrigger(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDS)); } @@ -6916,7 +6916,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDualDacTrigger(HRTIM_TypeDef *HRTIMx, ui { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(* pReg, HRTIM_TIMCR2_DCDE); } @@ -6937,7 +6937,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(* pReg, HRTIM_TIMCR2_DCDE); } @@ -6958,7 +6958,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDualDacTrigger(const HRTIM_TypeDe { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(* pReg, HRTIM_TIMCR2_DCDE) == (HRTIM_TIMCR2_DCDE)) ? 1UL : 0UL); } @@ -7296,7 +7296,7 @@ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); } @@ -7326,7 +7326,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); } @@ -7355,7 +7355,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); } @@ -7377,7 +7377,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); } @@ -7398,7 +7398,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTR)); } @@ -7422,7 +7422,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); } @@ -7445,7 +7445,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); } @@ -7467,7 +7467,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); } @@ -7488,7 +7488,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); } @@ -7512,7 +7512,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); } @@ -7535,7 +7535,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); } @@ -7556,7 +7556,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRLK); } @@ -7577,7 +7577,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRSLK); } @@ -7598,7 +7598,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFLK); } @@ -7619,7 +7619,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFSLK); } @@ -7656,7 +7656,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); } @@ -7697,7 +7697,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); } @@ -7734,7 +7734,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); } @@ -7767,7 +7767,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); } @@ -7796,7 +7796,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); } @@ -7836,7 +7836,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); } @@ -7873,7 +7873,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); } @@ -8050,7 +8050,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, SetSrc); } @@ -8218,7 +8218,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIM { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -8387,7 +8387,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, ResetSrc); } @@ -8555,7 +8555,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRT { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -8600,7 +8600,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]), (Configuration << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -8632,7 +8632,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -8662,7 +8662,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, u { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -8694,7 +8694,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput]))); } @@ -8724,7 +8724,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, u { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -8757,7 +8757,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -8787,7 +8787,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -8822,7 +8822,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -8854,7 +8854,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -8886,7 +8886,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -8916,7 +8916,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -8948,7 +8948,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -8978,7 +8978,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -9009,7 +9009,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HR { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1STAT_Pos); } @@ -9049,7 +9049,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); + REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); SET_BIT(*pReg, HRTIM_SET1R_SST); } @@ -9079,7 +9079,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1CPY_Pos); } @@ -9160,7 +9160,7 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]), (Configuration << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -9200,7 +9200,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -9238,7 +9238,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -9277,7 +9277,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -9313,7 +9313,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -9353,7 +9353,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -9391,7 +9391,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -9424,7 +9424,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -9455,7 +9455,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -9655,9 +9655,9 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); - uint64_t cfg = ( (uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 bit */ + uint64_t cfg = ((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 bit */ (((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */ - uint64_t mask = ( (uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe bit 0 */ + uint64_t mask = ((uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe bit 0 */ (((uint64_t)(HRTIM_FLTINR2_FLT1SRC_1) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe bit 1 */ MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg)); @@ -9937,7 +9937,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -9963,7 +9963,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -9989,7 +9989,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -10016,7 +10016,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uin { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) == (HRTIM_FLTINR1_FLT1E)) ? 1UL : 0UL); } @@ -10043,7 +10043,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_EnableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]); } @@ -10069,7 +10069,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); CLEAR_BIT(*pReg, (HRTIM_FLTINR3_FLT1BLKE << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -10095,7 +10095,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabledBlanking(const HRTIM_TypeDef *HRT { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); uint32_t temp; /* MISRAC-2012 compliance */ temp = READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]; @@ -10131,7 +10131,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1BLKS << REG_SHIFT_TAB_FLTxE[iFault]), (Source << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -10157,7 +10157,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetBlankingSrc(const HRTIM_TypeDef *HRTIMx { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKS) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault])); } @@ -10185,7 +10185,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef *HRTIMx, uin { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1CNT << REG_SHIFT_TAB_FLTxE[iFault]), (Threshold << REG_SHIFT_TAB_FLTxCNT[iFault])); } @@ -10211,7 +10211,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetCounterThreshold(const HRTIM_TypeDef *H { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CNT) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxCNT[iFault]); } @@ -10240,7 +10240,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t F { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1RSTM << REG_SHIFT_TAB_FLTxE[iFault]), Mode << REG_SHIFT_TAB_FLTxE[iFault]); } @@ -10269,7 +10269,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetResetMode(const HRTIM_TypeDef *HRTIMx, { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1RSTM) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -10295,7 +10295,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_ResetCounter(HRTIM_TypeDef *HRTIMx, uint32_t F { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CRES) << REG_SHIFT_TAB_FLTxE[iFault]); } @@ -11018,7 +11018,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MUPD); } @@ -11041,7 +11041,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL); } @@ -11065,7 +11065,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MREP); } @@ -11089,7 +11089,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL); } @@ -11113,7 +11113,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP1); } @@ -11136,7 +11136,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL); } @@ -11160,7 +11160,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP2); } @@ -11183,7 +11183,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL); } @@ -11207,7 +11207,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP3); } @@ -11230,7 +11230,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL); } @@ -11254,7 +11254,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP4); } @@ -11277,7 +11277,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL); } @@ -11299,7 +11299,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); } @@ -11320,7 +11320,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL); } @@ -11342,7 +11342,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); } @@ -11363,7 +11363,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL); } @@ -11385,7 +11385,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET1C); } @@ -11406,7 +11406,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL); } @@ -11428,7 +11428,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST1C); } @@ -11449,7 +11449,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL); } @@ -11471,7 +11471,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET2C); } @@ -11492,7 +11492,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL); } @@ -11514,7 +11514,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST2C); } @@ -11535,7 +11535,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL); } @@ -11557,7 +11557,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RSTC); } @@ -11578,7 +11578,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL); } @@ -11600,7 +11600,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC); } @@ -11621,7 +11621,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL); } @@ -11983,7 +11983,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -12006,7 +12006,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -12029,7 +12029,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL); } @@ -12053,7 +12053,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -12076,7 +12076,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -12099,7 +12099,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL); } @@ -12123,7 +12123,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -12146,7 +12146,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -12169,7 +12169,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL); } @@ -12193,7 +12193,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -12216,7 +12216,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -12239,7 +12239,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL); } @@ -12263,7 +12263,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -12286,7 +12286,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -12309,7 +12309,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL); } @@ -12333,7 +12333,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -12356,7 +12356,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -12379,7 +12379,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL); } @@ -12401,7 +12401,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -12422,7 +12422,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -12443,7 +12443,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL); } @@ -12465,7 +12465,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -12486,7 +12486,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -12507,7 +12507,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL); } @@ -12529,7 +12529,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -12550,7 +12550,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -12571,7 +12571,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL); } @@ -12593,7 +12593,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -12614,7 +12614,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -12635,7 +12635,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL); } @@ -12657,7 +12657,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -12678,7 +12678,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -12699,7 +12699,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL); } @@ -12721,7 +12721,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -12742,7 +12742,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -12763,7 +12763,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL); } @@ -12785,7 +12785,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -12806,7 +12806,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -12827,7 +12827,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL); } @@ -12849,7 +12849,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -12870,7 +12870,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -12891,7 +12891,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL); } @@ -12956,7 +12956,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -12979,7 +12979,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32 { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -13002,7 +13002,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL); } @@ -13026,7 +13026,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -13049,7 +13049,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -13072,7 +13072,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL); } @@ -13096,7 +13096,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -13119,7 +13119,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -13142,7 +13142,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL); } @@ -13166,7 +13166,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -13189,7 +13189,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -13212,7 +13212,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL); } @@ -13236,7 +13236,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -13259,7 +13259,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -13282,7 +13282,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL); } @@ -13306,7 +13306,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -13329,7 +13329,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -13352,7 +13352,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL); } @@ -13374,7 +13374,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -13395,7 +13395,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -13416,7 +13416,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL); } @@ -13438,7 +13438,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -13459,7 +13459,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -13480,7 +13480,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL); } @@ -13502,7 +13502,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -13523,7 +13523,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -13544,7 +13544,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL); } @@ -13566,7 +13566,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -13587,7 +13587,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -13608,7 +13608,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL); } @@ -13630,7 +13630,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -13651,7 +13651,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -13672,7 +13672,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL); } @@ -13694,7 +13694,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -13715,7 +13715,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -13736,7 +13736,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL); } @@ -13758,7 +13758,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -13779,7 +13779,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -13800,7 +13800,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL); } @@ -13822,7 +13822,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -13843,7 +13843,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32 { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -13864,7 +13864,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL); } @@ -13877,7 +13877,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HR /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions * @{ */ -ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); +ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx); /** * @} */ @@ -13903,4 +13903,3 @@ ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); #endif /* STM32G4xx_LL_HRTIM_H */ - diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_rtc.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_rtc.h index 7c3099f66..e70347dcb 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_rtc.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_rtc.h @@ -445,17 +445,17 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK * @{ */ -#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ -#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ #if (RTC_TAMP_NB == 3) -#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ #elif (RTC_TAMP_NB == 8) -#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ -#define LL_RTC_TAMPER_MASK_TAMPER4 TAMP_CR2_TAMP4MF /*!< Tamper 4 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ -#define LL_RTC_TAMPER_MASK_TAMPER5 TAMP_CR2_TAMP5MF /*!< Tamper 5 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ -#define LL_RTC_TAMPER_MASK_TAMPER6 TAMP_CR2_TAMP6MF /*!< Tamper 6 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ -#define LL_RTC_TAMPER_MASK_TAMPER7 TAMP_CR2_TAMP7MF /*!< Tamper 7 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ -#define LL_RTC_TAMPER_MASK_TAMPER8 TAMP_CR2_TAMP8MF /*!< Tamper 8 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_RTC_TAMPER_MASK_TAMPER4 TAMP_CR2_TAMP4MSK /*!< Tamper 4 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER5 TAMP_CR2_TAMP5MSK /*!< Tamper 5 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_RTC_TAMPER_MASK_TAMPER6 TAMP_CR2_TAMP6MSK /*!< Tamper 6 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER7 TAMP_CR2_TAMP7MSK /*!< Tamper 7 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_RTC_TAMPER_MASK_TAMPER8 TAMP_CR2_TAMP8MSK /*!< Tamper 8 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ #else #warning "RTC_TAMP_NB is not correct" #endif /* (RTC_TAMP_NB) */ diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_spi.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_spi.h index 62d903e78..ec201ba9c 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_spi.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_spi.h @@ -55,53 +55,66 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -378,7 +391,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -408,7 +421,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); } @@ -436,7 +449,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); } @@ -465,7 +478,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); } @@ -494,7 +507,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); } @@ -534,7 +547,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); } @@ -562,7 +575,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); } @@ -599,7 +612,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); } @@ -648,7 +661,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) * @arg @ref LL_SPI_DATAWIDTH_15BIT * @arg @ref LL_SPI_DATAWIDTH_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); } @@ -675,7 +688,7 @@ __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thres * @arg @ref LL_SPI_RX_FIFO_TH_HALF * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); } @@ -719,7 +732,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } @@ -747,7 +760,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) * @arg @ref LL_SPI_CRC_8BIT * @arg @ref LL_SPI_CRC_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); } @@ -782,7 +795,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPR)); } @@ -793,7 +806,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRCR)); } @@ -804,7 +817,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRCR)); } @@ -845,7 +858,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); @@ -883,7 +896,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); } @@ -902,7 +915,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } @@ -913,7 +926,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } @@ -924,7 +937,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } @@ -935,7 +948,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -946,7 +959,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -964,7 +977,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } @@ -975,7 +988,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } @@ -990,7 +1003,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_RX_FIFO_HALF_FULL * @arg @ref LL_SPI_RX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); } @@ -1005,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_TX_FIFO_HALF_FULL * @arg @ref LL_SPI_TX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); } @@ -1045,7 +1058,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->DR; @@ -1061,7 +1074,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -1078,7 +1091,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1112,7 +1126,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1150,7 +1165,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } @@ -1161,7 +1176,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } @@ -1172,7 +1187,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } @@ -1213,7 +1228,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } @@ -1246,7 +1261,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } @@ -1273,7 +1288,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); } @@ -1300,7 +1315,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); } @@ -1311,7 +1326,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) { return (uint32_t) &(SPIx->DR); } @@ -1388,7 +1403,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); @@ -1656,7 +1671,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); } @@ -1689,7 +1704,7 @@ __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat * @arg @ref LL_I2S_DATAFORMAT_24B * @arg @ref LL_I2S_DATAFORMAT_32B */ -__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); } @@ -1716,7 +1731,7 @@ __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_I2S_POLARITY_LOW * @arg @ref LL_I2S_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); } @@ -1751,7 +1766,7 @@ __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_I2S_STANDARD_PCM_SHORT * @arg @ref LL_I2S_STANDARD_PCM_LONG */ -__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); } @@ -1782,7 +1797,7 @@ __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_I2S_MODE_MASTER_TX * @arg @ref LL_I2S_MODE_MASTER_RX */ -__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); } @@ -1805,7 +1820,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t Presca * @param SPIx SPI Instance * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); } @@ -1832,7 +1847,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t Presc * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); } @@ -1865,7 +1880,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); } @@ -1899,7 +1914,7 @@ __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); } @@ -1919,7 +1934,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_RXNE(SPIx); } @@ -1930,7 +1945,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_TXE(SPIx); } @@ -1941,7 +1956,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_BSY(SPIx); } @@ -1952,7 +1967,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_OVR(SPIx); } @@ -1963,7 +1978,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); } @@ -1974,7 +1989,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_FRE(SPIx); } @@ -1988,7 +2003,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); } @@ -2010,7 +2025,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -2023,7 +2038,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) { LL_SPI_ClearFlag_FRE(SPIx); } @@ -2110,7 +2125,7 @@ __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_ERR(SPIx); } @@ -2121,7 +2136,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_RXNE(SPIx); } @@ -2132,7 +2147,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_TXE(SPIx); } @@ -2173,7 +2188,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_RX(SPIx); } @@ -2206,7 +2221,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_TX(SPIx); } @@ -2251,7 +2266,7 @@ __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_system.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_system.h index 87b6f2f00..dca87bcb8 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_system.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_system.h @@ -187,7 +187,6 @@ extern "C" { /** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCMSRAM WRP * @{ */ -#if defined(CCMSRAM_BASE) #define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */ @@ -198,7 +197,6 @@ extern "C" { #define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */ -#endif /* CCMSRAM_BASE */ #if defined(SYSCFG_SWPR_PAGE10) #define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */ @@ -210,6 +208,8 @@ extern "C" { #define LL_SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */ +#endif /* SYSCFG_SWPR_PAGE10 */ +#if defined(SYSCFG_SWPR_PAGE20) #define LL_SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */ @@ -222,7 +222,7 @@ extern "C" { #define LL_SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */ -#endif /* SYSCFG_SWPR_PAGE10 */ +#endif /* SYSCFG_SWPR_PAGE20 */ /** * @} */ @@ -758,7 +758,6 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x1FU)); } -#if defined (CCMSRAM_BASE) /** * @brief Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation. This bit is * automatically cleared at the end of the CCMSRAM erase operation.) @@ -784,7 +783,6 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsCCMSRAMEraseOngoing(void) return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMBSY) == (SYSCFG_SCSR_CCMBSY)) ? 1UL : 0UL); } -#endif /* CCMSRAM_BASE */ /** * @brief Set connections to TIM1/8/15/16/17 Break inputs * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n @@ -840,7 +838,6 @@ __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF); } -#if defined(CCMSRAM_BASE) /** * @brief Enable CCMSRAM page write protection * @note Write protection is cleared only by a system reset @@ -909,7 +906,6 @@ __STATIC_INLINE void LL_SYSCFG_UnlockCCMSRAMWRP(void) WRITE_REG(SYSCFG->SKR, 0xCA); WRITE_REG(SYSCFG->SKR, 0x53); } -#endif /* CCMSRAM_BASE */ /** * @} */ diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_ucpd.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_ucpd.h index 0e90d7edc..16d6228da 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_ucpd.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_ucpd.h @@ -1446,10 +1446,10 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx) */ /** - * @brief Check if FRS interrupt + * @brief Check if FRS Event Flag is active * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx) { @@ -1460,7 +1460,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPD * @brief Check if type c event on CC2 * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) { @@ -1471,7 +1471,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * * @brief Check if type c event on CC1 * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) { @@ -1479,10 +1479,21 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * } /** - * @brief Check if Rx message end interrupt + * @brief Check if Rx error flag is active + * @rmtoll SR RXERR LL_UCPD_IsActiveFlag_RxErr + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXERR) == UCPD_SR_RXERR) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx message end flag is active * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx) { @@ -1490,10 +1501,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const } /** - * @brief Check if Rx overrun interrupt + * @brief Check if Rx overrun flag is active * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx) { @@ -1501,10 +1512,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UC } /** - * @brief Check if Rx hard reset interrupt + * @brief Check if Rx hard reset flag is active * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx) { @@ -1512,7 +1523,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const U } /** - * @brief Check if Rx orderset interrupt + * @brief Check if Rx orderset flag is active * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1523,7 +1534,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *con } /** - * @brief Check if Rx non empty interrupt + * @brief Check if Rx non empty flag is active * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1534,7 +1545,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCP } /** - * @brief Check if TX underrun interrupt + * @brief Check if TX underrun flag is active * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1545,7 +1556,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UC } /** - * @brief Check if hard reset sent interrupt + * @brief Check if hard reset sent flag is active * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1556,7 +1567,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *con } /** - * @brief Check if hard reset discard interrupt + * @brief Check if hard reset discard flag is active * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1567,7 +1578,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *con } /** - * @brief Check if Tx message abort interrupt + * @brief Check if Tx message abort flag is active * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1578,7 +1589,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const } /** - * @brief Check if Tx message sent interrupt + * @brief Check if Tx message sent flag is active * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1589,7 +1600,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *cons } /** - * @brief Check if Tx message discarded interrupt + * @brief Check if Tx message discarded flag is active * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1600,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *cons } /** - * @brief Check if Tx data receive interrupt + * @brief Check if Tx data interrupt flag is active * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). diff --git a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_utils.h b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_utils.h index e8c955f10..9fb3ff5cb 100644 --- a/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_utils.h +++ b/stm32cube/stm32g4xx/drivers/include/stm32g4xx_ll_utils.h @@ -160,13 +160,13 @@ typedef struct */ #define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ #define LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U /*!< WLCSP64 package type */ -#if defined (STM32G431xx) || defined (STM32G414xx) || defined (STM32G441xx) || defined (STM32G471xx) || \ - defined (STM32G473xx) || defined (STM32G483xx) || defined (STM32G474xx) || defined (STM32G484xx) +#if defined (STM32G411xB) || defined (STM32G411xC) || defined (STM32G431xx) || defined (STM32G414xx) || defined (STM32G441xx) || \ + defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G483xx) || defined (STM32G474xx) || defined (STM32G484xx) #define LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 0x00000002U /*!< LQFP100 \ LQFP80 package type */ #define LL_UTILS_PACKAGETYPE_LQFP100 LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 /*!< For backward compatibility */ #else #define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ -#endif /* STM32G431xx || STM32G414xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */ +#endif /* STM32G411xB || STM32G411xC || STM32G431xx || STM32G414xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */ #define LL_UTILS_PACKAGETYPE_WLCSP81 0x00000005U /*!< WLCSP81 package type */ #define LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 0x00000007U /*!< LQFP128 \ UFBGA121 package type */ #define LL_UTILS_PACKAGETYPE_LQFP128 LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 /*!< For backward compatibility */ diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal.c index 53d264a71..563b90d0c 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal.c @@ -48,11 +48,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32G4xx HAL Driver version number V1.2.4 + * @brief STM32G4xx HAL Driver version number V1.2.5 */ #define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ -#define __STM32G4xx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */ +#define __STM32G4xx_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */ #define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\ @@ -594,7 +594,6 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void) @endverbatim * @{ */ -#if defined (CCMSRAM_BASE) /** * @brief Start a hardware CCMSRAM erase operation. * @note As long as CCMSRAM is not erased the CCMER bit will be set. @@ -609,7 +608,6 @@ void HAL_SYSCFG_CCMSRAMErase(void) /* Starts a hardware CCMSRAM erase operation*/ SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER); } -#endif /* CCMSRAM_BASE */ /** * @brief Enable the Internal FLASH Bank Swapping. @@ -768,7 +766,6 @@ void HAL_SYSCFG_DisableIOSwitchVDD(void) CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); } -#if defined(CCMSRAM_BASE) /** @brief CCMSRAM page write protection enable * @param Page: This parameter is a long 32bit value and can be a value of @ref SYSCFG_CCMSRAMWRP * @note write protection can only be disabled by a system reset @@ -780,7 +777,6 @@ void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page) SET_BIT(SYSCFG->SWPR, (uint32_t)(Page)); } -#endif /* CCMSRAM_BASE */ /** * @} diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_comp.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_comp.c index 796998dbe..1dc7f91da 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_comp.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_comp.c @@ -900,7 +900,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) if (tmp_comp_exti_flag_set != 0UL) { - /* Clear COMP EXTI line pending bit */ + /* Clear COMP EXTI line pending bit */ #if defined(COMP7) if (tmp_comp_exti_flag_set == 2UL) { diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_crc_ex.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_crc_ex.c index fb4cad65b..aee09bf8b 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_crc_ex.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_dac.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_dac.c index 5c00e03be..662e3bb90 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_dac.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_dac.c @@ -103,7 +103,8 @@ To connect, use sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL; or - sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH; + sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH; (caution: dependence to other parameters, + refer to literal description). *** GPIO configurations guidelines *** ===================== @@ -1175,6 +1176,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } + else + { + /* In case of mode normal and buffer disabled, connection to both on chip periph and external pin is not possible */ + if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_DISABLE) + { + assert_param(sConfig->DAC_ConnectOnChipPeripheral != DAC_CHIPCONNECT_BOTH); + } + } assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat)); diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_dma.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_dma.c index cc505efc6..a80291320 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_dma.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_dma.c @@ -1057,9 +1057,9 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) else { /* DMA2 */ -#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G414xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx) +#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G414xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx) || defined (STM32G411xC) DMAMUX1_ChannelBase = DMAMUX1_Channel8; -#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) +#elif defined (STM32G411xB) || defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) DMAMUX1_ChannelBase = DMAMUX1_Channel6; #else DMAMUX1_ChannelBase = DMAMUX1_Channel7; diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_fdcan.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_fdcan.c index be0a0a656..92d65227d 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_fdcan.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_fdcan.c @@ -1309,7 +1309,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA if (sFilterConfig->IdType == FDCAN_STANDARD_ID) { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.StdFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU)); assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType)); @@ -1329,7 +1329,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.ExtFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU)); assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType)); diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_flash_ex.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_flash_ex.c index 6e65fbef3..4816af797 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_flash_ex.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_flash_ex.c @@ -920,7 +920,6 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_PE); optr_reg_mask |= FLASH_OPTR_SRAM_PE; } -#if defined(CCMSRAM_BASE) if ((UserType & OB_USER_CCMSRAM_RST) != 0U) { /* CCMSRAM_RST option byte should be modified */ @@ -930,7 +929,6 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserCon optr_reg_val |= (UserConfig & FLASH_OPTR_CCMSRAM_RST); optr_reg_mask |= FLASH_OPTR_CCMSRAM_RST; } -#endif /* CCMSRAM_BASE */ if ((UserType & OB_USER_nSWBOOT0) != 0U) { /* nSWBOOT0 option byte should be modified */ diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_fmac.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_fmac.c index 82207191f..802911ade 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_fmac.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_fmac.c @@ -1199,7 +1199,7 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti */ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check handle state is ready */ if (hfmac->State == HAL_FMAC_STATE_READY) @@ -1218,11 +1218,24 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { (*(hfmac->pInputSize)) = hfmac->InputCurrentSize; } + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL)) { (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize; } + if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA) + { + /* Disable the DMA stream managing FMAC input data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaIn); + } + + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA) && (status == HAL_OK)) + { + /* Disable the DMA stream managing FMAC output data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaOut); + } + /* Reset FMAC unit (internal pointers) */ if (FMAC_Reset(hfmac) == HAL_ERROR) { @@ -1235,8 +1248,6 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { /* Reset the data pointers */ FMAC_ResetDataPointers(hfmac); - - status = HAL_OK; } /* Reset the busy flag */ diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_hrtim.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_hrtim.c index 7b0ab4919..cf99f6f61 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_hrtim.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_hrtim.c @@ -84,7 +84,6 @@ any restriction. HRTIM waveform modes are managed through the set of functions named HAL_HRTIM_Waveform -============================================================================== ##### How to use this driver ##### ============================================================================== [..] @@ -444,70 +443,70 @@ static uint32_t TimerIdxToTimerId[] = /** @defgroup HRTIM_Private_Functions HRTIM Private Functions * @{ */ -static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); +static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); -static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); -static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimerCfgTypeDef * pTimerCfg); +static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimerCfgTypeDef *pTimerCfg); -static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef *pTimerCfg); -static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCtlTypeDef * pTimerCtl); + const HRTIM_TimerCtlTypeDef *pTimerCtl); -static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t pRollOverMode); -static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event); -static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg); +static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t Output, + const HRTIM_OutputCfgTypeDef *pOutputCfg); -static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef * pEventCfg); + const HRTIM_EventCfgTypeDef *pEventCfg); -static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event); -static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); -static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, - const DMA_HandleTypeDef * hdma); +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim, + const DMA_HandleTypeDef *hdma); -static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); -static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim); +static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim); -static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim); +static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim); -static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma); @@ -526,7 +525,7 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma); */ /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions @verbatim =============================================================================== ##### Initialization and Time Base Configuration functions ##### @@ -549,20 +548,20 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma); * @param hhrtim pointer to HAL HRTIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) +HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim) { uint8_t timer_idx; uint32_t hrtim_mcr; /* Check the HRTIM handle allocation */ - if(hhrtim == NULL) + if (hhrtim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance)); - assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests)); + assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptRequests)); #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) if (hhrtim->State == HAL_HRTIM_STATE_RESET) @@ -694,10 +693,10 @@ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim) +HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim) { /* Check the HRTIM handle allocation */ - if(hhrtim == NULL) + if (hhrtim == NULL) { return HAL_ERROR; } @@ -730,7 +729,7 @@ HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -745,7 +744,7 @@ __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -770,7 +769,7 @@ __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim) * within the HAL_HRTIM_PollForDLLCalibration function, just before * exiting the function. */ -HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim, uint32_t CalibrationRate) { /* Check the parameters */ @@ -820,7 +819,7 @@ HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim, * interrupt is generated every time the calibration completes which * will significantly increases the overall interrupt rate. */ -HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim, uint32_t CalibrationRate) { /* Check the parameters */ @@ -861,7 +860,7 @@ HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim, * @param Timeout Timeout duration in millisecond * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim, uint32_t Timeout) { uint32_t tickstart; @@ -869,11 +868,11 @@ HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim, tickstart = HAL_GetTick(); /* Check End of conversion flag */ - while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET) + while (__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET) { if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hhrtim->State = HAL_HRTIM_STATE_ERROR; return HAL_TIMEOUT; @@ -913,16 +912,16 @@ HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio)); assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Set the HRTIM state */ @@ -950,7 +949,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions - * @brief Simple time base mode functions. + * @brief Simple time base mode functions. @verbatim =============================================================================== ##### Simple time base mode functions ##### @@ -983,10 +982,10 @@ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -1019,10 +1018,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -1056,10 +1055,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -1103,10 +1102,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -1153,24 +1152,24 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim, * @param Length The length of data items (data size) to be transferred * from source to destination */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -1188,12 +1187,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA transfer completed callback */ @@ -1211,14 +1210,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer repetition DMA request */ if (TimerIdx == HRTIM_TIMERINDEX_MASTER) @@ -1256,10 +1255,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -1274,7 +1273,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } /* Disable the timer repetition DMA request */ __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP); @@ -1295,12 +1294,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hdma) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } /* Disable the timer repetition DMA request */ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP); - } + } } /* Disable the timer counter */ @@ -1311,11 +1310,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } else { - return HAL_OK; + return HAL_OK; } } @@ -1324,7 +1323,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions - * @brief Simple output compare functions + * @brief Simple output compare functions @verbatim =============================================================================== ##### Simple output compare functions ##### @@ -1381,10 +1380,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, * Inactive: SETxy =0, RSTxy = CMPy * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel, + const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg) { uint32_t CompareUnit = (uint32_t)RESET; HRTIM_OutputCfgTypeDef OutputCfg; @@ -1396,9 +1395,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity)); assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -1410,29 +1409,29 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure timer compare unit */ switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { CompareUnit = HRTIM_COMPAREUNIT_1; hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { CompareUnit = HRTIM_COMPAREUNIT_2; hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -1443,9 +1442,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ @@ -1458,7 +1457,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, switch (pSimpleOCChannelCfg->Mode) { - case HRTIM_BASICOCMODE_TOGGLE: + case HRTIM_BASICOCMODE_TOGGLE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1472,7 +1471,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_BASICOCMODE_ACTIVE: + case HRTIM_BASICOCMODE_ACTIVE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1486,7 +1485,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_BASICOCMODE_INACTIVE: + case HRTIM_BASICOCMODE_INACTIVE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1500,7 +1499,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -1514,9 +1513,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } HRTIM_OutputConfig(hhrtim, @@ -1560,11 +1559,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1613,11 +1612,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1671,13 +1670,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim, * Output set inactive: output reset interrupt is enabled * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t interrupt; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1733,13 +1732,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t interrupt; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1803,26 +1802,26 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim, * Output set inactive: output reset DMA request is enabled * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; uint32_t dma_request; /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -1835,7 +1834,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Process Locked */ __HAL_LOCK(hhrtim); - /* Enable the timer output */ + /* Enable the timer output */ hhrtim->Instance->sCommonRegs.OENR |= OCChannel; /* Get the DMA request to enable */ @@ -1846,12 +1845,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA error callback */ @@ -1862,14 +1861,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request); @@ -1913,9 +1912,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t dma_request; @@ -1964,7 +1963,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions - * @brief Simple PWM output functions + * @brief Simple PWM output functions @verbatim =============================================================================== ##### Simple PWM output functions ##### @@ -2024,10 +2023,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, * enabled (otherwise the behavior is not guaranteed). * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel, + const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; uint32_t hrtim_timcr; @@ -2038,9 +2037,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse)); assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -2051,30 +2050,30 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure timer compare unit */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -2088,14 +2087,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1); - OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1); + OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1); OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE; OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; @@ -2147,11 +2146,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2200,11 +2199,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2254,11 +2253,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2272,29 +2271,29 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Enable the timer interrupt (depends on the PWM output) */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2305,9 +2304,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2349,11 +2348,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2367,29 +2366,29 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer interrupt (depends on the PWM output) */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2400,9 +2399,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -2448,25 +2447,25 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, * from source to destination * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -2503,41 +2502,41 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2548,9 +2547,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2592,9 +2591,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); @@ -2622,29 +2621,29 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer DMA request */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2655,9 +2654,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -2676,7 +2675,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions - * @brief Simple input capture functions + * @brief Simple input capture functions @verbatim =============================================================================== ##### Simple input capture functions ##### @@ -2719,10 +2718,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, * edges on event channel. * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel, + const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg) { HRTIM_EventCfgTypeDef EventCfg; @@ -2736,9 +2735,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhr assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event, pSimpleCaptureChannelCfg->EventFilter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -2791,11 +2790,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhr * units. It can be used directly and is active as soon as the timing * unit counter is enabled. */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2807,19 +2806,19 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2830,9 +2829,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2863,14 +2862,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; uint32_t hrtim_cpt2cr; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2882,19 +2881,19 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2905,9 +2904,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -2946,11 +2945,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2962,7 +2961,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; @@ -2971,7 +2970,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; @@ -2980,7 +2979,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2991,9 +2990,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -3025,15 +3024,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; uint32_t hrtim_cpt2cr; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -3045,7 +3044,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -3054,7 +3053,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -3063,7 +3062,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3074,9 +3073,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -3119,16 +3118,16 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, * from source to destination * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -3142,12 +3141,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA error callback */ @@ -3158,18 +3157,18 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { /* Set the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; @@ -3178,7 +3177,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { /* Set the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; @@ -3188,7 +3187,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3197,11 +3196,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - } + } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -3233,9 +3232,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; @@ -3254,17 +3253,17 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { /* Reset the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -3274,7 +3273,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { /* Reset the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -3284,7 +3283,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3295,9 +3294,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -3323,7 +3322,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions - * @brief Simple one pulse functions + * @brief Simple one pulse functions @verbatim =============================================================================== ##### Simple one pulse functions ##### @@ -3383,10 +3382,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, * second call will override the reset event related configuration data * provided in the first call. */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel, + const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; HRTIM_EventCfgTypeDef EventCfg; @@ -3403,9 +3402,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event, pSimpleOnePulseChannelCfg->EventFilter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3416,31 +3415,31 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh /* Configure timer compare unit */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -3454,13 +3453,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ - OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1); + OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1); OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1); OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE; OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; @@ -3477,7 +3476,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE; EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F); EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1); - EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS); + EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS); EventCfg.Source = HRTIM_EEV1SRC_GPIO; /* source 1 for External Event */ HRTIM_EventConfig(hhrtim, @@ -3524,7 +3523,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel) { @@ -3577,9 +3576,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3631,9 +3630,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3649,29 +3648,29 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Enable the timer interrupt (depends on the OnePulse output) */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3682,9 +3681,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -3726,9 +3725,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3744,29 +3743,29 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer interrupt (depends on the OnePulse output) */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3777,9 +3776,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -3798,7 +3797,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions - * @brief HRTIM configuration functions + * @brief HRTIM configuration functions @verbatim =============================================================================== ##### HRTIM configuration functions ##### @@ -3825,8 +3824,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the burst mode * controller */ -HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg) +HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg) { uint32_t hrtim_bmcr; @@ -3837,9 +3836,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable)); assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3905,9 +3904,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef* pEventCfg) + const HRTIM_EventCfgTypeDef *pEventCfg) { /* Check parameters */ assert_param(IS_HRTIM_EVENT(Event)); @@ -3917,9 +3916,9 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode)); assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3950,15 +3949,15 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler) { /* Check parameters */ assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3993,13 +3992,13 @@ HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, * enabling faults inputs * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultCfgTypeDef* pFaultCfg) + const HRTIM_FaultCfgTypeDef *pFaultCfg) { uint32_t hrtim_fltinr1; uint32_t hrtim_fltinr2; - uint32_t source0,source1; + uint32_t source0, source1; /* Check parameters */ assert_param(IS_HRTIM_FAULT(Fault)); @@ -4008,9 +4007,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter)); assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4022,12 +4021,12 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1; hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2; - source0 = (pFaultCfg->Source & 1U); + source0 = (pFaultCfg->Source & 1U); source1 = ((pFaultCfg->Source & 2U) >> 1); switch (Fault) { - case HRTIM_FAULT_1: + case HRTIM_FAULT_1: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK); hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P); @@ -4039,7 +4038,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_2: + case HRTIM_FAULT_2: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P); @@ -4051,7 +4050,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_3: + case HRTIM_FAULT_3: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P); @@ -4061,9 +4060,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F); hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK); break; - } + } - case HRTIM_FAULT_4: + case HRTIM_FAULT_4: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC_0 | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P); @@ -4075,7 +4074,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_5: + case HRTIM_FAULT_5: { hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC_0 | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK); hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P); @@ -4087,7 +4086,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_6: + case HRTIM_FAULT_6: { hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6P | HRTIM_FLTINR2_FLT6SRC_0 | HRTIM_FLTINR2_FLT6F | HRTIM_FLTINR2_FLT6LCK); hrtim_fltinr2 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR2_FLT6P); @@ -4099,7 +4098,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4110,9 +4109,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Update the HRTIM registers except LOCK bit */ @@ -4120,8 +4119,8 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK))); /* Update the HRTIM registers LOCK bit */ - SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK)); - SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK)); + SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1, (hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK)); + SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2, (hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK)); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4144,15 +4143,15 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer and before * enabling faults inputs */ -HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler) { /* Check parameters */ assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4187,17 +4186,17 @@ HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called when fault is not enabled * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * hhrtim, - uint32_t Fault, - const HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg) +HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef *hhrtim, + uint32_t Fault, + const HRTIM_FaultBlankingCfgTypeDef *pFaultBlkCfg) { /* Check parameters */ assert_param(IS_HRTIM_FAULT(Fault)); assert_param(IS_HRTIM_FAULTBLANKNGMODE(pFaultBlkCfg->BlankingSource)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4207,56 +4206,56 @@ HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * h switch (Fault) { - case HRTIM_FAULT_1: + case HRTIM_FAULT_1: { - MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, - (HRTIM_FLTINR3_FLT1BLKS | HRTIM_FLTINR3_FLT1BLKE), - ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT1BLKS_Pos) | + MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, + (HRTIM_FLTINR3_FLT1BLKS | HRTIM_FLTINR3_FLT1BLKE), + ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT1BLKS_Pos) | HRTIM_FLTINR3_FLT1BLKE)); - break; + break; } - case HRTIM_FAULT_2: + case HRTIM_FAULT_2: { - MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, - (HRTIM_FLTINR3_FLT2BLKS | HRTIM_FLTINR3_FLT2BLKE), - ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT2BLKS_Pos) | + MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, + (HRTIM_FLTINR3_FLT2BLKS | HRTIM_FLTINR3_FLT2BLKE), + ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT2BLKS_Pos) | HRTIM_FLTINR3_FLT2BLKE)); - break; + break; } - case HRTIM_FAULT_3: + case HRTIM_FAULT_3: { - MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, - (HRTIM_FLTINR3_FLT3BLKS | HRTIM_FLTINR3_FLT3BLKE), - ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT3BLKS_Pos) | + MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, + (HRTIM_FLTINR3_FLT3BLKS | HRTIM_FLTINR3_FLT3BLKE), + ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT3BLKS_Pos) | HRTIM_FLTINR3_FLT3BLKE)); - break; + break; } - case HRTIM_FAULT_4: + case HRTIM_FAULT_4: { - MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, - (HRTIM_FLTINR3_FLT4BLKS | HRTIM_FLTINR3_FLT4BLKE), - ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT4BLKS_Pos) | + MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, + (HRTIM_FLTINR3_FLT4BLKS | HRTIM_FLTINR3_FLT4BLKE), + ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT4BLKS_Pos) | HRTIM_FLTINR3_FLT4BLKE)); - break; + break; } - case HRTIM_FAULT_5: + case HRTIM_FAULT_5: { MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, - (HRTIM_FLTINR4_FLT5BLKS | HRTIM_FLTINR4_FLT5BLKE), - ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT5BLKS_Pos) | + (HRTIM_FLTINR4_FLT5BLKS | HRTIM_FLTINR4_FLT5BLKE), + ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT5BLKS_Pos) | HRTIM_FLTINR4_FLT5BLKE)); break; } - case HRTIM_FAULT_6: + case HRTIM_FAULT_6: { MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, - (HRTIM_FLTINR4_FLT6BLKS | HRTIM_FLTINR4_FLT6BLKE), - ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT6BLKS_Pos) | + (HRTIM_FLTINR4_FLT6BLKS | HRTIM_FLTINR4_FLT6BLKE), + ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT6BLKS_Pos) | HRTIM_FLTINR4_FLT6BLKE)); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4267,9 +4266,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * h } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4298,18 +4297,18 @@ HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * h * * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg) + const HRTIM_FaultBlankingCfgTypeDef *pFaultBlkCfg) { /* Check parameters */ assert_param(IS_HRTIM_FAULT(Fault)); assert_param(IS_HRTIM_FAULTCOUNTER(pFaultBlkCfg->Threshold)); assert_param(IS_HRTIM_FAULTCOUNTERRST(pFaultBlkCfg->ResetMode)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4319,56 +4318,56 @@ HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim, switch (Fault) { - case HRTIM_FAULT_1: + case HRTIM_FAULT_1: { - MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, - (HRTIM_FLTINR3_FLT1RSTM | HRTIM_FLTINR3_FLT1CNT), - (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT1CNT_Pos) | - (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT1RSTM_Pos)); - break; + MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, + (HRTIM_FLTINR3_FLT1RSTM | HRTIM_FLTINR3_FLT1CNT), + (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT1CNT_Pos) | + (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT1RSTM_Pos)); + break; } - case HRTIM_FAULT_2: + case HRTIM_FAULT_2: { - MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, - (HRTIM_FLTINR3_FLT2RSTM | HRTIM_FLTINR3_FLT2CNT), - (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT2CNT_Pos) | - (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT2RSTM_Pos)); - break; + MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, + (HRTIM_FLTINR3_FLT2RSTM | HRTIM_FLTINR3_FLT2CNT), + (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT2CNT_Pos) | + (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT2RSTM_Pos)); + break; } - case HRTIM_FAULT_3: + case HRTIM_FAULT_3: { - MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, - (HRTIM_FLTINR3_FLT3RSTM | HRTIM_FLTINR3_FLT3CNT), - (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT3CNT_Pos) | - (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT3RSTM_Pos)); - break; + MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, + (HRTIM_FLTINR3_FLT3RSTM | HRTIM_FLTINR3_FLT3CNT), + (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT3CNT_Pos) | + (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT3RSTM_Pos)); + break; } - case HRTIM_FAULT_4: + case HRTIM_FAULT_4: { - MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, - (HRTIM_FLTINR3_FLT4RSTM | HRTIM_FLTINR3_FLT4CNT), - (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT4CNT_Pos) | - (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT4RSTM_Pos)); - break; + MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, + (HRTIM_FLTINR3_FLT4RSTM | HRTIM_FLTINR3_FLT4CNT), + (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT4CNT_Pos) | + (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT4RSTM_Pos)); + break; } - case HRTIM_FAULT_5: + case HRTIM_FAULT_5: { - MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, - (HRTIM_FLTINR4_FLT5RSTM | HRTIM_FLTINR4_FLT5CNT), - (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT5CNT_Pos) | - (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT5RSTM_Pos)); - break; + MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, + (HRTIM_FLTINR4_FLT5RSTM | HRTIM_FLTINR4_FLT5CNT), + (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT5CNT_Pos) | + (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT5RSTM_Pos)); + break; } - case HRTIM_FAULT_6: + case HRTIM_FAULT_6: { - MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, - (HRTIM_FLTINR4_FLT6RSTM | HRTIM_FLTINR4_FLT6CNT), - (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT6CNT_Pos) | - (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT6RSTM_Pos)); - break; + MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, + (HRTIM_FLTINR4_FLT6RSTM | HRTIM_FLTINR4_FLT6CNT), + (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT6CNT_Pos) | + (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT6RSTM_Pos)); + break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4379,9 +4378,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4405,15 +4404,15 @@ HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_FAULT_6: Fault input 6 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault) { /* Check parameters */ assert_param(IS_HRTIM_FAULT(Fault)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4423,38 +4422,38 @@ HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim, switch (Fault) { - case HRTIM_FAULT_1: + case HRTIM_FAULT_1: { MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT1CRES, HRTIM_FLTINR3_FLT1CRES) ; break; } - case HRTIM_FAULT_2: + case HRTIM_FAULT_2: { MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT2CRES, HRTIM_FLTINR3_FLT2CRES) ; break; } - case HRTIM_FAULT_3: + case HRTIM_FAULT_3: { - MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT3CRES, HRTIM_FLTINR3_FLT3CRES) ; - break; + MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT3CRES, HRTIM_FLTINR3_FLT3CRES) ; + break; } - case HRTIM_FAULT_4: + case HRTIM_FAULT_4: { MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT4CRES, HRTIM_FLTINR3_FLT4CRES) ; break; } - case HRTIM_FAULT_5: + case HRTIM_FAULT_5: { MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, HRTIM_FLTINR4_FLT5CRES, HRTIM_FLTINR4_FLT5CRES) ; break; } - case HRTIM_FAULT_6: + case HRTIM_FAULT_6: { MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, HRTIM_FLTINR4_FLT6CRES, HRTIM_FLTINR4_FLT6CRES) ; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4465,9 +4464,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4495,9 +4494,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled * @retval None */ -void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, - uint32_t Faults, - uint32_t Enable) +void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, + uint32_t Faults, + uint32_t Enable) { /* Check parameters */ assert_param(IS_HRTIM_FAULT(Faults)); @@ -4557,9 +4556,9 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg) + const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg) { uint32_t hrtim_cr1; uint32_t hrtim_adcur; @@ -4568,9 +4567,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger)); assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4584,7 +4583,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, switch (ADCTrigger) { - case HRTIM_ADCTRIGGER_1: + case HRTIM_ADCTRIGGER_1: { hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC); hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC); @@ -4594,7 +4593,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_2: + case HRTIM_ADCTRIGGER_2: { hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC); @@ -4604,7 +4603,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_3: + case HRTIM_ADCTRIGGER_3: { hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC); @@ -4614,7 +4613,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_4: + case HRTIM_ADCTRIGGER_4: { hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC); @@ -4624,7 +4623,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_5: + case HRTIM_ADCTRIGGER_5: { hrtim_adcur &= ~(HRTIM_ADCUR_AD5USRC); hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 16U) & HRTIM_ADCUR_AD5USRC); @@ -4635,7 +4634,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_6: + case HRTIM_ADCTRIGGER_6: { hrtim_adcur &= ~(HRTIM_ADCUR_AD6USRC); hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 12U) & HRTIM_ADCUR_AD6USRC); @@ -4646,7 +4645,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_7: + case HRTIM_ADCTRIGGER_7: { hrtim_adcur &= ~(HRTIM_ADCUR_AD7USRC); hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 8U) & HRTIM_ADCUR_AD7USRC); @@ -4657,7 +4656,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_8: + case HRTIM_ADCTRIGGER_8: { hrtim_adcur &= ~(HRTIM_ADCUR_AD8USRC); hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 4U) & HRTIM_ADCUR_AD8USRC); @@ -4668,7 +4667,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_9: + case HRTIM_ADCTRIGGER_9: { hrtim_adcur &= ~(HRTIM_ADCUR_AD9USRC); hrtim_adcur |= ((pADCTriggerCfg->UpdateSource) & HRTIM_ADCUR_AD9USRC); @@ -4679,7 +4678,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_10: + case HRTIM_ADCTRIGGER_10: { hrtim_adcur &= ~(HRTIM_ADCUR_AD10USRC); hrtim_adcur |= ((pADCTriggerCfg->UpdateSource << 4U) & HRTIM_ADCUR_AD10USRC); @@ -4690,7 +4689,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4701,19 +4700,19 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Update the HRTIM registers */ if (ADCTrigger < HRTIM_ADCTRIGGER_5) { - hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1; + hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1; } else { - hhrtim->Instance->sCommonRegs.ADCUR = hrtim_adcur; + hhrtim->Instance->sCommonRegs.ADCUR = hrtim_adcur; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4744,16 +4743,16 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t ADCTrigger, - uint32_t Postscaler) +HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t ADCTrigger, + uint32_t Postscaler) { /* Check parameters */ assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4763,67 +4762,67 @@ HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim, switch (ADCTrigger) { - case HRTIM_ADCTRIGGER_1: + case HRTIM_ADCTRIGGER_1: { MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD1PSC, (Postscaler & HRTIM_ADCPS1_AD1PSC)); break; } - case HRTIM_ADCTRIGGER_2: + case HRTIM_ADCTRIGGER_2: { MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD2PSC, ((Postscaler << HRTIM_ADCPS1_AD2PSC_Pos) & HRTIM_ADCPS1_AD2PSC)); break; } - case HRTIM_ADCTRIGGER_3: + case HRTIM_ADCTRIGGER_3: { MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD3PSC, ((Postscaler << HRTIM_ADCPS1_AD3PSC_Pos) & HRTIM_ADCPS1_AD3PSC)); break; } - case HRTIM_ADCTRIGGER_4: + case HRTIM_ADCTRIGGER_4: { MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD4PSC, ((Postscaler << HRTIM_ADCPS1_AD4PSC_Pos) & HRTIM_ADCPS1_AD4PSC)); break; } - case HRTIM_ADCTRIGGER_5: + case HRTIM_ADCTRIGGER_5: { MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD5PSC, ((Postscaler << HRTIM_ADCPS1_AD5PSC_Pos) & HRTIM_ADCPS1_AD5PSC)); break; } - case HRTIM_ADCTRIGGER_6: + case HRTIM_ADCTRIGGER_6: { MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD6PSC, ((Postscaler << HRTIM_ADCPS2_AD6PSC_Pos) & HRTIM_ADCPS2_AD6PSC)); break; } - case HRTIM_ADCTRIGGER_7: + case HRTIM_ADCTRIGGER_7: { MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD7PSC, ((Postscaler << HRTIM_ADCPS2_AD7PSC_Pos) & HRTIM_ADCPS2_AD7PSC)); break; } - case HRTIM_ADCTRIGGER_8: + case HRTIM_ADCTRIGGER_8: { MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD8PSC, ((Postscaler << HRTIM_ADCPS2_AD8PSC_Pos) & HRTIM_ADCPS2_AD8PSC)); break; } - case HRTIM_ADCTRIGGER_9: + case HRTIM_ADCTRIGGER_9: { MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD9PSC, ((Postscaler << HRTIM_ADCPS2_AD9PSC_Pos) & HRTIM_ADCPS2_AD9PSC)); break; } - case HRTIM_ADCTRIGGER_10: + case HRTIM_ADCTRIGGER_10: { MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD10PSC, ((Postscaler << HRTIM_ADCPS2_AD10PSC_Pos) & HRTIM_ADCPS2_AD10PSC)); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4834,9 +4833,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4867,17 +4866,17 @@ HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIM_ROM_BOTH or HRTIM_TIM_ROM_CREST or HRTIM_TIM_ROM_VALLEY * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t RollOverCfg) +HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t RollOverCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_ROLLOVERMODE(RollOverCfg)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4885,7 +4884,7 @@ HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; - HRTIM_TimingUnitRollOver_Config(hhrtim,TimerIdx,RollOverCfg); + HRTIM_TimingUnitRollOver_Config(hhrtim, TimerIdx, RollOverCfg); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4901,7 +4900,7 @@ HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions - * @brief HRTIM timer configuration and control functions + * @brief HRTIM timer configuration and control functions @verbatim =============================================================================== ##### HRTIM timer configuration and control functions ##### @@ -4956,9 +4955,9 @@ HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef *pTimerCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -4973,9 +4972,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode)); assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5028,7 +5027,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure slave timer update re-synchronization */ if ((TimerIdx != HRTIM_TIMERINDEX_MASTER) - && (pTimerCfg->UpdateGating == HRTIM_UPDATEGATING_INDEPENDENT)) + && (pTimerCfg->UpdateGating == HRTIM_UPDATEGATING_INDEPENDENT)) { MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_RSYNCU_Msk, @@ -5060,43 +5059,43 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - const HRTIM_TimerCtlTypeDef * pTimerCtl) +HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + const HRTIM_TimerCtlTypeDef *pTimerCtl) { - /* Check parameters */ - assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - /* Relevant for all A..F HRTIM timers */ - assert_param(IS_HRTIM_TIMERUPDOWNMODE(pTimerCtl->UpDownMode)); - assert_param(IS_HRTIM_TIMERTRGHLFMODE(pTimerCtl->TrigHalf)); - assert_param(IS_HRTIM_TIMERGTCMP3(pTimerCtl->GreaterCMP3)); - assert_param(IS_HRTIM_TIMERGTCMP1(pTimerCtl->GreaterCMP1)); - assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset)); - assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep)); - assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable)); + /* Check parameters */ + assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); + /* Relevant for all A..F HRTIM timers */ + assert_param(IS_HRTIM_TIMERUPDOWNMODE(pTimerCtl->UpDownMode)); + assert_param(IS_HRTIM_TIMERTRGHLFMODE(pTimerCtl->TrigHalf)); + assert_param(IS_HRTIM_TIMERGTCMP3(pTimerCtl->GreaterCMP3)); + assert_param(IS_HRTIM_TIMERGTCMP1(pTimerCtl->GreaterCMP1)); + assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset)); + assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep)); + assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) - { - return HAL_BUSY; - } + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) + { + return HAL_BUSY; + } - /* Process Locked */ - __HAL_LOCK(hhrtim); + /* Process Locked */ + __HAL_LOCK(hhrtim); - hhrtim->State = HAL_HRTIM_STATE_BUSY; + hhrtim->State = HAL_HRTIM_STATE_BUSY; - /* Configure timing unit */ - HRTIM_TimingUnitWaveform_Control(hhrtim, TimerIdx, pTimerCtl); + /* Configure timing unit */ + HRTIM_TimingUnitWaveform_Control(hhrtim, TimerIdx, pTimerCtl); - /* Force a software update */ - HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx); + /* Force a software update */ + HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx); - hhrtim->State = HAL_HRTIM_STATE_READY; + hhrtim->State = HAL_HRTIM_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_OK; + return HAL_OK; } /** @@ -5116,43 +5115,43 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - const HRTIM_TimerCtlTypeDef * pTimerCtl) +HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + const HRTIM_TimerCtlTypeDef *pTimerCtl) { - assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset)); - assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep)); - assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable)); - - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) - { - return HAL_BUSY; - } + assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset)); + assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep)); + assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable)); - /* Process Locked */ - __HAL_LOCK(hhrtim); + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) + { + return HAL_BUSY; + } - hhrtim->State = HAL_HRTIM_STATE_BUSY; - /* clear DCDS,DCDR,DCDE bits */ - CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2, - (HRTIM_TIMER_DCDE_ENABLED | - HRTIM_TIMER_DCDS_OUT1RST | - HRTIM_TIMER_DCDR_OUT1SET) ); + /* Process Locked */ + __HAL_LOCK(hhrtim); - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 , - (HRTIM_TIMER_DCDE_ENABLED | - HRTIM_TIMER_DCDS_OUT1RST | - HRTIM_TIMER_DCDR_OUT1SET), - (pTimerCtl->DualChannelDacReset | - pTimerCtl->DualChannelDacStep | - pTimerCtl->DualChannelDacEnable)); + hhrtim->State = HAL_HRTIM_STATE_BUSY; + /* clear DCDS,DCDR,DCDE bits */ + CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2, + (HRTIM_TIMER_DCDE_ENABLED | + HRTIM_TIMER_DCDS_OUT1RST | + HRTIM_TIMER_DCDR_OUT1SET)); + + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2, + (HRTIM_TIMER_DCDE_ENABLED | + HRTIM_TIMER_DCDS_OUT1RST | + HRTIM_TIMER_DCDR_OUT1SET), + (pTimerCtl->DualChannelDacReset | + pTimerCtl->DualChannelDacStep | + pTimerCtl->DualChannelDacEnable)); - hhrtim->State = HAL_HRTIM_STATE_READY; + hhrtim->State = HAL_HRTIM_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_OK; + return HAL_OK; } /** @@ -5182,21 +5181,21 @@ HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrt * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg) + const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_EVENT(Event)); - assert_param(IS_HRTIM_TIMEVENTFILTER(TimerIdx,pTimerEventFilteringCfg->Filter)); + assert_param(IS_HRTIM_TIMEVENTFILTER(TimerIdx, pTimerEventFilteringCfg->Filter)); assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5207,75 +5206,85 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt /* Configure timer event filtering capabilities */ switch (Event) { - case HRTIM_EVENT_NONE: + case HRTIM_EVENT_NONE: { CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1); CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2); break; } - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), + (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U)); break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U)); break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U)); break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U)); break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), + (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U)); break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U)); break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U)); break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U)); break; } - default: - { + default: + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -5285,9 +5294,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5318,10 +5327,10 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t EventCounter, - const HRTIM_ExternalEventCfgTypeDef* pTimerExternalEventCfg) +HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t EventCounter, + const HRTIM_ExternalEventCfgTypeDef *pTimerExternalEventCfg) { uint32_t hrtim_eefr3; @@ -5332,9 +5341,9 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMEEVENT_COUNTER(pTimerExternalEventCfg->Counter)); assert_param(IS_HRTIM_EVENT(pTimerExternalEventCfg->Source)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5344,38 +5353,42 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim, if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U) { - if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE) - { /* reset External EventCounter A */ - WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0xFFFF0000U); - } - else - { - /* Set timer External EventCounter A configuration */ - hrtim_eefr3 = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVARSTM_Pos; - hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVASEL_Pos; - hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVACNT_Pos; - /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */ + if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE) + { + /* reset External EventCounter A */ + WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0xFFFF0000U); + } + else + { + /* Set timer External EventCounter A configuration */ + hrtim_eefr3 = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVARSTM_Pos; + hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVASEL_Pos; + hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVACNT_Pos; + /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */ - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, (HRTIM_EEFR3_EEVARSTM | HRTIM_EEFR3_EEVASEL | HRTIM_EEFR3_EEVACNT) , hrtim_eefr3 ); - } + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, + (HRTIM_EEFR3_EEVARSTM | HRTIM_EEFR3_EEVASEL | HRTIM_EEFR3_EEVACNT), hrtim_eefr3); + } } if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U) { - if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE) - { /* reset External EventCounter B */ - WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0x0000FFFFU); - } - else - { - /* Set timer External EventCounter B configuration */ - hrtim_eefr3 = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVBRSTM_Pos; - hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVBSEL_Pos; - hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVBCNT_Pos; - /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */ - - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, (HRTIM_EEFR3_EEVBRSTM | HRTIM_EEFR3_EEVBSEL | HRTIM_EEFR3_EEVBCNT) , hrtim_eefr3 ); - } + if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE) + { + /* reset External EventCounter B */ + WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0x0000FFFFU); + } + else + { + /* Set timer External EventCounter B configuration */ + hrtim_eefr3 = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVBRSTM_Pos; + hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVBSEL_Pos; + hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVBCNT_Pos; + /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */ + + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, + (HRTIM_EEFR3_EEVBRSTM | HRTIM_EEFR3_EEVBSEL | HRTIM_EEFR3_EEVBCNT), hrtim_eefr3); + } } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5403,17 +5416,17 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t EventCounter) +HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t EventCounter) { /* Check parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_TIMEEVENT(EventCounter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5427,7 +5440,7 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim, } if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U) { - SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE); + SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE); } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5455,17 +5468,17 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_EVENTCOUNTER_B * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t EventCounter) +HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t EventCounter) { /* Check parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_TIMEEVENT(EventCounter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5480,7 +5493,7 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim, if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U) { - CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE); + CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE); } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5509,17 +5522,17 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t EventCounter) +HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t EventCounter) { /* Check parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_TIMEEVENT(EventCounter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5533,7 +5546,7 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim, } if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U) { - SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3,HRTIM_EEFR3_EEVBCRES); + SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCRES); } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5559,9 +5572,9 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg) + const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg) { uint32_t hrtim_dtr; @@ -5575,9 +5588,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock)); assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5598,9 +5611,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, /* Update the HRTIM registers */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, ( - HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC | - HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF | - HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr); + HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC | + HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF | + HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5625,9 +5638,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before configuring the timer output(s) */ -HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg) + const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg) { uint32_t hrtim_chpr; @@ -5637,9 +5650,9 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle)); assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5703,16 +5716,16 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t RegistersToUpdate) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5723,50 +5736,50 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, /* Set the burst DMA timer update register */ switch (TimerIdx) { - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_F: + case HRTIM_TIMERINDEX_TIMER_F: { hhrtim->Instance->sCommonRegs.BDTFUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate; break; } - default: - { + default: + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -5776,9 +5789,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5817,17 +5830,17 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - const HRTIM_CompareCfgTypeDef* pCompareCfg) + const HRTIM_CompareCfgTypeDef *pCompareCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5841,43 +5854,43 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, switch (CompareUnit) { case HRTIM_COMPAREUNIT_1: - { + { hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_2: - { + { hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_3: - { + { hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_4: - { + { hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue; break; - } + } default: - { + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hhrtim); break; - } + } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } } @@ -5885,14 +5898,14 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, { switch (CompareUnit) { - case HRTIM_COMPAREUNIT_1: + case HRTIM_COMPAREUNIT_1: { /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue; break; } - case HRTIM_COMPAREUNIT_2: + case HRTIM_COMPAREUNIT_2: { /* Check parameters */ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); @@ -5927,17 +5940,17 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U); } - break; + break; } - case HRTIM_COMPAREUNIT_3: + case HRTIM_COMPAREUNIT_3: { /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue; break; } - case HRTIM_COMPAREUNIT_4: + case HRTIM_COMPAREUNIT_4: { /* Check parameters */ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); @@ -5972,24 +5985,24 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U); } - break; + break; } - default: - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + default: + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - break; - } - } + break; + } + } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) - { - return HAL_ERROR; - } + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) + { + return HAL_ERROR; + } } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -6019,10 +6032,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - const HRTIM_CaptureCfgTypeDef* pCaptureCfg) + const HRTIM_CaptureCfgTypeDef *pCaptureCfg) { uint32_t Trigger; uint32_t TimerF_Trigger = (uint32_t)(pCaptureCfg->Trigger >> 32); @@ -6032,9 +6045,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMER_CAPTUREFTRIGGER(TimerIdx, TimerF_Trigger)); assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -6044,37 +6057,37 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, /* TimerF_Trigger is valid for setting other Timers than Timer F */ if (TimerIdx == HRTIM_TIMERINDEX_TIMER_A) - { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFF0FFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TA1SET_Pos ); } + { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFF0FFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TA1SET_Pos); } else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_B) - { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFF0FFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TB1SET_Pos ); } + { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFF0FFFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TB1SET_Pos); } else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_C) - { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFF0FFFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TC1SET_Pos ); } + { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFF0FFFFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TC1SET_Pos); } else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_D) - { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xF0FFFFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TD1SET_Pos ); } + { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xF0FFFFFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TD1SET_Pos); } else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_E) - { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0x0FFFFFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TE1SET_Pos ); } + { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0x0FFFFFFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TE1SET_Pos); } else - { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFFFFFFU); } + { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFFFFFFU); } /* for setting source capture on Timer F, use Trigger only (all bits are valid then) */ /* Configure the capture unit */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, Trigger); break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, Trigger); break; } - default: - { + default: + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -6084,9 +6097,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } @@ -6128,10 +6141,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before configuring the timer and after * configuring the deadtime insertion feature (if required). */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg) +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t Output, + const HRTIM_OutputCfgTypeDef *pOutputCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); @@ -6142,9 +6155,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable)); assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -6199,7 +6212,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, * @note The 'software set/reset trigger' bit in the output set/reset registers * is automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, uint32_t OutputLevel) @@ -6208,9 +6221,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -6221,17 +6234,17 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, /* Force timer output level */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) { /* Force output to its active state */ - SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST); + SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R, HRTIM_SET1R_SST); } else { @@ -6241,12 +6254,12 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) { @@ -6261,7 +6274,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -6272,9 +6285,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -6305,10 +6318,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_OUTPUT(OutputsToStart)); /* Process Locked */ @@ -6347,10 +6360,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStop) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_OUTPUT(OutputsToStop)); /* Process Locked */ @@ -6384,8 +6397,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERID_TIMER_F * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); @@ -6422,8 +6435,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note The counter of a timer is stopped only if all timer outputs are disabled */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); @@ -6463,8 +6476,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim, * function. * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; @@ -6477,7 +6490,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; /* Enable HRTIM interrupts (if required) */ - __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests); + __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests); /* Enable master timer related interrupts (if required) */ if ((Timers & HRTIM_TIMERID_MASTER) != 0U) @@ -6507,7 +6520,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - return HAL_OK;} + return HAL_OK; +} /** * @brief Stop the counter of the designated timer(s) operating in waveform mode @@ -6526,8 +6540,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related interrupts are disabled. */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* ++ WA */ __IO uint32_t delai = (uint32_t)(0x17FU); @@ -6544,7 +6558,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; /* Disable HRTIM interrupts (if required) */ - __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests); + __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests); /* Disable master timer related interrupts (if required) */ if ((Timers & HRTIM_TIMERID_MASTER) != 0U) @@ -6599,18 +6613,18 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, * size of each DMA transfer are specified at timer configuration time * (see HAL_HRTIM_WaveformTimerConfig) */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } hhrtim->State = HAL_HRTIM_STATE_BUSY; @@ -6621,29 +6635,29 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) && (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U)) { - /* Set the DMA error callback */ - hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ; + /* Set the DMA error callback */ + hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ; - /* Set the DMA transfer completed callback */ - hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt; + /* Set the DMA transfer completed callback */ + hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt; - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hhrtim->hdmaMaster, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK) + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(hhrtim->hdmaMaster, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } - /* Enable the timer DMA request */ - __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); + /* Enable the timer DMA request */ + __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); } for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ; @@ -6651,7 +6665,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, timer_idx++) { if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) && - (hhrtim->TimerParam[timer_idx].DMARequests != 0U)) + (hhrtim->TimerParam[timer_idx].DMARequests != 0U)) { /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx); @@ -6666,7 +6680,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, return HAL_ERROR; } - /* Set the DMA error callback */ + /* Set the DMA error callback */ hdma->XferErrorCallback = HRTIM_DMAError ; /* Set the DMA transfer completed callback */ @@ -6674,17 +6688,17 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, - hhrtim->TimerParam[timer_idx].DMASrcAddress, - hhrtim->TimerParam[timer_idx].DMADstAddress, - hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->TimerParam[timer_idx].DMASrcAddress, + hhrtim->TimerParam[timer_idx].DMADstAddress, + hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK) + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, @@ -6721,8 +6735,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related DMA requests are disabled. */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; @@ -6737,14 +6751,14 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } else { - hhrtim->State = HAL_HRTIM_STATE_READY; - /* Disable the DMA request(s) */ - __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); + hhrtim->State = HAL_HRTIM_STATE_READY; + /* Disable the DMA request(s) */ + __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); } } @@ -6778,11 +6792,11 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } else { - return HAL_OK; + return HAL_OK; } } @@ -6796,15 +6810,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called after starting the timer(s) */ -HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim, uint32_t Enable) { /* Check parameters */ assert_param(IS_HRTIM_BURSTMODECTL(Enable)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -6830,9 +6844,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim) { - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -6870,7 +6884,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim * @note The 'software capture' bit in the capure configuration register is * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -6878,9 +6892,9 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -6891,32 +6905,32 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, /* Force a software capture on concerned capture unit */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT); break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - break; + break; } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -6943,15 +6957,15 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, * @note The 'software update' bits in the HRTIM control register 2 register are * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers) { /* Check parameters */ assert_param(IS_HRTIM_TIMERUPDATE(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -6984,15 +6998,15 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note The function is not significant when the Push-pull mode is enabled (PSHPLL = 1) */ -HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* Check parameters */ assert_param(IS_HRTIM_TIMERSWAP(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -7027,15 +7041,15 @@ HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef * hhrtim, * @note The 'software reset' bits in the HRTIM control register 2 are * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers) { /* Check parameters */ assert_param(IS_HRTIM_TIMERRESET(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -7067,31 +7081,31 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERSWAP_F * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { - /* Check parameters */ - assert_param(IS_HRTIM_TIMERSWAP(Timers)); + /* Check parameters */ + assert_param(IS_HRTIM_TIMERSWAP(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) - { - return HAL_BUSY; - } + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) + { + return HAL_BUSY; + } - /* Process Locked */ - __HAL_LOCK(hhrtim); + /* Process Locked */ + __HAL_LOCK(hhrtim); - hhrtim->State = HAL_HRTIM_STATE_BUSY; + hhrtim->State = HAL_HRTIM_STATE_BUSY; - /* Force timer(s) registers update */ - hhrtim->Instance->sCommonRegs.CR2 |= Timers; + /* Force timer(s) registers update */ + hhrtim->Instance->sCommonRegs.CR2 |= Timers; - hhrtim->State = HAL_HRTIM_STATE_READY; + hhrtim->State = HAL_HRTIM_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_OK; + return HAL_OK; } /** @@ -7107,31 +7121,31 @@ HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERSWAP_F * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { - /* Check parameters */ - assert_param(IS_HRTIM_TIMERSWAP(Timers)); + /* Check parameters */ + assert_param(IS_HRTIM_TIMERSWAP(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) - { - return HAL_BUSY; - } + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) + { + return HAL_BUSY; + } - /* Process Locked */ - __HAL_LOCK(hhrtim); + /* Process Locked */ + __HAL_LOCK(hhrtim); - hhrtim->State = HAL_HRTIM_STATE_BUSY; + hhrtim->State = HAL_HRTIM_STATE_BUSY; - /* Force timer(s) registers update */ - hhrtim->Instance->sCommonRegs.CR2 &= ~(Timers); + /* Force timer(s) registers update */ + hhrtim->Instance->sCommonRegs.CR2 &= ~(Timers); - hhrtim->State = HAL_HRTIM_STATE_READY; + hhrtim->State = HAL_HRTIM_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_OK; + return HAL_OK; } /** @@ -7165,18 +7179,18 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, uint32_t BurstBufferAddress, uint32_t BurstBufferLength) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U)) + if ((BurstBufferAddress == 0U) || (BurstBufferLength == 0U)) { return HAL_ERROR; } @@ -7210,17 +7224,17 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, - BurstBufferAddress, - (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR), - BurstBufferLength) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + BurstBufferAddress, + (uint32_t) &(hhrtim->Instance->sCommonRegs.BDMADR), + BurstBufferLength) != HAL_OK) + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -7246,9 +7260,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers) + uint32_t Timers) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERUPDATE(Timers)); /* Process Locked */ @@ -7265,7 +7279,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, __HAL_UNLOCK(hhrtim); return HAL_OK; - } +} /** * @brief Disable the transfer from preload to active registers for one @@ -7302,14 +7316,14 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, __HAL_UNLOCK(hhrtim); return HAL_OK; - } +} /** * @} */ /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions - * @brief Peripheral State functions + * @brief Peripheral State functions @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -7334,7 +7348,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval HAL state */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim) +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim) { /* Return HRTIM state */ return hhrtim->State; @@ -7357,7 +7371,7 @@ HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim) * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval Captured value */ -uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -7370,21 +7384,21 @@ uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, /* Read captured value */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & 0x0000FFFFU; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & 0x0000FFFFU; break; } - default: - { - captured_value = 0xFFFFFFFFUL; + default: + { + captured_value = 0xFFFFFFFFUL; break; } @@ -7410,9 +7424,9 @@ uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval captured value and direction structure */ -HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureUnit) +HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureUnit) { uint32_t tmp; HRTIM_CaptureValueTypeDef captured; @@ -7424,21 +7438,21 @@ HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef * hhrt /* Read captured value */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: tmp = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR; captured.Value = tmp & HRTIM_CPT1R_CPT1R & 0x0000FFFFU; - captured.Dir = (((tmp & HRTIM_CPT1R_DIR) == HRTIM_CPT1R_DIR)?1U:0U); - break; - case HRTIM_CAPTUREUNIT_2: + captured.Dir = (((tmp & HRTIM_CPT1R_DIR) == HRTIM_CPT1R_DIR) ? 1U : 0U); + break; + case HRTIM_CAPTUREUNIT_2: tmp = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR; captured.Value = tmp & HRTIM_CPT2R_CPT2R & 0x0000FFFFU; - captured.Dir = (((tmp & HRTIM_CPT2R_DIR ) == HRTIM_CPT2R_DIR)?1U:0U); - break; - default: + captured.Dir = (((tmp & HRTIM_CPT2R_DIR) == HRTIM_CPT2R_DIR) ? 1U : 0U); + break; + default: captured.Value = 0xFFFFFFFFUL; captured.Dir = 0xFFFFFFFFUL; - break; - } + break; + } return captured; } @@ -7463,9 +7477,9 @@ HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef * hhrt * @arg HRTIM_TIMERUPDOWNMODE_UP * @arg HRTIM_TIMERUPDOWNMODE_UPDOWN */ -uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureUnit) +uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureUnit) { uint32_t tmp; @@ -7476,15 +7490,15 @@ uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef * hhrtim, /* Read captured value */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: - tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & HRTIM_CPT1R_DIR ) >> HRTIM_CPT1R_DIR_Pos); - break; - case HRTIM_CAPTUREUNIT_2: - tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & HRTIM_CPT2R_DIR ) >> HRTIM_CPT2R_DIR_Pos); - break; - default: - tmp = 0xFFFFFFFFU; - break; + case HRTIM_CAPTUREUNIT_1: + tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & HRTIM_CPT1R_DIR) >> HRTIM_CPT1R_DIR_Pos); + break; + case HRTIM_CAPTUREUNIT_2: + tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & HRTIM_CPT2R_DIR) >> HRTIM_CPT2R_DIR_Pos); + break; + default: + tmp = 0xFFFFFFFFU; + break; } return tmp; @@ -7520,7 +7534,7 @@ uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef * hhrtim, * @note Returned output level is taken before the output stage (chopper, * polarity). */ -uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -7532,12 +7546,12 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, /* Read the output level */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET) { @@ -7547,15 +7561,15 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, { output_level = HRTIM_OUTPUTLEVEL_INACTIVE; } - break; + break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET) { @@ -7568,7 +7582,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { output_level = 0xFFFFFFFFUL; break; @@ -7605,7 +7619,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval Output state */ -uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -7621,79 +7635,79 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, /* Set output state according to output control status and output disable status */ switch (Output) { - case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TA1: { output_bit = HRTIM_OENR_TA1OEN; break; } - case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TA2: { output_bit = HRTIM_OENR_TA2OEN; break; } - case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TB1: { output_bit = HRTIM_OENR_TB1OEN; break; } - case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TB2: { output_bit = HRTIM_OENR_TB2OEN; break; } - case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TC1: { output_bit = HRTIM_OENR_TC1OEN; break; } - case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TC2: { output_bit = HRTIM_OENR_TC2OEN; break; } - case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TD1: { output_bit = HRTIM_OENR_TD1OEN; break; } - case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TD2: { output_bit = HRTIM_OENR_TD2OEN; break; } - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TE1: { output_bit = HRTIM_OENR_TE1OEN; break; } - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TE2: { output_bit = HRTIM_OENR_TE2OEN; break; } - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TF1: { output_bit = HRTIM_OENR_TF1OEN; break; } - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TF2: { output_bit = HRTIM_OENR_TF2OEN; break; } - default: + default: { output_bit = 0UL; break; @@ -7719,7 +7733,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, } } - return(output_state); + return (output_state); } /** @@ -7750,7 +7764,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval Delayed protection status */ -uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -7762,12 +7776,12 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim /* Read the delayed protection status */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET) { @@ -7782,12 +7796,12 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET) { @@ -7802,7 +7816,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim break; } - default: + default: { delayed_protection_status = 0xFFFFFFFFUL; break; @@ -7817,7 +7831,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim * @param hhrtim pointer to HAL HRTIM handle * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim) +uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim) { uint32_t burst_mode_status; @@ -7841,7 +7855,7 @@ uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { uint32_t current_pushpull_status; @@ -7870,7 +7884,7 @@ uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval Idle Push Pull Status */ -uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { uint32_t idle_pushpull_status; @@ -7889,25 +7903,25 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling - * @brief Functions called when HRTIM generates an interrupt - * 7 interrupts can be generated by the master timer: - * - Master timer registers update - * - Synchronization event received - * - Master timer repetition event - * - Master Compare 1 to 4 event - * 14 interrupts can be generated by each timing unit: - * - Delayed protection triggered - * - Counter reset or roll-over event - * - Output 1 and output 2 reset (transition active to inactive) - * - Output 1 and output 2 set (transition inactive to active) - * - Capture 1 and 2 events - * - Timing unit registers update - * - Repetition event - * - Compare 1 to 4 event - * 8 global interrupts are generated for the whole HRTIM: - * - System fault and Fault 1 to 5 (regardless of the timing unit attribution) - * - DLL calibration done - * - Burst mode period completed + * @brief Functions called when HRTIM generates an interrupt + * 7 interrupts can be generated by the master timer: + * - Master timer registers update + * - Synchronization event received + * - Master timer repetition event + * - Master Compare 1 to 4 event + * 14 interrupts can be generated by each timing unit: + * - Delayed protection triggered + * - Counter reset or roll-over event + * - Output 1 and output 2 reset (transition active to inactive) + * - Output 1 and output 2 set (transition inactive to active) + * - Capture 1 and 2 events + * - Timing unit registers update + * - Repetition event + * - Compare 1 to 4 event + * 8 global interrupts are generated for the whole HRTIM: + * - System fault and Fault 1 to 5 (regardless of the timing unit attribution) + * - DLL calibration done + * - Burst mode period completed @verbatim =============================================================================== ##### HRTIM interrupts handling ##### @@ -7958,7 +7972,7 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, * This parameter can be any value of HRTIM_Timer_Index * @retval None */ -void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, +void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* HRTIM interrupts handling */ @@ -7984,7 +7998,7 @@ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval None * @retval None */ -__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -7999,7 +8013,7 @@ __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8014,7 +8028,7 @@ __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8029,7 +8043,7 @@ __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8044,7 +8058,7 @@ __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8059,7 +8073,7 @@ __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8074,7 +8088,7 @@ __weak void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8089,7 +8103,7 @@ __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8104,7 +8118,7 @@ __weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8119,7 +8133,7 @@ __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8143,7 +8157,7 @@ __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -8169,7 +8183,7 @@ __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -8196,8 +8210,8 @@ __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8223,8 +8237,8 @@ __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @arg HRTIM_TIMERINDEX_TIMER_F for timer F */ -__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8250,8 +8264,8 @@ __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8277,8 +8291,8 @@ __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8302,8 +8316,8 @@ __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8327,8 +8341,8 @@ __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8353,8 +8367,8 @@ __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8379,8 +8393,8 @@ __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8404,8 +8418,8 @@ __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8429,8 +8443,8 @@ __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8454,8 +8468,8 @@ __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8479,8 +8493,8 @@ __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -8505,7 +8519,7 @@ __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None */ -__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -8554,7 +8568,7 @@ __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim) * @param pCallback Callback function pointer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_CallbackTypeDef pCallback) { @@ -8692,7 +8706,7 @@ HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HAL_HRTIM_MSPDEINIT_CB_ID * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -8704,86 +8718,86 @@ HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, { switch (CallbackID) { - case HAL_HRTIM_FAULT1CALLBACK_CB_ID : - hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback; - break; + case HAL_HRTIM_FAULT1CALLBACK_CB_ID : + hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback; + break; - case HAL_HRTIM_FAULT2CALLBACK_CB_ID : - hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback; - break; + case HAL_HRTIM_FAULT2CALLBACK_CB_ID : + hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback; + break; - case HAL_HRTIM_FAULT3CALLBACK_CB_ID : - hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback; - break; + case HAL_HRTIM_FAULT3CALLBACK_CB_ID : + hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback; + break; - case HAL_HRTIM_FAULT4CALLBACK_CB_ID : - hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback; - break; + case HAL_HRTIM_FAULT4CALLBACK_CB_ID : + hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback; + break; - case HAL_HRTIM_FAULT5CALLBACK_CB_ID : - hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback; - break; + case HAL_HRTIM_FAULT5CALLBACK_CB_ID : + hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback; + break; - case HAL_HRTIM_FAULT6CALLBACK_CB_ID : - hhrtim->Fault6Callback = HAL_HRTIM_Fault6Callback; - break; + case HAL_HRTIM_FAULT6CALLBACK_CB_ID : + hhrtim->Fault6Callback = HAL_HRTIM_Fault6Callback; + break; - case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID : - hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback; - break; + case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID : + hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback; + break; - case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID : - hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback; - break; + case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID : + hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback; + break; - case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID : - hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback; - break; + case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID : + hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback; + break; - case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID : - hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback; - break; + case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID : + hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback; + break; - case HAL_HRTIM_ERRORCALLBACK_CB_ID : - hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback; - break; + case HAL_HRTIM_ERRORCALLBACK_CB_ID : + hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback; + break; - case HAL_HRTIM_MSPINIT_CB_ID : - hhrtim->MspInitCallback = HAL_HRTIM_MspInit; - break; + case HAL_HRTIM_MSPINIT_CB_ID : + hhrtim->MspInitCallback = HAL_HRTIM_MspInit; + break; - case HAL_HRTIM_MSPDEINIT_CB_ID : - hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; - break; + case HAL_HRTIM_MSPDEINIT_CB_ID : + hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; + break; - default : - /* Update the state */ - hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; + default : + /* Update the state */ + hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + /* Return error status */ + status = HAL_ERROR; + break; } } else if (HAL_HRTIM_STATE_RESET == hhrtim->State) { switch (CallbackID) { - case HAL_HRTIM_MSPINIT_CB_ID : - hhrtim->MspInitCallback = HAL_HRTIM_MspInit; - break; + case HAL_HRTIM_MSPINIT_CB_ID : + hhrtim->MspInitCallback = HAL_HRTIM_MspInit; + break; - case HAL_HRTIM_MSPDEINIT_CB_ID : - hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; - break; + case HAL_HRTIM_MSPDEINIT_CB_ID : + hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; + break; - default : - /* Update the state */ - hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; + default : + /* Update the state */ + hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -8824,7 +8838,7 @@ HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @param pCallback Callback function pointer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_TIMxCallbackTypeDef pCallback) { @@ -8905,7 +8919,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, hhrtim->BurstDMATransferCallback = pCallback; break; - default : + default : /* Update the state */ hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; @@ -8951,7 +8965,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -9023,7 +9037,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback; break; - default : + default : /* Update the state */ hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; @@ -9065,8 +9079,8 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @param pTimeBaseCfg pointer to the time base configuration structure * @retval None */ -static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) +static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { uint32_t hrtim_mcr; @@ -9094,9 +9108,9 @@ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimeBaseCfg pointer to the time base configuration structure * @retval None */ -static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx , - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) +static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { uint32_t hrtim_timcr; @@ -9123,8 +9137,8 @@ static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimerCfg pointer to the timer configuration data structure * @retval None */ -static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimerCfgTypeDef * pTimerCfg) +static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimerCfgTypeDef *pTimerCfg) { uint32_t hrtim_mcr; uint32_t hrtim_bmcr; @@ -9139,26 +9153,27 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, /* INTLVD bits are set to 00 */ hrtim_mcr &= ~(HRTIM_MCR_INTLVD); - if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED) || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL)) + if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED) + || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL)) { /* INTLVD bits set to 00 */ hrtim_mcr &= ~(HRTIM_MCR_INTLVD); hrtim_mcr |= (HRTIM_MCR_HALF); } - else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE) + else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE) { - hrtim_mcr |= (HRTIM_MCR_INTLVD_0); - hrtim_mcr &= ~(HRTIM_MCR_INTLVD_1); + hrtim_mcr |= (HRTIM_MCR_INTLVD_0); + hrtim_mcr &= ~(HRTIM_MCR_INTLVD_1); } - else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD) + else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD) { - hrtim_mcr |= (HRTIM_MCR_INTLVD_1); - hrtim_mcr &= ~(HRTIM_MCR_INTLVD_0); + hrtim_mcr |= (HRTIM_MCR_INTLVD_1); + hrtim_mcr &= ~(HRTIM_MCR_INTLVD_0); } else { - hrtim_mcr &= ~(HRTIM_MCR_HALF); - hrtim_mcr &= ~(HRTIM_MCR_INTLVD); + hrtim_mcr &= ~(HRTIM_MCR_HALF); + hrtim_mcr &= ~(HRTIM_MCR_INTLVD); } /* Enable/Disable the timer start upon synchronization event reception */ @@ -9201,9 +9216,9 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimerCfg pointer to the timer configuration data structure * @retval None */ -static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef *pTimerCfg) { uint32_t hrtim_timcr; uint32_t hrtim_timfltr; @@ -9224,26 +9239,27 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, hrtim_timcr &= ~(HRTIM_TIMCR_HALF); hrtim_timcr |= pTimerCfg->HalfModeEnable; - if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED) || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL)) + if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED) + || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL)) { /* INTLVD bits set to 00 */ hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD); hrtim_timcr |= (HRTIM_TIMCR_HALF); } - else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE) + else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE) { - hrtim_timcr |= (HRTIM_TIMCR_INTLVD_0); - hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_1); + hrtim_timcr |= (HRTIM_TIMCR_INTLVD_0); + hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_1); } - else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD) + else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD) { - hrtim_timcr |= (HRTIM_TIMCR_INTLVD_1); - hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_0); + hrtim_timcr |= (HRTIM_TIMCR_INTLVD_1); + hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_0); } else { - hrtim_timcr &= ~(HRTIM_TIMCR_HALF); - hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD); + hrtim_timcr &= ~(HRTIM_TIMCR_HALF); + hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD); } /* Enable/Disable the timer start upon synchronization event reception */ @@ -9293,19 +9309,19 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK); hrtim_timfltr |= pTimerCfg->FaultLock; - /* Enable/Disable dead time insertion at timer level */ - hrtim_timoutr &= ~(HRTIM_OUTR_DTEN); - hrtim_timoutr |= pTimerCfg->DeadTimeInsertion; + /* Enable/Disable dead time insertion at timer level */ + hrtim_timoutr &= ~(HRTIM_OUTR_DTEN); + hrtim_timoutr |= pTimerCfg->DeadTimeInsertion; /* Enable/Disable delayed protection at timer level Delayed Idle is available whatever the timer operating mode (regular, push-pull) Balanced Idle is only available in push-pull mode */ - if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) + if (((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)) - || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED)) + || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED)) { - hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN); + hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT | HRTIM_OUTR_DLYPRTEN); hrtim_timoutr |= pTimerCfg->DelayedProtectionMode; } @@ -9319,50 +9335,50 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, /* Set the timer burst mode */ switch (TimerIdx) { - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hrtim_bmcr &= ~(HRTIM_BMCR_TABM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 1U); break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hrtim_bmcr &= ~(HRTIM_BMCR_TBBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 2U); break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hrtim_bmcr &= ~(HRTIM_BMCR_TCBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 3U); break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hrtim_bmcr &= ~(HRTIM_BMCR_TDBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 4U); break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hrtim_bmcr &= ~(HRTIM_BMCR_TEBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 5U); break; } - case HRTIM_TIMERINDEX_TIMER_F: + case HRTIM_TIMERINDEX_TIMER_F: { hrtim_bmcr &= ~(HRTIM_BMCR_TFBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 6U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 6U); break; } - default: - break; + default: + break; } /* Update the HRTIM registers */ @@ -9380,47 +9396,47 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimerCtl pointer to the timer configuration data structure * @retval None */ -static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCtlTypeDef * pTimerCtl) + const HRTIM_TimerCtlTypeDef *pTimerCtl) { - uint32_t hrtim_timcr2; + uint32_t hrtim_timcr2; - /* Configure timing unit (Timer A to Timer F) */ - hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2; + /* Configure timing unit (Timer A to Timer F) */ + hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2; - /* Set the UpDown counting Mode */ - hrtim_timcr2 &= ~(HRTIM_TIMCR2_UDM); - hrtim_timcr2 |= (pTimerCtl->UpDownMode << HRTIM_TIMCR2_UDM_Pos) ; + /* Set the UpDown counting Mode */ + hrtim_timcr2 &= ~(HRTIM_TIMCR2_UDM); + hrtim_timcr2 |= (pTimerCtl->UpDownMode << HRTIM_TIMCR2_UDM_Pos) ; - /* Set the TrigHalf Mode : requires the counter to be disabled */ - hrtim_timcr2 &= ~(HRTIM_TIMCR2_TRGHLF); - hrtim_timcr2 |= pTimerCtl->TrigHalf; + /* Set the TrigHalf Mode : requires the counter to be disabled */ + hrtim_timcr2 &= ~(HRTIM_TIMCR2_TRGHLF); + hrtim_timcr2 |= pTimerCtl->TrigHalf; - /* define the compare event operating mode */ - hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP1); - hrtim_timcr2 |= pTimerCtl->GreaterCMP1; + /* define the compare event operating mode */ + hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP1); + hrtim_timcr2 |= pTimerCtl->GreaterCMP1; - /* define the compare event operating mode */ - hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP3); - hrtim_timcr2 |= pTimerCtl->GreaterCMP3; + /* define the compare event operating mode */ + hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP3); + hrtim_timcr2 |= pTimerCtl->GreaterCMP3; - if (pTimerCtl->DualChannelDacEnable == HRTIM_TIMER_DCDE_ENABLED) - { - /* Set the DualChannel DAC Reset trigger : requires DCDE enabled */ - hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDR); - hrtim_timcr2 |= pTimerCtl->DualChannelDacReset; + if (pTimerCtl->DualChannelDacEnable == HRTIM_TIMER_DCDE_ENABLED) + { + /* Set the DualChannel DAC Reset trigger : requires DCDE enabled */ + hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDR); + hrtim_timcr2 |= pTimerCtl->DualChannelDacReset; - /* Set the DualChannel DAC Step trigger : requires DCDE enabled */ - hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDS); - hrtim_timcr2 |= pTimerCtl->DualChannelDacStep; + /* Set the DualChannel DAC Step trigger : requires DCDE enabled */ + hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDS); + hrtim_timcr2 |= pTimerCtl->DualChannelDacStep; - /* Enable the DualChannel DAC trigger */ - hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDE); - hrtim_timcr2 |= pTimerCtl->DualChannelDacEnable; - } - /* Update the HRTIM registers */ - hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2; + /* Enable the DualChannel DAC trigger */ + hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDE); + hrtim_timcr2 |= pTimerCtl->DualChannelDacEnable; + } + /* Update the HRTIM registers */ + hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2; } @@ -9431,7 +9447,7 @@ static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim, * @param pRollOverMode: a combination of the timer RollOver Mode configuration * @retval None */ -static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t pRollOverMode) { @@ -9442,15 +9458,15 @@ static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim, if ((hrtim_timcr2 & HRTIM_TIMCR2_UDM) != 0U) { - /* xxROM bitfield must be reset before programming a new value */ - hrtim_timcr2 &= ~(HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM | - HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM); + /* xxROM bitfield must be reset before programming a new value */ + hrtim_timcr2 &= ~(HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM | + HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM); - /* Update the HRTIM TIMxCR2 register */ - hrtim_timcr2 |= pRollOverMode & (HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM | - HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM); + /* Update the HRTIM TIMxCR2 register */ + hrtim_timcr2 |= pRollOverMode & (HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM | + HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM); - hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2; + hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2; } } @@ -9462,7 +9478,7 @@ static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim, * @param Event Event reference * @retval None */ -static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event) @@ -9471,86 +9487,86 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, switch (Event) { - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1; break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2; break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3; break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4; break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5; break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6; break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7; break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9; break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10; break; } - default: - break; + default: + break; } switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger; break; } - default: - break; + default: + break; } } @@ -9562,10 +9578,10 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, * @param pOutputCfg pointer to the output configuration data structure * @retval None */ -static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg) + const HRTIM_OutputCfgTypeDef *pOutputCfg) { uint32_t hrtim_outr; uint32_t hrtim_dtr; @@ -9577,12 +9593,12 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { /* Set the output set/reset crossbar */ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource; @@ -9590,12 +9606,12 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { /* Set the output set/reset crossbar */ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource; @@ -9604,15 +9620,15 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: - break; + default: + break; } /* Clear output config */ hrtim_outr &= ~((HRTIM_OUTR_POL1 | HRTIM_OUTR_IDLM1 | - HRTIM_OUTR_IDLES1| - HRTIM_OUTR_FAULT1| + HRTIM_OUTR_IDLES1 | + HRTIM_OUTR_FAULT1 | HRTIM_OUTR_CHP1 | HRTIM_OUTR_DIDL1) << shift); @@ -9655,7 +9671,7 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, * @param pEventCfg pointer to the event channel configuration data structure * @retval None */ -static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, const HRTIM_EventCfgTypeDef *pEventCfg) { @@ -9670,7 +9686,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, switch (Event) { - case HRTIM_EVENT_NONE: + case HRTIM_EVENT_NONE: { /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR1 = 0U; @@ -9679,7 +9695,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST); hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC); @@ -9693,7 +9709,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST); hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC); @@ -9707,7 +9723,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST); hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC); @@ -9721,7 +9737,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST); hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC); @@ -9735,7 +9751,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST); hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC); @@ -9749,7 +9765,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS); hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC); @@ -9763,7 +9779,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS); hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC); @@ -9777,21 +9793,21 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS); hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC); hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL); hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS); hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F); - hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F ); + hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F); /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS); hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC); @@ -9805,7 +9821,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS); hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC); @@ -9819,8 +9835,8 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: - break; + default: + break; } } @@ -9831,74 +9847,74 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, * @param Event Event channel identifier * @retval None */ -static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event) { switch (Event) { - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1; break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2; break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3; break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4; break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5; break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6; break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7; break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9; break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10; break; } - default: - break; + default: + break; } } @@ -9923,7 +9939,7 @@ static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval Interrupt to enable or disable */ -static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -9933,14 +9949,14 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { - /* Retreives actual OC mode and set interrupt accordingly */ + /* Retrieves actual OC mode and set interrupt accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R; @@ -9953,30 +9969,30 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ interrupt = HRTIM_TIM_IT_SET1; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ interrupt = HRTIM_TIM_IT_RST1; } else { - /* nothing to do */ + /* nothing to do */ } break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { - /* Retreives actual OC mode and set interrupt accordingly */ + /* Retrieves actual OC mode and set interrupt accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R; @@ -9989,24 +10005,24 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ interrupt = HRTIM_TIM_IT_SET2; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ interrupt = HRTIM_TIM_IT_RST2; } else { - /* nothing to do */ + /* nothing to do */ } break; } - default: - break; + default: + break; } return interrupt; @@ -10033,7 +10049,7 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2 * @retval DMA request to enable or disable */ -static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -10043,14 +10059,14 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: - case HRTIM_OUTPUT_TF1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TF1: { - /* Retreives actual OC mode and set dma_request accordingly */ + /* Retrieves actual OC mode and set dma_request accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R; @@ -10063,30 +10079,30 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ dma_request = HRTIM_TIM_DMA_SET1; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ dma_request = HRTIM_TIM_DMA_RST1; } else { - /* nothing to do */ + /* nothing to do */ } break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: - case HRTIM_OUTPUT_TF2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TF2: { - /* Retreives actual OC mode and set dma_request accordingly */ + /* Retrieves actual OC mode and set dma_request accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R; @@ -10099,87 +10115,87 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ dma_request = HRTIM_TIM_DMA_SET2; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ dma_request = HRTIM_TIM_DMA_RST2; } else { - /* nothing to do */ + /* nothing to do */ } break; } - default: - break; + default: + break; } return dma_request; } -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL; + DMA_HandleTypeDef *hdma = (DMA_HandleTypeDef *)NULL; switch (TimerIdx) { - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hdma = hhrtim->hdmaMaster; break; } - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hdma = hhrtim->hdmaTimerA; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hdma = hhrtim->hdmaTimerB; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hdma = hhrtim->hdmaTimerC; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hdma = hhrtim->hdmaTimerD; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hdma = hhrtim->hdmaTimerE; break; } - case HRTIM_TIMERINDEX_TIMER_F: + case HRTIM_TIMERINDEX_TIMER_F: { hdma = hhrtim->hdmaTimerF; break; } - default: - break; + default: + break; } return hdma; } -static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, - const DMA_HandleTypeDef * hdma) +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim, + const DMA_HandleTypeDef *hdma) { uint32_t timed_idx = 0xFFFFFFFFU; @@ -10225,55 +10241,55 @@ static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, * @param TimerIdx Timer index * @retval None */ -static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { switch (TimerIdx) { - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU; break; } - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU; break; } - case HRTIM_TIMERINDEX_TIMER_F: + case HRTIM_TIMERINDEX_TIMER_F: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TFSWU; break; } - default: - break; + default: + break; } } @@ -10283,15 +10299,15 @@ static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) +static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim) { uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); /* Fault 1 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1); @@ -10305,9 +10321,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 2 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2); @@ -10321,9 +10337,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 3 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3); @@ -10337,9 +10353,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 4 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4); @@ -10353,9 +10369,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 5 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5); @@ -10369,9 +10385,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 6 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT6) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT6) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT6) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT6) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT6); @@ -10385,9 +10401,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* System fault event */ - if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT); @@ -10402,11 +10418,11 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /** -* @brief Master timer interrupts service routine -* @param hhrtim pointer to HAL HRTIM handle -* @retval None -*/ -static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) + * @brief Master timer interrupts service routine + * @param hhrtim pointer to HAL HRTIM handle + * @retval None + */ +static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim) { uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); @@ -10414,9 +10430,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER); /* DLL calibration ready event */ - if((uint32_t)(isrflags & HRTIM_FLAG_DLLRDY) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_DLLRDY) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_DLLRDY) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_DLLRDY) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY); @@ -10436,9 +10452,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Burst mode period event */ - if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER); @@ -10452,9 +10468,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 1 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1); @@ -10468,9 +10484,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 2 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2); @@ -10484,9 +10500,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 3 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3); @@ -10500,9 +10516,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 4 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4); @@ -10516,9 +10532,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer repetition event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP); @@ -10532,9 +10548,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Synchronization input event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC); @@ -10548,9 +10564,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer registers update event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD); @@ -10576,17 +10592,17 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @retval None -*/ -static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) + */ +static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR); uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER); /* Timer compare 1 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); @@ -10600,9 +10616,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 2 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); @@ -10616,9 +10632,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 3 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3); @@ -10632,9 +10648,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 4 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4); @@ -10648,9 +10664,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer repetition event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP); @@ -10664,9 +10680,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer registers update event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD); @@ -10680,9 +10696,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 1 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1); @@ -10696,9 +10712,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 2 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2); @@ -10712,9 +10728,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 set event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1); @@ -10728,9 +10744,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1); @@ -10744,9 +10760,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 set event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2); @@ -10760,9 +10776,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2); @@ -10776,9 +10792,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST); @@ -10792,9 +10808,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Delayed protection event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT); @@ -10815,7 +10831,7 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, */ static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET) { @@ -10888,11 +10904,11 @@ static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma) { uint8_t timer_idx; - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma); - if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;} + if (!IS_HRTIM_TIMING_UNIT(timer_idx)) {return;} if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET) { @@ -11013,16 +11029,16 @@ static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma) } /** -* @brief DMA error callback -* @param hdma pointer to DMA handle. -* @retval None -*/ + * @brief DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ static void HRTIM_DMAError(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) - hrtim->ErrorCallback(hrtim); + hrtim->ErrorCallback(hrtim); #else HAL_HRTIM_ErrorCallback(hrtim); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ @@ -11035,10 +11051,10 @@ static void HRTIM_DMAError(DMA_HandleTypeDef *hdma) */ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) - hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); + hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); #else HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_i2s.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_i2s.c index 4c510c109..40eeb9592 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_i2s.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_i2s.c @@ -758,15 +758,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -877,15 +876,14 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -975,15 +973,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1002,6 +999,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, hi2s->TxXferCount = Size; } + __HAL_UNLOCK(hi2s); + /* Enable TXE and ERR interrupt */ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); @@ -1012,7 +1011,6 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, __HAL_I2S_ENABLE(hi2s); } - __HAL_UNLOCK(hi2s); return HAL_OK; } @@ -1041,15 +1039,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1068,6 +1065,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u hi2s->RxXferCount = Size; } + __HAL_UNLOCK(hi2s); + /* Enable RXNE and ERR interrupt */ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); @@ -1078,7 +1077,6 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u __HAL_I2S_ENABLE(hi2s); } - __HAL_UNLOCK(hi2s); return HAL_OK; } @@ -1105,15 +1103,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1155,12 +1152,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Check if the I2S is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } + __HAL_UNLOCK(hi2s); /* Check if the I2S Tx request is already enabled */ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN)) @@ -1169,7 +1161,13 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); } - __HAL_UNLOCK(hi2s); + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + return HAL_OK; } @@ -1196,15 +1194,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1252,12 +1249,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Check if the I2S is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } + __HAL_UNLOCK(hi2s); /* Check if the I2S Rx request is already enabled */ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN)) @@ -1266,7 +1258,13 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); } - __HAL_UNLOCK(hi2s); + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + return HAL_OK; } diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_nand.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_nand.c index 99591335e..8cb2748ee 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_nand.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_nand.c @@ -493,7 +493,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig) { hnand->Config.PageSize = pDeviceConfig->PageSize; hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_opamp_ex.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_opamp_ex.c index d4bfb2f46..07c8d7801 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_opamp_ex.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_opamp_ex.c @@ -75,7 +75,7 @@ * @param hopamp4 handle (1) * @param hopamp5 handle (1) * @param hopamp6 handle (1) - * (1) Parameter not present on STM32GBK1CB/STM32G431xx/STM32G441xx/STM32G471xx devices. + * (1) Parameter not present on STM32GBK1CB/STM32G411xB/STM32G411xC/STM32G431xx/STM32G441xx/STM32G471xx devices. * @retval HAL status * @note Updated offset trimming values (PMOS & NMOS), user trimming is enabled * @note Calibration runs about 25 ms. @@ -83,22 +83,30 @@ #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, - OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4, OPAMP_HandleTypeDef *hopamp5, OPAMP_HandleTypeDef *hopamp6) + OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4, + OPAMP_HandleTypeDef *hopamp5, OPAMP_HandleTypeDef *hopamp6) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3) #elif defined(STM32G491xx) || defined(STM32G4A1xx) HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp6) -#endif +#elif defined(STM32G411xB) || defined(STM32G411xC) +HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1) +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ { uint32_t trimmingvaluen1; uint32_t trimmingvaluep1; +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) uint32_t trimmingvaluen2; uint32_t trimmingvaluep2; uint32_t trimmingvaluen3; uint32_t trimmingvaluep3; -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) uint32_t trimmingvaluen4; uint32_t trimmingvaluep4; uint32_t trimmingvaluen5; @@ -108,16 +116,22 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA #elif defined(STM32G491xx) || defined(STM32G4A1xx) uint32_t trimmingvaluen6; uint32_t trimmingvaluep6; -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ uint32_t delta; - if ((hopamp1 == NULL) || (hopamp2 == NULL) || (hopamp3 == NULL) -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) + if ((hopamp1 == NULL) +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) + || (hopamp2 == NULL) || (hopamp3 == NULL) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || (hopamp4 == NULL) || (hopamp5 == NULL) || (hopamp6 == NULL) #elif defined(STM32G491xx) || defined(STM32G4A1xx) || (hopamp6 == NULL) -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ ) { return HAL_ERROR; @@ -126,6 +140,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA { return HAL_ERROR; } +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) else if (hopamp2->State != HAL_OPAMP_STATE_READY) { return HAL_ERROR; @@ -134,7 +151,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA { return HAL_ERROR; } -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) else if (hopamp4->State != HAL_OPAMP_STATE_READY) { return HAL_ERROR; @@ -152,111 +171,151 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA { return HAL_ERROR; } -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ else { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance)); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) assert_param(IS_OPAMP_ALL_INSTANCE(hopamp4->Instance)); assert_param(IS_OPAMP_ALL_INSTANCE(hopamp5->Instance)); assert_param(IS_OPAMP_ALL_INSTANCE(hopamp6->Instance)); #elif defined(STM32G491xx) || defined(STM32G4A1xx) assert_param(IS_OPAMP_ALL_INSTANCE(hopamp6->Instance)); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* Set Calibration mode */ /* Non-inverting input connected to calibration reference voltage. */ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP); SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP); SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_FORCEVP); SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP); #elif defined(STM32G491xx) || defined(STM32G4A1xx) SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* user trimming values are used for offset calibration */ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM); SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_USERTRIM); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_USERTRIM); SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_USERTRIM); SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_USERTRIM); #elif defined(STM32G491xx) || defined(STM32G4A1xx) SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_USERTRIM); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* Enable calibration */ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALON); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALON); SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_CALON); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_CALON); SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_CALON); SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON); #elif defined(STM32G491xx) || defined(STM32G4A1xx) SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* 1st calibration - N */ /* Select 90% VREF */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); #elif defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* Enable the opamps */ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN); SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN); SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_OPAMPxEN); SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN); #elif defined(STM32G491xx) || defined(STM32G4A1xx) SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* Init trimming counter */ /* Medium value */ trimmingvaluen1 = 16UL; +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) trimmingvaluen2 = 16UL; trimmingvaluen3 = 16UL; -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) trimmingvaluen4 = 16UL; trimmingvaluen5 = 16UL; trimmingvaluen6 = 16UL; #elif defined(STM32G491xx) || defined(STM32G4A1xx) trimmingvaluen6 = 16UL; -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ delta = 8UL; while (delta != 0UL) { /* Set candidate trimming */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3 << OPAMP_INPUT_INVERTING); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); #elif defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ /* Offset trim time: during calibration, minimum time needed between */ @@ -273,7 +332,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* OPAMP_CSR_OUTCAL is LOW try lower trimming */ trimmingvaluen1 -= delta; } - +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL) { /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */ @@ -296,7 +357,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA trimmingvaluen3 -= delta; } -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL) { /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */ @@ -341,7 +404,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* OPAMP_CSR_OUTCAL is LOW try lower trimming */ trimmingvaluen6 -= delta; } -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ delta >>= 1; } @@ -349,15 +412,20 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Still need to check if righ calibration is current value or un step below */ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3 << OPAMP_INPUT_INVERTING); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); #elif defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ /* Offset trim time: during calibration, minimum time needed between */ @@ -371,7 +439,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Set right trimming */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING); } - +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL) { /* OPAMP_CSR_OUTCAL is actually one value more */ @@ -388,7 +458,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3 << OPAMP_INPUT_INVERTING); } -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL) { /* OPAMP_CSR_OUTCAL is actually one value more */ @@ -421,33 +493,43 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Set right trimming */ MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); } -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* 2nd calibration - P */ /* Select 10% VREF */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); #elif defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* Init trimming counter */ /* Medium value */ trimmingvaluep1 = 16UL; +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) trimmingvaluep2 = 16UL; trimmingvaluep3 = 16UL; -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) trimmingvaluep4 = 16UL; trimmingvaluep5 = 16UL; trimmingvaluep6 = 16UL; #elif defined(STM32G491xx) || defined(STM32G4A1xx) trimmingvaluep6 = 16UL; -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ delta = 8UL; @@ -455,15 +537,20 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA { /* Set candidate trimming */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep5 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); #elif defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ /* Offset trim time: during calibration, minimum time needed between */ @@ -480,6 +567,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA trimmingvaluep1 -= delta; } +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL) { /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */ @@ -500,7 +590,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA trimmingvaluep3 -= delta; } -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL) { /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */ @@ -541,7 +633,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA { trimmingvaluep6 -= delta; } -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ delta >>= 1; } @@ -550,15 +642,20 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */ /* Set candidate trimming */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep5 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); #elif defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ /* Offset trim time: during calibration, minimum time needed between */ @@ -573,6 +670,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING); } +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL) { /* Trimming value is actually one value more */ @@ -589,7 +689,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING); } -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL) { /* Trimming value is actually one value more */ @@ -622,43 +724,58 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Set right trimming */ MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); } -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* Disable calibration */ CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALON); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALON); CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_CALON); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_CALON); CLEAR_BIT(hopamp5->Instance->CSR, OPAMP_CSR_CALON); CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON); #elif defined(STM32G491xx) || defined(STM32G4A1xx) CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* Disable the OPAMPs */ CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN); CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN); CLEAR_BIT(hopamp5->Instance->CSR, OPAMP_CSR_OPAMPxEN); CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN); #elif defined(STM32G491xx) || defined(STM32G4A1xx) CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* Set normal operating mode back */ CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP); CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP); CLEAR_BIT(hopamp5->Instance->CSR, OPAMP_CSR_FORCEVP); CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP); #elif defined(STM32G491xx) || defined(STM32G4A1xx) CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* Self calibration is successful */ /* Store calibration(user timing) results in init structure. */ @@ -666,62 +783,87 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Write calibration result N */ hopamp1->Init.TrimmingValueN = trimmingvaluen1; +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) hopamp2->Init.TrimmingValueN = trimmingvaluen2; hopamp3->Init.TrimmingValueN = trimmingvaluen3; -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) hopamp4->Init.TrimmingValueN = trimmingvaluen4; hopamp5->Init.TrimmingValueN = trimmingvaluen5; hopamp6->Init.TrimmingValueN = trimmingvaluen6; #elif defined(STM32G491xx) || defined(STM32G4A1xx) hopamp6->Init.TrimmingValueN = trimmingvaluen6; -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* Write calibration result P */ hopamp1->Init.TrimmingValueP = trimmingvaluep1; +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) hopamp2->Init.TrimmingValueP = trimmingvaluep2; hopamp3->Init.TrimmingValueP = trimmingvaluep3; -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) hopamp4->Init.TrimmingValueP = trimmingvaluep4; hopamp5->Init.TrimmingValueP = trimmingvaluep5; hopamp6->Init.TrimmingValueP = trimmingvaluep6; #elif defined(STM32G491xx) || defined(STM32G4A1xx) hopamp6->Init.TrimmingValueP = trimmingvaluep6; -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ /* Select user timing mode */ /* And updated with calibrated settings */ hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER; +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER; hopamp3->Init.UserTrimming = OPAMP_TRIMMING_USER; -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) hopamp4->Init.UserTrimming = OPAMP_TRIMMING_USER; hopamp5->Init.UserTrimming = OPAMP_TRIMMING_USER; hopamp6->Init.UserTrimming = OPAMP_TRIMMING_USER; #elif defined(STM32G491xx) || defined(STM32G4A1xx) hopamp6->Init.UserTrimming = OPAMP_TRIMMING_USER; -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3 << OPAMP_INPUT_INVERTING); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); #elif defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING); +#if defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ + defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) || \ + defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING); -#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) +#endif /* STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G474xx || \ + STM32G483xx || STM32G484xx || STM32G491xx || STM32G4A1xx */ +#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx) MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep5 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); #elif defined(STM32G491xx) || defined(STM32G4A1xx) MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); -#endif +#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */ } diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_pcd.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_pcd.c index 606551cec..6f021c3c0 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_pcd.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_pcd.c @@ -1809,7 +1809,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } } @@ -1930,7 +1929,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2006,7 +2005,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2038,11 +2037,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2092,6 +2091,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2103,10 +2108,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2137,7 +2144,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2165,6 +2172,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2177,10 +2190,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2210,7 +2225,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -2219,7 +2234,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_pwr_ex.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_pwr_ex.c index aad092537..f53c9292a 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_pwr_ex.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_pwr_ex.c @@ -42,7 +42,7 @@ #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G414xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) #define PWR_PORTF_AVAILABLE_PINS 0x0000FFFFU /* PF0..PF15 */ #define PWR_PORTG_AVAILABLE_PINS 0x000007FFU /* PG0..PG10 */ -#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) || defined (STM32G491xx) || defined (STM32G4A1xx) +#elif defined (STM32G411xB) || defined (STM32G411xC) || defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) || defined (STM32G491xx) || defined (STM32G4A1xx) #define PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */ #define PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */ #endif /* STM32G471xx || STM32G473xx || STM32G414xx || STM32G474xx || STM32G483xx || STM32G484xx */ diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_rcc_ex.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_rcc_ex.c index f08f8aa26..7b652420e 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_rcc_ex.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_rcc_ex.c @@ -553,6 +553,13 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | \ RCC_PERIPHCLK_RTC; +#elif defined(STM32G411xB) || defined(STM32G411xC) + + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_UART4 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | \ + RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_RTC; + #elif defined(STM32GBK1CB) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_rtc_ex.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_rtc_ex.c index a563c2884..7e5742e0c 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_rtc_ex.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_rtc_ex.c @@ -1363,7 +1363,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef /* Configuration register 2 */ tmpreg = READ_REG(TAMP->CR2); - tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MF_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) { @@ -1372,7 +1372,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { - tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MF_Pos); + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); } if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) @@ -1423,7 +1423,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /* Configuration register 2 */ tmpreg = READ_REG(TAMP->CR2); - tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MF_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) { @@ -1432,7 +1432,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { - tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MF_Pos); + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); } if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) @@ -1478,13 +1478,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) { + UNUSED(hrtc); + assert_param(IS_RTC_TAMPER(Tamper)); /* Disable the selected Tamper pin */ CLEAR_BIT(TAMP->CR1, Tamper); /* Clear tamper mask/noerase/trigger configuration */ - CLEAR_BIT(TAMP->CR2, ((Tamper << TAMP_CR2_TAMP1TRG_Pos) | (Tamper << TAMP_CR2_TAMP1MF_Pos) | (Tamper << TAMP_CR2_TAMP1NOERASE_Pos))); + CLEAR_BIT(TAMP->CR2, ((Tamper << TAMP_CR2_TAMP1TRG_Pos) | (Tamper << TAMP_CR2_TAMP1MSK_Pos) | (Tamper << TAMP_CR2_TAMP1NOERASE_Pos))); /* Clear tamper interrupt mode configuration */ CLEAR_BIT(TAMP->IER, Tamper); diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_spi.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_spi.c index cd330e653..60c10a060 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_spi.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_spi.c @@ -44,7 +44,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -190,7 +191,8 @@ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -818,38 +820,35 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; uint16_t initial_TxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); initial_TxXferCount = Size; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -888,7 +887,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -898,7 +897,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -907,9 +906,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -922,13 +921,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr ++; hspi->TxXferCount--; } @@ -941,13 +940,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -957,9 +956,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -984,19 +983,18 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint __HAL_SPI_CLEAR_OVRFLAG(hspi); } + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; } /** @@ -1016,12 +1014,15 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -1031,17 +1032,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } + /* Process Locked */ + __HAL_LOCK(hspi); /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1113,9 +1108,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1137,9 +1132,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1156,8 +1151,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* the latest data has not been received */ - errorcode = HAL_TIMEOUT; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Receive last data in 16 Bit mode */ @@ -1175,8 +1170,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC to Flush DR and RXNE flag */ @@ -1202,8 +1198,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1229,18 +1226,17 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } #endif /* USE_SPI_CRC */ + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** @@ -1253,8 +1249,8 @@ error : * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; @@ -1271,14 +1267,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1293,18 +1285,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1316,7 +1310,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1356,7 +1350,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -1379,7 +1373,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1410,9 +1404,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1423,13 +1417,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -1454,13 +1448,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -1506,9 +1500,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1522,8 +1516,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) @@ -1548,8 +1543,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1565,30 +1561,32 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { - errorcode = HAL_ERROR; hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** @@ -1599,9 +1597,8 @@ error : * @param Size amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1609,14 +1606,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } /* Process Locked */ @@ -1625,7 +1620,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1673,8 +1668,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** @@ -1687,13 +1681,15 @@ error : */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -1704,12 +1700,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -1781,8 +1771,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Enable RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** @@ -1794,11 +1783,11 @@ error : * @param Size amount of data to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1808,16 +1797,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } /* Process locked */ @@ -1831,7 +1819,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1892,8 +1880,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Enable TXE, RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** @@ -1904,9 +1891,8 @@ error : * @param Size amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1914,25 +1900,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1994,9 +1978,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2006,16 +1990,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2030,15 +2014,17 @@ error : */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -2055,12 +2041,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2138,9 +2118,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2150,16 +2130,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2172,12 +2152,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u * @param Size amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); @@ -2186,26 +2165,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -2214,7 +2192,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2305,9 +2283,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -2326,9 +2304,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2337,16 +2315,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2439,7 +2418,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2472,7 +2452,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2727,9 +2708,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() */ /* Abort the SPI DMA tx Stream/Channel */ @@ -3019,7 +3002,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -3031,7 +3014,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -3058,7 +3041,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; /* Init tickstart for timeout management*/ @@ -3115,7 +3098,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3232,7 +3215,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3270,7 +3253,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) } else { - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -3332,7 +3316,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3350,7 +3334,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3368,7 +3352,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3386,7 +3370,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3409,7 +3393,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3431,7 +3415,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->hdmatx->XferAbortCallback = NULL; @@ -3447,7 +3431,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3497,7 +3482,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3514,7 +3499,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3650,14 +3636,14 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Transmit data in packing Bit mode */ if (hspi->TxXferCount >= 2U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } /* Transmit data in 8 Bit mode */ else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -3751,7 +3737,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3904,7 +3890,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3930,7 +3916,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -4032,7 +4018,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; - __IO uint8_t *ptmpreg8; + __IO const uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Adjust Timeout value in case of end of transfer */ @@ -4387,7 +4373,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4430,7 +4417,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4459,7 +4447,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_sram.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_sram.c index a1425a9dc..7f252d275 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_sram.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_sram.c @@ -1038,6 +1038,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1060,6 +1061,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1082,6 +1084,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_tim_ex.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_tim_ex.c index e02903037..972616ab5 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_tim_ex.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_tim_ex.c @@ -2357,6 +2357,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos; break; } +#if defined (COMP2) case TIM_BREAKINPUTSOURCE_COMP2: { bkin_enable_mask = TIM1_AF1_BKCMP2E; @@ -2365,6 +2366,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; break; } +#endif /* COMP2 */ case TIM_BREAKINPUTSOURCE_COMP3: { bkin_enable_mask = TIM1_AF1_BKCMP3E; @@ -2373,6 +2375,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos; break; } +#if defined (COMP4) case TIM_BREAKINPUTSOURCE_COMP4: { bkin_enable_mask = TIM1_AF1_BKCMP4E; @@ -2381,6 +2384,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos; break; } +#endif /* COMP4 */ #if defined (COMP5) case TIM_BREAKINPUTSOURCE_COMP5: { diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_uart.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_uart.c index ba9df1e60..edb49009a 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_uart.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_hal_uart.c @@ -3817,7 +3817,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_adc.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_adc.c index 907fbb3d1..092a253c7 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_adc.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_adc.c @@ -250,7 +250,7 @@ ) \ ) \ ) -#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ @@ -490,7 +490,7 @@ ) \ ) \ ) -#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_comp.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_comp.c index 3c840a080..cc573b9a1 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_comp.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_comp.c @@ -117,6 +117,26 @@ (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \ )) +#elif defined(STM32G411xB) || defined(STM32G411xC) +#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) || \ + (((__COMP_INSTANCE__) == COMP1) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP2) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \ + ) || \ + (((__COMP_INSTANCE__) == COMP3) && \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \ + )) #endif #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \ @@ -254,6 +274,29 @@ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \ ) +#elif defined(STM32G411xB) || defined(STM32G411xC) +#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + ((((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ + || \ + (((__INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ + || \ + (((__INSTANCE__) == COMP3) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ + ) #endif /** * @} diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_dac.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_dac.c index f47938f67..f1579a5a0 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_dac.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_dac.c @@ -53,6 +53,14 @@ (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)) \ ) +#elif defined(STM32G411xB) || defined(STM32G411xC) +#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ + (((__DACX__) == DAC1) ? \ + ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ + : \ + (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ + || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)) \ + ) #else #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ @@ -77,7 +85,7 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_RST_TRG5) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_RST_TRG6) \ || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ - : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ + : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ || (((__DACX__) == DAC1) && ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_TRGO1))\ || (((__DACX__) == DAC2) && ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_TRGO2))\ || (((__DACX__) == DAC3) && ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_TRGO3))\ @@ -94,7 +102,7 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ - : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ + : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ ) #endif /* STM32G414xx || STM32G474xx || STM32G484xx */ @@ -115,7 +123,7 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6) \ || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ - : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ + : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ ) #else #define IS_LL_DAC_TRIGGER_SOURCE2(__DACX__, __TRIGGER_SOURCE__) \ @@ -128,7 +136,7 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ || (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ - : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ + : ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \ ) #endif /* STM32G414xx || STM32G474xx || STM32G484xx */ diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_fmc.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_fmc.c index 2a6a2f601..9ccb56ee2 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_fmc.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_fmc.c @@ -59,7 +59,7 @@ * @{ */ #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) \ - || defined(HAL_SRAM_MODULE_ENABLED) + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -176,7 +176,7 @@ * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init) + const FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; uint32_t btcr_reg; @@ -364,7 +364,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { uint32_t tmpr; @@ -381,14 +381,15 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set FMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | - ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) | - ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | - (Timing->AccessMode))); + Device->BTCR[Bank + 1U] = + (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | + (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | + (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | + (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) | + (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | + ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | + ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | + Timing->AccessMode; /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) @@ -414,7 +415,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) { /* Check the parameters */ @@ -563,7 +564,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @param Init Pointer to NAND Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -596,7 +597,7 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -610,10 +611,10 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos))); + Device->PMEM = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); return HAL_OK; } @@ -627,7 +628,7 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -641,10 +642,10 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos))); + Device->PATT = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); return HAL_OK; } @@ -748,7 +749,7 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { uint32_t tickstart; @@ -788,7 +789,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui #endif /* FMC_BANK3 */ - /** * @} */ diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_rcc.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_rcc.c index d2b00dbf5..3ccc07816 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_rcc.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_rcc.c @@ -41,7 +41,7 @@ #if defined(RCC_CCIPR_USART3SEL) #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ - || (__VALUE__) == LL_RCC_USART3_CLKSOURCE) + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) #else #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_spi.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_spi.c index ecce5e2c1..178dd8ca9 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_spi.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_spi.c @@ -130,7 +130,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; @@ -191,8 +191,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the + * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior + * calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) @@ -379,7 +380,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx) { return LL_SPI_DeInit(SPIx); } diff --git a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_usb.c b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_usb.c index 61a3edb09..ad8909f2f 100644 --- a/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_usb.c +++ b/stm32cube/stm32g4xx/drivers/src/stm32g4xx_ll_usb.c @@ -319,6 +319,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -423,7 +427,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -525,9 +529,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -559,19 +563,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -580,15 +590,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -599,18 +607,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -654,26 +652,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } diff --git a/stm32cube/stm32g4xx/soc/stm32g411xb.h b/stm32cube/stm32g4xx/soc/stm32g411xb.h new file mode 100644 index 000000000..11cc46300 --- /dev/null +++ b/stm32cube/stm32g4xx/soc/stm32g411xb.h @@ -0,0 +1,11550 @@ +/** + ****************************************************************************** + * @file stm32g411xb.h + * @author MCD Application Team + * @brief CMSIS STM32G411xB Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g411xb + * @{ + */ + +#ifndef __STM32G411xB_H +#define __STM32G411xB_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_IRQn = 65, /*!< COMP4 */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 16u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ +} TAMP_TypeDef; + + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + + + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 128 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */ +#define SRAM2_BASE (0x20004000UL) /*!< SRAM2(6 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(10 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */ +#define SRAM2_SIZE (0x00001800UL) /*!< SRAM2 size (6 KBytes) */ +#define CCMSRAM_SIZE (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ + __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ + __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ + __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ + uint32_t RESERVED3[7]; /*!< Reserved3, Address offset: 0x54 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ + __IO uint32_t SEC2R; /*!< FLASH Securable memory register bank2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 32u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ +} TAMP_TypeDef; + + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + + + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 256 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */ +#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(16 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ +#define CCMSRAM_SIZE (0x00004000UL) /*!< CCMSRAM size (16 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL) +#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM20 ((TIM_TypeDef *) TIM20_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ -#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) +#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) -#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ +#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_cortex.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_cortex.h index d6fe1ea25..dc6bd5789 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_cortex.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_cortex.h @@ -123,14 +123,10 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< MPU is disabled during HardFault and NMI handlers, - privileged software access to the default memory map is disabled */ -#define MPU_HARDFAULT_NMI 2U /*!< MPU is enabled during HardFault and NMI handlers, - privileged software access to the default memory map is disabled */ -#define MPU_PRIVILEGED_DEFAULT 4U /*!< MPU is disabled during HardFault and NMI handlers, - privileged software access to the default memory map is enabled */ -#define MPU_HFNMI_PRIVDEF 6U /*!< MPU is enabled during HardFault and NMI handlers, - privileged software access to the default memory map is enabled */ +#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -138,8 +134,8 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ -#define MPU_REGION_ENABLE 1U /*!< MPU region enabled */ -#define MPU_REGION_DISABLE 0U /*!< MPU region disabled */ +#define MPU_REGION_ENABLE 1U /*!< Enable region */ +#define MPU_REGION_DISABLE 0U /*!< Disable region */ /** * @} */ @@ -147,8 +143,8 @@ typedef struct /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ -#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< MPU region execution permitted (if read permitted) */ -#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< MPU region execution not permitted */ +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */ +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */ /** * @} */ @@ -156,9 +152,9 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ -#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< MPU region not shareable */ -#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< MPU region outer shareable */ -#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< MPU region inner shareable */ +#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */ +#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */ +#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */ /** * @} */ @@ -166,10 +162,10 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_PRIV_RW 0U /*!< MPU region Read/write by privileged code only */ -#define MPU_REGION_ALL_RW 1U /*!< MPU region Read/write by any privilege level */ -#define MPU_REGION_PRIV_RO 2U /*!< MPU region Read-only by privileged code only */ -#define MPU_REGION_ALL_RO 3U /*!< MPU region Read-only by any privilege level */ +#define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */ +#define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */ +#define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */ +#define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */ /** * @} */ @@ -213,18 +209,26 @@ typedef struct /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes * @{ */ -#define MPU_DEVICE_nGnRnE 0x0U /*!< Device, noGather, noReorder, noEarly acknowledge. */ -#define MPU_DEVICE_nGnRE 0x4U /*!< Device, noGather, noReorder, Early acknowledge. */ -#define MPU_DEVICE_nGRE 0x8U /*!< Device, noGather, Reorder, Early acknowledge. */ -#define MPU_DEVICE_GRE 0xCU /*!< Device, Gather, Reorder, Early acknowledge. */ +/* Device memory attributes */ +#define MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ -#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ +/* Normal memory attributes */ +/* To set with INNER_OUTER() macro for both inner/outer cache attributes */ + +/* Non-cacheable memory attribute */ #define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */ -#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ +#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ +/* - transient mode attribute */ #define MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */ #define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */ - +/* - allocation attribute */ #define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */ #define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */ #define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_dac.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_dac.h index d147af57f..01c13b4e7 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_dac.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_dac.h @@ -297,10 +297,13 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) -#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) -#define DAC_CHIPCONNECT_BOTH (1UL << 2) - +#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/ +#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. */ +#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. + Note: this connection is not available in mode normal + with buffer disabled. */ /** * @} */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_def.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_def.h index fe75b0d49..b01fcfa51 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_def.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_def.h @@ -175,7 +175,7 @@ typedef enum /** * @brief __RAM_FUNC definition */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) /* ARM Compiler @@ -208,7 +208,7 @@ typedef enum /** * @brief __NOINLINE definition */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) || defined ( __GNUC__ ) +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) || defined ( __GNUC__ ) /* ARM & GNUCompiler */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_eth.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_eth.h index c32b34c6a..153c2c369 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_eth.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_eth.h @@ -105,7 +105,7 @@ typedef struct uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*> 10) #endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || \ - defined(STM32H523xx) || defined(STM32H503xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || \ - defined(STM32H5E5xx) || defined(STM32H5E4xx)*/ + defined(STM32H523xx) || defined(STM32H503xx) */ /** diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_hcd.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_hcd.h index c73f5e17b..3c515a292 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_hcd.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_hcd.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_ll_usb.h" -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32H5xx_HAL_Driver * @{ */ @@ -53,12 +53,20 @@ typedef enum HAL_HCD_STATE_TIMEOUT = 0x04 } HCD_StateTypeDef; +#if defined (USB_DRD_FS) typedef USB_DRD_TypeDef HCD_TypeDef; typedef USB_DRD_CfgTypeDef HCD_InitTypeDef; typedef USB_DRD_HCTypeDef HCD_HCTypeDef; typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef; typedef USB_DRD_HCStateTypeDef HCD_HCStateTypeDef; - +#else +typedef USB_OTG_GlobalTypeDef HCD_TypeDef; +typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; +typedef USB_OTG_HCTypeDef HCD_HCTypeDef; +typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; +#endif /* defined (USB_DRD_FS) */ +#if defined (USB_DRD_FS) typedef enum { HCD_HCD_STATE_DISCONNECTED = 0x00U, @@ -73,7 +81,7 @@ typedef enum * 8Bytes each Block 32Bit in each word */ #define PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U)) - +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -90,13 +98,13 @@ typedef struct HCD_TypeDef *Instance; /*!< Register base address */ HCD_InitTypeDef Init; /*!< HCD required parameters */ HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ - +#if defined (USB_DRD_FS) uint32_t ep0_PmaAllocState; /*!< EP0 PMA allocation State (allocated, virtual Ch, EP0 direction) */ uint16_t phy_chin_state[8]; /*!< Physical Channel in State (Used/Free) */ uint16_t phy_chout_state[8]; /*!< Physical Channel out State (Used/Free)*/ uint32_t PMALookupTable[PMA_BLOCKS]; /*PMA LookUp Table */ HCD_HostStateTypeDef HostState; /*!< USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME */ - +#endif /* defined (USB_DRD_FS) */ HAL_LockTypeDef Lock; /*!< HCD peripheral status */ __IO HCD_StateTypeDef State; /*!< HCD communication state */ __IO uint32_t ErrorCode; /*!< HCD Error code */ @@ -130,6 +138,7 @@ typedef struct /** @defgroup HCD_Speed HCD Speed * @{ */ +#define HCD_SPEED_HIGH USBH_HS_SPEED #define HCD_SPEED_FULL USBH_FSLS_SPEED #define HCD_SPEED_LOW USBH_FSLS_SPEED /** @@ -181,11 +190,29 @@ typedef struct #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ & (__INTERRUPT__)) == (__INTERRUPT__)) +#if defined (USB_DRD_FS) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) +#else +#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \ + ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__)) + +#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) +#endif /* defined (USB_DRD_FS) */ #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) +#if defined (USB_DRD_FS) #define __HAL_HCD_GET_CHNUM(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN) #define __HAL_HCD_GET_CHDIR(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR) +#else +#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) +#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT) +#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN) +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -205,9 +232,9 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); - +#if defined (USB_DRD_FS) HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num); - +#endif /* defined (USB_DRD_FS) */ void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); @@ -282,10 +309,10 @@ void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); - +#if defined (USB_DRD_FS) void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd); void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd); - +#endif /* defined (USB_DRD_FS) */ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state); /** @@ -299,11 +326,11 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); - +#if defined (USB_DRD_FS) HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd); - +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -319,7 +346,7 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, u uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); - +#if defined (USB_DRD_FS) /* PMA Allocation functions **********************************************/ /** @addtogroup PMA Allocation * @{ @@ -333,7 +360,7 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); /** * @} */ - +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -343,7 +370,7 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); /** @defgroup HCD_Private_Macros HCD Private Macros * @{ */ - +#if defined (USB_DRD_FS) #define HCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) #define HCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) @@ -577,7 +604,7 @@ __STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint1 return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum)); } - +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -593,7 +620,7 @@ __STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint1 /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_i2s.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_i2s.h index bbd0a528d..a9030e38d 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_i2s.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_i2s.h @@ -505,6 +505,11 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); +/* IO Swap feature */ +HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s); + /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_lptim.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_lptim.h index 228003eb5..303706eef 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_lptim.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_lptim.h @@ -1086,9 +1086,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ - ((__AUTORELOAD__) <= 0x0000FFFFUL)) - #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) #define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_pcd.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_pcd.h index ca798235a..86a762c08 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_pcd.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_pcd.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_ll_usb.h" -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32H5xx_HAL_Driver * @{ @@ -80,9 +80,16 @@ typedef enum } PCD_BCD_MsgTypeDef; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +typedef USB_OTG_GlobalTypeDef PCD_TypeDef; +typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; +typedef USB_OTG_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) typedef USB_DRD_TypeDef PCD_TypeDef; typedef USB_DRD_CfgTypeDef PCD_InitTypeDef; typedef USB_DRD_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_DRD_FS) */ /** * @brief PCD Handle Structure definition @@ -96,14 +103,21 @@ typedef struct PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ __IO uint8_t USB_Address; /*!< USB Address */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ +#endif /* defined (USB_DRD_FS) */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ __IO PCD_StateTypeDef State; /*!< PCD communication state */ __IO uint32_t ErrorCode; /*!< PCD Error code */ uint32_t Setup[12]; /*!< Setup packet buffer */ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; + uint32_t FrameNumber; /*!< Store Current Frame number */ uint32_t lpm_active; /*!< Enable or disable the Link Power Management . @@ -149,6 +163,8 @@ typedef struct /** @defgroup PCD_Speed PCD Speed * @{ */ +#define PCD_SPEED_HIGH USBD_HS_SPEED +#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED #define PCD_SPEED_FULL USBD_FS_SPEED /** * @} @@ -191,13 +207,25 @@ typedef struct #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ - &= (uint16_t)(~(__INTERRUPT__))) +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) -#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR2 |= USB_WAKEUP_EXTI_LINE -#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR2 &= ~(USB_WAKEUP_EXTI_LINE) +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ + ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ + &= (uint16_t)(~(__INTERRUPT__))) +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -334,6 +362,10 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); /** * @} @@ -359,15 +391,19 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 15) /*!< USB FS EXTI Line WakeUp Interrupt */ +#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 28) /*!< USB HS EXTI Line WakeUp Interrupt */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - +#if defined (USB_DRD_FS) #define USB_WAKEUP_EXTI_LINE (0x1U << 15) /*!< USB FS EXTI Line WakeUp Interrupt */ - +#endif /* defined (USB_DRD_FS) */ /** * @} */ - +#if defined (USB_DRD_FS) /** @defgroup PCD_EP0_MPS PCD EP0 MPS * @{ */ @@ -402,16 +438,42 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** * @} */ - +#endif /* defined (USB_DRD_FS) */ /** * @} */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#ifndef USB_OTG_DOEPINT_OTEPSPR +#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ + +#ifndef USB_OTG_DOEPMSK_OTEPSPRM +#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ + +#ifndef USB_OTG_DOEPINT_NAK +#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ +#endif /* defined USB_OTG_DOEPINT_NAK */ + +#ifndef USB_OTG_DOEPMSK_NAKM +#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NAKM */ + +#ifndef USB_OTG_DOEPINT_STPKTRX +#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_STPKTRX */ + +#ifndef USB_OTG_DOEPMSK_NYETM +#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NYETM */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros * @{ */ - +#if defined (USB_DRD_FS) /* PMA RX counter */ #ifndef PCD_RX_PMA_CNT #define PCD_RX_PMA_CNT 10U @@ -607,7 +669,7 @@ __STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(const PCD_TypeDef *Instance, uint1 return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bEpNum)); } - +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -620,7 +682,7 @@ __STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(const PCD_TypeDef *Instance, uint1 /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_pcd_ex.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_pcd_ex.h index eb75ab685..cb91e40ff 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_pcd_ex.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_pcd_ex.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_hal_def.h" -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32H5xx_HAL_Driver * @{ */ @@ -45,11 +45,15 @@ extern "C" { /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - +#if defined (USB_DRD_FS) HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); - +#endif /* defined (USB_DRD_FS) */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); @@ -77,7 +81,7 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_pka.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_pka.h index a96befc26..cadb56f2e 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_pka.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_pka.h @@ -107,6 +107,9 @@ typedef struct PKA_TypeDef *Instance; /*!< Register base address */ __IO HAL_PKA_StateTypeDef State; /*!< PKA state */ __IO uint32_t ErrorCode; /*!< PKA Error code */ + __IO uint32_t primeordersize; /*!< Elliptic curve prime order length */ + __IO uint32_t opsize; /*!< Modular exponentiation operand length */ + __IO uint32_t modulussize; /*!< Elliptic curve modulus length */ #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */ void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Error callback */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rcc.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rcc.h index 3a73efd8e..2f3ed7912 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rcc.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rcc.h @@ -873,6 +873,7 @@ typedef struct #define __HAL_RCC_ETHTX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) #define __HAL_RCC_ETHRX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) + #endif /*ETH*/ #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) @@ -1122,6 +1123,7 @@ typedef struct #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) #endif /* SAES */ + #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) #if defined(SRAM3_BASE) @@ -1149,16 +1151,6 @@ typedef struct } while(0) #endif /* OTFDEC1 */ -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OTFDEC2 */ - #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1199,34 +1191,10 @@ typedef struct } while(0) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OCTOSPIM */ - #if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) #endif /* OTFDEC1 */ -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN) -#endif /* OTFDEC2 */ - #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) #endif /* SDMMC1 */ @@ -1243,13 +1211,6 @@ typedef struct #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN) -#endif /* OCTOSPIM */ /** * @} */ @@ -1802,25 +1763,6 @@ typedef struct } while(0) #endif /*USB_DRD_FS*/ -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /*LTDC*/ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /*GFXTIM*/ #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) @@ -1863,14 +1805,6 @@ typedef struct #if defined(USB_DRD_FS) #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) #endif /* USB_DRD_FS */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) -#endif /* GFXTIM */ /** * @} */ @@ -2004,24 +1938,6 @@ typedef struct UNUSED(tmpreg); \ } while(0) -#if defined (PLAY1) -#define __HAL_RCC_PLAY1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_PLAY1APB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* PLAY1 */ - #define __HAL_RCC_SBS_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) #if defined(SPI5) @@ -2066,10 +1982,6 @@ typedef struct #define __HAL_RCC_RTC_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) -#if defined (PLAY1) -#define __HAL_RCC_PLAY1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN) -#define __HAL_RCC_PLAY1APB_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN) -#endif /* PLAY1 */ /** * @} */ @@ -2372,10 +2284,6 @@ typedef struct #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) != 0U) #endif /* OTFDEC1 */ -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN) != 0U) -#endif /* OTFDEC2 */ - #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) != 0U) #endif /* SDMMC1 */ @@ -2392,22 +2300,10 @@ typedef struct #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) != 0U) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN) != 0U) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN) != 0U) -#endif /* OCTOSPIM */ - #if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) == 0U) #endif /* OTFDEC1 */ -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC2EN) == 0U) -#endif /* OTFDEC2 */ - #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) == 0U) #endif /* SDMMC1 */ @@ -2424,14 +2320,6 @@ typedef struct #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) == 0U) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI2EN) == 0U) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPIMEN) == 0U) -#endif /* OCTOSPIM */ - /** * @} */ @@ -2710,14 +2598,6 @@ typedef struct #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) #endif /* USB_DRD_FS */ -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) != 0U) -#endif /* GFXTIM */ - #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) @@ -2759,14 +2639,6 @@ typedef struct #if defined(USB_DRD_FS) #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) #endif /* USB_DRD_FS */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) == 0U) -#endif /* GFXTIM */ /** * @} */ @@ -2823,11 +2695,6 @@ typedef struct #define __HAL_RCC_RTC_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) -#if defined(PLAY1) -#define __HAL_RCC_PLAY1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN) != 0U) -#define __HAL_RCC_PLAY1APB_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN) != 0U) -#endif /* PLAY1 */ - #define __HAL_RCC_SBS_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) == 0U) #if defined(SPI5) @@ -2872,11 +2739,6 @@ typedef struct #define __HAL_RCC_RTC_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) -#if defined(PLAY1) -#define __HAL_RCC_PLAY1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1EN) == 0U) -#define __HAL_RCC_PLAY1APB_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_PLAY1APBEN) == 0U) -#endif /* PLAY1 */ - /** * @} */ @@ -3026,10 +2888,6 @@ typedef struct #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) #endif /* SAES*/ -#if defined(RCC_AHB2RSTR_OTGHSPHYRST) -#define __HAL_RCC_OTGPHY_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGHSPHYRST) -#endif /* RCC_AHB2RSTR_OTGHSPHYRST */ - #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) @@ -3085,10 +2943,6 @@ typedef struct #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) #endif /* SAES*/ -#if defined(RCC_AHB2RSTR_OTGHSPHYRST) -#define __HAL_RCC_OTGPHY_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGHSPHYRST) -#endif /* RCC_AHB2RSTR_OTGHSPHYRST */ - /** * @} */ @@ -3122,18 +2976,6 @@ typedef struct #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI2RST) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPIMRST) -#endif /* OCTOSPIM */ - -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC2RST) -#endif /* OTFDEC2 */ - #if defined(FMC_BASE) #define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00000000U) #endif /* FMC_BASE */ @@ -3158,18 +3000,6 @@ typedef struct #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI2RST) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPIMRST) -#endif /* OCTOSPIM */ - -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC2RST) -#endif /* OTFDEC2 */ - /** * @} */ @@ -3446,14 +3276,6 @@ typedef struct #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) #endif /* SAI2 */ -#if defined(LTDC) -#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) -#endif /* GFXTIM */ - #if defined(USB_DRD_FS) #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) #endif /* USB_DRD_FS */ @@ -3498,14 +3320,6 @@ typedef struct #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) #endif /* SAI2 */ -#if defined(LTDC) -#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) -#endif /* GFXTIM */ - #if defined(USB_DRD_FS) #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) #endif /* USB_DRD_FS */ @@ -3561,11 +3375,6 @@ typedef struct #define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) #endif /* VREFBUF */ -#if defined(PLAY1) -#define __HAL_RCC_PLAY1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1RST) -#define __HAL_RCC_PLAY1POR_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1POR) -#endif /* PLAY1 */ - #define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) #if defined(SPI5) @@ -3608,10 +3417,6 @@ typedef struct #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) #endif /* VREFBUF */ -#if defined(PLAY1) -#define __HAL_RCC_PLAY1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1RST) -#define __HAL_RCC_PLAY1POR_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_PLAY1POR) -#endif /* PLAY1 */ /** * @} */ @@ -3647,10 +3452,6 @@ typedef struct #define __HAL_RCC_ETHTX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) #define __HAL_RCC_ETHRX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) - -#if defined(RCC_AHB1LPENR_ETHCKLPEN) -#define __HAL_RCC_ETHINTERN_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHCKLPEN) -#endif /* RCC_AHB1LPENR_ETHCKLPEN */ #endif /* ETH */ #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) @@ -3690,10 +3491,6 @@ typedef struct #define __HAL_RCC_ETHTX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) #define __HAL_RCC_ETHRX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) - -#if defined(RCC_AHB1LPENR_ETHCKLPEN) -#define __HAL_RCC_ETHINTERN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHCKLPEN) -#endif /* RCC_AHB1LPENR_ETHCKLPEN */ #endif /* ETH */ #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) @@ -3754,10 +3551,6 @@ typedef struct #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility */ #endif /* DCMI */ -#if defined(RCC_AHB2LPENR_OTGPHYLPEN) -#define __HAL_RCC_OTGPHY_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_OTGPHYLPEN); -#endif /* RCC_AHB2LPENR_OTGPHYLPEN */ - #if defined(AES) #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); #endif /* AES */ @@ -3817,10 +3610,6 @@ typedef struct #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility */ #endif /* DCMI */ -#if defined(RCC_AHB2LPENR_OTGPHYLPEN) -#define __HAL_RCC_OTGPHY_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_OTGPHYLPEN) -#endif /* RCC_AHB2LPENR_OTGPHYLPEN */ - #if defined(AES) #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); #endif /* AES */ @@ -3857,10 +3646,6 @@ typedef struct #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) #endif /* OTFDEC1 */ -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC2LPEN) -#endif /* OTFDEC2 */ - #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) #endif /* SDMMC1*/ @@ -3877,22 +3662,10 @@ typedef struct #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI2LPEN) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPIMLPEN) -#endif /* OCTOSPIM */ - #if defined(OTFDEC1) #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) #endif /* OTFDEC1 */ -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC2LPEN) -#endif /* OTFDEC2 */ - #if defined(SDMMC1) #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) #endif /* SDMMC1*/ @@ -3909,14 +3682,6 @@ typedef struct #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) #endif /* OCTOSPI1 */ -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI2LPEN) -#endif /* OCTOSPI2 */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPIMLPEN) -#endif /* OCTOSPIM */ - /** * @} */ @@ -4186,14 +3951,6 @@ typedef struct #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) #endif /* SAI2 */ -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_LTDCLPEN) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_GFXTIMLPEN) -#endif /* GFXTIM */ - #if defined(USB_DRD_FS) #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) #endif /* USB_DRD_FS */ @@ -4236,15 +3993,6 @@ typedef struct #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) #endif /* SAI2 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_LTDCLPEN) -#endif /* LTDC */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_GFXTMLPEN) -#endif /* GFXTIM */ - #if defined(USB_DRD_FS) #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) #endif /* USB_DRD_FS */ @@ -4303,10 +4051,6 @@ typedef struct #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) -#if defined(PLAY1) -#define __HAL_RCC_PLAY1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_PLAY1LPEN) -#endif /* PLAY1 */ - #define __HAL_RCC_SBS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN) #if defined(SPI5) @@ -4351,9 +4095,6 @@ typedef struct #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) -#if defined(PLAY1) -#define __HAL_RCC_PLAY1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_PLAY1LPEN) -#endif /* PLAY1 */ /** * @} */ @@ -5316,16 +5057,10 @@ typedef struct ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ ((DIV) == RCC_MCODIV_15)) -#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) -#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ - ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) -#else #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ ((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) -#endif /* STM32H5E5xx || STM32H5E4xx || !STM32H5F5xx || STM32H5F4xx */ #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_CSI) || \ ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rcc_ex.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rcc_ex.h index e9d7b77b3..b72a8063b 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rcc_ex.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rcc_ex.h @@ -429,6 +429,16 @@ typedef struct * @} */ +#if defined(PWR_USBSCR_OTGHSEN) +/** @defgroup OTGHS_CLK48_VALUE OTG_HS output clock + * @{ + */ +#define OTGHS_CLK48_VALUE 48000000U /*!< Value of the OTGHS_CLK48 in Hz*/ +/** + * @} + */ +#endif /* PWR_USBSCR_OTGHSEN */ + /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection * @{ */ @@ -531,6 +541,7 @@ typedef struct #if defined(I3C2) #define RCC_PERIPHCLK_I3C2 ((uint64_t)0x100000000000U) #endif /* I3C2 */ + /** * @} */ @@ -1372,6 +1383,7 @@ typedef struct #define __HAL_RCC_TIMIC_ENABLE() SET_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< HSI/1024, CSI/128 and HSI/8 generation for Timers 12,15 and LPTimer2 Input capture */ #define __HAL_RCC_TIMIC_DISABLE() CLEAR_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< No clock available for Timers Input capture */ + /** @brief Macro to configure the PLL2 clock source. * @note This function must be used only when all PLL2 is disabled. * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rng.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rng.h index 798995177..8837fb6fd 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rng.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rng.h @@ -178,6 +178,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ /** * @} */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rtc_ex.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rtc_ex.h index e4ff1c700..1a5249957 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rtc_ex.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_rtc_ex.h @@ -1736,6 +1736,17 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(const RTC_HandleTypeDef *hrtc, RTC_ */ #endif /* TAMP_PRIVCFGR_TAMPPRIV */ +#if defined (RTC_OR_OUT2_RMP) +/** @defgroup RTCEx_Exported_Functions_Group9 Extended RTC Backup register functions + * @{ + */ +void HAL_RTCEx_EnableRemapRtcOut2(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_DisableRemapRtcOut2(RTC_HandleTypeDef *hrtc); +/** + * @} + */ +#endif /* defined (RTC_OR_OUT2_RMP) */ + /** * @} */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_spi.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_spi.h index 15bf52d9f..e1332b18c 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_spi.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_spi.h @@ -1091,6 +1091,9 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ ((LENGTH) == SPI_CRC_LENGTH_4BIT)) + +#define IS_SPI_LIMITED_TRANSFER_SIZE(SIZE) (((SIZE) < 0x3FFU) && ((SIZE) != 0U)) + /** * @brief CRC Length for limited instance */ @@ -1100,6 +1103,8 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) +#define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL) + #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ @@ -1113,6 +1118,8 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); #define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) + +#define IS_SPI_TRANSFER_SIZE(SIZE) (((SIZE) < 0xFFFFU) && ((SIZE) != 0U)) /** * @} */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_spi_ex.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_spi_ex.h index b840f05ee..72a3a6903 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_spi_ex.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_spi_ex.h @@ -76,6 +76,10 @@ HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour); +#if defined(SPI_CFG1_DRDS) +HAL_StatusTypeDef HAL_SPIEx_EnableDelayReadDataSampling(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_DisableDelayReadDataSampling(SPI_HandleTypeDef *hspi); +#endif /* SPI_CFG1_DRDS */ /** * @} */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_wwdg.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_wwdg.h index 3ed2304e3..6504dee46 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_wwdg.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_wwdg.h @@ -191,7 +191,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__ WWDG handle + * @param __HANDLE__: WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_xspi.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_xspi.h index 3bb5f1556..9231b0784 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_xspi.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_hal_xspi.h @@ -341,38 +341,38 @@ typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi); /** @defgroup XSPI_MemorySize XSPI Memory Size * @{ */ -#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Byte = 2^( 0+1)) */ -#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Byte = 2^( 1+1)) */ -#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Byte = 2^( 2+1)) */ -#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Byte = 2^( 3+1)) */ -#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Byte = 2^( 4+1)) */ -#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Byte = 2^( 5+1)) */ -#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Byte = 2^( 6+1)) */ -#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Byte = 2^( 7+1)) */ -#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Byte = 2^( 8+1)) */ -#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KByte = 2^( 9+1)) */ -#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KByte = 2^(10+1)) */ -#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KByte = 2^(11+1)) */ -#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KByte = 2^(12+1)) */ -#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KByte = 2^(13+1)) */ -#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KByte = 2^(14+1)) */ -#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KByte = 2^(15+1)) */ -#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KByte = 2^(16+1)) */ -#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KByte = 2^(17+1)) */ -#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KByte = 2^(18+1)) */ -#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MByte = 2^(19+1)) */ -#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MByte = 2^(20+1)) */ -#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MByte = 2^(21+1)) */ -#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MByte = 2^(22+1)) */ -#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MByte = 2^(23+1)) */ -#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MByte = 2^(24+1)) */ -#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MByte = 2^(25+1)) */ -#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MByte = 2^(26+1)) */ -#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MByte = 2^(27+1)) */ -#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (256 MByte = 2^(28+1)) */ -#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits (256 MByte = 2^(29+1)) */ -#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits (256 MByte = 2^(30+1)) */ -#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits (256 MByte = 2^(31+1)) */ +#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Bytes = 2^( 0+1)) */ +#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Bytes = 2^( 1+1)) */ +#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Bytes = 2^( 2+1)) */ +#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Bytes = 2^( 3+1)) */ +#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Bytes = 2^( 4+1)) */ +#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Bytes = 2^( 5+1)) */ +#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Bytes = 2^( 6+1)) */ +#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Bytes = 2^( 7+1)) */ +#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Bytes = 2^( 8+1)) */ +#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KBytes = 2^( 9+1)) */ +#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KBytes = 2^(10+1)) */ +#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KBytes = 2^(11+1)) */ +#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KBytes = 2^(12+1)) */ +#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KBytes = 2^(13+1)) */ +#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KBytes = 2^(14+1)) */ +#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KBytes = 2^(15+1)) */ +#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KBytes = 2^(16+1)) */ +#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KBytes = 2^(17+1)) */ +#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KBytes = 2^(18+1)) */ +#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MBytes = 2^(19+1)) */ +#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MBytes = 2^(20+1)) */ +#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MBytes = 2^(21+1)) */ +#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MBytes = 2^(22+1)) */ +#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MBytes = 2^(23+1)) */ +#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MBytes = 2^(24+1)) */ +#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MBytes = 2^(25+1)) */ +#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MBytes = 2^(26+1)) */ +#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MBytes = 2^(27+1)) */ +#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (512 MBytes = 2^(28+1)) */ +#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits ( 1 GBytes = 2^(29+1)) */ +#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits ( 2 GBytes = 2^(30+1)) */ +#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits ( 4 GBytes = 2^(31+1)) */ /** * @} */ @@ -428,38 +428,38 @@ typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi); /** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary * @{ */ -#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ -#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Byte = 2^(1)) */ -#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Byte = 2^(2)) */ -#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Byte = 2^(3)) */ -#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Byte = 2^(4)) */ -#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Byte = 2^(5)) */ -#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Byte = 2^(6)) */ -#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Byte = 2^(7)) */ -#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Byte = 2^(8)) */ -#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Byte = 2^(9)) */ -#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KByte = 2^(10)) */ -#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KByte = 2^(11)) */ -#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KByte = 2^(12)) */ -#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KByte = 2^(13)) */ -#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KByte = 2^(14)) */ -#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KByte = 2^(15)) */ -#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KByte = 2^(16)) */ -#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KByte = 2^(17)) */ -#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KByte = 2^(18)) */ -#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KByte = 2^(19)) */ -#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MByte = 2^(20)) */ -#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MByte = 2^(21)) */ -#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MByte = 2^(22)) */ -#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MByte = 2^(23)) */ -#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MByte = 2^(24)) */ -#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MByte = 2^(25)) */ -#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MByte = 2^(26)) */ -#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MByte = 2^(27)) */ -#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MByte = 2^(28)) */ -#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MByte = 2^(29)) */ -#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GByte = 2^(30)) */ -#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GByte = 2^(31)) */ +#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ +#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Bytes = 2^(1)) */ +#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Bytes = 2^(2)) */ +#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Bytes = 2^(3)) */ +#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Bytes = 2^(4)) */ +#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Bytes = 2^(5)) */ +#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Bytes = 2^(6)) */ +#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Bytes = 2^(7)) */ +#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Bytes = 2^(8)) */ +#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Bytes = 2^(9)) */ +#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KBytes = 2^(10)) */ +#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KBytes = 2^(11)) */ +#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KBytes = 2^(12)) */ +#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KBytes = 2^(13)) */ +#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KBytes = 2^(14)) */ +#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KBytes = 2^(15)) */ +#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KBytes = 2^(16)) */ +#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KBytes = 2^(17)) */ +#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KBytes = 2^(18)) */ +#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KBytes = 2^(19)) */ +#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MBytes = 2^(20)) */ +#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MBytes = 2^(21)) */ +#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MBytes = 2^(22)) */ +#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MBytes = 2^(23)) */ +#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MBytes = 2^(24)) */ +#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MBytes = 2^(25)) */ +#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MBytes = 2^(26)) */ +#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MBytes = 2^(27)) */ +#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MBytes = 2^(28)) */ +#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MBytes = 2^(29)) */ +#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GBytes = 2^(30)) */ +#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GBytes = 2^(31)) */ /** * @} */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_bus.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_bus.h index 3973a6c56..f84959f49 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_bus.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_bus.h @@ -2236,7 +2236,6 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR USBEN LL_APB2_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 @@ -2325,7 +2324,6 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USB - * * (*) : Not available for all stm32h5xxxx family lines. * @retval None diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_cortex.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_cortex.h index 83282d744..ae3e9e84d 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_cortex.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_cortex.h @@ -103,14 +103,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control * @{ */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< MPU is disabled during HardFault and NMI handlers, - privileged software access to the default memory map is disabled */ -#define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< MPU is enabled during HardFault and NMI handlers, - privileged software access to the default memory map is disabled */ -#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< MPU is disabled during HardFault and NMI handlers, - privileged software access to the default memory map is enabled */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< MPU is enabled during HardFault and NMI handlers, - privileged software access to the default memory map is enabled */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -118,18 +114,24 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes * @{ */ -#define LL_MPU_DEVICE_nGnRnE 0x0U /*!< Device, noGather, noReorder, noEarly acknowledge. */ -#define LL_MPU_DEVICE_nGnRE 0x4U /*!< Device, noGather, noReorder, Early acknowledge. */ -#define LL_MPU_DEVICE_nGRE 0x8U /*!< Device, noGather, Reorder, Early acknowledge. */ -#define LL_MPU_DEVICE_GRE 0xCU /*!< Device, Gather, Reorder, Early acknowledge. */ +/* Device memory attributes */ +#define LL_MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define LL_MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ -#define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ +/* Normal memory attributes */ +/* Non-cacheable memory attribute */ #define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */ -#define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ +#define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ +/* - transient mode attribute */ #define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */ #define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */ - +/* - allocation attribute */ #define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */ #define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */ #define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */ @@ -150,9 +152,8 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access * @{ */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< MPU region execution permitted - if read permitted */ -#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< MPU region execution not permitted */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */ /** * @} */ @@ -160,9 +161,9 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable * @{ */ -#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< MPU region not shareable */ -#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< MPU region outer shareable */ -#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< MPU region inner shareable */ +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */ +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */ +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */ /** * @} */ @@ -170,10 +171,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes * @{ */ -#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< MPU region Read/write by privileged code only */ -#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< MPU region Read/write by any privilege level */ -#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< MPU region Read-only by privileged code only */ -#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< MPU region Read-only by any privilege level */ +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */ +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */ +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */ +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */ /** * @} */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_crs.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_crs.h index 8479714cb..4daf0368e 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_crs.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_crs.h @@ -107,9 +107,9 @@ extern "C" { /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source * @{ */ -#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ -#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** * @} */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_exti.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_exti.h index 5adeee312..e19224a37 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_exti.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_exti.h @@ -193,21 +193,6 @@ typedef struct #if defined(EXTI_IMR2_IM58) #define LL_EXTI_LINE_58 EXTI_IMR2_IM58 /*!< Extended line 58 */ #endif /* EXTI_IMR2_IM58 */ -#if defined(EXTI_IMR2_IM59) -#define LL_EXTI_LINE_59 EXTI_IMR2_IM59 /*!< Extended line 59 */ -#endif /* EXTI_IMR2_IM59 */ -#if defined(EXTI_IMR2_IM60) -#define LL_EXTI_LINE_60 EXTI_IMR2_IM60 /*!< Extended line 60 */ -#endif /* EXTI_IMR2_IM60 */ -#if defined(EXTI_IMR2_IM61) -#define LL_EXTI_LINE_61 EXTI_IMR2_IM61 /*!< Extended line 61 */ -#endif /* EXTI_IMR2_IM61 */ -#if defined(EXTI_IMR2_IM62) -#define LL_EXTI_LINE_62 EXTI_IMR2_IM62 /*!< Extended line 62 */ -#endif /* EXTI_IMR2_IM62 */ -#if defined(EXTI_IMR2_IM63) -#define LL_EXTI_LINE_63 EXTI_IMR2_IM63 /*!< Extended line 63 */ -#endif /* EXTI_IMR2_IM63 */ #define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< ALL Extended lines */ #define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ @@ -928,7 +913,6 @@ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * @note Please check each device line mapping for EXTI Line availability @@ -988,7 +972,6 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * @@ -1036,7 +1019,6 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 - * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * @@ -1211,6 +1193,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * + * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -1429,6 +1412,7 @@ __STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * + * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1478,6 +1462,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * + * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -1619,8 +1604,6 @@ __STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine) * @arg @ref LL_EXTI_EXTI_PORTG (*) * @arg @ref LL_EXTI_EXTI_PORTH * @arg @ref LL_EXTI_EXTI_PORTI (*) - * @arg @ref LL_EXTI_EXTI_PORTJ (*) - * @arg @ref LL_EXTI_EXTI_PORTK (*) * * (*) value not defined in all devices * @param Line This parameter can be one of the following values: @@ -1693,8 +1676,6 @@ __STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) * @arg @ref LL_EXTI_EXTI_PORTG (*) * @arg @ref LL_EXTI_EXTI_PORTH * @arg @ref LL_EXTI_EXTI_PORTI (*) - * @arg @ref LL_EXTI_EXTI_PORTJ (*) - * @arg @ref LL_EXTI_EXTI_PORTK (*) * * (*) value not defined in all devices */ @@ -2053,6 +2034,7 @@ __STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_56 * @arg @ref LL_EXTI_LINE_57 * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_63 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note Please check each device line mapping for EXTI Line availability * @retval None diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_gpio.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_gpio.h index a5c0c6020..72db31d69 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_gpio.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_gpio.h @@ -32,7 +32,7 @@ extern "C" { */ #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \ - defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + defined (GPIOG) || defined (GPIOH) || defined (GPIOI) /** @defgroup GPIO_LL GPIO * @{ @@ -1169,8 +1169,7 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); */ #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \ - defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || \ - defined (GPIOK) */ + defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */ /** * @} */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_pwr.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_pwr.h index 4c992b287..f2e046e83 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_pwr.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_pwr.h @@ -1567,13 +1567,13 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) } /** - * @brief Indicate whether the VDD voltage is below the threshold or not. + * @brief Indicate whether the VDDA voltage is below the threshold or not. * @rmtoll VMSR AVDO LL_PWR_IsActiveFlag_AVDO * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void) { - return ((READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == (PWR_VMSR_AVDO)) ? 1UL : 0UL); + return ((READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) == (PWR_VMSR_AVDO)) ? 1UL : 0UL); } /** diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_rcc.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_rcc.h index ee4a74ccc..75c5eebf1 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_rcc.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_rcc.h @@ -920,6 +920,8 @@ typedef struct #define LL_RCC_USB_CLKSOURCE_PLL1Q RCC_CCIPR4_USBSEL_0 /*!< PLL1 Q clock used as USB clock source */ #if defined(RCC_CR_PLL3ON) #define LL_RCC_USB_CLKSOURCE_PLL3Q RCC_CCIPR4_USBSEL_1 /*!< PLL3 Q clock used as USB clock source */ +#else +#define LL_RCC_USB_CLKSOURCE_PLL2Q RCC_CCIPR4_USBSEL_1 /*!< PLL2 Q clock used as USB clock source */ #endif /* PLL3 */ #define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CCIPR4_USBSEL /*!< HSI48 clock used as USB clock source */ /** @@ -2821,8 +2823,9 @@ __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**) * @retval None * - * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (*) : For stm32h56xxx, stm32h57xxx, stm32h5exxx and stm32h5fxxx family lines. * (**) : For stm32h503xx family line. + * (***) : For stm32h5exxx and stm32h5fxxx family lines. */ __STATIC_INLINE void LL_RCC_SetI3CClockSource(uint32_t I3CxSource) { @@ -3013,10 +3016,11 @@ __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) * @param USBxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_NONE * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2Q (*) * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q (*) * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 * - * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (*) : Available in some STM32H5 lines only. * @retval None */ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) @@ -3776,10 +3780,11 @@ __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_NONE * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2Q (*) * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q (*) * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 * - * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (*) : Available in some STM32H5 lines only. */ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) { diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_rtc.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_rtc.h index 5984bb4e9..c12adfe69 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_rtc.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_rtc.h @@ -3507,7 +3507,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(const RTC_TypeDef *RTCx, uint32 /** * @brief Enable backup register erase after internal tamper event detection * @rmtoll TAMP_CR3 ITAMP1NOER LL_RTC_TAMPER_ITAMP_EnableEraseBKP - * @rmtoll TAMP_CR3 ITAMP2NOER LL_RTC_TAMPER_ITAMP_EnableEraseBKP + * TAMP_CR3 ITAMP2NOER... LL_RTC_TAMPER_ITAMP_EnableEraseBKP * @param RTCx RTC Instance * @param InternalTamper This parameter can be a combination of the following values: * @arg @ref RTC_LL_EC_ITAMPER_NOERASE @@ -3523,7 +3523,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_EnableEraseBKP(const RTC_TypeDef *RTCx, /** * @brief Disable backup register erase after internal tamper event detection * @rmtoll TAMP_CR3 ITAMP1NOER LL_RTC_TAMPER_ITAMP_DisableEraseBKP - * @rmtoll TAMP_CR3 ITAMP2NOER LL_RTC_TAMPER_ITAMP_DisableEraseBKP + * TAMP_CR3 ITAMP2NOER... LL_RTC_TAMPER_ITAMP_DisableEraseBKP * @param RTCx RTC Instance * @param InternalTamper This parameter can be a combination of the following values: * @arg @ref RTC_LL_EC_ITAMPER_NOERASE @@ -6413,9 +6413,49 @@ __STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(const RTC_TypeDef *RTCx) return READ_REG(TAMP->COUNT1R); } +#if defined (RTC_OR_OUT2_RMP) /** - * @} + * @brief Enable RTC OUT2 remap feature. + * @rmtoll RTC_OR OUT2_RMP LL_RTC_EnableRemapRtcOut2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableRemapRtcOut2(const RTC_TypeDef *RTCx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(RTCx); + /* Enable RTC OUT2 remap */ + SET_BIT(RTC->OR, RTC_OR_OUT2_RMP); +} + +/** + * @brief Disable RTC OUT2 remap feature. + * @rmtoll RTC_OR OUT2_RMP LL_RTC_DisableRemapRtcOut2 + * @param RTCx RTC Instance + * @retval None */ +__STATIC_INLINE void LL_RTC_DisableRemapRtcOut2(const RTC_TypeDef *RTCx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(RTCx); + /* Disable RTC OUT2 remap */ + CLEAR_BIT(RTC->OR, RTC_OR_OUT2_RMP); +} + +/** + * @brief Check if RTC_OUT2 is mapped on PB2. + * @rmtoll RTC_OR OUT2_RMP IsEnabledRemapRtcOut2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledRemapRtcOut2(const RTC_TypeDef *RTCx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(RTCx); + /* Disable RTC OUT2 remap */ + return ((READ_BIT(RTC->OR, RTC_OR_OUT2_RMP) == (RTC_OR_OUT2_RMP)) ? 1U : 0U); +} +#endif /* defined (RTC_OR_OUT2_RMP) */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_spi.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_spi.h index 88b6e715e..ba71bac45 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_spi.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_spi.h @@ -3632,7 +3632,7 @@ __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) */ ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_ucpd.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_ucpd.h index 70f303803..72aae2579 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_ucpd.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_ucpd.h @@ -1468,10 +1468,10 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx) */ /** - * @brief Check if FRS interrupt + * @brief Check if FRS Event Flag is active * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx) { @@ -1482,7 +1482,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPD * @brief Check if type c event on CC2 * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) { @@ -1493,7 +1493,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * * @brief Check if type c event on CC1 * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) { @@ -1501,10 +1501,21 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * } /** - * @brief Check if Rx message end interrupt + * @brief Check if Rx error flag is active + * @rmtoll SR RXERR LL_UCPD_IsActiveFlag_RxErr + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXERR) == UCPD_SR_RXERR) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx message end flag is active * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx) { @@ -1512,10 +1523,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const } /** - * @brief Check if Rx overrun interrupt + * @brief Check if Rx overrun flag is active * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx) { @@ -1523,10 +1534,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UC } /** - * @brief Check if Rx hard reset interrupt + * @brief Check if Rx hard reset flag is active * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx) { @@ -1534,7 +1545,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const U } /** - * @brief Check if Rx orderset interrupt + * @brief Check if Rx orderset flag is active * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1545,7 +1556,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *con } /** - * @brief Check if Rx non empty interrupt + * @brief Check if Rx non empty flag is active * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1556,7 +1567,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCP } /** - * @brief Check if TX underrun interrupt + * @brief Check if TX underrun flag is active * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1567,7 +1578,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UC } /** - * @brief Check if hard reset sent interrupt + * @brief Check if hard reset sent flag is active * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1578,7 +1589,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *con } /** - * @brief Check if hard reset discard interrupt + * @brief Check if hard reset discard flag is active * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1589,7 +1600,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *con } /** - * @brief Check if Tx message abort interrupt + * @brief Check if Tx message abort flag is active * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1600,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const } /** - * @brief Check if Tx message sent interrupt + * @brief Check if Tx message sent flag is active * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1611,7 +1622,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *cons } /** - * @brief Check if Tx message discarded interrupt + * @brief Check if Tx message discarded flag is active * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1622,7 +1633,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *cons } /** - * @brief Check if Tx data receive interrupt + * @brief Check if Tx data interrupt flag is active * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_usb.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_usb.h index b310e7ee4..2b84d460a 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_usb.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_usb.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h5xx_hal_def.h" -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32H5xx_HAL_Driver * @{ */ @@ -41,6 +41,10 @@ extern "C" { #define HAL_USB_TIMEOUT 0xF000000U #endif /* define HAL_USB_TIMEOUT */ +#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS +#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U +#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */ + /** * @brief USB Mode definition */ @@ -48,7 +52,8 @@ extern "C" { typedef enum { USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1 + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 } USB_ModeTypeDef; /** @@ -117,9 +122,16 @@ typedef struct uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) uint8_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ uint8_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ +#endif /* defined (USB_DRD_FS) */ } USB_CfgTypeDef; typedef struct @@ -133,13 +145,18 @@ typedef struct uint8_t is_stall; /*!< Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint8_t is_iso_incomplete; /*!< Endpoint isoc condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + uint8_t type; /*!< Endpoint type This parameter can be any value of @ref USB_LL_EP_Type */ uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - +#if defined (USB_DRD_FS) uint16_t pmaadress; /*!< PMA Address This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ @@ -151,7 +168,7 @@ typedef struct uint8_t doublebuffer; /*!< Double buffer enable This parameter can be 0 or 1 */ - +#endif /* defined (USB_DRD_FS) */ uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ @@ -162,29 +179,57 @@ typedef struct uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_size; /*!< requested transfer size */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ +#endif /* defined (USB_DRD_FS) */ } USB_EPTypeDef; typedef struct { uint8_t dev_addr; /*!< USB device address. This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ - +#if defined (USB_DRD_FS) uint8_t phy_ch_num; /*!< Host channel number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint8_t ep_num; /*!< Endpoint number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint8_t ch_dir; /*!< channel direction This parameter store the physical channel direction IN/OUT/BIDIR */ +#else + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#endif /* defined (USB_DRD_FS) */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint8_t speed; /*!< USB Host Channel speed. This parameter can be any value of @ref HCD_Device_Speed: (HCD_DEVICE_SPEED_xxx) */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ + uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ + uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ + uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + uint8_t hub_port_nbr; /*!< USB HUB port number */ uint8_t hub_addr; /*!< USB HUB address */ @@ -199,10 +244,14 @@ typedef struct uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - uint32_t xfer_len; /*!< Current transfer length. */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint32_t XferSize; /*!< OTG Channel transfer size. */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + uint32_t xfer_len; /*!< Current transfer length. */ +#if defined (USB_DRD_FS) uint32_t xfer_len_db; /*!< Current transfer length used in double buffer mode. */ - +#endif /* defined (USB_DRD_FS) */ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ @@ -211,9 +260,14 @@ typedef struct uint8_t toggle_out; /*!< OUT transfer current toggle flag This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ uint32_t ErrCnt; /*!< Host channel error count. */ +#if defined (USB_DRD_FS) uint16_t pmaadress; /*!< PMA Address This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ @@ -225,6 +279,7 @@ typedef struct uint8_t doublebuffer; /*!< Double buffer enable This parameter can be 0 or 1 */ +#endif /* defined (USB_DRD_FS) */ USB_URBStateTypeDef urb_state; /*!< URB state. This parameter can be any value of @ref USB_URBStateTypeDef */ @@ -233,18 +288,113 @@ typedef struct This parameter can be any value of @ref USB_HCStateTypeDef */ } USB_HCTypeDef; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; +typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; +typedef USB_EPTypeDef USB_OTG_EPTypeDef; +typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; +typedef USB_HCTypeDef USB_OTG_HCTypeDef; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) typedef USB_ModeTypeDef USB_DRD_ModeTypeDef; typedef USB_CfgTypeDef USB_DRD_CfgTypeDef; typedef USB_EPTypeDef USB_DRD_EPTypeDef; typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef; typedef USB_HCStateTypeDef USB_DRD_HCStateTypeDef; typedef USB_HCTypeDef USB_DRD_HCTypeDef; +#endif /* defined (USB_DRD_FS) */ /* Exported constants --------------------------------------------------------*/ /** @defgroup PCD_Exported_Constants PCD Exported Constants * @{ */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_OTG_CORE VERSION ID + * @{ + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +/** + * @} + */ + +/** @defgroup USB_Core_Mode_ USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U +/** + * @} + */ + +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +#define USB_OTG_SPEED_FULL 3U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY + * @{ + */ +#define USB_OTG_EMBEDDED_PHY 2U +#define USB_OTG_HS_EMBEDDED_PHY 3U +/** + * @} + */ + +/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_HS_TRDT_VALUE +#define USBD_HS_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +/** + * @} + */ + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ @@ -292,12 +442,105 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; /** @defgroup USB_LL Device Speed * @{ */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U #define USBD_FS_SPEED 2U #define USBH_FSLS_SPEED 1U /** * @} */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ + +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U +/** + * @} + */ + +/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines + * @{ + */ +#define HFIR_6_MHZ 6000U +#define HFIR_60_MHZ 60000U +#define HFIR_48_MHZ 48000U +/** + * @} + */ + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU + +#define HC_MAX_PKT_CNT 256U +#define ISO_SPLT_MPS 188U + +#define HCSPLT_BEGIN 1U +#define HCSPLT_MIDDLE 2U +#define HCSPLT_END 3U +#define HCSPLT_FULL 4U + +#define TEST_J 1U +#define TEST_K 2U +#define TEST_SE0_NAK 3U +#define TEST_PACKET 4U +#define TEST_FORCE_EN 5U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ + + USB_OTG_HOST_CHANNEL_BASE\ + + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) + + +#define EP_ADDR_MSK 0xFU +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) #define EP_ADDR_MSK 0x7U #ifndef USE_USB_DOUBLE_BUFFER @@ -692,7 +935,7 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; } \ else if ((wCount) <= 62U) \ { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ @@ -824,12 +1067,22 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; */ #define USB_DRD_GET_CHEP_DBUF0_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_TX_CNT((USBx), (bEpChNum))) #define USB_DRD_GET_CHEP_DBUF1_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_RX_CNT((USBx), (bEpChNum))) - +#endif /* defined (USB_DRD_FS) */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) + +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** * @} */ @@ -838,8 +1091,65 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; /** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma); + +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); + +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, + USB_OTG_HCTypeDef *hc, uint8_t dma); + +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - +#if defined (USB_DRD_FS) HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx); @@ -885,7 +1195,7 @@ void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); - +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -901,7 +1211,7 @@ void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_utils.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_utils.h index 86bcdd01a..039106930 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_utils.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_ll_utils.h @@ -186,25 +186,25 @@ typedef struct /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE * @{ */ -#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ -#define LL_UTILS_PACKAGETYPE_VFQFPN68 0x00000001U /*!< VFQFPN68 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA176 0x00000003U /*!< UFBGA176+25 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000006U /*!< UFBGA169 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP176 0x00000007U /*!< LQFP176 package type */ -#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000009U /*!< UFQFPN32 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000BU /*!< UFBGA176+25 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x0000000DU /*!< LQFP176 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000EU /*!< UFBGA169 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP25 0x0000000FU /*!< WLCSP25 package type */ -#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x00000010U /*!< UFQFPN48 package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP39 0x00000011U /*!< WLCSP39 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA100 0x00000014U /*!< UFBGA100 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA144 0x00000015U /*!< UFBGA144 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_VFQFPN68 0x00000001U /*!< VFQFPN68 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176 0x00000003U /*!< UFBGA176+25 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000006U /*!< UFBGA169 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176 0x00000007U /*!< LQFP176 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000009U /*!< UFQFPN32 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000BU /*!< UFBGA176+25 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x0000000DU /*!< LQFP176 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000EU /*!< UFBGA169 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP25 0x0000000FU /*!< WLCSP25 package type */ +#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x00000010U /*!< UFQFPN48 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP39 0x00000011U /*!< WLCSP39 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA100 0x00000014U /*!< UFBGA100 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144 0x00000015U /*!< UFBGA144 package type */ /** * @} */ diff --git a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_util_i3c.h b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_util_i3c.h index 2cd97d7ff..146828c24 100644 --- a/stm32cube/stm32h5xx/drivers/include/stm32h5xx_util_i3c.h +++ b/stm32cube/stm32h5xx/drivers/include/stm32h5xx_util_i3c.h @@ -33,7 +33,8 @@ extern "C" { #include "stm32h5xx_ll_i3c.h" #endif /* USE_FULL_LL_DRIVER */ -/** @addtogroup STM32H5xx_UTIL_Driver +#if (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER) +/** @addtogroup STM32H7RSxx_UTIL_Driver * @{ */ @@ -128,6 +129,7 @@ ErrorStatus I3C_TgtTimingComputation(const I3C_TgtTimingTypeDef *pInputTiming, * @} */ +#endif /* (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER) */ #ifdef __cplusplus } #endif diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal.c index 42780e8e8..f7e50f788 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal.c @@ -48,10 +48,10 @@ /* Private typedef ---------------------------------------------------------------------------------------------------*/ /* Private define ----------------------------------------------------------------------------------------------------*/ /** - * @brief STM32H5xx HAL Driver version number 1.3.0 + * @brief STM32H5xx HAL Driver version number 1.4.0 */ #define __STM32H5XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32H5XX_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ +#define __STM32H5XX_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ #define __STM32H5XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32H5XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32H5XX_HAL_VERSION ((__STM32H5XX_HAL_VERSION_MAIN << 24U)\ diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_adc.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_adc.c index 1441e2755..c2e280c94 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_adc.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_adc.c @@ -2843,7 +2843,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_Chann /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { - if (pConfig->Channel == ADC_CHANNEL_0) + if ((pConfig->Channel == ADC_CHANNEL_0) + || ((pConfig->Channel == ADC_CHANNEL_1) && (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED))) { LL_ADC_EnableChannel0_GPIO(hadc->Instance); } diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_adc_ex.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_adc_ex.c index 9fb60dca3..16cd801f4 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_adc_ex.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_adc_ex.c @@ -1907,11 +1907,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, /* mode is disabled. */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { - if (pConfigInjected->InjectedChannel == ADC_CHANNEL_0) + if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_0) + || ((pConfigInjected->InjectedChannel == ADC_CHANNEL_1) + && (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)) + ) { LL_ADC_EnableChannel0_GPIO(hadc->Instance); } - /* If auto-injected mode is disabled: no constraint */ if (pConfigInjected->AutoInjectedConv == DISABLE) { diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_cortex.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_cortex.c index 624abb2b6..8d1b01e06 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_cortex.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_cortex.c @@ -74,19 +74,22 @@ (++) Reload Value should not exceed 0xFFFFFF [..] - *** How to configure MPU (secure and non secure) using CORTEX HAL driver *** - =========================================================== + *** How to configure MPU regions using CORTEX HAL driver *** + ============================================================ [..] - This section provides functions allowing to Enable and configure the MPU secure and non-secure. + This section provides functions allowing to configure the Memory Protection Unit (MPU). + (#) Disable the MPU using HAL_MPU_Disable(). + (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes(). + (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration link to + the right MPU attributes number. (#) Enable the MPU using HAL_MPU_Enable() function. - (#) Disable the MPU using HAL_MPU_Disable() function. - (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU. - (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU. - (#) Configure the MPU region using HAL_MPU_ConfigRegion() - and HAL_MPU_ConfigRegion_NS() to address the non secure MPU. - (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes() - and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU. + + -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter the memory + management fault handler MemManage_Handler() when an illegal memory access is performed. + -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region configuration + from affecting the new MPU configuration. + -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the secure context @endverbatim ****************************************************************************** diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_cryp.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_cryp.c index 179643cf8..699767974 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_cryp.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_cryp.c @@ -363,6 +363,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma); static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize); static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp); static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); @@ -635,6 +636,13 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size, data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode); @@ -649,10 +657,23 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD { /* Disable AES to change key mode */ __HAL_CRYP_DISABLE(hcryp); + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set key mode selection (Normal, Wrapped or Shared key )*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | \ AES_CR_KEYSEL | AES_CR_KEYPROT | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | \ @@ -1206,7 +1227,11 @@ HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_Contex hcryp->Init.KeyMode = pcont->KeyMode; hcryp->Phase = pcont->Phase; hcryp->KeyIVConfig = pcont->KeyIVConfig; - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } /* Restore CRYP CR register content */ WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg)); @@ -1379,11 +1404,25 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); } else { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode and normal key selection */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_ENCRYPT | CRYP_KEYMODE_NORMAL); } @@ -1474,10 +1513,22 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, { hcryp->Size = Size; } - - /* Set Decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + if (IS_AES_ALL_INSTANCE(hcryp->Instance)) + { + /* Set Decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_DECRYPT | CRYP_KEYMODE_NORMAL); + } /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; @@ -1584,7 +1635,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1687,7 +1744,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -1772,7 +1835,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1934,7 +2003,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -3573,7 +3648,31 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @brief Writes Key in Key registers. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -3647,7 +3746,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -5998,7 +6096,7 @@ static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *In static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; - uint32_t count = 0U; + uint32_t count; /* In case of GCM payload phase encryption, check that suspension can be carried out */ if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_cryp_ex.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_cryp_ex.c index 3637c0226..d6a95d996 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_cryp_ex.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_cryp_ex.c @@ -39,7 +39,7 @@ /** @addtogroup CRYPEx_Private_Defines * @{ */ - +#define CRYPEx_GENERAL_TIMEOUT 82U #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ #define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ #define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ @@ -66,6 +66,7 @@ /* Private function prototypes -----------------------------------------------*/ static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef CRYPEx_KeyGeneration(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); /* Exported functions---------------------------------------------------------*/ /** @addtogroup CRYPEx_Exported_Functions @@ -126,6 +127,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c /* Check if initialization phase has already been performed */ if (hcryp->Phase == CRYPEx_PHASE_PROCESS) { + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Change the CRYP phase */ hcryp->Phase = CRYPEx_PHASE_FINAL; @@ -144,19 +152,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -504,7 +509,13 @@ HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Encryption operating mode(Mode 0)*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -568,7 +579,13 @@ HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Decryption operating mode(Mode 3)*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -809,6 +826,31 @@ static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t T __HAL_UNLOCK(hcryp); return HAL_OK; } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ + +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @brief Key Generation * @param hcryp pointer to a CRYP_HandleTypeDef structure diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_dac.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_dac.c index 79388cd6b..f1f294089 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_dac.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_dac.c @@ -1250,6 +1250,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } + else + { + /* In case of mode normal and buffer disabled, connection to both on chip periph and external pin is not possible */ + if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_DISABLE) + { + assert_param(sConfig->DAC_ConnectOnChipPeripheral != DAC_CHIPCONNECT_BOTH); + } + } assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat)); diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_dac_ex.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_dac_ex.c index 8ba7fbfc7..9d541efef 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_dac_ex.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_dac_ex.c @@ -749,8 +749,8 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Init trimming counter */ /* Medium value */ - trimmingvalue = 16UL; - delta = 8UL; + trimmingvalue = 0x10UL; + delta = 0x08UL; while (delta != 0UL) { /* Set candidate trimming */ @@ -796,8 +796,12 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { - /* Trimming is actually one value more */ - trimmingvalue++; + /* Check trimming value below maximum */ + if (trimmingvalue < 0x1FU) + { + /* Trimming is actually one value more */ + trimmingvalue++; + } /* Set right trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); } @@ -870,8 +874,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval Trimming value : range: 0->31 - * + * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel) { diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_dma_ex.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_dma_ex.c index 21d339b5b..27d2c19b6 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_dma_ex.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_dma_ex.c @@ -1091,10 +1091,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNod assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); } /* Check DMA channel security and privilege attributes parameters */ @@ -3903,8 +3899,19 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO); } /********************************************************************************* CBR2 register value is updated */ - } + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_2D_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + else + { + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_LINEAR_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } /* Update node information value ************************************************************************************/ /* Set node information */ diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_eth.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_eth.c index 204b3dc10..cf15474ad 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_eth.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_eth.c @@ -1074,7 +1074,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) heth->RxDescList.RxDataLength = 0; } - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + /* Get the Frame Length of the received packet */ bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; /* Check if last descriptor */ @@ -1218,7 +1218,7 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) if (heth->RxDescList.RxBuildDescCnt != desccount) { /* Set the tail pointer index */ - tailidx = (descidx + 1U) % ETH_RX_DESC_CNT; + tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT; /* DMB instruction to avoid race condition */ __DMB(); @@ -1438,7 +1438,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) #ifdef HAL_ETH_USE_PTP /* Disable Ptp transmission */ - CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U)); + CLEAR_BIT(heth->Init.TxDesc[idx].DESC2, ETH_DMATXNDESCRF_TTSE); if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD) && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS)) @@ -1515,6 +1515,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT return HAL_ERROR; } + /* Mask the Timestamp Trigger interrupt */ + CLEAR_BIT(heth->Instance->MACIER, ETH_MACIER_TSIE); + tmpTSCR = ptpconfig->Timestamp | ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) | ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) | @@ -1548,8 +1551,11 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT } } - /* Ptp Init */ - SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); + /* Enable Update mode */ + if (ptpconfig->TimestampUpdateMode == ENABLE) + { + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT); + } /* Set PTP Configuration done */ heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED; @@ -1561,6 +1567,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT HAL_ETH_PTP_SetTime(heth, &time); + /* Ptp Init */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); + /* Return function status */ return HAL_OK; } @@ -1978,7 +1987,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) if ((mac_flag & ETH_MAC_LPI_IT) != 0U) { /* Get MAC LPI interrupt source and clear the status register pending bit */ - heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU); + heth->MACLPIEvent = READ_BIT(heth->Instance->MACLCSR, 0x0000000FU); #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /* Call registered EEE callback*/ @@ -2462,7 +2471,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_ ((uint32_t)pFilterConfig->HashMulticast << 2) | ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | ((uint32_t)pFilterConfig->PassAllMulticast << 4) | - ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | + ((uint32_t)((pFilterConfig->BroadcastFilter == ENABLE) ? 1U : 0U) << 5) | ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | @@ -2495,7 +2504,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_ pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE; - pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE; + pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) > 0U) ? ENABLE : DISABLE; pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF); pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; @@ -3027,7 +3036,7 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @param pTxConfig: Tx packet configuration - * @param ItMode: Enable or disable Tx EOT interrept + * @param ItMode: Enable or disable Tx EOT interrupt * @retval Status */ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_fdcan.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_fdcan.c index 68c573d40..99c1543a8 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_fdcan.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_fdcan.c @@ -1309,7 +1309,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA if (sFilterConfig->IdType == FDCAN_STANDARD_ID) { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.StdFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU)); assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType)); @@ -1329,7 +1329,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.ExtFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU)); assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType)); diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_flash.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_flash.c index ae7425ca0..363a539ae 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_flash.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_flash.c @@ -124,6 +124,9 @@ static void FLASH_Program_QuadWord(uint32_t FlashAddress, uint32_t Data static void FLASH_Program_QuadWord_OBK(uint32_t FlashAddress, uint32_t DataAddress); #endif /* FLASH_SR_OBKERR */ static void FLASH_Program_HalfWord(uint32_t FlashAddress, uint32_t DataAddress); +#if defined(FLASH_EDATAR_EDATA_EN) +static void FLASH_Program_Word(uint32_t FlashAddress, uint32_t DataAddress); +#endif /* FLASH_EDATAR_EDATA_EN */ /** * @} @@ -170,9 +173,6 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - /* Process Locked */ - __HAL_LOCK(&pFlash); - /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; @@ -218,6 +218,14 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, /* Program a Flash high-cycle data half-word at a specified address */ FLASH_Program_HalfWord(FlashAddress, DataAddress); } + else if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_WORD_EDATA) + { + /* Check the parameters */ + assert_param(IS_FLASH_EDATA_ADDRESS(FlashAddress)); + + /* Program a Flash high-cycle data half-word at a specified address */ + FLASH_Program_Word(FlashAddress, DataAddress); + } #endif /* FLASH_EDATAR_EDATA_EN */ else { @@ -246,9 +254,6 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, CLEAR_BIT((*reg_cr), (TypeProgram & ~(FLASH_NON_SECURE_MASK | FLASH_OTP))); #endif /* FLASH_SR_OBKERR */ } - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - /* return status */ return status; } @@ -271,9 +276,6 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - /* Process Locked */ - __HAL_LOCK(&pFlash); - /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; @@ -336,6 +338,14 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre /* Program a Flash high-cycle data half-word at a specified address */ FLASH_Program_HalfWord(FlashAddress, DataAddress); } + else if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_WORD_EDATA) + { + /* Check the parameters */ + assert_param(IS_FLASH_EDATA_ADDRESS(FlashAddress)); + + /* Program a Flash high-cycle data word at a specified address */ + FLASH_Program_Word(FlashAddress, DataAddress); + } #endif /* FLASH_EDATAR_EDATA_EN */ else { @@ -483,8 +493,6 @@ void HAL_FLASH_IRQHandler(void) (*reg_cr) &= ~(FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | \ FLASH_IT_STRBERR | FLASH_IT_INCERR | FLASH_IT_OPTCHANGEERR); #endif /* FLASH_SR_OBKERR */ - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); } } @@ -916,6 +924,31 @@ static void FLASH_Program_HalfWord(uint32_t FlashAddress, uint32_t DataAddress) *(__IO uint16_t *)FlashAddress = *(__IO uint16_t *)DataAddress; } +#if defined(FLASH_EDATAR_EDATA_EN) +/** + * @brief Program a word (32-bit) at a specified address. + * @param FlashAddress specifies the address to be programmed. + * @param DataAddress specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_Word(uint32_t FlashAddress, uint32_t DataAddress) +{ + __IO uint32_t *reg_cr; + + /* Access to SECCR or NSCR registers depends on operation type */ +#if defined (FLASH_OPTSR2_TZEN) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); +#else + reg_cr = &(FLASH_NS->NSCR); +#endif /* FLASH_OPTSR2_TZEN */ + + /* Set PG bit */ + SET_BIT((*reg_cr), FLASH_CR_PG); + + *(__IO uint32_t *)FlashAddress = *(__IO uint32_t *)DataAddress; +} +#endif /* FLASH_EDATAR_EDATA_EN */ + /** * @} */ diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_flash_ex.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_flash_ex.c index 2d83c5411..db13a5322 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_flash_ex.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_flash_ex.c @@ -261,9 +261,6 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - /* Process Locked */ - __HAL_LOCK(&pFlash); - /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; @@ -272,8 +269,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) if (status != HAL_OK) { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); + return status; } else { @@ -597,6 +593,38 @@ HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap(uint32_t SwapOffset) return status; } +/** + * @brief Swap the FLASH Option Bytes Keys (OBK) with interrupt enabled + * @param SwapOffset Specifies the number of keys to be swapped. + * This parameter can be a value between 0 (no OBK data swapped) and 511 (all OBK data swapped). + * Typical value are available in @ref FLASH_OBK_SWAP_Offset + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap_IT(uint32_t SwapOffset) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_obkcfgr; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Access to SECOBKCFGR or NSOBKCFGR registers depends on operation type */ + reg_obkcfgr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECOBKCFGR) : &(FLASH_NS->NSOBKCFGR); + + /* Enable End of Operation and Error interrupts */ + (*reg_obkcfgr) |= (FLASH_IT_EOP | FLASH_IT_WRPERR | FLASH_IT_PGSERR | FLASH_IT_STRBERR | FLASH_IT_INCERR); + + /* Set OBK swap offset */ + MODIFY_REG((*reg_obkcfgr), FLASH_OBKCFGR_SWAP_OFFSET, (SwapOffset << FLASH_OBKCFGR_SWAP_OFFSET_Pos)); + + /* Set OBK swap request */ + SET_BIT((*reg_obkcfgr), FLASH_OBKCFGR_SWAP_SECT_REQ); + } + + return status; +} #endif /* FLASH_SR_OBKERR */ /** diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_fmac.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_fmac.c index 8709c6672..a336d765a 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_fmac.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_fmac.c @@ -1199,7 +1199,7 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti */ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check handle state is ready */ if (hfmac->State == HAL_FMAC_STATE_READY) @@ -1218,11 +1218,24 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { (*(hfmac->pInputSize)) = hfmac->InputCurrentSize; } + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL)) { (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize; } + if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA) + { + /* Disable the DMA stream managing FMAC input data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaIn); + } + + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA) && (status == HAL_OK)) + { + /* Disable the DMA stream managing FMAC output data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaOut); + } + /* Reset FMAC unit (internal pointers) */ if (FMAC_Reset(hfmac) == HAL_ERROR) { @@ -1235,8 +1248,6 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { /* Reset the data pointers */ FMAC_ResetDataPointers(hfmac); - - status = HAL_OK; } /* Reset the busy flag */ diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_gtzc.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_gtzc.c index 26ccc25b5..13482f839 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_gtzc.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_gtzc.c @@ -599,7 +599,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddres * (Parameter already checked) */ size = GTZC_TZSC_MPCWM3_MEM_SIZE; - register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR); + register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3BR); break; #endif /* (FMC_SDRAM_BANK_1) */ #if defined(BKPSRAM_BASE) @@ -617,7 +617,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddres * (Parameter already checked) */ size = GTZC_TZSC_MPCWM4_SDRAM_MEM_SIZE ; - register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR); + register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4BR); break; #endif /* (FMC_SDRAM_BANK_2) */ default: @@ -697,7 +697,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAdd #endif /* defined(FMC_BANK3) */ #if defined(FMC_SDRAM_BANK_1) case FMC_SDRAM_BANK_1: - register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR); + register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3BR); break; #endif /* (FMC_SDRAM_BANK_1) */ #if defined(BKPSRAM_BASE) @@ -707,7 +707,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAdd #endif /* (BKPSRAM_BASE) */ #if defined(FMC_SDRAM_BANK_2) case FMC_SDRAM_BANK_2: - register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR); + register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4BR); break; #endif /* (FMC_SDRAM_BANK_2) */ default: diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_hcd.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_hcd.c index ab74378f5..9d5019227 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_hcd.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_hcd.c @@ -35,29 +35,1953 @@ (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API: (##) Enable the HCD/USB Low Level interface clock using the following macros + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode) + (+++) __HAL_RCC_USB_CLK_ENABLE(); (##) Initialize the related GPIO clocks (##) Configure HCD pin-out (##) Configure HCD NVIC interrupt - (#)Associate the Upper USB Host stack to the HAL HCD Driver: - (##) hhcd.pData = phost; + (#)Associate the Upper USB Host stack to the HAL HCD Driver: + (##) hhcd.pData = phost; + + (#)Enable HCD transmission and reception: + (##) HAL_HCD_Start(); + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +#ifdef HAL_HCD_MODULE_ENABLED +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/** @defgroup HCD HCD + * @brief HCD HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup HCD_Private_Functions HCD Private Functions + * @{ + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd); +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) +{ +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ + + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); + +#if defined (USB_OTG_FS) + USBx = hhcd->Instance; +#endif /* defined (USB_OTG_FS) */ + + if (hhcd->State == HAL_HCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; + + if (hhcd->MspInitCallback == NULL) + { + hhcd->MspInitCallback = HAL_HCD_MspInit; + } + + /* Init the low level hardware */ + hhcd->MspInitCallback(hhcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_HCD_MspInit(hhcd); +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ + } + + hhcd->State = HAL_HCD_STATE_BUSY; + +#if defined (USB_OTG_FS) + /* Disable DMA mode for FS instance */ + if (USBx == USB_OTG_FS) + { + hhcd->Init.dma_enable = 0U; + } +#endif /* defined (USB_OTG_FS) */ + + /* Disable the Interrupts */ + __HAL_HCD_DISABLE(hhcd); + + /* Init the Core (common init.) */ + if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Force Host Mode */ + if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Init Host */ + if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK) + { + hhcd->State = HAL_HCD_STATE_ERROR; + return HAL_ERROR; + } + + hhcd->State = HAL_HCD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initialize a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number. + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed. + * This parameter can be one of these values: + * HCD_DEVICE_SPEED_HIGH: High speed mode, + * HCD_DEVICE_SPEED_FULL: Full speed mode, + * HCD_DEVICE_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type, + * EP_TYPE_ISOC: Isochronous type, + * EP_TYPE_BULK: Bulk type, + * EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size. + * This parameter can be a value from 0 to32K + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef status; + uint32_t HostCoreSpeed; + uint32_t HCcharMps = mps; + + __HAL_LOCK(hhcd); + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].dev_addr = dev_address; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].ep_type = ep_type; + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + + (void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num); + + if ((epnum & 0x80U) == 0x80U) + { + hhcd->hc[ch_num].ep_is_in = 1U; + } + else + { + hhcd->hc[ch_num].ep_is_in = 0U; + } + + HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); + + if (ep_type == EP_TYPE_ISOC) + { + /* FS device plugged to HS HUB */ + if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + if (HCcharMps > ISO_SPLT_MPS) + { + /* ISO Max Packet Size for Split mode */ + HCcharMps = ISO_SPLT_MPS; + } + } + } + + hhcd->hc[ch_num].speed = speed; + hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps; + + status = USB_HC_Init(hhcd->Instance, ch_num, epnum, + dev_address, speed, ep_type, (uint16_t)HCcharMps); + + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Halt a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Halt(hhcd->Instance, ch_num); + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief DeInitialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) +{ + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + hhcd->State = HAL_HCD_STATE_BUSY; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + if (hhcd->MspDeInitCallback == NULL) + { + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hhcd->MspDeInitCallback(hhcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_HCD_MspDeInit(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_DISABLE(hhcd); + + hhcd->State = HAL_HCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @brief HCD IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USB Host Data + Transfer + +@endverbatim + * @{ + */ + +/** + * @brief Submit a new URB for processing. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param direction Channel number. + * This parameter can be one of these values: + * 0 : Output / 1 : Input + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type/ + * EP_TYPE_ISOC: Isochronous type/ + * EP_TYPE_BULK: Bulk type/ + * EP_TYPE_INTR: Interrupt type/ + * @param token Endpoint Type. + * This parameter can be one of these values: + * 0: HC_PID_SETUP / 1: HC_PID_DATA1 + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). + * This parameter can be one of these values: + * 0 : do ping inactive / 1 : do ping active + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, + uint16_t length, + uint8_t do_ping) +{ + hhcd->hc[ch_num].ep_is_in = direction; + hhcd->hc[ch_num].ep_type = ep_type; + + if (token == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_SETUP; + hhcd->hc[ch_num].do_ping = do_ping; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + + /* Manage Data Toggle */ + switch (ep_type) + { + case EP_TYPE_CTRL: + if (token == 1U) /* send data */ + { + if (direction == 0U) + { + if (length == 0U) + { + /* For Status OUT stage, Length == 0U, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + } + + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].do_ssplit == 1U) + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + } + } + break; + + case EP_TYPE_BULK: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + + break; + case EP_TYPE_INTR: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_ISOC: + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + break; + + default: + break; + } + + hhcd->hc[ch_num].xfer_buff = pbuff; + hhcd->hc[ch_num].xfer_len = length; + hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].xfer_count = 0U; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].state = HC_IDLE; + + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable); +} + +/** + * @brief Handle HCD interrupt request. + * @param hhcd HCD handle + * @retval None + */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + uint32_t interrupt; + + /* Ensure that we are in device mode */ + if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) + { + /* Avoid spurious interrupt */ + if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) + { + return; + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); + } + + /* Handle Host Disconnect Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) + { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); + + if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) + { + /* Flush USB Fifo */ + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); + + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + /* Restore FS Clock */ + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } + + /* Handle Host Port Disconnect Interrupt */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else + HAL_HCD_Disconnect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + + /* Handle Host Port Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) + { + HCD_Port_IRQHandler(hhcd); + } + + /* Handle Host SOF Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback(hhcd); +#else + HAL_HCD_SOF_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Host channel Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) + { + interrupt = USB_HC_ReadInterrupt(hhcd->Instance); + for (i = 0U; i < hhcd->Init.Host_channels; i++) + { + if ((interrupt & (1UL << (i & 0xFU))) != 0U) + { + if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) + { + HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); + } + else + { + HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i); + } + } + } + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); + } + + /* Handle Rx Queue Level Interrupts */ + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) + { + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + HCD_RXQLVL_IRQHandler(hhcd); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + } +} + + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief Connection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Connect_Callback could be implemented in the user file + */ +} + +/** + * @brief Disconnection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Enabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Disabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Notify URB state change callback. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @param urb_state: + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ + * @retval None + */ +__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + UNUSED(chnum); + UNUSED(urb_state); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file + */ +} + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB HCD Callback + * To be used instead of the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = pCallback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = pCallback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = pCallback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = pCallback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = pCallback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Unregister an USB HCD Callback + * USB HCD callback is redirected to the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + /* Setup Legacy weak Callbacks */ + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Register USB HCD Host Channel Notify URB Change Callback + * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = pCallback; + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Unregister the USB HCD Host Channel Notify URB Change Callback + * USB HCD Host Channel Notify URB Change Callback is redirected + * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the HCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + /* Enable port power */ + (void)USB_DriveVbus(hhcd->Instance, 1U); + + /* Enable global interrupt */ + __HAL_HCD_ENABLE(hhcd); + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Stop the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + (void)USB_StopHost(hhcd->Instance); + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Reset the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) +{ + return (USB_ResetPort(hhcd->Instance)); +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the HCD handle state. + * @param hhcd HCD handle + * @retval HAL state + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd) +{ + return hhcd->State; +} + +/** + * @brief Return URB state for a channel. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval URB state. + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL + */ +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].urb_state; +} + + +/** + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval last transfer size in byte + */ +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].xfer_count; +} + +/** + * @brief Return the Host Channel state. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval Host channel state + * This parameter can be one of these values: + * HC_IDLE/ + * HC_XFRC/ + * HC_HALTED/ + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ + * HC_DATATGLERR + */ +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].state; +} + +/** + * @brief Return the current Host frame number. + * @param hhcd HCD handle + * @retval Current Host frame number + */ +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetCurrentFrame(hhcd->Instance)); +} + +/** + * @brief Return the Host enumeration speed. + * @param hhcd HCD handle + * @retval Enumeration speed + */ +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetHostSpeed(hhcd->Instance)); +} + +/** + * @brief Set host channel Hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param addr Hub address + * @param PortNbr Hub port number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr) +{ + uint32_t HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); + + /* LS/FS device plugged to HS HUB */ + if ((hhcd->hc[ch_num].speed != HCD_DEVICE_SPEED_HIGH) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + hhcd->hc[ch_num].do_ssplit = 1U; + + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) && (hhcd->hc[ch_num].ep_is_in != 0U)) + { + hhcd->hc[ch_num].toggle_in = 1U; + } + } + + hhcd->hc[ch_num].hub_addr = addr; + hhcd->hc[ch_num].hub_port_nbr = PortNbr; + + return HAL_OK; +} + + +/** + * @brief Clear host channel hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + hhcd->hc[ch_num].do_ssplit = 0U; + hhcd->hc[ch_num].do_csplit = 0U; + hhcd->hc[ch_num].hub_addr = 0U; + hhcd->hc[ch_num].hub_port_nbr = 0U; + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup HCD_Private_Functions + * @{ + */ +/** + * @brief Handle Host Channel IN interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR); + hhcd->hc[chnum].state = HC_BBLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else + { + /* ... */ + } + + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) + { + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) + { + /* Clear any pending ACK IT */ + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + if (hhcd->Init.dma_enable != 0U) + { + hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + } + + hhcd->hc[chnum].state = HC_XFRC; + hhcd->hc[chnum].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + } + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || + (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC)) + { + USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[chnum].urb_state = URB_DONE; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + /* ... */ + } + + if (hhcd->Init.dma_enable == 1U) + { + if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U) + { + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 1U; + hhcd->hc[chnum].state = HC_ACK; + + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + + if (hhcd->hc[chnum].state == HC_XFRC) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + } + else if (hhcd->hc[chnum].state == HC_STALL) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; + } + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + hhcd->hc[chnum].ep_ss_schedule = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_NYET) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + { + hhcd->hc[chnum].NyetErrCnt++; + if (hhcd->hc[chnum].NyetErrCnt > 2U) + { + hhcd->hc[chnum].NyetErrCnt = 0U; + hhcd->hc[chnum].do_csplit = 0U; + + if (hhcd->hc[chnum].ErrCnt < 3U) + { + hhcd->hc[chnum].ep_ss_schedule = 1U; + } + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Set Complete split and re-activate the channel */ + USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + else if (hhcd->hc[chnum].state == HC_BBLERR) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + if (hhcd->hc[chnum].state == HC_HALTED) + { + return; + } + } + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].state = HC_NYET; - (#)Enable HCD transmission and reception: - (##) HAL_HCD_Start(); + if (hhcd->hc[chnum].do_ssplit == 0U) + { + hhcd->hc[chnum].ErrCnt = 0U; + } - @endverbatim - ****************************************************************************** + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + hhcd->hc[chnum].ErrCnt = 0U; + + if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U)) + { + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + } + else + { + /* ... */ + } + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + __HAL_HCD_UNMASK_ACK_HC_INT(chnum); + } + + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + } + else + { + /* ... */ + } +} + +/** + * @brief Handle Host Channel OUT interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none */ +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + uint32_t num_packets; -/* Includes ------------------------------------------------------------------*/ -#include "stm32h5xx_hal.h" + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); -/** @addtogroup STM32H5xx_HAL_Driver - * @{ + if (hhcd->hc[chnum].do_ping == 1U) + { + hhcd->hc[chnum].do_ping = 0U; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + + if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U)) + { + if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC) + { + hhcd->hc[chnum].do_csplit = 1U; + } + + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + + /* reset error_count */ + hhcd->hc[chnum].ErrCnt = 0U; + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) + { + hhcd->hc[chnum].ErrCnt = 0U; + + /* transaction completed with NYET state, update do ping state */ + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + hhcd->hc[chnum].do_ping = 1U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + } + + if (hhcd->hc[chnum].do_csplit != 0U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + hhcd->hc[chnum].state = HC_XFRC; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + hhcd->hc[chnum].state = HC_NYET; + + if (hhcd->hc[chnum].do_ssplit == 0U) + { + hhcd->hc[chnum].do_ping = 1U; + } + + hhcd->hc[chnum].ErrCnt = 0U; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + + if (hhcd->hc[chnum].do_ping == 0U) + { + if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH) + { + hhcd->hc[chnum].do_ping = 1U; + } + } + + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) + { + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else + { + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) + { + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + + if (hhcd->hc[chnum].state == HC_XFRC) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || + (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)) + { + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[chnum].toggle_out ^= 1U; + } + + if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U)) + { + num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet; + + if ((num_packets & 1U) != 0U) + { + hhcd->hc[chnum].toggle_out ^= 1U; + } + } + } + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + } + else if (hhcd->hc[chnum].state == HC_NYET) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[chnum].state == HC_STALL) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; + } + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + else + { + return; + } + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + return; + } +} + +/** + * @brief Handle Rx Queue Level interrupt requests. + * @param hhcd HCD handle + * @retval none */ +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t pktsts; + uint32_t pktcnt; + uint32_t GrxstspReg; + uint32_t xferSizePktCnt; + uint32_t tmpreg; + uint32_t chnum; + + GrxstspReg = hhcd->Instance->GRXSTSP; + chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; + pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; + pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; + + switch (pktsts) + { + case GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer. */ + if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0)) + { + if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len) + { + (void)USB_ReadPacket(hhcd->Instance, + hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt); -#ifdef HAL_HCD_MODULE_ENABLED + /* manage multiple Xfer */ + hhcd->hc[chnum].xfer_buff += pktcnt; + hhcd->hc[chnum].xfer_count += pktcnt; + + /* get transfer size packet count */ + xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; + + if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U)) + { + /* re-activate the channel when more packets are expected */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[chnum].urb_state = URB_ERROR; + } + } + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + case GRXSTS_PKTSTS_CH_HALTED: + default: + break; + } +} + +/** + * @brief Handle Host Port interrupt requests. + * @param hhcd HCD handle + * @retval None + */ +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0; + __IO uint32_t hprt0_dup; + + /* Handle Host Port Interrupts */ + hprt0 = USBx_HPRT0; + hprt0_dup = USBx_HPRT0; + + hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Check whether Port Connect detected */ + if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) + { + if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->ConnectCallback(hhcd); +#else + HAL_HCD_Connect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + hprt0_dup |= USB_OTG_HPRT_PCDET; + } + + /* Check whether Port Enable Changed */ + if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) + { + hprt0_dup |= USB_OTG_HPRT_PENCHNG; + + if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) + { + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); + } + else + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } + } + else + { + if (hhcd->Init.speed == HCD_SPEED_FULL) + { + USBx_HOST->HFIR = HFIR_60_MHZ; + } + } +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortEnabledCallback(hhcd); +#else + HAL_HCD_PortEnabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + } + else + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortDisabledCallback(hhcd); +#else + HAL_HCD_PortDisabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + + /* Check for an overcurrent */ + if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) + { + hprt0_dup |= USB_OTG_HPRT_POCCHNG; + } + + /* Clear Port Interrupts */ + USBx_HPRT0 = hprt0_dup; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #if defined (USB_DRD_FS) /** @defgroup HCD HCD @@ -222,7 +2146,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, return HAL_ERROR; } - if (((epnum & 0xFU)== 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) + if (((epnum & 0xFU) == 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) { hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[0U].pmaadress; hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[0U].pmaaddr0; @@ -1510,6 +3434,7 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) * @param hhcd HCD handle * @retval speed : Device speed after Host enumeration * This parameter can be one of these values: + * @arg HCD_DEVICE_SPEED_HIGH: High speed mode * @arg HCD_DEVICE_SPEED_FULL: Full speed mode * @arg HCD_DEVICE_SPEED_LOW: Low speed mode */ @@ -1522,7 +3447,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) * @brief Set host channel Hub Information. * @param hhcd HCD handle * @param ch_num Channel number. - * This parameter can be a value from 1 to 8 + * This parameter can be a value from 1 to 15 * @param addr Hub address * @param PortNbr Hub port number * @retval HAL status @@ -1541,7 +3466,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, * @brief Clear host channel hub information. * @param hhcd HCD handle * @param ch_num Channel number. - * This parameter can be a value from 1 to 8 + * This parameter can be a value from 1 to 15 * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num) diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_i2c.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_i2c.c index f2314a626..5214c911e 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_i2c.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_i2c.c @@ -3424,6 +3424,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3481,37 +3483,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -7590,15 +7619,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_i2s.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_i2s.c index c5c92b8a5..cda2d90a2 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_i2s.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_i2s.c @@ -2004,6 +2004,107 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) return errorcode; } +/** + * @brief Enable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx. + * Original SDI pin becomes SDO and original SDO pin becomes SDI (Also applicable + * on half-duplex mode in case of single data line). + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state. + * @retval HAL_OK IO Swap feature enabled successfully. + */ +HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the global state */ + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_ERROR; + } + + /* Check for IOLock */ + if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) + { + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE) + { + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + } + + /* Enable IO Swap feature */ + SET_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP); + + return HAL_OK; +} + +/** + * @brief Disable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx. + * Original SDI pin becomes SDI and original SDO pin becomes SDO (Also applicable + * on half-duplex mode in case of single data line). + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state. + * @retval HAL_OK IO Swap feature disabled successfully. + */ +HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the global state */ + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_ERROR; + } + + /* Check for IOLock */ + if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) + { + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE) + { + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + } + + /* Disable the IO Swap feature */ + CLEAR_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP); + + return HAL_OK; +} + +/** + * @brief Retrieve the SDO/SDI alternate functions inversion feature status for the dedicated I2Sx. + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval 1 when I2S IO swap feature is enabled, 0 otherwise, or when hi2s pointer is null. + */ +uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return 0; + } + + return ((READ_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); +} + /** * @brief This function handles I2S interrupt request. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_i3c.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_i3c.c index 13dffa2fd..fe73e7c15 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_i3c.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_i3c.c @@ -127,7 +127,7 @@ The I3C_XferTypeDef structure contains different parameters about Control, Status buffer, and Transmit and Receive buffer. Use HAL_I3C_AddDescToFrame() function each time application add a descriptor in the frame before call - an IO operation interface + a Controller IO operation interface One element of the frame descriptor correspond to one frame to manage through IO operation. (#) To check if I3C target device is ready for communication, use the function HAL_I3C_Ctrl_IsDeviceI3C_Ready() @@ -1661,8 +1661,8 @@ void HAL_I3C_EV_IRQHandler(I3C_HandleTypeDef *hi3c) /* Derogation MISRAC2012-Rul All different characteristics must be fill through structure I3C_DeviceConfTypeDef. This function is called only when mode is Controller. - (+) Call the function HAL_I3C_AddDescToFrame() to prepare the full transfer usecase in a transfer descriptor - which contained different buffer pointers and their associated size through I3C_XferTypeDef. + (+) Call the function HAL_I3C_AddDescToFrame() to prepare the full transfer usecase in a Controller transfer + descriptor which contained different buffer pointers and their associated size through I3C_XferTypeDef. This function must be called before initiate any communication transfer. (+) Call the function HAL_I3C_Ctrl_SetConfigResetPattern() to configure the insertion of the reset pattern at the end of a Frame. @@ -2141,10 +2141,10 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_ConfigBusDevices(I3C_HandleTypeDef *hi3 } /** - * @brief Add Private or CCC descriptor in the user data transfer descriptor. - * @note This function must be called before initiate any communication transfer. This function help the preparation - * of the full transfer usecase in a transfer descriptor which contained different buffer pointers - * and their associated size through I3C_XferTypeDef. + * @brief Add Private or CCC descriptor in the user data transfer controller descriptor. + * @note This function must be called before initiate initiate any controller communication transfer. This function + * help the preparation of the full transfer usecase in a transfer descriptor which contained different buffer + * pointers and their associated size through I3C_XferTypeDef. * @note The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains * multiple transmission frames. * @param hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information @@ -5495,7 +5495,6 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_GenerateArbitration(I3C_HandleTypeDef *hi3c, uint * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers * information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data * to transmit in bytes (TxBuf.Size)). - * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @param timeout : [IN] Timeout duration in millisecond. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ @@ -5639,7 +5638,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers * information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data * to transmit in bytes (TxBuf.Size)). - * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) @@ -5738,7 +5736,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeD * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers * information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data * to transmit in bytes (TxBuf.Size)). - * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) @@ -5899,7 +5896,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferType * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers * information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data * to be received in bytes (RxBuf.Size)). - * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @param timeout : [IN] Timeout duration in millisecond. * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ @@ -6042,7 +6038,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef * * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers * information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data * to be received in bytes (RxBuf.Size)). - * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) @@ -6137,7 +6132,6 @@ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDe * @param pXferData : [IN] Pointer to an I3C_XferTypeDef structure that contains required reception buffers * information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data * to be received in bytes (RxBuf.Size)). - * This value contain transfer data after called @ref HAL_I3C_AddDescToFrame(). * @retval HAL Status : Value from HAL_StatusTypeDef enumeration. */ HAL_StatusTypeDef HAL_I3C_Tgt_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData) diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pcd.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pcd.c index 67bcd95c1..b1f98c349 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pcd.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pcd.c @@ -38,6 +38,8 @@ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: (##) Enable the PCD/USB Low Level interface clock using (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) (##) Initialize the related GPIO clocks (##) Configure PCD pin-out @@ -67,7 +69,7 @@ #ifdef HAL_PCD_MODULE_ENABLED -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -86,13 +88,19 @@ /** @defgroup PCD_Private_Functions PCD Private Functions * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); #if (USE_USB_DOUBLE_BUFFER == 1U) static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -123,6 +131,9 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ uint8_t i; /* Check the PCD handle allocation */ @@ -134,6 +145,10 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); +#if defined (USB_OTG_FS) + USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + if (hpcd->State == HAL_PCD_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -169,15 +184,40 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; +#if defined (USB_OTG_FS) + /* Disable DMA mode for FS instance */ + if (USBx == USB_OTG_FS) + { + hpcd->Init.dma_enable = 0U; + } +#endif /* defined (USB_OTG_FS) */ + /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); + /*Init the Core (common init.) */ + if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Force Device Mode */ + if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + /* Init endpoints structures */ for (i = 0U; i < hpcd->Init.dev_endpoints; i++) { /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; hpcd->IN_ep[i].num = i; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + hpcd->IN_ep[i].tx_fifo_num = i; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; hpcd->IN_ep[i].maxpacket = 0U; @@ -197,7 +237,11 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) } /* Init Device */ - (void)USB_DevInit(hpcd->Instance, hpcd->Init); + if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } hpcd->USB_Address = 0U; hpcd->State = HAL_PCD_STATE_READY; @@ -208,6 +252,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) (void)HAL_PCDEx_ActivateLPM(hpcd); } + (void)USB_DevDisconnect(hpcd->Instance); + return HAL_OK; } @@ -975,7 +1021,18 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + __HAL_LOCK(hpcd); +#if defined (USB_OTG_FS) + if (hpcd->Init.battery_charging_enable == 1U) + { + /* Enable USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } +#endif /* defined (USB_OTG_FS) */ __HAL_PCD_ENABLE(hpcd); (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); @@ -990,15 +1047,493 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); (void)USB_DevDisconnect(hpcd->Instance); + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_OTG_FS) + if (hpcd->Init.battery_charging_enable == 1U) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } +#endif /* defined (USB_OTG_FS) */ + __HAL_UNLOCK(hpcd); return HAL_OK; } +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t i; + uint32_t ep_intr; + uint32_t epint; + uint32_t epnum; + uint32_t fifoemptymsk; + uint32_t RegVal; + + /* ensure that we are in device mode */ + if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) + { + /* avoid spurious interrupt */ + if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) + { + return; + } + + /* store current frame number */ + hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) + { + /* incorrect mode, acknowledge the interrupt */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); + } + + /* Handle RxQLevel Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + { + USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + RegVal = USBx->GRXSTSP; + + ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; + + if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) + { + (void)USB_ReadPacket(USBx, ep->xfer_buff, + (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + } + } + else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + } + else + { + /* ... */ + } + + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + { + epnum = 0U; + + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) + { + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); + (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); + /* Class B setup phase done for previous decoded setup */ + (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); + } + + /* Clear OUT Endpoint disable interrupt */ + if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) + { + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; + } + + ep = &hpcd->OUT_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); + } + + /* Clear Status Phase Received interrupt */ + if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + + /* Clear OUT NAK interrupt */ + if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) + { + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); + + epnum = 0U; + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) /* In ITR */ + { + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); + + if (hpcd->Init.dma_enable == 1U) + { + hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; + + /* this is ZLP, so prepare EP0 for next setup */ + if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) + { + /* prepare to rx more setup packets */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); + } + if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); + } + if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); + } + if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + { + (void)USB_FlushTxFifo(USBx, epnum); + + ep = &hpcd->IN_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); + } + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) + { + (void)PCD_WriteEmptyTxFifo(hpcd, epnum); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + /* Handle Resume Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) + { + /* Clear the Remote Wake-up Signaling */ + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + + if (hpcd->LPM_State == LPM_L1) + { + hpcd->LPM_State = LPM_L0; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else + HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); + } + + /* Handle Suspend Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) + { + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); + } + + /* Handle LPM Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); + + if (hpcd->LPM_State == LPM_L0) + { + hpcd->LPM_State = LPM_L1; + hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Handle Reset Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) + { + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + } + USBx_DEVICE->DAINTMSK |= 0x10001U; + + if (hpcd->Init.use_dedicated_ep1 != 0U) + { + USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM; + + USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + else + { + USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM | + USB_OTG_DOEPMSK_OTEPSPRM | + USB_OTG_DOEPMSK_NAKM; + + USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + + /* Set Default Address to 0 */ + USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; + + /* setup EP0 to receive SETUP packets */ + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, + (uint8_t *)hpcd->Setup); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); + } + + /* Handle Enumeration done Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) + { + (void)USB_ActivateSetup(hpcd->Instance); + hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); + + /* Set USB Turnaround time */ + (void)USB_SetTurnaroundTime(hpcd->Instance, + HAL_RCC_GetHCLKFreq(), + (uint8_t)hpcd->Init.speed); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else + HAL_PCD_ResetCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); + } + + /* Handle SOF Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else + HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Global OUT NAK effective Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) + { + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) + { + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + } + } + } + + /* Handle Incomplete ISO IN Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_INEP(epnum)->DIEPCTL; + + if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) + { + hpcd->IN_ep[epnum].is_iso_incomplete = 1U; + + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); + } + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); + } + + /* Handle Incomplete ISO OUT Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_OUTEP(epnum)->DOEPCTL; + + if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && + ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + { + hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; + + USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + break; + } + } + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + /* Handle Connection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ConnectCallback(hpcd); +#else + HAL_PCD_ConnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); + } + /* Handle Disconnection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) + { + RegVal = hpcd->Instance->GOTGINT; + + if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DisconnectCallback(hpcd); +#else + HAL_PCD_DisconnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + hpcd->Instance->GOTGINT |= RegVal; + } + } +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) /** * @brief This function handles PCD interrupt request. * @param hpcd PCD handle @@ -1142,7 +1677,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) return; } } - +#endif /* defined (USB_DRD_FS) */ /** * @brief Data OUT stage callback. @@ -1342,7 +1877,20 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + __HAL_LOCK(hpcd); + +#if defined (USB_OTG_FS) + if (hpcd->Init.battery_charging_enable == 1U) + { + /* Enable USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } +#endif /* defined (USB_OTG_FS) */ + (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); @@ -1356,8 +1904,21 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) { +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + __HAL_LOCK(hpcd); (void)USB_DevDisconnect(hpcd->Instance); + +#if defined (USB_OTG_FS) + if (hpcd->Init.battery_charging_enable == 1U) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } +#endif /* defined (USB_OTG_FS) */ + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1407,6 +1968,14 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if (ep->is_in != 0U) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) { @@ -1470,7 +2039,16 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->is_in = 0U; ep->num = ep_addr & EP_ADDR_MSK; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); +#else (void)USB_EPStartXfer(hpcd->Instance, ep); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ return HAL_OK; } @@ -1502,13 +2080,24 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; +#if defined (USB_DRD_FS) ep->xfer_fill_db = 1U; ep->xfer_len_db = len; +#endif /* defined (USB_DRD_FS) */ ep->xfer_count = 0U; ep->is_in = 1U; ep->num = ep_addr & EP_ADDR_MSK; +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); +#else (void)USB_EPStartXfer(hpcd->Instance, ep); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ return HAL_OK; } @@ -1546,6 +2135,13 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) (void)USB_EPSetStall(hpcd->Instance, ep); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + } +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1686,6 +2282,35 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) return hpcd->State; } +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set the USB Device high speed test mode. + * @param hpcd PCD handle + * @param testmode USB Device high speed test mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode) +{ + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + + switch (testmode) + { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + case TEST_FORCE_EN: + USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; + break; + + default: + break; + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** * @} */ @@ -1698,8 +2323,215 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) /** @addtogroup PCD_Private_Functions * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Check FIFO for the next packet to be loaded. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t len; + uint32_t len32b; + uint32_t fifoemptymsk; + + ep = &hpcd->IN_ep[epnum]; + + if (ep->xfer_count > ep->xfer_len) + { + return HAL_ERROR; + } + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + len32b = (len + 3U) / 4U; + + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + len32b = (len + 3U) / 4U; + + (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, + (uint8_t)hpcd->Init.dma_enable); + + ep->xfer_buff += len; + ep->xfer_count += len; + } + + if (ep->xfer_len <= ep->xfer_count) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_EPTypeDef *ep; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if (hpcd->Init.dma_enable == 1U) + { + if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + } + else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + ep = &hpcd->OUT_ep[epnum]; + + /* out data packet received over EP */ + ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + + if (epnum == 0U) + { + if (ep->xfer_len == 0U) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + else + { + ep->xfer_buff += ep->xfer_count; + } + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { + /* ... */ + } + } + else + { + if (gSNPSiD == USB_OTG_CORE_ID_310A) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { + if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT setup packet received interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + + /* Inform the upper layer that a setup packet is available */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) + { + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) /** * @brief This function handles PCD Endpoint interrupt request. * @param hpcd PCD handle @@ -2225,12 +3057,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, return HAL_OK; } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - +#endif /* defined (USB_DRD_FS) */ /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ /** * @} diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pcd_ex.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pcd_ex.c index 8edff6121..48c89e721 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pcd_ex.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pcd_ex.c @@ -34,7 +34,7 @@ #ifdef HAL_PCD_MODULE_ENABLED -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -59,7 +59,306 @@ @endverbatim * @{ */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set Tx FIFO + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) +{ + uint8_t i; + uint32_t Tx_Offset; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + Tx_Offset = hpcd->Instance->GRXFSIZ; + + if (fifo == 0U) + { + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; + } + else + { + Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; + for (i = 0U; i < (fifo - 1U); i++) + { + Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; + } + + return HAL_OK; +} + +/** + * @brief Set Rx FIFO + * @param hpcd PCD handle + * @param size Size of Rx fifo + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) +{ + hpcd->Instance->GRXFSIZ = size; + + return HAL_OK; +} + +/** + * @brief Activate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 1U; + hpcd->LPM_State = LPM_L0; + USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + +/** + * @brief Deactivate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; + USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + +/** + * @brief Handle BatteryCharging Process. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t gccfg_msk; + uint32_t tickstart = HAL_GetTick(); + + /* Enable DCD : Data Contact Detect */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG |= USB_OTG_GCCFG_DCDETEN; + } +#endif /* defined (USB_OTG_HS) */ + + /* Wait for Min DCD Timeout */ + HAL_Delay(300U); + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + /* Check Detect flag */ + if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Primary detection: checks if connected to Standard Downstream Port + (without charging capability) */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN; + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG &= ~USB_OTG_GCCFG_DCDETEN; + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_PDETEN; + } +#endif /* defined (USB_OTG_HS) */ + HAL_Delay(50U); + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + gccfg_msk = USB_OTG_GCCFG_PDET; + } +#if defined (USB_OTG_HS) + else + { + gccfg_msk = USB_OTG_GCCFG_CHGDET; + } +#endif /* defined (USB_OTG_HS) */ + + if ((USBx->GCCFG & gccfg_msk) == 0U) + { + /* Case of Standard Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* start secondary detection to check connection to Charging Downstream + Port or Dedicated Charging Port */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + HAL_Delay(50U); + + gccfg_msk = USB_OTG_GCCFG_SDET; + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN); + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_SDETEN; + HAL_Delay(50U); + + gccfg_msk = USB_OTG_GCCFG_FSVPLUS; + } +#endif /* defined (USB_OTG_HS) */ + + if ((USBx->GCCFG & gccfg_msk) == gccfg_msk) + { + /* case Dedicated Charging Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* case Charging Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Battery Charging capability discovery finished */ + (void)HAL_PCDEx_DeActivateBCD(hpcd); + + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Activate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + + /* Power Down USB transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Enable Battery charging */ + USBx->GCCFG |= USB_OTG_GCCFG_BCDEN; + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDETEN); + } +#endif /* defined (USB_OTG_HS) */ + + hpcd->battery_charging_active = 1U; + + return HAL_OK; +} + +/** + * @brief Deactivate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + + /* Disable Battery charging */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDETEN); + } +#endif /* defined (USB_OTG_HS) */ + + hpcd->battery_charging_active = 0U; + + return HAL_OK; +} + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) /** * @brief Configure PMA for EP * @param hpcd Device instance @@ -276,7 +575,7 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) return HAL_OK; } - +#endif /* defined (USB_DRD_FS) */ /** * @brief Send LPM message to user layer callback. @@ -319,7 +618,7 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ /** diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pka.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pka.c index d13000162..19c742326 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pka.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pka.c @@ -276,6 +276,7 @@ * @{ */ #define PKA_RAM_SIZE 1334U +#define PKA_RAM_ERASE_TIMEOUT 1000U /* Private macro -------------------------------------------------------------*/ #define __PKA_RAM_PARAM_END(TAB,INDEX) do{ \ @@ -287,9 +288,6 @@ */ /* Private variables ---------------------------------------------------------*/ -static uint32_t primeordersize; -static uint32_t opsize; -static uint32_t modulussize; /* Private function prototypes -----------------------------------------------*/ /** @defgroup PKA_Private_Functions PKA Private Functions * @{ @@ -399,8 +397,22 @@ HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka) /* Set the state to busy */ hpka->State = HAL_PKA_STATE_BUSY; - /* Reset the control register and enable the PKA */ - hpka->Instance->CR = PKA_CR_EN; + /* Get current tick */ + tickstart = HAL_GetTick(); + + /* Reset the control register and enable the PKA (wait the end of PKA RAM erase) */ + while ((hpka->Instance->CR & PKA_CR_EN) != PKA_CR_EN) + { + hpka->Instance->CR = PKA_CR_EN; + + /* Check the Timeout */ + if ((HAL_GetTick() - tickstart) > PKA_RAM_ERASE_TIMEOUT) + { + /* Set timeout status */ + err = HAL_TIMEOUT; + break; + } + } /* Get current tick */ tickstart = HAL_GetTick(); @@ -502,12 +514,50 @@ __weak void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka) */ __weak void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpka); - - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, the HAL_PKA_MspDeInit can be implemented in the user file + user should take into consideration PKA RAM erase when resetting PKA */ + uint32_t tickstart = HAL_GetTick(); + + /* Enable PKA reset state */ + __HAL_RCC_PKA_FORCE_RESET(); + + /* Release PKA from reset state */ + __HAL_RCC_PKA_RELEASE_RESET(); + + /* Wait the INITOK flag Setting */ + while (hpka->Instance->CR != PKA_CR_EN) + { + hpka->Instance->CR = PKA_CR_EN; + + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > PKA_RAM_ERASE_TIMEOUT) + { + /* update the state */ + hpka->State = HAL_PKA_STATE_ERROR; + } + } + + /* Get current tick */ + tickstart = HAL_GetTick(); + + /* Wait the INITOK flag Setting */ + if (PKA_WaitOnFlagUntilTimeout(hpka, PKA_SR_INITOK, RESET, tickstart, PKA_RAM_ERASE_TIMEOUT) != HAL_OK) + { + /* update the state */ + hpka->State = HAL_PKA_STATE_ERROR; + } + + /* Reset any pending flag */ + SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + /* PKA Periph clock disable */ + hpka->Instance->CR = 0; + __HAL_RCC_PKA_CLK_DISABLE(); + + /* PKA Periph IRQ disable */ + HAL_NVIC_DisableIRQ(PKA_IRQn); } #if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) @@ -811,7 +861,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *i { /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); - opsize = in->OpSize; + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout); } @@ -826,7 +876,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef { /* Set input parameter in PKA RAM */ PKA_ModExp_Set(hpka, in); - opsize = in->OpSize; + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP); } @@ -842,7 +892,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFast { /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); - opsize = in->OpSize; + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout); } @@ -857,7 +907,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF { /* Set input parameter in PKA RAM */ PKA_ModExpFastMode_Set(hpka, in); - opsize = in->OpSize; + hpka->opsize = in->OpSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE); } @@ -875,7 +925,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpP { /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); - opsize = in->OpSize; + hpka->opsize = in->OpSize; return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout); } @@ -890,7 +940,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModE { /* Set input parameter in PKA RAM */ PKA_ModExpProtectMode_Set(hpka, in); - opsize = in->OpSize; + hpka->opsize = in->OpSize; return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT); } @@ -906,7 +956,7 @@ void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) uint32_t size; /* Get output result size */ - size = opsize; + size = hpka->opsize; /* Move the result to appropriate location (indicated in out parameter) */ PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size); @@ -923,7 +973,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInType { /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); - primeordersize = in->primeOrderSize; + hpka->primeordersize = in->primeOrderSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout); } @@ -938,7 +988,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT { /* Set input parameter in PKA RAM */ PKA_ECDSASign_Set(hpka, in); - primeordersize = in->primeOrderSize; + hpka->primeordersize = in->primeOrderSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE); } @@ -955,7 +1005,7 @@ void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDe uint32_t size; /* Get output result size */ - size = primeordersize; + size = hpka->primeordersize; if (out != NULL) @@ -1071,11 +1121,18 @@ void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) */ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + } + else + { + return HAL_ERROR; + } } /** @@ -1086,11 +1143,18 @@ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTy */ HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + } + else + { + return HAL_ERROR; + } } /** @@ -1116,7 +1180,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *i { /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); - modulussize = in->modulusSize; + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); } @@ -1131,7 +1195,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef { /* Set input parameter in PKA RAM */ PKA_ECCMul_Set(hpka, in); - modulussize = in->modulusSize; + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } @@ -1146,7 +1210,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDe { /* Set input parameter in PKA RAM */ PKA_ECCMulEx_Set(hpka, in); - modulussize = in->modulusSize; + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); } @@ -1161,7 +1225,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTyp { /* Set input parameter in PKA RAM */ PKA_ECCMulEx_Set(hpka, in); - modulussize = in->modulusSize; + hpka->modulussize = in->modulusSize; /* Start the operation */ return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); } @@ -1176,7 +1240,7 @@ void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out uint32_t size; /* Get output result size */ - size = modulussize; + size = hpka->modulussize; /* If a destination buffer is provided */ if (out != NULL) diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pwr.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pwr.c index d71429317..aca2facf6 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pwr.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_pwr.c @@ -518,6 +518,13 @@ __weak void HAL_PWR_PVDCallback(void) * privileged access. * @note Privilege attribute for nsecure items can be managed by a secure * privileged access or by a nsecure privileged access. + * @note As the privileged attributes concern either all secure or all non-secure + * PWR resources accesses and not each PWR individual items access attribute, + * the application must ensure that the privilege access attribute configurations + * are coherent amongst the security level set on PWR individual items so not to + * overwrite a previous more restricted access rule (consider either all secure + * and/or all non-secure PWR resources accesses by privileged-only transactions + * or privileged and unprivileged transactions). * @param Item : Specifies the item(s) to set attributes on. * This parameter can be a combination of @ref PWR_Items. * @param Attributes : Specifies the available attribute(s). diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rcc.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rcc.c index b142aa486..466d625fb 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rcc.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rcc.c @@ -1742,6 +1742,13 @@ __weak void HAL_RCC_CSSCallback(void) * Default state is non-secure and unprivileged access allowed. * @note Secure and non-secure attributes can only be set from the secure * state when the system implements the security (TZEN=1). + * @note As the privileged attributes concern either all secure or all non-secure + * RCC resources accesses and not each RCC individual items access attribute, + * the application must ensure that the privilege access attribute configurations + * are coherent amongst the security level set on RCC individual items + * so not to overwrite a previous more restricted access rule (consider either + * all secure and/or all non-secure RCC resources accesses by privileged-only + * transactions or privileged and unprivileged transactions). * @param Item Item(s) to set attributes on. * This parameter can be a one or a combination of @ref RCC_items (**). * @param Attributes specifies the RCC secure/privilege attributes. diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rcc_ex.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rcc_ex.c index 6eb5ad771..84eb931fe 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rcc_ex.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rcc_ex.c @@ -2448,7 +2448,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe * clocks (ADC12, DAC, SDMMC1, SDMMC2, OCTOSPI1, TIM, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6, * SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8, * UART9, USART10, USART11, UART12, LPUART1, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2, CEC, FDCAN, SAI1, - * SAI2, USB, PLAY1), PLL2 and PLL3. + * SAI2, USB), PLL2 and PLL3. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) @@ -2758,61 +2758,6 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) { pPeriphClkInit->TimPresSelection = RCC_TIMPRES_ACTIVATED; } - -#if defined(PLAY1) - /* Get the PLAY1 clock source ------------------------------------------------*/ - pPeriphClkInit->PLAY1ClockSelection = __HAL_RCC_GET_PLAY1_SOURCE(); -#endif /* PLAY1 */ - -#if defined(USB_OTG_FS) - /* Get the USB_OTG_FS clock source ------------------------------------------------*/ - pPeriphClkInit->OtgfsClockSelection = __HAL_RCC_GET_OTGFS_SOURCE(); -#endif /* USB_OTG_FS */ - -#if defined(USB_OTG_HS) - /* Get the USB_OTG_HS clock source ------------------------------------------------*/ - pPeriphClkInit->OtghsClockSelection = __HAL_RCC_GET_OTGHS_SOURCE(); -#endif /* USB_OTG_HS */ - -#if defined(OCTOSPI2) - /* Get the OSPI2 clock source -----------------------------------------------*/ - pPeriphClkInit->Ospi2ClockSelection = __HAL_RCC_GET_OSPI2_SOURCE(); -#endif /* OCTOSPI2 */ - -#if defined(LTDC) - /* Get the LTDC clock source ------------------------------------------------*/ - pPeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); -#endif /* LTDC */ - -#if defined(ADF1) - /* Get the ADF1 clock source ------------------------------------------------*/ - pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE(); -#endif /* ADF1 */ - -#if defined(MDF1) - /* Get the MDF1 clock source ------------------------------------------------*/ - pPeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE(); -#endif /* MDF1 */ - -#if defined(RCC_CCIPR4_ETHCLKSEL) - /* Get the ETH clock source ------------------------------------------------*/ - pPeriphClkInit->EthClockSelection = __HAL_RCC_GET_ETH_SOURCE(); -#endif /* RCC_CCIPR4_ETHCLKSEL */ - -#if defined(RCC_CCIPR5_ETHPTPCLKSEL) - /* Get the ETHPTP clock source ------------------------------------------------*/ - pPeriphClkInit->EthptpClockSelection = __HAL_RCC_GET_ETHPTP_SOURCE(); -#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ - -#if defined(RCC_CCIPR5_ETHT1SCLKSEL) - /* Get the ETHT1S clock source ------------------------------------------------*/ - pPeriphClkInit->Etht1sClockSelection = __HAL_RCC_GET_ETHT1S_SOURCE(); -#endif /* RCC_CCIPR5_ETHT1SCLKSEL */ - -#if defined(RCC_CCIPR5_ETHREFCLKSEL) - /* Get the ETHREF clock source ------------------------------------------------*/ - pPeriphClkInit->EthrefClockSelection = __HAL_RCC_GET_ETHREF_SOURCE(); -#endif /* RCC_CCIPR5_ETHREFCLKSEL */ } /** @@ -2847,7 +2792,7 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *pPLL1_Clocks) pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N); pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); - pll1fracen = RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN; + pll1fracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ RCC_PLL1FRACR_PLL1FRACN_Pos)); @@ -2983,7 +2928,7 @@ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *pPLL2_Clocks) pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N); pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC); pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos); - pll2fracen = RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN; + pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos); fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \ RCC_PLL2FRACR_PLL2FRACN_Pos)); @@ -3117,7 +3062,7 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *pPLL3_Clocks) pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N); pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC); pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos); - pll3fracen = RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN; + pll3fracen = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN) >> RCC_PLL3CFGR_PLL3FRACEN_Pos); fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \ RCC_PLL3FRACR_PLL3FRACN_Pos)); @@ -5308,33 +5253,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) frequency = 0U; break; #endif /* USB_DRD_FS */ - -#if defined(RCC_CCIPR4_ETHCLKSEL) - case RCC_PERIPHCLK_ETH: - - /* Get the current ETH kernel source */ - srcclk = __HAL_RCC_GET_ETH_SOURCE(); - switch (srcclk) - { - case RCC_ETHCLKSOURCE_PLL1Q: - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - break; - } - case RCC_ETHCLKSOURCE_HSE: - { - frequency = HSE_VALUE; - break; - } - default: - { - frequency = 0U; - break; - } - } - break; -#endif /* RCC_CCIPR4_ETHCLKSEL */ } } return (frequency); diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rng.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rng.c index caecaa7c5..cb6ca88a7 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rng.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rng.c @@ -197,19 +197,20 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Disable RNG */ __HAL_RNG_DISABLE(hrng); - /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ - MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); #if defined(RNG_CR_NIST_VALUE) /* Recommended value for NIST compliance, refer to application note AN4230 */ - WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE); -#endif /* defined(RNG_CR_NIST_VALUE) */ + WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST | hrng->Init.ClockErrorDetection); +#else + /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); +#endif /* RNG_CR_NIST_VALUE */ #if defined(RNG_HTCR_NIST_VALUE) /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); -#endif /* defined(RNG_HTCR_NIST_VALUE) */ +#endif /* RNG_HTCR_NIST_VALUE */ #if defined(RNG_NSCR_NIST_VALUE) WRITE_REG(hrng->Instance->NSCR, RNG_NSCR_NIST_VALUE); -#endif /* defined(RNG_NSCR_NIST_VALUE) */ +#endif /* RNG_NSCR_NIST_VALUE */ /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -652,6 +653,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } } diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rng_ex.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rng_ex.c index 96bd9d982..693747bde 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rng_ex.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rng_ex.c @@ -306,6 +306,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /* sequence to fully recover from a seed error */ status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } } else { diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rtc_ex.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rtc_ex.c index 348ead9a4..10dc59269 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rtc_ex.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_rtc_ex.c @@ -3099,6 +3099,38 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(const RTC_HandleTypeDef *hrtc, RTC_ */ #endif /* TAMP_PRIVCFGR_TAMPPRIV */ +#if defined (RTC_OR_OUT2_RMP) +/** + * @brief Enable RTC OUT2 remap feature. + * @note When enable RTC_OUT2 is mapped on PB2. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_EnableRemapRtcOut2(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Enable RTC OUT2 remap */ + SET_BIT(RTC->OR, RTC_OR_OUT2_RMP); +} + +/** + * @brief Disable RTC OUT2 remap feature. + * @note When disable RTC_OUT2 is mapped on PI8. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_DisableRemapRtcOut2(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Disable RTC OUT2 remap */ + CLEAR_BIT(RTC->OR, RTC_OR_OUT2_RMP); +} +#endif /* defined (RTC_OR_OUT2_RMP) */ + /** * @} */ diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_smartcard.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_smartcard.c index 13efd2571..62a740c02 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_smartcard.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_smartcard.c @@ -828,6 +828,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, co /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -935,6 +943,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; @@ -1001,6 +1017,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->TxXferCount = Size; hsmartcard->TxISR = NULL; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -1094,6 +1118,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Configure Rx interrupt processing */ if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess)) { @@ -1395,8 +1427,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1420,8 +1454,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1492,8 +1528,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1558,8 +1596,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1657,9 +1697,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable DMA Tx at UART level */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1681,8 +1723,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1771,8 +1815,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1869,8 +1915,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmarx != NULL) { @@ -2052,8 +2100,10 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel */ if (hsmartcard->hdmarx != NULL) { @@ -2106,8 +2156,10 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel */ if (hsmartcard->hdmatx != NULL) { @@ -2759,10 +2811,12 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); hsmartcard->TxXferCount = 0U; +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the SMARTCARD associated USART CR3 register */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Enable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); } @@ -2782,10 +2836,12 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the SMARTCARD associated USART CR3 register */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* At end of Rx process, restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_spi.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_spi.c index 02a4f0776..69990384a 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_spi.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_spi.c @@ -242,6 +242,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { uint32_t crc_length; uint32_t packet_length; +#if (USE_SPI_CRC != 0UL) + uint32_t crc_poly_msb_mask; +#endif /* USE_SPI_CRC */ /* Check the SPI handle allocation */ if (hspi == NULL) @@ -329,6 +332,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) crc_length = hspi->Init.CRCLength; } + /* Verify the correctness of polynom size */ + assert_param(IS_SPI_CRC_POLYNOMIAL_SIZE(hspi->Init.CRCPolynomial, crc_length)); + /* Verify that the CRC Length is higher than DataSize */ if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos)) { @@ -446,15 +452,21 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) || ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT))) { + /* Set SPI_CR1_CRC33_17 bit */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + /* Write CRC polynomial in SPI Register */ + WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); } else { + /* Clear SPI_CR1_CRC33_17 bit */ CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); - } - /* Write CRC polynomial in SPI Register */ - WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); + /* Write CRC polynomial and set MSB bit at 1 in SPI Register */ + /* Set MSB is mandatory for a correct CRC computation */ + crc_poly_msb_mask = (0x1UL << ((crc_length >> SPI_CFG1_CRCSIZE_Pos) + 0x1U)); + WRITE_REG(hspi->Instance->CRCPOLY, (hspi->Init.CRCPolynomial) | crc_poly_msb_mask); + } } #endif /* USE_SPI_CRC */ @@ -836,6 +848,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1052,6 +1074,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint32_t temp_sr_reg; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); #if defined (__GNUC__) __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ @@ -1059,6 +1084,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1117,8 +1152,18 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { - /* Check the RXWNE/EOT flag */ - if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) { *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); hspi->pRxBuffPtr += sizeof(uint32_t); @@ -1149,6 +1194,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + /* Check the RXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { @@ -1156,6 +1204,34 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; @@ -1185,6 +1261,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + /* Check the RXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { @@ -1192,6 +1271,26 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->pRxBuffPtr += sizeof(uint8_t); hspi->RxXferCount--; } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } else { /* Timeout management */ @@ -1262,12 +1361,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t uint32_t tickstart; uint32_t fifo_length; + uint32_t temp_sr_reg; uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1343,28 +1455,44 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check RXWNE/EOT flag */ - if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL)) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount --; - initial_RxXferCount = hspi->RxXferCount; - } + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + if (initial_RxXferCount > 0UL) { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - /* Unlock the process */ - __HAL_UNLOCK(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1390,32 +1518,70 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check the RXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + if (initial_RxXferCount > 0UL) { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } - - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - /* Unlock the process */ - __HAL_UNLOCK(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1434,28 +1600,58 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check the RXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + if (initial_RxXferCount > 0UL) { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - /* Unlock the process */ - __HAL_UNLOCK(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1497,6 +1693,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if ((pData == NULL) || (Size == 0UL)) { return HAL_ERROR; @@ -1581,6 +1787,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1676,6 +1892,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1793,6 +2019,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1979,6 +2215,15 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } if (hspi->State != HAL_SPI_STATE_READY) { @@ -2169,6 +2414,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -2203,9 +2458,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); /* Packing mode management is enabled by the DMA settings */ - if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && \ + ((hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) || \ + (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD)) && \ (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ - ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && \ + ((hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE) || \ + (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)))) { /* Restriction the DMA data received is not allowed in this mode */ /* Unlock the process */ @@ -2618,6 +2877,15 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized before any call to DMA Abort functions */ + if (hspi->hdmarx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */ + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + } + if (hspi->hdmatx != NULL) { if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_spi_ex.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_spi_ex.c index 6df6b9b5e..b5ae786b9 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_spi_ex.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_spi_ex.c @@ -57,7 +57,6 @@ data transfers. (#) SPIEx function: - (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_EnableLockConfiguration() (++) HAL_SPIEx_ConfigureUnderrun() @@ -208,6 +207,100 @@ HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t __HAL_UNLOCK(hspi); return errorcode; } +#if defined(SPI_CFG1_DRDS) + +/** + * @brief Enable the Delay Read Data Sampling on Master Input IO + * DRDS setting has no impact on the other SCK management. + * When CRC is enabled, CRC computation and evaluation is delayed too. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +HAL_StatusTypeDef HAL_SPIEx_EnableDelayReadDataSampling(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Check if the SPI is disabled to edit DRDS bit */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_DRDS); + } + else + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_DRDS); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Disable the Delay Read Data Sampling on Master Input IO + * DRDS setting has no impact on the other SCK management. + * When CRC is enabled, CRC computation and evaluation is delayed too. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +HAL_StatusTypeDef HAL_SPIEx_DisableDelayReadDataSampling(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Check if the SPI is disabled to edit DRDS bit */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_DRDS); + } + else + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_DRDS); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} +#endif /* SPI_CFG1_DRDS */ /** * @} diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_uart.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_uart.c index 241bd8f83..c0f6fb8dc 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_uart.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_uart.c @@ -1452,6 +1452,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + +#endif /* USART_DMAREQUESTS_SW_WA */ if (huart->hdmatx != NULL) { /* Set the UART DMA transfer complete callback */ @@ -1514,9 +1519,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } } +#if !defined(USART_DMAREQUESTS_SW_WA) /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -3968,7 +3975,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_xspi.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_xspi.c index c2015166e..466490ba4 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_xspi.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_hal_xspi.c @@ -865,9 +865,10 @@ HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTyp if (pCmd->DataMode == HAL_XSPI_DATA_NONE) { /* When there is no data phase, the transfer start as soon as the configuration is done - so wait until TC flag is set to go back in idle state */ - status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); + so wait until BUSY flag is reset to go back in idle state */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + /* Clear TC flag */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); } else @@ -2394,12 +2395,10 @@ HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSP HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) { HAL_StatusTypeDef status = HAL_OK; - uint32_t state; uint32_t tickstart = HAL_GetTick(); - /* Check if the state is in one of the busy or configured states */ - state = hxspi->State; - if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + /* Check if the state is not in reset state */ + if (hxspi->State != HAL_XSPI_STATE_RESET) { /* Check if the DMA is enabled */ if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) @@ -2472,11 +2471,9 @@ HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) { HAL_StatusTypeDef status = HAL_OK; - uint32_t state; - /* Check if the state is in one of the busy or configured states */ - state = hxspi->State; - if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + /* Check if the state is not in reset state */ + if (hxspi->State != HAL_XSPI_STATE_RESET) { /* Disable all interrupts */ HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE)); @@ -3050,6 +3047,14 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC /* Configure the CCR register with DQS and SIOO modes */ *ccr_reg = (pCmd->DQSMode | pCmd->SIOOMode); + /* Workaround for Erratasheet: Memory-mapped write error response when DQS output is disabled */ + if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) + { + /* When doing memory-mapped writes, set the DQSE bit of the OCTOSPI_WCCR register, + even for memories that have no DQS pin. */ + SET_BIT((*ccr_reg), XSPI_CCR_DQSE); + } + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) { /* Configure the ABR register with alternate bytes value */ @@ -3072,6 +3077,25 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC } } + /* Configure SSHIFT register to handle SDR/DTR data transfer */ + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE) + { + /* Deactivate sample shifting when receiving data in DTR mode (DDTR=1) */ + CLEAR_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); + } + else if (hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE) + { + /* Configure sample shifting */ + SET_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); + } + else + { + /* Do nothing */ + } + } + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) { if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_dac.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_dac.c index 4583232d4..df2c52616 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_dac.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_dac.c @@ -54,22 +54,22 @@ /* Devices STM32H563/H573xx */ #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_CH1) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_CH1) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_CH1) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_CH1) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ ) #else /* Devices STM32H503xx */ #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ - ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ + ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_dma.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_dma.c index 054beb89d..d2d784ac7 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_dma.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_dma.c @@ -847,8 +847,7 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection)); } - /* Check node type */ - if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE) + /* Check non 2D addressing settings */ { assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength)); assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength)); @@ -1087,7 +1086,11 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2)); } } - + else + { + /* Reset of the CLLR of the node being created */ + pNode->LinkRegisters[reg_counter] = 0U; + } return (uint32_t)SUCCESS; } diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_exti.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_exti.c index 58c008e9f..5029fdbcf 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_exti.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_exti.c @@ -81,20 +81,17 @@ ErrorStatus LL_EXTI_DeInit(void) { /* Interrupt mask register set to default reset values */ LL_EXTI_WriteReg(IMR1, 0xFFFE0000U); -#if defined(STM32H533xx) || defined(STM32H523xx) +#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx)) + LL_EXTI_WriteReg(IMR2, 0x03DBBFFFU); +#elif defined(STM32H533xx) LL_EXTI_WriteReg(IMR2, 0x07DBFFFFU); -#elif defined(STM32H503xx) - LL_EXTI_WriteReg(IMR2, 0x001BFFFFU); #else - LL_EXTI_WriteReg(IMR2, 0x03DBBFFFU); -#endif /* defined(STM32H533xx) || defined(STM32H523xx) */ + LL_EXTI_WriteReg(IMR2, 0x001BFFFFU); +#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */ /* Event mask register set to default reset values */ LL_EXTI_WriteReg(EMR1, 0x00000000U); LL_EXTI_WriteReg(EMR2, 0x00000000U); -#if defined(EXTI_EMR3_EM) - LL_EXTI_WriteReg(EMR3, 0x00000000U); -#endif /* EXTI_EMR3_EM */ /* Rising Trigger selection register set to default reset values */ LL_EXTI_WriteReg(RTSR1, 0x00000000U); @@ -262,7 +259,6 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) /* De-configure EXTI Lines in range from 32 to 63 */ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); - } return status; } diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_gpio.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_gpio.c index efa633a2b..340ed846b 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_gpio.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_gpio.c @@ -31,7 +31,7 @@ */ #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \ - defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + defined (GPIOG) || defined (GPIOH) || defined (GPIOI) /** @addtogroup GPIO_LL * @{ @@ -166,20 +166,6 @@ ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx) LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOI); } #endif /* GPIOI */ -#if defined(GPIOJ) - else if (GPIOx == GPIOJ) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOJ); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOJ); - } -#endif /* GPIOJ */ -#if defined(GPIOK) - else if (GPIOx == GPIOK) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOK); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOK); - } -#endif /* GPIOK */ else { status = ERROR; @@ -293,8 +279,7 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) */ #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \ - defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || \ - defined (GPIOK) ||*/ + defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */ /** * @} diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_i3c.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_i3c.c index cabc24279..634a56757 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_i3c.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_i3c.c @@ -18,8 +18,8 @@ #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ -#include "stm32h5xx_ll_i3c.h" #include "stm32h5xx_ll_bus.h" +#include "stm32h5xx_ll_i3c.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_rcc.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_rcc.c index 59aadb886..3930068f2 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_rcc.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_rcc.c @@ -2098,6 +2098,7 @@ uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource) } break; + case LL_RCC_I3C2_CLKSOURCE_NONE: /* No Clock used for I3C2 */ break; @@ -2884,7 +2885,18 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) } } break; -#endif /* LL_RCC_USB_CLKSOURCE_PLL3 */ +#else + case LL_RCC_USB_CLKSOURCE_PLL2Q: /* PLL2 Q clock used as USB clock source */ + if (LL_RCC_PLL2_IsReady() != 0U) + { + if (LL_RCC_PLL2Q_IsEnabled() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + usb_frequency = PLL_Clocks.PLL_Q_Frequency; + } + } + break; +#endif /* LL_RCC_USB_CLKSOURCE_PLL3Q */ case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */ if (LL_RCC_HSI48_IsReady() == 1U) diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_spi.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_spi.c index d0b0e04d1..12233eb70 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_spi.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_spi.c @@ -566,7 +566,7 @@ ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx) * - SUCCESS: SPI registers are Initialized * - ERROR: SPI registers are not Initialized */ -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct) { uint32_t i2sdiv = 0UL; uint32_t i2sodd = 0UL; diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_usb.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_usb.c index bcff16901..7904b05e6 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_usb.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_ll_usb.c @@ -46,14 +46,2272 @@ */ #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) -#if defined (USB_DRD_FS) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ + +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the USB Core + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; +#if defined (STM32H5F5xx) || defined (STM32H5E5xx) + if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + { + /* Init The UTMI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS); + } + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + if (cfg.dma_enable == 1U) + { + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + } + +#else + + /* Select FS Embedded PHY */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + if (cfg.battery_charging_enable == 0U) + { + /* Activate the USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + else + { + /* Deactivate the USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } +#endif /* defined (STM32H5F5xx) || defined (STM32H5E5xx) */ + + return ret; +} + + +/** + * @brief Set the USB turnaround time + * @param USBx USB Instance + * @param hclk: AHB clock frequency + * @retval USB turnaround time In PHY Clocks number + */ +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, + uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USBD_FS_SPEED) + { + if ((hclk >= 14200000U) && (hclk < 15000000U)) + { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } + else if ((hclk >= 15000000U) && (hclk < 16000000U)) + { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } + else if ((hclk >= 16000000U) && (hclk < 17200000U)) + { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } + else if ((hclk >= 17200000U) && (hclk < 18500000U)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } + else if ((hclk >= 18500000U) && (hclk < 20000000U)) + { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } + else if ((hclk >= 20000000U) && (hclk < 21800000U)) + { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } + else if ((hclk >= 21800000U) && (hclk < 24000000U)) + { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } + else if ((hclk >= 24000000U) && (hclk < 27700000U)) + { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } + else if ((hclk >= 27700000U) && (hclk < 32000000U)) + { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } + else if (speed == USBD_HS_SPEED) + { + UsbTrd = USBD_HS_TRDT_VALUE; + } + else + { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); + + return HAL_OK; +} + +/** + * @brief USB_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_SetCurrentMode Set functional mode + * @param USBx Selected device + * @param mode current core mode + * This parameter can be one of these values: + * @arg USB_DEVICE_MODE Peripheral mode + * @arg USB_HOST_MODE Host mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) +{ + uint32_t ms = 0U; + + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_HOST_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + + do + { + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); + } + else if (mode == USB_DEVICE_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + + do + { + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); + } + else + { + return HAL_ERROR; + } + + if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_DevInit Initializes the USB_OTG controller registers + * for device mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + /* Disable USB PHY pulldown resistors */ + USBx->GCCFG &= ~USB_OTG_GCCFG_PULLDOWNEN; + } + + /* VBUS Sensing setup */ + if (cfg.vbus_sensing_enable == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + /* Deactivate VBUS Sensing B */ + USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + /* B-peripheral session valid override enable */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN; + USBx->GCCFG |= USB_OTG_GCCFG_VBVALOVAL; + } +#endif /* defined (USB_OTG_HS) */ + } + else + { + /* B-peripheral session valid override disable */ + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + USBx->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN; + USBx->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL; + } +#if defined (USB_OTG_HS) + else + { + USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALEXTOEN; + USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALOVAL; + } +#endif /* defined (USB_OTG_HS) */ + + /* Enable HW VBUS sensing */ + USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; + } + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + +#if defined (STM32H5F5xx) || defined (STM32H5E5xx) + if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + { + if (cfg.speed == USBD_HS_SPEED) + { + /* Set Core speed to High speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); + } + } + else +#endif /* defined (STM32H5F5xx) || defined (STM32H5E5xx) */ + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); + } + + /* Flush the FIFOs */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending Device Interrupts */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } + } + else + { + USBx_INEP(i)->DIEPCTL = 0U; + } + + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + } + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } + } + else + { + USBx_OUTEP(i)->DOEPCTL = 0U; + } + + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xBFFFFFFFU; + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Device mode ONLY */ + USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; + + if (cfg.Sof_enable != 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; + } + + if (cfg.vbus_sensing_enable == 1U) + { + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + } + + return ret; +} + +/** + * @brief USB_FlushTxFifo Flush a Tx FIFO + * @param USBx Selected device + * @param num FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush TX Fifo */ + count = 0U; + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo Flush Rx FIFO + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush RX Fifo */ + count = 0U; + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register + * depending the PHY type and the enumeration speed of the device. + * @param USBx Selected device + * @param speed device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @retval Hal status + */ +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG |= speed; + return HAL_OK; +} + +/** + * @brief USB_GetDevSpeed Return the Dev Speed + * @param USBx Selected device + * @retval speed device speed + * This parameter can be one of these values: + * @arg USBD_HS_SPEED: High speed mode + * @arg USBD_FS_SPEED: Full speed mode + */ +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + { + speed = USBD_HS_SPEED; + } + else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) + { + speed = USBD_FS_SPEED; + } + else + { + speed = 0xFU; + } + + return speed; +} + +/** + * @brief Activate and configure an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + } + else + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } + } + return HAL_OK; +} + +/** + * @brief Activate and configure a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + } + + return HAL_OK; +} + +/** + * @brief USB_EPStartXfer : setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (pktcnt << 19)); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (pktcnt << 29)); + } + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + } + + if (dma == 1U) + { + if ((uint32_t)ep->dma_addr != 0U) + { + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + } + else + { + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + else + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); + } + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; + + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + } + } + + if (dma == 1U) + { + if ((uint32_t)ep->xfer_buff != 0U) + { + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); + } + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } + else + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } + } + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + + return HAL_OK; +} + + +/** + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* EP enable, IN data in FIFO */ + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); + } + } + else /* OUT endpoint */ + { + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } + } + + return ret; +} + + +/** + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * with the EP/channel + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t *pSrc = src; + uint32_t count32b; + uint32_t i; + + if (dma == 0U) + { + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) + { + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; + pSrc++; + pSrc++; + pSrc++; + } + } + + return HAL_OK; +} + +/** + * @brief USB_ReadPacket : read a packet from the RX FIFO + * @param USBx Selected device + * @param dest source pointer + * @param len Number of bytes to read + * @retval pointer to destination buffer + */ +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t *pDest = dest; + uint32_t pData; + uint32_t i; + uint32_t count32b = (uint32_t)len >> 2U; + uint16_t remaining_bytes = len % 4U; + + for (i = 0U; i < count32b; i++) + { + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); + pDest++; + pDest++; + pDest++; + pDest++; + } + + /* When Number of data is not word aligned, read the remaining byte */ + if (remaining_bytes != 0U) + { + i = 0U; + __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); + + do + { + *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); + i++; + pDest++; + remaining_bytes--; + } while (remaining_bytes != 0U); + } + + return ((void *)pDest); +} + +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return HAL_OK; +} + +/** + * @brief USB_StopDevice : Stop the usb device mode + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Clear Pending interrupt */ + for (i = 0U; i < 15U; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + /* Clear interrupt masks */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + /* Flush the FIFO */ + ret = USB_FlushRxFifo(USBx); + if (ret != HAL_OK) + { + return ret; + } + + ret = USB_FlushTxFifo(USBx, 0x10U); + if (ret != HAL_OK) + { + return ret; + } + + return ret; +} + +/** + * @brief USB_SetDevAddress : Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + + return HAL_OK; +} + +/** + * @brief USB_DevConnect : Connect the USB device by enabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx Selected device + * @retval USB Global Interrupt status + */ +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t tmpreg; + + tmpreg = USBx->GINTSTS; + tmpreg &= USBx->GINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadChInterrupts: return USB channel interrupt status + * @param USBx Selected device + * @param chnum Channel number + * @retval USB Channel Interrupt status + */ +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_HC(chnum)->HCINT; + tmpreg &= USBx_HC(chnum)->HCINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status + * @param USBx Selected device + * @retval USB Device OUT EP interrupt status + */ +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); +} + +/** + * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status + * @param USBx Selected device + * @retval USB Device IN EP interrupt status + */ +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; + tmpreg &= USBx_DEVICE->DOEPMSK; + + return tmpreg; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + uint32_t msk; + uint32_t emp; + + msk = USBx_DEVICE->DIEPMSK; + emp = USBx_DEVICE->DIEPEMPMSK; + msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + + return tmpreg; +} + +/** + * @brief USB_ClearInterrupts: clear a USB interrupt + * @param USBx Selected device + * @param interrupt flag + * @retval None + */ +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) +{ + USBx->GINTSTS &= interrupt; +} + +/** + * @brief Returns USB core mode + * @param USBx Selected device + * @retval return core mode : Host or Device + * This parameter can be one of these values: + * 0 : Host + * 1 : Device + */ +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) +{ + return ((USBx->GINTSTS) & 0x1U); +} + +/** + * @brief Activate EP0 for Setup transactions + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* Set the MPS of the IN EP0 to 64 bytes */ + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; + + return HAL_OK; +} + +/** + * @brief Prepare the EP0 to start the first control setup + * @param USBx Selected device + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @param psetup pointer to setup packet + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + + if (gSNPSiD > USB_OTG_CORE_ID_300A) + { + if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + return HAL_OK; + } + } + + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + + if (dma == 1U) + { + USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; + /* EP enable */ + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; + } + + return HAL_OK; +} + +/** + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRSTDONE) == 0U); + + /* Clear Core Soft Reset */ + USBx->GRSTCTL &= ~USB_OTG_GRSTCTL_CSRST; + + return HAL_OK; +} + +/** + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + /* Enable USB PHY pulldown resistors */ + USBx->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN; + } + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { +#if defined (USB_OTG_HS) + /* Disable VBUS override */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBVALOVAL | USB_OTG_GCCFG_VBVALEXTOEN); +#endif /* defined (USB_OTG_HS) */ + } + + /* Disable VBUS sensing */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) + { + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + } +#if defined (USB_OTG_HS) + else + { + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + } +#endif /* defined (USB_OTG_HS) */ + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + if (cfg.speed == USBH_FSLS_SPEED) + { + /* Force Device Enumeration to FS/LS mode only */ + USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + + /* Make sure the FIFOs are flushed. */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending HC Interrupts */ + for (i = 0U; i < cfg.Host_channels; i++) + { + USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; + USBx_HC(i)->HCINTMSK = 0U; + } + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x200U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + } + else +#endif /* defined (USB_OTG_HS) */ + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x80U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + } + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Host mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + + return ret; +} + +/** + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * HCFG register on the PHY type and set the right frame interval + * @param USBx Selected device + * @param freq clock frequency + * This parameter can be one of these values: + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @retval HAL status + */ +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) + { + USBx_HOST->HFIR = HFIR_48_MHZ; + } + else if (freq == HCFG_6_MHZ) + { + USBx_HOST->HFIR = HFIR_6_MHZ; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_OTG_ResetPort : Reset Host Port + * @param USBx Selected device + * @retval HAL status + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + HAL_Delay(100U); /* See Note #1 */ + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + HAL_Delay(10U); + + return HAL_OK; +} + +/** + * @brief USB_DriveVbus : activate or de-activate vbus + * @param state VBUS state + * This parameter can be one of these values: + * 0 : Deactivate VBUS + * 1 : Activate VBUS + * @retval HAL status + */ +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) + { + USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); + } + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) + { + USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + } + return HAL_OK; +} + +/** + * @brief Return Host Core speed + * @param USBx Selected device + * @retval speed : Host speed + * This parameter can be one of these values: + * @arg HCD_SPEED_HIGH: High speed mode + * @arg HCD_SPEED_FULL: Full speed mode + * @arg HCD_SPEED_LOW: Low speed mode + */ +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); +} + +/** + * @brief Return Host Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); +} + +/** + * @brief Initialize a host channel + * @param USBx Selected device + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @arg USB_OTG_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL: Control type + * @arg EP_TYPE_ISOC: Isochronous type + * @arg EP_TYPE_BULK: Bulk type + * @arg EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size + * This parameter can be a value from 0 to 32K + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir; + uint32_t HCcharLowSpeed; + uint32_t HostCoreSpeed; + + /* Clear old interrupt conditions for this host channel. */ + USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; + + /* Enable channel interrupts required for this transfer. */ + switch (ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + else + { +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM; + } +#endif /* defined (USB_OTG_HS) */ + } + break; + + case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + + break; + + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + } + break; + + default: + ret = HAL_ERROR; + break; + } + + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + + /* Enable host channel Halt interrupt */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; + + /* Enable the top level host channel interrupt. */ + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + /* Make sure host channel interrupts are enabled. */ + USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; + + /* Program the HCCHAR register */ + if ((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + HostCoreSpeed = USB_GetHostSpeed(USBx); + + /* LS device plugged to HUB */ + if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | + USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; + + if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) + { + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + } + + return ret; +} + +/** + * @brief Start a transfer over a host channel + * @param USBx Selected device + * @param hc pointer to host channel structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + __IO uint32_t tmpreg; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; + +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ + if (dma == 1U) + { + if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U)) + { + + USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NAKM); + } + } + else + { + if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U)) + { + (void)USB_DoPing(USBx, hc->ch_num); + return HAL_OK; + } + } + } +#endif /* defined (USB_OTG_HS) */ + + if (hc->do_ssplit == 1U) + { + /* Set number of packet to 1 for Split transaction */ + num_packets = 1U; + + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + if (hc->ep_type == EP_TYPE_ISOC) + { + if (hc->xfer_len > ISO_SPLT_MPS) + { + /* Isochrone Max Packet Size for Split mode */ + hc->XferSize = hc->max_packet; + hc->xfer_len = hc->XferSize; + + if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_MIDDLE; + } + else + { + hc->iso_splt_xactPos = HCSPLT_BEGIN; + } + } + else + { + hc->XferSize = hc->xfer_len; + + if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_FULL; + } + else + { + hc->iso_splt_xactPos = HCSPLT_END; + } + } + } + else + { + if ((dma == 1U) && (hc->xfer_len > hc->max_packet)) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + } + } + else + { + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + + /* + * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of + * max_packet size. + */ + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + + /* Initialize the HCTSIZn register */ + USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + + if (dma != 0U) + { + /* xfer_buff MUST be 32-bits aligned */ + USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; + } + + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + + if (hc->do_ssplit == 1U) + { + /* Set Hub start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) | + (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN; + + /* unmask ack & nyet for IN/OUT transactions */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NYET); + + if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + } + + if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) && + (hc->do_csplit == 1U) && (hc->ep_is_in == 1U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + } + + /* Position management for iso out transaction on split mode */ + if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U)) + { + /* Set data payload position */ + switch (hc->iso_splt_xactPos) + { + case HCSPLT_BEGIN: + /* First data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1; + break; + + case HCSPLT_MIDDLE: + /* Middle data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos; + break; + + case HCSPLT_END: + /* End data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0; + break; + + case HCSPLT_FULL: + /* Entire data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS; + break; + + default: + break; + } + } + } + else + { + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + } + + /* Set host channel enable */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + } + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + + if (dma != 0U) /* dma mode */ + { + return HAL_OK; + } + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U)) + { + switch (hc->ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; + + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; + + default: + break; + } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + } + + return HAL_OK; +} + +/** + * @brief Read all host channel interrupts status + * @param USBx Selected device + * @retval HAL state + */ +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); +} + +/** + * @brief Halt a host channel + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + __IO uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; + + /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. + At the end of the next uframe/frame (in the worst case), the core generates a channel halted + and disables the channel automatically. */ + + if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && + ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) + { + return HAL_OK; + } + + /* Check for space in the request queue to issue the halt. */ + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) + { + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + + return HAL_OK; +} + +/** + * @brief Initiate Do Ping protocol + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; + + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; + + /* Set host channel enable */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + + return HAL_OK; +} + +/** + * @brief Stop Host Core + * @param USBx Selected device + * @retval HAL state + */ +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t count = 0U; + uint32_t value; + uint32_t i; + + (void)USB_DisableGlobalInt(USBx); + + /* Flush USB FIFO */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Flush out any leftover queued requests. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + } + + /* Halt all channels to put them into a known state. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value |= USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + + /* Clear any pending Host interrupts */ + USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; + + (void)USB_EnableGlobalInt(USBx); + + return ret; +} + +/** + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; + } + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx); #if (USE_USB_DOUBLE_BUFFER == 1U) static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, @@ -1469,7 +3727,7 @@ HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx) return HAL_OK; } - +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -1477,7 +3735,7 @@ HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx) /** * @} */ -#endif /* defined (USB_DRD_FS) */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ /** diff --git a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_util_i3c.c b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_util_i3c.c index 19d16d2df..fcd6c007f 100644 --- a/stm32cube/stm32h5xx/drivers/src/stm32h5xx_util_i3c.c +++ b/stm32cube/stm32h5xx/drivers/src/stm32h5xx_util_i3c.c @@ -27,6 +27,8 @@ * @{ */ +#if (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER) + /* Private typedef ---------------------------------------------------------------------------------------------------*/ /* Private define ----------------------------------------------------------------------------------------------------*/ /** @defgroup I3C_UTIL_Private_Define I3C Utility Private Define @@ -412,6 +414,8 @@ ErrorStatus I3C_TgtTimingComputation(const I3C_TgtTimingTypeDef *pInputTiming, */ /* Private functions ---------------------------------------------------------*/ + +#endif /* (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER) */ /** * @} */ diff --git a/stm32cube/stm32h5xx/soc/stm32h503xx.h b/stm32cube/stm32h5xx/soc/stm32h503xx.h index bc59cb054..3399c9f16 100644 --- a/stm32cube/stm32h5xx/soc/stm32h503xx.h +++ b/stm32cube/stm32h5xx/soc/stm32h503xx.h @@ -186,7 +186,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ @@ -13300,7 +13300,7 @@ typedef struct /******************************** SPI Instances *******************************/ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI3_NS)) -#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == NULL) +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == ((SPI_TypeDef *) 0xDEADDEADUL)) #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI3_NS)) diff --git a/stm32cube/stm32h5xx/soc/stm32h523xx.h b/stm32cube/stm32h5xx/soc/stm32h523xx.h index 0d5f8cdda..1ec059f20 100644 --- a/stm32cube/stm32h5xx/soc/stm32h523xx.h +++ b/stm32cube/stm32h5xx/soc/stm32h523xx.h @@ -215,7 +215,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ diff --git a/stm32cube/stm32h5xx/soc/stm32h533xx.h b/stm32cube/stm32h5xx/soc/stm32h533xx.h index 4bcb43a9d..bad6174bb 100644 --- a/stm32cube/stm32h5xx/soc/stm32h533xx.h +++ b/stm32cube/stm32h5xx/soc/stm32h533xx.h @@ -218,7 +218,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ diff --git a/stm32cube/stm32h5xx/soc/stm32h562xx.h b/stm32cube/stm32h5xx/soc/stm32h562xx.h index ecd0ae8fb..333ff277e 100644 --- a/stm32cube/stm32h5xx/soc/stm32h562xx.h +++ b/stm32cube/stm32h5xx/soc/stm32h562xx.h @@ -234,7 +234,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ diff --git a/stm32cube/stm32h5xx/soc/stm32h563xx.h b/stm32cube/stm32h5xx/soc/stm32h563xx.h index b4631f9fb..45beaa197 100644 --- a/stm32cube/stm32h5xx/soc/stm32h563xx.h +++ b/stm32cube/stm32h5xx/soc/stm32h563xx.h @@ -239,7 +239,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ diff --git a/stm32cube/stm32h5xx/soc/stm32h573xx.h b/stm32cube/stm32h5xx/soc/stm32h573xx.h index fcb7e97fe..a2d20dd2f 100644 --- a/stm32cube/stm32h5xx/soc/stm32h573xx.h +++ b/stm32cube/stm32h5xx/soc/stm32h573xx.h @@ -242,7 +242,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ diff --git a/stm32cube/stm32h5xx/soc/stm32h5xx.h b/stm32cube/stm32h5xx/soc/stm32h5xx.h index 947ccec92..e60a558bb 100644 --- a/stm32cube/stm32h5xx/soc/stm32h5xx.h +++ b/stm32cube/stm32h5xx/soc/stm32h5xx.h @@ -57,7 +57,7 @@ application */ -#if !defined (STM32H573xx) && !defined (STM32H563xx) \ +#if !defined (STM32H573xx) && !defined (STM32H563xx) \ && !defined (STM32H562xx) && !defined (STM32H503xx) \ && !defined (STM32H533xx) && !defined (STM32H523xx) /* #define STM32H573xx */ /*!< STM32H573xx Devices */ @@ -81,12 +81,12 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number 1.3.0 + * @brief CMSIS Device version number 1.3.1 */ -#define __STM32H5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32H5_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ -#define __STM32H5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ -#define __STM32H5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32H5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32H5_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32H5_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32H5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H5_CMSIS_VERSION ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\ |(__STM32H5_CMSIS_VERSION_SUB1 << 16U)\ |(__STM32H5_CMSIS_VERSION_SUB2 << 8U )\ diff --git a/stm32cube/stm32h7xx/CMakeLists.txt b/stm32cube/stm32h7xx/CMakeLists.txt index b283d6397..29d67ba8a 100644 --- a/stm32cube/stm32h7xx/CMakeLists.txt +++ b/stm32cube/stm32h7xx/CMakeLists.txt @@ -76,6 +76,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SAI drivers/src/stm32h7xx_hal_ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SAI_EX drivers/src/stm32h7xx_hal_sai_ex.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SD drivers/src/stm32h7xx_hal_sd.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SD_EX drivers/src/stm32h7xx_hal_sd_ex.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SDIO drivers/src/stm32h7xx_hal_sdio.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SDRAM drivers/src/stm32h7xx_hal_sdram.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD drivers/src/stm32h7xx_hal_smartcard.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD_EX drivers/src/stm32h7xx_hal_smartcard_ex.c) diff --git a/stm32cube/stm32h7xx/README b/stm32cube/stm32h7xx/README index d3b32cdbd..89d85ad64 100644 --- a/stm32cube/stm32h7xx/README +++ b/stm32cube/stm32h7xx/README @@ -6,7 +6,7 @@ Origin: http://www.st.com/en/embedded-software/stm32cubeh7.html Status: - version v1.11.2 + version v1.12.0 Purpose: ST Microelectronics official MCU package for STM32H7 series. @@ -23,7 +23,7 @@ URL: https://github.com/STMicroelectronics/STM32CubeH7 Commit: - abbf9ca1b36c9abdb9339e86f0b7b2f4e79edc35 + 430c9b3b3676dd71e1ce8ce81e1221d60298beb2 Maintained-by: External @@ -35,6 +35,7 @@ License Link: https://opensource.org/licenses/BSD-3-Clause Patch List: + *Changes from official delivery: -dos2unix applied -trailing white spaces removed @@ -57,26 +58,8 @@ Patch List: drivers/src/stm32h7xx_hal_eth.c ST Internal Reference: 142115 - *Enable legacy ethernet driver using HAL_ETH_LEGACY_MODULE_ENABLED - This will have to be removed once Zephyr driver is magrated ot the new - Cube HAL ethernet API. - - *Fix to use transmit timestamp when it is valid - Read timestamp only when status flag is set in Tx descriptor. - Fire transmit timestamp callbacks only when there is a valid - non-zero timestamp. - Impacted files: - drivers/src/stm32h7xx_hal_eth.c - ST Internal Reference: 157129 - *Fix to remove PAGESIZE definition which conflicts with POSIX Impacted files: drivers/include/Legacy/stm32_hal_legacy.h - *include STM32Cube patch in stm32h7xx_hal_ospi.c: - [HAL][OSPI] Fix wrong parameters passed to HAL_MDMA_Start_IT function - - *include STM32Cube patch in stm32h7xx_ll_delayblock.c: - [LL][DELAYBLOCK] Add a missing define for OSPI to the defgroup DELAYB… - See release_note.html from STM32Cube diff --git a/stm32cube/stm32h7xx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32h7xx/drivers/include/Legacy/stm32_hal_legacy.h index 2013593cd..07a7c67ae 100644 --- a/stm32cube/stm32h7xx/drivers/include/Legacy/stm32_hal_legacy.h +++ b/stm32cube/stm32h7xx/drivers/include/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) /* #define PAGESIZE FLASH_PAGE_SIZE */ +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -806,6 +817,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -860,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -997,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1249,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1264,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1817,7 +1847,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1999,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -2731,6 +2761,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3659,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3910,7 +3946,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4204,6 +4241,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal.h index c3760b173..222a4e9d2 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal.h @@ -59,8 +59,14 @@ typedef enum * @{ */ #define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */ +#define REV_ID_Z ((uint32_t)0x1001) /*!< STM32H7 rev.Z */ +#define REV_ID_A ((uint32_t)0x1000) /*!< STM32H7 rev.A */ #define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */ +#if (STM32H7_DEV_ID == 0x450UL) #define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */ +#else +#define REV_ID_X ((uint32_t)0x1007) /*!< STM32H7 rev.X */ +#endif /* STM32H7_DEV_ID */ #define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */ /** diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc.h index 861324a38..7cde9f1e7 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc.h @@ -1962,7 +1962,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pDa HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); @@ -1990,8 +1990,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc_ex.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc_ex.h index 2da227fa9..d2900314b 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc_ex.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc_ex.h @@ -1011,6 +1011,80 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15) ) +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input for ADC1. + * @param __CHANNEL__: programmed ADC channel. + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) ? ADC_CHANNEL_0 : \ + ((__CHANNEL__) == ADC_CHANNEL_2) ? ADC_CHANNEL_6 : \ + ((__CHANNEL__) == ADC_CHANNEL_3) ? ADC_CHANNEL_7 : \ + ((__CHANNEL__) == ADC_CHANNEL_4) ? ADC_CHANNEL_8 : \ + ((__CHANNEL__) == ADC_CHANNEL_5) ? ADC_CHANNEL_9 : \ + ((__CHANNEL__) == ADC_CHANNEL_10) ? ADC_CHANNEL_11 : \ + ((__CHANNEL__) == ADC_CHANNEL_11) ? ADC_CHANNEL_12 : \ + ((__CHANNEL__) == ADC_CHANNEL_12) ? ADC_CHANNEL_13 : \ + ((__CHANNEL__) == ADC_CHANNEL_16) ? ADC_CHANNEL_17 : \ + ((__CHANNEL__) == ADC_CHANNEL_18) ? ADC_CHANNEL_19 : 0UL) + +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input for ADC2. + * @param __CHANNEL__: programmed ADC channel. + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) ? ADC_CHANNEL_0 : \ + ((__CHANNEL__) == ADC_CHANNEL_2) ? ADC_CHANNEL_6 : \ + ((__CHANNEL__) == ADC_CHANNEL_3) ? ADC_CHANNEL_7 : \ + ((__CHANNEL__) == ADC_CHANNEL_4) ? ADC_CHANNEL_8 : \ + ((__CHANNEL__) == ADC_CHANNEL_5) ? ADC_CHANNEL_9 : \ + ((__CHANNEL__) == ADC_CHANNEL_10) ? ADC_CHANNEL_11 : \ + ((__CHANNEL__) == ADC_CHANNEL_11) ? ADC_CHANNEL_12 : \ + ((__CHANNEL__) == ADC_CHANNEL_12) ? ADC_CHANNEL_13 : \ + ((__CHANNEL__) == ADC_CHANNEL_18) ? ADC_CHANNEL_19 : 0UL) + +#if defined(ADC_VER_V5_V90) +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input for ADC3. + * @param __CHANNEL__: programmed ADC channel. + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT_ADC3(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) ? ADC_CHANNEL_0 : \ + ((__CHANNEL__) == ADC_CHANNEL_2) ? ADC_CHANNEL_6 : \ + ((__CHANNEL__) == ADC_CHANNEL_3) ? ADC_CHANNEL_7 : \ + ((__CHANNEL__) == ADC_CHANNEL_4) ? ADC_CHANNEL_8 : \ + ((__CHANNEL__) == ADC_CHANNEL_5) ? ADC_CHANNEL_9 : \ + ((__CHANNEL__) == ADC_CHANNEL_10) ? ADC_CHANNEL_11 : \ + ((__CHANNEL__) == ADC_CHANNEL_11) ? ADC_CHANNEL_12 : \ + ((__CHANNEL__) == ADC_CHANNEL_13) ? ADC_CHANNEL_14 : \ + ((__CHANNEL__) == ADC_CHANNEL_14) ? ADC_CHANNEL_15 : 0UL) +#endif /* ADC_VER_V5_V90 */ + +#if defined(ADC_VER_V5_V90) +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input on the ADC instance selected. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ This parameter can be one of the following values: + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) : \ + (((__HANDLE__)->Instance) == ADC2) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) : \ + (((__HANDLE__)->Instance) == ADC3) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC3(__CHANNEL__) : 0UL) +#else +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input on the ADC instance selected. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ This parameter can be one of the following values: + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) : \ + (((__HANDLE__)->Instance) == ADC2) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) : 0UL) +#endif /* ADC_VER_V5_V90 */ + /** * @brief Verify the ADC single-ended input or differential mode setting. * @param __SING_DIFF__ programmed channel setting. @@ -1311,7 +1385,7 @@ typedef struct /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff); -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff); HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); @@ -1328,12 +1402,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); /* ADC multimode */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_comp.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_comp.h index 9d16f6aad..83265b014 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_comp.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_comp.h @@ -915,7 +915,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); * @{ */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp); /* Callback in Interrupt mode */ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @@ -926,8 +926,8 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @addtogroup COMP_Exported_Functions_Group4 * @{ */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp); /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_conf.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_conf.h index 36ed9cac7..54fcc2d9f 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_conf.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_conf.h @@ -84,6 +84,7 @@ #define HAL_RTC_MODULE_ENABLED #define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED +#define HAL_SDIO_MODULE_ENABLED #define HAL_SDRAM_MODULE_ENABLED #define HAL_SMARTCARD_MODULE_ENABLED #define HAL_SMBUS_MODULE_ENABLED @@ -168,6 +169,8 @@ #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ #define USE_SPI_CRC 1U /*!< use CRC in SPI */ #define USE_FLASH_ECC 0U /*!< use ECC error management in FLASH */ +#define USE_SDIO_TRANSCEIVER 0U /*!< use SDIO Transceiver */ +#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */ #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ @@ -208,6 +211,7 @@ #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ #define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ #define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ #define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ @@ -438,6 +442,10 @@ #include "stm32h7xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32h7xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32h7xx_hal_sdram.h" #endif /* HAL_SDRAM_MODULE_ENABLED */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cordic.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cordic.h index 0aa08c431..28949bede 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cordic.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cordic.h @@ -149,7 +149,6 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants * @{ @@ -166,6 +165,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + /** * @} */ @@ -183,6 +183,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */ #define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ #define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ + /** * @} */ @@ -212,6 +213,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ |CORDIC_CSR_PRECISION_0)) + /** * @} */ @@ -229,6 +231,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0)) #define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1)) #define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) + /** * @} */ @@ -237,6 +240,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */ + /** * @} */ @@ -245,6 +249,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */ + /** * @} */ @@ -253,6 +258,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */ + /** * @} */ @@ -288,6 +294,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */ #define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */ + /** * @} */ @@ -297,6 +304,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */ #define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */ + /** * @} */ @@ -305,6 +313,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */ + /** * @} */ @@ -316,6 +325,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */ #define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */ #define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */ + /** * @} */ @@ -336,9 +346,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET) @@ -416,7 +426,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ -/* Private macros --------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /** @defgroup CORDIC_Private_Macros CORDIC Private Macros * @{ */ @@ -584,6 +594,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); /* Peripheral State functions *************************************************/ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); + /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cortex.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cortex.h index 134fc483f..cc4c24c75 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cortex.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cortex.h @@ -309,7 +309,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); void HAL_MPU_EnableRegion(uint32_t RegionNumber); void HAL_MPU_DisableRegion(uint32_t RegionNumber); -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ uint32_t HAL_NVIC_GetPriorityGrouping(void); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp.h index a6802ed6b..59bf9cd5a 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp.h @@ -454,11 +454,11 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu */ /* Interrupt Handler functions **********************************************/ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp); void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); -uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); +uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp); /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp_ex.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp_ex.h index 8820e0b7a..3c193cde8 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp_ex.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp_ex.h @@ -91,8 +91,8 @@ extern "C" { /** @addtogroup CRYPEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout); /** diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dac.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dac.h index 65e5fd938..90590387b 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dac.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dac.h @@ -286,10 +286,13 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) -#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) -#define DAC_CHIPCONNECT_BOTH (1UL << 2) - +#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/ +#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. */ +#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. + Note: this connection is not available in mode normal + with buffer disabled. */ /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dcmi.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dcmi.h index a21afc09d..672d5de0f 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dcmi.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dcmi.h @@ -569,8 +569,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_ * @{ */ /* Peripheral State functions *************************************************/ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi); -uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi); +uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi); /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma.h index 82f6f215e..59ad97a8f 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma.h @@ -1211,8 +1211,8 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca * @brief Peripheral State functions * @{ */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma); /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma2d.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma2d.h index 00f205bc0..dd32a99b2 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma2d.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma2d.h @@ -511,9 +511,9 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); @@ -550,8 +550,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t */ /* Peripheral State functions ***************************************************/ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d); +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d); /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dts.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dts.h index f9bff1703..3bb262faf 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dts.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dts.h @@ -423,7 +423,7 @@ HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Tempe HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts); HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts); void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts); -HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts); +HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts); /* Callback in Interrupt mode */ void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts); void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_eth.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_eth.h index 726127ea6..b3d9eefbb 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_eth.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_eth.h @@ -105,7 +105,7 @@ typedef struct uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) ) +#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ + (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX)))) /** * @brief Verify the FMAC filter parameter R. diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gfxmmu.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gfxmmu.h index 9e93c2295..1a1e98498 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gfxmmu.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gfxmmu.h @@ -344,16 +344,16 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @{ */ /* Operation functions ********************************************************/ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address); -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber); -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam); @@ -373,7 +373,7 @@ void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu); * @{ */ /* State function *************************************************************/ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu); +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu); uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); /** diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gpio.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gpio.h index 1cd9178bb..e0b75b703 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gpio.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gpio.h @@ -252,7 +252,7 @@ typedef enum * @{ */ /* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** * @} @@ -262,7 +262,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); * @{ */ /* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash.h index 15b1213f1..54df4670a 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash.h @@ -117,13 +117,13 @@ typedef struct { HASH_InitTypeDef Init; /*!< HASH required parameters */ - uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ + uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ + uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ uint32_t HashBuffSize; /*!< Size of buffer to be processed */ @@ -476,15 +476,17 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS /* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); @@ -497,15 +499,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** @@ -517,9 +519,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); */ /* HASH processing using DMA *************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -531,9 +533,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu */ /* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -544,9 +548,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @{ */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -558,8 +562,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ /* HASH-HMAC processing using DMA ********************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -571,13 +575,13 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /* Peripheral State methods **************************************************/ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash); -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash); -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash); +HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash); +void HAL_HASH_ContextSaving(const HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer); +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer); void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash); /** * @} @@ -594,19 +598,27 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); */ /* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash_ex.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash_ex.h index 78fc650fc..2ac9297a9 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash_ex.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash_ex.h @@ -50,15 +50,15 @@ extern "C" { * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -69,15 +69,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer); /** @@ -87,9 +89,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin /** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -99,9 +101,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -111,9 +113,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -124,8 +126,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -135,20 +137,24 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); + +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); + +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hrtim.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hrtim.h index 7b709f3e7..a6841ada0 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hrtim.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hrtim.h @@ -21,7 +21,7 @@ #define STM32H7xx_HAL_HRTIM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -60,7 +60,7 @@ */ typedef struct { - uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. + uint32_t HRTIMInterruptRequests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */ uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals. The HRTIM instance can be configured to act as a slave (waiting for a trigger @@ -119,7 +119,7 @@ typedef struct __HRTIM_HandleTypeDef typedef struct #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ { - HRTIM_TypeDef * Instance; /*!< Register base address */ + HRTIM_TypeDef *Instance; /*!< Register base address */ HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */ @@ -129,12 +129,12 @@ typedef struct __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */ - DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */ + DMA_HandleTypeDef *hdmaMaster; /*!< Master timer DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerA; /*!< Timer A DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerB; /*!< Timer B DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerC; /*!< Timer C DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerD; /*!< Timer D DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerE; /*!< Timer E DMA handle parameters */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 1 interrupt callback function pointer */ @@ -481,7 +481,8 @@ typedef struct /** * @brief HAL HRTIM Callback ID enumeration definition */ -typedef enum { +typedef enum +{ HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /*!< Fault 1 interrupt callback ID */ HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /*!< Fault 2 interrupt callback ID */ HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /*!< Fault 3 interrupt callback ID */ @@ -510,7 +511,7 @@ typedef enum { HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /*!< HRTIM MspInit callback ID */ HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /*!< HRTIM MspInit callback ID */ -}HAL_HRTIM_CallbackIDTypeDef; +} HAL_HRTIM_CallbackIDTypeDef; /** * @brief HAL HRTIM Callback function pointer definitions @@ -556,8 +557,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */ #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */ /** - * @} - */ + * @} + */ /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit * @{ @@ -567,9 +568,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */ #define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */ #define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit * @{ @@ -609,10 +610,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */ #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ - (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) + (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) /** * @} */ @@ -649,10 +650,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ - /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio +/** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio * @{ * @brief Constants defining timer high-resolution clock prescaler ratio. - */ + */ #define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ @@ -934,9 +935,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */ #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ - (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) + (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) /** * @} */ @@ -1040,9 +1041,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level * @{ @@ -1267,9 +1268,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle * @{ @@ -1804,8 +1805,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Force the output to its inactive state */ #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ - (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ - ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) + (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ + ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) /** * @} */ @@ -1999,169 +2000,169 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @} */ - /* Private macros --------------------------------------------------------*/ +/* Private macros --------------------------------------------------------*/ /** @addtogroup HRTIM_Private_Macros * @{ */ #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) + (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) + (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U) #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) + (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ - (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ - ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) + (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ + ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U) #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ - ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TE2)))) + ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ + (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ + (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ + (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ + (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ + (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TE2)))) #define IS_HRTIM_EVENT(EVENT)\ - (((EVENT) == HRTIM_EVENT_NONE)|| \ - ((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5) || \ - ((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) + (((EVENT) == HRTIM_EVENT_NONE)|| \ + ((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5) || \ + ((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10)) #define IS_HRTIM_FAULT(FAULT)\ - (((FAULT) == HRTIM_FAULT_1) || \ - ((FAULT) == HRTIM_FAULT_2) || \ - ((FAULT) == HRTIM_FAULT_3) || \ - ((FAULT) == HRTIM_FAULT_4) || \ - ((FAULT) == HRTIM_FAULT_5)) + (((FAULT) == HRTIM_FAULT_1) || \ + ((FAULT) == HRTIM_FAULT_2) || \ + ((FAULT) == HRTIM_FAULT_3) || \ + ((FAULT) == HRTIM_FAULT_4) || \ + ((FAULT) == HRTIM_FAULT_5)) #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) + (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) #define IS_HRTIM_MODE(MODE)\ - (((MODE) == HRTIM_MODE_CONTINUOUS) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) + (((MODE) == HRTIM_MODE_CONTINUOUS) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) #define IS_HRTIM_MODE_ONEPULSE(MODE)\ - (((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) + (((MODE) == HRTIM_MODE_SINGLESHOT) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) #define IS_HRTIM_HALFMODE(HALFMODE)\ - (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ - ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) + (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ + ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) #define IS_HRTIM_SYNCSTART(SYNCSTART)\ - (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ - ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) + (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ + ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) #define IS_HRTIM_SYNCRESET(SYNCRESET)\ - (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ - ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) + (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ + ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) #define IS_HRTIM_DACSYNC(DACSYNC)\ - (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) + (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) #define IS_HRTIM_PRELOAD(PRELOAD)\ - (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ - ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) + (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ + ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) + (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) + (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) #define IS_HRTIM_TIMERBURSTMODE(MODE) \ - (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ - ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) + (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ + ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ - (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ - ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) + (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ + ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ - ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ + ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U) #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ - (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ - ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) + (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ + ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\ - ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ - ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ - ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ - || \ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ - ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) + ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ + ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ + ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ + || \ + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ + ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\ - ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ - || \ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ - (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) + ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ + || \ + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ + (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U) @@ -2169,128 +2170,128 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ - (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ - ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) + (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ + ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) /* Auto delayed mode is only available for compare units 2 and 4U */ #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \ - ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ - || \ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) + ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ + || \ + (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\ - (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ - ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) + (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ + ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU) #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ - (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) + (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ - (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) + (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ - (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ - ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) + (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ + ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\ - (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ - ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) + (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ + ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\ - (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) + (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\ - (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ - ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) + (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ + ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\ - (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ - ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) + (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ + ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \ @@ -2304,420 +2305,420 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \ || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\ - (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) + (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ - (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ - ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) + (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ + ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) + (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ - (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ - ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) + (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ + ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ - (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ - ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) + (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ + ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\ - (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ - ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) + (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ + ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\ - (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ - ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) + (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ + ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\ - (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ - ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) + (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ + ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\ - (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ - ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) + (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ + ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) + (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\ - (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) + (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\ - (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) + (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\ - (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) + (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ + ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ + ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\ - (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) + (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\ - (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) + (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ + ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ + ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) #define IS_HRTIM_EVENTSRC(EVENTSRC)\ - (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_4)) + (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_4)) #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\ - ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ - (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ - ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ - || \ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) + ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ + (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ + ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ + || \ + (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) + (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\ - (((((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) && \ - (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ - ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ - || \ - (((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10))) + (((((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5)) && \ + (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ + ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ + || \ + (((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10))) #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\ - ((((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) \ - || \ - ((((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) && \ - (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ - ((FILTER) == HRTIM_EVENTFILTER_1) || \ - ((FILTER) == HRTIM_EVENTFILTER_2) || \ - ((FILTER) == HRTIM_EVENTFILTER_3) || \ - ((FILTER) == HRTIM_EVENTFILTER_4) || \ - ((FILTER) == HRTIM_EVENTFILTER_5) || \ - ((FILTER) == HRTIM_EVENTFILTER_6) || \ - ((FILTER) == HRTIM_EVENTFILTER_7) || \ - ((FILTER) == HRTIM_EVENTFILTER_8) || \ - ((FILTER) == HRTIM_EVENTFILTER_9) || \ - ((FILTER) == HRTIM_EVENTFILTER_10) || \ - ((FILTER) == HRTIM_EVENTFILTER_11) || \ - ((FILTER) == HRTIM_EVENTFILTER_12) || \ - ((FILTER) == HRTIM_EVENTFILTER_13) || \ - ((FILTER) == HRTIM_EVENTFILTER_14) || \ - ((FILTER) == HRTIM_EVENTFILTER_15)))) + ((((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5)) \ + || \ + ((((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10)) && \ + (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ + ((FILTER) == HRTIM_EVENTFILTER_1) || \ + ((FILTER) == HRTIM_EVENTFILTER_2) || \ + ((FILTER) == HRTIM_EVENTFILTER_3) || \ + ((FILTER) == HRTIM_EVENTFILTER_4) || \ + ((FILTER) == HRTIM_EVENTFILTER_5) || \ + ((FILTER) == HRTIM_EVENTFILTER_6) || \ + ((FILTER) == HRTIM_EVENTFILTER_7) || \ + ((FILTER) == HRTIM_EVENTFILTER_8) || \ + ((FILTER) == HRTIM_EVENTFILTER_9) || \ + ((FILTER) == HRTIM_EVENTFILTER_10) || \ + ((FILTER) == HRTIM_EVENTFILTER_11) || \ + ((FILTER) == HRTIM_EVENTFILTER_12) || \ + ((FILTER) == HRTIM_EVENTFILTER_13) || \ + ((FILTER) == HRTIM_EVENTFILTER_14) || \ + ((FILTER) == HRTIM_EVENTFILTER_15)))) #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ - (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) + (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ - (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ - ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) + (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ + ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ - (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ - ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) + (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ + ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ - (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ - ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) + (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ + ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ - (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) + (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\ - (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ - ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) + (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ + ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\ - (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) + (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) #define IS_HRTIM_BURSTMODE(BURSTMODE)\ - (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ - ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) + (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ + ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\ - (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) + (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\ - (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) + (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\ - (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ - ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) + (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ + ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\ - (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) + (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\ - (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) + (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ - (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) + (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ - ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) + ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ - (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ - ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) + (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ + ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U) @@ -2750,10 +2751,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET) #endif @@ -2782,44 +2783,44 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\ do {\ if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ - }\ + {\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ }\ + }\ } while(0U) @@ -2852,8 +2853,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable * @retval None */ -#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__)) -#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ + |= (__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ + &= ~(__INTERRUPT__)) /** @brief Enables or disables the specified HRTIM Timerx interrupts. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2892,7 +2895,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2907,7 +2911,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2937,7 +2942,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clears the specified HRTIM common pending flag. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2967,7 +2973,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag * @retval None */ -#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR\ + = (__INTERRUPT__)) /** @brief Clears the specified HRTIM Timerx pending flag. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2990,7 +2997,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag * @retval None */ -#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__)) +#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ + = (__INTERRUPT__)) /* DMA HANDLING */ /** @brief Enables or disables the specified HRTIM Master timer DMA requests. @@ -3033,14 +3041,18 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__)) #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__)) -#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR &\ + (__FLAG__)) == (__FLAG__)) #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__)) -#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR &\ + (__FLAG__)) == (__FLAG__)) #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__)) -#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__)) -#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__)) +#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR &\ + (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ + = (__FLAG__)) /** @brief Sets the HRTIM timer Counter Register value on runtime * @param __HANDLE__ HRTIM Handle. @@ -3136,16 +3148,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @retval None */ #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \ - (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ - : \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) + (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ + : \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) /** @brief Gets the HRTIM timer Compare Register value on runtime * @param __HANDLE__ HRTIM Handle. @@ -3161,16 +3173,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @retval Compare value */ #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \ - (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ - ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ - : \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ - ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) + (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ + ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ + : \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ + ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) /** * @} @@ -3178,17 +3190,17 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< /* Exported functions --------------------------------------------------------*/ /** @addtogroup HRTIM_Exported_Functions -* @{ -*/ + * @{ + */ /** @addtogroup HRTIM_Exported_Functions_Group1 -* @{ -*/ + * @{ + */ /* Initialization and Configuration functions ********************************/ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim); -HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim); +HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim); void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim); @@ -3196,244 +3208,244 @@ void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group2 -* @{ -*/ + * @{ + */ /* Simple time base related functions *****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group3 -* @{ -*/ + * @{ + */ /* Simple output compare related functions ************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); + uint32_t TimerIdx, + uint32_t OCChannel, + const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t OCChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group4 -* @{ -*/ + * @{ + */ /* Simple PWM output related functions ****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); + uint32_t TimerIdx, + uint32_t PWMChannel, + const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t PWMChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group5 -* @{ -*/ + * @{ + */ /* Simple capture related functions *******************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); + uint32_t TimerIdx, + uint32_t CaptureChannel, + const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t CaptureChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group6 -* @{ -*/ + * @{ + */ /* Simple one pulse related functions *****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); + uint32_t TimerIdx, + uint32_t OnePulseChannel, + const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group7 -* @{ -*/ + * @{ + */ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, - const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); + const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg); HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef* pEventCfg); + const HRTIM_EventCfgTypeDef *pEventCfg); HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultCfgTypeDef* pFaultCfg); + const HRTIM_FaultCfgTypeDef *pFaultCfg); HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); -void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, +void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, uint32_t Faults, uint32_t Enable); HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); + const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group8 -* @{ -*/ + * @{ + */ /* Waveform related functions *************************************************/ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef *pTimerCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - const HRTIM_CompareCfgTypeDef* pCompareCfg); + const HRTIM_CompareCfgTypeDef *pCompareCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - const HRTIM_CaptureCfgTypeDef* pCaptureCfg); + const HRTIM_CaptureCfgTypeDef *pCaptureCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg); + const HRTIM_OutputCfgTypeDef *pOutputCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3443,15 +3455,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); + const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg); HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); + const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg); HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); + const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg); HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3459,22 +3471,22 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart); @@ -3503,7 +3515,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, uint32_t BurstBufferLength); HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); @@ -3513,12 +3525,12 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group9 -* @{ -*/ + * @{ + */ /* HRTIM peripheral state functions */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim); +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim); -uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit); @@ -3526,7 +3538,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); -uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); @@ -3547,8 +3559,8 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group10 -* @{ -*/ + * @{ + */ /* IRQ handler */ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); @@ -3565,50 +3577,50 @@ void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim); /* Timer events related callback functions */ void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim); #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_TIMxCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_i2s.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_i2s.h index 407bf2ccb..40f321f8e 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_i2s.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_i2s.h @@ -505,6 +505,11 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); +/* IO Swap feature */ +HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s); + /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ltdc.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ltdc.h index d5b4a665b..a72e42f9f 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ltdc.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ltdc.h @@ -592,7 +592,8 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); @@ -625,8 +626,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 * @{ */ /* Peripheral State functions *************************************************/ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc); /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdios.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdios.h index 50c61f41d..fecf9fe2a 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdios.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdios.h @@ -509,8 +509,8 @@ HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_ HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data); HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData); -uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios); -uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetWrittenRegAddress(const MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetReadRegAddress(const MDIOS_HandleTypeDef *hmdios); HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); @@ -527,8 +527,8 @@ void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios); /** @addtogroup MDIOS_Exported_Functions_Group3 * @{ */ -uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios); -HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetError(const MDIOS_HandleTypeDef *hmdios); +HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(const MDIOS_HandleTypeDef *hmdios); /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdma.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdma.h index a39cc0d75..fb6117864 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdma.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdma.h @@ -655,7 +655,7 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM */ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig); -HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode); +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, const MDMA_LinkNodeTypeDef *pPrevNode); HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode); HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma); HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma); @@ -687,8 +687,8 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma); * @brief Peripheral State functions * @{ */ -HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma); -uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(const MDMA_HandleTypeDef *hmdma); +uint32_t HAL_MDMA_GetError(const MDMA_HandleTypeDef *hmdma); /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc.h index ed4e5e5ad..3b242bae0 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc.h @@ -30,6 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup MMC * @{ @@ -121,7 +122,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< MMC locking object */ - const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ uint32_t TxXferSize; /*!< MMC Tx Transfer size */ @@ -135,6 +136,8 @@ typedef struct __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ + __IO uint16_t RPMBErrorCode; /*!< MMC RPMB Area Error codes */ + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ uint32_t CSD[4U]; /*!< MMC card specific data table */ @@ -276,45 +279,55 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); /** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition * @{ */ -#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ -#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ -#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ -#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ -#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ -#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ -#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ -#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ -#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ +#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ /*!< number of transferred bytes does not match the block length */ -#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ -#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ -#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ -#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ +#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ /*!< command or if there was an attempt to access a locked card */ -#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ -#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ -#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ -#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ -#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ -#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ -#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ -#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ -#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ -#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ -#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ +#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ /*!< of erase sequence command was received */ -#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ -#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ -#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ -#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ -#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ -#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ -#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ -#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ -#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +/*!< response results after operating with RPMB partition */ +#define HAL_MMC_ERROR_RPMB_OPERATION_OK 0x0000U /*!< Operation OK */ +#define HAL_MMC_ERROR_RPMB_GENERAL_FAILURE 0x0001U /*!< General failure */ +#define HAL_MMC_ERROR_RPMB_AUTHENTICATION_FAILURE 0x0002U /*!< Authentication failure */ +#define HAL_MMC_ERROR_RPMB_COUNTER_FAILURE 0x0003U /*!< Counter failure */ +#define HAL_MMC_ERROR_RPMB_ADDRESS_FAILURE 0x0004U /*!< Address failure */ +#define HAL_MMC_ERROR_RPMB_WRITE_FAILURE 0x0005U /*!< Write failure */ +#define HAL_MMC_ERROR_RPMB_READ_FAILURE 0x0006U /*!< Read failure */ +#define HAL_MMC_ERROR_RPMB_KEY_NOT_YET_PROG 0x0007U /*!< Authentication Key not yet programmed */ +#define HAL_MMC_ERROR_RPMB_COUNTER_EXPIRED 0x0080U /*!< Write Counter has expired i.e. reached its max value */ #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) -#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @} @@ -399,6 +412,19 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); * @} */ +/** @defgroup MMC_Exported_Constansts_Group7 MMC Partitions types + * @{ + */ +typedef uint32_t HAL_MMC_PartitionTypeDef; + +#define HAL_MMC_USER_AREA_PARTITION 0x00000000U /*!< User area partition */ +#define HAL_MMC_BOOT_PARTITION1 0x00000100U /*!< Boot partition 1 */ +#define HAL_MMC_BOOT_PARTITION2 0x00000200U /*!< Boot partition 2 */ +#define HAL_MMC_RPMB_PARTITION 0x00000300U /*!< RPMB partition */ +/** + * @} + */ + /** * @} */ @@ -686,6 +712,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca */ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode); +HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition); /** * @} */ @@ -694,9 +721,9 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 * @{ */ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); /** * @} @@ -705,8 +732,9 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC /** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions * @{ */ -HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc); -uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); +HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetRPMBError(const MMC_HandleTypeDef *hmmc); /** * @} */ @@ -740,6 +768,29 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); /** * @} */ + +/** @defgroup MMC_Exported_Functions_Group9 Replay Protected Memory Block management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, + uint32_t Timeout); +uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout); +uint32_t HAL_MMC_RPMB_GetWriteCounter_IT(MMC_HandleTypeDef *hmmc, uint8_t *pNonce); +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC); +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC, + uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC); + +/** + * @} + */ + /* Private types -------------------------------------------------------------*/ /** @defgroup MMC_Private_Types MMC Private Types * @{ @@ -812,6 +863,7 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc_ex.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc_ex.h index 215749583..c610a2bdf 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc_ex.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc_ex.h @@ -30,7 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ - +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup MMCEx * @brief SD HAL extended module driver * @{ @@ -100,6 +100,7 @@ void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_nand.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_nand.h index 7290893bd..b0b31b91b 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_nand.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_nand.h @@ -193,7 +193,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig); HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_opamp.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_opamp.h index ef354861f..cac094840 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_opamp.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_opamp.h @@ -417,7 +417,7 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_O HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId); #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); -HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); +HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (const OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); /** * @} @@ -428,7 +428,7 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop */ /* Peripheral State functions **************************************************/ -HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp); +HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(const OPAMP_HandleTypeDef *hopamp); /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_otfdec.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_otfdec.h index bfdfb0b45..9aa5e3ab6 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_otfdec.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_otfdec.h @@ -342,8 +342,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32 HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode); HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, - OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); -uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey); + const OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); +uint32_t HAL_OTFDEC_KeyCRCComputation(const uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); /** @@ -353,8 +353,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32 /** @addtogroup @addtogroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions * @{ */ -HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec); -uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); +HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(const OTFDEC_HandleTypeDef *hotfdec); +uint32_t HAL_OTFDEC_RegionGetKeyCRC(const OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config); /** diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pcd_ex.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pcd_ex.h index 9cfa0125e..221e2af37 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pcd_ex.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pcd_ex.h @@ -45,7 +45,6 @@ extern "C" { /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr.h index 91a905409..c1d722236 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr.h @@ -692,7 +692,7 @@ void HAL_PWR_DisableBkUpAccess (void); */ /* Peripheral Control functions **********************************************/ /* PVD configuration */ -void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_ConfigPVD (const PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_EnablePVD (void); void HAL_PWR_DisablePVD (void); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr_ex.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr_ex.h index 61c76092c..e8455d8d2 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr_ex.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr_ex.h @@ -544,7 +544,7 @@ void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock); void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock); #endif /* defined(PWR_CR1_SRDRAMSO) */ /* Wakeup Pins control functions */ -void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams); +void HAL_PWREx_EnableWakeUpPin (const PWREx_WakeupPinTypeDef *sPinParams); void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin); uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag); HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag); @@ -599,7 +599,7 @@ uint32_t HAL_PWREx_GetVBATLevel (void); PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void); #endif /* PWR_CSR1_MMCVDO */ /* Power AVD configuration functions */ -void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD); +void HAL_PWREx_ConfigAVD (const PWREx_AVDTypeDef *sConfigAVD); void HAL_PWREx_EnableAVD (void); void HAL_PWREx_DisableAVD (void); /* Power PVD/AVD IRQ Handler */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_qspi.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_qspi.h index 98b2c5cf1..321f05f52 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_qspi.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_qspi.h @@ -26,6 +26,9 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" +#if defined (DLYB_QUADSPI) +#include "stm32h7xx_ll_delayblock.h" +#endif /* DLYB_QUADSPI */ #if defined(QUADSPI) diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ramecc.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ramecc.h index f9444ebc8..b681c8dee 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ramecc.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ramecc.h @@ -303,12 +303,12 @@ HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc); * @brief Error information functions * @{ */ -uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingAddress(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingDataLow(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingDataHigh(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetHammingErrorCode(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_IsECCSingleErrorDetected(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(const RAMECC_HandleTypeDef *hramecc); /** * @} */ @@ -317,9 +317,9 @@ uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc); * @brief State and Error Functions * @{ */ -HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetRAMECCError(RAMECC_HandleTypeDef *hramecc); +HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetError(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetRAMECCError(const RAMECC_HandleTypeDef *hramecc); /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc.h index 1626c6d05..564a8a09f 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc.h @@ -7968,7 +7968,7 @@ typedef struct /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc_ex.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc_ex.h index 2fb1fd290..d39df84c7 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc_ex.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc_ex.h @@ -3936,7 +3936,7 @@ void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx); * @{ */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit); void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng.h index e7dd55a1e..409ac73bd 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng.h @@ -178,6 +178,9 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#if defined(RNG_CR_CONDRST) +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ +#endif /* RNG_CR_CONDRST */ /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng_ex.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng_ex.h index ee43ec107..05c83d073 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng_ex.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,9 +55,9 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ } RNG_ConfigTypeDef; /** @@ -65,11 +65,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -108,7 +108,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -123,7 +123,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -132,7 +132,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -141,7 +141,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -150,7 +150,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -187,7 +187,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -196,11 +196,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -211,7 +211,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc.h index ad0fa135f..301982631 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc.h @@ -935,9 +935,9 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca */ /* RTC Time and Date functions ************************************************/ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); /** * @} */ @@ -949,7 +949,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); @@ -970,7 +970,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); * @{ */ /* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc); /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc_ex.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc_ex.h index bb29abe86..61845fff6 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc_ex.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc_ex.h @@ -1658,8 +1658,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions * @{ */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); @@ -1668,8 +1668,8 @@ void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); #if defined(TAMP) -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper); HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout); void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc); @@ -1679,8 +1679,8 @@ void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper); -HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed); +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper); +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed); HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc); #endif /* TAMP */ @@ -1700,7 +1700,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); @@ -1717,8 +1717,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions * @{ */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +void HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); /** * @} */ @@ -1742,7 +1742,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); #if defined(TAMP) HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance); -HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance); #endif /* TAMP */ /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd.h index 83fa74fde..a2536da2d 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd.h @@ -33,6 +33,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @defgroup SD SD * @brief SD HAL module driver @@ -315,12 +316,12 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ #define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ #define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ - /*!< number of transferred bytes does not match the block length */ +/*!< number of transferred bytes does not match the block length */ #define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ #define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ #define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ #define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ - /*!< command or if there was an attempt to access a locked card */ +/*!< command or if there was an attempt to access a locked card */ #define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ #define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ #define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ @@ -332,7 +333,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ #define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ #define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ - /*!< of erase sequence command was received */ +/*!< of erase sequence command was received */ #define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ #define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ #define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ @@ -690,10 +691,10 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t * @{ */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ @@ -701,8 +702,8 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInf /** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions * @{ */ -HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd); -uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); +HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd); +uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd); /** * @} */ @@ -787,6 +788,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd_ex.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd_ex.h index 450e7dfad..050005b0e 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd_ex.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd_ex.h @@ -30,6 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup SDEx * @brief SD HAL extended module driver @@ -98,6 +99,7 @@ void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdio.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdio.h new file mode 100644 index 000000000..77cb250eb --- /dev/null +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdio.h @@ -0,0 +1,600 @@ +/** + ********************************************************************************************************************** + * @file stm32h7xx_hal_sdio.h + * @author MCD Application Team + * @brief Header file of SDIO HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32H7xx_HAL_SDIO_H +#define STM32H7xx_HAL_SDIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7xx_ll_sdmmc.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ +#if defined (SDMMC1) || defined (SDMMC2) + +/** @defgroup SDIO SDIO + * @brief SDIO HAL module driver + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Types SDIO Exported Types + * @{ + */ + +/** @defgroup SDIO_Exported_Types_Group1 SDIO State enumeration structure + * @{ + + */ +typedef enum +{ + HAL_SDIO_STATE_RESET = 0x00U, /*!< SDIO not yet initialized or disabled */ + HAL_SDIO_STATE_READY = 0x01U, /*!< SDIO initialized and ready for us */ + HAL_SDIO_STATE_BUSY = 0x02U, /*!< SDIO process ongoing */ +} HAL_SDIO_StateTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Types_Group2 SDIO Handle and Structure definition + * @{ + */ +/** + * @brief SDIO Card Common Control Register Structure definition + */ +typedef struct +{ + uint8_t sdio_revision; /*!< SDIO revision */ + uint8_t cccr_revision; /*!< CCCR version */ + uint8_t sd_spec_revision; /*!< SD revision */ + uint8_t bus_width_8Bit; /*!< SDIO bus width 8 bit support */ + uint32_t card_capability; /*!< SDIO card capability */ + uint32_t commonCISPointer; /*!< point to common CIS */ +} HAL_SDIO_CCCR_TypeDef; + +/** + * @brief sdio card FBR register(Function Basic Register) + */ +typedef struct +{ + uint8_t flags; /*!< SDIO current IO flags */ + uint8_t ioStdFunctionCode; /*!< SDIO current IO standard function code */ + uint8_t ioExtFunctionCode; /*!< SDIO current IO extended function code */ + uint32_t ioPointerToCIS; /*!< SDIO current IO pointer to CIS */ + uint32_t ioPointerToCSA; /*!< SDIO current IO pointer to CSA */ +} HAL_SDIO_FBR_t; + +/** + * @brief SDIO CMD52 Structure definition + */ +typedef struct +{ + uint32_t Reg_Addr; /*!< This is the address of the byte of data inside of the selected function to read or write */ + uint8_t ReadAfterWrite; /*!< This is the read after write flag, it is used for write access only. */ + uint8_t IOFunctionNbr; /*!< The number of the function within the IO card you wish to read or write */ +} HAL_SDIO_DirectCmd_TypeDef; + +/** + * @brief SDIO CMD53 Structure definition + */ +typedef struct +{ + uint32_t Reg_Addr; /*!< This is the address of the byte of data inside of the selected function to read or write */ + uint32_t OpCode; /*!< Read/Write operation mode */ + uint32_t Block_Mode; /*!< Bytes or Blocks mode */ + uint32_t IOFunctionNbr; /*!< The number of the function within the IO card you wish to read or write */ +} HAL_SDIO_ExtendedCmd_TypeDef; + +#define SDIO_InitTypeDef SDMMC_InitTypeDef +#define SDIO_TypeDef SDMMC_TypeDef + +/** + * @brief SDIO handle Structure definition + */ +typedef struct __SDIO_HandleTypeDef +{ + SDIO_TypeDef *Instance; /*!< SDIO registers base address */ + + SDIO_InitTypeDef Init; /*!< SDIO required parameters */ + + HAL_LockTypeDef Lock; /*!< SDIO locking object */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SDIO Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< SDIO Tx Transfer size */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SDIO Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< SDIO Rx Transfer size */ + + uint32_t remaining_data; /*!< Remaining data to transfer */ + + uint32_t next_data_addr; /*!< SDIO Next data address */ + + __IO uint32_t next_reg_addr; /*!< SDIO Next register address */ + + uint16_t block_size; /*!< SDIO Block size */ + + __IO uint32_t Context; /*!< SDIO transfer context */ + + __IO HAL_SDIO_StateTypeDef State; /*!< SDIO card State */ + + __IO uint32_t ErrorCode; /*!< SDIO Card Error codes */ + + uint8_t IOFunctionMask; /*!< SDIO used to record current enabled io interrupt */ + + volatile uint8_t IOInterruptNbr; /*!< SDIO used to record total enabled io interrupt numbers */ + + void (* SDIO_IOFunction_Callback[SDIO_MAX_IO_NUMBER])(struct __SDIO_HandleTypeDef *hsdio, uint32_t func); + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* RxCpltCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* ErrorCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* MspInitCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* MspDeInitCallback)(struct __SDIO_HandleTypeDef *hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) + void (* DriveTransceiver_1_8V_Callback)(struct __SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + + HAL_StatusTypeDef(* SDIO_IdentifyCard)(struct __SDIO_HandleTypeDef *hsdio); + +} SDIO_HandleTypeDef; + +/** + * @} + */ +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) +/** @defgroup SDIO_Exported_Types_Group3 SDIO Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_SDIO_TX_CPLT_CB_ID = 0x00U, /*!< SDIO Tx Complete Callback ID */ + HAL_SDIO_RX_CPLT_CB_ID = 0x01U, /*!< SDIO Rx Complete Callback ID */ + HAL_SDIO_ERROR_CB_ID = 0x02U, /*!< SDIO Error Callback ID */ + HAL_SDIO_MSP_INIT_CB_ID = 0x10U, /*!< SDIO MspInit Callback ID */ + HAL_SDIO_MSP_DEINIT_CB_ID = 0x11U /*!< SDIO MspDeInit Callback ID */ +} HAL_SDIO_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup SDIO_Exported_Types_Group4 SDIO Callback pointer definition + * @{ + */ +typedef void (*pSDIO_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio); +/** + * @} + */ +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) +typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + +typedef HAL_StatusTypeDef(*pSDIO_IdentifyCardCallbackTypeDef)(SDIO_HandleTypeDef *hsdio); +typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, uint32_t func); +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Constants SDIO Exported Constants + * @{ + */ + +/** @defgroup SDIO_Exported_Constansts_Group1 SDIO Error status Structure definition + * @{ + */ +#define HAL_SDIO_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_SDIO_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_SDIO_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_SDIO_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_SDIO_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_SDIO_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +#define HAL_SDIO_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group2 SDIO context enumeration + * @{ + */ +#define SDIO_CONTEXT_NONE 0x00U /*!< None */ +#define SDIO_CONTEXT_READ_SINGLE_BLOCK 0x01U /*!< Read single block operation */ +#define SDIO_CONTEXT_READ_MULTIPLE_BLOCK 0x02U /*!< Read multiple blocks operation */ +#define SDIO_CONTEXT_WRITE_SINGLE_BLOCK 0x10U /*!< Write single block operation */ +#define SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK 0x20U /*!< Write multiple blocks operation */ +#define SDIO_CONTEXT_IT 0x08U /*!< Process in Interrupt mode */ +#define SDIO_CONTEXT_DMA 0x80U /*!< Process in DMA mode */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group3 SDIO Block mode enumeration + * @{ + */ +#define HAL_SDIO_MODE_BYTE SDMMC_SDIO_MODE_BYTE +#define HAL_SDIO_MODE_BLOCK SDMMC_SDIO_MODE_BLOCK +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group4 SDIO operation code enumeration + * @{ + */ +#define HAL_SDIO_OP_CODE_NO_INC SDMMC_SDIO_NO_INC +#define HAL_SDIO_OP_CODE_AUTO_INC SDMMC_SDIO_AUTO_INC +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group5 SDIO Read After Write(RAW) enumeration + * @{ + */ +#define HAL_SDIO_WRITE_ONLY SDMMC_SDIO_WO /*!< SDIO Write only */ +#define HAL_SDIO_READ_AFTER_WRITE SDMMC_SDIO_RAW /*!< SDIO Read after write */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group6 SDIO wire mode enumeration + * @{ + */ +#define HAL_SDIO_1_WIRE_MODE 0U /*!< SDIO wire support 1 wire */ +#define HAL_SDIO_4_WIRES_MODE 1U /*!< SDIO wire support 4 wires */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group7 SDIO Data block size enumeration + * @{ + */ +#define HAL_SDIO_DATA_BLOCK_SIZE_1BYTE 1U /*!< SDIO data block size 1 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_2BYTE 2U /*!< SDIO data block size 2 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_4BYTE 4U /*!< SDIO data block size 4 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_8BYTE 8U /*!< SDIO data block size 8 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_16BYTE 16U /*!< SDIO data block size 16 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_32BYTE 32U /*!< SDIO data block size 32 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_64BYTE 64U /*!< SDIO data block size 64 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_128BYTE 128U /*!< SDIO data block size 128 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_256BYTE 256U /*!< SDIO data block size 256 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_512BYTE 512U /*!< SDIO data block size 512 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE 1024U /*!< SDIO data block size 1024 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE 2048U /*!< SDIO data block size 2048 byte */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group8 SDIO Bus Width enumeration + * @{ + */ +#define HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED 0U /*!< SDIO bus width 8 bit is not supported */ +#define HAL_SDIO_BUS_WIDTH_8BIT_SUPPORTED 1U /*!< SDIO bus width 8 bit is supported */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group9 SDIO Data rate definitions + * @{ + */ +#define HAL_SDIOS_DATA_RATE_SDR12 0U /*!< SDIO Data rate SDR12 */ +#define HAL_SDIOS_DATA_RATE_SDR25 1U /*!< SDIO Data rate SDR25 */ +#define HAL_SDIOS_DATA_RATE_SDR50 2U /*!< SDIO Data rate SDR50 */ +#define HAL_SDIOS_DATA_RATE_DDR50 3U /*!< SDIO Data rate DDR50 */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group10 SDIO Functions definitions + * @{ + */ +#define HAL_SDIO_FUNCTION_0 0U /*!< SDIO function 0 */ +#define HAL_SDIO_FUNCTION_1 1U /*!< SDIO function 1 */ +#define HAL_SDIO_FUNCTION_2 2U /*!< SDIO function 2 */ +#define HAL_SDIO_FUNCTION_3 3U /*!< SDIO function 3 */ +#define HAL_SDIO_FUNCTION_4 4U /*!< SDIO function 4 */ +#define HAL_SDIO_FUNCTION_5 5U /*!< SDIO function 5 */ +#define HAL_SDIO_FUNCTION_6 6U /*!< SDIO function 6 */ +#define HAL_SDIO_FUNCTION_7 7U /*!< SDIO function 7 */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group11 SDIO FBR definitions + * @{ + */ +#define HAL_SDIO_FBR_SUPPORT_CSA 1U /*!< SDIO function support CSA */ +#define HAL_SDIO_FBR_SUPPORT_POWER_SELECTION 1U /*!< SDIO function support power selection */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_macros SDIO Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +/** + * @brief Enable the SDIO device interrupt. + * @param __HANDLE__ SDIO Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources. + * @retval None + */ +#define __HAL_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the SDIO device interrupt. + * @param __HANDLE__ SDIO Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources. + * @retval None + */ +#define __HAL_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified SDIO flag is set or not. + * @param __HANDLE__ SDIO Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @ref SDMMC_LL_Flags. + * @retval The new state of SDIO FLAG (SET or RESET). + */ +#define __HAL_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the SDIO's pending flags. + * @param __HANDLE__ SDIO Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one or a combination of @ref SDMMC_LL_Flags. + * @retval None + */ +#define __HAL_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified SDIO interrupt has occurred or not. + * @param __HANDLE__ SDIO Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * This parameter can be one of @ref SDMMC_LL_Interrupt_sources. + * @retval The new state of SDIO IT (SET or RESET). + */ +#define __HAL_SDIO_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Checks whether the specified SDIO interrupt is enabled or not. + * @param __HANDLE__ : SDIO handle. + * @param __INTERRUPT__ : specifies the SDMMC interrupt source to check. + * @retval The state of SDIO IT (SET or RESET). + */ +#define __HAL_SDIO_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + __SDMMC_GET_IT_SOURCE((__HANDLE__)->Instance, (__INTERRUPT__)) +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Functions SDIO Exported Functions + * @{ + */ +/** @defgroup SDIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio); +HAL_StatusTypeDef HAL_SDIO_DeInit(SDIO_HandleTypeDef *hsdio); + +void HAL_SDIO_MspInit(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_MspDeInit(SDIO_HandleTypeDef *hsdio); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_SetDataBusWidth(SDIO_HandleTypeDef *hsdio, uint32_t BusWide); +HAL_StatusTypeDef HAL_SDIO_ConfigFrequency(SDIO_HandleTypeDef *hsdio, uint32_t ClockSpeed); + +HAL_StatusTypeDef HAL_SDIO_SetBlockSize(SDIO_HandleTypeDef *hsdio, uint8_t function_nbr, uint16_t BlockSize); +HAL_StatusTypeDef HAL_SDIO_SetSpeedMode(SDIO_HandleTypeDef *hsdio, uint32_t DataRate); + +HAL_StatusTypeDef HAL_SDIO_CardReset(SDIO_HandleTypeDef *hsdio); +HAL_StatusTypeDef HAL_SDIO_GetCardCommonControlRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CCCR_TypeDef *pCccr); +HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_FBR_t *pFbr); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group3 Process functions + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData); +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data); + +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); + +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); + +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte); + +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group4 IRQHandler and callback functions + * @{ + */ +void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio); + +void HAL_SDIO_TxCpltCallback(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_RxCpltCallback(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_ErrorCallback(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_IOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t func); +#if (USE_SDIO_TRANSCEIVER != 0U) +/* Callback to switch in 1.8V mode */ +void HAL_SDIO_DriveTransceiver_1_8V_Callback(SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID, + pSDIO_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) +HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_TransceiverCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio); +#endif /* USE_SDIO_TRANSCEIVER */ + +HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, + HAL_SDIO_IOFunction_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_SDIO_StateTypeDef HAL_SDIO_GetState(const SDIO_HandleTypeDef *hsdio); +uint32_t HAL_SDIO_GetError(const SDIO_HandleTypeDef *hsdio); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group6 Peripheral IO interrupt + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); +HAL_StatusTypeDef HAL_SDIO_DisableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); + +HAL_StatusTypeDef HAL_SDIO_EnableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); +HAL_StatusTypeDef HAL_SDIO_DisableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); + +HAL_StatusTypeDef HAL_SDIO_SelectIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); +HAL_StatusTypeDef HAL_SDIO_AbortIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); + +HAL_StatusTypeDef HAL_SDIO_EnableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio); +HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio); + +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Types SDIO Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines ---------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Defines SDIO Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Variables SDIO Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Constants SDIO Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Macros SDIO Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes --------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Functions_Prototypes SDIO Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Functions SDIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SDMMC1 || SDMMC2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7xx_HAL_SDIO_H */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdram.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdram.h index cee1ffdd3..e90d546c2 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdram.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdram.h @@ -211,7 +211,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); * @{ */ /* SDRAM State functions ********************************************************/ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram); /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_swpmi.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_swpmi.h index 4180c713c..0a9e11ae2 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_swpmi.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_swpmi.h @@ -92,7 +92,7 @@ typedef struct SWPMI_InitTypeDef Init; /*!< SWPMI communication parameters */ - uint32_t *pTxBuffPtr; /*!< Pointer to SWPMI Tx transfer Buffer */ + const uint32_t *pTxBuffPtr; /*!< Pointer to SWPMI Tx transfer Buffer */ uint32_t TxXferSize; /*!< SWPMI Tx Transfer size */ @@ -122,7 +122,7 @@ typedef struct void (*ErrorCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */ void (*MspInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */ void (*MspDeInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */ -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } SWPMI_HandleTypeDef; @@ -145,7 +145,7 @@ typedef enum * @brief SWPMI callback pointer definition */ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /** * @} @@ -170,7 +170,7 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); #define HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY ((uint32_t)0x00000080) /*!< Transceiver not ready */ #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) #define HAL_SWPMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100) /*!< Invalid callback error */ -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /** * @} */ @@ -258,14 +258,14 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); * @retval None */ #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) -#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET) -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /** * @brief Enable the SWPMI peripheral. @@ -401,7 +401,8 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt. * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET) +#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__))\ + == (__IT__)) ? SET : RESET) /** * @} @@ -424,14 +425,15 @@ HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, pSWPMI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi, HAL_SWPMI_CallbackIDTypeDef CallbackID); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi); HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi); @@ -444,8 +446,8 @@ void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi); void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi); /* Peripheral Control and State functions ************************************/ -HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi); -uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi); +HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(const SWPMI_HandleTypeDef *hswpmi); +uint32_t HAL_SWPMI_GetError(const SWPMI_HandleTypeDef *hswpmi); /** * @} diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_uart.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_uart.h index c6fced028..5f0db2205 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_uart.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_uart.h @@ -1233,7 +1233,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1248,8 +1248,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_usart.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_usart.h index 518c0aa35..28ba1ed15 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_usart.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_usart.h @@ -706,8 +706,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_wwdg.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_wwdg.h index 8f2e4dc19..bee4437ed 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_wwdg.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_wwdg.h @@ -191,7 +191,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__ WWDG handle + * @param __HANDLE__: WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_adc.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_adc.h index c8f38afa4..8ca787b35 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_adc.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_adc.h @@ -386,12 +386,12 @@ extern "C" { #endif /* ADC_VER_V5_3 */ #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) +#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) #define TEMPSENSOR_CAL2_TEMP ((((DBGMCU->IDCODE) >> 16) <= ((uint32_t)0x1003)) ? 110L : 130L) /* Internal temperature sensor , temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR 110 °C for revision Y and 130 °C for revision V (tolerance: +-5 DegC) (unit: DegC). */ #else -#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been +#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #endif /* defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) */ #define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ @@ -2600,7 +2600,7 @@ typedef struct * (1) Available on devices with several ADC instances. * @retval ADC register address */ -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) { uint32_t data_reg_addr; @@ -2688,7 +2688,7 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); } @@ -2750,7 +2750,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); } @@ -2887,7 +2887,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval Value between Min_Data=0x00 and Max_Data=0x7F */ -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff) +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff) { /* Retrieve bits with position in register depending on parameter */ /* "SingleDiff". */ @@ -3059,7 +3059,7 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution * (1): Specific to ADC instance: ADC1, ADC2 * (2): Specific to ADC instance: ADC3 */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) { #if defined (ADC_VER_V5_3) @@ -3204,7 +3204,7 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * @arg @ref LL_ADC_LP_MODE_NONE * @arg @ref LL_ADC_LP_AUTOWAIT */ -__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); } @@ -3285,7 +3285,7 @@ __STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_CHANNEL_19 * @retval the preselection state of Channel (!= 0 : pre-selected, == 0 : not pre-selected) */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(const ADC_TypeDef *ADCx, uint32_t Channel) { #if defined(ADC_VER_V5_V90) if (ADCx != ADC3) @@ -3458,7 +3458,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3484,7 +3484,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off * @arg @ref LL_ADC_OFFSET_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3526,7 +3526,7 @@ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offset * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(const ADC_TypeDef *ADCx, uint32_t Offsety) { return (uint32_t)((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL)); } @@ -3581,7 +3581,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) { #if defined(ADC_VER_V5_V90) if (ADCx == ADC3) @@ -3649,7 +3649,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offs * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) { if (ADCx == ADC3) { @@ -3713,7 +3713,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, u * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety) { if (ADCx == ADC3) { @@ -3787,7 +3787,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); if (ADCx == ADC3) @@ -3898,7 +3898,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); @@ -3925,7 +3925,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); } @@ -3960,7 +3960,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); } @@ -4105,7 +4105,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); } @@ -4160,7 +4160,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM)); } @@ -4354,7 +4354,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); @@ -4400,7 +4400,7 @@ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Co * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT)); } @@ -4438,7 +4438,7 @@ __STATIC_INLINE void LL_ADC_DisableDMAReq(ADC_TypeDef *ADCx) CLEAR_BIT (ADCx->CFGR, ADC3_CFGR_DMAEN); } -__STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN) == (ADC3_CFGR_DMAEN)) ? 1UL : 0UL); } @@ -4515,7 +4515,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDMATransferMode(ADC_TypeDef *ADCx, uint32_t D * @arg @ref LL_ADC3_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC3_REG_DMA_TRANSFER_UNLIMITED */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(const ADC_TypeDef *ADCx) { if (ADCx == ADC3) { @@ -4544,7 +4544,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED * @arg @ref LL_ADC_REG_DFSDM_TRANSFER */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT)); } @@ -4584,7 +4584,7 @@ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD)); } @@ -4685,7 +4685,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); @@ -4712,7 +4712,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); } @@ -4747,7 +4747,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN)); } @@ -4794,7 +4794,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); } @@ -4827,7 +4827,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN)); } @@ -4962,7 +4962,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->JSQR, (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) @@ -5014,7 +5014,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO)); } @@ -5075,7 +5075,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMo * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS)); } @@ -5491,7 +5491,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); @@ -5623,7 +5623,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha * @arg @ref LL_ADC_CHANNEL_19 * @retval 0: channel in single-ended mode, else: channel in differential mode */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel) { #if defined(ADC_VER_V5_V90) return (uint32_t)(READ_BIT(ADCx->DIFSEL_RES12, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); @@ -5910,7 +5910,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * * (0) On STM32H7, parameter available only on analog watchdog number: AWD1. */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); @@ -6085,7 +6085,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { #if defined(ADC_VER_V5_V90) if (ADCx == ADC3) @@ -6245,7 +6245,7 @@ __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES */ -__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy) { if (ADCx == ADC3) { @@ -6318,7 +6318,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs * @arg @ref LL_ADC_OVS_GRP_INJECTED * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); } @@ -6364,7 +6364,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t O * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); } @@ -6441,7 +6441,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) { #if defined(ADC_VER_V5_V90) if(ADCx==ADC3) @@ -6478,7 +6478,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); } @@ -6536,7 +6536,7 @@ __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode) * @param ADCx ADC instance * @retval 0: Boost disabled 1: Boost enabled */ -__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(const ADC_TypeDef *ADCx) { if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */ { @@ -6598,7 +6598,7 @@ __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint3 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ -__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); } @@ -6689,7 +6689,7 @@ __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF)); } @@ -6767,7 +6767,7 @@ __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_C * (6) Parameter available only if ADC resolution is 12 bits. * (7) Parameter available only if ADC resolution is 16 or 14 bits. */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); } @@ -6829,7 +6829,7 @@ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); } @@ -6878,7 +6878,7 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } @@ -6938,7 +6938,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } @@ -6949,7 +6949,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ -__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } @@ -7003,7 +7003,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t Calibra * @param ADCx ADC instance * @retval 0: calibration complete, 1: calibration in progress. */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } @@ -7070,7 +7070,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } @@ -7081,7 +7081,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } @@ -7095,7 +7095,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7110,7 +7110,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7125,7 +7125,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7140,7 +7140,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7155,7 +7155,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7170,7 +7170,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7195,7 +7195,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_MULTI_MASTER_SLAVE * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) @@ -7265,7 +7265,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); } @@ -7276,7 +7276,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group injected. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); } @@ -7298,7 +7298,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7325,7 +7325,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7352,7 +7352,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7379,7 +7379,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7406,7 +7406,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7433,7 +7433,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7459,7 +7459,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } @@ -7470,7 +7470,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } @@ -7481,7 +7481,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } @@ -7492,7 +7492,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } @@ -7503,7 +7503,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } @@ -7514,7 +7514,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); } @@ -7525,7 +7525,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); } @@ -7536,7 +7536,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); } @@ -7547,7 +7547,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL); } @@ -7558,7 +7558,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } @@ -7569,7 +7569,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } @@ -7580,7 +7580,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } @@ -7716,7 +7716,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL); } @@ -7728,7 +7728,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL); } @@ -7740,7 +7740,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } @@ -7752,7 +7752,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } @@ -7764,7 +7764,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL); } @@ -7776,7 +7776,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL); } @@ -7788,7 +7788,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL); } @@ -7800,7 +7800,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL); } @@ -7812,7 +7812,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL); } @@ -7824,7 +7824,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL); } @@ -7836,7 +7836,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL); } @@ -7848,7 +7848,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL); } @@ -7860,7 +7860,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL); } @@ -7872,7 +7872,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL); } @@ -7884,7 +7884,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL); } @@ -7896,7 +7896,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL); } @@ -7908,7 +7908,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL); } @@ -7920,7 +7920,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL); } @@ -7932,7 +7932,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL); } @@ -7944,7 +7944,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL); } @@ -7956,7 +7956,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL); } @@ -7968,7 +7968,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL); } @@ -8230,7 +8230,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } @@ -8242,7 +8242,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } @@ -8254,7 +8254,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } @@ -8266,7 +8266,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } @@ -8278,7 +8278,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } @@ -8290,7 +8290,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); } @@ -8302,7 +8302,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); } @@ -8314,7 +8314,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); } @@ -8326,7 +8326,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } @@ -8338,7 +8338,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } @@ -8350,7 +8350,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } @@ -8365,7 +8365,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) */ /* Initialization of some features of ADC common parameters and multimode */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON); ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_bdma.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_bdma.h index 8db1b7cc6..72b747a64 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_bdma.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_bdma.h @@ -132,7 +132,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */ uint32_t PeriphRequest; /*!< Specifies the peripheral request. - This parameter can be a value of @ref DMAMUX2_Request_selection + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */ @@ -499,7 +499,7 @@ LL_BDMA_CHANNEL_7) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -521,7 +521,7 @@ __STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -543,7 +543,7 @@ __STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channe * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -584,7 +584,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_CURRENTTARGETMEM0 or @ref LL_BDMA_CURRENTTARGETMEM1 * @retval None */ -__STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_BDMA_ConfigTransfer(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -613,7 +613,7 @@ __STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channe * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction) +__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -640,7 +640,7 @@ __STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint3 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY */ -__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -668,7 +668,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, u * @arg @ref LL_BDMA_MODE_CIRCULAR * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode) +__STATIC_INLINE void LL_BDMA_SetMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -693,7 +693,7 @@ __STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint * @arg @ref LL_BDMA_MODE_NORMAL * @arg @ref LL_BDMA_MODE_CIRCULAR */ -__STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -719,7 +719,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_PERIPH_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -744,7 +744,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_PERIPH_INCREMENT * @arg @ref LL_BDMA_PERIPH_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -770,7 +770,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_MEMORY_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -795,7 +795,7 @@ __STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_MEMORY_INCREMENT * @arg @ref LL_BDMA_MEMORY_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -822,7 +822,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_PDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +__STATIC_INLINE void LL_BDMA_SetPeriphSize(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -848,7 +848,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD * @arg @ref LL_BDMA_PDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -875,7 +875,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_MDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +__STATIC_INLINE void LL_BDMA_SetMemorySize(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -901,7 +901,7 @@ __STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD * @arg @ref LL_BDMA_MDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -929,7 +929,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority) +__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -956,7 +956,7 @@ __STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32 * @arg @ref LL_BDMA_PRIORITY_HIGH * @arg @ref LL_BDMA_PRIORITY_VERYHIGH */ -__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -982,7 +982,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, ui * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData) +__STATIC_INLINE void LL_BDMA_SetDataLength(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1007,7 +1007,7 @@ __STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1033,7 +1033,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_CURRENTTARGETMEM1 * @retval None */ -__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory) +__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1057,7 +1057,7 @@ __STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t C * @arg @ref LL_BDMA_CURRENTTARGETMEM0 * @arg @ref LL_BDMA_CURRENTTARGETMEM1 */ -__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1079,7 +1079,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32 * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1101,7 +1101,7 @@ __STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_ * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1123,7 +1123,7 @@ __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32 * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { register uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1154,7 +1154,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, +__STATIC_INLINE void LL_BDMA_ConfigAddresses(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1191,7 +1191,7 @@ __STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Chann * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_BDMA_SetMemoryAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1216,7 +1216,7 @@ __STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress) +__STATIC_INLINE void LL_BDMA_SetPeriphAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1239,7 +1239,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1262,7 +1262,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1287,7 +1287,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1312,7 +1312,7 @@ __STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1335,7 +1335,7 @@ __STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1358,7 +1358,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1381,7 +1381,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t * @param Address Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address) +__STATIC_INLINE void LL_BDMA_SetMemory1Address(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1403,7 +1403,7 @@ __STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1449,7 +1449,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_BDMA_SetPeriphRequest(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request) { UNUSED(BDMAx); MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); @@ -1493,7 +1493,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Chan * * @note (*) Availability depends on devices. */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(const BDMA_TypeDef *BDMAx, uint32_t Channel) { UNUSED(BDMAx); return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); @@ -1513,7 +1513,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL); } @@ -1524,7 +1524,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL); } @@ -1535,7 +1535,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL); } @@ -1546,7 +1546,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL); } @@ -1557,7 +1557,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL); } @@ -1568,7 +1568,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL); } @@ -1579,7 +1579,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL); } @@ -1590,7 +1590,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL); } @@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL); } @@ -1611,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL); } @@ -1622,7 +1622,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL); } @@ -1633,7 +1633,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL); } @@ -1644,7 +1644,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL); } @@ -1655,7 +1655,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL); } @@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL); } @@ -1677,7 +1677,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL); } @@ -1688,7 +1688,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL); } @@ -1699,7 +1699,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL); } @@ -1710,7 +1710,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL); } @@ -1721,7 +1721,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL); } @@ -1732,7 +1732,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL); } @@ -1743,7 +1743,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL); } @@ -1754,7 +1754,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL); } @@ -1765,7 +1765,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL); } @@ -1776,7 +1776,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL); } @@ -1787,7 +1787,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL); } @@ -1798,7 +1798,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL); } @@ -1809,7 +1809,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL); } @@ -1820,7 +1820,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL); } @@ -1831,7 +1831,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL); } @@ -1842,7 +1842,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL); } @@ -1853,7 +1853,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL); } @@ -2264,7 +2264,7 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2286,7 +2286,7 @@ __STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2308,7 +2308,7 @@ __STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2330,7 +2330,7 @@ __STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2352,7 +2352,7 @@ __STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2374,7 +2374,7 @@ __STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2396,7 +2396,7 @@ __STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2418,7 +2418,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Ch * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2440,7 +2440,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Ch * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_comp.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_comp.h index 44fd717d1..0a0ba7770 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_comp.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_comp.h @@ -341,7 +341,7 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM * @arg @ref LL_COMP_WINDOWMODE_DISABLE * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON */ -__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON) +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef *COMPxy_COMMON) { return (uint32_t)(READ_BIT(COMPxy_COMMON->CFGR, COMP_CFGRx_WINMODE)); } @@ -378,7 +378,7 @@ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMod * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER */ -__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_PWRMODE)); } @@ -480,7 +480,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * @arg @ref LL_COMP_INPUT_PLUS_IO2 * @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1 */ -__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx) { #if defined (COMP_CFGRx_INP2SEL) return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INPSEL | COMP_CFGRx_INP2SEL)); @@ -549,7 +549,7 @@ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMi * @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1 * @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP */ -__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INMSEL | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)); } @@ -580,7 +580,7 @@ __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t In * @arg @ref LL_COMP_HYSTERESIS_MEDIUM * @arg @ref LL_COMP_HYSTERESIS_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_HYST)); } @@ -615,7 +615,7 @@ __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t Out * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED * @arg @ref LL_COMP_OUTPUTPOL_INVERTED */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_POLARITY)); } @@ -660,7 +660,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32 * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5 * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1 */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_BLANKING)); } @@ -685,7 +685,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_AF_PK2 * @retval None */ -__STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(COMP_TypeDef *COMPx, uint32_t CompAFx) +__STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(const COMP_TypeDef *COMPx, uint32_t CompAFx) { MODIFY_REG(COMP12->OR, 0x7FFUL, (COMPx == COMP1) ? ((~CompAFx) & 0x7FFUL) : CompAFx); } @@ -706,7 +706,7 @@ __STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(COMP_TypeDef *COMPx, uin * @arg @ref LL_COMP_AF_PI4 * @arg @ref LL_COMP_AF_PK2 */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputAlternateFunction(COMP_TypeDef *COMPx ) +__STATIC_INLINE uint32_t LL_COMP_GetOutputAlternateFunction(const COMP_TypeDef *COMPx ) { return (uint32_t) ((COMPx == COMP1) ? ((~COMP12->OR) & 0x7FFUL) : (COMP12->OR & 0x7FFUL)); } @@ -751,7 +751,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_EN) == (COMP_CFGRx_EN)) ? 1UL : 0UL); } @@ -778,7 +778,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_LOCK) == (COMP_CFGRx_LOCK)) ? 1UL : 0UL); } @@ -803,7 +803,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx) { if (COMPx == COMP1) { @@ -829,7 +829,7 @@ __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(const COMP_TypeDef *COMPx) { if (COMPx == COMP1) { @@ -847,7 +847,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval None */ -__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(COMP_TypeDef *COMPx) +__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(const COMP_TypeDef *COMPx) { if (COMPx == COMP1) { @@ -895,7 +895,7 @@ __STATIC_INLINE void LL_COMP_DisableIT_OutputTrig(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_ITEN) == (COMP_CFGRx_ITEN)) ? 1UL : 0UL); } diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_cordic.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_cordic.h index fe1f6f9ef..f36ebfc0e 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_cordic.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_cordic.h @@ -131,12 +131,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE * @{ */ -#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one - 32-bit data input (Q1.31 format), or two - 16-bit data input (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input - (Q1.31 format) */ +#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one + 32-bits data input (Q1.31 format), or two + 16-bits data input (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input + (Q1.31 format) */ /** * @} */ @@ -144,12 +144,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBREAD NBREAD * @{ */ -#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data output (Q1.31 format), or two - 16-bit data output (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output - (Q1.31 format) */ +#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one + 32-bits data output (Q1.31 format), or two + 16-bits data output (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output + (Q1.31 format) */ /** * @} */ @@ -218,9 +218,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions * @{ */ @@ -749,8 +747,6 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma.h index c05815a94..5195c3b7e 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma.h @@ -140,7 +140,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ uint32_t PeriphRequest; /*!< Specifies the peripheral request. - This parameter can be a value of @ref DMAMUX1_Request_selection + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ @@ -486,7 +486,7 @@ typedef struct * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableStream(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -508,7 +508,7 @@ __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableStream(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -530,7 +530,7 @@ __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -571,7 +571,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stre * @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1 *@retval None */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -599,7 +599,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, u * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -624,7 +624,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -651,7 +651,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint * @arg @ref LL_DMA_MODE_PFCTRL * @retval None */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) +__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -677,7 +677,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t * @arg @ref LL_DMA_MODE_CIRCULAR * @arg @ref LL_DMA_MODE_PFCTRL */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -702,7 +702,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_PERIPH_INCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -726,7 +726,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_PERIPH_NOINCREMENT * @arg @ref LL_DMA_PERIPH_INCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -751,7 +751,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_MEMORY_INCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -775,7 +775,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_MEMORY_NOINCREMENT * @arg @ref LL_DMA_MEMORY_INCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -801,7 +801,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_PDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -826,7 +826,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, ui * @arg @ref LL_DMA_PDATAALIGN_HALFWORD * @arg @ref LL_DMA_PDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -852,7 +852,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_MDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -877,7 +877,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, ui * @arg @ref LL_DMA_MDATAALIGN_HALFWORD * @arg @ref LL_DMA_MDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -902,7 +902,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 * @retval None */ -__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) +__STATIC_INLINE void LL_DMA_SetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -926,7 +926,7 @@ __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_OFFSETSIZE_PSIZE * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 */ -__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -953,7 +953,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) +__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -979,7 +979,7 @@ __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_PRIORITY_HIGH * @arg @ref LL_DMA_PRIORITY_VERYHIGH */ -__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1001,7 +1001,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32 * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1023,7 +1023,7 @@ __STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1048,7 +1048,7 @@ __STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_ * @param NbData Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) +__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1072,7 +1072,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, ui * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1396,7 +1396,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, * * @note (*) Availability depends on devices. */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Stream) { return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); } @@ -1421,7 +1421,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t St * @arg @ref LL_DMA_MBURST_INC16 * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1447,7 +1447,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_MBURST_INC8 * @arg @ref LL_DMA_MBURST_INC16 */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1474,7 +1474,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_PBURST_INC16 * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1500,7 +1500,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_PBURST_INC8 * @arg @ref LL_DMA_PBURST_INC16 */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1525,7 +1525,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_CURRENTTARGETMEM1 * @retval None */ -__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) +__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1549,7 +1549,7 @@ __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stre * @arg @ref LL_DMA_CURRENTTARGETMEM0 * @arg @ref LL_DMA_CURRENTTARGETMEM1 */ -__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1571,7 +1571,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1593,7 +1593,7 @@ __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1615,9 +1615,9 @@ __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL); } @@ -1643,7 +1643,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uin * @arg @ref LL_DMA_FIFOSTATUS_EMPTY * @arg @ref LL_DMA_FIFOSTATUS_FULL */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1665,7 +1665,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1687,7 +1687,7 @@ __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1714,7 +1714,7 @@ __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL * @retval None */ -__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) +__STATIC_INLINE void LL_DMA_SetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1740,7 +1740,7 @@ __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1771,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) +__STATIC_INLINE void LL_DMA_ConfigFifo(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1801,7 +1801,7 @@ __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint3 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1837,7 +1837,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, * @param MemoryAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1862,7 +1862,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @param PeriphAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) +__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1885,7 +1885,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1908,7 +1908,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1933,7 +1933,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Str * @param MemoryAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @param MemoryAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1981,7 +1981,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2004,7 +2004,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2027,7 +2027,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Str * @param Address Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +__STATIC_INLINE void LL_DMA_SetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2049,7 +2049,7 @@ __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2070,7 +2070,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t St * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL); } @@ -2081,7 +2081,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL); } @@ -2092,7 +2092,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL); } @@ -2103,7 +2103,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL); } @@ -2114,7 +2114,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL); } @@ -2125,7 +2125,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL); } @@ -2136,7 +2136,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL); } @@ -2147,7 +2147,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL); } @@ -2158,7 +2158,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL); } @@ -2169,7 +2169,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL); } @@ -2180,7 +2180,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL); } @@ -2191,7 +2191,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL); } @@ -2202,7 +2202,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL); } @@ -2213,7 +2213,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL); } @@ -2224,7 +2224,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL); } @@ -2235,7 +2235,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL); } @@ -2246,7 +2246,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL); } @@ -2257,7 +2257,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL); } @@ -2268,7 +2268,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL); } @@ -2279,7 +2279,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL); } @@ -2290,7 +2290,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL); } @@ -2301,7 +2301,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL); } @@ -2312,7 +2312,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL); } @@ -2323,7 +2323,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL); } @@ -2334,7 +2334,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL); } @@ -2345,7 +2345,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL); } @@ -2356,7 +2356,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL); } @@ -2367,7 +2367,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL); } @@ -2378,7 +2378,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL); } @@ -2389,7 +2389,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL); } @@ -2400,7 +2400,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL); } @@ -2411,7 +2411,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL); } @@ -2422,7 +2422,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL); } @@ -2433,7 +2433,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL); } @@ -2444,7 +2444,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL); } @@ -2455,7 +2455,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL); } @@ -2466,7 +2466,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL); } @@ -2477,7 +2477,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL); } @@ -2488,7 +2488,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL); } @@ -2499,7 +2499,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL); } @@ -2967,7 +2967,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2989,7 +2989,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3011,7 +3011,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3033,7 +3033,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3055,7 +3055,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3077,7 +3077,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3099,7 +3099,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3121,7 +3121,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3143,7 +3143,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3165,7 +3165,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3187,7 +3187,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3209,7 +3209,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3231,7 +3231,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3253,7 +3253,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3275,7 +3275,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stre * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma2d.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma2d.h index daea47584..905cbc7ea 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma2d.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma2d.h @@ -582,7 +582,7 @@ __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL); } @@ -619,7 +619,7 @@ __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL); } @@ -644,7 +644,7 @@ __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL); } @@ -679,7 +679,7 @@ __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG */ -__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); } @@ -712,7 +712,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); } @@ -739,7 +739,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_ * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS)); } @@ -766,7 +766,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); } @@ -794,7 +794,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB)); } @@ -821,7 +821,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM)); } @@ -844,7 +844,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t Line * @param DMA2Dx DMA2D Instance * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); } @@ -867,7 +867,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint * @param DMA2Dx DMA2D Instance * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); } @@ -890,7 +890,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrO * @param DMA2Dx DMA2D Instance * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); } @@ -913,7 +913,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t O * @param DMA2Dx DMA2D Instance * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); } @@ -934,8 +934,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) { - MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ - OutputColor); + WRITE_REG(DMA2Dx->OCOLR, OutputColor); } /** @@ -950,7 +949,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t Out * @param DMA2Dx DMA2D Instance * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); @@ -974,7 +973,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t L * @param DMA2Dx DMA2D Instance * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); } @@ -997,7 +996,7 @@ __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTi * @param DMA2Dx DMA2D Instance * @retval Dead time value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); } @@ -1030,7 +1029,7 @@ __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); } @@ -1057,7 +1056,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me * @param DMA2Dx DMA2D Instance * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); } @@ -1079,7 +1078,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL); } @@ -1124,7 +1123,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_INPUT_MODE_A8 * @arg @ref LL_DMA2D_INPUT_MODE_A4 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); } @@ -1153,7 +1152,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); } @@ -1176,7 +1175,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph * @param DMA2Dx DMA2D Instance * @retval Alpha value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); } @@ -1203,7 +1202,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS)); } @@ -1230,7 +1229,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI)); } @@ -1253,7 +1252,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); } @@ -1293,7 +1292,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R * @param DMA2Dx DMA2D Instance * @retval Red color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); } @@ -1316,7 +1315,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Green color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); } @@ -1339,7 +1338,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Blue color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); } @@ -1362,7 +1361,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_ * @param DMA2Dx DMA2D Instance * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); } @@ -1385,7 +1384,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C * @param DMA2Dx DMA2D Instance * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); } @@ -1412,7 +1411,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); } @@ -1441,7 +1440,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint * @arg @ref LL_DMA2D_CSS_422 * @arg @ref LL_DMA2D_CSS_420 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS)); } @@ -1471,7 +1470,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me * @param DMA2Dx DMA2D Instance * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); } @@ -1493,7 +1492,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL); } @@ -1538,7 +1537,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_INPUT_MODE_A8 * @arg @ref LL_DMA2D_INPUT_MODE_A4 */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); } @@ -1567,7 +1566,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); } @@ -1590,7 +1589,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph * @param DMA2Dx DMA2D Instance * @retval Alpha value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); } @@ -1617,7 +1616,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS)); } @@ -1644,7 +1643,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI)); } @@ -1667,7 +1666,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); } @@ -1707,7 +1706,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R * @param DMA2Dx DMA2D Instance * @retval Red color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); } @@ -1730,7 +1729,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Green color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); } @@ -1753,7 +1752,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Blue color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); } @@ -1776,7 +1775,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_ * @param DMA2Dx DMA2D Instance * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); } @@ -1799,7 +1798,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C * @param DMA2Dx DMA2D Instance * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); } @@ -1826,7 +1825,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); } @@ -1850,7 +1849,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL); } @@ -1861,7 +1860,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL); } @@ -1872,7 +1871,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL); } @@ -1883,7 +1882,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL); } @@ -1894,7 +1893,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL); } @@ -1905,7 +1904,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL); } @@ -2122,7 +2121,7 @@ __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL); } @@ -2133,7 +2132,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL); } @@ -2144,7 +2143,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); } @@ -2155,7 +2154,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL); } @@ -2166,7 +2165,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL); } @@ -2177,7 +2176,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL); } @@ -2193,16 +2192,16 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) * @{ */ -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx); +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx); ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); /** diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dmamux.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dmamux.h index bf4cffa0b..be9b2fc40 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dmamux.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dmamux.h @@ -726,7 +726,7 @@ extern "C" { * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -919,7 +919,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -950,7 +950,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -980,7 +980,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1015,7 +1015,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1049,7 +1049,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_SYNC_POL_FALLING * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1079,7 +1079,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1109,7 +1109,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1139,7 +1139,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1169,7 +1169,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1199,7 +1199,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1229,7 +1229,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1284,7 +1284,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX2_SYNC_EXTI2 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1338,7 +1338,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 * @arg @ref LL_DMAMUX2_SYNC_EXTI0 * @arg @ref LL_DMAMUX2_SYNC_EXTI2 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1360,7 +1360,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1378,7 +1378,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1400,7 +1400,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1427,7 +1427,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *D * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1453,7 +1453,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1477,7 +1477,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1499,7 +1499,7 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1561,7 +1561,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMU * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1607,7 +1607,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX2_SYNC_EXTI0 * @arg @ref LL_DMAMUX2_SYNC_EXTI2 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1628,7 +1628,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1641,7 +1641,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1654,7 +1654,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1667,7 +1667,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1680,7 +1680,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1693,7 +1693,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1706,7 +1706,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1719,7 +1719,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1732,7 +1732,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1745,7 +1745,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1758,7 +1758,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1771,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1784,7 +1784,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1797,7 +1797,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1810,7 +1810,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1823,7 +1823,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1836,7 +1836,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1849,7 +1849,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1862,7 +1862,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1875,7 +1875,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1888,7 +1888,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1901,7 +1901,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1914,7 +1914,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1927,7 +1927,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1940,7 +1940,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1953,7 +1953,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1966,7 +1966,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1979,7 +1979,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1992,7 +1992,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2005,7 +2005,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2018,7 +2018,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2031,7 +2031,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2044,7 +2044,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2057,7 +2057,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2070,7 +2070,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2083,7 +2083,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2096,7 +2096,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2109,7 +2109,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2122,7 +2122,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2135,7 +2135,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2148,7 +2148,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2161,7 +2161,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2174,7 +2174,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2187,7 +2187,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2200,7 +2200,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2213,7 +2213,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2226,7 +2226,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2239,7 +2239,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2277,7 +2277,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2307,7 +2307,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2337,7 +2337,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2359,7 +2359,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2381,7 +2381,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2403,7 +2403,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmac.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmac.h index 8e92c3d4d..5edb287d8 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmac.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmac.h @@ -38,7 +38,6 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ /** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants * @{ @@ -147,9 +146,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions * @{ */ @@ -1033,8 +1030,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions * @{ @@ -1042,7 +1037,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx); ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx); - /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmc.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmc.h index 3d34898e3..7509bcedb 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmc.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmc.h @@ -190,61 +190,62 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device + by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ + This parameter can be a value of @ref FMC_Write_FIFO */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ + This parameter can be a value of @ref FMC_Page_Size */ } FMC_NORSRAM_InitTypeDef; /** @@ -288,7 +289,7 @@ typedef struct in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ + This parameter can be a value of @ref FMC_Access_Mode */ } FMC_NORSRAM_TimingTypeDef; /** @@ -1056,11 +1057,11 @@ typedef struct * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); + const FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); @@ -1086,11 +1087,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -1101,7 +1102,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); /** * @} @@ -1117,9 +1118,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} @@ -1131,7 +1132,7 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); + const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_gpio.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_gpio.h index b51f9d3bf..b099741d9 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_gpio.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_gpio.h @@ -309,7 +309,7 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); } @@ -377,7 +377,7 @@ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinM * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); } @@ -450,7 +450,7 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint * @arg @ref LL_GPIO_SPEED_FREQ_HIGH * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); } @@ -515,7 +515,7 @@ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_DOWN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); } @@ -591,7 +591,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); @@ -669,7 +669,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * @@ -741,7 +741,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -752,7 +752,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMa * @param GPIOx GPIO Port * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) { return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); } @@ -771,7 +771,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) * @param GPIOx GPIO Port * @retval Input data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->IDR)); } @@ -800,7 +800,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -823,7 +823,7 @@ __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortV * @param GPIOx GPIO Port * @retval Output data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->ODR)); } @@ -852,7 +852,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -954,7 +954,7 @@ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @{ */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hrtim.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hrtim.h index d3f3608fe..741d758b9 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hrtim.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hrtim.h @@ -1972,7 +1972,7 @@ __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCT { uint32_t shift = ((3U * ADCTrig) & 0x1FU); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); WRITE_REG(*pReg, Src); } @@ -2247,7 +2247,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) { __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); WRITE_REG(*pReg, Src); } @@ -2464,7 +2464,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); return (*pReg); } @@ -3138,7 +3138,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3158,7 +3158,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3178,7 +3178,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL); } @@ -3209,7 +3209,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); } @@ -3238,7 +3238,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift); } @@ -3268,7 +3268,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); } @@ -3290,7 +3290,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); } @@ -3313,7 +3313,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); } @@ -3335,7 +3335,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uin { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MPER_MPER)); } @@ -3358,7 +3358,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); } @@ -3380,7 +3380,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MREP_MREP)); } @@ -3405,7 +3405,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); } @@ -3429,7 +3429,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); } @@ -3454,7 +3454,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); } @@ -3478,7 +3478,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); } @@ -3503,7 +3503,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); } @@ -3527,7 +3527,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); } @@ -3552,7 +3552,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); } @@ -3576,7 +3576,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); } @@ -3663,7 +3663,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); WRITE_REG(*pReg, ResetTrig); } @@ -3743,7 +3743,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3763,7 +3763,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3783,7 +3783,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3871,7 +3871,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); WRITE_REG(*pReg, CaptureTrig); } @@ -3957,7 +3957,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); return (READ_REG(*pReg)); } @@ -3977,7 +3977,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -3997,7 +3997,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -4017,7 +4017,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRT { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL); } @@ -4062,7 +4062,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); } @@ -4103,7 +4103,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); } @@ -4124,7 +4124,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4145,7 +4145,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4165,7 +4165,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL); } @@ -4195,7 +4195,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, Faults); } @@ -4225,7 +4225,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, Faults); } @@ -4255,7 +4255,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL); } @@ -4277,7 +4277,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); } @@ -4442,7 +4442,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeD { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); } @@ -4464,7 +4464,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); } @@ -4524,7 +4524,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4581,7 +4581,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4627,7 +4627,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4670,7 +4670,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *H uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4704,7 +4704,7 @@ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); } @@ -4733,7 +4733,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); } @@ -4761,7 +4761,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); } @@ -4782,7 +4782,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); } @@ -4802,7 +4802,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTR)); } @@ -4825,7 +4825,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); } @@ -4847,7 +4847,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); } @@ -4868,7 +4868,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); } @@ -4888,7 +4888,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); } @@ -4911,7 +4911,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); } @@ -4933,7 +4933,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); } @@ -4953,7 +4953,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRLK); } @@ -4973,7 +4973,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRSLK); } @@ -4993,7 +4993,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFLK); } @@ -5013,7 +5013,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFSLK); } @@ -5049,7 +5049,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); } @@ -5089,7 +5089,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); } @@ -5125,7 +5125,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); } @@ -5157,7 +5157,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); } @@ -5185,7 +5185,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); } @@ -5224,7 +5224,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); } @@ -5260,7 +5260,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); } @@ -5389,7 +5389,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, SetSrc); } @@ -5509,7 +5509,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIM { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5630,7 +5630,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, ResetSrc); } @@ -5750,7 +5750,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRT { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5793,7 +5793,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]), (Configuration << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5823,7 +5823,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5851,7 +5851,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, u { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -5881,7 +5881,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput]))); } @@ -5909,7 +5909,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, u { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -5940,7 +5940,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5968,7 +5968,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6001,7 +6001,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6031,7 +6031,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6061,7 +6061,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6089,7 +6089,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6119,7 +6119,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6147,7 +6147,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6176,7 +6176,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HR { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1STAT_Pos); } @@ -6214,7 +6214,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); + REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); SET_BIT(*pReg, HRTIM_SET1R_SST); } @@ -6242,7 +6242,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1CPY_Pos); } @@ -6323,7 +6323,7 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]), (Configuration << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6363,7 +6363,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6401,7 +6401,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6440,7 +6440,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6476,7 +6476,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6516,7 +6516,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6554,7 +6554,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6587,7 +6587,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6618,7 +6618,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6770,7 +6770,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]), (Configuration << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6799,7 +6799,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6824,8 +6824,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6853,7 +6853,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6878,8 +6878,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6921,7 +6921,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6960,8 +6960,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -7017,7 +7017,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7041,7 +7041,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7065,7 +7065,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7089,7 +7089,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uin { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) == (HRTIM_IER_FLT1)) ? 1UL : 0UL); } @@ -7765,7 +7765,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MUPD); } @@ -7787,7 +7787,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL); } @@ -7810,7 +7810,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MREP); } @@ -7833,7 +7833,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL); } @@ -7856,7 +7856,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP1); } @@ -7878,7 +7878,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL); } @@ -7901,7 +7901,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP2); } @@ -7923,7 +7923,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL); } @@ -7946,7 +7946,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP3); } @@ -7968,7 +7968,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL); } @@ -7991,7 +7991,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP4); } @@ -8013,7 +8013,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL); } @@ -8034,7 +8034,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); } @@ -8054,7 +8054,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL); } @@ -8075,7 +8075,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); } @@ -8095,7 +8095,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL); } @@ -8116,7 +8116,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET1C); } @@ -8136,7 +8136,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL); } @@ -8157,7 +8157,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST1C); } @@ -8177,7 +8177,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL); } @@ -8198,7 +8198,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET2C); } @@ -8218,7 +8218,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL); } @@ -8239,7 +8239,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST2C); } @@ -8259,7 +8259,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL); } @@ -8280,7 +8280,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RSTC); } @@ -8300,7 +8300,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL); } @@ -8321,7 +8321,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC); } @@ -8341,7 +8341,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL); } @@ -8636,7 +8636,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8658,7 +8658,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8680,7 +8680,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL); } @@ -8703,7 +8703,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8725,7 +8725,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8747,7 +8747,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL); } @@ -8770,7 +8770,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8792,7 +8792,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8814,7 +8814,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL); } @@ -8837,7 +8837,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -8859,7 +8859,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -8881,7 +8881,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL); } @@ -8904,7 +8904,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -8926,7 +8926,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -8948,7 +8948,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL); } @@ -8971,7 +8971,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -8993,7 +8993,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -9015,7 +9015,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL); } @@ -9036,7 +9036,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9056,7 +9056,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9076,7 +9076,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL); } @@ -9097,7 +9097,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9117,7 +9117,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9137,7 +9137,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL); } @@ -9158,7 +9158,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9178,7 +9178,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9198,7 +9198,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL); } @@ -9219,7 +9219,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9239,7 +9239,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9259,7 +9259,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL); } @@ -9280,7 +9280,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9300,7 +9300,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9320,7 +9320,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL); } @@ -9341,7 +9341,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9361,7 +9361,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9381,7 +9381,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL); } @@ -9402,7 +9402,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9422,7 +9422,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9442,7 +9442,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL); } @@ -9463,7 +9463,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9483,7 +9483,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9503,7 +9503,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL); } @@ -9567,7 +9567,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9589,7 +9589,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32 { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9611,7 +9611,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL); } @@ -9634,7 +9634,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9656,7 +9656,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9678,7 +9678,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL); } @@ -9701,7 +9701,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9723,7 +9723,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9745,7 +9745,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL); } @@ -9768,7 +9768,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9790,7 +9790,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9812,7 +9812,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL); } @@ -9835,7 +9835,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -9857,7 +9857,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -9879,7 +9879,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL); } @@ -9902,7 +9902,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -9924,7 +9924,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -9946,7 +9946,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL); } @@ -9967,7 +9967,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -9987,7 +9987,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -10007,7 +10007,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL); } @@ -10028,7 +10028,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10048,7 +10048,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10068,7 +10068,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL); } @@ -10089,7 +10089,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10109,7 +10109,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10129,7 +10129,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL); } @@ -10150,7 +10150,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10170,7 +10170,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10190,7 +10190,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL); } @@ -10211,7 +10211,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10231,7 +10231,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10251,7 +10251,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL); } @@ -10272,7 +10272,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10292,7 +10292,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10312,7 +10312,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL); } @@ -10333,7 +10333,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10353,7 +10353,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10373,7 +10373,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL); } @@ -10394,7 +10394,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10414,7 +10414,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32 { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10434,7 +10434,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL); } @@ -10447,7 +10447,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HR /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions * @{ */ -ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); +ErrorStatus LL_HRTIM_DeInit(const HRTIM_TypeDef *HRTIMx); /** * @} */ @@ -10473,4 +10473,3 @@ ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); #endif /* STM32H7xx_LL_HRTIM_H */ - diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hsem.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hsem.h index cff88b5cd..689b7e57e 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hsem.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hsem.h @@ -163,7 +163,7 @@ extern "C" { * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL); } @@ -178,7 +178,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t * @arg @ref LL_HSEM_COREID_CPU1 * @arg @ref LL_HSEM_COREID_CPU2 */ -__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk)); } @@ -190,7 +190,7 @@ __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semapho * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval Process number. Value between Min_Data=0 and Max_Data=255 */ -__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk)); } @@ -236,7 +236,7 @@ __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semapho * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval 1 lock fail, 0 lock successful or already locked by same core */ -__STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); } @@ -261,7 +261,7 @@ __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore * @param HSEMx HSEM Instance. * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval 0 semaphore is free, 1 semaphore is locked */ -__STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetStatus(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL); } @@ -284,7 +284,7 @@ __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key) * @param HSEMx HSEM Instance. * @retval key to unlock all semaphore from the same core */ -__STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx) +__STATIC_INLINE uint32_t LL_HSEM_GetKey(const HSEM_TypeDef *HSEMx) { return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos); } @@ -450,7 +450,7 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t Semap * depends on devices. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -586,7 +586,7 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -689,7 +689,7 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t Semap * depends on devices. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -736,7 +736,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_ * depends on devices. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -827,7 +827,7 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -872,7 +872,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_ * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_iwdg.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_iwdg.h index d34acc262..743c91730 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_iwdg.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_iwdg.h @@ -208,7 +208,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale * @arg @ref LL_IWDG_PRESCALER_128 * @arg @ref LL_IWDG_PRESCALER_256 */ -__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->PR)); } @@ -231,7 +231,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->RLR)); } @@ -254,7 +254,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->WINR)); } @@ -273,7 +273,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); } @@ -284,7 +284,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); } @@ -295,7 +295,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); } @@ -308,7 +308,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL); } diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_lpuart.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_lpuart.h index fe66becb5..2f362a4e7 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_lpuart.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_lpuart.h @@ -2605,6 +2605,21 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_mdma.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_mdma.h index 8b80c7d81..a55cb8289 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_mdma.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_mdma.h @@ -688,7 +688,7 @@ typedef struct * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableChannel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -718,7 +718,7 @@ __STATIC_INLINE void LL_MDMA_EnableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableChannel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -748,7 +748,7 @@ __STATIC_INLINE void LL_MDMA_DisableChannel(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -778,7 +778,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_GenerateSWRequest(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -814,7 +814,7 @@ __STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_BYTE_ENDIANNESS_PRESERVE or @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_MDMA_ConfigXferEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -848,7 +848,7 @@ __STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) +__STATIC_INLINE void LL_MDMA_SetWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -881,7 +881,7 @@ __STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -914,7 +914,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) +__STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -947,7 +947,7 @@ __STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -980,7 +980,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) +__STATIC_INLINE void LL_MDMA_SetByteEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1013,7 +1013,7 @@ __STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1048,7 +1048,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority) +__STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1083,7 +1083,7 @@ __STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1143,7 +1143,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(MDMA_TypeDef *MDMAx, ui * @param BufferXferLength This parameter can be a value Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigTransfer(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength) +__STATIC_INLINE void LL_MDMA_ConfigTransfer(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1174,7 +1174,7 @@ __STATIC_INLINE void LL_MDMA_ConfigTransfer(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1204,7 +1204,7 @@ __STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_ * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1234,7 +1234,7 @@ __STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1267,7 +1267,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(MDMA_TypeDef *MDMAx, * @arg @ref LL_MDMA_REQUEST_MODE_SW * @retval None */ -__STATIC_INLINE void LL_MDMA_SetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode) +__STATIC_INLINE void LL_MDMA_SetRequestMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1300,7 +1300,7 @@ __STATIC_INLINE void LL_MDMA_SetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_REQUEST_MODE_SW * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1335,7 +1335,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_FULL_TRANSFER * @retval None */ -__STATIC_INLINE void LL_MDMA_SetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode) +__STATIC_INLINE void LL_MDMA_SetTriggerMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1370,7 +1370,7 @@ __STATIC_INLINE void LL_MDMA_SetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_FULL_TRANSFER * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1404,7 +1404,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_DATAALIGN_LEFT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment) +__STATIC_INLINE void LL_MDMA_SetPaddingAlignment(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_MDMA_SetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_DATAALIGN_LEFT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1469,7 +1469,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnablePacking(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1499,7 +1499,7 @@ __STATIC_INLINE void LL_MDMA_EnablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisablePacking(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1529,7 +1529,7 @@ __STATIC_INLINE void LL_MDMA_DisablePacking(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1560,7 +1560,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(MDMA_TypeDef *MDMAx, uint32_t * @param Length Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length) +__STATIC_INLINE void LL_MDMA_SetBufferTransferLength(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1592,7 +1592,7 @@ __STATIC_INLINE void LL_MDMA_SetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32 * @retval Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1631,7 +1631,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(MDMA_TypeDef *MDMAx, ui * @arg @ref LL_MDMA_DEST_BURST_128BEATS * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst) +__STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1670,7 +1670,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_DEST_BURST_128BEATS * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(MDMA_TypeDef *MDMAx, ui * @arg @ref LL_MDMA_SRC_BURST_128BEATS * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst) +__STATIC_INLINE void LL_MDMA_SetSourceBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1748,7 +1748,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_SRC_BURST_128BEATS * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1783,7 +1783,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_ * @arg @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) +__STATIC_INLINE void LL_MDMA_SetDestinationIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1818,7 +1818,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1853,7 +1853,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) +__STATIC_INLINE void LL_MDMA_SetSourceIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1888,7 +1888,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Chan * @arg @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1923,7 +1923,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize) +__STATIC_INLINE void LL_MDMA_SetDestinationDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_ * @arg @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1993,7 +1993,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(MDMA_TypeDef *MDMAx, uin * @arg @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize) +__STATIC_INLINE void LL_MDMA_SetSourceDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2028,7 +2028,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2062,7 +2062,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode) +__STATIC_INLINE void LL_MDMA_SetDestinationIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2096,7 +2096,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2130,7 +2130,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_SRC_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode) +__STATIC_INLINE void LL_MDMA_SetSourceIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2164,7 +2164,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Chan * @arg @ref LL_MDMA_SRC_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2197,7 +2197,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t * @param BlkDataLength Between 0 to 0x00010000 * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBlkCounters(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength) +__STATIC_INLINE void LL_MDMA_ConfigBlkCounters(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2230,7 +2230,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBlkCounters(MDMA_TypeDef *MDMAx, uint32_t Cha * @param BlkDataLength Between 0 to 0x00010000 * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength) +__STATIC_INLINE void LL_MDMA_SetBlkDataLength(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2261,7 +2261,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Chan * @retval Between 0 to 0x00010000 * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2292,7 +2292,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t * @param BlockRepeatCount Between 0 to 0x00000FFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount) +__STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2324,7 +2324,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Cha * @retval Between 0 to 0x00000FFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2358,7 +2358,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT or @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2393,7 +2393,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode) +__STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2426,7 +2426,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uin * @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2459,7 +2459,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, * @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode) +__STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2492,7 +2492,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2526,7 +2526,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigAddresses(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress) +__STATIC_INLINE void LL_MDMA_ConfigAddresses(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2557,7 +2557,7 @@ __STATIC_INLINE void LL_MDMA_ConfigAddresses(MDMA_TypeDef *MDMAx, uint32_t Chann * @param SrcAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress) +__STATIC_INLINE void LL_MDMA_SetSourceAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2588,7 +2588,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Chan * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2619,7 +2619,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t * @param DestAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress) +__STATIC_INLINE void LL_MDMA_SetDestinationAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2650,7 +2650,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2684,7 +2684,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(MDMA_TypeDef *MDMAx, uint * @param DestAdrUpdateValue Between Min_Data = 0 and Max_Data = 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue) +__STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2716,7 +2716,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMA_TypeDef *MDMAx, ui * @param DestAdrUpdateValue Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue) +__STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2748,7 +2748,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, u * @retval Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2779,7 +2779,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMA * @param SrcAdrUpdateValue Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue) +__STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2810,7 +2810,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, ui * @retval Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2841,7 +2841,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx * @param LinkAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress) +__STATIC_INLINE void LL_MDMA_SetLinkAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2872,7 +2872,7 @@ __STATIC_INLINE void LL_MDMA_SetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channe * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2906,7 +2906,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_SRC_BUS_SYSTEM_AXI or @ref LL_MDMA_SRC_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_MDMA_ConfigBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2941,7 +2941,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBusSelection(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_DEST_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus) +__STATIC_INLINE void LL_MDMA_SetDestBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2974,7 +2974,7 @@ __STATIC_INLINE void LL_MDMA_SetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_DEST_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3007,7 +3007,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_SRC_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus) +__STATIC_INLINE void LL_MDMA_SetSrcBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3040,7 +3040,7 @@ __STATIC_INLINE void LL_MDMA_SetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_SRC_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3108,7 +3108,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_ * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_MDMA_SetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest) +__STATIC_INLINE void LL_MDMA_SetHWTrigger(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3176,7 +3176,7 @@ __STATIC_INLINE void LL_MDMA_SetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel, * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3207,7 +3207,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Chan * @param MaskAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress) +__STATIC_INLINE void LL_MDMA_SetMaskAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3238,7 +3238,7 @@ __STATIC_INLINE void LL_MDMA_SetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channe * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3269,7 +3269,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Ch * @param MaskData Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData) +__STATIC_INLINE void LL_MDMA_SetMaskData(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3300,7 +3300,7 @@ __STATIC_INLINE void LL_MDMA_SetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel, * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetMaskData(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3333,7 +3333,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetMaskData(MDMA_TypeDef *MDMAx, uint32_t Chann * @arg @ref LL_MDMA_WRITE_ERROR * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3364,7 +3364,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(MDMA_TypeDef *MDMAx, uint * @retval Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3402,7 +3402,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(MDMA_TypeDef *MDMAx, uin * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(const MDMA_TypeDef *MDMAx, uint32_t Channel) { return ((READ_BIT(MDMAx->GISR0 ,(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU)))==(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } @@ -3430,7 +3430,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3460,7 +3460,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3490,7 +3490,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3520,7 +3520,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3550,7 +3550,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3580,7 +3580,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3610,7 +3610,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3640,7 +3640,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3670,7 +3670,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3700,7 +3700,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3730,7 +3730,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3760,7 +3760,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3790,7 +3790,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3820,7 +3820,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3850,7 +3850,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3888,7 +3888,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3918,7 +3918,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3948,7 +3948,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3978,7 +3978,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4008,7 +4008,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4038,7 +4038,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4068,7 +4068,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4098,7 +4098,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4128,7 +4128,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4158,7 +4158,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4188,7 +4188,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4218,7 +4218,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4248,7 +4248,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4278,7 +4278,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4308,7 +4308,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_opamp.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_opamp.h index 03ab42c70..abd81e3e4 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_opamp.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_opamp.h @@ -392,7 +392,7 @@ __STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode) * @arg @ref LL_OPAMP_MODE_FUNCTIONAL * @arg @ref LL_OPAMP_MODE_CALIBRATION */ -__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON)); } @@ -434,7 +434,7 @@ __STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t * @arg @ref LL_OPAMP_MODE_PGA_IO0_BIAS * @arg @ref LL_OPAMP_MODE_PGA_IO0_IO1_BIAS */ -__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL)); } @@ -469,7 +469,7 @@ __STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain * @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 * @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 */ -__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)); } @@ -498,7 +498,7 @@ __STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t Power * @arg @ref LL_OPAMP_POWERMODE_NORMAL * @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED */ -__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(const OPAMP_TypeDef *OPAMPx) { uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAHSM)); @@ -536,7 +536,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32 * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC2 (Only for OPAMP2) */ -__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL)); } @@ -572,7 +572,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO */ -__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(const OPAMP_TypeDef *OPAMPx) { uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL); @@ -611,7 +611,7 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t Tr * @arg @ref LL_OPAMP_TRIMMING_FACTORY * @arg @ref LL_OPAMP_TRIMMING_USER */ -__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM)); } @@ -658,7 +658,7 @@ __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uin * using two trimming steps (one with each transistors differential * pair NMOS and PMOS) */ -__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(const OPAMP_TypeDef *OPAMPx) { uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL)); @@ -675,7 +675,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(const OPAMP_TypeDef *OPAMPx) { return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT)?1UL:0UL); } @@ -728,7 +728,7 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t P * @arg @ref LL_OPAMP_TRIMMING_PMOS * @retval 0x0...0x1F */ -__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(const OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) { const __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); @@ -779,7 +779,7 @@ __STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(const OPAMP_TypeDef *OPAMPx) { return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN))?1UL:0UL); } diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rng.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rng.h index 62039d0e6..cf1ab84f1 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rng.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rng.h @@ -680,7 +680,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rtc.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rtc.h index 85e6fadda..c7c0084fc 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rtc.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rtc.h @@ -903,7 +903,7 @@ __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat * @arg @ref LL_RTC_HOURFORMAT_24HOUR * @arg @ref LL_RTC_HOURFORMAT_AMPM */ -__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); } @@ -935,7 +935,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOu * @arg @ref LL_RTC_ALARMOUT_ALMB * @arg @ref LL_RTC_ALARMOUT_WAKEUP */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); } @@ -992,7 +992,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Outpu * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE)); } @@ -1078,7 +1078,7 @@ __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polari * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW */ -__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); } @@ -1112,7 +1112,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL); } @@ -1173,7 +1173,7 @@ __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchP * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7F */ -__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); } @@ -1184,7 +1184,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); } @@ -1376,7 +1376,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 * @arg @ref LL_RTC_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); } @@ -1411,7 +1411,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); } @@ -1446,7 +1446,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); } @@ -1481,7 +1481,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); } @@ -1535,7 +1535,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(const RTC_TypeDef *RTCx) { uint32_t temp; @@ -1575,7 +1575,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL); } @@ -1617,7 +1617,7 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Sub second value (number between 0 and 65535) */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); } @@ -1674,7 +1674,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x99 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); } @@ -1713,7 +1713,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); } @@ -1767,7 +1767,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); } @@ -1797,7 +1797,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); } @@ -1865,7 +1865,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin * @param RTCx RTC Instance * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). */ -__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(const RTC_TypeDef *RTCx) { uint32_t temp; @@ -1944,7 +1944,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMA_MASK_SECONDS * @arg @ref LL_RTC_ALMA_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); } @@ -1994,7 +1994,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); } @@ -2031,7 +2031,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); } @@ -2058,7 +2058,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); } @@ -2086,7 +2086,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } @@ -2114,7 +2114,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); } @@ -2142,7 +2142,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); } @@ -2214,7 +2214,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); } @@ -2237,7 +2237,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); } @@ -2310,7 +2310,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMB_MASK_SECONDS * @arg @ref LL_RTC_ALMB_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); } @@ -2360,7 +2360,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } @@ -2397,7 +2397,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); } @@ -2424,7 +2424,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); } @@ -2452,7 +2452,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); } @@ -2480,7 +2480,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); } @@ -2508,7 +2508,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } @@ -2580,7 +2580,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); } @@ -2603,7 +2603,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); } @@ -2689,7 +2689,7 @@ __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); } @@ -2702,7 +2702,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TS_TIME_FORMAT_AM * @arg @ref LL_RTC_TS_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); } @@ -2715,7 +2715,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); } @@ -2728,7 +2728,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); } @@ -2741,7 +2741,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); } @@ -2759,7 +2759,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); @@ -2778,7 +2778,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); } @@ -2803,7 +2803,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); } @@ -2816,7 +2816,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2833,7 +2833,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of Weekday, Day and Month */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2844,7 +2844,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); } @@ -3070,7 +3070,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Dura * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH)); } @@ -3101,7 +3101,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t Fi * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT)); } @@ -3140,7 +3140,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t S * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ)); } @@ -3490,7 +3490,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL); } @@ -3527,7 +3527,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupCl * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); } @@ -3551,7 +3551,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Val * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); } @@ -3656,7 +3656,7 @@ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe * @arg @ref LL_RTC_BKP_DR31 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) +__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister) { uint32_t tmp; @@ -3707,7 +3707,7 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data) +__STATIC_INLINE void LL_RTC_BKP_SetRegister(const TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data) { uint32_t tmp; @@ -3805,7 +3805,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Freque * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); } @@ -3832,7 +3832,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL); } @@ -3865,7 +3865,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) * @arg @ref LL_RTC_CALIB_PERIOD_16SEC * @arg @ref LL_RTC_CALIB_PERIOD_8SEC */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); } @@ -3890,7 +3890,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); } @@ -3911,7 +3911,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)) ? 1UL : 0UL); } @@ -3922,7 +3922,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL); } @@ -3933,7 +3933,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL); } @@ -3944,7 +3944,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL); } @@ -3955,7 +3955,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL); } @@ -3966,7 +3966,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL); } @@ -3977,7 +3977,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL); } @@ -3988,7 +3988,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL); } @@ -3999,7 +3999,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL); } @@ -4010,7 +4010,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL); } @@ -4120,7 +4120,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL); } @@ -4131,7 +4131,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL); } @@ -4153,7 +4153,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL); } @@ -4164,7 +4164,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL); } @@ -4175,7 +4175,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL); } @@ -4186,7 +4186,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL); } @@ -4197,7 +4197,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL); } @@ -4801,7 +4801,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL); } @@ -4812,7 +4812,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL); } @@ -4823,7 +4823,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL); } @@ -4834,7 +4834,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL); } @@ -4846,7 +4846,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL); } @@ -4857,7 +4857,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL); @@ -4869,7 +4869,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL); } @@ -4880,7 +4880,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL); } diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_sdmmc.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_sdmmc.h index 6e12084e4..9887fe0ec 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_sdmmc.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_sdmmc.h @@ -30,7 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_Driver * @{ */ - +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup SDMMC_LL * @{ */ @@ -61,10 +61,10 @@ typedef struct uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ -#if (USE_SD_TRANSCEIVER != 0U) +#if (USE_SD_TRANSCEIVER != 0U) || (USE_SDIO_TRANSCEIVER != 0U) uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ -#endif /* USE_SD_TRANSCEIVER */ +#endif /* USE_SD_TRANSCEIVER || USE_SDIO_TRANSCEIVER */ } SDMMC_InitTypeDef; @@ -160,84 +160,128 @@ typedef struct #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ +/** + * @brief Masks for R5 Response + */ +/** this is the reserved for future use in spec RFU */ +#define SDMMC_SDIO_R5_ERROR ((uint32_t)0x00000400U) +/** Out of range error */ +#define SDMMC_SDIO_R5_OUT_OF_RANGE ((uint32_t)0x00000100U) +/** Invalid function number */ +#define SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER ((uint32_t)0x00000200U) +/** General or an unknown error */ +#define SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00000800U) +/** SDIO Card current state + * 00=DIS (card not selected) + * 01=CMD (data line free) + * 10=TRN (transfer on data lines) */ +#define SDMMC_SDIO_R5_IO_CURRENT_STATE ((uint32_t)0x00003000U) +/** Illegal command error */ +#define SDMMC_SDIO_R5_ILLEGAL_CMD ((uint32_t)0x00004000U) +/** CRC check of previous cmd failed */ +#define SDMMC_SDIO_R5_COM_CRC_FAILED ((uint32_t)0x00008000U) + +#define SDMMC_SDIO_R5_ERRORBITS (SDMMC_SDIO_R5_COM_CRC_FAILED | \ + SDMMC_SDIO_R5_ILLEGAL_CMD | \ + SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR | \ + SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER | \ + SDMMC_SDIO_R5_OUT_OF_RANGE) +/** + * @brief SDIO_CMD53_MODE + */ +#define SDMMC_SDIO_MODE_BYTE 0x00U /*!< Byte Mode */ +#define SDMMC_SDIO_MODE_BLOCK 0x01U /*!< Block Mode */ + +/** + * @brief SDIO_CMD53_OP_CODE + */ +#define SDMMC_SDIO_NO_INC 0x00U /*!< No auto indentation */ +#define SDMMC_SDIO_AUTO_INC 0x01U /*!< Auto indentation */ + +/** + * @brief SDIO_CMD53_RAW + */ +#define SDMMC_SDIO_WO 0x00U /*!< Write only Flag */ +#define SDMMC_SDIO_RAW 0x01U /*!< Read after write Flag */ + /** * @brief SDMMC Commands Index */ -#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ -#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ -#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ -#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ -#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ -#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ -#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ -#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ -#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ -#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ -#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ -#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ -#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ -#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ -#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ -#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ +#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ +#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_VOLTAGE_SWITCH 11U /*!< SD card Voltage switch to 1.8V mode. */ +#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ /*!< for SDHS and SDXC. */ -#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ -#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ -#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ -#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ -#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ -#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ -#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ -#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ -#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ -#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ -#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ -#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ -#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ -#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ -#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ -#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ +#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ +#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ +#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ +#define SDMMC_CMD_NO_CMD 64U /*!< No command */ /** * @brief Following commands are SD Card Specific commands. * SDMMC_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ -#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ -#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ -#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ -#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ -#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ -#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ -#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ /** * @brief Following commands are MMC Specific commands. */ -#define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */ +#define SDMMC_CMD_MMC_SLEEP_AWAKE 5U /*!< Toggle the device between Sleep state and Standby state. */ /** * @brief Following commands are SD Card Specific security commands. * SDMMC_CMD_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) -#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) -#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) -#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) -#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) -#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) -#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) -#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) -#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) +#define SDMMC_CMD_SD_APP_GET_MKB 43U +#define SDMMC_CMD_SD_APP_GET_MID 44U +#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U +#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U +#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U +#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U +#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U /** * @brief Masks for errors Card Status R1 (OCR Register) @@ -291,9 +335,14 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) -#ifndef SDMMC_DATATIMEOUT +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */ #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_DATATIMEOUT */ + +#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ +#define SDMMC_SWDATATIMEOUT ((uint32_t)0xFFFFFFFFU) +#endif /* SDMMC_SWDATATIMEOUT */ + #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) @@ -303,6 +352,8 @@ typedef struct #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) +/* SDMMC FIFO Size */ +#define SDMMC_FIFO_SIZE 32U /** * @brief Command Class supported */ @@ -543,9 +594,11 @@ typedef struct * @{ */ #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) +#define SDMMC_TRANSFER_MODE_SDIO SDMMC_DCTRL_DTMODE_0 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ + ((MODE) == SDMMC_TRANSFER_MODE_SDIO) || \ ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) /** * @} @@ -657,6 +710,82 @@ typedef struct * @} */ +/** @defgroup SDMMC_SDIO_CCCR_Registers + * @{ + */ +/*-------------------------------- CCCR0 ----------------------------------*/ +#define SDMMC_SDIO_CCCR0 0x000U /*!< SDIOS Card Common Control Register 0 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE0 0x000U /*!< SDIOS Card Common Control Register 0 Byte 0 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE1 0x001U /*!< SDIOS Card Common Control Register 0 Byte 1 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE2 0x002U /*!< SDIOS Card Common Control Register 0 Byte 2 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE3 0x003U /*!< SDIOS Card Common Control Register 0 Byte 3 */ + +/*-------------------------------- CCCR4 ----------------------------------*/ +#define SDMMC_SDIO_CCCR4 0x004U /*!< SDIOS Card Common Control Register 4 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE0 0x004U /*!< SDIOS Card Common Control Register 4 Byte 0 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE1 0x005U /*!< SDIOS Card Common Control Register 4 Byte 1 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE2 0x006U /*!< SDIOS Card Common Control Register 4 Byte 2 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE3 0x007U /*!< SDIOS Card Common Control Register 4 Byte 3 */ + +/*-------------------------------- CCCR8 ----------------------------------*/ +#define SDMMC_SDIO_CCCR8 0x008U /*!< SDIOS Card Common Control Register 8 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE0 0x008U /*!< SDIOS Card Common Control Register 8 Byte 0 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE1 0x009U /*!< SDIOS Card Common Control Register 8 Byte 1 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE2 0x00AU /*!< SDIOS Card Common Control Register 8 Byte 2 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE3 0x00BU /*!< SDIOS Card Common Control Register 8 Byte 3 */ + +/*-------------------------------- CCCR12 ---------------------------------*/ +#define SDMMC_SDIO_CCCR12 0x00CU /*!< SDIOS Card Common Control Register 12 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE0 0x00CU /*!< SDIOS Card Common Control Register 12 Byte 0 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE1 0x00DU /*!< SDIOS Card Common Control Register 12 Byte 1 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE2 0x00EU /*!< SDIOS Card Common Control Register 12 Byte 2 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE3 0x00FU /*!< SDIOS Card Common Control Register 12 Byte 3 */ + +/*-------------------------------- CCCR16 ---------------------------------*/ +#define SDMMC_SDIO_CCCR16 0x010U /*!< SDIOS Card Common Control Register 16 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE0 0x010U /*!< SDIOS Card Common Control Register 16 Byte 0 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE1 0x011U /*!< SDIOS Card Common Control Register 16 Byte 1 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE2 0x012U /*!< SDIOS Card Common Control Register 16 Byte 2 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE3 0x013U /*!< SDIOS Card Common Control Register 16 Byte 3 */ + +/*-------------------------------- CCCR20 ---------------------------------*/ +#define SDMMC_SDIO_CCCR20 0x014U /*!< SDIOS Card Common Control Register 20 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE0 0x014U /*!< SDIOS Card Common Control Register 20 Byte 0 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE1 0x015U /*!< SDIOS Card Common Control Register 20 Byte 1 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE2 0x016U /*!< SDIOS Card Common Control Register 20 Byte 2 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE3 0x017U /*!< SDIOS Card Common Control Register 20 Byte 3 */ + +/*-------------------------------- F1BR0 ----------------------------------*/ +#define SDMMC_SDIO_F1BR0 0x100U /*!< SDIOS Function 1 Basic Register 0 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE0 0x100U /*!< SDIOS Function 1 Basic Register 0 Byte 0 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE1 0x101U /*!< SDIOS Function 1 Basic Register 0 Byte 1 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE2 0x102U /*!< SDIOS Function 1 Basic Register 0 Byte 2 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE3 0x103U /*!< SDIOS Function 1 Basic Register 0 Byte 3 */ + +/*-------------------------------- F1BR8 ----------------------------------*/ +#define SDMMC_SDIO_F1BR8 0x108U /*!< SDIOS Function 1 Basic Register 8 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE0 0x108U /*!< SDIOS Function 1 Basic Register 8 Byte 0 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE1 0x109U /*!< SDIOS Function 1 Basic Register 8 Byte 1 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE2 0x10AU /*!< SDIOS Function 1 Basic Register 8 Byte 2 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE3 0x10BU /*!< SDIOS Function 1 Basic Register 8 Byte 3 */ + +/*-------------------------------- F1BR12 ---------------------------------*/ +#define SDMMC_SDIO_F1BR12 0x10CU /*!< SDIOS Function 1 Basic Register 12 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE0 0x10CU /*!< SDIOS Function 1 Basic Register 12 Byte 0 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE1 0x10DU /*!< SDIOS Function 1 Basic Register 12 Byte 1 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE2 0x10EU /*!< SDIOS Function 1 Basic Register 12 Byte 2 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE3 0x10FU /*!< SDIOS Function 1 Basic Register 12 Byte 3 */ + +/*-------------------------------- F1BR16 ---------------------------------*/ +#define SDMMC_SDIO_F1BR16 0x110U /*!< SDIOS Function 1 Basic Register 16 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE0 0x110U /*!< SDIOS Function 1 Basic Register 16 Byte 0 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE1 0x111U /*!< SDIOS Function 1 Basic Register 16 Byte 1 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE2 0x112U /*!< SDIOS Function 1 Basic Register 16 Byte 2 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE3 0x113U /*!< SDIOS Function 1 Basic Register 16 Byte 3 */ +/** + * @} + */ + /** * @} */ @@ -871,6 +1000,38 @@ typedef struct */ #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) +/** + * @brief Checks the source of specified interrupt. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval The new state of SDMMC_IT (SET or RESET). + */ +#define __SDMMC_GET_IT_SOURCE(__INSTANCE__, __INTERRUPT__) (((__HANDLE__)->Instance->STA & (__INTERRUPT__))) + /** * @brief Clears the SDMMC's interrupt pending bits. * @param __INSTANCE__ Pointer to SDMMC register base @@ -1009,7 +1170,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); /** @addtogroup HAL_SDMMC_LL_Group2 * @{ */ -uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); /** * @} @@ -1022,17 +1183,17 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx); /* Command path state machine (CPSM) management functions */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); -uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command); +uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response); /* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); -uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data); +uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx); /* SDMMC Cards mode management functions */ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); @@ -1073,6 +1234,10 @@ uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount); +uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse); +uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp); /** * @} */ @@ -1084,6 +1249,8 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp); +uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData); uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** @@ -1106,7 +1273,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** * @} */ - +#endif /* SDMMC1 || SDMMC2 */ /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_swpmi.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_swpmi.h index c2b31d604..06568c7b1 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_swpmi.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_swpmi.h @@ -63,24 +63,30 @@ typedef struct uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class. This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */ + This feature can be modified afterwards using unitary + function @ref LL_SWPMI_SetVoltageClass. */ uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler. - This parameter must be a number between Min_Data=0 and Max_Data=255U. + This parameter must be a number between Min_Data=0 + and Max_Data=255U. - The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER + The value can be calculated thanks to helper + macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */ + This feature can be modified afterwards using unitary + function @ref LL_SWPMI_SetBitRatePrescaler. */ uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode. This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */ + This feature can be modified afterwards using + unitary function @ref LL_SWPMI_SetTransmissionMode. */ uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode. This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */ + This feature can be modified afterwards using + unitary function @ref LL_SWPMI_SetReceptionMode. */ } LL_SWPMI_InitTypeDef; /** @@ -266,7 +272,7 @@ __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t R * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI */ -__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE)); } @@ -294,7 +300,7 @@ __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_ * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI */ -__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE)); } @@ -351,7 +357,7 @@ __STATIC_INLINE void LL_SWPMI_DisableTransceiver(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPEN) == (SWPMI_CR_SWPEN)) ? 1UL : 0UL); } @@ -381,7 +387,7 @@ __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActivated(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL); } @@ -428,7 +434,7 @@ __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_ * @param SWPMIx SWPMI Instance * @retval A number between Min_Data=0 and Max_Data=255U */ -__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR)); } @@ -455,7 +461,7 @@ __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t Vo * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B */ -__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS)); } @@ -474,7 +480,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL); } @@ -485,7 +491,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL); } @@ -496,7 +502,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL); } @@ -507,7 +513,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL); } @@ -518,7 +524,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL); } @@ -530,7 +536,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL); } @@ -542,7 +548,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL); } @@ -554,7 +560,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL); } @@ -566,7 +572,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL); } @@ -577,7 +583,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL); } @@ -588,7 +594,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL); } @@ -599,7 +605,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RDYF) == (SWPMI_ISR_RDYF)) ? 1UL : 0UL); } @@ -926,7 +932,7 @@ __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RDYIE) == (SWPMI_IER_RDYIE)) ? 1UL : 0UL); } @@ -937,7 +943,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL); } @@ -948,7 +954,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL); } @@ -959,7 +965,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL); } @@ -970,7 +976,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL); } @@ -981,7 +987,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL); } @@ -992,7 +998,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL); } @@ -1003,7 +1009,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL); } @@ -1014,7 +1020,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL); } @@ -1025,7 +1031,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL); } @@ -1066,7 +1072,7 @@ __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL); } @@ -1099,7 +1105,7 @@ __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL); } @@ -1114,19 +1120,19 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) * @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(const SWPMI_TypeDef *SWPMIx, uint32_t Direction) { uint32_t data_reg_addr; if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ - data_reg_addr = (uint32_t)&(SWPMIx->TDR); + data_reg_addr = (uint32_t) &(SWPMIx->TDR); } else { /* return address of RDR register */ - data_reg_addr = (uint32_t)&(SWPMIx->RDR); + data_reg_addr = (uint32_t) &(SWPMIx->RDR); } return data_reg_addr; @@ -1146,7 +1152,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t * @param SWPMIx SWPMI Instance * @retval Value between Min_Data=0x00 and Max_Data=0x1F */ -__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL)); } @@ -1210,8 +1216,8 @@ __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx) * @{ */ -ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx); -ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct); +ErrorStatus LL_SWPMI_DeInit(const SWPMI_TypeDef *SWPMIx); +ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, const LL_SWPMI_InitTypeDef *SWPMI_InitStruct); void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct); /** diff --git a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_wwdg.h b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_wwdg.h index eef033dd6..a8625e967 100644 --- a/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_wwdg.h +++ b/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_wwdg.h @@ -135,7 +135,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); } @@ -162,7 +162,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Counter value */ -__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CR, WWDG_CR_T)); } @@ -203,7 +203,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale * @arg @ref LL_WWDG_PRESCALER_64 * @arg @ref LL_WWDG_PRESCALER_128 */ -__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); } @@ -235,7 +235,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Window value */ -__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); } @@ -256,7 +256,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); } @@ -298,7 +298,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); } diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal.c index 468fd83a0..45a804a9a 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal.c @@ -51,7 +51,7 @@ */ #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ #define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */ -#define __STM32H7xx_HAL_VERSION_SUB2 (0x03UL) /*!< [15:8] sub2 version */ +#define __STM32H7xx_HAL_VERSION_SUB2 (0x04UL) /*!< [15:8] sub2 version */ #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_adc.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_adc.c index 74cf03aec..855ea82de 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_adc.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_adc.c @@ -2341,7 +2341,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC group regular conversion data */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3022,11 +3022,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { - /* Set sampling time of the selected ADC channel */ - /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, - (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), - sConfig->SamplingTime); + /* Set ADC channel preselection of corresponding negative channel */ + LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfig->Channel)); } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ @@ -3494,7 +3491,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3508,7 +3505,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) * @param hadc ADC handle * @retval ADC error code (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_adc_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_adc_ex.c index 749473f77..b2dc363b8 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_adc_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_adc_ex.c @@ -197,7 +197,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval Calibration value. */ -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1016,7 +1016,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status; ADC_HandleTypeDef tmphadcSlave; @@ -1277,7 +1277,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) * @retval The converted data values. */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc) { const ADC_Common_TypeDef *tmpADC_Common; @@ -1323,7 +1323,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 * @retval ADC group injected conversion data */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { uint32_t tmp_jdr; @@ -2296,8 +2296,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { - /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); + /* Set ADC channel preselection of corresponding negative channel */ + LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfigInjected->InjectedChannel)); } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_comp.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_comp.c index 165c09e37..621a0a05d 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_comp.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_comp.c @@ -1148,7 +1148,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) * @arg @ref COMP_OUTPUT_LEVEL_HIGH * */ -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); @@ -1201,7 +1201,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval HAL state */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp) { /* Check the COMP handle allocation */ if(hcomp == NULL) @@ -1221,7 +1221,7 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) * @param hcomp COMP handle * @retval COMP error code */ -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp) { /* Check the parameters */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cordic.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cordic.c index 7eea29cb6..da6b810bb 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cordic.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cordic.c @@ -164,12 +164,12 @@ static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAError(DMA_HandleTypeDef *hdma); + /** * @} */ /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions * @{ */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cortex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cortex.c index e272cfc2d..5c158d532 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cortex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cortex.c @@ -327,7 +327,7 @@ void HAL_MPU_DisableRegion(uint32_t RegionNumber) * the initialization and configuration information. * @retval None */ -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init) { /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_crc_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_crc_ex.c index b4ba3de35..c814b2871 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_crc_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cryp.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cryp.c index 61d732e4b..942c1e013 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cryp.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cryp.c @@ -74,7 +74,7 @@ the CRYP peripheral is configured and processes the buffer in input. At second call, no need to Initialize the CRYP, user have to get current configuration via HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set - new parametres, finally user can start encryption/decryption. + new parameters, finally user can start encryption/decryption. (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. @@ -1741,7 +1741,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) * the configuration information for the CRYP IP * @retval CRYP error code */ -uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) +uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp) { return hcryp->ErrorCode; } @@ -1752,7 +1752,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) * the configuration information for CRYP module. * @retval HAL state */ -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp) { return hcryp->State; } @@ -4434,7 +4434,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u uint32_t loopcounter; uint32_t size_in_bytes; uint32_t tmp; - uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU}; + const uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU}; /***************************** Header phase for GCM/GMAC or CCM *********************************/ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cryp_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cryp_ex.c index ddce86e43..5dee88e2f 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cryp_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_cryp_ex.c @@ -108,7 +108,7 @@ * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout) { uint32_t tickstart; uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */ @@ -274,7 +274,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout) { uint32_t tagaddr = (uint32_t)AuthTag; uint32_t ctr0 [4] = {0}; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dac.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dac.c index a5e622518..020767700 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dac.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dac.c @@ -1065,6 +1065,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } + else + { + /* In case of mode normal and buffer disabled, connection to both on chip periph and external pin is not possible */ + if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_DISABLE) + { + assert_param(sConfig->DAC_ConnectOnChipPeripheral != DAC_CHIPCONNECT_BOTH); + } + } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dac_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dac_ex.c index 15d998a43..e2b8e6aea 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dac_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dac_ex.c @@ -666,8 +666,8 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Init trimming counter */ /* Medium value */ - trimmingvalue = 16UL; - delta = 8UL; + trimmingvalue = 0x10UL; + delta = 0x08UL; while (delta != 0UL) { /* Set candidate trimming */ @@ -713,8 +713,12 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { - /* Trimming is actually one value more */ - trimmingvalue++; + /* Check trimming value below maximum */ + if (trimmingvalue < 0x1FU) + { + /* Trimming is actually one value more */ + trimmingvalue++; + } /* Set right trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); } @@ -787,8 +791,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval Trimming value : range: 0->31 - * + * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel) { diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dcmi.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dcmi.c index e1549e247..980270258 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dcmi.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dcmi.c @@ -914,7 +914,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn * the configuration information for DCMI. * @retval HAL state */ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi) { return hdcmi->State; } @@ -925,7 +925,7 @@ HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) * the configuration information for DCMI. * @retval DCMI Error Code */ -uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) +uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi) { return hdcmi->ErrorCode; } diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dma.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dma.c index dada223e6..871474105 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dma.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dma.c @@ -174,7 +174,7 @@ typedef struct */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma); static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); @@ -1733,7 +1733,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca * the configuration information for the specified DMA Stream. * @retval HAL state */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma) { return hdma->State; } @@ -1744,7 +1744,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Stream. * @retval DMA Error Code */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; } @@ -1893,7 +1893,7 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Stream. * @retval HAL status */ -static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dma2d.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dma2d.c index 520841c9f..e85122ce7 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dma2d.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dma2d.c @@ -323,7 +323,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) /* Before aborting any DMA2D transfer or CLUT loading, check first whether or not DMA2D clock is enabled */ - if (__HAL_RCC_DMA2D_IS_CLK_ENABLED()) + if (__HAL_RCC_DMA2D_IS_CLK_ENABLED() == 1U) { /* Abort DMA2D transfer if any */ if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START) @@ -1013,7 +1013,8 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); @@ -1067,7 +1068,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLU * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ @@ -1770,7 +1771,7 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) */ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { - DMA2D_LayerCfgTypeDef *pLayerCfg; + const DMA2D_LayerCfgTypeDef *pLayerCfg; uint32_t regMask; uint32_t regValue; @@ -2062,7 +2063,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t * the configuration information for the DMA2D. * @retval HAL state */ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d) { return hdma2d->State; } @@ -2073,7 +2074,7 @@ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) * the configuration information for DMA2D. * @retval DMA2D Error Code */ -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d) { return hdma2d->ErrorCode; } diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dts.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dts.c index 9f122a49b..3b9b85a20 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dts.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_dts.c @@ -948,7 +948,7 @@ __weak void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts) * @param hdts DTS handle * @retval HAL state */ -HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts) +HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts) { /* Check the DTS handle allocation */ if (hdts == NULL) diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_eth.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_eth.c index 183eda6b4..c4b31a89c 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_eth.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_eth.c @@ -1074,7 +1074,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) heth->RxDescList.RxDataLength = 0; } - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + /* Get the Frame Length of the received packet */ bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; /* Check if last descriptor */ @@ -1218,7 +1218,7 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) if (heth->RxDescList.RxBuildDescCnt != desccount) { /* Set the tail pointer index */ - tailidx = (descidx + 1U) % ETH_RX_DESC_CNT; + tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT; /* DMB instruction to avoid race condition */ __DMB(); @@ -1438,7 +1438,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) #ifdef HAL_ETH_USE_PTP /* Disable Ptp transmission */ - CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U)); + CLEAR_BIT(heth->Init.TxDesc[idx].DESC2, ETH_DMATXNDESCRF_TTSE); if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD) && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS)) @@ -1515,6 +1515,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT return HAL_ERROR; } + /* Mask the Timestamp Trigger interrupt */ + CLEAR_BIT(heth->Instance->MACIER, ETH_MACIER_TSIE); + tmpTSCR = ptpconfig->Timestamp | ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) | ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) | @@ -1548,8 +1551,11 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT } } - /* Ptp Init */ - SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); + /* Enable Update mode */ + if (ptpconfig->TimestampUpdateMode == ENABLE) + { + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT); + } /* Set PTP Configuration done */ heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED; @@ -1561,6 +1567,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT HAL_ETH_PTP_SetTime(heth, &time); + /* Ptp Init */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); + /* Return function status */ return HAL_OK; } @@ -2500,7 +2509,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_ ((uint32_t)pFilterConfig->HashMulticast << 2) | ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | ((uint32_t)pFilterConfig->PassAllMulticast << 4) | - ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | + ((uint32_t)((pFilterConfig->BroadcastFilter == ENABLE) ? 1U : 0U) << 5) | ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | @@ -2533,7 +2542,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_ pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE; - pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE; + pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) > 0U) ? ENABLE : DISABLE; pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF); pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; @@ -2781,6 +2790,16 @@ uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth) return heth->MACWakeUpEvent; } +/** + * @brief Returns the ETH Tx Buffers in use number + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH Tx Buffers in use number + */ +uint32_t HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth) +{ + return heth->TxDescList.BuffersInUse; +} /** * @} */ @@ -3065,7 +3084,7 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @param pTxConfig: Tx packet configuration - * @param ItMode: Enable or disable Tx EOT interrept + * @param ItMode: Enable or disable Tx EOT interrupt * @retval Status */ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_exti.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_exti.c index fe54a0374..07825da41 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_exti.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_exti.c @@ -509,7 +509,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT * @param hexti Exti handle. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; @@ -682,7 +682,7 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin * @param hexti Exti handle. * @retval none. */ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; @@ -734,9 +734,9 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) * This parameter is kept for compatibility with other series. * @retval 1 if interrupt is pending else 0. */ -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) { - __IO uint32_t *regaddr; + const __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; @@ -785,7 +785,7 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) * This parameter is kept for compatibility with other series. * @retval None. */ -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) { __IO uint32_t *regaddr; uint32_t maskline; @@ -827,7 +827,7 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) * @param hexti Exti handle. * @retval None. */ -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t maskline; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_flash_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_flash_ex.c index bed7b5e75..7a1e2d76f 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_flash_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_flash_ex.c @@ -1020,26 +1020,26 @@ void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData) */ void HAL_FLASHEx_BusFault_IRQHandler(void) { - /* Check if the ECC double error occured*/ + /* Check if the ECC double error occurred*/ if ((FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1) != 0) { /* FLASH ECC detection user callback */ HAL_FLASHEx_EccDetectionCallback(); /* Clear Bank 1 ECC double detection error flag - note : this step will clear all the informations related to the flash ECC detection + note : this step will clear all the information related to the flash ECC detection */ __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_DBECCERR_BANK1); } #if defined (DUAL_BANK) - /* Check if the ECC double error occured*/ + /* Check if the ECC double error occurred*/ if ((FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2) != 0) { /* FLASH ECC detection user callback */ HAL_FLASHEx_EccDetectionCallback(); /* Clear Bank 2 ECC double detection error flag - note : this step will clear all the informations related to the flash ECC detection + note : this step will clear all the information related to the flash ECC detection */ __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_DBECCERR_BANK2); } diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_fmac.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_fmac.c index f4cebd05d..306073b60 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_fmac.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_fmac.c @@ -204,7 +204,6 @@ not defined, the callback registration feature is not available and weak callbacks are used. - @endverbatim * */ @@ -229,7 +228,6 @@ /** @defgroup FMAC_Private_Constants FMAC Private Constants * @{ */ - #define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU) #define MAX_PRELOAD_INDEX 0xFFU #define PRELOAD_ACCESS_DMA 0x00U @@ -322,7 +320,6 @@ /* Private variables ---------------------------------------------------------*/ /* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac); @@ -348,7 +345,6 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma); static void FMAC_DMAError(DMA_HandleTypeDef *hdma); /* Functions Definition ------------------------------------------------------*/ - /** @defgroup FMAC_Exported_Functions FMAC Exported Functions * @{ */ @@ -1203,7 +1199,7 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti */ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check handle state is ready */ if (hfmac->State == HAL_FMAC_STATE_READY) @@ -1222,11 +1218,24 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { (*(hfmac->pInputSize)) = hfmac->InputCurrentSize; } + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL)) { (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize; } + if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA) + { + /* Disable the DMA stream managing FMAC input data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaIn); + } + + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA) && (status == HAL_OK)) + { + /* Disable the DMA stream managing FMAC output data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaOut); + } + /* Reset FMAC unit (internal pointers) */ if (FMAC_Reset(hfmac) == HAL_ERROR) { @@ -1239,8 +1248,6 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { /* Reset the data pointers */ FMAC_ResetDataPointers(hfmac); - - status = HAL_OK; } /* Reset the busy flag */ @@ -2410,7 +2417,6 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma) #else HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ - } /** @@ -2516,11 +2522,11 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma) HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ } + /** * @} */ - /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_gfxmmu.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_gfxmmu.c index 7e771a792..f6961785f 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_gfxmmu.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_gfxmmu.c @@ -518,7 +518,7 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @param Address Start address of LUT in flash. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address) @@ -570,7 +570,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber) { @@ -615,7 +615,7 @@ HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, * @param lutLine LUT line parameters. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine) +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine) { HAL_StatusTypeDef status = HAL_OK; @@ -841,7 +841,7 @@ __weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu) * @param hgfxmmu GFXMMU handle. * @retval GFXMMU state. */ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu) +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu) { /* Return GFXMMU handle state */ return hgfxmmu->State; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_gpio.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_gpio.c index 3580f78a5..7133e81e7 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_gpio.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_gpio.c @@ -162,7 +162,7 @@ * the configuration information for the specified GPIO peripheral. * @retval None */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) { uint32_t position = 0x00U; uint32_t iocurrent; @@ -386,7 +386,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { GPIO_PinState bitstatus; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hash.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hash.c index 8bc984da5..27513cfa7 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hash.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hash.c @@ -272,10 +272,10 @@ */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size); static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash); static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash); static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout); @@ -764,7 +764,8 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -790,7 +791,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -805,7 +806,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -822,7 +823,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -848,7 +850,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -863,7 +865,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -911,7 +913,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -935,7 +937,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -949,7 +951,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -965,7 +967,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -990,7 +992,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1004,7 +1006,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1077,7 +1079,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1107,7 +1109,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1164,7 +1166,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutB * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -1183,7 +1186,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -1225,7 +1229,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -1243,7 +1247,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1254,7 +1258,6 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ - /** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode * @brief HMAC processing functions using DMA modes. * @@ -1297,7 +1300,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1322,7 +1325,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1369,7 +1372,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI * @param hhash HASH handle. * @retval HAL HASH state */ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash) { return hhash->State; } @@ -1382,7 +1385,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) * @param hhash HASH handle. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) +HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash) { return hhash->Status; } @@ -1400,7 +1403,7 @@ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. * @retval None */ -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) +void HAL_HASH_ContextSaving(const HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; @@ -1441,7 +1444,7 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) * beforehand). * @retval None */ -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; @@ -1620,7 +1623,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) * @param hhash pointer to a HASH_HandleTypeDef structure. * @retval HASH Error Code */ -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash) { /* Return HASH Error Code */ return hhash->ErrorCode; @@ -1821,7 +1824,7 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma) * suspension time is stored in the handle for resumption later on. * @retval HAL status */ -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -1917,8 +1920,8 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB if ((Size % 4U) == 3U) { tmp = *(uint8_t *)inputaddr; - tmp |= (uint32_t)*(uint8_t *)(inputaddr + 1U) << 8U; - tmp |= (uint32_t)*(uint8_t *)(inputaddr + 2U) << 16U; + tmp |= (uint32_t) * (uint8_t *)(inputaddr + 1U) << 8U; + tmp |= (uint32_t) * (uint8_t *)(inputaddr + 2U) << 16U; HASH->DIN = tmp; } @@ -1927,7 +1930,6 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB { HASH->DIN = *(uint32_t *)inputaddr; } - /*hhash->HashInCount += 4U;*/ } @@ -1940,7 +1942,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size message digest size in bytes. * @retval None */ -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; @@ -2005,7 +2007,6 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) } - /** * @brief Handle HASH processing Timeout. * @param hhash HASH handle. @@ -2491,10 +2492,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2526,7 +2528,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Set the phase */ @@ -2542,7 +2544,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; Size_tmp = hhash->HashInCount; } /* ... or multi-buffer HASH processing end */ @@ -2550,7 +2552,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint { /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; + pInBuffer_tmp = (const uint8_t *)pInBuffer; Size_tmp = Size; /* Configure the number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(Size); @@ -2628,9 +2630,10 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2662,7 +2665,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */ } @@ -2673,7 +2676,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Check if initialization phase has already be performed */ @@ -2731,7 +2734,8 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -2841,7 +2845,6 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff } - /** * @brief Initialize the HASH peripheral, next process pInBuffer then * read the computed digest in interruption mode. @@ -2853,7 +2856,8 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2902,6 +2906,19 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ } + else if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) && (SizeVar < 4U)) + { + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) + { + /* It remains data to enter and the Peripheral is ready to trigger DINIE,carry on as usual. + Update HashInCount and pHashInBuffPtr accordingly. */ + hhash->HashInCount = SizeVar; + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; + /* Update the configuration of the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(SizeVar); + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + } + } else { initialization_skipped = 1; /* info user later on in case of multi-buffer */ @@ -3011,7 +3028,8 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; @@ -3188,7 +3206,8 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, ui * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3252,7 +3271,6 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint } - /** * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then * read the computed digest in interruption mode. @@ -3266,7 +3284,8 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3361,7 +3380,6 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u } - /** * @brief Initialize the HASH peripheral in HMAC mode then initiate the required * DMA transfers to feed the key and the input buffer to the Peripheral. @@ -3377,7 +3395,8 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hash_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hash_ex.c index 86b7030c5..00c4340c9 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hash_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hash_ex.c @@ -86,8 +86,6 @@ #include "stm32h7xx_hal.h" - - /** @addtogroup STM32H7xx_HAL_Driver * @{ */ @@ -148,7 +146,7 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -174,7 +172,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -189,7 +187,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -206,7 +204,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -232,7 +230,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -247,7 +245,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -290,7 +288,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -314,7 +312,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -328,7 +326,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -344,7 +343,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -368,7 +367,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -382,7 +381,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -422,8 +422,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin */ - - /** * @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer * to feed the input buffer to the Peripheral. @@ -434,7 +432,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -464,7 +462,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -507,7 +505,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p */ - /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then * read the computed digest. @@ -521,7 +518,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -540,7 +537,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -570,7 +567,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI */ - /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then * read the computed digest in interrupt mode. @@ -583,7 +579,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -601,15 +597,13 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); } - - /** * @} */ @@ -639,7 +633,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t */ - /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required * DMA transfers to feed the key and the input buffer to the Peripheral. @@ -659,7 +652,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -683,7 +676,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -759,7 +752,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -780,7 +773,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -806,7 +799,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -829,7 +822,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -850,7 +843,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -876,7 +869,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -898,7 +891,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -919,7 +913,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -945,7 +939,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -967,7 +962,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); @@ -988,7 +984,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -1014,7 +1010,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hcd.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hcd.c index 17f99edb5..e1fbd0043 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hcd.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hcd.c @@ -1693,6 +1693,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else { hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; } } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hrtim.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hrtim.c index 2e11610e8..65efda001 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hrtim.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_hrtim.c @@ -83,7 +83,6 @@ any restriction. HRTIM waveform modes are managed through the set of functions named HAL_HRTIM_Waveform -============================================================================== ##### How to use this driver ##### ============================================================================== [..] @@ -423,62 +422,62 @@ static uint32_t TimerIdxToTimerId[] = /** @defgroup HRTIM_Private_Functions HRTIM Private Functions * @{ */ -static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); +static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); -static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); -static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimerCfgTypeDef * pTimerCfg); +static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimerCfgTypeDef *pTimerCfg); -static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef *pTimerCfg); -static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event); -static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg); +static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t Output, + const HRTIM_OutputCfgTypeDef *pOutputCfg); -static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef * pEventCfg); + const HRTIM_EventCfgTypeDef *pEventCfg); -static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event); -static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); -static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, - const DMA_HandleTypeDef * hdma); +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim, + const DMA_HandleTypeDef *hdma); -static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); -static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim); +static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim); -static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim); +static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim); -static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx); +static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx); static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma); @@ -497,7 +496,7 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma); */ /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions @verbatim =============================================================================== ##### Initialization and Time Base Configuration functions ##### @@ -518,20 +517,20 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma); * @param hhrtim pointer to HAL HRTIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) +HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim) { uint8_t timer_idx; uint32_t hrtim_mcr; /* Check the HRTIM handle allocation */ - if(hhrtim == NULL) + if (hhrtim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance)); - assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests)); + assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptRequests)); #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) if (hhrtim->State == HAL_HRTIM_STATE_RESET) @@ -660,10 +659,10 @@ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim) +HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim) { /* Check the HRTIM handle allocation */ - if(hhrtim == NULL) + if (hhrtim == NULL) { return HAL_ERROR; } @@ -696,7 +695,7 @@ HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -711,7 +710,7 @@ __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -743,16 +742,16 @@ __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim) */ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio)); assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Set the HRTIM state */ @@ -780,7 +779,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions - * @brief Simple time base mode functions. + * @brief Simple time base mode functions. @verbatim =============================================================================== ##### Simple time base mode functions ##### @@ -812,10 +811,10 @@ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -847,10 +846,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -883,10 +882,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -929,10 +928,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); /* Process Locked */ @@ -978,24 +977,24 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim, * @param Length The length of data items (data size) to be transferred * from source to destination */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -1013,12 +1012,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA transfer completed callback */ @@ -1036,14 +1035,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer repetition DMA request */ if (TimerIdx == HRTIM_TIMERINDEX_MASTER) @@ -1080,10 +1079,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -1098,7 +1097,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } /* Disable the timer repetition DMA request */ __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP); @@ -1119,12 +1118,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hdma) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } /* Disable the timer repetition DMA request */ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP); - } + } } /* Disable the timer counter */ @@ -1135,11 +1134,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } else { - return HAL_OK; + return HAL_OK; } } @@ -1148,7 +1147,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions - * @brief Simple output compare functions + * @brief Simple output compare functions @verbatim =============================================================================== ##### Simple output compare functions ##### @@ -1202,10 +1201,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, * Inactive: SETxy =0, RSTxy = CMPy * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel, + const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg) { uint32_t CompareUnit = (uint32_t)RESET; HRTIM_OutputCfgTypeDef OutputCfg; @@ -1217,9 +1216,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity)); assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -1231,27 +1230,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure timer compare unit */ switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { CompareUnit = HRTIM_COMPAREUNIT_1; hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { CompareUnit = HRTIM_COMPAREUNIT_2; hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -1262,9 +1261,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ @@ -1277,7 +1276,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, switch (pSimpleOCChannelCfg->Mode) { - case HRTIM_BASICOCMODE_TOGGLE: + case HRTIM_BASICOCMODE_TOGGLE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1291,7 +1290,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_BASICOCMODE_ACTIVE: + case HRTIM_BASICOCMODE_ACTIVE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1305,7 +1304,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_BASICOCMODE_INACTIVE: + case HRTIM_BASICOCMODE_INACTIVE: { if (CompareUnit == HRTIM_COMPAREUNIT_1) { @@ -1319,7 +1318,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -1333,9 +1332,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } HRTIM_OutputConfig(hhrtim, @@ -1376,11 +1375,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1426,11 +1425,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1481,13 +1480,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim, * Output set inactive: output reset interrupt is enabled * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t interrupt; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1540,13 +1539,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t interrupt; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); /* Process Locked */ @@ -1607,26 +1606,26 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim, * Output set inactive: output reset DMA request is enabled * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; uint32_t dma_request; /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -1639,7 +1638,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Process Locked */ __HAL_LOCK(hhrtim); - /* Enable the timer output */ + /* Enable the timer output */ hhrtim->Instance->sCommonRegs.OENR |= OCChannel; /* Get the DMA request to enable */ @@ -1650,12 +1649,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA error callback */ @@ -1666,14 +1665,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request); @@ -1714,9 +1713,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OCChannel) { uint32_t dma_request; @@ -1765,7 +1764,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions - * @brief Simple PWM output functions + * @brief Simple PWM output functions @verbatim =============================================================================== ##### Simple PWM output functions ##### @@ -1822,10 +1821,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, * enabled (otherwise the behavior is not guaranteed). * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel, + const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; uint32_t hrtim_timcr; @@ -1836,9 +1835,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse)); assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -1849,28 +1848,28 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure timer compare unit */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -1884,14 +1883,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1); - OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1); + OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1); OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE; OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; @@ -1940,11 +1939,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -1990,11 +1989,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2041,11 +2040,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2059,27 +2058,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Enable the timer interrupt (depends on the PWM output) */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2090,9 +2089,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2131,11 +2130,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); /* Process Locked */ @@ -2149,27 +2148,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer interrupt (depends on the PWM output) */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2180,9 +2179,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -2225,25 +2224,25 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim, * from source to destination * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U)) { return HAL_ERROR; } @@ -2280,39 +2279,39 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2323,9 +2322,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2364,9 +2363,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel) +HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t PWMChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); @@ -2394,27 +2393,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer DMA request */ switch (PWMChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2425,9 +2424,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -2446,7 +2445,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions - * @brief Simple input capture functions + * @brief Simple input capture functions @verbatim =============================================================================== ##### Simple input capture functions ##### @@ -2488,10 +2487,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, * edges on event channel. * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel, + const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg) { HRTIM_EventCfgTypeDef EventCfg; @@ -2505,9 +2504,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhr assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event, pSimpleCaptureChannelCfg->EventFilter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -2559,11 +2558,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhr * units. It can be used directly and is active as soon as the timing * unit counter is enabled. */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2575,19 +2574,19 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2598,9 +2597,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2630,14 +2629,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; uint32_t hrtim_cpt2cr; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2649,19 +2648,19 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2672,9 +2671,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -2712,11 +2711,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2728,7 +2727,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; @@ -2737,7 +2736,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; @@ -2746,7 +2745,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2757,9 +2756,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2790,15 +2789,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; uint32_t hrtim_cpt2cr; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2810,7 +2809,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Set the capture unit trigger */ switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -2819,7 +2818,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -2828,7 +2827,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2839,9 +2838,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -2883,16 +2882,16 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim, * from source to destination * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); @@ -2906,12 +2905,12 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (hdma == NULL) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } /* Set the DMA error callback */ @@ -2922,18 +2921,18 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { /* Set the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1; @@ -2942,7 +2941,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { /* Set the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2; @@ -2952,7 +2951,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -2961,11 +2960,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - } + } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -2996,9 +2995,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t CaptureChannel) { uint32_t hrtim_cpt1cr; @@ -3017,17 +3016,17 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; + return HAL_ERROR; } switch (CaptureChannel) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { /* Reset the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -3037,7 +3036,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { /* Reset the capture unit trigger */ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; @@ -3047,7 +3046,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3058,9 +3057,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR; @@ -3086,7 +3085,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions - * @brief Simple one pulse functions + * @brief Simple one pulse functions @verbatim =============================================================================== ##### Simple one pulse functions ##### @@ -3143,10 +3142,10 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, * second call will override the reset event related configuration data * provided in the first call. */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel, + const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; HRTIM_EventCfgTypeDef EventCfg; @@ -3163,9 +3162,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event, pSimpleOnePulseChannelCfg->EventFilter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3176,29 +3175,29 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh /* Configure timer compare unit */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse; OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; break; } - default: + default: { OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; @@ -3212,13 +3211,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Configure timer output */ - OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1); + OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1); OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1); OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE; OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; @@ -3235,7 +3234,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE; EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F); EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1); - EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS); + EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS); EventCfg.Source = HRTIM_EVENTSRC_1; HRTIM_EventConfig(hhrtim, @@ -3279,7 +3278,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel) { @@ -3329,9 +3328,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3380,9 +3379,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3398,27 +3397,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Enable the timer interrupt (depends on the OnePulse output) */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3429,9 +3428,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Enable the timer counter */ @@ -3470,9 +3469,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel) +HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t OnePulseChannel) { /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); @@ -3488,27 +3487,27 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, /* Disable the timer interrupt (depends on the OnePulse output) */ switch (OnePulseChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3519,9 +3518,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Disable the timer counter */ @@ -3540,7 +3539,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions - * @brief HRTIM configuration functions + * @brief HRTIM configuration functions @verbatim =============================================================================== ##### HRTIM configuration functions ##### @@ -3567,8 +3566,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the burst mode * controller */ -HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg) +HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg) { uint32_t hrtim_bmcr; @@ -3579,9 +3578,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable)); assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3647,9 +3646,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef* pEventCfg) + const HRTIM_EventCfgTypeDef *pEventCfg) { /* Check parameters */ assert_param(IS_HRTIM_EVENT(Event)); @@ -3659,9 +3658,9 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode)); assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3692,15 +3691,15 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler) { /* Check parameters */ assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3734,9 +3733,9 @@ HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, * enabling faults inputs * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultCfgTypeDef* pFaultCfg) + const HRTIM_FaultCfgTypeDef *pFaultCfg) { uint32_t hrtim_fltinr1; uint32_t hrtim_fltinr2; @@ -3748,9 +3747,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter)); assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3764,7 +3763,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, switch (Fault) { - case HRTIM_FAULT_1: + case HRTIM_FAULT_1: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK); hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P); @@ -3774,7 +3773,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_2: + case HRTIM_FAULT_2: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P); @@ -3784,7 +3783,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_3: + case HRTIM_FAULT_3: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P); @@ -3792,9 +3791,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F); hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK); break; - } + } - case HRTIM_FAULT_4: + case HRTIM_FAULT_4: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P); @@ -3804,7 +3803,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_FAULT_5: + case HRTIM_FAULT_5: { hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK); hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P); @@ -3814,7 +3813,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -3825,9 +3824,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Update the HRTIM registers except LOCK bit */ @@ -3835,8 +3834,8 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK))); /* Update the HRTIM registers LOCK bit */ - SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK)); - SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK)); + SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1, (hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK)); + SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2, (hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK)); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -3859,15 +3858,15 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer and before * enabling faults inputs */ -HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler) { /* Check parameters */ assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3902,9 +3901,9 @@ HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled * @retval None */ -void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, - uint32_t Faults, - uint32_t Enable) +void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, + uint32_t Faults, + uint32_t Enable) { /* Check parameters */ assert_param(IS_HRTIM_FAULT(Faults)); @@ -3946,9 +3945,9 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg) + const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg) { uint32_t hrtim_cr1; @@ -3956,9 +3955,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger)); assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -3971,7 +3970,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, switch (ADCTrigger) { - case HRTIM_ADCTRIGGER_1: + case HRTIM_ADCTRIGGER_1: { hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC); hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC); @@ -3981,7 +3980,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_2: + case HRTIM_ADCTRIGGER_2: { hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC); @@ -3991,7 +3990,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_3: + case HRTIM_ADCTRIGGER_3: { hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC); @@ -4001,7 +4000,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_ADCTRIGGER_4: + case HRTIM_ADCTRIGGER_4: { hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC); hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC); @@ -4011,7 +4010,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4022,9 +4021,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } /* Update the HRTIM registers */ @@ -4044,7 +4043,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions - * @brief HRTIM timer configuration and control functions + * @brief HRTIM timer configuration and control functions @verbatim =============================================================================== ##### HRTIM timer configuration and control functions ##### @@ -4098,9 +4097,9 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef *pTimerCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -4114,9 +4113,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode)); assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4199,10 +4198,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before starting the timer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg) + const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); @@ -4211,9 +4210,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4224,75 +4223,85 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt /* Configure timer event filtering capabilities */ switch (Event) { - case HRTIM_EVENT_NONE: + case HRTIM_EVENT_NONE: { CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1); CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2); break; } - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), + (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U)); break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U)); break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U)); break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U)); break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), + (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch)); break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U)); break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U)); break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U)); break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) ); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), + ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U)); break; } - default: - { + default: + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -4302,9 +4311,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4329,9 +4338,9 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg) + const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg) { uint32_t hrtim_dtr; @@ -4345,9 +4354,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock)); assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4368,9 +4377,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, /* Update the HRTIM registers */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, ( - HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC | - HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF | - HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr); + HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC | + HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF | + HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4394,9 +4403,9 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before configuring the timer output(s) */ -HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg) + const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg) { uint32_t hrtim_chpr; @@ -4406,9 +4415,9 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle)); assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4471,16 +4480,16 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t RegistersToUpdate) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4491,44 +4500,44 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, /* Set the burst DMA timer update register */ switch (TimerIdx) { - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate; break; } - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate; break; } - default: - { + default: + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -4538,9 +4547,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4578,17 +4587,17 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - const HRTIM_CompareCfgTypeDef* pCompareCfg) + const HRTIM_CompareCfgTypeDef *pCompareCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4602,43 +4611,43 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, switch (CompareUnit) { case HRTIM_COMPAREUNIT_1: - { + { hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_2: - { + { hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_3: - { + { hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue; break; - } + } case HRTIM_COMPAREUNIT_4: - { + { hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue; break; - } + } default: - { + { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hhrtim); break; - } + } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } } @@ -4646,14 +4655,14 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, { switch (CompareUnit) { - case HRTIM_COMPAREUNIT_1: + case HRTIM_COMPAREUNIT_1: { /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue; break; } - case HRTIM_COMPAREUNIT_2: + case HRTIM_COMPAREUNIT_2: { /* Check parameters */ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); @@ -4688,17 +4697,17 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U); } - break; + break; } - case HRTIM_COMPAREUNIT_3: + case HRTIM_COMPAREUNIT_3: { /* Set the compare value */ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue; break; } - case HRTIM_COMPAREUNIT_4: + case HRTIM_COMPAREUNIT_4: { /* Check parameters */ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); @@ -4733,24 +4742,24 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U); } - break; + break; } - default: - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + default: + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - break; - } - } + break; + } + } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) - { - return HAL_ERROR; - } + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) + { + return HAL_ERROR; + } } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4779,18 +4788,18 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called before starting the timer */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - const HRTIM_CaptureCfgTypeDef* pCaptureCfg) + const HRTIM_CaptureCfgTypeDef *pCaptureCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4801,19 +4810,19 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, /* Configure the capture unit */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, pCaptureCfg->Trigger); break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, pCaptureCfg->Trigger); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -4824,9 +4833,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } @@ -4865,10 +4874,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, * @note This function must be called before configuring the timer and after * configuring the deadtime insertion feature (if required). */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx, - uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg) +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + uint32_t Output, + const HRTIM_OutputCfgTypeDef *pOutputCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); @@ -4879,9 +4888,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable)); assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4933,7 +4942,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, * @note The 'software set/reset trigger' bit in the output set/reset registers * is automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, uint32_t OutputLevel) @@ -4942,9 +4951,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -4955,16 +4964,16 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, /* Force timer output level */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) { /* Force output to its active state */ - SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST); + SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R, HRTIM_SET1R_SST); } else { @@ -4974,11 +4983,11 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) { @@ -4993,7 +5002,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; @@ -5004,9 +5013,9 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5035,10 +5044,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_OUTPUT(OutputsToStart)); /* Process Locked */ @@ -5075,10 +5084,10 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStop) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_OUTPUT(OutputsToStop)); /* Process Locked */ @@ -5111,8 +5120,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERID_TIMER_E * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); @@ -5148,8 +5157,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note The counter of a timer is stopped only if all timer outputs are disabled */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); @@ -5188,8 +5197,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim, * function. * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; @@ -5202,7 +5211,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; /* Enable HRTIM interrupts (if required) */ - __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests); + __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests); /* Enable master timer related interrupts (if required) */ if ((Timers & HRTIM_TIMERID_MASTER) != 0U) @@ -5232,7 +5241,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - return HAL_OK;} + return HAL_OK; +} /** * @brief Stop the counter of the designated timer(s) operating in waveform mode @@ -5250,8 +5260,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related interrupts are disabled. */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { /* ++ WA */ __IO uint32_t delai = (uint32_t)(0x17FU); @@ -5268,7 +5278,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; /* Disable HRTIM interrupts (if required) */ - __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests); + __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests); /* Disable master timer related interrupts (if required) */ if ((Timers & HRTIM_TIMERID_MASTER) != 0U) @@ -5322,18 +5332,18 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, * size of each DMA transfer are specified at timer configuration time * (see HAL_HRTIM_WaveformTimerConfig) */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } hhrtim->State = HAL_HRTIM_STATE_BUSY; @@ -5344,29 +5354,29 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) && (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U)) { - /* Set the DMA error callback */ - hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ; + /* Set the DMA error callback */ + hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ; - /* Set the DMA transfer completed callback */ - hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt; + /* Set the DMA transfer completed callback */ + hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt; - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hhrtim->hdmaMaster, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK) + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(hhrtim->hdmaMaster, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } - /* Enable the timer DMA request */ - __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); + /* Enable the timer DMA request */ + __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); } for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ; @@ -5374,7 +5384,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, timer_idx++) { if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) && - (hhrtim->TimerParam[timer_idx].DMARequests != 0U)) + (hhrtim->TimerParam[timer_idx].DMARequests != 0U)) { /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx); @@ -5389,7 +5399,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, return HAL_ERROR; } - /* Set the DMA error callback */ + /* Set the DMA error callback */ hdma->XferErrorCallback = HRTIM_DMAError ; /* Set the DMA transfer completed callback */ @@ -5397,17 +5407,17 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, - hhrtim->TimerParam[timer_idx].DMASrcAddress, - hhrtim->TimerParam[timer_idx].DMADstAddress, - hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->TimerParam[timer_idx].DMASrcAddress, + hhrtim->TimerParam[timer_idx].DMADstAddress, + hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK) + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the timer DMA request */ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, @@ -5443,8 +5453,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related DMA requests are disabled. */ -HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, - uint32_t Timers) +HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, + uint32_t Timers) { uint8_t timer_idx; @@ -5459,14 +5469,14 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, /* Disable the DMA */ if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK) { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + hhrtim->State = HAL_HRTIM_STATE_ERROR; } else { - hhrtim->State = HAL_HRTIM_STATE_READY; - /* Disable the DMA request(s) */ - __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, - hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); + hhrtim->State = HAL_HRTIM_STATE_READY; + /* Disable the DMA request(s) */ + __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, + hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests); } } @@ -5500,11 +5510,11 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } else { - return HAL_OK; + return HAL_OK; } } @@ -5518,15 +5528,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim, * @retval HAL status * @note This function must be called after starting the timer(s) */ -HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim, uint32_t Enable) { /* Check parameters */ assert_param(IS_HRTIM_BURSTMODECTL(Enable)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5552,9 +5562,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim) { - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5591,7 +5601,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim * @note The 'software capture' bit in the capure configuration register is * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -5599,9 +5609,9 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5612,32 +5622,32 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, /* Force a software capture on concerned capture unit */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT); break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT); break; } - default: + default: { hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hhrtim); - break; + break; } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) + if (hhrtim->State == HAL_HRTIM_STATE_ERROR) { - return HAL_ERROR; + return HAL_ERROR; } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5663,15 +5673,15 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, * @note The 'software update' bits in the HRTIM control register 2 register are * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers) { /* Check parameters */ assert_param(IS_HRTIM_TIMERUPDATE(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5705,15 +5715,15 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, * @note The 'software reset' bits in the HRTIM control register 2 are * automatically reset by hardware */ -HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers) { /* Check parameters */ assert_param(IS_HRTIM_TIMERRESET(Timers)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Process Locked */ @@ -5761,18 +5771,18 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, uint32_t BurstBufferAddress, uint32_t BurstBufferLength) { - DMA_HandleTypeDef * hdma; + DMA_HandleTypeDef *hdma; /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if(hhrtim->State == HAL_HRTIM_STATE_BUSY) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - if(hhrtim->State == HAL_HRTIM_STATE_READY) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U)) + if ((BurstBufferAddress == 0U) || (BurstBufferLength == 0U)) { return HAL_ERROR; } @@ -5806,17 +5816,17 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hdma, - BurstBufferAddress, - (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR), - BurstBufferLength) != HAL_OK) - { - hhrtim->State = HAL_HRTIM_STATE_ERROR; + BurstBufferAddress, + (uint32_t) &(hhrtim->Instance->sCommonRegs.BDMADR), + BurstBufferLength) != HAL_OK) + { + hhrtim->State = HAL_HRTIM_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); - return HAL_ERROR; - } + return HAL_ERROR; + } hhrtim->State = HAL_HRTIM_STATE_READY; @@ -5841,9 +5851,9 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers) + uint32_t Timers) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_HRTIM_TIMERUPDATE(Timers)); /* Process Locked */ @@ -5860,7 +5870,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, __HAL_UNLOCK(hhrtim); return HAL_OK; - } +} /** * @brief Disable the transfer from preload to active registers for one @@ -5896,14 +5906,14 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, __HAL_UNLOCK(hhrtim); return HAL_OK; - } +} /** * @} */ /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions - * @brief Peripheral State functions + * @brief Peripheral State functions @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -5928,7 +5938,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval HAL state */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim) +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim) { /* Return HRTIM state */ return hhrtim->State; @@ -5950,7 +5960,7 @@ HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim) * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval Captured value */ -uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -5963,21 +5973,21 @@ uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, /* Read captured value */ switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR; break; } - default: - { - captured_value = 0xFFFFFFFFUL; + default: + { + captured_value = 0xFFFFFFFFUL; break; } @@ -6013,7 +6023,7 @@ uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, * @note Returned output level is taken before the output stage (chopper, * polarity). */ -uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -6025,11 +6035,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, /* Read the output level */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET) { @@ -6039,14 +6049,14 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, { output_level = HRTIM_OUTPUTLEVEL_INACTIVE; } - break; + break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET) { @@ -6059,7 +6069,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, break; } - default: + default: { output_level = 0xFFFFFFFFUL; break; @@ -6093,7 +6103,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Output state */ -uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -6109,67 +6119,67 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, /* Set output state according to output control status and output disable status */ switch (Output) { - case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TA1: { output_bit = HRTIM_OENR_TA1OEN; break; } - case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TA2: { output_bit = HRTIM_OENR_TA2OEN; break; } - case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TB1: { output_bit = HRTIM_OENR_TB1OEN; break; } - case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TB2: { output_bit = HRTIM_OENR_TB2OEN; break; } - case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TC1: { output_bit = HRTIM_OENR_TC1OEN; break; } - case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TC2: { output_bit = HRTIM_OENR_TC2OEN; break; } - case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TD1: { output_bit = HRTIM_OENR_TD1OEN; break; } - case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TD2: { output_bit = HRTIM_OENR_TD2OEN; break; } - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TE1: { output_bit = HRTIM_OENR_TE1OEN; break; } - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TE2: { output_bit = HRTIM_OENR_TE2OEN; break; } - default: + default: { output_bit = 0UL; break; @@ -6195,7 +6205,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, } } - return(output_state); + return (output_state); } /** @@ -6223,7 +6233,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Delayed protection status */ -uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output) { @@ -6235,11 +6245,11 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim /* Read the delayed protection status */ switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET) { @@ -6254,11 +6264,11 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET) { @@ -6273,7 +6283,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim break; } - default: + default: { delayed_protection_status = 0xFFFFFFFFUL; break; @@ -6288,7 +6298,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim * @param hhrtim pointer to HAL HRTIM handle * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim) +uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim) { uint32_t burst_mode_status; @@ -6311,7 +6321,7 @@ uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { uint32_t current_pushpull_status; @@ -6339,7 +6349,7 @@ uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval Idle Push Pull Status */ -uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { uint32_t idle_pushpull_status; @@ -6358,24 +6368,24 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, */ /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling - * @brief Functions called when HRTIM generates an interrupt - * 7 interrupts can be generated by the master timer: - * - Master timer registers update - * - Synchronization event received - * - Master timer repetition event - * - Master Compare 1 to 4 event - * 14 interrupts can be generated by each timing unit: - * - Delayed protection triggered - * - Counter reset or roll-over event - * - Output 1 and output 2 reset (transition active to inactive) - * - Output 1 and output 2 set (transition inactive to active) - * - Capture 1 and 2 events - * - Timing unit registers update - * - Repetition event - * - Compare 1 to 4 event - * 7 global interrupts are generated for the whole HRTIM: - * - System fault and Fault 1 to 5 (regardless of the timing unit attribution) - * - Burst mode period completed + * @brief Functions called when HRTIM generates an interrupt + * 7 interrupts can be generated by the master timer: + * - Master timer registers update + * - Synchronization event received + * - Master timer repetition event + * - Master Compare 1 to 4 event + * 14 interrupts can be generated by each timing unit: + * - Delayed protection triggered + * - Counter reset or roll-over event + * - Output 1 and output 2 reset (transition active to inactive) + * - Output 1 and output 2 set (transition inactive to active) + * - Capture 1 and 2 events + * - Timing unit registers update + * - Repetition event + * - Compare 1 to 4 event + * 7 global interrupts are generated for the whole HRTIM: + * - System fault and Fault 1 to 5 (regardless of the timing unit attribution) + * - Burst mode period completed @verbatim =============================================================================== ##### HRTIM interrupts handling ##### @@ -6424,7 +6434,7 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, * This parameter can be any value of HRTIM_Timer_Index * @retval None */ -void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, +void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* HRTIM interrupts handling */ @@ -6450,7 +6460,7 @@ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval None * @retval None */ -__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6465,7 +6475,7 @@ __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6480,7 +6490,7 @@ __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6495,7 +6505,7 @@ __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6510,7 +6520,7 @@ __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6525,7 +6535,7 @@ __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6540,7 +6550,7 @@ __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6555,7 +6565,7 @@ __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim) * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim) +__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6578,7 +6588,7 @@ __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -6603,7 +6613,7 @@ __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -6629,8 +6639,8 @@ __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6655,8 +6665,8 @@ __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_D for timer D * @arg HRTIM_TIMERINDEX_TIMER_E for timer E */ -__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6681,8 +6691,8 @@ __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6707,8 +6717,8 @@ __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6731,8 +6741,8 @@ __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6755,8 +6765,8 @@ __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6780,8 +6790,8 @@ __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6805,8 +6815,8 @@ __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6829,8 +6839,8 @@ __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6853,8 +6863,8 @@ __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6877,8 +6887,8 @@ __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6901,8 +6911,8 @@ __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhrtim); @@ -6926,7 +6936,7 @@ __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None */ -__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim, +__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { /* Prevent unused argument(s) compilation warning */ @@ -6973,7 +6983,7 @@ __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim) * @param pCallback Callback function pointer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_CallbackTypeDef pCallback) { @@ -7102,7 +7112,7 @@ HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HAL_HRTIM_MSPDEINIT_CB_ID * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -7114,79 +7124,79 @@ HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, { switch (CallbackID) { - case HAL_HRTIM_FAULT1CALLBACK_CB_ID : - hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback; - break; + case HAL_HRTIM_FAULT1CALLBACK_CB_ID : + hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback; + break; - case HAL_HRTIM_FAULT2CALLBACK_CB_ID : - hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback; - break; + case HAL_HRTIM_FAULT2CALLBACK_CB_ID : + hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback; + break; - case HAL_HRTIM_FAULT3CALLBACK_CB_ID : - hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback; - break; + case HAL_HRTIM_FAULT3CALLBACK_CB_ID : + hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback; + break; - case HAL_HRTIM_FAULT4CALLBACK_CB_ID : - hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback; - break; + case HAL_HRTIM_FAULT4CALLBACK_CB_ID : + hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback; + break; - case HAL_HRTIM_FAULT5CALLBACK_CB_ID : - hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback; - break; + case HAL_HRTIM_FAULT5CALLBACK_CB_ID : + hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback; + break; - case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID : - hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback; - break; + case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID : + hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback; + break; - case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID : - hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback; - break; + case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID : + hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback; + break; - case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID : - hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback; - break; + case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID : + hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback; + break; - case HAL_HRTIM_ERRORCALLBACK_CB_ID : - hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback; - break; + case HAL_HRTIM_ERRORCALLBACK_CB_ID : + hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback; + break; - case HAL_HRTIM_MSPINIT_CB_ID : - hhrtim->MspInitCallback = HAL_HRTIM_MspInit; - break; + case HAL_HRTIM_MSPINIT_CB_ID : + hhrtim->MspInitCallback = HAL_HRTIM_MspInit; + break; - case HAL_HRTIM_MSPDEINIT_CB_ID : - hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; - break; + case HAL_HRTIM_MSPDEINIT_CB_ID : + hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; + break; - default : - /* Update the state */ - hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; + default : + /* Update the state */ + hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + /* Return error status */ + status = HAL_ERROR; + break; } } else if (HAL_HRTIM_STATE_RESET == hhrtim->State) { switch (CallbackID) { - case HAL_HRTIM_MSPINIT_CB_ID : - hhrtim->MspInitCallback = HAL_HRTIM_MspInit; - break; + case HAL_HRTIM_MSPINIT_CB_ID : + hhrtim->MspInitCallback = HAL_HRTIM_MspInit; + break; - case HAL_HRTIM_MSPDEINIT_CB_ID : - hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; - break; + case HAL_HRTIM_MSPDEINIT_CB_ID : + hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit; + break; - default : - /* Update the state */ - hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; + default : + /* Update the state */ + hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -7227,7 +7237,7 @@ HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @param pCallback Callback function pointer * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_TIMxCallbackTypeDef pCallback) { @@ -7308,7 +7318,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, hhrtim->BurstDMATransferCallback = pCallback; break; - default : + default : /* Update the state */ hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; @@ -7354,7 +7364,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID * @retval HAL status */ -HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -7426,7 +7436,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback; break; - default : + default : /* Update the state */ hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK; @@ -7468,8 +7478,8 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @param pTimeBaseCfg pointer to the time base configuration structure * @retval None */ -static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) +static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { uint32_t hrtim_mcr; @@ -7497,9 +7507,9 @@ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimeBaseCfg pointer to the time base configuration structure * @retval None */ -static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx , - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) +static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx, + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg) { uint32_t hrtim_timcr; @@ -7526,8 +7536,8 @@ static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimerCfg pointer to the timer configuration data structure * @retval None */ -static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - const HRTIM_TimerCfgTypeDef * pTimerCfg) +static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim, + const HRTIM_TimerCfgTypeDef *pTimerCfg) { uint32_t hrtim_mcr; uint32_t hrtim_bmcr; @@ -7580,9 +7590,9 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, * @param pTimerCfg pointer to the timer configuration data structure * @retval None */ -static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef *pTimerCfg) { uint32_t hrtim_timcr; uint32_t hrtim_timfltr; @@ -7662,11 +7672,11 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, Delayed Idle is available whatever the timer operating mode (regular, push-pull) Balanced Idle is only available in push-pull mode */ - if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) + if (((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)) - || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED)) + || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED)) { - hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN); + hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT | HRTIM_OUTR_DLYPRTEN); hrtim_timoutr |= pTimerCfg->DelayedProtectionMode; } @@ -7676,43 +7686,43 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, /* Set the timer burst mode */ switch (TimerIdx) { - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hrtim_bmcr &= ~(HRTIM_BMCR_TABM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 1U); break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hrtim_bmcr &= ~(HRTIM_BMCR_TBBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 2U); break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hrtim_bmcr &= ~(HRTIM_BMCR_TCBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 3U); break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hrtim_bmcr &= ~(HRTIM_BMCR_TDBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 4U); break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hrtim_bmcr &= ~(HRTIM_BMCR_TEBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U); + hrtim_bmcr |= (pTimerCfg->BurstMode << 5U); break; } - default: - break; + default: + break; } /* Update the HRTIM registers */ @@ -7731,7 +7741,7 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, * @param Event Event reference * @retval None */ -static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, uint32_t Event) @@ -7740,86 +7750,86 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, switch (Event) { - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1; break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2; break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3; break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4; break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5; break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6; break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7; break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9; break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10; break; } - default: - break; + default: + break; } switch (CaptureUnit) { - case HRTIM_CAPTUREUNIT_1: + case HRTIM_CAPTUREUNIT_1: { hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger; break; } - case HRTIM_CAPTUREUNIT_2: + case HRTIM_CAPTUREUNIT_2: { hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger; break; } - default: - break; + default: + break; } } @@ -7831,10 +7841,10 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, * @param pOutputCfg pointer to the output configuration data structure * @retval None */ -static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg) + const HRTIM_OutputCfgTypeDef *pOutputCfg) { uint32_t hrtim_outr; uint32_t hrtim_dtr; @@ -7846,11 +7856,11 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, switch (Output) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { /* Set the output set/reset crossbar */ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource; @@ -7858,11 +7868,11 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { /* Set the output set/reset crossbar */ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource; @@ -7871,15 +7881,15 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: - break; + default: + break; } /* Clear output config */ hrtim_outr &= ~((HRTIM_OUTR_POL1 | HRTIM_OUTR_IDLM1 | - HRTIM_OUTR_IDLES1| - HRTIM_OUTR_FAULT1| + HRTIM_OUTR_IDLES1 | + HRTIM_OUTR_FAULT1 | HRTIM_OUTR_CHP1 | HRTIM_OUTR_DIDL1) << shift); @@ -7922,7 +7932,7 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, * @param pEventCfg pointer to the event channel configuration data structure * @retval None */ -static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, const HRTIM_EventCfgTypeDef *pEventCfg) { @@ -7937,7 +7947,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, switch (Event) { - case HRTIM_EVENT_NONE: + case HRTIM_EVENT_NONE: { /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR1 = 0U; @@ -7946,7 +7956,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST); hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC); @@ -7960,7 +7970,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST); hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC); @@ -7974,7 +7984,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST); hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC); @@ -7988,7 +7998,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST); hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC); @@ -8002,7 +8012,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST); hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC); @@ -8016,7 +8026,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS); hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC); @@ -8030,7 +8040,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS); hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC); @@ -8044,21 +8054,21 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS); hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC); hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL); hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS); hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F); - hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F ); + hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F); /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS); hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC); @@ -8072,7 +8082,7 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS); hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC); @@ -8086,8 +8096,8 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, break; } - default: - break; + default: + break; } } @@ -8098,74 +8108,74 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, * @param Event Event channel identifier * @retval None */ -static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event) { switch (Event) { - case HRTIM_EVENT_1: + case HRTIM_EVENT_1: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1; break; } - case HRTIM_EVENT_2: + case HRTIM_EVENT_2: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2; break; } - case HRTIM_EVENT_3: + case HRTIM_EVENT_3: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3; break; } - case HRTIM_EVENT_4: + case HRTIM_EVENT_4: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4; break; } - case HRTIM_EVENT_5: + case HRTIM_EVENT_5: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5; break; } - case HRTIM_EVENT_6: + case HRTIM_EVENT_6: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6; break; } - case HRTIM_EVENT_7: + case HRTIM_EVENT_7: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7; break; } - case HRTIM_EVENT_8: + case HRTIM_EVENT_8: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8; break; } - case HRTIM_EVENT_9: + case HRTIM_EVENT_9: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9; break; } - case HRTIM_EVENT_10: + case HRTIM_EVENT_10: { hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10; break; } - default: - break; + default: + break; } } @@ -8188,7 +8198,7 @@ static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Interrupt to enable or disable */ -static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -8198,13 +8208,13 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { - /* Retreives actual OC mode and set interrupt accordingly */ + /* Retrieves actual OC mode and set interrupt accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R; @@ -8217,29 +8227,29 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ interrupt = HRTIM_TIM_IT_SET1; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ interrupt = HRTIM_TIM_IT_RST1; } else { - /* nothing to do */ + /* nothing to do */ } break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { - /* Retreives actual OC mode and set interrupt accordingly */ + /* Retrieves actual OC mode and set interrupt accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R; @@ -8252,24 +8262,24 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ interrupt = HRTIM_TIM_IT_SET2; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ interrupt = HRTIM_TIM_IT_RST2; } else { - /* nothing to do */ + /* nothing to do */ } break; } - default: - break; + default: + break; } return interrupt; @@ -8294,7 +8304,7 @@ static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval DMA request to enable or disable */ -static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -8304,13 +8314,13 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, switch (OCChannel) { - case HRTIM_OUTPUT_TA1: - case HRTIM_OUTPUT_TB1: - case HRTIM_OUTPUT_TC1: - case HRTIM_OUTPUT_TD1: - case HRTIM_OUTPUT_TE1: + case HRTIM_OUTPUT_TA1: + case HRTIM_OUTPUT_TB1: + case HRTIM_OUTPUT_TC1: + case HRTIM_OUTPUT_TD1: + case HRTIM_OUTPUT_TE1: { - /* Retreives actual OC mode and set dma_request accordingly */ + /* Retrieves actual OC mode and set dma_request accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R; @@ -8323,29 +8333,29 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ dma_request = HRTIM_TIM_DMA_SET1; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ dma_request = HRTIM_TIM_DMA_RST1; } else { - /* nothing to do */ + /* nothing to do */ } break; } - case HRTIM_OUTPUT_TA2: - case HRTIM_OUTPUT_TB2: - case HRTIM_OUTPUT_TC2: - case HRTIM_OUTPUT_TD2: - case HRTIM_OUTPUT_TE2: + case HRTIM_OUTPUT_TA2: + case HRTIM_OUTPUT_TB2: + case HRTIM_OUTPUT_TC2: + case HRTIM_OUTPUT_TD2: + case HRTIM_OUTPUT_TE2: { - /* Retreives actual OC mode and set dma_request accordingly */ + /* Retrieves actual OC mode and set dma_request accordingly */ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R; hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R; @@ -8358,81 +8368,81 @@ static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) && (hrtim_reset == 0U)) { - /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ dma_request = HRTIM_TIM_DMA_SET2; } else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2)) { - /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ + /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ dma_request = HRTIM_TIM_DMA_RST2; } else { - /* nothing to do */ + /* nothing to do */ } break; } - default: - break; + default: + break; } return dma_request; } -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) +static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { - DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL; + DMA_HandleTypeDef *hdma = (DMA_HandleTypeDef *)NULL; switch (TimerIdx) { - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hdma = hhrtim->hdmaMaster; break; } - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hdma = hhrtim->hdmaTimerA; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hdma = hhrtim->hdmaTimerB; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hdma = hhrtim->hdmaTimerC; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hdma = hhrtim->hdmaTimerD; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hdma = hhrtim->hdmaTimerE; break; } - default: - break; + default: + break; } return hdma; } -static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, - const DMA_HandleTypeDef * hdma) +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim, + const DMA_HandleTypeDef *hdma) { uint32_t timed_idx = 0xFFFFFFFFU; @@ -8474,49 +8484,49 @@ static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, * @param TimerIdx Timer index * @retval None */ -static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, +static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx) { switch (TimerIdx) { - case HRTIM_TIMERINDEX_MASTER: + case HRTIM_TIMERINDEX_MASTER: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU; break; } - case HRTIM_TIMERINDEX_TIMER_A: + case HRTIM_TIMERINDEX_TIMER_A: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU; break; } - case HRTIM_TIMERINDEX_TIMER_B: + case HRTIM_TIMERINDEX_TIMER_B: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU; break; } - case HRTIM_TIMERINDEX_TIMER_C: + case HRTIM_TIMERINDEX_TIMER_C: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU; break; } - case HRTIM_TIMERINDEX_TIMER_D: + case HRTIM_TIMERINDEX_TIMER_D: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU; break; } - case HRTIM_TIMERINDEX_TIMER_E: + case HRTIM_TIMERINDEX_TIMER_E: { hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU; break; } - default: - break; + default: + break; } } @@ -8526,15 +8536,15 @@ static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval None */ -static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) +static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim) { uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); /* Fault 1 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1); @@ -8548,9 +8558,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 2 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2); @@ -8564,9 +8574,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 3 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3); @@ -8580,9 +8590,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 4 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4); @@ -8596,9 +8606,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 5 event */ - if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5); @@ -8612,9 +8622,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* System fault event */ - if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT); @@ -8629,11 +8639,11 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /** -* @brief Master timer interrupts service routine -* @param hhrtim pointer to HAL HRTIM handle -* @retval None -*/ -static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) + * @brief Master timer interrupts service routine + * @param hhrtim pointer to HAL HRTIM handle + * @retval None + */ +static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim) { uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); @@ -8641,9 +8651,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER); /* Burst mode period event */ - if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET) + if ((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET) { - if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET) + if ((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER); @@ -8657,9 +8667,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 1 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1); @@ -8673,9 +8683,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 2 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2); @@ -8689,9 +8699,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 3 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3); @@ -8705,9 +8715,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 4 event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4); @@ -8721,9 +8731,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer repetition event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP); @@ -8737,9 +8747,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Synchronization input event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC); @@ -8753,9 +8763,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer registers update event */ - if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) + if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) { - if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET) + if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD); @@ -8780,17 +8790,17 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_D for timer D * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval None -*/ -static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx) + */ +static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim, + uint32_t TimerIdx) { uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR); uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER); /* Timer compare 1 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); @@ -8804,9 +8814,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 2 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); @@ -8820,9 +8830,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 3 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3); @@ -8836,9 +8846,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 4 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4); @@ -8852,9 +8862,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer repetition event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP); @@ -8868,9 +8878,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer registers update event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD); @@ -8884,9 +8894,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 1 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1); @@ -8900,9 +8910,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 2 event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2); @@ -8916,9 +8926,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 set event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1); @@ -8932,9 +8942,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1); @@ -8948,9 +8958,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 set event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2); @@ -8964,9 +8974,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2); @@ -8980,9 +8990,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer reset event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST); @@ -8996,9 +9006,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Delayed protection event */ - if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) + if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) { - if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET) + if ((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT); @@ -9019,7 +9029,7 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, */ static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET) { @@ -9092,11 +9102,11 @@ static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma) { uint8_t timer_idx; - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma); - if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;} + if (!IS_HRTIM_TIMING_UNIT(timer_idx)) {return;} if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET) { @@ -9217,16 +9227,16 @@ static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma) } /** -* @brief DMA error callback -* @param hdma pointer to DMA handle. -* @retval None -*/ + * @brief DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ static void HRTIM_DMAError(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) - hrtim->ErrorCallback(hrtim); + hrtim->ErrorCallback(hrtim); #else HAL_HRTIM_ErrorCallback(hrtim); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ @@ -9239,10 +9249,10 @@ static void HRTIM_DMAError(DMA_HandleTypeDef *hdma) */ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma) { - HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent; + HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) - hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); + hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); #else HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma)); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_i2c.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_i2c.c index 39b2d68dd..665cab063 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_i2c.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_i2c.c @@ -90,7 +90,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -156,7 +156,7 @@ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() @@ -214,7 +214,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -1407,14 +1407,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - /* Preload TX data if no stretch enable */ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { @@ -1428,6 +1420,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1439,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1451,6 +1459,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -3255,6 +3267,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3312,37 +3326,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -4552,7 +4593,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) } /** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value @@ -4561,7 +4602,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if (hi2c->Mode == HAL_I2C_MODE_MASTER) + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -7284,15 +7327,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_i2s.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_i2s.c index d44926769..0cd61d309 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_i2s.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_i2s.c @@ -1835,6 +1835,107 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) return errorcode; } +/** + * @brief Enable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx. + * Original SDI pin becomes SDO and original SDO pin becomes SDI (Also applicable + * on half-duplex mode in case of single data line). + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state. + * @retval HAL_OK IO Swap feature enabled successfully. + */ +HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the global state */ + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_ERROR; + } + + /* Check for IOLock */ + if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) + { + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE) + { + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + } + + /* Enable IO Swap feature */ + SET_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP); + + return HAL_OK; +} + +/** + * @brief Disable the SDO/SDI alternate functions inversion feature for the dedicated I2Sx. + * Original SDI pin becomes SDI and original SDO pin becomes SDO (Also applicable + * on half-duplex mode in case of single data line). + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval HAL_ERROR When IO is locked, handle is NULL or wrong state. + * @retval HAL_OK IO Swap feature disabled successfully. + */ +HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* Check the global state */ + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_ERROR; + } + + /* Check for IOLock */ + if (READ_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) + { + return HAL_ERROR; + } + + /* Check if the I2S is already enabled */ + if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE) + { + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + } + + /* Disable the IO Swap feature */ + CLEAR_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP); + + return HAL_OK; +} + +/** + * @brief Retrieve the SDO/SDI alternate functions inversion feature status for the dedicated I2Sx. + * @param hi2s Pointer to a @ref I2S_HandleTypeDef structure that contains + * the configuration information for I2S module. + * @retval 1 when I2S IO swap feature is enabled, 0 otherwise, or when hi2s pointer is null. + */ +uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return 0; + } + + return ((READ_BIT(hi2s->Instance->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); +} + /** * @brief This function handles I2S interrupt request. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_iwdg.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_iwdg.c index 2ec282987..23955db40 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_iwdg.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_iwdg.c @@ -127,7 +127,8 @@ The timeout value is multiplied by 1000 to be converted in milliseconds. LSI startup time is also considered here by adding LSI_STARTUP_TIME converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \ + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ltdc.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ltdc.c index 80fe3ad95..5b89f544f 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ltdc.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ltdc.c @@ -279,24 +279,20 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); /* Set Synchronization size */ - hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); tmp = (hltdc->Init.HorizontalSync << 16U); - hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync)); /* Set Accumulated Back porch */ - hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); tmp = (hltdc->Init.AccumulatedHBP << 16U); - hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP)); /* Set Accumulated Active Width */ - hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); tmp = (hltdc->Init.AccumulatedActiveW << 16U); - hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH)); /* Set Total Width */ - hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); tmp = (hltdc->Init.TotalWidth << 16U); - hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh)); /* Set the background color value */ tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); @@ -916,11 +912,12 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx) { uint32_t tmp; uint32_t counter; - uint32_t *pcolorlut = pCLUT; + const uint32_t *pcolorlut = pCLUT; /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); @@ -2092,7 +2089,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 * the configuration information for the LTDC. * @retval HAL state */ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc) { return hltdc->State; } @@ -2103,7 +2100,7 @@ HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) * the configuration information for the LTDC. * @retval LTDC Error Code */ -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc) { return hltdc->ErrorCode; } @@ -2154,9 +2151,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); tmp2 = (pLayerCfg->Alpha0 << 24U); - LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | - LTDC_LxDCCR_DCALPHA); - LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2)); /* Specifies the constant alpha value */ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); @@ -2167,8 +2162,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); /* Configure the color frame buffer start address */ - LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); - LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress); if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) { diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mdios.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mdios.c index dc7b722ac..50b04a985 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mdios.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mdios.c @@ -635,7 +635,7 @@ HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum * @param hmdios: mdios handle * @retval bit map of written registers addresses */ -uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios) +uint32_t HAL_MDIOS_GetWrittenRegAddress(const MDIOS_HandleTypeDef *hmdios) { return hmdios->Instance->WRFR; } @@ -645,7 +645,7 @@ uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios) * @param hmdios: mdios handle * @retval bit map of read registers addresses */ -uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios) +uint32_t HAL_MDIOS_GetReadRegAddress(const MDIOS_HandleTypeDef *hmdios) { return hmdios->Instance->RDFR; } @@ -916,7 +916,7 @@ __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) * @param hmdios: mdios handle * @retval mdios error code */ -uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) +uint32_t HAL_MDIOS_GetError(const MDIOS_HandleTypeDef *hmdios) { /* return the error code */ return hmdios->ErrorCode; @@ -927,7 +927,7 @@ uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) * @param hmdios: mdios handle * @retval HAL state */ -HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios) +HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(const MDIOS_HandleTypeDef *hmdios) { /* Return MDIOS state */ return hmdios->State; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mdma.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mdma.c index 089d9fbb1..064949bc5 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mdma.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mdma.c @@ -708,7 +708,7 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MD * * @retval HAL status */ -HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode) +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, const MDMA_LinkNodeTypeDef *pPrevNode) { MDMA_LinkNodeTypeDef *pNode; uint32_t counter = 0, nodeInserted = 0; @@ -1719,7 +1719,7 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) * the configuration information for the specified MDMA Channel. * @retval HAL state */ -HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma) +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(const MDMA_HandleTypeDef *hmdma) { return hmdma->State; } @@ -1730,7 +1730,7 @@ HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma) * the configuration information for the specified MDMA Channel. * @retval MDMA Error Code */ -uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma) +uint32_t HAL_MDMA_GetError(const MDMA_HandleTypeDef *hmdma) { return hmdma->ErrorCode; } diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mmc.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mmc.c index 0aa5d6631..b67bdef9a 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mmc.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mmc.c @@ -56,7 +56,6 @@ (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization - *** MMC Card Initialization and configuration *** ================================================ [..] @@ -93,6 +92,7 @@ (#) Select the corresponding MMC Card according to the address read with the step 2. (#) Configure the MMC Card in wide bus mode: 4-bits data. + (#) Select the MMC Card partition using HAL_MMC_SwitchPartition() *** MMC Card Read operation *** ============================== @@ -169,6 +169,64 @@ (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register. Some of the CID parameters are useful for card initialization and identification. + *** MMC Card Reply Protected Memory Block (RPMB) Key Programming operation *** + ============================== + [..] + (+) You can program the authentication key of RPMB area in polling mode by using function + HAL_MMC_RPMB_ProgramAuthenticationKey(). + This function is only used once during the life of an MMC card. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + (+) You can program the authentication key of RPMB area in Interrupt mode by using function + HAL_MMC_RPMB_ProgramAuthenticationKey_IT(). + This function is only used once during the life of an MMC card. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + + *** MMC Card Reply Protected Memory Block (RPMB) write counter operation *** + ============================== + [..] + (+) You can get the write counter value of RPMB area in polling mode by using function + HAL_MMC_RPMB_GetWriteCounter(). + (+) You can get the write counter value of RPMB area in Interrupt mode by using function + HAL_MMC_RPMB_GetWriteCounter_IT(). + + *** MMC Card Reply Protected Memory Block (RPMB) write operation *** + ============================== + [..] + (+) You can write to the RPMB area of MMC card in polling mode by using function + HAL_MMC_WriteBlocks(). + This function supports the one, two, or thirty two blocks write operation + (with 512-bytes block length). + You can choose the number of blocks at the multiple block read operation by adjusting + the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + (+) You can write to the RPMB area of MMC card in Interrupt mode by using function + HAL_MMC_WriteBlocks_IT(). + This function supports the one, two, or thirty two blocks write operation + (with 512-bytes block length). + You can choose the number of blocks at the multiple block read operation by adjusting + the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for operation state. + + *** MMC Card Reply Protected Memory Block (RPMB) read operation *** + ============================== + [..] + (+) You can read from the RPMB area of MMC card in polling mode by using function + HAL_MMC_RPMB_ReadBlocks(). + The block size should be chosen as multiple of 512 bytes. + You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for MMC card state. + (+) You can read from the RPMB area of MMC card in Interrupt mode by using function + HAL_MMC_RPMB_ReadBlocks_IT(). + The block size should be chosen as multiple of 512 bytes. + You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetRPMBError() function for MMC card state. + *** MMC HAL driver macros list *** ================================== [..] @@ -204,7 +262,7 @@ and a pointer to the user callback function. Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. (+) ErrorCallback : callback when error occurs. @@ -218,9 +276,9 @@ This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_MMC_Init + reset to the legacy weak (overridden) functions in the HAL_MMC_Init and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -235,7 +293,7 @@ When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -253,6 +311,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_MMC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -290,6 +349,12 @@ /* Frequencies used in the driver for clock divider calculation */ #define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ #define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */ + +/* The Data elements' postitions in the frame Frame for RPMB area */ +#define MMC_RPMB_KEYMAC_POSITION 196U +#define MMC_RPMB_DATA_POSITION 228U +#define MMC_RPMB_NONCE_POSITION 484U +#define MMC_RPMB_WRITE_COUNTER_POSITION 500U /** * @} */ @@ -538,7 +603,6 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) return HAL_OK; } - /** * @brief Initializes the MMC MSP. * @param hmmc: Pointer to MMC handle @@ -655,7 +719,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -697,10 +761,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = SDMMC_ReadFIFO(hmmc->Instance); *tempbuff = (uint8_t)(data & 0xFFU); @@ -712,7 +776,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) @@ -850,7 +914,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pD if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -892,10 +956,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pD while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Write data to SDMMC Tx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = (uint32_t)(*tempbuff); tempbuff++; @@ -907,7 +971,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pD tempbuff++; (void)SDMMC_WriteFIFO(hmmc->Instance, &data); } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) @@ -1044,7 +1108,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -1157,7 +1221,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -1271,7 +1335,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -1386,7 +1450,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - add *= 512U; + add *= MMC_BLOCKSIZE; } /* Configure the MMC DPSM (Data Path State Machine) */ @@ -1504,8 +1568,8 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - start_add *= 512U; - end_add *= 512U; + start_add *= MMC_BLOCKSIZE; + end_add *= MMC_BLOCKSIZE; } /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ @@ -1793,7 +1857,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) * @param hmmc: Pointer to mmc handle * @retval HAL state */ -HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) +HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc) { return hmmc->State; } @@ -1804,7 +1868,7 @@ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) * the configuration information. * @retval MMC Error Code */ -uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) +uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc) { return hmmc->ErrorCode; } @@ -1872,7 +1936,7 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) /** * @brief Register a User MMC Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @note The HAL_MMC_RegisterCallback() may be called before HAL_MMC_Init() in * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID * and HAL_MMC_MSP_DEINIT_CB_ID. @@ -1977,7 +2041,7 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call /** * @brief Unregister a User MMC Callback - * MMC Callback is redirected to the weak (surcharged) predefined callback + * MMC Callback is redirected to the weak (overridden) predefined callback * @note The HAL_MMC_UnRegisterCallback() may be called before HAL_MMC_Init() in * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID * and HAL_MMC_MSP_DEINIT_CB_ID. @@ -2099,7 +2163,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); @@ -2185,14 +2249,14 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); - hmmc->MmcCard.LogBlockSize = 512U; + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / MMC_BLOCKSIZE); + hmmc->MmcCard.LogBlockSize = MMC_BLOCKSIZE; } else if (hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) { hmmc->MmcCard.BlockNbr = block_nbr; hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr; - hmmc->MmcCard.BlockSize = 512U; + hmmc->MmcCard.BlockSize = MMC_BLOCKSIZE; hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize; } else @@ -2250,7 +2314,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp * will contain the MMC card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); @@ -2300,7 +2364,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 512U; + config.DataLength = MMC_BLOCKSIZE; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; @@ -2326,7 +2390,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { *tmp_buf = SDMMC_ReadFIFO(hmmc->Instance); tmp_buf++; @@ -2707,7 +2771,8 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); /*we will send the CMD12 in all cases in order to stop the data transfers*/ - /*In case the data transfer just finished , the external memory will not respond and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/ + /*In case the data transfer just finished, the external memory will not respond + and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/ /*In case the data transfer aborted , the external memory will respond and will return HAL_MMC_ERROR_NONE*/ /*Other scenario will return HAL_ERROR*/ @@ -2723,40 +2788,40 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) { if (hmmc->ErrorCode == HAL_MMC_ERROR_NONE) { - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } } } if (hmmc->ErrorCode == HAL_MMC_ERROR_CMD_RSP_TIMEOUT) { - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } } } } else if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC) { - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } } } else @@ -2764,13 +2829,15 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) /* Nothing to do*/ } - /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear the appropriate flags that will be set depending of the abort/non abort of the memory */ - /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result in next SDMMC read/write operation to fail */ + /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear + the appropriate flags that will be set depending of the abort/non abort of the memory */ + /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result + in next SDMMC read/write operation to fail */ /*SDMMC ready for clear data flags*/ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - /* If IDMA Context, disable Internal DMA */ + /* If IDMA Context, disable Internal DMA */ hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; hmmc->State = HAL_MMC_STATE_READY; @@ -2902,8 +2969,8 @@ HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseT /* In case of low capacity card, the address is not block number but bytes */ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - start_add *= 512U; - end_add *= 512U; + start_add *= MMC_BLOCKSIZE; + end_add *= MMC_BLOCKSIZE; } /* Send CMD35 MMC_ERASE_GRP_START with start address as argument */ @@ -3562,7 +3629,6 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc) * @{ */ - /** * @brief Initializes the mmc card. * @param hmmc: Pointer to MMC handle @@ -3646,7 +3712,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) hmmc->ErrorCode |= errorstate; } - /* Get Extended CSD parameters */ if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) { @@ -3789,7 +3854,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 512U; + config.DataLength = MMC_BLOCKSIZE; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; @@ -3814,7 +3879,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { tmp_data = SDMMC_ReadFIFO(hmmc->Instance); /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ @@ -3896,10 +3961,10 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) tmp = hmmc->pRxBuffPtr; - if (hmmc->RxXferSize >= 32U) + if (hmmc->RxXferSize >= SDMMC_FIFO_SIZE) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = SDMMC_ReadFIFO(hmmc->Instance); *tmp = (uint8_t)(data & 0xFFU); @@ -3913,7 +3978,7 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) } hmmc->pRxBuffPtr = tmp; - hmmc->RxXferSize -= 32U; + hmmc->RxXferSize -= SDMMC_FIFO_SIZE; } } @@ -3931,10 +3996,10 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) tmp = hmmc->pTxBuffPtr; - if (hmmc->TxXferSize >= 32U) + if (hmmc->TxXferSize >= SDMMC_FIFO_SIZE) { /* Write data to SDMMC Tx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = (uint32_t)(*tmp); tmp++; @@ -3948,7 +4013,7 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) } hmmc->pTxBuffPtr = tmp; - hmmc->TxXferSize -= 32U; + hmmc->TxXferSize -= SDMMC_FIFO_SIZE; } } @@ -4276,6 +4341,1553 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 return errorstate; } +/** + * @brief Used to select the partition. + * @param hmmc: Pointer to MMC handle + * @param Partition: Partition type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition) +{ + uint32_t errorstate; + uint32_t response = 0U; + uint32_t count; + uint32_t tickstart = HAL_GetTick(); + uint32_t arg = Partition | 0x03B30000U; + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Index : 179 - Value : partition */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, arg); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT) + { + errorstate = HAL_MMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Allows to program the authentication key within the RPMB partition + * @param hmmc: Pointer to MMC handle + * @param pKey: pointer to the authentication key (32 bytes) + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + + tail_pack[11] = 0x01; + + if (NULL == pKey) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x80000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = pKey; + } + else if ((byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) && \ + (byte_count >= MMC_RPMB_DATA_POSITION)) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packet */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + /* Check result of operation */ + if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x01U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to get the value of write counter within the RPMB partition. + * @param hmmc: Pointer to MMC handle + * @param pNonce: pointer to the value of nonce (16 bytes) + * @param Timeout: Specify timeout value + * @retval write counter value. + */ +uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + uint8_t *tempbuff = zero_pack; + + tail_pack[11] = 0x02; + + if (NULL == pNonce) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*tempbuff); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + byte_count++; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = (uint8_t *)pNonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packt */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (pNonce[i] != echo_nonce[i]) + { + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } + } + + return ((uint32_t)tail_pack[3] | ((uint32_t)tail_pack[2] << 8) | ((uint32_t)tail_pack[1] << 16) | \ + ((uint32_t)tail_pack[0] << 24)); + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE; + return 0; + } +} + +/** + * @brief Allows to write block(s) to a specified address in the RPMB partition. The Data + * transfer is managed by polling mode. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @param pMAC: Pointer to the authentication MAC buffer + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout) +{ + + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint32_t dataremaining; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + const uint8_t local_nonce[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x00, 0x01, 0x02, + 0x03, 0x04, 0x00, 0x01, 0x02, 0x03, 0x04, 0x08 + }; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + uint32_t arg = 0x80000000U; + uint32_t offset = 0; + + if ((NumberOfBlocks != 0x1U) && (NumberOfBlocks != 0x2U) && (NumberOfBlocks != 0x20U)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if ((NULL == pData) || (NULL == pMAC)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + tail_pack[11] = 0x02; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001U); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + rtempbuff = local_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packt */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 0x00000001); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (local_nonce[i] != echo_nonce[i]) + { + return HAL_ERROR; + } + } + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } + tail_pack[11] = 0x03; + tail_pack[10] = 0x00; + tail_pack[7] = (uint8_t)(NumberOfBlocks) & 0xFFU; + tail_pack[6] = (uint8_t)(NumberOfBlocks >> 8) & 0xFFU; + tail_pack[5] = (uint8_t)(BlockAdd) & 0xFFU; + tail_pack[4] = (uint8_t)(BlockAdd >> 8) & 0xFFU; + + rtempbuff = zero_pack; + byte_count = 0; + arg |= NumberOfBlocks; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + rtempbuff = pMAC; + } + if (byte_count == MMC_RPMB_DATA_POSITION) + { + rtempbuff = &pData[offset]; + } + if ((byte_count >= MMC_RPMB_NONCE_POSITION) && \ + (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION)) + { + rtempbuff = zero_pack; + } + if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else if (byte_count == MMC_BLOCKSIZE) + { + offset += (uint32_t)256U; + byte_count = 0; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Response Packet */ + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + + { + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + } + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + /* Check result of operation */ + if (((tail_pack[9] & (uint8_t)0xFEU) != 0x00U) || (tail_pack[10] != 0x03U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to read block(s) to a specified address in the RPMB partition. The Data + * transfer is managed by polling mode. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @param pNonce: Pointer to the buffer that will contain the nonce to transmit + * @param pMAC: Pointer to the authentication MAC buffer + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC, + uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t byte_count = 0; + uint32_t data; + uint8_t tail_pack[12] = {0}; + uint8_t zero_pack[4] = {0}; + uint8_t echo_nonce[16] = {0}; + uint32_t dataremaining; + const uint8_t *rtempbuff; + uint8_t *tempbuff; + uint32_t arg = 0; + uint32_t offset = 0; + + arg |= NumberOfBlocks; + + tail_pack[11] = 0x04; + tail_pack[10] = 0x00; + tail_pack[7] = 0x00; + tail_pack[6] = 0x00; + tail_pack[5] = (uint8_t)(BlockAdd) & 0xFFU; + tail_pack[4] = (uint8_t)(BlockAdd >> 8) & 0xFFU; + tail_pack[3] = 0x00; + tail_pack[2] = 0x00; + tail_pack[1] = 0x00; + tail_pack[0] = 0x00; + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 1); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send Request Packet */ + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + rtempbuff = zero_pack; + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + + /* Write data to SDMMC Tx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = (uint32_t)(*rtempbuff); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 8U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 16U); + rtempbuff++; + byte_count++; + data |= ((uint32_t)(*rtempbuff) << 24U); + rtempbuff++; + byte_count++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + if (byte_count < MMC_RPMB_NONCE_POSITION) + { + rtempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + rtempbuff = pNonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + rtempbuff = tail_pack; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Read Response Packet */ + errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Write Blocks in Polling mode */ + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0); + + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* Poll on SDMMC flags */ + tempbuff = zero_pack; + byte_count = 0; + + dataremaining = config.DataLength; + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + byte_count++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + byte_count++; + if (byte_count < MMC_RPMB_KEYMAC_POSITION) + { + tempbuff = zero_pack; + } + else if (byte_count == MMC_RPMB_KEYMAC_POSITION) + { + tempbuff = (uint8_t *)pMAC; + } + else if (byte_count == MMC_RPMB_DATA_POSITION) + { + tempbuff = &pData[offset]; + } + else if (byte_count == MMC_RPMB_NONCE_POSITION) + { + tempbuff = echo_nonce; + } + else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION) + { + tempbuff = tail_pack; + } + else if (byte_count == MMC_BLOCKSIZE) + { + byte_count = 0; + offset += (uint32_t)256U; + } + else + { + /* Nothing to do */ + } + } + dataremaining -= SDMMC_FIFO_SIZE; + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + for (uint8_t i = 0; i < 16U; i++) + { + if (pNonce[i] != echo_nonce[i]) + { + return HAL_ERROR; + } + } + + /* Check result of operation */ + if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x04U)) + { + hmmc->RPMBErrorCode |= tail_pack[9]; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + + /** * @brief Read DMA Buffer 0 Transfer completed callbacks * @param hmmc: MMC handle @@ -4341,6 +5953,7 @@ __weak void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc) */ #endif /* HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mmc_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mmc_ex.c index 10acaf361..872386706 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mmc_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_mmc_ex.c @@ -45,6 +45,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_MMC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -59,7 +60,6 @@ */ - /** @addtogroup MMCEx_Exported_Functions_Group1 * @brief Multibuffer functions * @@ -333,7 +333,6 @@ HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_D return HAL_OK; } - /** * @} */ @@ -343,6 +342,7 @@ HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_D */ #endif /* HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_nand.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_nand.c index 87c492d0f..370d123d5 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_nand.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_nand.c @@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig) { hnand->Config.PageSize = pDeviceConfig->PageSize; hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_opamp.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_opamp.c index 688ff3e7a..5bb808031 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_opamp.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_opamp.c @@ -902,10 +902,10 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp) * or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available * */ -HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) +HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (const OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) { HAL_OPAMP_TrimmingValueTypeDef trimmingvalue; - __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ + __IO const uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ /* Check the OPAMP handle allocation */ /* Value can be retrieved in HAL_OPAMP_STATE_READY state */ @@ -1122,7 +1122,7 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL * @param hopamp OPAMP handle * @retval HAL state */ -HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp) +HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(const OPAMP_HandleTypeDef *hopamp) { /* Check the OPAMP handle allocation */ if(hopamp == NULL) diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ospi.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ospi.c index a38e06b30..5c5f6efc6 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ospi.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ospi.c @@ -1177,7 +1177,8 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1270,7 +1271,8 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1493,7 +1495,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat } /* Enable the transmit MDMA Channel */ - if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize, 1) == \ + if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize, 1) == \ HAL_OK) { /* Enable the transfer error interrupt */ @@ -2581,8 +2583,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * } /********************* Deactivation of other instance *********************/ - if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || - (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || + ((cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && (cfg->DQSPort != 0U)) || + (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_otfdec.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_otfdec.c index af78206b1..f34f39611 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_otfdec.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_otfdec.c @@ -69,11 +69,11 @@ The compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions HAL_OTFDEC_RegisterCallback() + Use Functions @ref HAL_OTFDEC_RegisterCallback() to register an interrupt callback. [..] - Function HAL_OTFDEC_RegisterCallback() allows to register following callbacks: + Function @ref HAL_OTFDEC_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : OTFDEC error callback (+) MspInitCallback : OTFDEC Msp Init callback (+) MspDeInitCallback : OTFDEC Msp DeInit callback @@ -81,11 +81,11 @@ and a pointer to the user callback function. [..] - Use function HAL_OTFDEC_UnRegisterCallback to reset a callback to the default + Use function @ref HAL_OTFDEC_UnRegisterCallback to reset a callback to the default weak function. [..] - HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle, + @ref HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : OTFDEC error callback @@ -93,27 +93,27 @@ (+) MspDeInitCallback : OTFDEC Msp DeInit callback [..] - By default, after the HAL_OTFDEC_Init() and when the state is HAL_OTFDEC_STATE_RESET + By default, after the @ref HAL_OTFDEC_Init() and when the state is @ref HAL_OTFDEC_STATE_RESET all callbacks are set to the corresponding weak functions: - example HAL_OTFDEC_ErrorCallback(). + example @ref HAL_OTFDEC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_OTFDEC_Init()HAL_OTFDEC_DeInit() only when + reset to the legacy weak functions in the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the HAL_OTFDEC_Init()/HAL_OTFDEC_DeInit() + If MspInit or MspDeInit are not null, the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in HAL_OTFDEC_STATE_READY state only. + Callbacks can be registered/unregistered in @ref HAL_OTFDEC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_OTFDEC_STATE_READY or HAL_OTFDEC_STATE_RESET state, + in @ref HAL_OTFDEC_STATE_READY or @ref HAL_OTFDEC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_OTFDEC_RegisterCallback() before calling HAL_OTFDEC_DeInit() - or HAL_OTFDEC_Init() function. + using @ref HAL_OTFDEC_RegisterCallback() before calling @ref HAL_OTFDEC_DeInit() + or @ref HAL_OTFDEC_Init() function. [..] When the compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS is set to 0 or @@ -693,7 +693,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32 * @retval HAL state */ HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, - OTFDEC_RegionConfigTypeDef *Config, uint32_t lock) + const OTFDEC_RegionConfigTypeDef *Config, uint32_t lock) { OTFDEC_Region_TypeDef *region; uint32_t address; @@ -753,16 +753,16 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_ * @param pKey pointer at set of keys * @retval CRC value */ -uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey) +uint32_t HAL_OTFDEC_KeyCRCComputation(const uint32_t *pKey) { uint8_t crc7_poly = 0x7; - uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U}; + const uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U}; uint8_t i; uint8_t crc = 0; uint32_t j; uint32_t keyval; uint32_t k; - uint32_t *temp = pKey; + const uint32_t *temp = pKey; for (j = 0U; j < 4U; j++) { @@ -901,7 +901,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32 * the configuration information for OTFDEC module * @retval HAL state */ -HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec) +HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(const OTFDEC_HandleTypeDef *hotfdec) { return hotfdec->State; } @@ -914,9 +914,9 @@ HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec) * @param RegionIndex index of region the keys CRC of which is read * @retval Key CRC */ -uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex) +uint32_t HAL_OTFDEC_RegionGetKeyCRC(const OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex) { - OTFDEC_Region_TypeDef *region; + const OTFDEC_Region_TypeDef *region; uint32_t address; uint32_t keycrc; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pcd.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pcd.c index 221cdfc08..a50cac24b 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pcd.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pcd.c @@ -1453,7 +1453,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && - ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; @@ -1766,7 +1766,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1781,7 +1781,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; if (ep->is_in != 0U) @@ -2101,6 +2101,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t tes case TEST_SE0_NAK: case TEST_PACKET: case TEST_FORCE_EN: + USBx_DEVICE->DCTL &= ~(0x7U << 4); USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; break; @@ -2331,13 +2332,11 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint } #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - /** * @} */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pwr.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pwr.c index 60fb841d8..426272549 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pwr.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pwr.c @@ -412,7 +412,7 @@ void HAL_PWR_DisableBkUpAccess (void) * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. * @retval None. */ -void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) +void HAL_PWR_ConfigPVD (const PWR_PVDTypeDef *sConfigPVD) { /* Check the PVD configuration parameter */ if (sConfigPVD == NULL) diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pwr_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pwr_ex.c index 4b1a86e7c..6faff7386 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pwr_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_pwr_ex.c @@ -308,6 +308,10 @@ * PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. + * @note This API is deprecated and is kept only for backward compatibility's sake. + * The power supply configuration is handled as part of the system initialization + * process during startup. + * For more details, please refer to the power control chapter in the reference manual * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) @@ -1299,7 +1303,7 @@ void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock) * Cortex-M4. * @retval None. */ -void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams) +void HAL_PWREx_EnableWakeUpPin (const PWREx_WakeupPinTypeDef *sPinParams) { uint32_t pinConfig; uint32_t regMask; @@ -1973,7 +1977,7 @@ PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void) * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. * @retval None. */ -void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) +void HAL_PWREx_ConfigAVD (const PWREx_AVDTypeDef *sConfigAVD) { /* Check the parameters */ assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_qspi.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_qspi.c index 1d8fa10e6..56d07f22b 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_qspi.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_qspi.c @@ -2550,6 +2550,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } else @@ -2577,6 +2580,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } } @@ -2611,6 +2617,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateBytesSize | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } else @@ -2640,6 +2649,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + + /* Clear AR register */ + CLEAR_REG(hqspi->Instance->AR); } } } diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ramecc.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ramecc.c index d59992a95..ec1e1f34a 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ramecc.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_ramecc.c @@ -613,7 +613,7 @@ __weak void HAL_RAMECC_DetectErrorCallback(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval Failing address offset. */ -uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetFailingAddress(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -629,7 +629,7 @@ uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval Failing data low. */ -uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetFailingDataLow(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -645,7 +645,7 @@ uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval Failing data high. */ -uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetFailingDataHigh(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -661,7 +661,7 @@ uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval Hamming bits injected. */ -uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetHammingErrorCode(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -677,7 +677,7 @@ uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval State of bit (1 or 0). */ -uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_IsECCSingleErrorDetected(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -693,7 +693,7 @@ uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc) * Monitor. * @retval State of bit (1 or 0). */ -uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(const RAMECC_HandleTypeDef *hramecc) { /* Check the parameters */ assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance)); @@ -734,7 +734,7 @@ uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc) * specified RAMECC instance. * @retval RAMECC state. */ -HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc) +HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(const RAMECC_HandleTypeDef *hramecc) { /* Return the RAMECC state */ return hramecc->State; @@ -747,7 +747,7 @@ HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc) * specified RAMECC instance. * @retval RAMECC error code. */ -uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetError(const RAMECC_HandleTypeDef *hramecc) { /* Return the RAMECC error code */ return hramecc->ErrorCode; @@ -760,7 +760,7 @@ uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc) * specified RAMECC instance. * @retval RAMECC error code detected. */ -uint32_t HAL_RAMECC_GetRAMECCError(RAMECC_HandleTypeDef *hramecc) +uint32_t HAL_RAMECC_GetRAMECCError(const RAMECC_HandleTypeDef *hramecc) { /* Return the RAMECC error code detected*/ return hramecc->RAMECCErrorCode; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rcc.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rcc.c index 8c987ac8e..dad88545f 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rcc.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rcc.c @@ -919,7 +919,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { HAL_StatusTypeDef halstatus; uint32_t tickstart; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rcc_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rcc_ex.c index 96517ce08..b619c4ae5 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rcc_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rcc_ex.c @@ -58,8 +58,8 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider); -static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider); +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider); +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider); /* Exported functions --------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions @@ -3379,7 +3379,7 @@ void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) * @param pInit Pointer on RCC_CRSInitTypeDef structure * @retval None */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit) { uint32_t value; @@ -3690,7 +3690,7 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) * * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { uint32_t tickstart; @@ -3795,7 +3795,7 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D * * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rng.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rng.c index ef602992f..7f5142d28 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rng.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rng.c @@ -116,9 +116,9 @@ /* Health test control register information to use in CCM algorithm */ #define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ #if defined(RNG_VER_3_1) || defined(RNG_VER_3_0) -#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x000CAA74U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #else /* RNG_VER_3_2 */ -#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x00007274U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #endif /* RNG_VER_3_1 || RNG_VER_3_0 */ /** * @} @@ -216,7 +216,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0) /*!< magic number must be written immediately before to RNG_HTCRG */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1); - /* for best latency and to be compliant with NIST */ + /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG); #endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ @@ -257,12 +257,12 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Get tick */ tickstart = HAL_GetTick(); /* Check if data register contains valid random data */ - while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { hrng->State = HAL_RNG_STATE_ERROR; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; @@ -673,6 +673,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } } diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rng_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rng_ex.c index 70c554052..0bcb1add3 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rng_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rng_ex.c @@ -30,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNG_Ex +/** @addtogroup RNGEx * @brief RNG Extended HAL module driver. * @{ */ @@ -45,16 +45,16 @@ /* Health test control register information to use in CCM algorithm */ #define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ #if defined(RNG_VER_3_1) || defined(RNG_VER_3_0) -#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x000CAA74U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #else /* RNG_VER_3_2 */ -#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */ +#define RNG_HTCFG 0x00007274U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ #endif /* RNG_VER_3_1 || RNG_VER_3_0 */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Private_Constants +/** @addtogroup RNGEx_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -66,11 +66,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions * @{ */ -/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -141,7 +141,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0) /*!< magic number must be written immediately before to RNG_HTCRG */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1); - /* for best latency and to be compliant with NIST */ + /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG); #endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ @@ -283,7 +283,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim @@ -320,6 +320,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /* sequence to fully recover from a seed error */ status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } } else { diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rtc.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rtc.c index 140826c0f..81b4d05a1 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rtc.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rtc.c @@ -920,7 +920,7 @@ HAL_StatusTypeDef status; * to ensure consistency between the time and date values. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { uint32_t tmpreg; @@ -1052,7 +1052,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * Reading RTC current time locks the values in calendar shadow registers until Current date is read. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { uint32_t datetmpreg; @@ -1604,7 +1604,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { uint32_t tmpreg; uint32_t subsecondtmpreg; @@ -1883,7 +1883,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval HAL state */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc) { /* Return RTC handle state */ return hrtc->State; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rtc_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rtc_ex.c index 252dce91b..70ad6f438 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rtc_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_rtc_ex.c @@ -469,7 +469,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, const RTC_TamperTypeDef * sTamper) { uint32_t tmpreg; @@ -537,7 +537,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, const RTC_TamperTypeDef * sTamper) { uint32_t tmpreg; @@ -671,7 +671,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, const RTC_TamperTypeDef * sTamper) { uint32_t tmpreg; @@ -748,7 +748,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDef * sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, const RTC_TamperTypeDef * sTamper) { uint32_t tmpreg; @@ -981,7 +981,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t * @param sIntTamper Pointer to Internal Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper) +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper) { /* Check the parameters */ assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); @@ -1007,7 +1007,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_Inter * @param sIntTamper Pointer to Internal Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper) +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper) { /* Check the parameters */ assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); @@ -1063,7 +1063,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, ui * @param sAllTamper Pointer to active Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper) +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper) { uint32_t IER, CR1, CR2, ATCR1, CR, i, tickstart; @@ -1177,7 +1177,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active * @param pSeed Pointer to active tamper seed values. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed) +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed) { uint32_t i, tickstart; @@ -2129,7 +2129,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval Counter value */ -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) +uint32_t HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc) { /* Get the counter value */ return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); @@ -2273,7 +2273,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef * hrtc, ui * @param Data Data to be written in the specified Backup data register. * @retval None */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint32_t Data) +void HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint32_t Data) { uint32_t tmp; @@ -2282,9 +2282,9 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint /* Point on address of first backup register */ #if defined(TAMP) - tmp = (uint32_t) & (((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); + tmp = (uint32_t) &(((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); #else - tmp = (uint32_t) & (hrtc->Instance->BKP0R); + tmp = (uint32_t) &(hrtc->Instance->BKP0R); #endif /* TAMP */ tmp += (BackupRegister * 4U); @@ -2302,7 +2302,7 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint * specify the register. * @retval Read value */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister) +uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef * hrtc, uint32_t BackupRegister) { uint32_t tmp; @@ -2311,9 +2311,9 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister) /* Point on address of first backup register */ #if defined(TAMP) - tmp = (uint32_t) & (((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); + tmp = (uint32_t) &(((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); #else - tmp = (uint32_t) & (hrtc->Instance->BKP0R); + tmp = (uint32_t) &(hrtc->Instance->BKP0R); #endif /* TAMP */ tmp += (BackupRegister * 4U); @@ -2709,7 +2709,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef * hrtc) __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + hrtc->Instance->CR |= (uint32_t)RTC_CR_BYPSHAD; /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -2741,7 +2741,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef * hrtc) __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD); + hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BYPSHAD); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -2784,7 +2784,7 @@ HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, * @param Counter monotonic counter value * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance) +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance) { UNUSED(hrtc); UNUSED(Instance); diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sd.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sd.c index fea068085..ae33c6827 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sd.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sd.c @@ -56,7 +56,6 @@ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization - *** SD Card Initialization and configuration *** ================================================ [..] @@ -211,7 +210,7 @@ respectively HAL_SD_RegisterTransceiverCallback(). Use function HAL_SD_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: + weak (overridden) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. (+) ErrorCallback : callback when error occurs. @@ -227,9 +226,9 @@ respectively HAL_SD_UnRegisterTransceiverCallback(). By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. + all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SD_Init + reset to the legacy weak (overridden) functions in the HAL_SD_Init and HAL_SD_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -244,7 +243,7 @@ When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -261,6 +260,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_SD_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -439,7 +439,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) tickstart = HAL_GetTick(); while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -607,7 +607,6 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) return HAL_OK; } - /** * @brief Initializes the SD MSP. * @param hsd: Pointer to SD handle @@ -704,7 +703,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -746,10 +745,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 dataremaining = config.DataLength; while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = SDMMC_ReadFIFO(hsd->Instance); *tempbuff = (uint8_t)(data & 0xFFU); @@ -761,7 +760,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) @@ -889,7 +888,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -932,10 +931,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Write data to SDMMC Tx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = (uint32_t)(*tempbuff); tempbuff++; @@ -947,7 +946,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData tempbuff++; (void)SDMMC_WriteFIFO(hsd->Instance, &data); } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) @@ -1074,7 +1073,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -1169,7 +1168,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pD if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -1266,7 +1265,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -1310,7 +1309,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Enable transfer interrupts */ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - return HAL_OK; } else @@ -1365,7 +1363,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *p if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - add *= 512U; + add *= BLOCKSIZE; } /* Configure the SD DPSM (Data Path State Machine) */ @@ -1377,7 +1375,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *p config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMABASE0 = (uint32_t) pData ; @@ -1474,8 +1471,8 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui /* Get start and end block for high capacity cards */ if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { - start_add *= 512U; - end_add *= 512U; + start_add *= BLOCKSIZE; + end_add *= BLOCKSIZE; } /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ @@ -1765,7 +1762,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) * @param hsd: Pointer to sd handle * @retval HAL state */ -HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) +HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd) { return hsd->State; } @@ -1776,7 +1773,7 @@ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) * the configuration information. * @retval SD Error Code */ -uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) +uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd) { return hsd->ErrorCode; } @@ -1860,7 +1857,7 @@ __weak void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status) #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) /** * @brief Register a User SD Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @note The HAL_SD_RegisterCallback() may be called before HAL_SD_Init() in * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID * and HAL_SD_MSP_DEINIT_CB_ID. @@ -1965,7 +1962,7 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback /** * @brief Unregister a User SD Callback - * SD Callback is redirected to the weak (surcharged) predefined callback + * SD Callback is redirected to the weak (overridden) predefined callback * @note The HAL_SD_UnRegisterCallback() may be called before HAL_SD_Init() in * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID * and HAL_SD_MSP_DEINIT_CB_ID. @@ -2062,7 +2059,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba #if (USE_SD_TRANSCEIVER != 0U) /** * @brief Register a User SD Transceiver Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @param hsd : SD handle * @param pCallback : pointer to the Callback function * @retval status @@ -2100,7 +2097,7 @@ HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_ /** * @brief Unregister a User SD Transceiver Callback - * SD Callback is redirected to the weak (surcharged) predefined callback + * SD Callback is redirected to the weak (overridden) predefined callback * @param hsd : SD handle * @retval status */ @@ -2157,7 +2154,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); @@ -2236,8 +2233,8 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); - hsd->SdCard.LogBlockSize = 512U; + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / BLOCKSIZE); + hsd->SdCard.LogBlockSize = BLOCKSIZE; } else if (hsd->SdCard.CardType == CARD_SDHC_SDXC) { @@ -2246,7 +2243,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; - hsd->SdCard.BlockSize = 512U; + hsd->SdCard.BlockSize = BLOCKSIZE; hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; } else @@ -2363,7 +2360,6 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT status = HAL_ERROR; } - return status; } @@ -2374,7 +2370,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT * will contain the SD card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); @@ -2404,6 +2400,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t SDMMC_InitTypeDef Init; uint32_t errorstate; uint32_t sdmmc_clk; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ @@ -2833,7 +2830,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t tickstart = HAL_GetTick(); while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -2893,11 +2890,12 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { /* DIsable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); __SDMMC_CMDTRANS_DISABLE(hsd->Instance); /*we will send the CMD12 in all cases in order to stop the data transfers*/ - /*In case the data transfer just finished , the external memory will not respond and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/ + /*In case the data transfer just finished , the external memory will not respond + and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/ /*In case the data transfer aborted , the external memory will respond and will return HAL_SD_ERROR_NONE*/ /*Other scenario will return HAL_ERROR*/ @@ -2913,40 +2911,40 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { if (hsd->ErrorCode == HAL_SD_ERROR_NONE) { - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State = HAL_SD_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } } } if (hsd->ErrorCode == HAL_SD_ERROR_CMD_RSP_TIMEOUT) { - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State = HAL_SD_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } } } } else if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC) { - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State = HAL_SD_STATE_READY; - return HAL_TIMEOUT; - } + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } } } else @@ -2962,7 +2960,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) /*SDMMC ready for clear data flags*/ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_BUSYD0END); __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - /* If IDMA Context, disable Internal DMA */ + /* If IDMA Context, disable Internal DMA */ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; hsd->State = HAL_SD_STATE_READY; @@ -2973,7 +2971,6 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) return HAL_OK; } - /** * @brief Abort the current transfer and disable the SD (IT mode). * @param hsd: pointer to a SD_HandleTypeDef structure that contains @@ -3031,7 +3028,6 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) * @{ */ - /** * @brief Initializes the sd card. * @param hsd: Pointer to SD handle @@ -3237,7 +3233,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Check to CKSTOP */ while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3267,7 +3263,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Check VSWEND Flag */ while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) { - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3375,7 +3371,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } } - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3403,7 +3399,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) *pData = SDMMC_ReadFIFO(hsd->Instance); pData++; - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3538,7 +3534,6 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) } } - /** * @brief Finds the SD card SCR register value. * @param hsd: Pointer to SD handle @@ -3593,8 +3588,7 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) index++; } - - if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3624,11 +3618,11 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \ - ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24U) | ((tempscr[1] & SDMMC_8TO15BITS) << 8U) | \ + ((tempscr[1] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24U)); scr++; - *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \ - ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24U) | ((tempscr[0] & SDMMC_8TO15BITS) << 8U) | \ + ((tempscr[0] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24U)); } @@ -3649,10 +3643,10 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd) tmp = hsd->pRxBuffPtr; - if (hsd->RxXferSize >= 32U) + if (hsd->RxXferSize >= SDMMC_FIFO_SIZE) { /* Read data from SDMMC Rx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = SDMMC_ReadFIFO(hsd->Instance); *tmp = (uint8_t)(data & 0xFFU); @@ -3666,7 +3660,7 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd) } hsd->pRxBuffPtr = tmp; - hsd->RxXferSize -= 32U; + hsd->RxXferSize -= SDMMC_FIFO_SIZE; } } @@ -3684,10 +3678,10 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) tmp = hsd->pTxBuffPtr; - if (hsd->TxXferSize >= 32U) + if (hsd->TxXferSize >= SDMMC_FIFO_SIZE) { /* Write data to SDMMC Tx FIFO */ - for (count = 0U; count < 8U; count++) + for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++) { data = (uint32_t)(*tmp); tmp++; @@ -3701,7 +3695,7 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) } hsd->pTxBuffPtr = tmp; - hsd->TxXferSize -= 32U; + hsd->TxXferSize -= SDMMC_FIFO_SIZE; } } @@ -3750,7 +3744,6 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); - errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode); if (errorstate != HAL_SD_ERROR_NONE) { @@ -3768,8 +3761,7 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) } loop ++; } - - if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -3885,7 +3877,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeed loop ++; } - if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -4015,7 +4007,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) loop ++; } - if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; hsd->State = HAL_SD_STATE_READY; @@ -4142,12 +4134,12 @@ __weak void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd) */ } - /** * @} */ #endif /* HAL_SD_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sd_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sd_ex.c index 1cc19e313..aa50d0bf3 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sd_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sd_ex.c @@ -44,6 +44,7 @@ * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) #ifdef HAL_SD_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ @@ -303,6 +304,7 @@ HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABu */ #endif /* HAL_SD_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sdio.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sdio.c new file mode 100644 index 000000000..ddde94eb9 --- /dev/null +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sdio.c @@ -0,0 +1,2877 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_sdio.c + * @author MCD Application Team + * @brief SDIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital Input Output (SDIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this SDIO card. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + the user in HAL_SDIO_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDMMC memories which uses the HAL + SDMMC driver functions to interface with SDIO cards devices. + It is used as follows: + + (#)Initialize the SDMMC low level resources by implementing the HAL_SDIO_MspInit() API: + (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); + (##) SDMMC pins configuration for SDIO card + (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) NVIC configuration if you need to use interrupt process (HAL_SDIO_ReadExtended_DMA() + and HAL_SDIO_WriteExtended_DMA() APIs). + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_SDIO_ENABLE_IT() + and __HAL_SDIO_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SDIO_GET_IT(). + (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used. + + (#) At this stage, you can perform SDIO read/write/erase operations after SDIO card initialization. + + *** SDIO Card Initialization and configuration *** + ================================================ + [..] + To initialize the SDIO Card, use the HAL_SDIO_Init() function. It Initializes + SDMMC Peripheral(STM32 side) and the SDIO Card, and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Apply the SDIO Card initialization process at 400KHz. You can change or adapt this + frequency by adjusting the "ClockDiv" field. + The SDIO Card frequency (SDMMC_CK) is computed as follows: + + SDMMC_CK = SDMMCCLK / (2 * ClockDiv) + + In initialization mode and according to the SDIO Card standard, + make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. + + (#) Initialize the SDIO card. The API used is HAL_SDIO_Init(). + This phase allows the card initialization and identification. + + (#) Configure the SDIO Card Data transfer frequency. You can change or adapt this + frequency by adjusting the "ClockDiv" field by the API HAL_SDIO_ConfigFrequency(). + + (#) Configure the SDIO Card in wide bus mode: 4-bits data by the API HAL_SDIO_SetDataBusWidth(). + + (#) Configure the SDIO Card data block size by the API : HAL_SDIO_SetBlockSize(). + + (#) Configure the SDIO Card speed mode by the API : HAL_SDIO_SetSpeedMode(). + + (#) To custumize the SDIO Init card function for the enumeration card sequence, you can register a user callback + function by calling the HAL_SDIO_RegisterIdentifyCardCallback before the HAL_SDIO_Init() function. + + *** SDIO Card Read operation *** + ============================== + [..] + (+) You can read from SDIO card in polling mode by using function HAL_SDIO_ReadExtended(). + This function support only 2048-bytes block length (the block size should be + chosen by using the API HAL_SDIO_SetBlockSize). + + (+) You can read from SDIO card in DMA mode by using function HAL_SDIO_ReadExtended_DMA(). + This function support only 2048-bytes block length (the block size should be + chosen by using the API HAL_SDIO_SetBlockSize). + After this, you have to ensure that the transfer is done correctly. + You could also check the DMA transfer process through the SDIO Rx interrupt event. + + *** SDIO Card Write operation *** + =============================== + [..] + (+) You can write to SDIO card in polling mode by using function HAL_SDIO_WriteExtended(). + This function support only 2048-bytes block length (the block size should be + chosen by using the API HAL_SDIO_SetBlockSize). + + (+) You can write to SDIO card in DMA mode by using function HAL_SDIO_WriteExtended_DMA(). + This function support only 2048-bytes block length (the block size should be + chosen by using the API HAL_SDIO_SetBlockSize). + You could also check the DMA transfer process through the SDIO Tx interrupt event. + + + *** SDIO card common control register (CCCR) *** + ====================== + [..] + (+) The SDIO CCCR allow for quick host checking and control of an IO card's enable and interrupts on a per card and + per function basis. + To get the Card common control registers field, you can use the API HAL_SDIO_GetCardCommonControlRegister(). + + *** SDIO card Function basic register (FBR) *** + =========================== + [..] + (+) The SDIO card function basic register are used to allow the host to quickly determine the abilities and + requirements of each function. + (+) To get the SDIO function basic register information, you can use the API HAL_SDIO_GetCardFBRRegister(). + + *** SDIO HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SDIO HAL driver. + + (+) __HAL_SDIO_ENABLE_IT: Enable the SDIO device interrupt + (+) __HAL_SDIO_DISABLE_IT: Disable the SDIO device interrupt + (+) __HAL_SDIO_GET_FLAG: Check whether the specified SDIO flag is set or not + (+) __HAL_SDIO_CLEAR_FLAG: Clear the SDIO's pending flags + (+) __HAL_SDIO_GET_IT: Check whether the specified SDIO interrupt has occurred or not + (+) __HAL_SDIO_GET_IT_SOURCE: Checks whether the specified SDIO interrupt is enabled or not + + (@) You can refer to the SDIO HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SDIO_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_SDIO_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) MspInitCallback : SDIO MspInit. + (+) MspDeInitCallback : SDIO MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + For specific callbacks TransceiverCallback use dedicated register callbacks: + respectively HAL_SDIO_RegisterTransceiverCallback(). + + Use function HAL_SDIO_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) MspInitCallback : SDIO MspInit. + (+) MspDeInitCallback : SDIO MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + For specific callbacks TransceiverCallback use dedicated unregister callbacks: + respectively HAL_SDIO_UnRegisterTransceiverCallback(). + + By default, after the HAL_SDIO_Init and if the state is HAL_SDIO_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_SDIO_Init + and HAL_SDIO_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SDIO_Init and HAL_SDIO_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SDIO_RegisterCallback before calling HAL_SDIO_DeInit + or HAL_SDIO_Init function. + + When The compilation define USE_HAL_SDIO_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + *** SDIO peripheral IO interrupt *** + ============================================= + [..] + (+) Below the list of most used SDIO function to check and control the IO card's enable and interrupts on a per + functions basis. + + (+) HAL_SDIO_EnableIOFunctionInterrupt: Enable SDIO IO interrupt. + (+) HAL_SDIO_DisableIOFunctionInterrupt: Disable SDIO IO interrupt. + (+) HAL_SDIO_EnableIOFunction: Enable Function number(0-7) + (+) HAL_SDIO_DisableIOFunction: Disable Function number(0-7) + (+) HAL_SDIO_SelectIOFunction: Select a function number(0-7) + (+) HAL_SDIO_AbortIOFunction: Abort an IO read or write operation and free the SDIO bus. + (+) HAL_SDIO_EnableIOAsynInterrupt: Enable Bit of asynchronous interrupt + (+) HAL_SDIO_DisableIOAsynInterrupt: Disable Bit of asynchronous interrupt + + @endverbatim + ****************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ +#if defined (SDMMC1) || defined (SDMMC2) +#ifdef HAL_SDIO_MODULE_ENABLED + +/* Private define ----------------------------------------------------------------------------------------------------*/ +/** @addtogroup SDIO_Private_Defines + * @{ + */ +#define SDIO_INIT_FREQ 400000U /*!< Initialization phase : 400 kHz max */ +#define SDIO_TIMEOUT 1000U /*!< SDIO timeout millisecond */ + +#define SDIO_FUNCTION_0 0x00U /*!< SDIO_Functions 0 */ +#define SDIO_FUNCTION_1 0x01U /*!< SDIO_Functions 1 */ + +#define SDIO_READ 0x0U /*!< Read flag for cmd52 and cmd53 */ +#define SDIO_WRITE 0x1U /*!< Write flag for cmd52 and cmd53 */ + +#define SDIO_BUS_SPEED_SDR12 0x00U /*!< SDIO bus speed mode SDR12 */ +#define SDIO_BUS_SPEED_SDR25 0x02U /*!< SDIO bus speed mode SDR25 */ +#define SDIO_BUS_SPEED_SDR50 0x04U /*!< SDIO bus speed mode SDR50 */ +#define SDIO_BUS_SPEED_DDR50 0x08U /*!< SDIO bus speed mode DDR50 */ + +#define SDIO_CCCR_REG_NUMBER 0x16U /*!< SDIO card cccr register number */ + +#define SDIO_OCR_VDD_32_33 (1U << 20U) +#define SDIO_OCR_SDIO_S18R (1U << 24U) +/** + * @} + */ + +/* Private macro -----------------------------------------------------------------------------------------------------*/ +#define IS_SDIO_RAW_FLAG(ReadAfterWrite) (((ReadAfterWrite) == HAL_SDIO_WRITE_ONLY) || \ + ((ReadAfterWrite) == HAL_SDIO_READ_AFTER_WRITE)) + +#define IS_SDIO_FUNCTION(FN) (((FN) >= HAL_SDIO_FUNCTION_1) && ((FN) <= HAL_SDIO_FUNCTION_7)) + +#define IS_SDIO_SUPPORTED_BLOCK_SIZE(BLOCKSIZE) (((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_4BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_8BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_16BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_32BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_64BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_128BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_256BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE) || \ + ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE)) + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Functions SDIO Private Functions + * @{ + */ +static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio); +static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, + uint8_t *pData); +static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, + uint8_t *pData); +static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, + uint8_t *pData, uint16_t Size_byte); +static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size); +static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SDIO_Exported_Functions + * @{ + */ +/** @addtogroup SDIO_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the SDIO + device to be ready for use. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the SDIO according to the specified parameters in the + SDIO_HandleTypeDef and create the associated handle. + * @param hsdio: Pointer to the SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) +{ + SDIO_InitTypeDef Init; + uint32_t sdmmc_clk; + uint8_t data; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDMMC_ALL_INSTANCE(hsdio->Instance)); + assert_param(IS_SDMMC_CLOCK_EDGE(hsdio->Init.ClockEdge)); + assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsdio->Init.ClockPowerSave)); + assert_param(IS_SDMMC_BUS_WIDE(hsdio->Init.BusWide)); + assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsdio->Init.HardwareFlowControl)); + assert_param(IS_SDMMC_CLKDIV(hsdio->Init.ClockDiv)); + + /* Check the SDIO handle allocation */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_RESET) + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_SDIO_STATE_RESET only */ + hsdio->TxCpltCallback = HAL_SDIO_TxCpltCallback; + hsdio->RxCpltCallback = HAL_SDIO_RxCpltCallback; + hsdio->ErrorCallback = HAL_SDIO_ErrorCallback; +#if (USE_SDIO_TRANSCEIVER != 0U) + if (hsdio->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) + { + hsdio->DriveTransceiver_1_8V_Callback = HAL_SDIO_DriveTransceiver_1_8V_Callback; + } +#endif /* USE_SDIO_TRANSCEIVER */ + + if (hsdio->MspInitCallback == NULL) + { + hsdio->MspInitCallback = HAL_SDIO_MspInit; + } + /* Init the low level hardware */ + hsdio->MspInitCallback(hsdio); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_SDIO_MspInit(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } + + Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDMMC_BUS_WIDE_1B; + Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); + if (sdmmc_clk == 0U) + { + hsdio->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; + return HAL_ERROR; + } + Init.ClockDiv = sdmmc_clk / (2U * SDIO_INIT_FREQ); + /* Initialize SDMMC peripheral interface with default configuration */ + (void)SDMMC_Init(hsdio->Instance, Init); + + /* Set Power State to ON */ + (void)SDMMC_PowerState_ON(hsdio->Instance); + + /* wait 74 Cycles: required power up waiting time before starting the SDIO initialization sequence */ + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + + if (hsdio->SDIO_IdentifyCard == NULL) + { + hsdio->SDIO_IdentifyCard = SDIO_InitCard; + } + /* SDIO enumeration sequence */ + if (hsdio->SDIO_IdentifyCard(hsdio) != HAL_OK) + { + hsdio->State = HAL_SDIO_STATE_RESET; + return HAL_ERROR; + } + + /* Configure the SDMMC user parameters */ + Init.ClockEdge = hsdio->Init.ClockEdge; + Init.ClockPowerSave = hsdio->Init.ClockPowerSave; + Init.BusWide = hsdio->Init.BusWide; + Init.HardwareFlowControl = hsdio->Init.HardwareFlowControl; + Init.ClockDiv = hsdio->Init.ClockDiv; + (void)SDMMC_Init(hsdio->Instance, Init); + + data = (hsdio->Init.BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U; + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK) + { + return HAL_ERROR; + } + + hsdio->Context = SDIO_CONTEXT_NONE; + hsdio->State = HAL_SDIO_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initializes the SDIO device. + * @param hsdio: Pointer to the SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_DeInit(SDIO_HandleTypeDef *hsdio) +{ + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hsdio->Instance)); + + /* Check the SDIO handle allocation */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + /* Set Power State to OFF */ + (void)SDMMC_PowerState_OFF(hsdio->Instance); + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + if (hsdio->MspDeInitCallback == NULL) + { + hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit; + } + + /* DeInit the low level hardware */ + hsdio->MspDeInitCallback(hsdio); +#else + /* De-Initialize the MSP layer */ + HAL_SDIO_MspDeInit(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the SDIO MSP. + * @param hsdio: Pointer to SDIO handle + * @retval None + */ +__weak void HAL_SDIO_MspInit(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize SDIO MSP. + * @param hsdio: Pointer to SDIO handle + * @retval None + */ +__weak void HAL_SDIO_MspDeInit(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_MspDeInit could be implemented in the user file + */ +} +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group2 + * @brief + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to re-configure the SDIO peripheral. + +@endverbatim + * @{ + */ +/** + * @brief Enables wide bus operation for the requested card if supported by card. + * @param hsdio: Pointer to SDIO handle + * @param BusWide: Specifies the SDIO card wide bus mode + * This parameter can be one of the following values: + * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer + * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer + * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_SetDataBusWidth(SDIO_HandleTypeDef *hsdio, uint32_t BusWide) +{ + uint8_t data; + HAL_StatusTypeDef error_state = HAL_OK; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + data = (BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U; + MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_WIDBUS, + (BusWide == HAL_SDIO_4_WIRES_MODE) ? SDMMC_BUS_WIDE_4B : SDMMC_BUS_WIDE_1B); + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK) + { + error_state = HAL_ERROR; + } + } + else + { + error_state = HAL_ERROR; + } + + return error_state; +} + +/** + * @brief Update the SDIO Clock. + * @param hsdio: Pointer to SDIO handle. + * @param ClockSpeed: SDIO Clock speed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_ConfigFrequency(SDIO_HandleTypeDef *hsdio, uint32_t ClockSpeed) +{ + uint32_t ClockDiv; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + ClockDiv = (HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC)) / (2U * ClockSpeed); + MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_CLKDIV, ClockDiv); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Set the SDIO block size. + * @param hsdio: Pointer to SDIO handle + * @param function_nbr: Specifies the SDIO function number. + * @param BlockSize: Specifies the SDIO Block size to set. + * This parameter can be one of the following values @ref SDIO_Exported_Constansts_Group7. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_SetBlockSize(SDIO_HandleTypeDef *hsdio, uint8_t function_nbr, uint16_t BlockSize) +{ + HAL_SDIO_ExtendedCmd_TypeDef cmd53; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(function_nbr)); + assert_param(IS_SDIO_SUPPORTED_BLOCK_SIZE(BlockSize)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + /* Set SDIO F1 block size */ + cmd53.IOFunctionNbr = SDIO_FUNCTION_0; + cmd53.OpCode = HAL_SDIO_OP_CODE_AUTO_INC; + cmd53.Block_Mode = HAL_SDIO_MODE_BYTE; + cmd53.Reg_Addr = (function_nbr * 0x100UL) + 0x10UL; + if (SDIO_WriteExtended(hsdio, &cmd53, (uint8_t *)(&BlockSize), 2U) != HAL_OK) + { + return HAL_ERROR; + } + + hsdio->block_size = BlockSize; + + return HAL_OK; +} + +/** + * @brief Configure the data rate. + * @param hsdio: Pointer to SDIO handle + * @param DataRate: Specifies the SDIO data rate to set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_SetSpeedMode(SDIO_HandleTypeDef *hsdio, uint32_t DataRate) +{ + HAL_StatusTypeDef errorstate = HAL_OK; + uint8_t data; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + switch (DataRate) + { + case HAL_SDIOS_DATA_RATE_SDR25: + data = SDIO_BUS_SPEED_SDR25; + errorstate = SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR16_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data); + break; + + case HAL_SDIOS_DATA_RATE_SDR50: + data = SDIO_BUS_SPEED_SDR50; + errorstate = SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2U) | (SDIO_FUNCTION_0 << 1U) | (SDIO_FUNCTION_0 << 14U) + | SDMMC_SDIO_CCCR16_SD_BYTE3), HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data); + MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED, SDMMC_CLKCR_BUSSPEED); + break; + + case HAL_SDIOS_DATA_RATE_DDR50: + data = SDIO_BUS_SPEED_DDR50; + errorstate = SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2) | (SDIO_FUNCTION_0 << 1) | (SDIO_FUNCTION_0 << 14) | + SDMMC_SDIO_CCCR16_SD_BYTE3), HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data); + MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED, + SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED); + break; + default: /* SDR12 */ + break; + } + + return (errorstate != HAL_OK) ? HAL_ERROR : HAL_OK; +} + +/** + * @brief Reset SDIO Card + * @param hsdio: Pointer to SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_CardReset(SDIO_HandleTypeDef *hsdio) +{ + uint8_t data = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + /** To reset the SDIO module by CMD52 with writing to RES in CCCR or send CMD0 the card shall change the speed mode + * default speed mode. + * The reset cmd (cmd0) is only used for memory. In order to reset an I/O card or the I/O portion of a combo card, + * Use CMD52 to write 1 to the RES bit in the CCC(bit3 of register 6). + */ + if (SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2) | (SDIO_FUNCTION_0 << 1) | (SDIO_FUNCTION_0 << 14) | + SDMMC_SDIO_CCCR4_SD_BYTE2), + HAL_SDIO_WRITE_ONLY, + 0U, + &data) != HAL_OK) + { + return HAL_ERROR; + } + + hsdio->State = HAL_SDIO_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Get Card Common Control register (CCCR). + * @param hsdio: Pointer to SDIO handle. + * @param pCccr: Pointer to Cccr register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_GetCardCommonControlRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CCCR_TypeDef *pCccr) +{ + uint8_t tempBuffer[256] = {0U}; + uint32_t count; + + assert_param(hsdio != NULL); + assert_param(pCccr != NULL); + + if ((hsdio == NULL) || (pCccr == NULL)) + { + return HAL_ERROR; + } + + for (count = 0U; count <= SDIO_CCCR_REG_NUMBER; count++) + { + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0 + count, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &tempBuffer[count]) != + HAL_OK) + { + return HAL_ERROR; + } + } + + pCccr->cccr_revision = tempBuffer[0] & 0x0FU; + pCccr->sdio_revision = (tempBuffer[0] & 0xF0U) >> 4U; + pCccr->sd_spec_revision = tempBuffer[0x01U] & 0x0FU; + pCccr->bus_width_8Bit = ((tempBuffer[0x07U] & 0x04U) != 0U) ? HAL_SDIO_BUS_WIDTH_8BIT_SUPPORTED + : HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED; + pCccr->card_capability = (tempBuffer[0x08U] & 0xDFUL); + /* common CIS pointer */ + pCccr->commonCISPointer = tempBuffer[0x09U] | ((uint32_t)tempBuffer[(uint32_t)0x09U + 1U] << 8U) | + ((uint32_t)tempBuffer[(uint32_t)0x09U + 2U] << 16U); + + return HAL_OK; +} + +/** + * @brief Get Card Function Basic register(FBR). + * @param hsdio: Pointer to SDIO handle. + * @param pFbr: Pointer to Fbr register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_FBR_t *pFbr) +{ + uint8_t tempBuffer[256] = {0U}; + uint32_t count; + uint8_t func_idx; + + assert_param(hsdio != NULL); + assert_param(pFbr != NULL); + + if ((hsdio == NULL) || (pFbr == NULL)) + { + return HAL_ERROR; + } + + for (func_idx = 2U; func_idx <= SDIO_MAX_IO_NUMBER; func_idx++) + { + for (count = 0U; count <= SDIO_CCCR_REG_NUMBER; count++) + { + if (SDIO_ReadDirect(hsdio, (((uint32_t)SDMMC_SDIO_F1BR0 * (uint32_t)func_idx) + count), + HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &tempBuffer[count]) != HAL_OK) + { + return HAL_ERROR; + } + } + pFbr[(uint32_t)func_idx - 1U].ioStdFunctionCode = tempBuffer[0U] & 0x0FU; + pFbr[(uint32_t)func_idx - 1U].ioExtFunctionCode = tempBuffer[1U]; + pFbr[(uint32_t)func_idx - 1U].ioPointerToCIS = tempBuffer[9U] | ((uint32_t)tempBuffer[10U] << 8U) | + ((uint32_t)tempBuffer[11U] << 16U); + pFbr[(uint32_t)func_idx - 1U].ioPointerToCSA = tempBuffer[12U] | ((uint32_t)tempBuffer[13U] << 8U) | + ((uint32_t)tempBuffer[14U] << 16U); + if ((tempBuffer[2U] & 0x01U) != 0U) + { + pFbr[(uint32_t)func_idx - 1U].flags |= (uint8_t)HAL_SDIO_FBR_SUPPORT_POWER_SELECTION; + } + if ((tempBuffer[0U] & 0x40U) != 0U) + { + pFbr[(uint32_t)func_idx - 1U].flags |= (uint8_t)HAL_SDIO_FBR_SUPPORT_CSA; + } + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group3 + * @brief + * +@verbatim + ============================================================================== + ##### Data management functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data transfer from/to SDIO card. + +@endverbatim + * @{ + */ +/** + * @brief Read data from a specified address using the direct mode through cmd52. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Specifies the SDIO Argument. + * @param pData: pointer to the buffer that will contain the received data. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData) +{ + uint32_t cmd; + uint32_t errorstate; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + assert_param(IS_SDIO_RAW_FLAG(Argument->ReadAfterWrite)); + + if ((hsdio == NULL) || (Argument == NULL) || (NULL == pData)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + cmd = SDIO_READ << 31U; + cmd |= (((uint32_t)Argument->IOFunctionNbr) << 28U); + cmd |= (((uint32_t)Argument->ReadAfterWrite) << 27U); + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= 0U; + errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, pData); + + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + hsdio->State = HAL_SDIO_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + + +/** + * @brief Read data from a specified address using the direct mode through cmd52. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Specifies the SDIO Argument. + * @param Data: pointer to the buffer that will contain the received data. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data) +{ + uint32_t cmd; + uint32_t errorstate; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(IS_SDIO_RAW_FLAG(Argument->ReadAfterWrite)); + + if ((hsdio == NULL) || (Argument == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + cmd = SDIO_WRITE << 31U; + cmd |= ((uint32_t)Argument->IOFunctionNbr) << 28U; + cmd |= ((uint32_t)Argument->ReadAfterWrite) << 27U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= Data; + errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, &Data); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + hsdio->State = HAL_SDIO_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Read data from a specified address using extended mode through cmd53. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Pointer to SDIO argument + * @param pData: pointer to the buffer that will contain the data to transmit + * @param Size_byte: size to read. + * @param Timeout_Ms: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms) +{ + uint32_t cmd; + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t regCount; + uint8_t byteCount; + uint32_t data; + uint32_t dataremaining; + uint8_t *tempbuff = pData; + uint32_t nbr_of_block; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + + if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + /* Compute how many blocks are to be send for pData of length data_size to be send */ + nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size)); + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + /* Configure the SDIO DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */ + if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + /* (Argument & 0x1FFU) is to get the 9 bits of Block/Byte counts */ + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + /* (Argument & 0x1FFU) is to get the 9 bits of Block/Byte counts */ + config.DataLength = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC ; + /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */ + config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK : + SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + /* Correspond to the write or read bit of the CMD argument */ + /* Read */ + hsdio->Context = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_READ_MULTIPLE_BLOCK : + SDIO_CONTEXT_READ_SINGLE_BLOCK; + cmd = SDIO_READ << 31U; + cmd |= Argument->IOFunctionNbr << 28U; + cmd |= Argument->Block_Mode << 27U; + cmd |= Argument->OpCode << 26U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= (Size_byte & 0x1FFU); + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */ + /* Poll on SDMMC flags */ + dataremaining = config.DataLength; + + while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + { + /* Read data from SDMMC Rx FIFO */ + for (regCount = 0U; regCount < 8U; regCount++) + { + data = SDMMC_ReadFIFO(hsdio->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + } + dataremaining -= 32U; + } + else if (dataremaining < 32U) + { + while ((dataremaining > 0U) && !(__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOE))) + { + data = SDMMC_ReadFIFO(hsdio->Instance); + for (byteCount = 0U; byteCount < 4U; byteCount++) + { + if (dataremaining > 0U) + { + *tempbuff = (uint8_t)((data >> (byteCount * 8U)) & 0xFFU); + tempbuff++; + dataremaining--; + } + } + } + } + else + { + /* Nothing to do */ + } + if ((HAL_GetTick() - tickstart) >= Timeout_Ms) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + /* Get error state */ + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_RX_OVERRUN; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + hsdio->State = HAL_SDIO_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Write data from a specified address using extended mode through cmd53. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Pointer to SDIO argument + * @param pData: pointer to the buffer that will contain the data to transmit + * @param Size_byte: Block size to write. + * @param Timeout_Ms: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms) +{ + uint32_t cmd; + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t regCount; + uint8_t byteCount; + uint32_t data; + uint32_t dataremaining; + uint8_t *u32tempbuff = pData; + uint32_t nbr_of_block; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + + if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + /* Compute how many blocks are to be send for pData of length data_size to be send */ + nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size)); + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + /* Configure the SDIO DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + config.DataLength = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */ + config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK : + SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + /* Correspond to the write or read bit of the CMD argument */ + hsdio->Context = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK : + SDIO_CONTEXT_WRITE_SINGLE_BLOCK; + cmd = SDIO_WRITE << 31U; + cmd |= Argument->IOFunctionNbr << 28U; + cmd |= Argument->Block_Mode << 27U; + cmd |= Argument->OpCode << 26U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= (Size_byte & 0x1FFU); + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + SDMMC_FLAG_DATAEND)) + { + + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + { + /* Read data from SDMMC Rx FIFO */ + for (regCount = 0U; regCount < 8U; regCount++) + { + hsdio->Instance->FIFO = *u32tempbuff; + u32tempbuff++; + } + dataremaining -= 32U; + } + else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE))) + { + uint8_t *u8buff = (uint8_t *)u32tempbuff; + while (dataremaining > 0U) + { + data = 0U; + for (byteCount = 0U; (byteCount < 4U) && (dataremaining > 0U); byteCount++) + { + data |= ((uint32_t)(*u8buff) << (byteCount << 3U)); + u8buff++; + dataremaining--; + } + hsdio->Instance->FIFO = data; + } + } + if (((HAL_GetTick() - tickstart) >= Timeout_Ms)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + /* Get error state */ + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_TX_UNDERRUN; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + hsdio->State = HAL_SDIO_STATE_READY; + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Read data from a specified address using extended mode through cmd53 in DMA mode. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Pointer to SDIO argument + * @param pData: pointer to the buffer that will contain the data to transmit + * @param Size_byte: Block size to write. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint8_t *p_dma_buffer; + uint32_t cmd; + uint32_t nbr_of_block; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + + if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + p_dma_buffer = (uint8_t *)pData; + hsdio->pRxBuffPtr = (uint8_t *)pData; + hsdio->RxXferSize = Size_byte; + hsdio->next_data_addr = (uint32_t)pData; + + /* Compute how many blocks are to be send for pData of length data_size to be send */ + nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size)); + + if (nbr_of_block != 0U) + { + hsdio->remaining_data = (Size_byte - (hsdio->block_size * nbr_of_block)); + hsdio->next_reg_addr = (Argument->Reg_Addr) | ((((nbr_of_block * hsdio->block_size) >> 1U) & 0x3FFFU) << 1U) + | ((hsdio->remaining_data <= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? 1U : 0U); + hsdio->next_data_addr += (nbr_of_block * hsdio->block_size); + } + else + { + hsdio->next_data_addr += (Size_byte < HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? Size_byte : + HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + if (hsdio->remaining_data != 0U) + { + hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? + (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) : + (Size_byte - hsdio->remaining_data); + hsdio->next_reg_addr += (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? \ + (HAL_SDIO_DATA_BLOCK_SIZE_512BYTE + 1U) : (Size_byte + 1U); + } + } + + /* DMA configuration (use single buffer) */ + hsdio->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + hsdio->Instance->IDMABASE0 = (uint32_t)p_dma_buffer; + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + config.DataLength = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC ; + config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK : + SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + /* Read */ + hsdio->Context = (uint32_t)((Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_READ_MULTIPLE_BLOCK : + SDIO_CONTEXT_READ_SINGLE_BLOCK) | SDIO_CONTEXT_DMA; + + cmd = SDIO_READ << 31U; + cmd |= Argument->IOFunctionNbr << 28U; + cmd |= Argument->Block_Mode << 27U; + cmd |= Argument->OpCode << 26U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= ((nbr_of_block == 0U) ? Size_byte : nbr_of_block) & 0x1FFU; + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + /* Enable interrupt */ + __HAL_SDIO_ENABLE_IT(hsdio, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Write data from a specified address using extended mode through cmd53 in DMA mode. + * @param hsdio: Pointer to SDIO handle + * @param Argument: Pointer to SDIO argument + * @param pData: pointer to the buffer that will contain the data to transmit + * @param Size_byte: Block size to write. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte) +{ + uint32_t cmd; + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint8_t *p_dma_buffer; + uint32_t nbr_of_block; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(Argument != NULL); + assert_param(pData != NULL); + + if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL)) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + hsdio->State = HAL_SDIO_STATE_BUSY; + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + p_dma_buffer = (uint8_t *)pData; + hsdio->pTxBuffPtr = (uint8_t *)pData; + hsdio->TxXferSize = Size_byte; + hsdio->next_data_addr = (uint32_t)pData; + + nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size)); + + if (nbr_of_block != 0U) + { + hsdio->remaining_data = (Size_byte - (hsdio->block_size * nbr_of_block)); + if (hsdio->block_size <= 128U) + { + hsdio->next_reg_addr = (Argument->Reg_Addr) | + ((((nbr_of_block * hsdio->block_size) >> 1U) & 0x3FFFU) << 1U) | + ((hsdio->remaining_data <= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? 1U : 0U); + } + else + { + hsdio->next_reg_addr = (nbr_of_block * hsdio->block_size) >> 1U; + } + hsdio->next_data_addr += (nbr_of_block * hsdio->block_size); + } + else + { + hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? + (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) : + (Size_byte - hsdio->remaining_data); + if (hsdio->remaining_data != 0U) + { + hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? + (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) : + (Size_byte - hsdio->remaining_data); + hsdio->next_reg_addr += ((Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? \ + (HAL_SDIO_DATA_BLOCK_SIZE_512BYTE >> 1U) : (Size_byte >> 1U)) | + (((hsdio->remaining_data > 0U) ? 0U : 1U)); + } + hsdio->next_data_addr += (Size_byte < HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? Size_byte : + HAL_SDIO_DATA_BLOCK_SIZE_512BYTE; + } + + /* DMA configuration (use single buffer) */ + hsdio->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; + hsdio->Instance->IDMABASE0 = (uint32_t)p_dma_buffer; + + /* Configure the SDIO DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + config.DataLength = (Size_byte > HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? HAL_SDIO_DATA_BLOCK_SIZE_512BYTE : Size_byte; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK + : SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + /* Write */ + hsdio->Context = (uint32_t)((Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? + SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK : + SDIO_CONTEXT_WRITE_SINGLE_BLOCK) | SDIO_CONTEXT_DMA; + cmd = SDIO_WRITE << 31U; + cmd |= Argument->IOFunctionNbr << 28U; + cmd |= Argument->Block_Mode << 27U; + cmd |= Argument->OpCode << 26U; + cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= ((nbr_of_block == 0U) ? ((Size_byte > HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? + HAL_SDIO_DATA_BLOCK_SIZE_512BYTE : Size_byte) : nbr_of_block) & 0x1FFU; + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED | + SDMMC_ERROR_GENERAL_UNKNOWN_ERR)) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + } + /* Enable interrupt */ + __HAL_SDIO_ENABLE_IT(hsdio, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group4 + * @brief + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set callback functions allowing to manage the data transfer from/to SDIO card. + +@endverbatim + * @{ + */ +/** + * @brief This function handles SDIO device interrupt request. + * @param hsdio: Pointer to SDIO handle + * @retval None + */ +void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio) +{ + HAL_SDIO_ExtendedCmd_TypeDef CMD53_desc; + HAL_StatusTypeDef errorstate; + uint32_t ctx = hsdio->Context; + uint32_t flags; + + flags = READ_REG(((SDMMC_TypeDef *)((uint32_t)(hsdio)->Instance))->STA); + + if (READ_BIT(flags, SDMMC_FLAG_SDIOIT) != 0U) + { + (void)SDIO_IOFunction_IRQHandler(hsdio); + } + + if (READ_BIT(flags, SDMMC_FLAG_DATAEND) != 0U) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_FLAG_DATAEND); + + hsdio->State = HAL_SDIO_STATE_READY; + + __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | + SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF); + + __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_IDMABTC); + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + if ((ctx & SDIO_CONTEXT_DMA) != 0U) + { + hsdio->Instance->DLEN = 0; + hsdio->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + hsdio->Context = SDIO_CONTEXT_NONE; + hsdio->State = HAL_SDIO_STATE_READY; + } + + if (hsdio->remaining_data != 0U) + { + CMD53_desc.Block_Mode = HAL_SDIO_MODE_BYTE; + CMD53_desc.Reg_Addr = hsdio->next_reg_addr; + CMD53_desc.IOFunctionNbr = 1; + CMD53_desc.OpCode = 1; + if (((ctx & SDIO_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((ctx & SDIO_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { + hsdio->pRxBuffPtr = (uint8_t *)hsdio->next_data_addr; + errorstate = HAL_SDIO_ReadExtended_DMA(hsdio, &CMD53_desc, hsdio->pRxBuffPtr, hsdio->remaining_data); + } + else + { + hsdio->pTxBuffPtr = (uint8_t *)hsdio->next_data_addr; + errorstate = HAL_SDIO_WriteExtended_DMA(hsdio, &CMD53_desc, hsdio->pTxBuffPtr, hsdio->remaining_data); + } + if (errorstate != HAL_OK) + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1) + hsdio->ErrorCallback(hsdio); +#else + HAL_SDIO_ErrorCallback(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } + } + else if (((ctx & SDIO_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((ctx & SDIO_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + hsdio->RxCpltCallback(hsdio); +#else + HAL_SDIO_RxCpltCallback(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } + else + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + hsdio->TxCpltCallback(hsdio); +#else + HAL_SDIO_TxCpltCallback(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } + } + + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR)) + { +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1) + hsdio->ErrorCallback(hsdio); +#else + HAL_SDIO_ErrorCallback(hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Tx Transfer completed callbacks + * @param hsdio: Pointer to SDIO handle + * @retval None + */ +__weak void HAL_SDIO_TxCpltCallback(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hsdio: Pointer SDIO handle + * @retval None + */ +__weak void HAL_SDIO_RxCpltCallback(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief SDIO error callbacks + * @param hsdio: Pointer SDIO handle + * @retval None + */ +__weak void HAL_SDIO_ErrorCallback(SDIO_HandleTypeDef *hsdio) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief SDIO IO Function complete callback + * @param hsdio: Pointer SDIO handle + * @param func: SDIO IO Function + * @retval None + */ +__weak void HAL_SDIO_IOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t func) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + UNUSED(func); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_ErrorCallback can be implemented in the user file + */ +} + +#if (USE_SDIO_TRANSCEIVER != 0U) +/** + * @brief Enable/Disable the SDIO Transceiver 1.8V Mode Callback. + * @param hsdio: Pointer SDIO handle + * @param status: Voltage Switch State + * @retval None + */ +__weak void HAL_SDIO_DriveTransceiver_1_8V_Callback(SDIO_HandleTypeDef *hsdio, FlagStatus status) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdio); + UNUSED(status); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SDIO_EnableTransceiver could be implemented in the user file + */ +} +#endif /* USE_SDIO_TRANSCEIVER */ + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SDIO Callback + * To be used instead of the weak (overridden) predefined callback + * @param hsdio : SDIO handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SDIO_TX_CPLT_CB_ID SDIO Tx Complete Callback ID + * @arg @ref HAL_SDIO_RX_CPLT_CB_ID SDIO Rx Complete Callback ID + * @arg @ref HAL_SDIO_ERROR_CB_ID SDIO Error Callback ID + * @arg @ref HAL_SDIO_MSP_INIT_CB_ID SDIO MspInit Callback ID + * @arg @ref HAL_SDIO_MSP_DEINIT_CB_ID SDIO MspDeInit Callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID, + pSDIO_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(pCallback != NULL); + + if (pCallback == NULL) + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + switch (CallbackID) + { + case HAL_SDIO_TX_CPLT_CB_ID : + hsdio->TxCpltCallback = pCallback; + break; + case HAL_SDIO_RX_CPLT_CB_ID : + hsdio->RxCpltCallback = pCallback; + break; + case HAL_SDIO_ERROR_CB_ID : + hsdio->ErrorCallback = pCallback; + break; + case HAL_SDIO_MSP_INIT_CB_ID : + hsdio->MspInitCallback = pCallback; + break; + case HAL_SDIO_MSP_DEINIT_CB_ID : + hsdio->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsdio->State == HAL_SDIO_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SDIO_MSP_INIT_CB_ID : + hsdio->MspInitCallback = pCallback; + break; + case HAL_SDIO_MSP_DEINIT_CB_ID : + hsdio->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User SDIO Callback + * SDIO Callback is redirected to the weak (overridden) predefined callback. + * @note The HAL_SDIO_UnRegisterCallback() may be called before HAL_SDIO_Init() in + * HAL_SDIO_STATE_RESET to register callbacks for HAL_SDIO_MSP_INIT_CB_ID + * and HAL_SDIO_MSP_DEINIT_CB_ID. + * @param hsdio : SDIO handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values @ref SDIO_Exported_Types_Group3. + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + switch (CallbackID) + { + case HAL_SDIO_TX_CPLT_CB_ID : + hsdio->TxCpltCallback = HAL_SDIO_TxCpltCallback; + break; + case HAL_SDIO_RX_CPLT_CB_ID : + hsdio->RxCpltCallback = HAL_SDIO_RxCpltCallback; + break; + case HAL_SDIO_ERROR_CB_ID : + hsdio->ErrorCallback = HAL_SDIO_ErrorCallback; + break; + case HAL_SDIO_MSP_INIT_CB_ID : + hsdio->MspInitCallback = HAL_SDIO_MspInit; + break; + case HAL_SDIO_MSP_DEINIT_CB_ID : + hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit; + break; + default : + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else if (hsdio->State == HAL_SDIO_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SDIO_MSP_INIT_CB_ID : + hsdio->MspInitCallback = HAL_SDIO_MspInit; + break; + case HAL_SDIO_MSP_DEINIT_CB_ID : + hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit; + break; + default : + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + break; + } + } + else + { + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) +/** + * @brief Register a User SDIO Transceiver Callback + * To be used instead of the weak (overridden) predefined callback + * @param hsdio : SDIO handle + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_TransceiverCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->DriveTransceiver_1_8V_Callback = pCallback; + } + else + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User SDIO Transceiver Callback + * SDIO Callback is redirected to the weak (overridden) predefined callback + * @param hsdio : SDIO handle + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hsdio->State == HAL_SDIO_STATE_READY) + { + hsdio->DriveTransceiver_1_8V_Callback = HAL_SDIO_DriveTransceiver_1_8V_Callback; + } + else + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_SDIO_TRANSCEIVER */ + +/** + * @brief Register a User SDIO Identification Callback + * @param hsdio: Pointer to SDIO handle + * @param pCallback: pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(pCallback != NULL); + + if (pCallback == NULL) + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + hsdio->SDIO_IdentifyCard = pCallback; + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group5 + * @brief + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the SDIO card operations. + +@endverbatim + * @{ + */ +/** + * @brief return the SDIO state + * @param hsdio: Pointer to SDIO handle + * @retval HAL state + */ +HAL_SDIO_StateTypeDef HAL_SDIO_GetState(const SDIO_HandleTypeDef *hsdio) +{ + return hsdio->State; +} + +/** + * @brief Return the SDIO error code + * @param hsdio : Pointer to a SDIO_HandleTypeDef structure that contains the configuration information. + * @retval SDIO Error Code + */ +uint32_t HAL_SDIO_GetError(const SDIO_HandleTypeDef *hsdio) +{ + return hsdio->ErrorCode; +} + +/** + * @} + */ + +/** @addtogroup SDIO_Exported_Functions_Group6 + * @brief + * +@verbatim + ============================================================================== + ##### Peripheral IO interrupt ##### + ============================================================================== + [..] + This subsection provides a set functions allowing to enable/disable IO functions interrupt features + on the SDIO card. + +@endverbatim + * @{ + */ +/** + * @brief Enable SDIO IO interrupt. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + uint8_t intEn = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &intEn) != HAL_OK) + { + return HAL_ERROR; + } + + /* if already enable , do not need enable again */ + if ((((intEn >> (uint32_t)IOFunction) & 0x01U) == 0x01U) && ((intEn & 0x01U) != 0U)) + { + return HAL_OK; + } + else + { + intEn |= (1U << (uint32_t)IOFunction) | 0x01U; + hsdio->IOInterruptNbr++; + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, + &intEn) != HAL_OK) + { + return HAL_ERROR; + } + + __HAL_SDIO_ENABLE_IT(hsdio, SDMMC_IT_SDIOIT); + + /* Enable host SDIO interrupt operations */ + __SDMMC_OPERATION_ENABLE(hsdio->Instance); + + return HAL_OK; +} + +/** + * @brief Enable SDIO IO interrupt. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_DisableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + uint8_t intEn = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &intEn) != HAL_OK) + { + return HAL_ERROR; + } + + /* if already disable , do not need enable again */ + if (((intEn >> (uint32_t)IOFunction) & 0x01U) == 0x00U) + { + return HAL_OK; + } + else + { + /* disable the interrupt, don't disable the interrupt master here */ + intEn &= ~(1U << (uint32_t)IOFunction); + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + &intEn) != HAL_OK) + { + return HAL_ERROR; + } + + if (hsdio->IOInterruptNbr > 1U) + { + hsdio->IOInterruptNbr--; + } + else + { + hsdio->IOInterruptNbr = 0U; + __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_SDIOIT); + } + return HAL_OK; +} + +/** + * @brief Enable SDIO IO Enable. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + uint8_t ioEn = 0U; + uint8_t ioReady = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioEn) != HAL_OK) + { + return HAL_ERROR; + } + + /* if already enable , do not need to enable again */ + if (((ioEn >> (uint32_t)IOFunction) & 0x01U) == 0x01U) + { + return HAL_OK; + } + else + { + ioEn |= (1U << (uint32_t)IOFunction); + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, &ioEn) != HAL_OK) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioReady) != HAL_OK) + { + return HAL_ERROR; + } + /* check if IO ready */ + if ((ioReady & (1U << (uint32_t)IOFunction)) != 0U) + { + return HAL_OK; + } + + return HAL_ERROR; +} + +/** + * @brief Disable SDIO IO Enable. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_DisableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + uint8_t ioEn = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioEn) != HAL_OK) + { + return HAL_ERROR; + } + + /* if already enable , do not need enable again */ + if (((ioEn >> (uint32_t)IOFunction) & 0x01U) == 0x00U) + { + return HAL_OK; + } + else + { + ioEn &= ~(1U << (uint32_t)IOFunction); + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, &ioEn) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Select SDIO IO Enable. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction: Specifies the SDIO IO function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_SelectIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR12_SD_BYTE1, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + (uint8_t *)&IOFunction) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Abort IO transfer. + * @param hsdio: Pointer to SDIO handle + * @param IOFunction IO number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_AbortIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + (uint8_t *)&IOFunction) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Enable Assynchrone interrupt. + * @param hsdio: Pointer to SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio) +{ + uint8_t enable_asyn_it = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &enable_asyn_it) + != HAL_OK) + { + return HAL_ERROR; + } + + /* if already enable , do not need enable again */ + if ((enable_asyn_it & 0x02U) == 0x02U) + { + return HAL_OK; + } + else + { + enable_asyn_it |= 0x02U; + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + &enable_asyn_it) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disable Assynchrone interrupt. + * @param hsdio: Pointer to SDIO handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio) +{ + uint8_t enable_asyn_it = 0U; + + /* Check the parameters */ + assert_param(hsdio != NULL); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &enable_asyn_it) + != HAL_OK) + { + return HAL_ERROR; + } + + /* if already disable , do not need disable again */ + if ((enable_asyn_it & 0x02U) == 0x00U) + { + return HAL_OK; + } + else + { + enable_asyn_it &= (uint8_t) ~(0x02U); + } + + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, + &enable_asyn_it) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief sdio set io IRQ handler. + * @param hsdio Pointer to SDIO handle + * @param IOFunction IO function io number. + * @param Callback io IRQ handler. + */ +HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, + HAL_SDIO_IOFunction_CallbackTypeDef pCallback) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(IS_SDIO_FUNCTION(IOFunction)); + + /* Check the SDIO peripheral handle parameter */ + if (hsdio == NULL) + { + return HAL_ERROR; + } + + hsdio->SDIO_IOFunction_Callback[(uint32_t)IOFunction] = pCallback; + hsdio->IOFunctionMask |= (1U << (uint8_t)IOFunction); + + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private function --------------------------------------------------------------------------------------------------*/ +/** @addtogroup SDIO_Private_Functions + * @{ + */ +/** + * @brief Initializes the SDIO device. + * @param hsdio: Pointer to the SDIO handle + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio) +{ + uint32_t errorstate; + uint32_t timeout = 0U; + uint16_t sdio_rca = 1U; + uint32_t Resp4; + uint32_t nbr_of_func; + + /* Identify card operating voltage */ + errorstate = SDMMC_CmdGoIdleState(hsdio->Instance); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + + /* Check the power State */ + if (SDMMC_GetPowerState(hsdio->Instance) == 0U) + { + return HAL_ERROR; + } + + /* Send CMD5 */ + errorstate = SDMMC_CmdSendOperationcondition(hsdio->Instance, 0U, &Resp4); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + + nbr_of_func = ((Resp4 & 0x70000000U) >> 28U); + /* Check if Nbr of function > 0 and OCR valid */ + if (nbr_of_func > 0U) + { + /* Send CMD5 with arg= S18R, WV*/ + if (SDMMC_CmdSendOperationcondition(hsdio->Instance, (SDIO_OCR_VDD_32_33 | SDIO_OCR_SDIO_S18R), &Resp4) + != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + /* Check if IORDY = 1 and S18A = 1 */ + if ((((Resp4 & 0x80000000U) >> 31U) != 0U) && (((Resp4 & 0x1000000U) >> 24U) != 0U)) + { + /* Send CMD11 to switch 1.8V mode */ + errorstate = SDMMC_CmdVoltageSwitch(hsdio->Instance); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + } + else + { + /* S18A is not supported */ + } + } + + /** Cmd3 is sent while response is SDMMC_ERROR_ILLEGAL_CMD, due to the partial init test done before + * (sending cmd0 after the sequence cmd0/cmd3 is sent is considered illegal). + */ + do + { + errorstate = SDMMC_CmdSetRelAdd(hsdio->Instance, &sdio_rca); + timeout++; + HAL_Delay(1); + } while ((errorstate == SDMMC_ERROR_ILLEGAL_CMD) && (timeout != SDIO_TIMEOUT)); + + if ((timeout == SDIO_TIMEOUT) || (errorstate != HAL_SDIO_ERROR_NONE)) + { + return HAL_ERROR; + } + + /* Select the Card ( Sending CMD7)*/ + errorstate = SDMMC_CmdSelDesel(hsdio->Instance, (uint32_t)(((uint32_t)sdio_rca) << 16U)); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Read 1 byte data. + * @param hsdio: Pointer to SDIO handle + * @param cmd_arg: formatted CMD52 structure + * @param pData: pointer to write or read data + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, + uint32_t function_nbr, uint8_t *pData) +{ + uint32_t errorstate; + uint32_t cmd; + + cmd = SDIO_READ << 31U; + cmd |= function_nbr << 28U; + cmd |= raw << 27U; + cmd |= (addr & 0x1FFFFU) << 9U; + errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, pData); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + return HAL_OK; +} + +/** + * @brief Write 1 byte data. + * @param hsdio: Pointer to SDIO handle + * @param cmd_arg: formatted CMD52 structure + * @param pData: pointer to write or read data + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, + uint32_t function_nbr, uint8_t *pData) +{ + uint32_t errorstate; + uint32_t cmd; + uint8_t response; + + cmd = SDIO_WRITE << 31U; + cmd |= function_nbr << 28U; + cmd |= raw << 27U; + cmd |= (addr & 0x1FFFFU) << 9U; + cmd |= ((uint32_t) * pData & 0x000000FFU); + errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, &response); + + if (errorstate != HAL_SDIO_ERROR_NONE) + { + hsdio->ErrorCode |= errorstate; + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + + /* Clear all the static flags */ + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + return HAL_OK; +} + +/** + * @brief Write multiple data with a single command. + * @param hsdio: Pointer to SDIO handle + * @param cmd_arg: formatted cmd53 structure + * @param Size_byte: block size if CMD53 defined in HAL_SDIO_MODE_BLOCK + * @param pData: pointer to write or read data + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, + uint8_t *pData, uint16_t Size_byte) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t regCount; + uint8_t byteCount; + uint32_t data; + uint32_t dataremaining; + uint32_t *u32tempbuff = (uint32_t *)(uint32_t)pData; + SDMMC_TypeDef *SDMMCx; + uint32_t cmd; + uint32_t nbr_of_block; + + hsdio->ErrorCode = HAL_SDIO_ERROR_NONE; + + /* Compute how many blocks are to be send for pData of length data_size to be send */ + nbr_of_block = (((uint32_t)Size_byte & ~((uint32_t)hsdio->block_size & 1U))) >> __CLZ(__RBIT(hsdio->block_size)); + + /* Initialize data control register */ + if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U) + { + hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN; + } + else + { + hsdio->Instance->DCTRL = 0U; + } + + /* Configure the SDIO DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + if (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) + { + config.DataLength = (uint32_t)(nbr_of_block * hsdio->block_size); + config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size); + } + else + { + config.DataLength = Size_byte; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B; + } + + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK : + SDMMC_TRANSFER_MODE_SDIO; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hsdio->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hsdio->Instance); + + hsdio->Context = (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK : + SDIO_CONTEXT_WRITE_SINGLE_BLOCK; + cmd = SDIO_WRITE << 31U; + cmd |= cmd_arg->IOFunctionNbr << 28U; + cmd |= cmd_arg->Block_Mode << 27U; + cmd |= cmd_arg->OpCode << 26U; + cmd |= (cmd_arg->Reg_Addr & 0x1FFFFU) << 9U; + cmd |= (((uint32_t)Size_byte) & 0x1FFU); + errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd); + if (errorstate != HAL_SDIO_ERROR_NONE) + { + MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->ErrorCode |= errorstate; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + + SDMMCx = hsdio->Instance; + dataremaining = config.DataLength; + while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + SDMMC_FLAG_DATAEND)) + { + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + { + for (regCount = 8U; regCount > 0U; regCount--) + { + SDMMCx->FIFO = *u32tempbuff; + u32tempbuff++; + } + dataremaining -= 32U; + } + else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE))) + { + uint8_t *u8buff = (uint8_t *)u32tempbuff; + while (dataremaining > 0U) + { + data = 0U; + for (byteCount = 0U; (byteCount < 4U) && (dataremaining > 0U); byteCount++) + { + data |= ((uint32_t)(*u8buff) << (byteCount << 3U)); + u8buff++; + dataremaining--; + } + SDMMCx->FIFO = data; + } + } + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + + __SDMMC_CMDTRANS_DISABLE(hsdio->Instance); + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR)) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS); + hsdio->ErrorCode |= HAL_SDIO_ERROR_TX_UNDERRUN; + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER) + { + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + hsdio->State = HAL_SDIO_STATE_READY; + hsdio->Context = SDIO_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS); + + return HAL_OK; +} + +/** + * @brief Allows to convert a block size in the according SDMMC value for configuring the SDMMC when doing a CMD53 + * @param hsdio: Pointer to the SDIO handle. + * @param block_size: block size in bytes + * @retval block size as DBLOCKSIZE[3:0] bits format + */ +static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size) +{ + UNUSED(hsdio); + + uint8_t most_bit = (uint8_t)__CLZ(__RBIT(block_size)); + /*(1 << most_bit) - 1) is the mask used for blocksize*/ + if (((uint8_t)block_size & ((1U << most_bit) - 1U)) != 0U) + { + return (uint8_t)SDMMC_DATABLOCK_SIZE_4B; + } + return most_bit << SDMMC_DCTRL_DBLOCKSIZE_Pos; +} + +/*! + * @brief SDIO card io pending interrupt handle function. + * @note This function is used to handle the pending io interrupt. + * To register a IO IRQ handler, Use HAL_SDIO_EnableIOInterrupt and HAL_SDIO_SetIOIRQHandler + * @param hsdio: Pointer to SDIO handle + * @retval HAL status + */ +static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio) +{ + uint8_t count; + uint8_t pendingInt; + + if (hsdio->IOInterruptNbr == 1U) + { + if ((hsdio->SDIO_IOFunction_Callback[hsdio->IOFunctionMask - 1U]) != NULL) + { + (hsdio->SDIO_IOFunction_Callback[hsdio->IOFunctionMask - 1U])(hsdio, hsdio->IOFunctionMask - 1U); + } + } + else if ((hsdio->IOInterruptNbr > 1U) && (hsdio->IOFunctionMask != 0U)) + { + /* Get pending int firstly */ + if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE1, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &pendingInt) != + HAL_OK) + { + return HAL_ERROR; + } + + if ((pendingInt != 0U) && (hsdio->IOFunctionMask != 0U)) + { + for (count = 1; count <= SDIO_MAX_IO_NUMBER; count++) + { + if (((pendingInt & (1U << count)) != 0U) && (((1U << count) & hsdio->IOFunctionMask) != 0U)) + { + if ((hsdio->SDIO_IOFunction_Callback[count - 1U]) != NULL) + { + (hsdio->SDIO_IOFunction_Callback[count - 1U])(hsdio, count); + } + } + } + } + } + else + { + /* Nothing to do */ + } + + return HAL_OK; +} +/** + * @} + */ +#endif /* HAL_SDIO_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ +/** + * @} + */ + +/** + * @} + */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sdram.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sdram.c index 8859a08cd..d376e4463 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sdram.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sdram.c @@ -1214,7 +1214,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) * the configuration information for SDRAM module. * @retval HAL state */ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram) { return hsdram->State; } @@ -1237,6 +1237,7 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) */ static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ @@ -1259,6 +1260,7 @@ static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma) */ static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ @@ -1281,6 +1283,7 @@ static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) */ static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_smartcard.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_smartcard.c index 4641fc2c9..d8742f742 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_smartcard.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_smartcard.c @@ -2408,7 +2408,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; } - MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg); + WRITE_REG(hsmartcard->Instance->RTOR, tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_smbus_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_smbus_ex.c index 354966a13..6149a5f1e 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_smbus_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_smbus_ex.c @@ -6,6 +6,8 @@ * This file provides firmware functions to manage the following * functionalities of SMBUS Extended peripheral: * + Extended features functions + * + WakeUp Mode Functions + * + FastModePlus Functions * ****************************************************************************** * @attention diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_spi.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_spi.c index 932eb3fb3..e0571e0d9 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_spi.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_spi.c @@ -2235,7 +2235,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - if (hspi->State != HAL_SPI_STATE_READY) { __HAL_UNLOCK(hspi); @@ -2418,9 +2417,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); /* Packing mode management is enabled by the DMA settings */ - if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ - ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ - (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)))) + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && \ + ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD) || \ + (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && \ + (((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ + (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ + ((hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ + (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))) { /* Restriction the DMA data received is not allowed in this mode */ /* Unlock the process */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_spi_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_spi_ex.c index 7cf5fb343..fac9ba50d 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_spi_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_spi_ex.c @@ -57,7 +57,6 @@ data transfers. (#) SPIEx function: - (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_EnableLockConfiguration() (++) HAL_SPIEx_ConfigureUnderrun() diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sram.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sram.c index 94d93ca06..b3ad7f707 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sram.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_sram.c @@ -1040,6 +1040,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) */ static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ @@ -1062,6 +1063,7 @@ static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma) */ static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ @@ -1084,6 +1086,7 @@ static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) */ static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_swpmi.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_swpmi.c index 0cf0c1c42..22fafc585 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_swpmi.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_swpmi.c @@ -131,7 +131,7 @@ and a pointer to the user callback function. [..] Use function HAL_SWPMI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_SWPMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. This function allows to reset following callbacks: @@ -144,10 +144,10 @@ (+) MspDeInitCallback : SWPMI MspDeInit. [..] By default, after the HAL_SWPMI_Init and if the state is HAL_SWPMI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak functions: examples HAL_SWPMI_RxCpltCallback(), HAL_SWPMI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SWPMI_Init + reset to the legacy weak functions in the HAL_SWPMI_Init and HAL_SWPMI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SWPMI_Init and HAL_SWPMI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -162,7 +162,7 @@ [..] When the compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim */ @@ -208,7 +208,8 @@ static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi); static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi); static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi); static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi); -static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, + uint32_t Timeout); /* Exported functions --------------------------------------------------------*/ @@ -276,7 +277,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_SWPMI_MspInit(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } hswpmi->State = HAL_SWPMI_STATE_BUSY; @@ -302,7 +303,8 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) /* Enable the SWPMI transceiver */ SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPEN); /* Wait on RDYF flag to activate SWPMI */ - if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK) + if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, + SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK) { status = HAL_TIMEOUT; } @@ -365,7 +367,7 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi) hswpmi->MspDeInitCallback(hswpmi); #else HAL_SWPMI_MspDeInit(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; hswpmi->State = HAL_SWPMI_STATE_RESET; @@ -410,7 +412,7 @@ __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi) #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) /** * @brief Register a user SWPMI callback - * to be used instead of the weak predefined callback. + * To be used to override the weak predefined callback. * @param hswpmi SWPMI handle. * @param CallbackID ID of the callback to be registered. * This parameter can be one of the following values: @@ -503,7 +505,7 @@ HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, /** * @brief Unregister a user SWPMI callback. - * SWPMI callback is redirected to the weak predefined callback. + * Callback is redirected to the weak predefined callback. * @param hswpmi SWPMI handle. * @param CallbackID ID of the callback to be unregistered. * This parameter can be one of the following values: @@ -651,12 +653,13 @@ HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpm * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; - uint32_t *ptmp_data; + const uint32_t *ptmp_data; uint32_t tmp_size; if ((pData == NULL) || (Size == 0U)) @@ -713,8 +716,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pDat } } } - } - while (tmp_size != 0U); + } while (tmp_size != 0U); /* Wait on TXBEF flag to be able to start a second transfer */ if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK) @@ -789,7 +791,8 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; /* Disable any receiver interrupts */ - CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_SRIE | SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE); + CLEAR_BIT(hswpmi->Instance->IER, + SWPMI_IT_SRIE | SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE); /* Enable SWPMI peripheral if not */ SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPACT); @@ -822,8 +825,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData } } } - } - while (tmp_size != 0U); + } while (tmp_size != 0U); if (status == HAL_OK) { @@ -868,7 +870,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; @@ -998,7 +1000,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; @@ -1044,7 +1046,8 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError; /* Enable the SWPMI transmit DMA stream */ - if (HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, + (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK) { hswpmi->State = tmp_state; /* Back to previous state */ hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA; @@ -1130,7 +1133,8 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError; /* Enable the DMA request */ - if (HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, + (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK) { hswpmi->State = tmp_state; /* Back to previous state */ hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA; @@ -1271,8 +1275,8 @@ HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi) */ /** @defgroup SWPMI_Exported_Group3 SWPMI IRQ handler and callbacks - * @brief SWPMI IRQ handler. - * + * @brief SWPMI IRQ handler. + * @verbatim ============================================================================== ##### SWPMI IRQ handler and callbacks ##### @@ -1363,7 +1367,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } else @@ -1375,7 +1379,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } else @@ -1408,7 +1412,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } else @@ -1420,7 +1424,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } } @@ -1555,19 +1559,19 @@ __weak void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi) * @param hswpmi SWPMI handle * @retval HAL state */ -HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi) +HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(const SWPMI_HandleTypeDef *hswpmi) { /* Return SWPMI handle state */ return hswpmi->State; } /** -* @brief Return the SWPMI error code. -* @param hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains + * @brief Return the SWPMI error code. + * @param hswpmi : pointer to a SWPMI_HandleTypeDef structure that contains * the configuration information for the specified SWPMI. -* @retval SWPMI Error Code -*/ -uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi) + * @retval SWPMI Error Code + */ +uint32_t HAL_SWPMI_GetError(const SWPMI_HandleTypeDef *hswpmi) { return hswpmi->ErrorCode; } @@ -1642,7 +1646,7 @@ static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi) hswpmi->TxCpltCallback(hswpmi); #else HAL_SWPMI_TxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1668,7 +1672,7 @@ static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi) hswpmi->RxCpltCallback(hswpmi); #else HAL_SWPMI_RxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } else @@ -1759,7 +1763,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } else { @@ -1778,7 +1782,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) hswpmi->TxCpltCallback(hswpmi); #else HAL_SWPMI_TxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } /* DMA Circular mode */ @@ -1788,7 +1792,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) hswpmi->TxCpltCallback(hswpmi); #else HAL_SWPMI_TxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } } @@ -1805,7 +1809,7 @@ static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) hswpmi->TxHalfCpltCallback(hswpmi); #else HAL_SWPMI_TxHalfCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } @@ -1841,7 +1845,7 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hswpmi->RxCpltCallback(hswpmi); #else HAL_SWPMI_RxCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1857,7 +1861,7 @@ static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) hswpmi->RxHalfCpltCallback(hswpmi); #else HAL_SWPMI_RxHalfCpltCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1879,7 +1883,7 @@ static void SWPMI_DMAError(DMA_HandleTypeDef *hdma) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1900,7 +1904,7 @@ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) hswpmi->ErrorCallback(hswpmi); #else HAL_SWPMI_ErrorCallback(hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } /** @@ -1911,7 +1915,8 @@ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) * @param Timeout timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hswpmi, uint32_t Flag, uint32_t Tickstart, + uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_tim.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_tim.c index 102029526..c0a36edfe 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_tim.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_tim.c @@ -6955,8 +6955,6 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - TIMx->CR1 = tmpcr1; - /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; @@ -6969,16 +6967,15 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure TIMx->RCR = Structure->RepetitionCounter; } + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } + TIMx->CR1 = tmpcr1; } /** diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_uart.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_uart.c index 3465d29cc..55f1c5835 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_uart.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_uart.c @@ -1078,6 +1078,9 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) reception services: (+) HAL_UARTEx_RxEventCallback() + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is @@ -2425,6 +2428,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3842,7 +3867,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -4513,6 +4537,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4677,6 +4702,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_uart_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_uart_ex.c index 6e5c0b20d..bb45995e9 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_uart_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_uart_ex.c @@ -576,7 +576,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_usart.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_usart.c index 85ccef27e..6c77f25fa 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_usart.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_usart.c @@ -144,7 +144,7 @@ */ /** @defgroup USART USART - * @brief HAL USART Synchronous module driver + * @brief HAL USART Synchronous SPI module driver * @{ */ @@ -225,8 +225,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit @@ -238,7 +238,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous SPI configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -316,7 +316,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) return HAL_ERROR; } - /* In Synchronous mode, the following bits must be kept cleared: + /* In Synchronous SPI mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ @@ -657,11 +657,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI data transfers. - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). [..] @@ -2910,7 +2909,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_usart_ex.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_usart_ex.c index b1a916da8..8fa72eeaa 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_usart_ex.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_usart_ex.c @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) /* Disable USART */ __HAL_USART_DISABLE(husart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_wwdg.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_wwdg.c index 4eed817e5..676b9c2eb 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_wwdg.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_wwdg.c @@ -51,17 +51,17 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values (case of STM32H74x/5x devices): (++) Counter min (T[5;0] = 0x00) @100MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 40.96us + max timeout before reset: approximately 40.96µs (++) Counter max (T[5;0] = 0x3F) @100MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 335.54ms (+) Typical values (case of STM32H7Ax/Bx devices): (++) Counter min (T[5;0] = 0x00) @140MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 29.25us + max timeout before reset: approximately 29.25µs (++) Counter max (T[5;0] = 0x3F) @140MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 239.67ms (+) Typical values (case of STM32H72x/3x devices): (++) Counter min (T[5;0] = 0x00) @125MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 32.76us + max timeout before reset: approximately 32.76µs (++) Counter max (T[5;0] = 0x3F) @125MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 268.43ms @@ -131,7 +131,6 @@ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt @endverbatim - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_adc.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_adc.c index 86ef0277a..2ecaf6ccb 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_adc.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_adc.c @@ -352,7 +352,7 @@ * - SUCCESS: ADC common registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON) { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_dma2d.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_dma2d.c index e79d45196..c1767ab03 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_dma2d.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_dma2d.c @@ -136,7 +136,7 @@ * - SUCCESS: DMA2D registers are de-initialized * - ERROR: DMA2D registers are not de-initialized */ -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx) { ErrorStatus status = SUCCESS; @@ -150,7 +150,6 @@ ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) /* Release reset of DMA2D clock */ LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_DMA2D); - } else { @@ -439,7 +438,7 @@ void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DM * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -483,7 +482,7 @@ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -527,7 +526,7 @@ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; @@ -571,7 +570,7 @@ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF */ -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) { uint32_t color; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_fmac.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_fmac.c index eab7ae8ca..fca256ff0 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_fmac.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_fmac.c @@ -113,8 +113,6 @@ ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx) return (status); } - - /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_fmc.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_fmc.c index b9fa468f1..27aadb10e 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_fmc.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_fmc.c @@ -61,7 +61,7 @@ * @{ */ #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\ - || defined(HAL_SRAM_MODULE_ENABLED) + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -188,7 +188,7 @@ * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init) + const FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; uint32_t btcr_reg; @@ -322,7 +322,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { uint32_t tmpr; @@ -338,13 +338,14 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Set FMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | - ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | - (Timing->AccessMode))); + Device->BTCR[Bank + 1U] = + (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | + (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | + (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | + (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | + ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | + ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | + Timing->AccessMode; /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) @@ -370,7 +371,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) { /* Check the parameters */ @@ -515,7 +516,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @param Init Pointer to NAND Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -548,7 +549,7 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -562,10 +563,10 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos))); + Device->PMEM = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); return HAL_OK; } @@ -579,7 +580,7 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -593,10 +594,10 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos))); + Device->PATT = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); return HAL_OK; } @@ -700,7 +701,7 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { uint32_t tickstart; @@ -739,7 +740,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui */ - /** @defgroup FMC_LL_SDRAM * @brief SDRAM Controller functions * @@ -786,7 +786,7 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui * @param Init Pointer to SDRAM Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -849,7 +849,7 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -979,7 +979,7 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u * @retval HAL state */ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) + const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_gpio.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_gpio.c index 67015f0e6..e37e28dcf 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_gpio.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_gpio.c @@ -101,7 +101,7 @@ * - SUCCESS: GPIO registers are de-initialized * - ERROR: Wrong GPIO Port */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx) { ErrorStatus status = SUCCESS; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_hrtim.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_hrtim.c index 1ee8c0a11..2abc2b1d2 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_hrtim.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_hrtim.c @@ -53,7 +53,7 @@ * - SUCCESS: HRTIMx registers are de-initialized * - ERROR: invalid HRTIMx instance */ -ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx) +ErrorStatus LL_HRTIM_DeInit(const HRTIM_TypeDef *HRTIMx) { ErrorStatus result = SUCCESS; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_rng.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_rng.c index 02981e2c4..192cc90a9 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_rng.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_rng.c @@ -112,7 +112,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content * - ERROR: not applicable */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_sdmmc.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_sdmmc.c index 38e7697ed..dd39836de 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_sdmmc.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_sdmmc.c @@ -162,7 +162,8 @@ * @{ */ -#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) +#if defined (SDMMC1) || defined (SDMMC2) +#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) || defined (HAL_SDIO_MODULE_ENABLED) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -248,7 +249,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ -uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx) { /* Read data from Rx FIFO */ return (SDMMCx->FIFO); @@ -335,7 +336,7 @@ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) * - 0x02: Power UP * - 0x03: Power ON */ -uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx) { return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL); } @@ -348,7 +349,7 @@ uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) * the configuration information for the SDMMC command * @retval HAL status */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command) { uint32_t tmpreg = 0; @@ -378,7 +379,7 @@ HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef * @param SDMMCx: Pointer to SDMMC register base * @retval Command index of the last command response received */ -uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) +uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx) { return (uint8_t)(SDMMCx->RESPCMD); } @@ -395,7 +396,7 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) * @arg SDMMC_RESP4: Response Register 4 * @retval The Corresponding response register value */ -uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) +uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response) { uint32_t tmp; @@ -416,7 +417,7 @@ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) * that contains the configuration information for the SDMMC data. * @retval HAL status */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data) +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data) { uint32_t tmpreg = 0; @@ -451,7 +452,7 @@ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef * @param SDMMCx: Pointer to SDMMC register base * @retval Number of remaining data bytes to be transferred */ -uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx) { return (SDMMCx->DCOUNT); } @@ -461,7 +462,7 @@ uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) * @param SDMMCx: Pointer to SDMMC register base * @retval Data received */ -uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx) { return (SDMMCx->FIFO); } @@ -529,6 +530,30 @@ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) return errorstate; } +/** + * @brief Send the Data Block number command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)BlockCount; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCK_COUNT; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCK_COUNT, SDMMC_CMDTIMEOUT); + + return errorstate; +} + /** * @brief Send the Read Single Block command and check the response * @param SDMMCx: Pointer to SDMMC register base @@ -1231,6 +1256,78 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) return errorstate; } +/** + * @brief Execute a cmd52 to write single byte data and read single byte data if needed + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: SDMMC command argument which is sent to a card as part of a command message + * @param pData: pointer to read response if needed + * @retval SD Card error state + */ +uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SDMMC_RW_DIRECT; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp5(SDMMCx, SDMMC_CMD_SDMMC_RW_DIRECT, pResponse); + + return errorstate; +} + +/** + * @brief Execute a cmd53 to write or read multiple data with a single command + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: SDMMC command argument which is sent to a card as part of a command message + * @retval SD Card error state + */ +uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SDMMC_RW_EXTENDED; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp5(SDMMCx, SDMMC_CMD_SDMMC_RW_EXTENDED, NULL); + + return errorstate; +} + +/** + * @brief Execute a cmd5 to write or read multiple data with a single command + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: SDMMC command argument which is sent to a card as part of a command message + * @retval SD Card error state + */ +uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SDMMC_SEN_OP_COND; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp4(SDMMCx, pResp); + + return errorstate; +} /** * @} */ @@ -1466,6 +1563,138 @@ uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_NONE; } +/** + * @brief Checks for error conditions for R4 response. + * @param SDMMCx: Pointer to SDMMC register base + * @param pResp: pointer to response + * @retval error state + */ +uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp) +{ + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else + { + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + /* We have received response, retrieve it. */ + *pResp = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R5 (cmd52/cmd53) response. + * @param SDMMCx: Pointer to SDMMC register base + * @param SDIO_CMD: The sent command index + * @param pData: pointer to the read/write buffer needed for cmd52 + * @retval SDIO Card error state + */ +uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData) +{ + uint32_t response_r5; + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + /* Check response received is of desired command */ + if (SDMMC_GetCommandResponse(SDMMCx) != SDIO_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + /* We have received response, retrieve it. */ + response_r5 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + if ((response_r5 & SDMMC_SDIO_R5_ERRORBITS) == SDMMC_ALLZERO) + { + /* we only want 8 bit read or write data and the 8 bit response flags are masked in the data pointer */ + if (pData != NULL) + { + *pData = (uint8_t)(response_r5 & 0xFFU); + } + + return SDMMC_ERROR_NONE; + } + else if ((response_r5 & SDMMC_SDIO_R5_OUT_OF_RANGE) == SDMMC_SDIO_R5_OUT_OF_RANGE) + { + return SDMMC_ERROR_ADDR_OUT_OF_RANGE; + } + else if ((response_r5 & SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER) == SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER) + { + return SDMMC_ERROR_INVALID_PARAMETER; + } + else if ((response_r5 & SDMMC_SDIO_R5_ILLEGAL_CMD) == SDMMC_SDIO_R5_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if ((response_r5 & SDMMC_SDIO_R5_COM_CRC_FAILED) == SDMMC_SDIO_R5_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + /** * @brief Checks for error conditions for R6 (RCA) response. * @param hsd: SD handle @@ -1635,6 +1864,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) */ #endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} */ diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_swpmi.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_swpmi.c index 20c2c5e1a..50d2377d2 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_swpmi.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_swpmi.c @@ -20,11 +20,11 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_ll_swpmi.h" #include "stm32h7xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ @@ -46,13 +46,13 @@ #define IS_LL_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 255U)) #define IS_LL_SWPMI_SW_BUFFER_RX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_SINGLE) \ - || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI)) + || ((__VALUE__) == LL_SWPMI_SW_BUFFER_RX_MULTI)) #define IS_LL_SWPMI_SW_BUFFER_TX(__VALUE__) (((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_SINGLE) \ - || ((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_MULTI)) + || ((__VALUE__) == LL_SWPMI_SW_BUFFER_TX_MULTI)) #define IS_LL_SWPMI_VOLTAGE_CLASS(__VALUE__) (((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_C) \ - || ((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_B)) + || ((__VALUE__) == LL_SWPMI_VOLTAGE_CLASS_B)) /** * @} @@ -76,7 +76,7 @@ * - SUCCESS: SWPMI registers are de-initialized * - ERROR: Not applicable */ -ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx) +ErrorStatus LL_SWPMI_DeInit(const SWPMI_TypeDef *SWPMIx) { ErrorStatus status = SUCCESS; @@ -108,7 +108,7 @@ ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx) * - SUCCESS: SWPMI registers are initialized * - ERROR: SWPMI registers are not initialized */ -ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct) +ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, const LL_SWPMI_InitTypeDef *SWPMI_InitStruct) { ErrorStatus status = SUCCESS; diff --git a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_usb.c b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_usb.c index ed2ca0f04..54ff752e9 100644 --- a/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_usb.c +++ b/stm32cube/stm32h7xx/drivers/src/stm32h7xx_ll_usb.c @@ -777,17 +777,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef } else { - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); + } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); - } } if (dma == 1U) @@ -1314,8 +1314,8 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * @param USBx Selected device * @retval return core mode : Host or Device * This parameter can be one of these values: - * 0 : Host - * 1 : Device + * 1 : Host + * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { diff --git a/stm32cube/stm32h7xx/soc/stm32h723xx.h b/stm32cube/stm32h7xx/soc/stm32h723xx.h index 4c8a9d0d3..b139a388a 100644 --- a/stm32cube/stm32h7xx/soc/stm32h723xx.h +++ b/stm32cube/stm32h7xx/soc/stm32h723xx.h @@ -11785,101 +11785,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -21641,7 +21738,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/stm32cube/stm32h7xx/soc/stm32h725xx.h b/stm32cube/stm32h7xx/soc/stm32h725xx.h index 56eb39388..02749c7a7 100644 --- a/stm32cube/stm32h7xx/soc/stm32h725xx.h +++ b/stm32cube/stm32h7xx/soc/stm32h725xx.h @@ -11786,101 +11786,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -21653,7 +21750,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/stm32cube/stm32h7xx/soc/stm32h730xx.h b/stm32cube/stm32h7xx/soc/stm32h730xx.h index 2b2cea29c..6bab03e37 100644 --- a/stm32cube/stm32h7xx/soc/stm32h730xx.h +++ b/stm32cube/stm32h7xx/soc/stm32h730xx.h @@ -12039,101 +12039,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -22128,7 +22225,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/stm32cube/stm32h7xx/soc/stm32h730xxq.h b/stm32cube/stm32h7xx/soc/stm32h730xxq.h index 01c6a27ff..4601a20b1 100644 --- a/stm32cube/stm32h7xx/soc/stm32h730xxq.h +++ b/stm32cube/stm32h7xx/soc/stm32h730xxq.h @@ -12040,101 +12040,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -22140,7 +22237,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/stm32cube/stm32h7xx/soc/stm32h733xx.h b/stm32cube/stm32h7xx/soc/stm32h733xx.h index 218232730..8d9f1048c 100644 --- a/stm32cube/stm32h7xx/soc/stm32h733xx.h +++ b/stm32cube/stm32h7xx/soc/stm32h733xx.h @@ -11981,7 +11981,7 @@ typedef struct #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} /** * @} diff --git a/stm32cube/stm32h7xx/soc/system_stm32h7xx.h b/stm32cube/stm32h7xx/soc/system_stm32h7xx.h index e228ef740..261074156 100644 --- a/stm32cube/stm32h7xx/soc/system_stm32h7xx.h +++ b/stm32cube/stm32h7xx/soc/system_stm32h7xx.h @@ -84,6 +84,7 @@ extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers ta extern void SystemInit(void); extern void SystemCoreClockUpdate(void); +extern void ExitRun0Mode(void); /** * @} */ diff --git a/stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_boot_cm4_cm7.c index 2d0b59ead..64af7e2a8 100644 --- a/stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_boot_cm4_cm7.c +++ b/stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_boot_cm4_cm7.c @@ -9,6 +9,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -149,7 +154,7 @@ */ uint32_t SystemCoreClock = 64000000; uint32_t SystemD2Clock = 64000000; - const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -284,7 +289,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -406,6 +411,98 @@ void SystemCoreClockUpdate (void) #endif /* CORE_CM4 */ } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} /** * @} diff --git a/stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_bootcm4_cm7gated.c b/stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_bootcm4_cm7gated.c index dc86d254a..94f202105 100644 --- a/stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_bootcm4_cm7gated.c +++ b/stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_bootcm4_cm7gated.c @@ -12,6 +12,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -152,7 +157,7 @@ */ uint32_t SystemCoreClock = 64000000; uint32_t SystemD2Clock = 64000000; - const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -276,7 +281,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -398,6 +403,99 @@ void SystemCoreClockUpdate (void) #endif /* DUAL_CORE && CORE_CM4 */ } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} + /** * @} */ diff --git a/stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_bootcm7_cm4gated.c b/stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_bootcm7_cm4gated.c index f3f340641..8cce90252 100644 --- a/stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_bootcm7_cm4gated.c +++ b/stm32cube/stm32h7xx/soc/system_stm32h7xx_dualcore_bootcm7_cm4gated.c @@ -12,6 +12,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -152,7 +157,7 @@ */ uint32_t SystemCoreClock = 64000000; uint32_t SystemD2Clock = 64000000; - const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -282,7 +287,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -404,6 +409,99 @@ void SystemCoreClockUpdate (void) #endif /* CORE_CM4 */ } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} + /** * @} */ diff --git a/stm32cube/stm32h7xx/soc/system_stm32h7xx_singlecore.c b/stm32cube/stm32h7xx/soc/system_stm32h7xx_singlecore.c index 6ab8cc2de..5e701b0c3 100644 --- a/stm32cube/stm32h7xx/soc/system_stm32h7xx_singlecore.c +++ b/stm32cube/stm32h7xx/soc/system_stm32h7xx_singlecore.c @@ -8,6 +8,11 @@ * * This file provides two functions and one global variable to be called from * user application: + * - ExitRun0Mode(): Specifies the Power Supply source. This function is + * called at startup just after reset and before the call + * of SystemInit(). This call is made inside + * the "startup_stm32h7xx.s" file. + * * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32h7xx.s" file. @@ -132,7 +137,7 @@ */ uint32_t SystemCoreClock = 64000000; uint32_t SystemD2Clock = 64000000; - const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -277,7 +282,7 @@ void SystemInit (void) } /** - * @brief Update SystemCoreClock variable according to Clock Register Values. + * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. @@ -401,6 +406,99 @@ void SystemCoreClockUpdate (void) #endif } +/** + * @brief Exit Run* mode and Configure the system Power Supply + * + * @note This function exits the Run* mode and configures the system power supply + * according to the definition to be used at compilation preprocessing level. + * The application shall set one of the following configuration option: + * - PWR_LDO_SUPPLY + * - PWR_DIRECT_SMPS_SUPPLY + * - PWR_EXTERNAL_SOURCE_SUPPLY + * - PWR_SMPS_1V8_SUPPLIES_LDO + * - PWR_SMPS_2V5_SUPPLIES_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * - PWR_SMPS_1V8_SUPPLIES_EXT + * - PWR_SMPS_2V5_SUPPLIES_EXT + * + * @note The function modifies the PWR->CR3 register to enable or disable specific + * power supply modes and waits until the voltage level flag is set, indicating + * that the power supply configuration is stable. + * + * @param None + * @retval None + */ +void ExitRun0Mode(void) +{ +#if defined(USE_PWR_LDO_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode by disabling SMPS and enabling LDO */ + PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; + #else + /* Enable LDO mode */ + PWR->CR3 |= PWR_CR3_LDOEN; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) + #if defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #else + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; + #endif /* SMPS */ + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 &= ~(PWR_CR3_LDOEN); + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) + /* Exit Run* mode */ + PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; + /* Wait till voltage level flag is set */ + while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) + {} +#else + /* No system power supply configuration is selected at exit Run* mode */ +#endif /* USE_PWR_LDO_SUPPLY */ +} + /** * @} */ diff --git a/stm32cube/stm32u0xx/CMakeLists.txt b/stm32cube/stm32u0xx/CMakeLists.txt index 70d017502..3c344f768 100644 --- a/stm32cube/stm32u0xx/CMakeLists.txt +++ b/stm32cube/stm32u0xx/CMakeLists.txt @@ -26,12 +26,10 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I2C drivers/src/stm32u0xx_hal_ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I2C_EX drivers/src/stm32u0xx_hal_i2c_ex.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_IRDA drivers/src/stm32u0xx_hal_irda.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_IWDG drivers/src/stm32u0xx_hal_iwdg.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_LCD drivers/src/stm32u0xx_hal_lcd.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_LPTIM drivers/src/stm32u0xx_hal_lptim.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_LCD drivers/src/stm32u0xx_hal_lcd.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_LPTIM drivers/src/stm32u0xx_hal_lptim.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_OPAMP drivers/src/stm32u0xx_hal_opamp.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_OPAMP_EX drivers/src/stm32u0xx_hal_opamp_ex.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_OSPI drivers/src/stm32u0xx_hal_ospi.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_OTFDEC drivers/src/stm32u0xx_hal_otfdec.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PCD drivers/src/stm32u0xx_hal_pcd.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PCD_EX drivers/src/stm32u0xx_hal_pcd_ex.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PWR drivers/src/stm32u0xx_hal_pwr.c) @@ -45,7 +43,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD_EX drivers/src/stm32 zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI drivers/src/stm32u0xx_hal_spi.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI_EX drivers/src/stm32u0xx_hal_spi_ex.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_TIM drivers/src/stm32u0xx_hal_tim.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_TIM_EX drivers/src/stm32u0xx_hal_tim_ex.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_TIM_EX drivers/src/stm32u0xx_hal_tim_ex.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_TSC drivers/src/stm32u0xx_hal_tsc.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_UART drivers/src/stm32u0xx_hal_uart.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_UART_EX drivers/src/stm32u0xx_hal_uart_ex.c) @@ -73,9 +71,3 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_TIM drivers/src/stm32u0xx_ll_ti zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_USART drivers/src/stm32u0xx_ll_usart.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_USB drivers/src/stm32u0xx_ll_usb.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_UTILS drivers/src/stm32u0xx_ll_utils.c) - - - - - - diff --git a/stm32cube/stm32u0xx/README b/stm32cube/stm32u0xx/README index f0c03190a..b2912abc0 100644 --- a/stm32cube/stm32u0xx/README +++ b/stm32cube/stm32u0xx/README @@ -6,7 +6,7 @@ Origin: https://www.st.com/en/embedded-software/stm32cubeu0.html Status: - version v1.1.0 + version v1.2.0 Purpose: ST Microelectronics official MCU package for STM32U0 series. @@ -23,7 +23,7 @@ URL: https://github.com/STMicroelectronics/STM32CubeU0 Commit: - 6452b2170313f522b4a3372054d2462b77d890d1 + 6f2310fce68e53f7277583774141bbf016df1838 Maintained-by: External @@ -40,12 +40,6 @@ Patch List: -dos2unix applied -trailing white spaces removed - *Created LL_SetFlashLatency function that return UTILS_SetFlashLatency - Impacted files: - stm32cube/stm32u0xx/drivers/src/stm32u0xx_ll_utils.c - stm32cube/stm32u0xx/drivers/include/stm32u0xx_ll_utils.h - Internal reference 187914. - *Provision to enable hal & ll asserts added -Added stm32cube/stm32u0xx/drivers/include/stm32_assert.h -Removed unused stm32cube/stm32u0xx/drivers/include/stm32_assert_template.h @@ -54,3 +48,4 @@ Patch List: Impacted files: stm32cube/stm32u0xx/drivers/include/Legacy/stm32_hal_legacy.h + See release_note.html from STM32Cube diff --git a/stm32cube/stm32u0xx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32u0xx/drivers/include/Legacy/stm32_hal_legacy.h index 9abf00a35..9a92ac366 100644 --- a/stm32cube/stm32u0xx/drivers/include/Legacy/stm32_hal_legacy.h +++ b/stm32cube/stm32u0xx/drivers/include/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) /* #define PAGESIZE FLASH_PAGE_SIZE */ +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -875,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -1012,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1264,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1279,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1466,7 +1481,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) || defined(STM32MP2) +#if defined(STM32U5) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -2014,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -3680,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3931,7 +3946,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32V7) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4225,6 +4241,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/stm32cube/stm32u0xx/drivers/include/stm32_assert_template.h b/stm32cube/stm32u0xx/drivers/include/stm32_assert_template.h new file mode 100644 index 000000000..654830053 --- /dev/null +++ b/stm32cube/stm32u0xx/drivers/include/stm32_assert_template.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file stm32_assert.h + * @author GPM Application Team + * @brief STM32 assert template file. + * This file should be copied to the application folder and renamed + * to stm32_assert.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ diff --git a/stm32cube/stm32u0xx/drivers/include/stm32u0xx_hal_pcd.h b/stm32cube/stm32u0xx/drivers/include/stm32u0xx_hal_pcd.h index b2fe0973e..e0a9c8da9 100644 --- a/stm32cube/stm32u0xx/drivers/include/stm32u0xx_hal_pcd.h +++ b/stm32cube/stm32u0xx/drivers/include/stm32u0xx_hal_pcd.h @@ -462,6 +462,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); #define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND #define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. diff --git a/stm32cube/stm32u0xx/drivers/include/stm32u0xx_hal_pcd_ex.h b/stm32cube/stm32u0xx/drivers/include/stm32u0xx_hal_pcd_ex.h index 0a36580a5..141a0838e 100644 --- a/stm32cube/stm32u0xx/drivers/include/stm32u0xx_hal_pcd_ex.h +++ b/stm32cube/stm32u0xx/drivers/include/stm32u0xx_hal_pcd_ex.h @@ -47,7 +47,6 @@ extern "C" { */ - HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); diff --git a/stm32cube/stm32u0xx/drivers/include/stm32u0xx_hal_rcc.h b/stm32cube/stm32u0xx/drivers/include/stm32u0xx_hal_rcc.h index 8a7be4893..7a76870a8 100644 --- a/stm32cube/stm32u0xx/drivers/include/stm32u0xx_hal_rcc.h +++ b/stm32cube/stm32u0xx/drivers/include/stm32u0xx_hal_rcc.h @@ -619,7 +619,7 @@ typedef struct */ /* Flags in the CR register */ #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI Ready flag */ -#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIDY_Pos)) /*!< HSI Ready flag */ +#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL Ready flag */ diff --git a/stm32cube/stm32u0xx/drivers/include/stm32u0xx_ll_usb.h b/stm32cube/stm32u0xx/drivers/include/stm32u0xx_ll_usb.h index a467f73c9..2beeb65b3 100644 --- a/stm32cube/stm32u0xx/drivers/include/stm32u0xx_ll_usb.h +++ b/stm32cube/stm32u0xx/drivers/include/stm32u0xx_ll_usb.h @@ -53,26 +53,26 @@ typedef enum */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. + uint8_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */ + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ } USB_CfgTypeDef; typedef struct @@ -526,20 +526,17 @@ typedef USB_EPTypeDef USB_DRD_EPTypeDef; \ (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ \ - if ((wCount) > 62U) \ + if ((wCount) == 0U) \ { \ - USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + (pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if ((wCount) <= 62U) \ + { \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ - if ((wCount) == 0U) \ - { \ - (pdwReg) |= USB_CNTRX_BLSIZE; \ - } \ - else \ - { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ - } \ + USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ } \ } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ diff --git a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal.c b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal.c index dc48e79e7..1b8961257 100644 --- a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal.c +++ b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal.c @@ -55,7 +55,7 @@ * @brief STM32U0xx HAL Driver version number */ #define __STM32U0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32U0xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32U0xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32U0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32U0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U0xx_HAL_VERSION ((__STM32U0xx_HAL_VERSION_MAIN << 24U)\ diff --git a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_i2c.c b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_i2c.c index 6b9c8690b..efa40a4cc 100644 --- a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_i2c.c +++ b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_i2c.c @@ -3220,6 +3220,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3277,37 +3279,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -6263,7 +6292,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6419,7 +6448,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6873,7 +6902,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -6913,7 +6942,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -6952,7 +6981,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7030,7 +7059,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7197,15 +7226,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_pcd.c b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_pcd.c index 61b42db81..0341786d8 100644 --- a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_pcd.c +++ b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_pcd.c @@ -1389,7 +1389,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1404,7 +1404,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; /* Set initial data PID. */ @@ -1809,7 +1809,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } } @@ -1930,7 +1929,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2006,7 +2005,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2038,11 +2037,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2092,6 +2091,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2103,10 +2108,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2137,7 +2144,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2165,6 +2172,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2177,10 +2190,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2210,7 +2225,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -2219,7 +2234,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; @@ -2227,13 +2242,11 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - /** * @} */ #endif /* defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_pcd_ex.c b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_pcd_ex.c index cb66616f1..42b6ac0b6 100644 --- a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_pcd_ex.c +++ b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_pcd_ex.c @@ -242,7 +242,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } } - /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -279,7 +278,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) } - /** * @brief Send LPM message to user layer callback. * @param hpcd PCD handle diff --git a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_timebase_tim_template.c b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_timebase_tim_template.c index aed8fe44b..fe6e04cc0 100644 --- a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_timebase_tim_template.c +++ b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_timebase_tim_template.c @@ -53,14 +53,14 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -extern TIM_HandleTypeDef TimHandle; -TIM_HandleTypeDef TimHandle; +static TIM_HandleTypeDef TimHandle; + /* Private function prototypes -----------------------------------------------*/ -void TIM6_DAC_LPTIM1_IRQHandler(void); +void TIM16_IRQHandler(void); /* Private functions ---------------------------------------------------------*/ /** - * @brief This function configures the TIM6 as a time base source. + * @brief This function configures the TIM16 as a time base source. * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after @@ -75,15 +75,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) uint32_t uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; + HAL_StatusTypeDef status; - /*Configure the TIM6 IRQ priority */ - HAL_NVIC_SetPriority(TIM6_DAC_LPTIM1_IRQn, TickPriority, 0U); - - /* Enable the TIM6 global Interrupt */ - HAL_NVIC_EnableIRQ(TIM6_DAC_LPTIM1_IRQn); - - /* Enable TIM6 clock */ - __HAL_RCC_TIM6_CLK_ENABLE(); + /* Enable TIM16 clock */ + __HAL_RCC_TIM16_CLK_ENABLE(); /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); @@ -91,7 +86,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; - /* Compute TIM6 clock */ + /* Compute TIM16 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) { uwTimclock = HAL_RCC_GetPCLK1Freq(); @@ -101,14 +96,14 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) uwTimclock = 2U * HAL_RCC_GetPCLK1Freq(); } - /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ + /* Compute the prescaler value to have TIM16 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t)((uwTimclock / 1000000U) - 1U); - /* Initialize TIM6 */ - TimHandle.Instance = TIM6; + /* Initialize TIM16 */ + TimHandle.Instance = TIM16; /* Initialize TIMx peripheral as follow: - + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + + Period = [(TIM16CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up @@ -117,42 +112,59 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) TimHandle.Init.Prescaler = uwPrescalerValue; TimHandle.Init.ClockDivision = 0U; TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK) + + status = HAL_TIM_Base_Init(&TimHandle); + if (status == HAL_OK) { /* Start the TIM time Base generation in interrupt mode */ - return HAL_TIM_Base_Start_IT(&TimHandle); + status = HAL_TIM_Base_Start_IT(&TimHandle); + if (status == HAL_OK) + { + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Enable the TIM16 global Interrupt */ + HAL_NVIC_SetPriority(TIM16_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } } - /* Return function status */ - return HAL_ERROR; + /* Enable the TIM16 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM16_IRQn); + + /* Return function status */ + return status; } /** * @brief Suspend Tick increment. - * @note Disable the tick increment by disabling TIM6 update interrupt. + * @note Disable the tick increment by disabling TIM16 update interrupt. * @retval None */ void HAL_SuspendTick(void) { - /* Disable TIM6 update interrupt */ + /* Disable TIM16 update interrupt */ __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE); } /** * @brief Resume Tick increment. - * @note Enable the tick increment by enabling TIM6 update interrupt. + * @note Enable the tick increment by enabling TIM16 update interrupt. * @retval None */ void HAL_ResumeTick(void) { - /* Enable TIM6 update interrupt */ + /* Enable TIM16 update interrupt */ __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE); } /** * @brief Period elapsed callback in non blocking mode - * @note This function is called when TIM6 interrupt took place, inside + * @note This function is called when TIM16 interrupt took place, inside * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment * a global variable "uwTick" used as application time base. * @param htim TIM handle @@ -165,9 +177,10 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) /** * @brief This function handles TIM interrupt request. + * @param None * @retval None */ -void TIM6_DAC_LPTIM1_IRQHandler(void) +void TIM16_IRQHandler(void) { HAL_TIM_IRQHandler(&TimHandle); } diff --git a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_uart.c b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_uart.c index f240b037e..8ee44661a 100644 --- a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_uart.c +++ b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_hal_uart.c @@ -1080,6 +1080,9 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) reception services: (+) HAL_UARTEx_RxEventCallback() + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is @@ -3880,7 +3883,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ diff --git a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_ll_usb.c b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_ll_usb.c index 1c84370e4..d23da79bb 100644 --- a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_ll_usb.c +++ b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_ll_usb.c @@ -344,6 +344,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -448,7 +452,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -550,9 +554,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -584,19 +588,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -605,15 +615,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -624,18 +632,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -679,26 +677,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } diff --git a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_ll_utils.c b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_ll_utils.c index 80b07fe49..3743cb55a 100644 --- a/stm32cube/stm32u0xx/drivers/src/stm32u0xx_ll_utils.c +++ b/stm32cube/stm32u0xx/drivers/src/stm32u0xx_ll_utils.c @@ -560,7 +560,7 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) { - return UTILS_SetFlashLatency(HCLK_Frequency); + return UTILS_SetFlashLatency(HCLK_Frequency); } /** diff --git a/stm32cube/stm32u0xx/soc/stm32u031xx.h b/stm32cube/stm32u0xx/soc/stm32u031xx.h index 342d2d408..30773e122 100644 --- a/stm32cube/stm32u0xx/soc/stm32u031xx.h +++ b/stm32cube/stm32u0xx/soc/stm32u031xx.h @@ -706,6 +706,10 @@ typedef struct #define UID_BASE (0x1FFF3E50UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF3EA0UL) /*!< Flash size data register base address */ +/*!< Bootloader Firmware */ +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF3500UL) + /** * @} */ diff --git a/stm32cube/stm32u0xx/soc/stm32u073xx.h b/stm32cube/stm32u0xx/soc/stm32u073xx.h index a4632c70a..2c22fb97a 100644 --- a/stm32cube/stm32u0xx/soc/stm32u073xx.h +++ b/stm32cube/stm32u0xx/soc/stm32u073xx.h @@ -775,6 +775,10 @@ typedef struct #define UID_BASE (0x1FFF6E50UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF6EA0UL) /*!< Flash size data register base address */ +/*!< Bootloader Firmware */ +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF6000UL) + /** * @} */ diff --git a/stm32cube/stm32u0xx/soc/stm32u083xx.h b/stm32cube/stm32u0xx/soc/stm32u083xx.h index 590776847..13995be2b 100644 --- a/stm32cube/stm32u0xx/soc/stm32u083xx.h +++ b/stm32cube/stm32u0xx/soc/stm32u083xx.h @@ -809,6 +809,10 @@ typedef struct #define UID_BASE (0x1FFF6E50UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF6EA0UL) /*!< Flash size data register base address */ +/*!< Bootloader Firmware */ +/************ Bootloader Exit Secure Memory Firmware *************/ +#define BL_EXIT_SEC_MEM_BASE (0x1FFF6000UL) + /** * @} */ diff --git a/stm32cube/stm32u0xx/soc/stm32u0xx.h b/stm32cube/stm32u0xx/soc/stm32u0xx.h index dc0718ba2..b896a2fa9 100644 --- a/stm32cube/stm32u0xx/soc/stm32u0xx.h +++ b/stm32cube/stm32u0xx/soc/stm32u0xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32U0xx device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * @@ -76,10 +76,10 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number 1.0.0 + * @brief CMSIS Device version number 1.2.0 */ #define __STM32U0_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32U0_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32U0_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32U0_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32U0_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32U0_CMSIS_VERSION ((__STM32U0_CMSIS_VERSION_MAIN << 24)\ @@ -127,8 +127,8 @@ typedef enum typedef enum { - ERROR = 0, - SUCCESS = !ERROR + SUCCESS = 0, + ERROR = !SUCCESS } ErrorStatus; /** diff --git a/stm32cube/stm32u0xx/soc/system_stm32u0xx.c b/stm32cube/stm32u0xx/soc/system_stm32u0xx.c index 6c221244d..0222b0f5a 100644 --- a/stm32cube/stm32u0xx/soc/system_stm32u0xx.c +++ b/stm32cube/stm32u0xx/soc/system_stm32u0xx.c @@ -327,7 +327,7 @@ void SystemCoreClockUpdate(void) } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U) & 0xFU]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } diff --git a/stm32cube/stm32u5xx/README b/stm32cube/stm32u5xx/README index 9a8dd5dd5..af025ab2a 100644 --- a/stm32cube/stm32u5xx/README +++ b/stm32cube/stm32u5xx/README @@ -6,7 +6,7 @@ Origin: http://www.st.com/en/embedded-software/stm32cubeu5.html Status: - version v1.6.0 + version v1.7.0 Purpose: ST Microelectronics official MCU package for STM32U5 series. @@ -23,7 +23,7 @@ URL: https://github.com/STMicroelectronics/STM32CubeU5 Commit: - 6591004477fdd8fba04573c0373679f2be0da595 + 7392378474639cdcd87a71918f5272f847454055 Maintained-by: External diff --git a/stm32cube/stm32u5xx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32u5xx/drivers/include/Legacy/stm32_hal_legacy.h index 2013593cd..07a7c67ae 100644 --- a/stm32cube/stm32u5xx/drivers/include/Legacy/stm32_hal_legacy.h +++ b/stm32cube/stm32u5xx/drivers/include/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) /* #define PAGESIZE FLASH_PAGE_SIZE */ +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -806,6 +817,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -860,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -997,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1249,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1264,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1817,7 +1847,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1999,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -2731,6 +2761,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3659,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3910,7 +3946,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4204,6 +4241,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32_assert_template.h b/stm32cube/stm32u5xx/drivers/include/stm32_assert_template.h new file mode 100644 index 000000000..fe5e44415 --- /dev/null +++ b/stm32cube/stm32u5xx/drivers/include/stm32_assert_template.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file stm32_assert.h + * @author MCD Application Team + * @brief STM32 assert template file. + * This file should be copied to the application folder and renamed + * to stm32_assert.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal.h index 08fef12a8..a779890d0 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal.h @@ -143,10 +143,22 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ +/** + * @} + */ +#if defined(SYSCFG_CFGR1_ENDCAP) +/** @defgroup SYSCFG_DECOUPLING_CAPACITANCE SYSCFG DECOUPLING CAPACITANCE + * @{ + */ +#define SYSCFG_HSPI_CAPACITANCE_OFF 0x00000000U /*!< Decoupling with no capacitance value on HSPI supply */ +#define SYSCFG_HSPI_CAPACITANCE_1_DIV_3 SYSCFG_CFGR1_ENDCAP_0 /*!< Decoupling with 1/3 of capacitance value on HSPI supply */ +#define SYSCFG_HSPI_CAPACITANCE_2_DIV_3 SYSCFG_CFGR1_ENDCAP_1 /*!< Decoupling with 2/3 of capacitance value on HSPI supply */ +#define SYSCFG_HSPI_CAPACITANCE_FULL SYSCFG_CFGR1_ENDCAP /*!< Decoupling with full capacitance value on HSPI supply */ /** * @} */ +#endif /* SYSCFG_CFGR1_ENDCAP */ /** @defgroup SYSCFG_Lock_items SYSCFG Lock items * @brief SYSCFG items to set lock on @@ -620,8 +632,14 @@ extern HAL_TickFreqTypeDef uwTickFreq; (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined(SYSCFG_CFGR1_ENDCAP) +#define IS_SYSCFG_DECOUPLING_CAPACITANCE(__CAPA__) (((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_OFF) || \ + ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_1_DIV_3) || \ + ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_2_DIV_3) || \ + ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_FULL)) +#endif /* SYSCFG_CFGR1_ENDCAP */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ ((__ATTRIBUTES__) == SYSCFG_NSEC)) @@ -642,11 +660,9 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) - - #endif /* __ARM_FEATURE_CMSE */ -#ifdef SYSCFG_OTGHSPHYCR_EN +#if defined SYSCFG_OTGHSPHYCR_EN #define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ @@ -750,8 +766,6 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); */ /* SYSCFG Control functions ****************************************************/ -void HAL_SYSCFG_SRAM2Erase(void); - void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); @@ -765,10 +779,14 @@ void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); #endif /* SYSCFG_OTGHSPHYCR_EN */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); -void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void); -void HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection(void); +void HAL_SYSCFG_EnableIOAnalogBooster(void); +void HAL_SYSCFG_DisableIOAnalogBooster(void); +void HAL_SYSCFG_EnableIOAnalogVoltageSelection(void); +void HAL_SYSCFG_DisableIOAnalogVoltageSelection(void); +#if defined(SYSCFG_CFGR1_ENDCAP) +void HAL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance); +uint32_t HAL_SYSCFG_GetHSPIDecouplingCapacitance(void); +#endif /* SYSCFG_CFGR1_ENDCAP */ void HAL_SYSCFG_EnableSRAMCached(void); void HAL_SYSCFG_DisableSRAMCached(void); void HAL_SYSCFG_EnableVddCompensationCell(void); diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_comp.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_comp.h index 7220ae173..423a1c1f1 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_comp.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_comp.h @@ -753,11 +753,11 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /* Exported functions --------------------------------------------------------*/ -/** @addtogroup COMP_Exported_Functions COMP Exported Functions +/** @addtogroup COMP_Exported_Functions * @{ */ -/** @addtogroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions +/** @addtogroup COMP_Exported_Functions_Group1 * @{ */ @@ -778,7 +778,7 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM */ /* IO operation functions *****************************************************/ -/** @addtogroup COMP_Exported_Functions_Group2 Start-Stop operation functions +/** @addtogroup COMP_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); @@ -789,7 +789,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); */ /* Peripheral Control functions ************************************************/ -/** @addtogroup COMP_Exported_Functions_Group3 Peripheral Control functions +/** @addtogroup COMP_Exported_Functions_Group3 * @{ */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); @@ -801,7 +801,7 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); */ /* Peripheral State functions **************************************************/ -/** @addtogroup COMP_Exported_Functions_Group4 Peripheral State functions +/** @addtogroup COMP_Exported_Functions_Group4 * @{ */ HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_cordic.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_cordic.h index f48923864..315b3b439 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_cordic.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_cordic.h @@ -149,7 +149,6 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants * @{ @@ -166,6 +165,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + /** * @} */ @@ -183,6 +183,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */ #define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ #define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ + /** * @} */ @@ -212,6 +213,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ |CORDIC_CSR_PRECISION_0)) + /** * @} */ @@ -229,6 +231,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0)) #define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1)) #define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) + /** * @} */ @@ -237,6 +240,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */ + /** * @} */ @@ -245,6 +249,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */ + /** * @} */ @@ -253,6 +258,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */ + /** * @} */ @@ -288,6 +294,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */ #define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */ + /** * @} */ @@ -297,6 +304,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */ #define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */ + /** * @} */ @@ -305,6 +313,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */ + /** * @} */ @@ -316,6 +325,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */ #define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */ #define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */ + /** * @} */ @@ -336,9 +346,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET) @@ -416,7 +426,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ -/* Private macros --------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /** @defgroup CORDIC_Private_Macros CORDIC Private Macros * @{ */ @@ -584,6 +594,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); /* Peripheral State functions *************************************************/ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); + /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_cortex.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_cortex.h index 77b64a5e2..3c5bd145d 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_cortex.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_cortex.h @@ -123,10 +123,10 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE 0U -#define MPU_HARDFAULT_NMI 2U -#define MPU_PRIVILEGED_DEFAULT 4U -#define MPU_HFNMI_PRIVDEF 6U +#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -134,8 +134,8 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ -#define MPU_REGION_ENABLE 1U -#define MPU_REGION_DISABLE 0U +#define MPU_REGION_ENABLE 1U /*!< Enable region */ +#define MPU_REGION_DISABLE 0U /*!< Disable region */ /** * @} */ @@ -143,8 +143,8 @@ typedef struct /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ -#define MPU_INSTRUCTION_ACCESS_ENABLE 0U -#define MPU_INSTRUCTION_ACCESS_DISABLE 1U +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */ +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */ /** * @} */ @@ -152,9 +152,9 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ -#define MPU_ACCESS_NOT_SHAREABLE 0U -#define MPU_ACCESS_OUTER_SHAREABLE 2U -#define MPU_ACCESS_INNER_SHAREABLE 3U +#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */ +#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */ +#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */ /** * @} */ @@ -162,10 +162,10 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_PRIV_RW 0U -#define MPU_REGION_ALL_RW 1U -#define MPU_REGION_PRIV_RO 2U -#define MPU_REGION_ALL_RO 3U +#define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */ +#define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */ +#define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */ +#define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */ /** * @} */ @@ -203,22 +203,30 @@ typedef struct /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes * @{ */ -#define MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ - -#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ -#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - -#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ -#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - -#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ -#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ -#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ -#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/* Device memory attributes */ +#define MPU_DEVICE_NGNRNE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define MPU_DEVICE_NGNRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define MPU_DEVICE_NGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* To set with INNER_OUTER() macro for both inner/outer cache attributes */ + +/* Non-cacheable memory attribute */ +#define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ +#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ +/* - transient mode attribute */ +#define MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ +#define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ +/* - allocation attribute */ +#define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ +#define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ +#define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ +#define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ /** * @} diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_cryp.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_cryp.h index a7c0a5589..015418e3a 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_cryp.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_cryp.h @@ -484,25 +484,25 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @arg @ref CRYP_FLAG_KEIF Key error flag * @arg @ref CRYP_FLAG_RWEIF Read/write Error flag - * @retval The state of __FLAG__ (TRUE or FALSE). + * @retval The state of __FLAG__ (FlagStatus). */ #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (\ - ((__FLAG__) == CRYP_FLAG_KEYVALID )?(((__HANDLE__)->Instance->SR \ - & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \ - ((__FLAG__) == CRYP_FLAG_BUSY )?(((__HANDLE__)->Instance->SR \ - & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \ - ((__FLAG__) == CRYP_FLAG_WRERR )?(((__HANDLE__)->Instance->SR \ + ((__FLAG__) == CRYP_FLAG_KEYVALID )?((((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_BUSY )?((((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_WRERR )?((((__HANDLE__)->Instance->SR \ & (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \ - (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \ - ((__FLAG__) == CRYP_FLAG_RDERR )?(((__HANDLE__)->Instance->SR \ + (CRYP_FLAG_WRERR & 0x7FFFFFFFU))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_RDERR )?((((__HANDLE__)->Instance->SR \ & (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \ - (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \ - ((__FLAG__) == CRYP_FLAG_KEIF )?(((__HANDLE__)->Instance->ISR \ - & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \ - ((__FLAG__) == CRYP_FLAG_RWEIF )?(((__HANDLE__)->Instance->ISR \ - & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \ - (((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF))) + (CRYP_FLAG_RDERR & 0x7FFFFFFFU))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_KEIF )?((((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_RWEIF )?((((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF))?SET:RESET) : \ + ((((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))?SET:RESET) /** @brief Clear the CRYP pending status flag. * @param __HANDLE__ specifies the CRYP handle. diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dac.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dac.h index cb23c4d9c..bdd6bb9f7 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dac.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dac.h @@ -291,10 +291,13 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) -#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) -#define DAC_CHIPCONNECT_BOTH (1UL << 2) - +#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/ +#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. */ +#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. + Note: this connection is not available in mode normal + with buffer disabled. */ /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dcmi.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dcmi.h index e3c9cbd57..7c565b2f5 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dcmi.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dcmi.h @@ -574,7 +574,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0 uint32_t YSize); HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi); -HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask); +HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask); /** * @} diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_def.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_def.h index 043f0df60..5fac6913c 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_def.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_def.h @@ -174,7 +174,7 @@ typedef enum /** * @brief __RAM_FUNC definition */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* ARM Compiler ------------ @@ -207,7 +207,7 @@ typedef enum /** * @brief __NOINLINE definition */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) /* ARM & GNUCompiler ---------------- */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dma.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dma.h index 72153b44e..a15d4fe8c 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dma.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dma.h @@ -561,7 +561,6 @@ typedef struct __DMA_HandleTypeDef */ - /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dsi.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dsi.h index 29a8e549e..cbb6e35ff 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dsi.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dsi.h @@ -1246,7 +1246,7 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t NbParams, uint32_t Param1, - uint8_t *ParametersTable); + const uint8_t *ParametersTable); HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, uint32_t ChannelNbr, uint8_t *Array, @@ -1274,8 +1274,8 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane * @brief Peripheral State and Errors functions * @{ */ -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); -HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); +uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi); +HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi); /** * @} diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_fdcan.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_fdcan.h index 9a8741bbb..0ddede43a 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_fdcan.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_fdcan.h @@ -517,8 +517,8 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ -#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ -#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Put element in full FIFO */ #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_fmac.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_fmac.h index da7ed7596..3641a3e16 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_fmac.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_fmac.h @@ -243,10 +243,7 @@ typedef struct * @} */ - /* Exported constants --------------------------------------------------------*/ - - /** @defgroup FMAC_Exported_Constants FMAC Exported Constants * @{ */ @@ -357,7 +354,6 @@ typedef struct * @} */ - /* Exported variables --------------------------------------------------------*/ /** @defgroup FMAC_Exported_variables FMAC Exported variables * @{ @@ -499,7 +495,7 @@ typedef struct * @} */ -/* Private Macros-----------------------------------------------------------*/ +/* Private Macros-------------------------------------------------------------*/ /** @addtogroup FMAC_Private_Macros FMAC Private Macros * @{ */ @@ -578,9 +574,9 @@ typedef struct * @param __FUNCTION__ ID of the filter function. * @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid) */ -#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ - (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ - (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) ) +#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ + (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX)))) /** * @brief Verify the FMAC filter parameter R. diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_gfxmmu.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_gfxmmu.h index b06c3dcea..0e7de3faf 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_gfxmmu.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_gfxmmu.h @@ -379,28 +379,28 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @{ */ /* Operation functions ********************************************************/ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address); -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber); -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_LutLineTypeDef *lutLine); #if defined(GFXMMU_CR_CE) HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam); HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu, - GFXMMU_CachePrefetchTypeDef *CachePrefetch); + const GFXMMU_CachePrefetchTypeDef *CachePrefetch); #endif /* GFXMMU_CR_CE */ -HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers); +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_BuffersTypeDef *Buffers); #if defined(GFXMMU_CR_ACE) HAL_StatusTypeDef HAL_GFXMMU_ModifyAddressCache(GFXMMU_HandleTypeDef *hgfxmmu, - GFXMMU_AddressCacheTypeDef *AddressCache); + const GFXMMU_AddressCacheTypeDef *AddressCache); #endif /* GFXMMU_CR_ACE */ void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu); @@ -414,7 +414,7 @@ void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu); * @{ */ /* State function *************************************************************/ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu); +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu); uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); /** diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_hash.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_hash.h index 2f02a3f67..72dc62917 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_hash.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_hash.h @@ -117,13 +117,13 @@ typedef struct { HASH_InitTypeDef Init; /*!< HASH required parameters */ - uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ + uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ + uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ uint32_t HashBuffSize; /*!< Size of buffer to be processed */ @@ -476,15 +476,15 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS /* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); @@ -497,15 +497,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** @@ -517,9 +517,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); */ /* HASH processing using DMA *************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -531,9 +531,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu */ /* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -544,9 +544,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @{ */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -558,8 +558,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ /* HASH-HMAC processing using DMA ********************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -594,19 +594,19 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); */ /* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); /** * @} diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_hash_ex.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_hash_ex.h index 3e26a61c4..adda0f89e 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_hash_ex.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_hash_ex.h @@ -50,15 +50,15 @@ extern "C" { * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -69,15 +69,15 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -87,9 +87,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin /** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -99,9 +99,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -111,9 +111,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -124,8 +124,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -135,20 +135,20 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_lptim.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_lptim.h index 0a6423dde..06358af1a 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_lptim.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_lptim.h @@ -220,6 +220,7 @@ typedef struct __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ __IO HAL_LPTIM_ChannelStateTypeDef ChannelState[2]; /*!< LPTIM channel operation state */ + #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */ void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */ @@ -616,6 +617,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Write the passed parameter in the Autoreload register. * @param __HANDLE__ LPTIM handle * @param __VALUE__ Autoreload value + * This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF. * @retval None * @note The ARR register can only be modified when the LPTIM instance is enabled. */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_mmc.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_mmc.h index 892676b7a..385cfc33b 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_mmc.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_mmc.h @@ -717,9 +717,9 @@ HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_Parti * @{ */ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); /** * @} diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_mmc_ex.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_mmc_ex.h index 9aca5ee18..3289331d1 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_mmc_ex.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_mmc_ex.h @@ -69,9 +69,11 @@ extern "C" { /** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions * @{ */ -HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, SDMMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, + const MMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, SDMMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, + const MMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks); HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_BuildNode(MMC_DMALinkNodeTypeDef *pNode, diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_pcd.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_pcd.h index 62741b5ec..a7958a58f 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_pcd.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_pcd.h @@ -508,6 +508,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); #define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND #define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_pcd_ex.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_pcd_ex.h index ab2bb878e..60e75c07f 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_pcd_ex.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_pcd_ex.h @@ -45,7 +45,6 @@ extern "C" { /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_rng.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_rng.h index c6610c709..d0847d18d 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_rng.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_rng.h @@ -178,6 +178,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_rng_ex.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_rng_ex.h index a01303c1b..807d02f26 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_rng_ex.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,11 +55,11 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs - value of @ref RNG_Ex_Auto_Reset */ + value of @ref RNGEx_Auto_Reset */ uint32_t HealthTest; /*!< RNG health test control must be a value between 0x0FFCABFF and 0x00005200 */ uint32_t NoiseSource; /*!< RNG noise source control(Oscillator Enable signals) @@ -71,11 +71,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -114,7 +114,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -123,7 +123,7 @@ typedef struct /** * @} */ -/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration +/** @defgroup RNGEx_Auto_Reset Auto Reset configuration * @{ */ #define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/ @@ -138,7 +138,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -147,7 +147,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -156,7 +156,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -165,7 +165,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -204,7 +204,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -213,11 +213,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -228,7 +228,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_rtc.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_rtc.h index 69cb662c8..b81e33e4d 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_rtc.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_rtc.h @@ -742,6 +742,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to */ #define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS)) +/** + * @brief Get RTC Binary mode. + * @param __HANDLE__ specifies the RTC handle. + * @retval The selected RTC Binary mode (RTC_BINARY_NONE, RTC_BINARY_ONLY, or RTC_BINARY_MIX). + */ +#define __HAL_RTC_GET_BINARY_MODE(__HANDLE__) (READ_REG(RTC->ICSR & RTC_ICSR_BIN)) + /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_sd.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_sd.h index 952df6876..bae7bc277 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_sd.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_sd.h @@ -687,10 +687,10 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t * @{ */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_sd_ex.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_sd_ex.h index 18e89ad8e..cc2de072f 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_sd_ex.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_sd_ex.h @@ -69,9 +69,9 @@ extern "C" { /** @defgroup SDEx_Exported_Functions_Group1 Linked List functions * @{ */ -HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SD_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, const SD_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SD_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, const SD_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks); HAL_StatusTypeDef HAL_SDEx_DMALinkedList_BuildNode(SD_DMALinkNodeTypeDef *pNode, SD_DMALinkNodeConfTypeDef *pNodeConf); diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_sdio.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_sdio.h index 0368251ab..f51f6806b 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_sdio.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_sdio.h @@ -6,7 +6,7 @@ ********************************************************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -154,12 +154,13 @@ typedef struct __SDIO_HandleTypeDef void (* ErrorCallback)(struct __SDIO_HandleTypeDef *hsdio); void (* MspInitCallback)(struct __SDIO_HandleTypeDef *hsdio); void (* MspDeInitCallback)(struct __SDIO_HandleTypeDef *hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ #if (USE_SDIO_TRANSCEIVER != 0U) void (* DriveTransceiver_1_8V_Callback)(struct __SDIO_HandleTypeDef *hsdio, FlagStatus status); #endif /* USE_SDIO_TRANSCEIVER */ -#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + HAL_StatusTypeDef(* SDIO_IdentifyCard)(struct __SDIO_HandleTypeDef *hsdio); } SDIO_HandleTypeDef; @@ -186,14 +187,16 @@ typedef enum * @{ */ typedef void (*pSDIO_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio); -#if (USE_SDIO_TRANSCEIVER != 0U) -typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status); -#endif /* USE_SDIO_TRANSCEIVER */ /** * @} */ #endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ +#if (USE_SDIO_TRANSCEIVER != 0U) +typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + +typedef HAL_StatusTypeDef(*pSDIO_IdentifyCardCallbackTypeDef)(SDIO_HandleTypeDef *hsdio); typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, uint32_t func); /** * @} @@ -213,9 +216,7 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u #define HAL_SDIO_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ #define HAL_SDIO_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ #define HAL_SDIO_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ -#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) #define HAL_SDIO_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ -#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ /** * @} */ @@ -289,7 +290,7 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @} */ -/** @defgroup SDIO_Exported_Constansts_Group8 SDIO Data block size enumeration +/** @defgroup SDIO_Exported_Constansts_Group8 SDIO Bus Width enumeration * @{ */ #define HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED 0U /*!< SDIO bus width 8 bit is not supported */ @@ -470,16 +471,19 @@ HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ pSDIO_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ #if (USE_SDIO_TRANSCEIVER != 0U) HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio, pSDIO_TransceiverCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio); #endif /* USE_SDIO_TRANSCEIVER */ -#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, - HAL_SDIO_IOFunction_CallbackTypeDef Callback); + HAL_SDIO_IOFunction_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback); /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_spi.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_spi.h index bbc186528..24fa33d53 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_spi.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_spi.h @@ -1083,6 +1083,9 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ ((LENGTH) == SPI_CRC_LENGTH_4BIT)) + +#define IS_SPI_LIMITED_TRANSFER_SIZE(SIZE) (((SIZE) < 0x3FFU) && ((SIZE) != 0U)) + /** * @brief CRC Length for limited instance */ @@ -1092,6 +1095,8 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) +#define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL) + #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ @@ -1105,6 +1110,8 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); #define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) + +#define IS_SPI_TRANSFER_SIZE(SIZE) (((SIZE) < 0xFFFFU) && ((SIZE) != 0U)) /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_tim.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_tim.h index e5919c183..bbe19eb39 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_tim.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_tim.h @@ -416,29 +416,28 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -1964,9 +1963,11 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ - (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ - ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + ((READ_BIT((__HANDLE__)->Instance->CR1, TIM_CR1_DITHEN) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x000FFFEFU))) : \ + ((__PERIOD__) > 0U )) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -2025,7 +2026,6 @@ mode. #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_uart.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_uart.h index 1460ba821..240c76c5a 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_uart.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_uart.h @@ -292,7 +292,6 @@ typedef enum HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ - HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ @@ -1217,7 +1216,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1232,8 +1231,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_uart_ex.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_uart_ex.h index fd29060dd..062bc86ba 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_uart_ex.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_uart_ex.h @@ -239,8 +239,6 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @{ */ -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); - void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_usart.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_usart.h index 36b95bbe4..d08fef203 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_usart.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_usart.h @@ -142,7 +142,7 @@ typedef struct __USART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value of @ref USARTEx_Slave_Mode */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value @@ -708,8 +708,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_usart_ex.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_usart_ex.h index 9a80671cb..55deb3151 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_usart_ex.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_usart_ex.h @@ -72,7 +72,7 @@ typedef struct * @{ */ #define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_xspi.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_xspi.h index 8014fe488..0e3e1edf2 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_xspi.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_xspi.h @@ -393,38 +393,38 @@ typedef struct /** @defgroup XSPI_MemorySize XSPI Memory Size * @{ */ -#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Byte = 2^( 0+1)) */ -#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Byte = 2^( 1+1)) */ -#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Byte = 2^( 2+1)) */ -#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Byte = 2^( 3+1)) */ -#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Byte = 2^( 4+1)) */ -#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Byte = 2^( 5+1)) */ -#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Byte = 2^( 6+1)) */ -#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Byte = 2^( 7+1)) */ -#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Byte = 2^( 8+1)) */ -#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KByte = 2^( 9+1)) */ -#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KByte = 2^(10+1)) */ -#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KByte = 2^(11+1)) */ -#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KByte = 2^(12+1)) */ -#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KByte = 2^(13+1)) */ -#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KByte = 2^(14+1)) */ -#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KByte = 2^(15+1)) */ -#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KByte = 2^(16+1)) */ -#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KByte = 2^(17+1)) */ -#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KByte = 2^(18+1)) */ -#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MByte = 2^(19+1)) */ -#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MByte = 2^(20+1)) */ -#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MByte = 2^(21+1)) */ -#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MByte = 2^(22+1)) */ -#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MByte = 2^(23+1)) */ -#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MByte = 2^(24+1)) */ -#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MByte = 2^(25+1)) */ -#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MByte = 2^(26+1)) */ -#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MByte = 2^(27+1)) */ -#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (256 MByte = 2^(28+1)) */ -#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits (256 MByte = 2^(29+1)) */ -#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits (256 MByte = 2^(30+1)) */ -#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits (256 MByte = 2^(31+1)) */ +#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Bytes = 2^( 0+1)) */ +#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Bytes = 2^( 1+1)) */ +#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Bytes = 2^( 2+1)) */ +#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Bytes = 2^( 3+1)) */ +#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Bytes = 2^( 4+1)) */ +#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Bytes = 2^( 5+1)) */ +#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Bytes = 2^( 6+1)) */ +#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Bytes = 2^( 7+1)) */ +#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Bytes = 2^( 8+1)) */ +#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KBytes = 2^( 9+1)) */ +#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KBytes = 2^(10+1)) */ +#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KBytes = 2^(11+1)) */ +#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KBytes = 2^(12+1)) */ +#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KBytes = 2^(13+1)) */ +#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KBytes = 2^(14+1)) */ +#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KBytes = 2^(15+1)) */ +#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KBytes = 2^(16+1)) */ +#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KBytes = 2^(17+1)) */ +#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KBytes = 2^(18+1)) */ +#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MBytes = 2^(19+1)) */ +#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MBytes = 2^(20+1)) */ +#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MBytes = 2^(21+1)) */ +#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MBytes = 2^(22+1)) */ +#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MBytes = 2^(23+1)) */ +#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MBytes = 2^(24+1)) */ +#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MBytes = 2^(25+1)) */ +#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MBytes = 2^(26+1)) */ +#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MBytes = 2^(27+1)) */ +#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (512 MBytes = 2^(28+1)) */ +#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits ( 1 GBytes = 2^(29+1)) */ +#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits ( 2 GBytes = 2^(30+1)) */ +#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits ( 4 GBytes = 2^(31+1)) */ /** * @} */ @@ -480,38 +480,38 @@ typedef struct /** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary * @{ */ -#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ -#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Byte = 2^(1)) */ -#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Byte = 2^(2)) */ -#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Byte = 2^(3)) */ -#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Byte = 2^(4)) */ -#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Byte = 2^(5)) */ -#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Byte = 2^(6)) */ -#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Byte = 2^(7)) */ -#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Byte = 2^(8)) */ -#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Byte = 2^(9)) */ -#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KByte = 2^(10)) */ -#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KByte = 2^(11)) */ -#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KByte = 2^(12)) */ -#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KByte = 2^(13)) */ -#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KByte = 2^(14)) */ -#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KByte = 2^(15)) */ -#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KByte = 2^(16)) */ -#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KByte = 2^(17)) */ -#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KByte = 2^(18)) */ -#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KByte = 2^(19)) */ -#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MByte = 2^(20)) */ -#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MByte = 2^(21)) */ -#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MByte = 2^(22)) */ -#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MByte = 2^(23)) */ -#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MByte = 2^(24)) */ -#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MByte = 2^(25)) */ -#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MByte = 2^(26)) */ -#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MByte = 2^(27)) */ -#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MByte = 2^(28)) */ -#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MByte = 2^(29)) */ -#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GByte = 2^(30)) */ -#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GByte = 2^(31)) */ +#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ +#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Bytes = 2^(1)) */ +#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Bytes = 2^(2)) */ +#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Bytes = 2^(3)) */ +#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Bytes = 2^(4)) */ +#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Bytes = 2^(5)) */ +#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Bytes = 2^(6)) */ +#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Bytes = 2^(7)) */ +#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Bytes = 2^(8)) */ +#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Bytes = 2^(9)) */ +#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KBytes = 2^(10)) */ +#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KBytes = 2^(11)) */ +#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KBytes = 2^(12)) */ +#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KBytes = 2^(13)) */ +#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KBytes = 2^(14)) */ +#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KBytes = 2^(15)) */ +#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KBytes = 2^(16)) */ +#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KBytes = 2^(17)) */ +#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KBytes = 2^(18)) */ +#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KBytes = 2^(19)) */ +#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MBytes = 2^(20)) */ +#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MBytes = 2^(21)) */ +#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MBytes = 2^(22)) */ +#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MBytes = 2^(23)) */ +#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MBytes = 2^(24)) */ +#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MBytes = 2^(25)) */ +#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MBytes = 2^(26)) */ +#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MBytes = 2^(27)) */ +#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MBytes = 2^(28)) */ +#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MBytes = 2^(29)) */ +#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GBytes = 2^(30)) */ +#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GBytes = 2^(31)) */ /** * @} */ @@ -781,7 +781,6 @@ typedef struct */ #if defined(OCTOSPIM) - /** @defgroup XSPI_IO_Manger_IOPort XSPI IO Port * @{ */ @@ -971,11 +970,11 @@ HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_Hyper uint32_t Timeout); /* XSPI indirect mode functions */ -HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout); HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); -HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); /* XSPI status flag polling mode functions */ @@ -1191,7 +1190,6 @@ HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSC #define IS_XSPI_DLYB_BYPASS(DLYB) (((DLYB) == HAL_XSPI_DELAY_BLOCK_ON) || \ ((DLYB) == HAL_XSPI_DELAY_BLOCK_BYPASS)) - #define IS_XSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) #define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_adc.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_adc.h index a6970bfd1..9d72f9aed 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_adc.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_adc.h @@ -3723,7 +3723,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32 { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); + /* Note: Value shift +1 for correspondence with channel definition using ADC_CHANNEL_ID_NUMBER_MASK */ + uint32_t ch_decimal = (READ_BIT(*preg, ADC_OFR1_OFFSET1_CH) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS + 1UL)); + return (uint32_t)__LL_ADC_DECIMAL_NB_TO_CHANNEL(ch_decimal); } /** @@ -4779,42 +4781,8 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_REG_RANK_15 * @arg @ref LL_ADC_REG_RANK_16 * Note: Specific case for ADC4, use literals LL_ADC_REG_RANK_x_ADC4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 (3) - * @arg @ref LL_ADC_CHANNEL_1 (3) - * @arg @ref LL_ADC_CHANNEL_2 (3) - * @arg @ref LL_ADC_CHANNEL_3 (3) - * @arg @ref LL_ADC_CHANNEL_4 (3) - * @arg @ref LL_ADC_CHANNEL_5 (3) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) - * - * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. - * (2) On STM32U5, parameter available only on ADC instance: ADC4. - * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). - * Other channels are slow channels (conversion rate: refer to reference manual). - * (1, 2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @retval Returned value corresponds to one of literals LL_ADC_CHANNEL_x with specific formatting, + * refer to note of this function. */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { @@ -5968,42 +5936,8 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 (3) - * @arg @ref LL_ADC_CHANNEL_1 (3) - * @arg @ref LL_ADC_CHANNEL_2 (3) - * @arg @ref LL_ADC_CHANNEL_3 (3) - * @arg @ref LL_ADC_CHANNEL_4 (3) - * @arg @ref LL_ADC_CHANNEL_5 (3) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) - * - * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. - * (2) On STM32U5, parameter available only on ADC instance: ADC4. - * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). - * Other channels are slow channels (conversion rate: refer to reference manual). - * (1, 2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @retval Returned value corresponds to one of literals LL_ADC_CHANNEL_x with specific formatting, + * refer to note of this function. */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { @@ -8582,6 +8516,20 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } +/** + * @brief Get flag ADC internal voltage regulator (LDO) ready. + * @note On this STM32 series, this flag indicates LDO state in different way depending on ADC instances: + * - ADC4: latched as other flags, clear flag function available + * - ADC1, ADC2 (if available): current state (not latched as other flags, no clear flag function) + * @rmtoll ISR LDORDY LL_ADC_IsActiveFlag_LDORDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL); +} + /** * @brief Clear flag ADC ready. * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC @@ -8695,6 +8643,19 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); } +/** + * @brief Clear flag ADC internal voltage regulator (LDO) ready. + * @note On this STM32 series, this flag indicates LDO state in different way depending on ADC instances: + * - ADC4: latched as other flags, clear flag function available + * - ADC1, ADC2 (if available): current state (not latched as other flags, no clear flag function) + * @rmtoll ISR LDORDY LL_ADC_ClearFlag_LDORDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_LDORDY(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_LDORDY); +} /** * @} diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_cordic.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_cordic.h index 3920592b6..8dd402176 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_cordic.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_cordic.h @@ -131,12 +131,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE * @{ */ -#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one - 32-bit data input (Q1.31 format), or two - 16-bit data input (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input - (Q1.31 format) */ +#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one + 32-bits data input (Q1.31 format), or two + 16-bits data input (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input + (Q1.31 format) */ /** * @} */ @@ -144,12 +144,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBREAD NBREAD * @{ */ -#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data output (Q1.31 format), or two - 16-bit data output (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output - (Q1.31 format) */ +#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one + 32-bits data output (Q1.31 format), or two + 16-bits data output (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output + (Q1.31 format) */ /** * @} */ @@ -218,9 +218,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions * @{ */ @@ -749,8 +747,6 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_cortex.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_cortex.h index 103ab54cb..3347305b1 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_cortex.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_cortex.h @@ -102,10 +102,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control * @{ */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U -#define LL_MPU_CTRL_HARDFAULT_NMI 2U -#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U -#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -113,22 +113,28 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes * @{ */ -#define LL_MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define LL_MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define LL_MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ - -#define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ -#define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - -#define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */ -#define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - -#define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ -#define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ -#define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ -#define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/* Device memory attributes */ +#define LL_MPU_DEVICE_NGNRNE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define LL_MPU_DEVICE_NGNRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_NGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* Non-cacheable memory attribute */ +#define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ +#define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ +/* - transient mode attribute */ +#define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ +#define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ +/* - allocation attribute */ +#define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ +#define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ +#define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ +#define LL_MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ /** * @} */ @@ -145,8 +151,8 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access * @{ */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) -#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */ /** * @} */ @@ -154,9 +160,9 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable * @{ */ -#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */ +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */ +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */ /** * @} */ @@ -164,10 +170,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes * @{ */ -#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */ +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */ +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */ +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */ /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_fmac.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_fmac.h index 970aeb938..d8161456a 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_fmac.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_fmac.h @@ -38,7 +38,6 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ /** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants * @{ @@ -147,9 +146,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions * @{ */ @@ -1033,8 +1030,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions * @{ @@ -1042,7 +1037,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx); ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx); - /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_lptim.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_lptim.h index da22b3e07..1fa88dfda 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_lptim.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_lptim.h @@ -94,10 +94,10 @@ static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] = /** Legacy definitions for compatibility purpose @cond 0 */ -#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 /* for legacy purpose */ -#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 /* for legacy purpose */ -#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 /* for legacy purpose */ -#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 /* for legacy purpose */ +#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 +#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 +#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 +#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 /** @endcond */ @@ -541,12 +541,12 @@ typedef struct /** Legacy definitions for compatibility purpose @cond 0 */ -#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM /* for legacy purpose */ +#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM +#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 +#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 +#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O +#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O +#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM /** @endcond */ @@ -1689,6 +1689,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL)); } + /** * @brief Clear the autoreload match flag (ARRMCF) * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_opamp.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_opamp.h index 9d0029586..654bba965 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_opamp.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_opamp.h @@ -193,8 +193,8 @@ typedef struct /** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting * @{ */ -#define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */ -#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (OPAMP_CSR_VP_SEL) /*!< OPAMP non inverting input connected to DAC1 channel output(channel1 for OPAMP1, channel2 for OPAMP2) */ +#define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */ +#define LL_OPAMP_INPUT_NONINVERT_DAC (OPAMP_CSR_VP_SEL) /*!< OPAMP non inverting input connected to DAC1 channel output(channel1 for OPAMP1, channel2 for OPAMP2) */ /** * @} */ @@ -213,13 +213,15 @@ typedef struct * @{ */ #define LL_OPAMP_NONINVERTINGINPUT_IO0 LL_OPAMP_INPUT_NONINVERT_IO0 -#define LL_OPAMP_NONINVERTINGINPUT_DAC_CH LL_OPAMP_INPUT_NONINV_DAC1_CH1 +#define LL_OPAMP_NONINVERTINGINPUT_DAC_CH LL_OPAMP_INPUT_NONINVERT_DAC #define LL_OPAMP_INVERTINGINPUT_IO0 LL_OPAMP_INPUT_INVERT_IO0 #define LL_OPAMP_INVERTINGINPUT_IO1 LL_OPAMP_INPUT_INVERT_IO1 #define LL_OPAMP_INVERTINGINPUT_CONNECT_NO LL_OPAMP_INPUT_INVERT_CONNECT_NO -#define LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 LL_OPAMP_INPUT_NONINV_DAC1_CH1 +#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 LL_OPAMP_INPUT_NONINVERT_DAC + +#define LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 LL_OPAMP_INPUT_NONINVERT_DAC /** * @} */ @@ -554,7 +556,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(const OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @param InputNonInverting This parameter can be one of the following values: * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 - * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC * @retval None */ __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting) @@ -568,7 +570,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32 * @param OPAMPx OPAMP instance * @retval Returned value can be one of the following values: * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 - * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC */ __STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(const OPAMP_TypeDef *OPAMPx) { diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_rng.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_rng.h index 6a62949c2..75a8fc455 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_rng.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_rng.h @@ -674,6 +674,9 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) { +#if defined(RNG_HTCR_NIST_VALUE) + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ +#endif /* defined(RNG_HTCR_NIST_VALUE) */ WRITE_REG(RNGx->HTCR, HTCFG); } @@ -691,11 +694,47 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) /** * @} */ +#if defined(RNG_NSCR_NIST_VALUE) + +/** @defgroup RNG_LL_EF_Noise_Test_Control Noise Test Control + * @{ + */ + +/** + * @brief Set RNG Noise Test Control + * @rmtoll NSCR NOISECFG LL_RNG_SetNoiseConfig + * @param RNGx RNG Instance + * @param NOISECFG can be values of 32 bits + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetNoiseConfig(RNG_TypeDef *RNGx, uint32_t NOISECFG) +{ + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ + WRITE_REG(RNGx->NSCR, NOISECFG); +} + +/** + * @brief Get RNG Noise Test Control + * @rmtoll NSCR NOISECFG LL_RNG_GetNoiseConfig + * @param RNGx RNG Instance + * @retval Return 32-bit RNG Noise Test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetNoiseConfig(const RNG_TypeDef *RNGx) +{ + + return (uint32_t)READ_REG(RNGx->NSCR); +} + +/** + * @} + */ + +#endif /* defined(RNG_NSCR_NIST_VALUE) */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_sdmmc.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_sdmmc.h index f714f38b2..f8984ade4 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_sdmmc.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_sdmmc.h @@ -357,12 +357,12 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) -#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */ #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_DATATIMEOUT */ #ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ -#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT +#define SDMMC_SWDATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_SWDATATIMEOUT */ #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) @@ -1208,12 +1208,12 @@ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx); /* Command path state machine (CPSM) management functions */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command); uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response); /* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data); uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx); @@ -1283,7 +1283,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** @addtogroup HAL_SDMMC_LL_Group6 * @{ */ -uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf); +uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, const SDMMC_DMALinkNodeConfTypeDef *pNodeConf); uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode, SDMMC_DMALinkNodeTypeDef *pNode); uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode); diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_system.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_system.h index 45b5f811d..275a4da59 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_system.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_system.h @@ -135,6 +135,19 @@ extern "C" { * @} */ +#if defined(SYSCFG_CFGR1_ENDCAP) +/** @defgroup SYSTEM_LL_DECOUPLING_CAPACITANCE SYSCFG DECOUPLING CAPACITANCE + * @{ + */ +#define LL_SYSCFG_HSPI_CAPACITANCE_OFF 0x00000000U /*!< Decoupling with no capacitance value on HSPI supply */ +#define LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3 SYSCFG_CFGR1_ENDCAP_0 /*!< Decoupling with 1/3 of capacitance value on HSPI supply */ +#define LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3 SYSCFG_CFGR1_ENDCAP_1 /*!< Decoupling with 2/3 of capacitance value on HSPI supply */ +#define LL_SYSCFG_HSPI_CAPACITANCE_FULL SYSCFG_CFGR1_ENDCAP /*!< Decoupling with full capacitance value on HSPI supply */ +/** + * @} + */ +#endif /* SYSCFG_CFGR1_ENDCAP */ + /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK * @{ */ @@ -151,6 +164,77 @@ extern "C" { * @} */ +#if defined(SYSCFG_OTGHSPHYCR_CLKSEL) +/** @defgroup SYSTEM_LL_OTG_PHY_CLOCK_FREQUENCY SYSCFG OTG High-speed (HS) PHY reference clock frequency selection + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_CLK_16MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< Reference clock freqeuncy is 16 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 19.2 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_20MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 20 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_24MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 24 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_26MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | \ + SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 26 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_32MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | \ + SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 32 Mhz */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYCR_CLKSEL */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE) +/** @defgroup SYSTEM_LL_OTG_PHYTUNER_DISCONNECT_THRESTHOLD SYSCFG OTG High-speed (HS) PHYTUNER disconnnect threshold + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ +#define LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE) +/** @defgroup SYSTEM_LL_OTG_SQUELSH SYSCFG OTG High-speed (HS) PHY Squelch threshold adjustment + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ +#define LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +/** @defgroup SYSTEM_LL_OTG_TRANSMITTER_PREEMPHASIS_CURRENT SYSCFG OTG High-speed (HS) transmitter preemphasis current control + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | \ + SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +/** @defgroup SYSCFG_Lock_items SYSCFG Lock items + * @{ + */ +#define LL_SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ +#define LL_SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define LL_SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ +#define LL_SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ +#define LL_SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ +#define LL_SYSCFG_LOCK_ALL (LL_SYSCFG_MPU_NSEC | LL_SYSCFG_VTOR_NSEC | LL_SYSCFG_SAU | LL_SYSCFG_MPU_SEC | \ + LL_SYSCFG_VTOR_AIRCR_SEC) /*!< All */ +#else +#define LL_SYSCFG_LOCK_ALL (LL_SYSCFG_MPU_NSEC | LL_SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + /** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes * @note Only available when system implements security (TZEN=1) * @{ @@ -267,10 +351,10 @@ extern "C" { /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE * @{ */ -#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ -#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ -#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 0 (VREF_OUT3) */ -#define LL_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_2 /*!< Voltage reference scale 1 (VREF_OUT4) */ +#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define LL_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ /** * @} */ @@ -406,8 +490,75 @@ __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); } +#if defined(SYSCFG_CFGR1_ENDCAP) +/** + * @brief Set decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP LL_SYSCFG_SetHSPIDecouplingCapacitance + * @param Capacitance This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_FULL + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP, Capacitance); +} + +/** + * @brief Get decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP LL_SYSCFG_GetHSPIDecouplingCapacitance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_FULL + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetHSPIDecouplingCapacitance(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP)); +} +#endif /* SYSCFG_CFGR1_ENDCAP */ + +#if defined(SYSCFG_CFGR1_SRAMCACHED) +/** + * @brief Enable the cachability of internal SRAMs by DCACHE2. + * @rmtoll SYSCFG_CFGR1 SRAMCACHED LL_SYSCFG_EnableSRAMsCachability + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableSRAMsCachability(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} + +/** + * @brief Disable the cachability of internal SRAMs by DCACHE2. + * @rmtoll SYSCFG_CFGR1 SRAMCACHED LL_SYSCFG_DisableSRAMsCachability + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableSRAMsCachability(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} + /** - * @brief Enable Floating Point Unit Invalid operation Interrupt + * @brief Check if internal SRAMs cachability by DCACHE2 is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 SRAMCACHED LL_SYSCFG_IsEnabledSRAMsCachability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSRAMsCachability(void) +{ + return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED) == SYSCFG_CFGR1_SRAMCACHED) ? 1UL : 0UL); +} +#endif /* SYSCFG_CFGR1_SRAMCACHED */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_FPU_IT_MANAGEMENT FPU interrupt management + * @{ + */ + +/** + * @brief Enable Floating Point Unit Invalid operation Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC * @retval None */ @@ -417,7 +568,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) } /** - * @brief Enable Floating Point Unit Divide-by-zero Interrupt + * @brief Enable Floating Point Unit Divide-by-zero Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC * @retval None */ @@ -427,7 +578,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) } /** - * @brief Enable Floating Point Unit Underflow Interrupt + * @brief Enable Floating Point Unit Underflow Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC * @retval None */ @@ -437,7 +588,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) } /** - * @brief Enable Floating Point Unit Overflow Interrupt + * @brief Enable Floating Point Unit Overflow Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC * @retval None */ @@ -447,7 +598,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) } /** - * @brief Enable Floating Point Unit Input denormal Interrupt + * @brief Enable Floating Point Unit Input denormal Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC * @retval None */ @@ -457,7 +608,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) } /** - * @brief Enable Floating Point Unit Inexact Interrupt + * @brief Enable Floating Point Unit Inexact Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC * @retval None */ @@ -467,7 +618,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) } /** - * @brief Disable Floating Point Unit Invalid operation Interrupt + * @brief Disable Floating Point Unit Invalid operation Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC * @retval None */ @@ -477,7 +628,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) } /** - * @brief Disable Floating Point Unit Divide-by-zero Interrupt + * @brief Disable Floating Point Unit Divide-by-zero Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC * @retval None */ @@ -487,7 +638,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) } /** - * @brief Disable Floating Point Unit Underflow Interrupt + * @brief Disable Floating Point Unit Underflow Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC * @retval None */ @@ -497,7 +648,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) } /** - * @brief Disable Floating Point Unit Overflow Interrupt + * @brief Disable Floating Point Unit Overflow Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC * @retval None */ @@ -507,7 +658,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) } /** - * @brief Disable Floating Point Unit Input denormal Interrupt + * @brief Disable Floating Point Unit Input denormal Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC * @retval None */ @@ -517,7 +668,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) } /** - * @brief Disable Floating Point Unit Inexact Interrupt + * @brief Disable Floating Point Unit Inexact Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC * @retval None */ @@ -587,7 +738,182 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) } /** - * @brief Set connections to TIM1/8/15/16/17 Break inputs + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_CPU_LOCK CPU secure/non-secure lock + * @{ + */ + +/** + * @brief Lock the secure or non-secure VTOR registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_LockVTOR + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockVTOR(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSVTAIRCR); +#else + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Check the lock state of secure or non-secure VTOR registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_IsLockedVTOR + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedVTOR(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSVTAIRCR) == SYSCFG_CSLCKR_LOCKSVTAIRCR) ? 1UL : 0UL); +#else + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR) == SYSCFG_CNSLCKR_LOCKNSVTOR) ? 1UL : 0UL); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the non-secure VTOR registers. + * @rmtoll CNSLCKR LOCKNSVTOR LL_SYSCFG_LockVTOR_NS + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockVTOR_NS(void) +{ + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR); +} + +/** + * @brief Check the lock state of non-secure VTOR registers. + * @rmtoll CNSLCKR LOCKNSVTOR LL_SYSCFG_IsLockedVTOR_NS + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedVTOR_NS(void) +{ + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR) == SYSCFG_CNSLCKR_LOCKNSVTOR) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Lock the secure or non-secure MPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKNSMPU/LOCKSMPU LL_SYSCFG_LockMPU + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockMPU(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSMPU); +#else + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Check the lock state of secure or non-secure MPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKNSMPU/LOCKSMPU LL_SYSCFG_IsLockedMPU + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedMPU(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSMPU) == SYSCFG_CSLCKR_LOCKSMPU) ? 1UL : 0UL); +#else + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU) == SYSCFG_CNSLCKR_LOCKNSMPU) ? 1UL : 0UL); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the non-secure MPU registers. + * @rmtoll CNSLCKR LOCKNSMPU LL_SYSCFG_LockMPU_NS + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockMPU_NS(void) +{ + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU); +} + +/** + * @brief Check the lock state of non-secure MPU registers. + * @rmtoll CNSLCKR LOCKNSMPU LL_SYSCFG_IsLockedMPU_NS + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedMPU_NS(void) +{ + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU) == SYSCFG_CNSLCKR_LOCKNSMPU) ? 1UL : 0UL); +} + +/** + * @brief Lock the secure SAU registers. + * @rmtoll CSLCKR LOCKSAU LL_SYSCFG_LockSAU + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockSAU(void) +{ + SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSAU); +} + +/** + * @brief Check the lock state of secure SAU registers. + * @rmtoll CSLCKR LOCKSAU LL_SYSCFG_IsLockedSAU + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedSAU(void) +{ + return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSAU) == SYSCFG_CSLCKR_LOCKSAU) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Lock the secure or non-secure CPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_LockConfig + * @param Item Item(s) to set lock on. + * This parameter can be a combination of: + * @arg @ref LL_SYSCFG_MPU_NSEC + * @arg @ref LL_SYSCFG_VTOR_NSEC + * @arg @ref LL_SYSCFG_SAU + * @arg @ref LL_SYSCFG_MPU_SEC + * @arg @ref LL_SYSCFG_VTOR_AIRCR_SEC + * @arg @ref LL_SYSCFG_LOCK_ALL + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockConfig(uint32_t Item) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + MODIFY_REG(SYSCFG->CSLCKR, (SYSCFG_CSLCKR_LOCKSVTAIRCR | SYSCFG_CSLCKR_LOCKSMPU | SYSCFG_CSLCKR_LOCKSAU), Item); +#else + MODIFY_REG(SYSCFG->CNSLCKR, (SYSCFG_CNSLCKR_LOCKNSVTOR | SYSCFG_CNSLCKR_LOCKNSMPU), Item); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the non-secure CPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_LockConfig_NS + * @param Item Item(s) to set lock on. + * This parameter can be a combination of: + * @arg @ref LL_SYSCFG_MPU_NSEC + * @arg @ref LL_SYSCFG_VTOR_NSEC + * @arg @ref LL_SYSCFG_LOCK_ALL + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockConfig_NS(uint32_t Item) +{ + MODIFY_REG(SYSCFG->CNSLCKR, (SYSCFG_CNSLCKR_LOCKNSVTOR | SYSCFG_CNSLCKR_LOCKNSMPU), Item); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_TIMER_BREAK Timer break inputs + * @{ + */ + +/** + * @brief Set connections to TIM1/8/15/16/17 Break inputs. * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n @@ -605,7 +931,7 @@ __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) } /** - * @brief Get connections to TIM1/8/15/16/17 Break inputs + * @brief Get connections to TIM1/8/15/16/17 Break inputs. * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n @@ -622,63 +948,68 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL)); } +/** + * @} + */ /** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management * @{ */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /** - * @brief Configure Secure mode - * @note Only available from secure state when system implements security (TZEN=1) - * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure - * @param Configuration This parameter shall be the full combination - * of the following values: - * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC - * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC - * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + * @brief Clear Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus * @retval None */ -__STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration) +__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void) { - WRITE_REG(SYSCFG->SECCFGR, Configuration); + SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE); } -#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @brief Get Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done + * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE)); +} /** - * @brief Get Secure mode configuration - * @note Only available when system implements security (TZEN=1) - * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure - * @retval Returned value is the combination of the following values: - * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC - * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC - * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams + * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus + * @retval None */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void) +__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void) { - return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU)); + SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR); } /** - * @} + * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams + * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done + * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR)); +} /** * @} */ -/** @defgroup SYSTEM_LL_EF_COMPENSATION SYSCFG COMPENSATION +/** @defgroup SYSTEM_LL_EF_SYSCFG_COMPENSATION SYSCFG Compensation cell * @{ */ /** - * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD. * @rmtoll CCVR PCV1 LL_SYSCFG_GetPMOSVddCompensationValue * @retval Returned value is the PMOS compensation cell */ @@ -688,7 +1019,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationValue(void) } /** - * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD. * @rmtoll CCVR NCV1 LL_SYSCFG_GetNMOSVddCompensationValue * @retval Returned value is the NMOS compensation cell */ @@ -698,7 +1029,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void) } /** - * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2 + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2. * @rmtoll CCVR PCV2 LL_SYSCFG_GetPMOSVddIO2CompensationValue * @retval Returned value is the PMOS compensation cell */ @@ -708,7 +1039,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationValue(void) } /** - * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2 + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2. * @rmtoll CCVR NCV2 LL_SYSCFG_GetNMOSVddIO2CompensationValue * @retval Returned value is the NMOS compensation cell */ @@ -719,7 +1050,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void) #if defined(SYSCFG_CCVR_PCV3) /** - * @brief Get the compensation cell value of the HSPI IO PMOS transistor supplied by VDD + * @brief Get the compensation cell value of the HSPI IO PMOS transistor supplied by VDD. * @rmtoll CCVR PCV3 LL_SYSCFG_GetPMOSVddHSPICompensationValue * @retval Returned value is the PMOS compensation cell */ @@ -729,7 +1060,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationValue(void) } /** - * @brief Get the compensation cell value of the HSPI IO NMOS transistor supplied by VDD + * @brief Get the compensation cell value of the HSPI IO NMOS transistor supplied by VDD. * @rmtoll CCVR NCV3 LL_SYSCFG_GetNMOSVddHSPICompensationValue * @retval Returned value is the NMOS compensation cell */ @@ -740,7 +1071,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationValue(void) #endif /* SYSCFG_CCVR_PCV3 */ /** - * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD. * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS1 bit of the @@ -753,7 +1084,7 @@ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode) } /** - * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD. * @rmtoll CCCR PCC1 LL_SYSCFG_GetPMOSVddCompensationCode * @retval Returned value is the PMOS compensation cell */ @@ -763,7 +1094,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void) } /** - * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2 + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2. * @rmtoll CCCR PCC2 LL_SYSCFG_SetPMOSVddIO2CompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS2 bit of the @@ -775,9 +1106,8 @@ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode) MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC2, PMOSCode << SYSCFG_CCCR_PCC2_Pos); } - /** - * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2 + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2. * @rmtoll CCCR PCC2 LL_SYSCFG_GetPMOSVddIO2CompensationCode * @retval Returned value is the PMOS compensation */ @@ -788,7 +1118,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void) #if defined(SYSCFG_CCCR_PCC3) /** - * @brief Set the compensation cell code of the HSPI IO PMOS transistor supplied by VDD + * @brief Set the compensation cell code of the HSPI IO PMOS transistor supplied by VDD. * @rmtoll CCCR PCC3 LL_SYSCFG_SetPMOSVddHSPICompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS3 bit of the @@ -801,7 +1131,7 @@ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddHSPICompensationCode(uint32_t PMOSCode) } /** - * @brief Get the compensation cell code of the HSPI IO PMOS transistor supplied by VDD + * @brief Get the compensation cell code of the HSPI IO PMOS transistor supplied by VDD. * @rmtoll CCCR PCC3 LL_SYSCFG_GetPMOSVddHSPICompensationCode * @retval Returned value is the PMOS compensation */ @@ -812,7 +1142,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationCode(void) #endif /* SYSCFG_CCCR_PCC3 */ /** - * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD. * @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode * @param NMOSCode NMOS compensation code * This code is applied to the NMOS compensation cell when the CS2 bit of the @@ -825,7 +1155,7 @@ __STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode) } /** - * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD. * @rmtoll CCCR NCC1 LL_SYSCFG_GetNMOSVddCompensationCode * @retval Returned value is the Vdd compensation cell code for NMOS transistors */ @@ -835,7 +1165,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void) } /** - * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2 + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2. * @rmtoll CCCR NCC2 LL_SYSCFG_SetNMOSVddIO2CompensationCode * @param NMOSCode NMOS compensation code * This code is applied to the NMOS compensation cell when the CS2 bit of the @@ -848,9 +1178,8 @@ __STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode) MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC2, NMOSCode << SYSCFG_CCCR_NCC2_Pos); } - /** - * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2 + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2. * @rmtoll CCCR NCC2 LL_SYSCFG_GetNMOSVddIO2CompensationCode * @retval Returned value is the NMOS compensation cell code */ @@ -861,7 +1190,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void) #if defined(SYSCFG_CCCR_NCC3) /** - * @brief Set the compensation cell code of the HSPI IO NMOS transistor supplied by VDD + * @brief Set the compensation cell code of the HSPI IO NMOS transistor supplied by VDD. * @rmtoll CCCR NCC3 LL_SYSCFG_SetNMOSVddHSPICompensationCode * @param NMOSCode NMOS compensation code * This code is applied to the NMOS compensation cell when the CS3 bit of the @@ -875,7 +1204,7 @@ __STATIC_INLINE void LL_SYSCFG_SetNMOSVddHSPICompensationCode(uint32_t NMOSCode) } /** - * @brief Get the compensation cell code of the HSPI IO NMOS transistor supplied by VDD + * @brief Get the compensation cell code of the HSPI IO NMOS transistor supplied by VDD. * @rmtoll CCCR NCC3 LL_SYSCFG_GetNMOSVddHSPICompensationCode * @retval Returned value is the NMOS compensation cell code */ @@ -886,7 +1215,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationCode(void) #endif /* SYSCFG_CCCR_NCC3 */ /** - * @brief Enable the Compensation Cell of GPIO supplied by VDD + * @brief Enable the Compensation Cell of GPIO supplied by VDD. * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell * @note The vdd compensation cell can be used only when the device supply * voltage ranges from 1.71 to 3.6 V @@ -898,7 +1227,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableVddCompensationCell(void) } /** - * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2 + * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2. * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell * @note The Vdd I/O compensation cell can be used only when the device supply * voltage ranges from 1.08 to 3.6 V @@ -911,7 +1240,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void) #if defined(SYSCFG_CCCSR_EN3) /** - * @brief Enable the Compensation Cell of HSPI IO supplied by VDD + * @brief Enable the Compensation Cell of HSPI IO supplied by VDD. * @rmtoll CCCSR EN3 LL_SYSCFG_EnableVddHSPICompensationCell * @retval None */ @@ -922,7 +1251,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableVddHSPICompensationCell(void) #endif /* SYSCFG_CCCSR_EN3 */ /** - * @brief Disable the Compensation Cell of GPIO supplied by VDD + * @brief Disable the Compensation Cell of GPIO supplied by VDD. * @rmtoll CCCSR EN1 LL_SYSCFG_DisableVddCompensationCell * @note The Vdd compensation cell can be used only when the device supply * voltage ranges from 1.71 to 3.6 V @@ -934,7 +1263,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void) } /** - * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2 + * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2. * @rmtoll CCCSR EN2 LL_SYSCFG_DisableVddIO2CompensationCell * @note The Vdd I/O compensation cell can be used only when the device supply * voltage ranges from 1.08 to 3.6 V @@ -947,7 +1276,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void) #if defined(SYSCFG_CCCSR_EN3) /** - * @brief Disable the Compensation Cell of HSPI IO supplied by VDD + * @brief Disable the Compensation Cell of HSPI IO supplied by VDD. * @rmtoll CCCSR EN3 LL_SYSCFG_DisableVddHSPICompensationCell * @retval None */ @@ -958,7 +1287,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableVddHSPICompensationCell(void) #endif /* SYSCFG_CCCSR_EN3 */ /** - * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable + * @brief Check if the Compensation Cell of GPIO supplied by VDD is enabled. * @rmtoll CCCSR EN1 LL_SYSCFG_IsEnabled_VddCompensationCell * @retval State of bit (1 or 0). */ @@ -968,7 +1297,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddCompensationCell(void) } /** - * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enable + * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enabled. * @rmtoll CCCSR EN2 LL_SYSCFG_IsEnabled_VddIO2CompensationCell * @retval State of bit (1 or 0). */ @@ -979,7 +1308,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void) #if defined(SYSCFG_CCCSR_EN3) /** - * @brief Check if the Compensation Cell of HSPI IO supplied by VDD is enable + * @brief Check if the Compensation Cell of HSPI IO supplied by VDD is enabled. * @rmtoll CCCSR EN3 LL_SYSCFG_IsEnabled_VddHSPICompensationCell * @retval State of bit (1 or 0). */ @@ -990,7 +1319,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddHSPICompensationCell(void) #endif /* SYSCFG_CCCSR_EN3 */ /** - * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD. * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddCMPCR * @retval State of bit (1 or 0). */ @@ -1000,7 +1329,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void) } /** - * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2 + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2. * @rmtoll CCCSR RDY2 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR * @retval State of bit (1 or 0). */ @@ -1011,7 +1340,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void) #if defined(SYSCFG_CCCSR_RDY3) /** - * @brief Get Compensation Cell ready Flag of HSPI IO supplied by VDD + * @brief Get Compensation Cell ready Flag of HSPI IO supplied by VDD. * @rmtoll CCCSR RDY3 LL_SYSCFG_IsActiveFlag_VddHSPICMPCR * @retval State of bit (1 or 0). */ @@ -1022,7 +1351,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddHSPICMPCR(void) #endif /* SYSCFG_CCCSR_RDY3 */ /** - * @brief Set the compensation cell code selection of GPIO supplied by VDD + * @brief Set the compensation cell code selection of GPIO supplied by VDD. * @rmtoll CCCSR CS1 LL_SYSCFG_SetVddCellCompensationCode * @param CompCode: Selects the code to be applied for the Vdd compensation cell * This parameter can be one of the following values: @@ -1036,7 +1365,7 @@ __STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode) } /** - * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2 + * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2. * @rmtoll CCCSR CS2 LL_SYSCFG_SetVddIO2CellCompensationCode * @param CompCode: Selects the code to be applied for the VddIO compensation cell * This parameter can be one of the following values: @@ -1051,7 +1380,7 @@ __STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode) #if defined(SYSCFG_CCCSR_CS3) /** - * @brief Set the compensation cell code selection of HSPI IO supplied by VDD + * @brief Set the compensation cell code selection of HSPI IO supplied by VDD. * @rmtoll CCCSR CS3 LL_SYSCFG_SetVddHSPICellCompensationCode * @param CompCode: Selects the code to be applied for the VddIO compensation cell * This parameter can be one of the following values: @@ -1066,7 +1395,7 @@ __STATIC_INLINE void LL_SYSCFG_SetVddHSPICellCompensationCode(uint32_t CompCode) #endif /* SYSCFG_CCCSR_CS3 */ /** - * @brief Get the compensation cell code selection of GPIO supplied by VDD + * @brief Get the compensation cell code selection of GPIO supplied by VDD. * @rmtoll CCCSR CS1 LL_SYSCFG_GetVddCellCompensationCode * @retval Returned value can be one of the following values: * @arg LL_SYSCFG_VDD_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) @@ -1078,7 +1407,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void) } /** - * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2 + * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2. * @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIO2CellCompensationCode * @retval Returned value can be one of the following values: * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) @@ -1092,7 +1421,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void) #if defined(SYSCFG_CCCSR_CS3) /** - * @brief Get the compensation cell code selection of HSPI IO supplied by VDD + * @brief Get the compensation cell code selection of HSPI IO supplied by VDD. * @rmtoll CCCSR CS3 LL_SYSCFG_GetVddHSPICellCompensationCode * @retval Returned value can be one of the following values: * @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) @@ -1104,6 +1433,247 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddHSPICellCompensationCode(void) return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS3)); } #endif /* SYSCFG_CCCSR_CS3 */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_OTGPHY OTG HS PHY configurations + * @{ + */ + +#if defined(SYSCFG_OTGHSPHYCR_EN) +/** + * @brief Enable the OTG high-speed PHY. + * @rmtoll SYSCFG_OTGHSPHYCR EN LL_SYSCFG_EnableOTGPHY + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableOTGPHY(void) +{ + SET_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN); +} + +/** + * @brief Disable the OTG high-speed PHY. + * @rmtoll SYSCFG_OTGHSPHYCR EN LL_SYSCFG_DisableOTGPHY + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableOTGPHY(void) +{ + CLEAR_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN); +} + +/** + * @brief Check if the OTG high-speed PHY is enabled or disabled. + * @rmtoll SYSCFG_OTGHSPHYCR EN LL_SYSCFG_IsEnabledOTGPHY + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledOTGPHY(void) +{ + return ((READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN) == SYSCFG_OTGHSPHYCR_EN) ? 1UL : 0UL); +} +#endif /* SYSCFG_OTGHSPHYCR_EN */ + +#if defined(SYSCFG_OTGHSPHYCR_PDCTRL) +/** + * @brief Enable the OTG high-speed PHY common block power-down control. + * @rmtoll SYSCFG_OTGHSPHYCR PDCTRL LL_SYSCFG_EnableOTGPHYPowerDown + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableOTGPHYPowerDown(void) +{ + SET_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL); +} + +/** + * @brief Disable the OTG high-speed PHY common block power-down control. + * @rmtoll SYSCFG_OTGHSPHYCR PDCTRL LL_SYSCFG_DisableOTGPHYPowerDown + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableOTGPHYPowerDown(void) +{ + CLEAR_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL); +} + +/** + * @brief Check if the OTG high-speed PHY common block power-down is enabled or disabled. + * @rmtoll SYSCFG_OTGHSPHYCR PDCTRL LL_SYSCFG_IsEnabledOTGPHYPowerDown + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledOTGPHYPowerDown(void) +{ + return ((READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL) == SYSCFG_OTGHSPHYCR_PDCTRL) ? 1UL : 0UL); +} +#endif /* SYSCFG_OTGHSPHYCR_PDCTRL */ + +#if defined(SYSCFG_OTGHSPHYCR_CLKSEL) +/** + * @brief Set the OTG high-speed PHY reference clock frequency selection. + * @rmtoll SYSCFG_OTGHSPHYCR CLKSEL LL_SYSCFG_SetOTGPHYReferenceClockFrequency + * @param ClockFrequency This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_16MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_20MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_24MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_26MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_32MHZ + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYReferenceClockFrequency(uint32_t ClockFrequency) +{ + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, ClockFrequency); +} + +/** + * @brief Get the OTG high-speed PHY reference clock frequency selection. + * @rmtoll SYSCFG_OTGHSPHYCR CLKSEL LL_SYSCFG_GetOTGPHYReferenceClockFrequency + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_16MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_20MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_24MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_26MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_32MHZ + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYReferenceClockFrequency(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL)); +} +#endif /* SYSCFG_OTGHSPHYCR_CLKSEL */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE) +/** + * @brief Set the OTG high-speed PHY disconnect threshold adjustment. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 COMPDISTUNE LL_SYSCFG_SetOTGPHYDisconnectThresholdAdjustment + * @param DisconnectThreshold This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYDisconnectThresholdAdjustment(uint32_t DisconnectThreshold) +{ + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold); +} + +/** + * @brief Get the OTG high-speed PHY disconnect threshold adjustment. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 COMPDISTUNE LL_SYSCFG_GetOTGPHYDisconnectThresholdAdjustment + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYDisconnectThresholdAdjustment(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE)); +} +#endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_SQRXTUNE) +/** + * @brief Set the voltage level for the threshold used to detect valid high-speed data. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 SQRXTUNE LL_SYSCFG_SetOTGPHYSquelchThresholdAdjustment + * @param SquelchThreshold This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYSquelchThresholdAdjustment(uint32_t SquelchThreshold) +{ + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold); +} + +/** + * @brief Get the voltage level for the threshold used to detect valid high-speed data. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 SQRXTUNE LL_SYSCFG_GetOTGPHYSquelchThresholdAdjustment + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYSquelchThresholdAdjustment(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE)); +} +#endif /* SYSCFG_OTGHSPHYTUNER2_SQRXTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +/** + * @brief Set the OTG high-speed PHY transmitter preemphasis current control. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 TXPREEMPAMPTUNE LL_SYSCFG_SetOTGPHYTransmitterPreemphasisCurrent + * @param PreemphasisCurrent This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_1X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_2X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_3X + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYTransmitterPreemphasisCurrent(uint32_t PreemphasisCurrent) +{ + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent); +} + +/** + * @brief Get the OTG high-speed PHY transmitter preemphasis current control. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 TXPREEMPAMPTUNE LL_SYSCFG_GetOTGPHYTransmitterPreemphasisCurrent + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_1X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_2X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_3X + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYTransmitterPreemphasisCurrent(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE)); +} +#endif /* SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure Secure mode. + * @note Only available from secure state when system implements security (TZEN=1) + * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure + * @param Configuration This parameter shall be the full combination + * of the following values: + * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC + * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC + * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration) +{ + WRITE_REG(SYSCFG->SECCFGR, Configuration); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get Secure mode configuration. + * @note Only available when system implements security (TZEN=1) + * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure + * @retval Returned value is the combination of the following values: + * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC + * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC + * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU)); +} + +/** + * @} + */ + /** * @} */ @@ -1173,7 +1743,6 @@ __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } - /** * @brief Enable the Debug Clock Trace * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock @@ -1574,6 +2143,7 @@ __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) /** @defgroup SYSTEM_LL_EF_FLASH FLASH * @{ */ + /** * @brief Set FLASH Latency * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency @@ -1725,59 +2295,6 @@ __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) * @} */ - -/** @defgroup SYSTEM_LL_EF_ERASE_MEMORIE_STATUS ERASE MEMORIE STATUS - * @{ - */ - -/** - * @brief Clear Status of End of Erase for ICACHE and PKA RAMs - * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void) -{ - SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE); -} - -/** - * @brief Get Status of End of Erase for ICACHE and PKA RAMs - * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done - * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE)); -} - - -/** - * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams - * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void) -{ - SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR); -} - -/** - * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams - * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done - * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR)); -} -/** - * @} - */ - #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */ /** diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_tim.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_tim.h index 4780f6649..ea3366760 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_tim.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_tim.h @@ -682,10 +682,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); } @@ -4036,7 +4036,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u /** * @brief Select the external trigger (ETR) input source. - * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or + * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or * not a timer instance supports ETR source selection. * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource * @param TIMx Timer instance diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_ucpd.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_ucpd.h index 5ff7ced25..bdae50c8d 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_ucpd.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_ucpd.h @@ -869,7 +869,7 @@ __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Enable Rx hard resrt interrupt + * @brief Enable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1034,7 +1034,7 @@ __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Disable Rx hard resrt interrupt + * @brief Disable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1199,7 +1199,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPD } /** - * @brief Check if Rx hard resrt interrupt enabled + * @brief Check if Rx hard reset interrupt enabled * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Clear Rx hard resrt interrupt + * @brief Clear Rx hard reset interrupt * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1468,10 +1468,10 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx) */ /** - * @brief Check if FRS interrupt + * @brief Check if FRS Event Flag is active * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx) { @@ -1482,7 +1482,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPD * @brief Check if type c event on CC2 * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) { @@ -1493,7 +1493,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * * @brief Check if type c event on CC1 * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) { @@ -1501,10 +1501,21 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * } /** - * @brief Check if Rx message end interrupt + * @brief Check if Rx error flag is active + * @rmtoll SR RXERR LL_UCPD_IsActiveFlag_RxErr + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXERR) == UCPD_SR_RXERR) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx message end flag is active * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx) { @@ -1512,10 +1523,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const } /** - * @brief Check if Rx overrun interrupt + * @brief Check if Rx overrun flag is active * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx) { @@ -1523,10 +1534,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UC } /** - * @brief Check if Rx hard resrt interrupt + * @brief Check if Rx hard reset flag is active * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx) { @@ -1534,7 +1545,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const U } /** - * @brief Check if Rx orderset interrupt + * @brief Check if Rx orderset flag is active * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1545,7 +1556,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *con } /** - * @brief Check if Rx non empty interrupt + * @brief Check if Rx non empty flag is active * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1556,7 +1567,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCP } /** - * @brief Check if TX underrun interrupt + * @brief Check if TX underrun flag is active * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1567,7 +1578,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UC } /** - * @brief Check if hard reset sent interrupt + * @brief Check if hard reset sent flag is active * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1578,7 +1589,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *con } /** - * @brief Check if hard reset discard interrupt + * @brief Check if hard reset discard flag is active * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1589,7 +1600,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *con } /** - * @brief Check if Tx message abort interrupt + * @brief Check if Tx message abort flag is active * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1600,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const } /** - * @brief Check if Tx message sent interrupt + * @brief Check if Tx message sent flag is active * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1611,7 +1622,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *cons } /** - * @brief Check if Tx message discarded interrupt + * @brief Check if Tx message discarded flag is active * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1622,7 +1633,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *cons } /** - * @brief Check if Tx data receive interrupt + * @brief Check if Tx data interrupt flag is active * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1812,7 +1823,7 @@ __STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx) /** * @brief Read data - * @rmtoll TXDR RXDATA LL_UCPD_ReadData + * @rmtoll RXDR RXDATA LL_UCPD_ReadData * @param UCPDx UCPD Instance * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF */ @@ -1855,7 +1866,7 @@ __STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt) */ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx); -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct); +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct); void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct); /** diff --git a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_usb.h b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_usb.h index e644ab255..ac1bb184a 100644 --- a/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_usb.h +++ b/stm32cube/stm32u5xx/drivers/include/stm32u5xx_ll_usb.h @@ -935,7 +935,7 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; } \ else if ((wCount) <= 62U) \ { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal.c index f1136de67..b587c12cc 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal.c @@ -52,11 +52,11 @@ * @{ */ /** - * @brief STM32U5xx HAL Driver version number 1.6.0 + * @brief STM32U5xx HAL Driver version number 1.6.1 */ #define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32U5xx_HAL_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ -#define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32U5xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ |(__STM32U5xx_HAL_VERSION_SUB1 << 16U)\ @@ -664,7 +664,7 @@ void HAL_SYSCFG_DisableVREFBUF(void) * * @retval None */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) +void HAL_SYSCFG_EnableIOAnalogBooster(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } @@ -674,7 +674,7 @@ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) * * @retval None */ -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) +void HAL_SYSCFG_DisableIOAnalogBooster(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } @@ -684,7 +684,7 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) * * @retval None */ -void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void) +void HAL_SYSCFG_EnableIOAnalogVoltageSelection(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); } @@ -694,11 +694,45 @@ void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void) * * @retval None */ -void HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection(void) +void HAL_SYSCFG_DisableIOAnalogVoltageSelection(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); } +#if defined(SYSCFG_CFGR1_ENDCAP) +/** + * @brief Set decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP HAL_SYSCFG_SetHSPIDecouplingCapacitance + * @param Capacitance This parameter can be one of the following values: + * @arg @ref SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_FULL + * @retval None + */ +void HAL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_DECOUPLING_CAPACITANCE(Capacitance)); + + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP, Capacitance); +} + +/** + * @brief Get decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP HAL_SYSCFG_GetHSPIDecouplingCapacitance + * @retval Returned value can be one of the following values: + * @arg @ref SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_FULL + */ +uint32_t HAL_SYSCFG_GetHSPIDecouplingCapacitance(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP)); +} +#endif /* SYSCFG_CFGR1_ENDCAP */ + #if defined(SYSCFG_CFGR1_SRAMCACHED) /** * @brief Enable the Cacheability of internal SRAMx by DCACHE2 @@ -756,6 +790,7 @@ void HAL_SYSCFG_EnableVddHSPICompensationCell(void) SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); } #endif /* SYSCFG_CCCSR_EN3 */ + /** * @brief Disable the Compensation Cell of GPIO supplied by VDD * @rmtoll CCCSR EN1 HAL_SYSCFG_DisableVddCompensationCell @@ -865,8 +900,6 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - - /** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions * @brief SYSCFG attributes management functions. * @@ -957,7 +990,6 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri This parameter can be one of @ref SYSCFG_OTG_PHY_Enable * @retval None */ - void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig) { /* Check the parameter */ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cordic.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cordic.c index d3b051c7e..5eb8029c3 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cordic.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cordic.c @@ -164,12 +164,12 @@ static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAError(DMA_HandleTypeDef *hdma); + /** * @} */ /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions * @{ */ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cortex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cortex.c index 9b800dd12..88eeaf26a 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cortex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cortex.c @@ -74,19 +74,23 @@ (++) Reload Value should not exceed 0xFFFFFF [..] - *** How to configure MPU (secure and non secure) using CORTEX HAL driver *** + *** How to configure MPU using CORTEX HAL driver *** =========================================================== [..] - This section provides functions allowing to Enable and configure the MPU secure and non-secure. + This section provides functions allowing to configure the Memory Protection Unit (MPU). + (#) Disable the MPU using HAL_MPU_Disable(). + (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes(). + (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration link to + the right MPU attributes number. (#) Enable the MPU using HAL_MPU_Enable() function. - (#) Disable the MPU using HAL_MPU_Disable() function. - (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU. - (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU. - (#) Configure the MPU region using HAL_MPU_ConfigRegion() - and HAL_MPU_ConfigRegion_NS() to address the non secure MPU. - (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes() - and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU. + + -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter the memory + management fault handler MemManage_Handler() when an illegal memory access is performed. + -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region configuration + from affecting the new MPU configuration. + -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the secure context + and the same sequence as above applies to configure the non-secure MPU. @endverbatim ****************************************************************************** diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_crc_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_crc_ex.c index 061ab9223..3d15366d2 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_crc_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cryp.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cryp.c index c873ad74f..054ba9240 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cryp.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cryp.c @@ -363,6 +363,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma); static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize); static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp); static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); @@ -635,6 +636,13 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size, data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode); @@ -649,10 +657,23 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD { /* Disable AES to change key mode */ __HAL_CRYP_DISABLE(hcryp); + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set key mode selection (Normal, Wrapped or Shared key )*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | \ AES_CR_KEYSEL | AES_CR_KEYPROT | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | \ @@ -1206,7 +1227,11 @@ HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_Contex hcryp->Init.KeyMode = pcont->KeyMode; hcryp->Phase = pcont->Phase; hcryp->KeyIVConfig = pcont->KeyIVConfig; - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } /* Restore CRYP CR register content */ WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg)); @@ -1379,11 +1404,25 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); } else { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode and normal key selection */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_ENCRYPT | CRYP_KEYMODE_NORMAL); } @@ -1474,10 +1513,22 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, { hcryp->Size = Size; } - - /* Set Decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + if (IS_AES_ALL_INSTANCE(hcryp->Instance)) + { + /* Set Decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_DECRYPT | CRYP_KEYMODE_NORMAL); + } /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; @@ -1584,7 +1635,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1613,6 +1670,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1687,7 +1745,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -1715,6 +1779,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1772,7 +1837,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1878,6 +1949,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1934,7 +2006,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -1962,6 +2040,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -2005,26 +2084,30 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp */ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) { + uint32_t itsource = hcryp->Instance->IER; + uint32_t itflagsr = hcryp->Instance->SR; + uint32_t itflagisr = hcryp->Instance->ISR; + /* Check if Read or write error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET) + if ((itsource & CRYP_IT_RWEIE) != 0U) { /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET) + if ((itflagsr & CRYP_FLAG_WRERR) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); } /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET) + if ((itflagsr & CRYP_FLAG_RDERR) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); } } /* Check if Key error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET) + if ((itsource & CRYP_IT_KEIE) != 0U) { - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET) + if ((itflagisr & CRYP_FLAG_KEIF) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF); @@ -2033,9 +2116,9 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) } } - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET) + if ((itflagisr & CRYP_FLAG_CCF) != 0U) { - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + if ((itsource & CRYP_IT_CCFIE) != 0U) { /* Clear computation complete flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -3536,7 +3619,31 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @brief Writes Key in Key registers. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -3610,7 +3717,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -5761,7 +5867,7 @@ static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *In static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; - uint32_t count = 0U; + uint32_t count; /* In case of GCM payload phase encryption, check that suspension can be carried out */ if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cryp_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cryp_ex.c index 86b58c4bc..6862b3b51 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cryp_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_cryp_ex.c @@ -39,7 +39,7 @@ /** @addtogroup CRYPEx_Private_Defines * @{ */ - +#define CRYPEx_GENERAL_TIMEOUT 82U #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ #define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ #define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ @@ -66,6 +66,7 @@ /* Private function prototypes -----------------------------------------------*/ static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); /* Exported functions---------------------------------------------------------*/ /** @addtogroup CRYPEx_Exported_Functions * @{ @@ -125,6 +126,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c /* Check if initialization phase has already been performed */ if (hcryp->Phase == CRYPEx_PHASE_PROCESS) { + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Change the CRYP phase */ hcryp->Phase = CRYPEx_PHASE_FINAL; @@ -143,19 +151,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -459,7 +464,13 @@ HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Encryption operating mode(Mode 0)*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -504,7 +515,13 @@ HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } status = CRYPEx_KeyDecrypt(hcryp, Timeout); } else @@ -724,6 +741,31 @@ static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t T __HAL_UNLOCK(hcryp); return HAL_OK; } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ + +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @} diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dac.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dac.c index cbfc1ac14..f75b812b2 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dac.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dac.c @@ -1263,6 +1263,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } + else + { + /* In case of mode normal and buffer disabled, connection to both on chip periph and external pin is not possible */ + if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_DISABLE) + { + assert_param(sConfig->DAC_ConnectOnChipPeripheral != DAC_CHIPCONNECT_BOTH); + } + } assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat)); diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dcmi.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dcmi.c index 30ce86bb7..828fbb74b 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dcmi.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dcmi.c @@ -86,7 +86,7 @@ and a pointer to the user callback function. Use function HAL_DCMI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. This function allows to reset following callbacks: @@ -98,10 +98,10 @@ (+) MspDeInitCallback : callback for DCMI MspDeInit. By default, after the HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak (overridden) functions: examples FrameEventCallback(), HAL_DCMI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DCMI_Init + reset to the legacy weak (overridden) functions in the HAL_DCMI_Init and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DCMI_Init and HAL_DCMI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -116,7 +116,7 @@ When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -1000,7 +1000,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) * the embedded synchronization delimiters unmasks. * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask) +HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask) { /* Process Locked */ __HAL_LOCK(hdcmi); diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dma_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dma_ex.c index b8c6ac1ff..d60eca23d 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dma_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dma_ex.c @@ -1091,10 +1091,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNod assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); } /* Check DMA channel security and privilege attributes parameters */ @@ -3901,9 +3897,21 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO); } /********************************************************************************* CBR2 register value is updated */ - } + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_2D_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + else + { + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_LINEAR_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + /* Update node information value ************************************************************************************/ /* Set node information */ pNode->NodeInfo = pNodeConfig->NodeType; diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dsi.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dsi.c index cfe40f630..501784e61 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dsi.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_dsi.c @@ -1808,14 +1808,14 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t NbParams, uint32_t Param1, - uint8_t *ParametersTable) + const uint8_t *ParametersTable) { uint32_t uicounter; uint32_t nbBytes; uint32_t count; uint32_t tickstart; uint32_t fifoword; - uint8_t *pparams = ParametersTable; + const uint8_t *pparams = ParametersTable; /* Process locked */ __HAL_LOCK(hdsi); @@ -2861,7 +2861,7 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane * the configuration information for the DSI. * @retval HAL state */ -HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) +HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi) { return hdsi->State; } @@ -2872,7 +2872,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) * the configuration information for the DSI. * @retval DSI Error Code */ -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) +uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi) { /* Get the error code */ return hdsi->ErrorCode; diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_fdcan.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_fdcan.c index b0dcc8ede..5ca5d8fee 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_fdcan.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_fdcan.c @@ -1302,7 +1302,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA if (sFilterConfig->IdType == FDCAN_STANDARD_ID) { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.StdFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU)); assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType)); @@ -1322,7 +1322,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.ExtFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU)); assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType)); diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_fmac.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_fmac.c index 5d437fa35..0e65908df 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_fmac.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_fmac.c @@ -204,7 +204,6 @@ not defined, the callback registration feature is not available and weak callbacks are used. - @endverbatim * */ @@ -229,7 +228,6 @@ /** @defgroup FMAC_Private_Constants FMAC Private Constants * @{ */ - #define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU) #define MAX_PRELOAD_INDEX 0xFFU #define PRELOAD_ACCESS_DMA 0x00U @@ -322,7 +320,6 @@ /* Private variables ---------------------------------------------------------*/ /* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac); @@ -348,7 +345,6 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma); static void FMAC_DMAError(DMA_HandleTypeDef *hdma); /* Functions Definition ------------------------------------------------------*/ - /** @defgroup FMAC_Exported_Functions FMAC Exported Functions * @{ */ @@ -1203,7 +1199,7 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti */ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check handle state is ready */ if (hfmac->State == HAL_FMAC_STATE_READY) @@ -1222,11 +1218,24 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { (*(hfmac->pInputSize)) = hfmac->InputCurrentSize; } + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL)) { (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize; } + if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA) + { + /* Disable the DMA stream managing FMAC input data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaIn); + } + + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA) && (status == HAL_OK)) + { + /* Disable the DMA stream managing FMAC output data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaOut); + } + /* Reset FMAC unit (internal pointers) */ if (FMAC_Reset(hfmac) == HAL_ERROR) { @@ -1239,8 +1248,6 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { /* Reset the data pointers */ FMAC_ResetDataPointers(hfmac); - - status = HAL_OK; } /* Reset the busy flag */ @@ -2576,7 +2583,6 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma) #else HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ - } /** @@ -2708,11 +2714,11 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma) HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ } + /** * @} */ - /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_gfxmmu.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_gfxmmu.c index c2b16597c..82c12bf3e 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_gfxmmu.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_gfxmmu.c @@ -538,7 +538,7 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @param Address Start address of LUT in flash. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address) @@ -593,7 +593,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber) { @@ -640,7 +640,7 @@ HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, * @param lutLine LUT line parameters. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine) +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_LutLineTypeDef *lutLine) { HAL_StatusTypeDef status = HAL_OK; @@ -725,7 +725,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uin * @retval HAL status. * @note This function is only available on STM32U599/STM32U5A9 devices. */ -HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers) +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_BuffersTypeDef *Buffers) { HAL_StatusTypeDef status = HAL_OK; @@ -761,7 +761,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU * @note This function is only available on STM32U599/STM32U5A9 devices. */ HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu, - GFXMMU_CachePrefetchTypeDef *CachePrefetch) + const GFXMMU_CachePrefetchTypeDef *CachePrefetch) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_FUNCTIONAL_STATE(CachePrefetch->Activation)); @@ -814,7 +814,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu, * @note This function is only available on STM32U5F9/STM32U5G9 devices. */ HAL_StatusTypeDef HAL_GFXMMU_ModifyAddressCache(GFXMMU_HandleTypeDef *hgfxmmu, - GFXMMU_AddressCacheTypeDef *AddressCache) + const GFXMMU_AddressCacheTypeDef *AddressCache) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_FUNCTIONAL_STATE(AddressCache->Activation)); @@ -910,7 +910,7 @@ __weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu) * @param hgfxmmu GFXMMU handle. * @retval GFXMMU state. */ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu) +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu) { /* Return GFXMMU handle state */ return hgfxmmu->State; @@ -924,6 +924,7 @@ HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu) uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu) { uint32_t error_code; + uint32_t primask = __get_PRIMASK(); /* Enter in critical section */ __disable_irq(); @@ -933,7 +934,7 @@ uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu) hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE; /* Exit from critical section */ - __enable_irq(); + __set_PRIMASK(primask); /* Return GFXMMU error code */ return error_code; diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_gtzc.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_gtzc.c index c8b17c129..023a52131 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_gtzc.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_gtzc.c @@ -612,7 +612,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddres break; #if defined (FMC_BANK1) case FMC_BANK1: - size = TZSC_MPCWM1_MEM_SIZE; + size = TZSC_MPCWM2_MEM_SIZE; if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) { register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR); diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_hash.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_hash.c index 067f1133d..8f81950c2 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_hash.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_hash.c @@ -272,10 +272,10 @@ */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size); static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash); static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash); static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout); @@ -764,7 +764,7 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -790,7 +790,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -805,7 +805,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -822,7 +822,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -848,7 +848,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -863,7 +863,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -911,7 +911,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -935,7 +935,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -949,7 +949,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -965,7 +965,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -990,7 +990,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1004,7 +1004,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1077,7 +1077,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1107,7 +1107,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1164,7 +1164,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutB * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -1183,7 +1183,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -1225,7 +1225,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -1243,7 +1243,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1297,7 +1297,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1322,7 +1322,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1832,7 +1832,7 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma) * suspension time is stored in the handle for resumption later on. * @retval HAL status */ -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -1951,7 +1951,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size message digest size in bytes. * @retval None */ -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; @@ -2502,10 +2502,10 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2537,7 +2537,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Set the phase */ @@ -2553,7 +2553,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; Size_tmp = hhash->HashInCount; } /* ... or multi-buffer HASH processing end */ @@ -2561,7 +2561,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint { /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; + pInBuffer_tmp = (const uint8_t *)pInBuffer; Size_tmp = Size; /* Configure the number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(Size); @@ -2639,9 +2639,9 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2673,7 +2673,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */ } @@ -2684,7 +2684,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Check if initialization phase has already be performed */ @@ -2742,7 +2742,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -2864,7 +2864,7 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3030,7 +3030,7 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; @@ -3235,7 +3235,7 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, ui * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3313,7 +3313,7 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3424,7 +3424,7 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_hash_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_hash_ex.c index 8215c1549..dcbae5f16 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_hash_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_hash_ex.c @@ -148,7 +148,7 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -174,7 +174,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -189,7 +189,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -206,7 +206,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -232,7 +232,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -247,7 +247,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -290,7 +290,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -314,7 +314,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -328,7 +328,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -344,7 +344,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -368,7 +368,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -382,7 +382,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -434,7 +434,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -464,7 +464,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -521,7 +521,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -540,7 +540,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -583,7 +583,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -601,7 +601,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -659,7 +659,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -683,7 +683,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -759,7 +759,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -780,7 +780,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -806,7 +806,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -829,7 +829,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -850,7 +850,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -876,7 +876,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -898,7 +898,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -919,7 +919,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -945,7 +945,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -967,7 +967,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); @@ -988,7 +988,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -1014,7 +1014,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_hcd.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_hcd.c index 009b20879..ad79d6e82 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_hcd.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_hcd.c @@ -1710,6 +1710,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else { hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; } } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); @@ -2140,7 +2146,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, return HAL_ERROR; } - if (((epnum & 0xFU)== 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) + if (((epnum & 0xFU) == 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) { hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[0U].pmaadress; hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[0U].pmaaddr0; @@ -3832,8 +3838,8 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num & 0xFU].xfer_len == 0U) || ((received_bytes < hhcd->hc[ch_num & 0xFU].max_packet))) { - hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; - hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; } else { @@ -3846,10 +3852,10 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) { - hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + hhcd->hc[ch_num & 0xFU].toggle_in ^= 1U; } } - /* manage NACK Response */ + /* Manage NACK Response */ else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_NAK) && (hhcd->hc[ch_num & 0xFU].urb_state != URB_DONE)) { @@ -3863,7 +3869,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); } } - /* manage STALL Response */ + /* Manage STALL Response */ else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL) { (void)HAL_HCD_HC_Halt(hhcd, ch_num); @@ -3952,7 +3958,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* Handle Isochronous channel */ if ((ch_reg & USB_CH_UTYPE) == USB_EP_ISOCHRONOUS) { - /* correct transaction */ + /* Correct transaction */ if ((hhcd->Instance->ISTR & USB_ISTR_ERR) == 0U) { /* Double buffer isochronous out */ @@ -3961,7 +3967,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) HCD_SET_CH_TX_CNT(hhcd->Instance, phy_chnum, 0U); } #if (USE_USB_DOUBLE_BUFFER == 1U) - else /* double buffer isochronous out */ + else /* Double buffer isochronous out */ { /* Odd Transaction */ if ((ch_reg & USB_CH_DTOG_TX) != 0U) @@ -4010,14 +4016,20 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[ch_num & 0xFU].xfer_len = 0U; } + if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) + { + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + } + /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { - /* manage multiple Xfer */ + /* Manage multiple Xfer */ hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr; hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; - /* start a new transfer */ + /* Start a new transfer */ (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num & 0xFU]); } else @@ -4026,12 +4038,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; hhcd->hc[ch_num & 0xFU].state = HC_XFRC; hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; - - if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || - (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) - { - hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; - } } } /* Check NACK Response */ @@ -4046,7 +4052,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* Get Channel register value */ WregCh = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); - /*clear NAK status*/ + /* Clear NAK status */ WregCh &= ~USB_CHEP_NAK & USB_CHEP_REG_MASK; /* Update channel register Value */ @@ -4137,13 +4143,13 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) /* Host Port State */ hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; - /* clear all allocated virtual channel */ + /* Clear all allocated virtual channel */ HAL_HCD_ClearPhyChannel(hhcd); /* Reset the PMA current pointer */ (void)HAL_HCD_PMAReset(hhcd); - /* reset Ep0 Pma allocation state */ + /* Reset Ep0 Pma allocation state */ hhcd->ep0_PmaAllocState = 0U; /* Disconnection Callback */ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_i2c.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_i2c.c index 31582a2dd..3b1a2ee7f 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_i2c.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_i2c.c @@ -3458,6 +3458,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3515,37 +3517,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -7624,15 +7653,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_iwdg.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_iwdg.c index 6f6cac1fc..b1c88eacc 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_iwdg.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_iwdg.c @@ -137,7 +137,8 @@ The timeout value is multiplied by 1000 to be converted in milliseconds. LSI startup time is also considered here by adding LSI_STARTUP_TIME converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT (((1UL * 1024UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define HAL_IWDG_DEFAULT_TIMEOUT (((1UL * 1024UL * 1000UL) / (LSI_VALUE / 128U)) + \ + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_EWU | IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_lptim.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_lptim.c index 184b4d0fc..821aaea8f 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_lptim.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_lptim.c @@ -387,10 +387,10 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) { if ((hlptim->Instance == LPTIM3) || (hlptim->Instance == LPTIM4)) { - /* Check LPTIM3 Input1 source */ + /* Check LPTIM Input1 source */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); - /* Configure LPTIM3 Input1 source */ + /* Configure LPTIM Input1 source */ hlptim->Instance->CFGR2 = hlptim->Init.Input1Source; } } diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_mmc.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_mmc.c index 634c86796..3ea9aaea5 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_mmc.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_mmc.c @@ -2120,7 +2120,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); @@ -2271,7 +2271,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp * will contain the MMC card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); @@ -4302,7 +4302,6 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 * @brief Used to select the partition. * @param hmmc: Pointer to MMC handle * @param Partition: Partition type - * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition) @@ -4683,7 +4682,7 @@ HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, /** * @brief Allows to get the value of write counter within the RPMB partition. * @param hmmc: Pointer to MMC handle - * @param Nonce: pointer to the value of nonce (16 bytes) + * @param pNonce: pointer to the value of nonce (16 bytes) * @param Timeout: Specify timeout value * @retval write counter value. */ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_mmc_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_mmc_ex.c index 79589f4b7..77b66947a 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_mmc_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_mmc_ex.c @@ -217,7 +217,8 @@ HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_DisableCircularMode(MMC_DMALinkedListT * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, + const MMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -326,7 +327,8 @@ HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, MM * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, + const MMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_ospi.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_ospi.c index 1a4a2077a..86b77be30 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_ospi.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_ospi.c @@ -1148,7 +1148,8 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1241,7 +1242,8 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -2708,8 +2710,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * } /********************* Deactivation of other instance *********************/ - if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || - (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || + ((cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && (cfg->DQSPort != 0U)) || + (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pcd.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pcd.c index 45621b97b..bed0c62be 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pcd.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pcd.c @@ -1055,7 +1055,6 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) __HAL_PCD_DISABLE(hpcd); (void)USB_DevDisconnect(hpcd->Instance); - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -1486,7 +1485,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && - ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; @@ -1951,7 +1950,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1966,7 +1965,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; #if defined (USB_OTG_FS) || defined (USB_OTG_HS) @@ -2642,7 +2641,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } } @@ -2763,7 +2761,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2839,7 +2837,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2871,11 +2869,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2925,6 +2923,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2936,10 +2940,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2970,7 +2976,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2998,6 +3004,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -3010,10 +3022,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -3043,7 +3057,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -3052,13 +3066,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - #endif /* defined (USB_DRD_FS) */ /** @@ -3066,7 +3079,6 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pcd_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pcd_ex.c index a4a9f4ac5..1e61af7f8 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pcd_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pcd_ex.c @@ -484,7 +484,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } } - /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -519,7 +518,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) return HAL_OK; } - #endif /* defined (USB_DRD_FS) */ /** diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pka.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pka.c index 5618ef5b0..b93ae117d 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pka.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pka.c @@ -1121,11 +1121,18 @@ void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) */ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + } + else + { + return HAL_ERROR; + } } /** @@ -1136,11 +1143,18 @@ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTy */ HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + } + else + { + return HAL_ERROR; + } } /** diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pwr.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pwr.c index a7a6fbda3..29304a020 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pwr.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pwr.c @@ -594,7 +594,6 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry) * clear of pending events before. * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and * no clear of pending event before. - * @note In System STOP mode, all I/O pins keep the same state as in Run mode. * @retval None. */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry) @@ -836,6 +835,13 @@ __weak void HAL_PWR_PVDCallback(void) * privileged access. * @note Privilege attribute for nsecure items can be managed by a secure * privileged access or by a nsecure privileged access. + * @note As the privileged attributes concern either all secure or all non-secure + * PWR resources accesses and not each PWR individual items access attribute, + * the application must ensure that the privilege access attribute configurations + * are coherent amongst the security level set on PWR individual items so not to + * overwrite a previous more restricted access rule (consider either all secure + * and/or all non-secure PWR resources accesses by privileged-only transactions + * or privileged and unprivileged transactions). * @param Item : Specifies the item(s) to set attributes on. * This parameter can be a combination of @ref PWR_Items. * @param Attributes : Specifies the available attribute(s). @@ -933,6 +939,8 @@ HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; } #else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); /* Get Non-Secure privileges attribute */ attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; #endif /* __ARM_FEATURE_CMSE */ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pwr_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pwr_ex.c index 0dc86b9ab..15b487453 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pwr_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_pwr_ex.c @@ -864,7 +864,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN1); } } @@ -877,7 +877,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN2); } } @@ -890,7 +890,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN3); } } @@ -903,7 +903,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN4); } } @@ -916,7 +916,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN5); } } @@ -929,7 +929,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN6); } } @@ -942,7 +942,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN7); } } @@ -955,7 +955,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN8); } } } diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rcc.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rcc.c index 1b47d2327..0d84eb060 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rcc.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rcc.c @@ -1657,6 +1657,10 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { GPIO_InitTypeDef gpio_initstruct; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(RCC_MCOx); + /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); @@ -2062,6 +2066,14 @@ __weak void HAL_RCC_CSSCallback(void) /** * @brief Configure the RCC item attribute(s). * @note Available attributes are to secure items and set RCC as privileged. + * @note As the privileged attributes concern either all secure or all + * non-secure RCC resources accesses and not each RCC individual items + * access attribute, the application must ensure that the privilege + * access attribute configurations are coherent amongst the security + * level set on RCC individual items so not to overwrite a previous + * more restricted access rule (consider either all secure and/or all + * non-secure RCC resources accesses by privileged-only transactions or + * privileged and unprivileged transactions). * @param Item Item(s) to set attributes on. * This parameter can be a one or a combination of @ref RCC_items * @param Attributes specifies the RCC secure/privilege attributes. @@ -2101,10 +2113,14 @@ void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes) /* Non-secure Privilege attribute */ case RCC_NSEC_PRIV: SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); break; /* Non-secure Non-Privilege attribute */ case RCC_NSEC_NPRIV: CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); break; #endif /* __ARM_FEATURE_CMSE */ default: @@ -2154,6 +2170,9 @@ HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut #else /* Get Non-Secure privileges attribute */ attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV; + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + #endif /* __ARM_FEATURE_CMSE */ /* return value */ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rng.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rng.c index bfcbe13ee..eaa87ecea 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rng.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rng.c @@ -197,8 +197,20 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Disable RNG */ __HAL_RNG_DISABLE(hrng); +#if defined(RNG_CR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST | hrng->Init.ClockErrorDetection); +#else /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); +#endif /* RNG_CR_NIST_VALUE */ +#if defined(RNG_HTCR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); +#endif /* RNG_HTCR_NIST_VALUE */ +#if defined(RNG_NSCR_NIST_VALUE) + WRITE_REG(hrng->Instance->NSCR, RNG_NSCR_NIST_VALUE); +#endif /* RNG_NSCR_NIST_VALUE */ /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -238,7 +250,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { hrng->State = HAL_RNG_STATE_ERROR; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; @@ -641,6 +653,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } } diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rng_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rng_ex.c index adeb1b3bb..145800688 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rng_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rng_ex.c @@ -30,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNG_Ex +/** @addtogroup RNGEx * @brief RNG Extended HAL module driver. * @{ */ @@ -41,7 +41,7 @@ /* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Private_Constants +/** @addtogroup RNGEx_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -53,11 +53,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions * @{ */ -/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim @@ -309,6 +309,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /* sequence to fully recover from a seed error */ status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } } else { diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rtc.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rtc.c index 96999b17f..236e5ca5e 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rtc.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_rtc.c @@ -362,39 +362,45 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Check if the calendar has been not initialized */ + /* Check whether the calendar needs to be initialized */ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) { - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - if (status == HAL_OK) + /* Check that the RTC mode is not 'binary only' */ + if (__HAL_RTC_GET_BINARY_MODE(hrtc) != RTC_BINARY_ONLY) { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); - /* Set RTC_CR register */ - SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); - - /* Configure the RTC PRER */ - WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Binary mode */ - MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); if (status == HAL_OK) { - MODIFY_REG(RTC->CR, \ - RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ - hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + + if (status == HAL_OK) + { + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + } } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } } else { diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_sd.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_sd.c index 594045c1b..af08837d2 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_sd.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_sd.c @@ -2111,7 +2111,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); @@ -2327,7 +2327,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT * will contain the SD card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_sd_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_sd_ex.c index 0e44eb5a6..b18160c1e 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_sd_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_sd_ex.c @@ -196,7 +196,8 @@ HAL_StatusTypeDef HAL_SDEx_DMALinkedList_DisableCircularMode(SD_DMALinkedListTyp * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SDMMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, + const SDMMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -290,7 +291,8 @@ HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SDMMC * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SDMMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, + const SDMMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks) { diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_sdio.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_sdio.c index a2d420733..83b3e7052 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_sdio.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_sdio.c @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -86,6 +86,9 @@ (#) Configure the SDIO Card speed mode by the API : HAL_SDIO_SetSpeedMode(). + (#) To custumize the SDIO Init card function for the enumeration card sequence, you can register a user callback + function by calling the HAL_SDIO_RegisterIdentifyCardCallback before the HAL_SDIO_Init() function. + *** SDIO Card Read operation *** ============================== [..] @@ -311,6 +314,7 @@ HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) { SDIO_InitTypeDef Init; uint32_t sdmmc_clk; + uint8_t data; /* Check the parameters */ assert_param(hsdio != NULL); @@ -375,12 +379,31 @@ HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); - if (SDIO_InitCard(hsdio) != HAL_OK) + if (hsdio->SDIO_IdentifyCard == NULL) + { + hsdio->SDIO_IdentifyCard = SDIO_InitCard; + } + /* SDIO enumeration sequence */ + if (hsdio->SDIO_IdentifyCard(hsdio) != HAL_OK) { hsdio->State = HAL_SDIO_STATE_RESET; return HAL_ERROR; } + /* Configure the SDMMC user parameters */ + Init.ClockEdge = hsdio->Init.ClockEdge; + Init.ClockPowerSave = hsdio->Init.ClockPowerSave; + Init.BusWide = hsdio->Init.BusWide; + Init.HardwareFlowControl = hsdio->Init.HardwareFlowControl; + Init.ClockDiv = hsdio->Init.ClockDiv; + (void)SDMMC_Init(hsdio->Instance, Init); + + data = (hsdio->Init.BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U; + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK) + { + return HAL_ERROR; + } + hsdio->Context = SDIO_CONTEXT_NONE; hsdio->State = HAL_SDIO_STATE_READY; @@ -1937,6 +1960,7 @@ HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDI return status; } +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ #if (USE_SDIO_TRANSCEIVER != 0U) /** @@ -1999,7 +2023,30 @@ HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsd } #endif /* USE_SDIO_TRANSCEIVER */ -#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ +/** + * @brief Register a User SDIO Identification Callback + * @param hsdio: Pointer to SDIO handle + * @param pCallback: pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(pCallback != NULL); + + if (pCallback == NULL) + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + hsdio->SDIO_IdentifyCard = pCallback; + + return HAL_OK; +} /** * @} */ @@ -2403,7 +2450,7 @@ HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio) * @param Callback io IRQ handler. */ HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, - HAL_SDIO_IOFunction_CallbackTypeDef Callback) + HAL_SDIO_IOFunction_CallbackTypeDef pCallback) { /* Check the parameters */ assert_param(hsdio != NULL); @@ -2415,7 +2462,7 @@ HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, return HAL_ERROR; } - hsdio->SDIO_IOFunction_Callback[(uint32_t)IOFunction] = Callback; + hsdio->SDIO_IOFunction_Callback[(uint32_t)IOFunction] = pCallback; hsdio->IOFunctionMask |= (1U << (uint8_t)IOFunction); return HAL_OK; @@ -2444,7 +2491,6 @@ static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio) uint16_t sdio_rca = 1U; uint32_t Resp4; uint32_t nbr_of_func; - SDMMC_InitTypeDef Init; /* Identify card operating voltage */ errorstate = SDMMC_CmdGoIdleState(hsdio->Instance); @@ -2514,21 +2560,6 @@ static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio) return HAL_ERROR; } - /* Configure the SDMMC user parameters */ - Init.ClockEdge = hsdio->Init.ClockEdge; - Init.ClockPowerSave = hsdio->Init.ClockPowerSave; - Init.BusWide = hsdio->Init.BusWide; - Init.HardwareFlowControl = hsdio->Init.HardwareFlowControl; - Init.ClockDiv = hsdio->Init.ClockDiv; - (void)SDMMC_Init(hsdio->Instance, Init); - - uint8_t data = (hsdio->Init.BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U; - - if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK) - { - return HAL_ERROR; - } - return HAL_OK; } diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_smartcard.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_smartcard.c index b46857074..b7f3a1bf4 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_smartcard.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_smartcard.c @@ -828,6 +828,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, co /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -935,6 +943,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; @@ -1001,6 +1017,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->TxXferCount = Size; hsmartcard->TxISR = NULL; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -1094,6 +1118,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Configure Rx interrupt processing */ if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess)) { @@ -1395,8 +1427,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1420,8 +1454,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1492,8 +1528,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1558,8 +1596,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1657,9 +1697,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable DMA Tx at UART level */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1681,8 +1723,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1771,8 +1815,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1869,8 +1915,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmarx != NULL) { @@ -2052,8 +2100,10 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel */ if (hsmartcard->hdmarx != NULL) { @@ -2106,8 +2156,10 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel */ if (hsmartcard->hdmatx != NULL) { @@ -2744,10 +2796,12 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); hsmartcard->TxXferCount = 0U; +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the SMARTCARD associated USART CR3 register */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Enable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); } @@ -2767,10 +2821,12 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the SMARTCARD associated USART CR3 register */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* At end of Rx process, restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_spi.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_spi.c index 58e66052e..86f93668e 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_spi.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_spi.c @@ -240,6 +240,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { uint32_t crc_length; uint32_t packet_length; +#if (USE_SPI_CRC != 0UL) + uint32_t crc_poly_msb_mask; +#endif /* USE_SPI_CRC */ /* Check the SPI handle allocation */ if (hspi == NULL) @@ -327,6 +330,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) crc_length = hspi->Init.CRCLength; } + /* Verify the correctness of polynom size */ + assert_param(IS_SPI_CRC_POLYNOMIAL_SIZE(hspi->Init.CRCPolynomial, crc_length)); + /* Verify that the CRC Length is higher than DataSize */ if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos)) { @@ -444,15 +450,21 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) || ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT))) { + /* Set SPI_CR1_CRC33_17 bit */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + /* Write CRC polynomial in SPI Register */ + WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); } else { + /* Clear SPI_CR1_CRC33_17 bit */ CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); - } - /* Write CRC polynomial in SPI Register */ - WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); + /* Write CRC polynomial and set MSB bit at 1 in SPI Register */ + /* Set MSB is mandatory for a correct CRC computation */ + crc_poly_msb_mask = (0x1UL << ((crc_length >> SPI_CFG1_CRCSIZE_Pos) + 0x1U)); + WRITE_REG(hspi->Instance->CRCPOLY, (hspi->Init.CRCPolynomial) | crc_poly_msb_mask); + } } #endif /* USE_SPI_CRC */ @@ -834,6 +846,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1050,6 +1072,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint32_t temp_sr_reg; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); #if defined (__GNUC__) __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ @@ -1057,6 +1082,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1115,13 +1150,32 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { - /* Check the RXWNE/EOT flag */ - if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); hspi->pRxBuffPtr += sizeof(uint32_t); hspi->RxXferCount--; } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + } + /* Check if transfer is locked because of a suspend */ + else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP)) + { + /* Verify suspend is triggered by hardware and not software */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + } + } else { /* Timeout management */ @@ -1147,6 +1201,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + /* Check the RXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { @@ -1158,6 +1215,43 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + /* Check if transfer is locked because of a suspend */ + else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP)) + { + /* Verify suspend is triggered by hardware and not software */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + } + } else { /* Timeout management */ @@ -1183,6 +1277,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + /* Check the RXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { @@ -1190,6 +1287,35 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->pRxBuffPtr += sizeof(uint8_t); hspi->RxXferCount--; } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + /* Check if transfer is locked because of a suspend */ + else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP)) + { + /* Verify suspend is triggered by hardware and not software */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + } + } else { /* Timeout management */ @@ -1260,12 +1386,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t uint32_t tickstart; uint32_t fifo_length; + uint32_t temp_sr_reg; uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1341,28 +1480,44 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check RXWNE/EOT flag */ - if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL)) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount --; - initial_RxXferCount = hspi->RxXferCount; - } + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + if (initial_RxXferCount > 0UL) { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - /* Unlock the process */ - __HAL_UNLOCK(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1388,32 +1543,70 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check the RXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + if (initial_RxXferCount > 0UL) { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1432,28 +1625,58 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check the RXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + if (initial_RxXferCount > 0UL) { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - /* Unlock the process */ - __HAL_UNLOCK(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1495,6 +1718,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if ((pData == NULL) || (Size == 0UL)) { return HAL_ERROR; @@ -1579,6 +1812,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1674,6 +1917,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1790,6 +2043,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1976,6 +2239,15 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } if (hspi->State != HAL_SPI_STATE_READY) { @@ -2166,6 +2438,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -2200,9 +2482,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); /* Packing mode management is enabled by the DMA settings */ - if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && \ + ((hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) || \ + (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD)) && \ (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ - ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && \ + ((hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE) || \ + (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)))) { /* Restriction the DMA data received is not allowed in this mode */ /* Unlock the process */ @@ -2609,6 +2895,15 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized before any call to DMA Abort functions */ + if (hspi->hdmarx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */ + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + } + if (hspi->hdmatx != NULL) { if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_spi_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_spi_ex.c index e46eb9502..e26b02892 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_spi_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_spi_ex.c @@ -57,7 +57,6 @@ data transfers. (#) SPIEx function: - (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_EnableLockConfiguration() (++) HAL_SPIEx_ConfigureUnderrun() diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_tim.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_tim.c index 97eadff42..48d7aa565 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_tim.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_tim.c @@ -7280,8 +7280,6 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - TIMx->CR1 = tmpcr1; - /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; @@ -7294,16 +7292,15 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure TIMx->RCR = Structure->RepetitionCounter; } + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } + TIMx->CR1 = tmpcr1; } /** @@ -7428,7 +7425,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - } if (IS_TIM_BREAK_INSTANCE(TIMx)) diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_tim_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_tim_ex.c index afe917be1..186beac39 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_tim_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_tim_ex.c @@ -872,7 +872,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -1149,17 +1149,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - @endverbatim * @{ */ @@ -1403,7 +1392,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -2199,6 +2188,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); @@ -2215,15 +2205,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); - - /* Set BREAK AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { @@ -2231,20 +2213,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); - - /* Set BREAK2 AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); } /* Set TIMx_BDTR */ @@ -2268,7 +2243,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - { HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; @@ -2703,7 +2677,6 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B } break; } - case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ @@ -3177,7 +3150,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) */ /** - * @brief Hall commutation changed callback in non-blocking mode + * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3191,7 +3164,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Hall commutation changed half complete callback in non-blocking mode + * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3206,7 +3179,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break detection callback in non-blocking mode + * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3221,7 +3194,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break2 detection callback in non blocking mode + * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ @@ -3461,6 +3434,11 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } else { /* nothing to do */ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_uart.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_uart.c index e1a10962c..0281da35c 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_uart.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_uart.c @@ -721,7 +721,6 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID @@ -846,7 +845,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID @@ -1444,6 +1442,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + +#endif /* USART_DMAREQUESTS_SW_WA */ if (huart->hdmatx != NULL) { /* Set the UART DMA transfer complete callback */ @@ -1506,9 +1509,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } } +#if !defined(USART_DMAREQUESTS_SW_WA) /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -2577,6 +2582,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3919,7 +3946,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -4591,6 +4617,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4755,6 +4782,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_uart_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_uart_ex.c index 9118d7922..e276ee185 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_uart_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_uart_ex.c @@ -555,7 +555,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; @@ -705,6 +705,14 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; @@ -824,6 +832,14 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->RxEventType = HAL_UART_RXEVENT_TC; diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_usart.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_usart.c index 0d77c727e..3793fb1b0 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_usart.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_usart.c @@ -144,7 +144,7 @@ */ /** @defgroup USART USART - * @brief HAL USART Synchronous module driver + * @brief HAL USART Synchronous SPI module driver * @{ */ @@ -227,8 +227,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit @@ -240,7 +240,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous SPI configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -318,7 +318,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) return HAL_ERROR; } - /* In Synchronous mode, the following bits must be kept cleared: + /* In Synchronous SPI mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ @@ -659,11 +659,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI data transfers. - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). [..] @@ -3224,7 +3223,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_usart_ex.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_usart_ex.c index 83112cccf..c050547f0 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_usart_ex.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_usart_ex.c @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) /* Disable USART */ __HAL_USART_DISABLE(husart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_xspi.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_xspi.c index 3b52eeb35..f7dcc4534 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_xspi.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_hal_xspi.c @@ -1282,7 +1282,7 @@ HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusC * @note This function is used only in Indirect Write Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout) +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); @@ -1302,7 +1302,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pD /* Configure counters and size */ hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; hxspi->XferSize = hxspi->XferCount; - hxspi->pBuffPtr = pData; + hxspi->pBuffPtr = (uint8_t *)pData; /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -1444,7 +1444,7 @@ HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pDa * @note This function is used only in Indirect Write Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; @@ -1462,7 +1462,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const /* Configure counters and size */ hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; hxspi->XferSize = hxspi->XferCount; - hxspi->pBuffPtr = pData; + hxspi->pBuffPtr = (uint8_t *)pData; /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -1565,7 +1565,7 @@ HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const * of data and the fifo threshold should be aligned on word * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; uint32_t data_size = hxspi->Instance->DLR + 1U; @@ -1644,7 +1644,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *cons if (status == HAL_OK) { hxspi->XferSize = hxspi->XferCount; - hxspi->pBuffPtr = pData; + hxspi->pBuffPtr = (uint8_t *)pData; /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -2542,12 +2542,10 @@ HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSP HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) { HAL_StatusTypeDef status = HAL_OK; - uint32_t state; uint32_t tickstart = HAL_GetTick(); - /* Check if the state is in one of the busy or configured states */ - state = hxspi->State; - if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + /* Check if the state is not in reset state */ + if (hxspi->State != HAL_XSPI_STATE_RESET) { /* Check if the DMA is enabled */ if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) @@ -2620,11 +2618,9 @@ HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) { HAL_StatusTypeDef status = HAL_OK; - uint32_t state; - /* Check if the state is in one of the busy or configured states */ - state = hxspi->State; - if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + /* Check if the state is not in reset state */ + if (hxspi->State != HAL_XSPI_STATE_RESET) { /* Disable all interrupts */ HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE)); @@ -3586,7 +3582,7 @@ static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxsp { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hxspi->State = HAL_XSPI_STATE_ERROR; + hxspi->State = HAL_XSPI_STATE_READY; hxspi->ErrorCode |= HAL_XSPI_ERROR_TIMEOUT; return HAL_TIMEOUT; @@ -3662,6 +3658,14 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC /* Configure the CCR register with DQS and SIOO modes */ *ccr_reg = (pCmd->DQSMode | pCmd->SIOOMode); + /* Workaround for Erratasheet: Memory-mapped write error response when DQS output is disabled */ + if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) + { + /* When doing memory-mapped writes, set the DQSE bit of the OCTOSPI_WCCR register, + even for memories that have no DQS pin. */ + SET_BIT((*ccr_reg), XSPI_CCR_DQSE); + } + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) { /* Configure the ABR register with alternate bytes value */ @@ -3684,6 +3688,25 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC } } + /* Configure SSHIFT register to handle SDR/DTR data transfer */ + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE) + { + /* Deactivate sample shifting when receiving data in DTR mode (DDTR=1) */ + CLEAR_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); + } + else if (hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE) + { + /* Configure sample shifting */ + SET_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); + } + else + { + /* Do nothing */ + } + } + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) { if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_dma.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_dma.c index 0c23c2cf1..8aa574e67 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_dma.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_dma.c @@ -875,9 +875,8 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode)); assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection)); } - - /* Check node type */ - if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE) + /* Check non 2D addressing settings */ + if (DMA_InitNodeStruct->NodeType != LL_DMA_LPDMA_LINEAR_NODE) { assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength)); assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength)); @@ -1133,6 +1132,11 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2)); } } + else + { + /* Reset of the CLLR of the node being created */ + pNode->LinkRegisters[reg_counter] = 0U; + } return (uint32_t)SUCCESS; } diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_fmac.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_fmac.c index efc43f584..19e0f767a 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_fmac.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_fmac.c @@ -113,8 +113,6 @@ ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx) return (status); } - - /** * @} */ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_opamp.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_opamp.c index 36072d65e..8e18806e4 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_opamp.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_opamp.c @@ -64,7 +64,7 @@ /* compatibility with other STM32 families. */ #define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__) \ ( ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0) \ - || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH1) \ + || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC) \ ) /* Note: Comparator non-inverting inputs parameters are the same on all */ diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_rng.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_rng.c index 0a2091b53..5f9cf34e7 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_rng.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_rng.c @@ -110,7 +110,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content * - ERROR: not applicable */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_sdmmc.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_sdmmc.c index 2aea608e2..03636ed13 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_sdmmc.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_sdmmc.c @@ -349,7 +349,7 @@ uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx) * the configuration information for the SDMMC command * @retval HAL status */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command) { uint32_t tmpreg = 0; @@ -417,7 +417,7 @@ uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response) * that contains the configuration information for the SDMMC data. * @retval HAL status */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data) +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data) { uint32_t tmpreg = 0; @@ -1849,7 +1849,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) * @param pNodeConf: Pointer to configuration parameters for new node to add. * @retval Error status */ -uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf) +uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, const SDMMC_DMALinkNodeConfTypeDef *pNodeConf) { if ((pNode == NULL) || (pNodeConf == NULL)) diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_tim.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_tim.c index c63a69ed4..12807c281 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_tim.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_tim.c @@ -748,6 +748,8 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ @@ -760,8 +762,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); @@ -815,8 +815,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); @@ -844,8 +842,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); @@ -894,8 +894,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); @@ -923,8 +921,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); @@ -973,8 +973,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); @@ -1002,8 +1000,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); @@ -1052,8 +1052,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); @@ -1081,8 +1079,10 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U); @@ -1357,7 +1357,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_ucpd.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_ucpd.c index 9c537026a..08a52f1ef 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_ucpd.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_ucpd.c @@ -112,7 +112,7 @@ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) * the configuration information for the UCPD peripheral. * @retval An ErrorStatus enumeration value. (Return always SUCCESS) */ -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct) +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct) { /* Check the ucpd Instance UCPDx*/ assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); diff --git a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_usb.c b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_usb.c index 4c841c934..1ffe57c1f 100644 --- a/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_usb.c +++ b/stm32cube/stm32u5xx/drivers/src/stm32u5xx_ll_usb.c @@ -794,17 +794,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef } else { - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); + } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); - } } if (dma == 1U) @@ -2604,6 +2604,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -2708,7 +2712,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -2810,9 +2814,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -2844,19 +2848,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -2865,15 +2875,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -2884,18 +2892,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -2939,26 +2937,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } @@ -3397,7 +3392,14 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, } /* Clear device address, Endpoint number and Low Speed Endpoint fields */ - wChRegVal &= ~(USB_CHEP_DEVADDR | USB_CHEP_ADDR | USB_CHEP_LSEP); + wChRegVal &= ~(USB_CHEP_DEVADDR | + USB_CHEP_ADDR | + USB_CHEP_LSEP | + USB_CHEP_NAK | + USB_CHEP_KIND | + USB_CHEP_ERRTX | + USB_CHEP_ERRRX | + (0xFU << 27)); /* Set device address and Endpoint number associated to the channel */ wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | @@ -3446,6 +3448,18 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) if (hc->doublebuffer == 0U) { + if ((hc->ep_type == EP_TYPE_BULK) || + (hc->ep_type == EP_TYPE_INTR)) + { + USB_DRD_CLEAR_RX_DTOG(USBx, phy_ch_num); + + /* Set Data PID */ + if (hc->data_pid == HC_PID_DATA1) + { + USB_DRD_RX_DTOG(USBx, phy_ch_num); + } + } + /* Set RX buffer count */ USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); } @@ -3503,6 +3517,18 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) { USB_DRD_CHEP_TX_SETUP(USBx, phy_ch_num); } + + if ((hc->ep_type == EP_TYPE_BULK) || + (hc->ep_type == EP_TYPE_INTR)) + { + USB_DRD_CLEAR_TX_DTOG(USBx, phy_ch_num); + + /* Set Data PID */ + if (hc->data_pid == HC_PID_DATA1) + { + USB_DRD_TX_DTOG(USBx, phy_ch_num); + } + } } #if (USE_USB_DOUBLE_BUFFER == 1U) else if (hc->ep_type == EP_TYPE_BULK) diff --git a/stm32cube/stm32u5xx/soc/stm32u535xx.h b/stm32cube/stm32u5xx/soc/stm32u535xx.h index 4c1c81abc..a26269d33 100644 --- a/stm32cube/stm32u5xx/soc/stm32u535xx.h +++ b/stm32cube/stm32u5xx/soc/stm32u535xx.h @@ -216,7 +216,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -4796,6 +4796,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ /* */ @@ -16168,7 +16171,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -20293,7 +20296,7 @@ typedef struct #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -4960,6 +4960,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ /* */ @@ -16720,7 +16723,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -20889,7 +20892,7 @@ typedef struct #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5198,6 +5198,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_NSCR_NIST_VALUE (0x17CBBU) /******************************************************************************/ /* */ @@ -17682,7 +17686,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -20856,9 +20860,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -20894,6 +20916,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -20965,11 +20990,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -20995,11 +21026,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -21040,9 +21074,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -21084,9 +21118,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -21118,6 +21152,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -21136,6 +21173,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -21177,21 +21217,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -21215,9 +21270,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -21251,6 +21306,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -21272,9 +21330,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -21328,12 +21386,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -21372,19 +21433,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -21597,51 +21684,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -21700,7 +21787,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -21709,7 +21795,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -21717,7 +21802,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -21763,9 +21847,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -21805,10 +21889,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -21820,7 +21904,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -21834,19 +21917,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -21950,6 +22030,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -21979,9 +22062,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -22014,9 +22097,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -22025,14 +22108,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -22064,15 +22147,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -22090,6 +22170,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -22104,18 +22190,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -22125,22 +22229,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5411,6 +5411,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_NSCR_NIST_VALUE (0x17CBBU) /******************************************************************************/ /* */ @@ -18292,7 +18296,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -21518,9 +21522,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -21556,6 +21578,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -21627,11 +21652,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -21657,11 +21688,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -21702,9 +21736,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -21746,9 +21780,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -21780,6 +21814,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -21798,6 +21835,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -21839,21 +21879,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -21877,9 +21932,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -21913,6 +21968,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -21934,9 +21992,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -21990,12 +22048,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -22034,19 +22095,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -22259,51 +22346,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -22362,7 +22449,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -22371,7 +22457,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -22379,7 +22464,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -22425,9 +22509,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -22467,10 +22551,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -22482,7 +22566,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -22496,19 +22579,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -22612,6 +22692,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -22641,9 +22724,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -22676,9 +22759,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -22687,14 +22770,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -22726,15 +22809,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -22752,6 +22832,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -22766,18 +22852,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -22787,22 +22891,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5443,6 +5443,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) /******************************************************************************/ /* */ @@ -18792,7 +18796,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -22154,9 +22158,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -22192,6 +22214,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -22263,11 +22288,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -22293,11 +22324,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -22338,9 +22372,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -22382,9 +22416,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -22416,6 +22450,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -22434,6 +22471,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -22475,21 +22515,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -22513,9 +22568,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -22549,6 +22604,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -22570,9 +22628,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -22626,12 +22684,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -22670,19 +22731,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -22875,13 +22962,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -22907,51 +22994,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -23010,7 +23097,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -23019,7 +23105,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -23027,7 +23112,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -23073,9 +23157,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -23115,10 +23199,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -23130,7 +23214,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -23144,19 +23227,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -23260,6 +23340,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -23289,9 +23372,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -23324,9 +23407,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -23335,14 +23418,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -23374,15 +23457,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -23400,6 +23480,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -23414,18 +23500,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -23435,22 +23539,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5731,6 +5731,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) /******************************************************************************/ /* */ @@ -22566,7 +22570,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -25988,9 +25992,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -26026,6 +26048,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -26097,11 +26122,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -26127,11 +26158,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -26172,9 +26206,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -26216,9 +26250,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -26250,6 +26284,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -26268,6 +26305,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -26309,21 +26349,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -26347,9 +26402,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -26383,6 +26438,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -26404,9 +26462,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -26460,12 +26518,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -26504,19 +26565,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -26709,13 +26796,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -26741,51 +26828,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -26844,7 +26931,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -26853,7 +26939,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -26861,7 +26946,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -26907,9 +26991,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -26949,10 +27033,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -26964,7 +27048,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -26978,19 +27061,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -27094,6 +27174,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -27123,9 +27206,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -27158,9 +27241,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -27169,14 +27252,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -27208,15 +27291,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -27234,6 +27314,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -27248,18 +27334,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -27269,22 +27373,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5656,6 +5656,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) /******************************************************************************/ /* */ @@ -19402,7 +19406,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -22816,9 +22820,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -22854,6 +22876,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -22925,11 +22950,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -22955,11 +22986,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -23000,9 +23034,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -23044,9 +23078,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -23078,6 +23112,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -23096,6 +23133,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -23137,21 +23177,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -23175,9 +23230,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -23211,6 +23266,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -23232,9 +23290,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -23288,12 +23346,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -23332,19 +23393,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -23537,13 +23624,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -23569,51 +23656,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -23672,7 +23759,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -23681,7 +23767,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -23689,7 +23774,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -23735,9 +23819,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -23777,10 +23861,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -23792,7 +23876,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -23806,19 +23889,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -23922,6 +24002,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -23951,9 +24034,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -23986,9 +24069,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -23997,14 +24080,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -24036,15 +24119,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -24062,6 +24142,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -24076,18 +24162,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -24097,22 +24201,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5944,6 +5944,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) /******************************************************************************/ /* */ @@ -23176,7 +23180,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -26650,9 +26654,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -26688,6 +26710,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -26759,11 +26784,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -26789,11 +26820,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -26834,9 +26868,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -26878,9 +26912,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -26912,6 +26946,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -26930,6 +26967,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -26971,21 +27011,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -27009,9 +27064,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -27045,6 +27100,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -27066,9 +27124,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -27122,12 +27180,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -27166,19 +27227,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -27371,13 +27458,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -27403,51 +27490,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -27506,7 +27593,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -27515,7 +27601,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -27523,7 +27608,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -27569,9 +27653,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -27611,10 +27695,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -27626,7 +27710,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -27640,19 +27723,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -27756,6 +27836,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -27785,9 +27868,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -27820,9 +27903,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -27831,14 +27914,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -27870,15 +27953,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -27896,6 +27976,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -27910,18 +27996,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -27931,22 +28035,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5739,6 +5739,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) /******************************************************************************/ /* */ @@ -20385,7 +20389,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -23835,9 +23839,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -23873,6 +23895,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -23944,11 +23969,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -23974,11 +24005,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -24019,9 +24053,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -24063,9 +24097,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -24097,6 +24131,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -24115,6 +24152,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -24156,21 +24196,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -24194,9 +24249,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -24230,6 +24285,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -24251,9 +24309,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -24307,12 +24365,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -24351,19 +24412,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -24556,13 +24643,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -24588,51 +24675,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -24691,7 +24778,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -24700,7 +24786,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -24708,7 +24793,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -24754,9 +24838,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -24796,10 +24880,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -24811,7 +24895,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -24825,19 +24908,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -24941,6 +25021,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -24970,9 +25053,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -25005,9 +25088,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -25016,14 +25099,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -25055,15 +25138,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -25081,6 +25161,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -25095,18 +25181,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -25116,22 +25220,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5859,6 +5859,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) /******************************************************************************/ /* */ @@ -23526,7 +23530,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -26988,9 +26992,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -27026,6 +27048,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -27097,11 +27122,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -27127,11 +27158,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -27172,9 +27206,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -27216,9 +27250,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -27250,6 +27284,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -27268,6 +27305,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -27309,21 +27349,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -27347,9 +27402,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -27383,6 +27438,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -27404,9 +27462,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -27460,12 +27518,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -27504,19 +27565,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -27709,13 +27796,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -27741,51 +27828,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -27844,7 +27931,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -27853,7 +27939,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -27861,7 +27946,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -27907,9 +27991,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -27949,10 +28033,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -27964,7 +28048,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -27978,19 +28061,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -28094,6 +28174,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -28123,9 +28206,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -28158,9 +28241,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -28169,14 +28252,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -28208,15 +28291,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -28234,6 +28314,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -28248,18 +28334,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -28269,22 +28373,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5952,6 +5952,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) /******************************************************************************/ /* */ @@ -20995,7 +20999,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -24497,9 +24501,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -24535,6 +24557,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -24606,11 +24631,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -24636,11 +24667,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -24681,9 +24715,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -24725,9 +24759,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -24759,6 +24793,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -24777,6 +24814,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -24818,21 +24858,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -24856,9 +24911,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -24892,6 +24947,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -24913,9 +24971,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -24969,12 +25027,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -25013,19 +25074,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -25218,13 +25305,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -25250,51 +25337,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -25353,7 +25440,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -25362,7 +25448,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -25370,7 +25455,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -25416,9 +25500,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -25458,10 +25542,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -25473,7 +25557,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -25487,19 +25570,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -25603,6 +25683,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -25632,9 +25715,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -25667,9 +25750,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -25678,14 +25761,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -25717,15 +25800,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -25743,6 +25823,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -25757,18 +25843,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -25778,22 +25882,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -6072,6 +6072,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) /******************************************************************************/ /* */ @@ -24136,7 +24140,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -27650,9 +27654,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -27688,6 +27710,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -27759,11 +27784,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -27789,11 +27820,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -27834,9 +27868,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -27878,9 +27912,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -27912,6 +27946,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -27930,6 +27967,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -27971,21 +28011,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -28009,9 +28064,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -28045,6 +28100,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -28066,9 +28124,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -28122,12 +28180,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -28166,19 +28227,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -28371,13 +28458,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -28403,51 +28490,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -28506,7 +28593,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -28515,7 +28601,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -28523,7 +28608,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -28569,9 +28653,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -28611,10 +28695,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -28626,7 +28710,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -28640,19 +28723,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -28756,6 +28836,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -28785,9 +28868,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -28820,9 +28903,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -28831,14 +28914,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -28870,15 +28953,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -28896,6 +28976,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -28910,18 +28996,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -28931,22 +29035,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!