diff --git a/stm32cube/stm32mp13xx/CMakeLists.txt b/stm32cube/stm32mp13xx/CMakeLists.txt index 93e651284..91a1160e0 100644 --- a/stm32cube/stm32mp13xx/CMakeLists.txt +++ b/stm32cube/stm32mp13xx/CMakeLists.txt @@ -8,35 +8,44 @@ zephyr_library_sources(drivers/src/stm32mp13xx_hal_rcc.c) zephyr_library_sources(drivers/src/stm32mp13xx_hal_rcc_ex.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_ADC drivers/src/stm32mp13xx_hal_adc.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_ADC_EX drivers/src/stm32mp13xx_hal_adc_ex.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_CEC drivers/src/stm32mp13xx_hal_cec.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_CORTEX drivers/src/stm32mp13xx_hal_cortex.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_BSEC drivers/src/stm32mp13xx_hal_bsec.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_CRC drivers/src/stm32mp13xx_hal_crc.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_CRC_EX drivers/src/stm32mp13xx_hal_crc_ex.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_CRYP drivers/src/stm32mp13xx_hal_cryp.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_CRYP_EX drivers/src/stm32mp13xx_hal_cryp_ex.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DAC drivers/src/stm32mp13xx_hal_dac.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DAC_EX drivers/src/stm32mp13xx_hal_dac_ex.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DCMI drivers/src/stm32mp13xx_hal_dcmi.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DCMIPP drivers/src/stm32mp13xx_hal_dcmipp.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DDR drivers/src/stm32mp13xx_hal_ddr.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DFSDM drivers/src/stm32mp13xx_hal_dfsdm.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DFSDM_EX drivers/src/stm32mp13xx_hal_dfsdm_ex.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DMA drivers/src/stm32mp13xx_hal_dma.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DMA_EX drivers/src/stm32mp13xx_hal_dma_ex.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DTS drivers/src/stm32mp13xx_hal_dts.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_ETH drivers/src/stm32mp13xx_hal_eth.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_ETH_EX drivers/src/stm32mp13xx_hal_eth_ex.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_EXTI drivers/src/stm32mp13xx_hal_exti.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_FDCAN drivers/src/stm32mp13xx_hal_fdcan.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_GPIO drivers/src/stm32mp13xx_hal_gpio.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_HASH drivers/src/stm32mp13xx_hal_hash.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_HASH_EX drivers/src/stm32mp13xx_hal_hash_ex.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_HSEM drivers/src/stm32mp13xx_hal_hsem.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_HCD drivers/src/stm32mp13xx_hal_hcd.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I2C drivers/src/stm32mp13xx_hal_i2c.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I2C_EX drivers/src/stm32mp13xx_hal_i2c_ex.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_IPCC drivers/src/stm32mp13xx_hal_ipcc.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I2S drivers/src/stm32mp13xx_hal_i2s.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_IWDG drivers/src/stm32mp13xx_hal_iwdg.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_LPTIM drivers/src/stm32mp13xx_hal_lptim.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_MDIOS drivers/src/stm32mp13xx_hal_mdios.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_LTDC drivers/src/stm32mp13xx_hal_ltdc.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_MCE drivers/src/stm32mp13xx_hal_mce.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_MDMA drivers/src/stm32mp13xx_hal_mdma.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_MMC drivers/src/stm32mp13xx_hal_mmc.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_MMC_EX drivers/src/stm32mp13xx_hal_mmc_ex.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_NAND drivers/src/stm32mp13xx_hal_nand.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PCD drivers/src/stm32mp13xx_hal_pcd.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PCD_EX drivers/src/stm32mp13xx_hal_pcd_ex.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PKA drivers/src/stm32mp13xx_hal_pka.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PWR drivers/src/stm32mp13xx_hal_pwr.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PWR_EX drivers/src/stm32mp13xx_hal_pwr_ex.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_QSPI drivers/src/stm32mp13xx_hal_qspi.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RNG drivers/src/stm32mp13xx_hal_rng.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RNG_EX drivers/src/stm32mp13xx_hal_rng_ex.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RTC drivers/src/stm32mp13xx_hal_rtc.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RTC_EX drivers/src/stm32mp13xx_hal_rtc_ex.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SAI drivers/src/stm32mp13xx_hal_sai.c) @@ -57,7 +66,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_UART drivers/src/stm32mp13xx_h zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_UART_EX drivers/src/stm32mp13xx_hal_uart_ex.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_USART drivers/src/stm32mp13xx_hal_usart.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_USART_EX drivers/src/stm32mp13xx_hal_usart_ex.c) -zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_WWDG drivers/src/stm32mp13xx_hal_wwdg.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_XSPI drivers/src/stm32mp13xx_hal_xspi.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_ADC drivers/src/stm32mp13xx_ll_adc.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_DELAYBLOCK drivers/src/stm32mp13xx_ll_delayblock.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_DMA drivers/src/stm32mp13xx_ll_dma.c) @@ -66,6 +75,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_FMC drivers/src/stm32mp13xx_ll_ zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_GPIO drivers/src/stm32mp13xx_ll_gpio.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_I2C drivers/src/stm32mp13xx_ll_i2c.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_LPTIM drivers/src/stm32mp13xx_ll_lptim.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_MDMA drivers/src/stm32mp13xx_ll_mdma.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_PWR drivers/src/stm32mp13xx_ll_pwr.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_RCC drivers/src/stm32mp13xx_ll_rcc.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_RTC drivers/src/stm32mp13xx_ll_rtc.c) @@ -73,3 +83,4 @@ zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_SDMMC drivers/src/stm32mp13xx_l zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_SPI drivers/src/stm32mp13xx_ll_spi.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_TIM drivers/src/stm32mp13xx_ll_tim.c) zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_USART drivers/src/stm32mp13xx_ll_usart.c) +zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_USB drivers/src/stm32mp13xx_ll_usb.c) diff --git a/stm32cube/stm32mp13xx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32mp13xx/drivers/include/Legacy/stm32_hal_legacy.h index aecfb0ed7..bd903607d 100644 --- a/stm32cube/stm32mp13xx/drivers/include/Legacy/stm32_hal_legacy.h +++ b/stm32cube/stm32mp13xx/drivers/include/Legacy/stm32_hal_legacy.h @@ -139,7 +139,7 @@ extern "C" { #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR @@ -241,9 +241,9 @@ extern "C" { */ #if defined(STM32H5) || defined(STM32C0) #else -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ #endif /** @@ -1558,35 +1558,35 @@ extern "C" { #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ #endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ @@ -2454,9 +2454,9 @@ extern "C" { /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ /** * @} diff --git a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_adc_ex.h b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_adc_ex.h index 2fd2c9629..a1e3cccdc 100644 --- a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_adc_ex.h +++ b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_adc_ex.h @@ -758,7 +758,16 @@ typedef struct * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ +#if defined(ADC1) & !defined(ADC2) +#define ADC_VREFINT_INSTANCE(__HANDLE__) ((__HANDLE__)->Instance == ADC1) +#endif +#if defined(ADC2) & !defined(ADC1) +#define ADC_VREFINT_INSTANCE(__HANDLE__) ((__HANDLE__)->Instance == ADC2) +#endif +#if defined(ADC1) & defined(ADC2) #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) +#endif + /** * @brief Verify the ADC instance connected to the internal voltage reference VDDCORE. * @param __HANDLE__ ADC handle. diff --git a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_conf.h b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_conf.h index 3d85ff536..1beffca41 100644 --- a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_conf.h +++ b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_conf.h @@ -2,26 +2,27 @@ ****************************************************************************** * @file stm32mp13xx_hal_conf.h * @author MCD Application Team - * @brief HAL configuration file. + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32mp13xx_hal_conf.h. ****************************************************************************** * @attention * - * Copyright (c) 2019 STMicroelectronics. + * Copyright (c) 2020 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * - ****************************************************************************** - */ + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32MP13xx_HAL_CONF_H #define STM32MP13xx_HAL_CONF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -33,25 +34,30 @@ */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED -// #define HAL_CEC_MODULE_ENABLED -// #define HAL_CORTEX_MODULE_ENABLED +#define HAL_BSEC_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED #define HAL_CRYP_MODULE_ENABLED -// #define HAL_DAC_MODULE_ENABLED -// #define HAL_DCMI_MODULE_ENABLED +#define HAL_DCMIPP_MODULE_ENABLED +#define HAL_DDR_MODULE_ENABLED #define HAL_DFSDM_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED +#define HAL_DTS_MODULE_ENABLED +#define HAL_ETH_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED #define HAL_FDCAN_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED #define HAL_HASH_MODULE_ENABLED -// #define HAL_HSEM_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED -// #define HAL_IPCC_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED #define HAL_LPTIM_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_MCE_MODULE_ENABLED #define HAL_MDMA_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_PKA_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED -// #define HAL_QSPI_MODULE_ENABLED +#define HAL_XSPI_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED #define HAL_RNG_MODULE_ENABLED #define HAL_RTC_MODULE_ENABLED @@ -59,28 +65,40 @@ #define HAL_SD_MODULE_ENABLED #define HAL_SMARTCARD_MODULE_ENABLED #define HAL_SMBUS_MODULE_ENABLED -#define HAL_SPDIFRX_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED -#define HAL_SRAM_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED #define HAL_USART_MODULE_ENABLED -// #define HAL_WWDG_MODULE_ENABLED /* ########################## Register Callbacks selection ############################## */ /** * @brief This is the list of modules where register callback can be used */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0u -#define USE_HAL_CEC_REGISTER_CALLBACKS 0u -#define USE_HAL_DAC_REGISTER_CALLBACKS 0u -#define USE_HAL_I2C_REGISTER_CALLBACKS 0u -#define USE_HAL_RNG_REGISTER_CALLBACKS 0u -#define USE_HAL_SPI_REGISTER_CALLBACKS 0u -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U -#define USE_HAL_UART_REGISTER_CALLBACKS 0u -#define USE_HAL_USART_REGISTER_CALLBACKS 0u -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* ################## SPI peripheral configuration ########################## */ @@ -88,7 +106,7 @@ * Activated: CRC code is present inside driver * Deactivated: CRC code cleaned from driver */ -#define USE_SPI_CRC 1U +#define USE_SPI_CRC 1U /* ######################### Oscillator Values adaptation ################### */ /** @@ -97,7 +115,7 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ +#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ /** @@ -105,7 +123,7 @@ * Timeout value */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -114,7 +132,7 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE 64000000U /*!< Value of the Internal oscillator in Hz*/ +#define HSI_VALUE 64000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -122,7 +140,7 @@ * Timeout value */ #if !defined (HSI_STARTUP_TIMEOUT) - #define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */ +#define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */ #endif /* HSI_STARTUP_TIMEOUT */ @@ -130,22 +148,27 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE 32000U +#define LSI_VALUE 32000U #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ +The real value may vary depending on the variations +in voltage and temperature. */ + +#if !defined (LSI_STARTUP_TIME) +#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in ms */ +#endif /* LSI_STARTUP_TIME */ + /** * @brief External Low Speed oscillator (LSE) value. */ #if !defined (LSE_VALUE) - #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ +#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ /** * @brief Time out for LSE start up value in ms. */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ /** @@ -153,7 +176,7 @@ * This value is the default CSI value after Reset. */ #if !defined (CSI_VALUE) - #define CSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#define CSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* CSI_VALUE */ /** @@ -162,7 +185,7 @@ * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/ +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -174,8 +197,8 @@ */ #define VDD_VALUE 3300U /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY ((uint32_t)(1U<<4U) - 1U) /*!< tick interrupt priority (lowest by default) */ - /* Warning: Must be set to higher priority for HAL_Delay() */ - /* and HAL_GetTick() usage under interrupt context */ +/* Warning: Must be set to higher priority for HAL_Delay() */ +/* and HAL_GetTick() usage under interrupt context */ #define USE_RTOS 0U #define PREFETCH_ENABLE 0U #define INSTRUCTION_CACHE_ENABLE 0U @@ -194,137 +217,149 @@ */ #ifdef HAL_RCC_MODULE_ENABLED - #include "stm32mp13xx_hal_rcc.h" +#include "stm32mp13xx_hal_rcc.h" #endif /* HAL_RCC_MODULE_ENABLED */ -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32mp13xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_HSEM_MODULE_ENABLED - #include "stm32mp13xx_hal_hsem.h" -#endif /* HAL_HSEM_MODULE_ENABLED */ - #ifdef HAL_DMA_MODULE_ENABLED - #include "stm32mp13xx_hal_dma.h" +#include "stm32mp13xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ #ifdef HAL_MDMA_MODULE_ENABLED - #include "stm32mp13xx_hal_mdma.h" +#include "stm32mp13xx_hal_mdma.h" #endif /* HAL_MDMA_MODULE_ENABLED */ -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32mp13xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - #ifdef HAL_ADC_MODULE_ENABLED - #include "stm32mp13xx_hal_adc.h" +#include "stm32mp13xx_hal_adc.h" #endif /* HAL_ADC_MODULE_ENABLED */ -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32mp13xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ +#ifdef HAL_BSEC_MODULE_ENABLED +#include "stm32mp13xx_hal_bsec.h" +#endif /* HAL_BSEC_MODULE_ENABLED */ #ifdef HAL_CRC_MODULE_ENABLED - #include "stm32mp13xx_hal_crc.h" +#include "stm32mp13xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32mp13xx_hal_cryp.h" +#include "stm32mp13xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32mp13xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ +#ifdef HAL_DCMIPP_MODULE_ENABLED +#include "stm32mp13xx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32mp13xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ +#ifdef HAL_DDR_MODULE_ENABLED +#include "stm32mp13xx_hal_ddr.h" +#endif /* HAL_DDR_MODULE_ENABLED */ #ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32mp13xx_hal_dfsdm.h" +#include "stm32mp13xx_hal_dfsdm.h" #endif /* HAL_DFSDM_MODULE_ENABLED */ +#ifdef HAL_DTS_MODULE_ENABLED +#include "stm32mp13xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED +#include "stm32mp13xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32mp13xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + #ifdef HAL_FDCAN_MODULE_ENABLED - #include "stm32mp13xx_hal_fdcan.h" +#include "stm32mp13xx_hal_fdcan.h" #endif /* HAL_FDCAN_MODULE_ENABLED */ +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32mp13xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + #ifdef HAL_HASH_MODULE_ENABLED - #include "stm32mp13xx_hal_hash.h" +#include "stm32mp13xx_hal_hash.h" #endif /* HAL_HASH_MODULE_ENABLED */ +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32mp13xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + #ifdef HAL_I2C_MODULE_ENABLED - #include "stm32mp13xx_hal_i2c.h" +#include "stm32mp13xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ -#ifdef HAL_IPCC_MODULE_ENABLED - #include "stm32mp13xx_hal_ipcc.h" -#endif /* HAL_IPCC_MODULE_ENABLED */ +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32mp13xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32mp13xx_hal_lptim.h" +#include "stm32mp13xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32mp13xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED +#include "stm32mp13xx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32mp13xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32mp13xx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + #ifdef HAL_PWR_MODULE_ENABLED - #include "stm32mp13xx_hal_pwr.h" +#include "stm32mp13xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32mp13xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32mp13xx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ #ifdef HAL_RNG_MODULE_ENABLED - #include "stm32mp13xx_hal_rng.h" +#include "stm32mp13xx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ #ifdef HAL_RTC_MODULE_ENABLED - #include "stm32mp13xx_hal_rtc.h" +#include "stm32mp13xx_hal_rtc.h" #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_SAI_MODULE_ENABLED - #include "stm32mp13xx_hal_sai.h" +#include "stm32mp13xx_hal_sai.h" #endif /* HAL_SAI_MODULE_ENABLED */ #ifdef HAL_SD_MODULE_ENABLED - #include "stm32mp13xx_hal_sd.h" +#include "stm32mp13xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ #ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32mp13xx_hal_smartcard.h" +#include "stm32mp13xx_hal_smartcard.h" #endif /* HAL_SMARTCARD_MODULE_ENABLED */ #ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32mp13xx_hal_smbus.h" +#include "stm32mp13xx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32mp13xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - #ifdef HAL_SPI_MODULE_ENABLED - #include "stm32mp13xx_hal_spi.h" +#include "stm32mp13xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32mp13xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - #ifdef HAL_TIM_MODULE_ENABLED - #include "stm32mp13xx_hal_tim.h" +#include "stm32mp13xx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ #ifdef HAL_UART_MODULE_ENABLED - #include "stm32mp13xx_hal_uart.h" +#include "stm32mp13xx_hal_uart.h" #endif /* HAL_UART_MODULE_ENABLED */ #ifdef HAL_USART_MODULE_ENABLED - #include "stm32mp13xx_hal_usart.h" +#include "stm32mp13xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32mp13xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** @@ -335,11 +370,11 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); +void assert_failed(uint8_t *file, uint32_t line); #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ #ifdef __cplusplus diff --git a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_cryp.h b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_cryp.h index 2770a24ab..17dbed094 100644 --- a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_cryp.h +++ b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_cryp.h @@ -420,7 +420,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point #define CRYP_FLAG_WRERR (SAES_SR_WRERR | 0x80000000U) /*!< SAES peripheral Write Error flag */ #define CRYP_FLAG_RDERR (SAES_SR_RDERR | 0x80000000U) /*!< SAES peripheral Read error flag */ -#define CRYP_FLAG_CCF SAES_SR_CCF /*!< SAES peripheral Computation completed flag +#define CRYP_FLAG_CCF SAES_SR_CCF /*!< SAES peripheral Computation completed flag as AES_ISR_CCF */ #define CRYP_FLAG_KEIF SAES_ISR_KEIF /*!< SAES peripheral Key error interrupt flag */ #define CRYP_FLAG_RWEIF SAES_ISR_RWEIF /*!< SAES peripheral Read or Write error Interrupt flag */ @@ -447,7 +447,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @{ */ -#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration +#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */ #define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */ @@ -462,7 +462,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point */ #define CRYP_KEYMODE_NORMAL 0x00000000U /*!< Normal key usage, Key registers are freely usable */ -#define CRYP_KEYMODE_WRAPPED SAES_CR_KMOD_0 /*!< Only for SAES, Wrapped key: to encrypt +#define CRYP_KEYMODE_WRAPPED SAES_CR_KMOD_0 /*!< Only for SAES, Wrapped key: to encrypt or decrypt AES keys */ #define CRYP_KEYMODE_SHARED SAES_CR_KMOD_1 /*!< Key shared by SAES peripheral */ /** @@ -474,16 +474,16 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point */ #define CRYP_KEYSEL_NORMAL 0x00000000U /*!< Normal key, key registers SAES_KEYx or CRYP_KEYx */ -#define CRYP_KEYSEL_HW SAES_CR_KEYSEL_0 /*!< Only for SAES, Hardware key : derived hardware +#define CRYP_KEYSEL_HW SAES_CR_KEYSEL_0 /*!< Only for SAES, Hardware key : derived hardware unique key (DHUK 256-bit) */ -#define CRYP_KEYSEL_SW SAES_CR_KEYSEL_1 /*!< Only for SAES, Software key : boot hardware +#define CRYP_KEYSEL_SW SAES_CR_KEYSEL_1 /*!< Only for SAES, Software key : boot hardware key BHK (256-bit) */ -#define CRYP_KEYSEL_HSW SAES_CR_KEYSEL_2 /*!< Only for SAES, DHUK XOR BHK Hardware unique +#define CRYP_KEYSEL_HSW SAES_CR_KEYSEL_2 /*!< Only for SAES, DHUK XOR BHK Hardware unique key XOR software key */ -#define CRYP_KEYSEL_AHK (SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0) /*!< Only for SAES, Software key : +#define CRYP_KEYSEL_AHK (SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0) /*!< Only for SAES, Software key : application hardware key AHK (128- or 256-bit) */ #define CRYP_KEYSEL_DUK_AHK (SAES_CR_KEYSEL_2|SAES_CR_KEYSEL_0) /*!< Only for SAES, DHUK XOR AHK */ -#define CRYP_KEYSEL_TEST_KEY (SAES_CR_KEYSEL_2|SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0) /*!< Test mode key (256-bit +#define CRYP_KEYSEL_TEST_KEY (SAES_CR_KEYSEL_2|SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0) /*!< Test mode key (256-bit hardware constant key 0xA5A5...A5A5) */ /** * @} @@ -494,9 +494,9 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @{ */ -#define CRYP_KEYPROT_ENABLE SAES_CR_KEYPROT /*!< Only for SAES, Key can't be shared between +#define CRYP_KEYPROT_ENABLE SAES_CR_KEYPROT /*!< Only for SAES, Key can't be shared between two applications with different security contexts */ -#define CRYP_KEYPROT_DISABLE 0x00000000U /*!< Only for SAES, Key can be shared between +#define CRYP_KEYPROT_DISABLE 0x00000000U /*!< Only for SAES, Key can be shared between two applications with different security contexts */ /** diff --git a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_eth.h b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_eth.h index e852f6f63..93d875187 100644 --- a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_eth.h +++ b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_eth.h @@ -105,7 +105,7 @@ typedef struct uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*TIMG2PRER & RCC_TIMG2PRER_TIMG2PRERDY) == RCC_TIMG2PRER_TIMG2PRERDY ) +/* Flags in the TIMG3PRER register */ +#define RCC_FLAG_TIMG3PRERDY ( (RCC->TIMG3PRER & RCC_TIMG3PRER_TIMG3PRERDY) == RCC_TIMG3PRER_TIMG3PRERDY ) + /* Flags in the MPCKDIVR register */ #define RCC_FLAG_MPUDIVRDY ( (RCC->MPCKDIVR & RCC_MPCKDIVR_MPUDIVRDY) == RCC_MPCKDIVR_MPUDIVRDY ) @@ -2095,8 +2095,6 @@ typedef struct #define __HAL_RCC_SYS_RESET() (RCC->MP_GRSTCSETR = RCC_MP_GRSTCSETR_MPSYSRST) - - /** @brief Enable or disable the APB1 peripheral clock during CSLEEP mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. @@ -2954,8 +2952,6 @@ typedef struct #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION) - - /** @brief Macro to configure the Minimum Reset Duration * @note Set and reset by software. They define the minimum guaranteed * duration of the NRST low pulse. The LSI oscillator is automatically @@ -2973,7 +2969,6 @@ typedef struct } while(0) - /** * @brief Macro (deprecated) to configure the External High Speed oscillator (HSE). * @note Macro name is kept to maintain compatibility and it is mapped on @@ -3154,7 +3149,6 @@ typedef struct #define __HAL_RCC_PLL1FRACV_DISABLE() CLEAR_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACLE) - /** * @brief Macro to configure PLL1 and PLL2 clock source * @note This function must be used only when the PLLs are disabled. @@ -3208,7 +3202,6 @@ typedef struct } while(0) - /** * @brief Macro to configure the PLL1 clock Fractional Part Of The Multiplication Factor * @@ -3269,7 +3262,6 @@ do{ MODIFY_REG( RCC->PLL1CSGR, (RCC_PLL1CSGR_MOD_PER | RCC_PLL1CSGR_TPDFN_DIS | }while (0) - /** @brief Macros to enable or disable the PLL2. * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can diff --git a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_rcc_ex.h b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_rcc_ex.h index ce4ab2094..508f47030 100644 --- a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_rcc_ex.h +++ b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_rcc_ex.h @@ -214,6 +214,11 @@ typedef struct This parameter can be a value of @ref RCCEx_TIMG2_Prescaler_Selection */ + uint32_t TIMG3PresSelection; /*!< Specifies TIM Group 3 Clock Prescalers + Selection. + This parameter can be a value of @ref + RCCEx_TIMG3_Prescaler_Selection */ + uint32_t RTCClockSelection; /*!< Specifies RTC clock source This parameter can be a value of @ref RCC_RTC_Clock_Source */ @@ -235,7 +240,7 @@ typedef struct /** @defgroup RCCEx_Periph_Clock_Selection RCCEx_Periph_Clock_Selection * @{ */ -#define RCC_PERIPHCLK_I2C12 ((uint64_t)0x00000001) +#define RCC_PERIPHCLK_I2C12 ((uint64_t)0x00000001U) #define RCC_PERIPHCLK_I2C3 ((uint64_t)0x00000002U) #define RCC_PERIPHCLK_I2C4 ((uint64_t)0x00000004U) #define RCC_PERIPHCLK_I2C5 ((uint64_t)0x00000008U) @@ -273,8 +278,9 @@ typedef struct #define RCC_PERIPHCLK_SAES ((uint64_t)0x800000000U) #define RCC_PERIPHCLK_TIMG1 ((uint64_t)0x1000000000U) #define RCC_PERIPHCLK_TIMG2 ((uint64_t)0x2000000000U) -#define RCC_PERIPHCLK_RTC ((uint64_t)0x4000000000U) -#define RCC_PERIPHCLK_CKPER ((uint64_t)0x8000000000U) +#define RCC_PERIPHCLK_TIMG3 ((uint64_t)0x4000000000U) +#define RCC_PERIPHCLK_RTC ((uint64_t)0x8000000000U) +#define RCC_PERIPHCLK_CKPER ((uint64_t)0x10000000000U) #define IS_RCC_PERIPHCLOCK(SELECTION) \ ((((SELECTION) & RCC_PERIPHCLK_I2C12) == RCC_PERIPHCLK_I2C12) || \ @@ -315,6 +321,7 @@ typedef struct (((SELECTION) & RCC_PERIPHCLK_SAES) == RCC_PERIPHCLK_SAES) || \ (((SELECTION) & RCC_PERIPHCLK_TIMG1) == RCC_PERIPHCLK_TIMG1) || \ (((SELECTION) & RCC_PERIPHCLK_TIMG2) == RCC_PERIPHCLK_TIMG2) || \ + (((SELECTION) & RCC_PERIPHCLK_TIMG3) == RCC_PERIPHCLK_TIMG3) || \ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ (((SELECTION) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)) @@ -337,14 +344,14 @@ typedef struct #define RCC_PERIPHCLK_TIM5 RCC_PERIPHCLK_TIMG1 #define RCC_PERIPHCLK_TIM6 RCC_PERIPHCLK_TIMG1 #define RCC_PERIPHCLK_TIM7 RCC_PERIPHCLK_TIMG1 -#define RCC_PERIPHCLK_TIM12 RCC_PERIPHCLK_TIMG1 -#define RCC_PERIPHCLK_TIM13 RCC_PERIPHCLK_TIMG1 -#define RCC_PERIPHCLK_TIM14 RCC_PERIPHCLK_TIMG1 +#define RCC_PERIPHCLK_TIM12 RCC_PERIPHCLK_TIMG3 +#define RCC_PERIPHCLK_TIM13 RCC_PERIPHCLK_TIMG3 +#define RCC_PERIPHCLK_TIM14 RCC_PERIPHCLK_TIMG3 #define RCC_PERIPHCLK_TIM1 RCC_PERIPHCLK_TIMG2 #define RCC_PERIPHCLK_TIM8 RCC_PERIPHCLK_TIMG2 -#define RCC_PERIPHCLK_TIM15 RCC_PERIPHCLK_TIMG2 -#define RCC_PERIPHCLK_TIM16 RCC_PERIPHCLK_TIMG2 -#define RCC_PERIPHCLK_TIM17 RCC_PERIPHCLK_TIMG2 +#define RCC_PERIPHCLK_TIM15 RCC_PERIPHCLK_TIMG3 +#define RCC_PERIPHCLK_TIM16 RCC_PERIPHCLK_TIMG3 +#define RCC_PERIPHCLK_TIM17 RCC_PERIPHCLK_TIMG3 #define IS_RCC_PERIPHONECLOCK(PERIPH) \ ((((PERIPH) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ @@ -354,7 +361,8 @@ typedef struct (((PERIPH) & RCC_PERIPHCLK_IWDG2) == RCC_PERIPHCLK_IWDG2) || \ (((PERIPH) & RCC_PERIPHCLK_DDRPHYC) == RCC_PERIPHCLK_DDRPHYC) || \ (((PERIPH) & RCC_PERIPHCLK_TIMG1) == RCC_PERIPHCLK_TIMG1) || \ - (((PERIPH) & RCC_PERIPHCLK_TIMG2) == RCC_PERIPHCLK_TIMG2)) + (((PERIPH) & RCC_PERIPHCLK_TIMG2) == RCC_PERIPHCLK_TIMG2) || \ + (((PERIPH) & RCC_PERIPHCLK_TIMG3) == RCC_PERIPHCLK_TIMG3)) /** * @} @@ -872,7 +880,6 @@ typedef struct #define RCC_FDCANCLKSOURCE_PLL4_R (RCC_FDCANCKSELR_FDCANSRC_1 | RCC_FDCANCKSELR_FDCANSRC_0) - #define IS_RCC_FDCANCLKSOURCE(SOURCE) \ (((SOURCE) == RCC_FDCANCLKSOURCE_HSE) || \ ((SOURCE) == RCC_FDCANCLKSOURCE_PLL3) || \ @@ -1146,7 +1153,6 @@ typedef struct #define RCC_LPTIM45CLKSOURCE_OFF (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_1) - #define IS_RCC_LPTIM45CLKSOURCE(SOURCE) \ (((SOURCE) == RCC_LPTIM45CLKSOURCE_PCLK3) || \ ((SOURCE) == RCC_LPTIM45CLKSOURCE_PLL4) || \ @@ -1185,6 +1191,18 @@ typedef struct * @} */ +/** @defgroup RCCEx_TIMG3_Prescaler_Selection TIMG3 Prescaler Selection + * @{ + */ +#define RCC_TIMG3PRES_DEACTIVATED 0U +#define RCC_TIMG3PRES_ACTIVATED RCC_TIMG3PRER_TIMG3PRE + +#define IS_RCC_TIMG3PRES(PRES) (((PRES) == RCC_TIMG3PRES_DEACTIVATED) || \ + ((PRES) == RCC_TIMG3PRES_ACTIVATED)) +/** + * @} + */ + /** * @} */ @@ -2140,11 +2158,10 @@ typedef struct #define __HAL_RCC_GET_LPTIM45_SOURCE() ((uint32_t)(READ_BIT(RCC->LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC))) - /** * @brief Macro to set the APB1 timer clock prescaler * @note Set and reset by software to control the clock frequency of all the timers connected to APB1 domain. - * It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. + * It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7. * @param __RCC_TIMG1PRES__: specifies the Timers clocks prescaler selection * This parameter can be one of the following values: * @arg RCC_TIMG1PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk @@ -2173,7 +2190,7 @@ typedef struct /** * @brief Macro to set the APB2 timers clocks prescaler * @note Set and reset by software to control the clock frequency of all the timers connected to APB2 domain. - * It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. + * It concerns TIM1 and TIM8. * @param __RCC_TIMG2PRES__: specifies the timers clocks prescaler selection * This parameter can be one of the following values: * @arg RCC_TIMG2PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if @@ -2198,7 +2215,33 @@ typedef struct */ #define __HAL_RCC_GET_TIMG2PRES() ((uint32_t)(RCC->TIMG2PRER & RCC_TIMG2PRER_TIMG2PRE)) +/** + * @brief Macro to set the APB6 timers clocks prescaler + * @note Set and reset by software to control the clock frequency of all the timers connected to APB6 domain. + * It concerns TIM12, TIM13, TIM14, TIM15, TIM16, and TIM17. + * @param __RCC_TIMG3PRES__: specifies the timers clocks prescaler selection + * This parameter can be one of the following values: + * @arg RCC_TIMG3PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if + * APB6DIV is corresponding to a division by 1 or 2, else + * it is equal to 2 x Fck_pclk2 (default after reset) + * @arg RCC_TIMG3PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB6DIV is + * correspondingto division by 1, 2 or 4, else + * it is equal to 4 x Fck_pclk1 + */ +#define __HAL_RCC_TIMG3PRES(__RCC_TIMG3PRES__) \ + do{ MODIFY_REG( RCC->TIMG3PRER, RCC_TIMG3PRER_TIMG3PRE , __RCC_TIMG3PRES__ );\ + } while(0) +/** @brief Macro to get the APB6 timer clock prescaler. + * @retval The APB6 timer clock prescaler. The returned value can be one + * of the following: + * - RCC_TIMG3PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB6DIV is corresponding + * to a division by 1 or 2, else it is equal to + * 2 x Fck_pclk1 (default after reset) + * - RCC_TIMG3PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB6DIV is corresponding + * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1 + */ +#define __HAL_RCC_GET_TIMG3PRES() ((uint32_t)(RCC->TIMG3PRER & RCC_TIMG3PRER_TIMG3PRE)) #define USB_PHY_VALUE ((uint32_t)48000000U) /*!< Value of the USB_PHY_VALUE signal in Hz It is equal to rcc_hsphy_CLK_48M which is diff --git a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_rtc_ex.h b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_rtc_ex.h index 9ee77924f..b9a35bd78 100644 --- a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_rtc_ex.h +++ b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_rtc_ex.h @@ -1851,7 +1851,7 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_Privil ((__STATE__) == TAMP_MONOTONIC_CNT2_YES) || \ ((__STATE__) == TAMP_MONOTONIC_CNT2_NO) || \ ((__STATE__) == TAMP_MONOTONIC_CNT1_NO)) - + #define IS_RTC_SECURE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_SECURE_FEATURE_ALL) == 0U) /** diff --git a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_tim_ex.h b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_tim_ex.h index 1e930e463..3472c0b11 100644 --- a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_tim_ex.h +++ b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_hal_tim_ex.h @@ -86,7 +86,7 @@ typedef struct /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ -#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is +#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ #define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ diff --git a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_ll_adc.h b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_ll_adc.h index b72bb6a74..e6a6a2db7 100644 --- a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_ll_adc.h +++ b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_ll_adc.h @@ -1967,8 +1967,15 @@ typedef struct * @param __ADCx__ ADC instance * @retval ADC common register instance */ +#if defined(ADC1) & !defined(ADC2) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) ADC1_COMMON +#endif +#if !defined(ADC1) & defined(ADC2) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) ADC2_COMMON +#endif +#if defined(ADC1) & defined(ADC2) #define __LL_ADC_COMMON_INSTANCE(__ADCx__)((((__ADCx__) == ADC1))? ((ADC1_COMMON)):((ADC2_COMMON))) - +#endif /** * @brief Helper macro to check if all ADC instances sharing the same * ADC common instance are disabled. @@ -1986,9 +1993,19 @@ typedef struct * Value "1" if at least one ADC instance sharing the same ADC common instance * is enabled. */ +#if !defined (ADC1) & defined(ADC2) #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - (LL_ADC_IsEnabled(ADC1) | \ - LL_ADC_IsEnabled(ADC2) ) + (LL_ADC_IsEnabled(ADC2) ) +#endif +#if defined (ADC1) & !defined(ADC2) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1) ) +#endif +#if defined (ADC1) & defined(ADC2) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1) | \ + LL_ADC_IsEnabled(ADC2) ) +#endif /** * @brief Helper macro to define the ADC conversion data full-scale digital diff --git a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_ll_rcc.h b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_ll_rcc.h index 6f91309ec..291045fec 100644 --- a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_ll_rcc.h +++ b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_ll_rcc.h @@ -4132,7 +4132,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) * @brief Configure TIMGx prescaler selection * @rmtoll TIMG1PRER TIMG1PRE LL_RCC_SetTIMGPrescaler\n * TIMG2PRER TIMG2PRE LL_RCC_SetTIMGPrescaler\n - * TIMG2PRER TIMG3PRE LL_RCC_SetTIMGPrescaler + * TIMG3PRER TIMG3PRE LL_RCC_SetTIMGPrescaler * @param PreSelection This parameter can be one of the following values: * @arg @ref LL_RCC_TIMG1PRES_DEACTIVATED * @arg @ref LL_RCC_TIMG1PRES_ACTIVATED @@ -4151,7 +4151,7 @@ __STATIC_INLINE void LL_RCC_SetTIMGPrescaler(uint32_t PreSelection) * @brief Get TIMGx prescaler selection * @rmtoll TIMG1PRER TIMG1PRE LL_RCC_GetTIMGPrescaler\n * TIMG2PRER TIMG2PRE LL_RCC_GetTIMGPrescaler\n - * TIMG2PRER TIMG3PRE LL_RCC_GetTIMGPrescaler + * TIMG3PRER TIMG3PRE LL_RCC_GetTIMGPrescaler * @param TIMGroup This parameter can be one of the following values: * @arg @ref LL_RCC_TIMG1PRES * @arg @ref LL_RCC_TIMG2PRES diff --git a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_ll_system.h b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_ll_system.h index 6b8b7eefb..e8b394208 100644 --- a/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_ll_system.h +++ b/stm32cube/stm32mp13xx/drivers/include/stm32mp13xx_ll_system.h @@ -122,7 +122,7 @@ extern "C" { */ #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input - and also the PVDE and PLS bits of the + and also the PVDE and PLS bits of the Power Control Interface */ /** * @} diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_adc.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_adc.c index 541068078..70d9ada7c 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_adc.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_adc.c @@ -2783,14 +2783,28 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf } else { +#if defined(ADC1) & !defined(ADC2) if (hadc->Instance == ADC1) { assert_param(IS_ADC1_DIFF_CHANNEL(pConfig->Channel)); } +#endif +#if defined(ADC2) & !defined(ADC1) if (hadc->Instance == ADC2) { assert_param(IS_ADC2_DIFF_CHANNEL(pConfig->Channel)); } +#endif +#if defined(ADC1) & defined(ADC2) + if (hadc->Instance == ADC1) + { + assert_param(IS_ADC1_DIFF_CHANNEL(pConfig->Channel)); + } + if (hadc->Instance == ADC2) + { + assert_param(IS_ADC2_DIFF_CHANNEL(pConfig->Channel)); + } +#endif } /* Process locked */ diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_adc_ex.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_adc_ex.c index 0bd72df62..ce68ce1ed 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_adc_ex.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_adc_ex.c @@ -1694,15 +1694,29 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I } else { +#if defined(ADC1) & !defined(ADC2) if (hadc->Instance == ADC1) { assert_param(IS_ADC1_DIFF_CHANNEL(pConfigInjected->InjectedChannel)); } +#endif +#if !defined(ADC1) & defined(ADC2) if (hadc->Instance == ADC2) { assert_param(IS_ADC2_DIFF_CHANNEL(pConfigInjected->InjectedChannel)); } - } +#endif +#if defined(ADC1) & defined(ADC2) + if (hadc->Instance == ADC1) + { + assert_param(IS_ADC1_DIFF_CHANNEL(pConfigInjected->InjectedChannel)); + } + if (hadc->Instance == ADC2) + { + assert_param(IS_ADC2_DIFF_CHANNEL(pConfigInjected->InjectedChannel)); + } +#endif +} /* Process locked */ __HAL_LOCK(hadc); diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_crc_ex.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_crc_ex.c index dc4a9cf0a..28c0d3ff5 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_crc_ex.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_crc_ex.c @@ -94,7 +94,7 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); - /* Ensure that the generating polynomial is odd */ + /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) { status = HAL_ERROR; @@ -114,7 +114,7 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol switch (PolyLength) { - + case CRC_POLYLENGTH_7B: if (msb >= HAL_CRC_LENGTH_7B) { @@ -133,7 +133,7 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol status = HAL_ERROR; } break; - + case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ break; diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_cryp.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_cryp.c index cff1a569a..900db95dd 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_cryp.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_cryp.c @@ -290,7 +290,7 @@ * @{ */ #define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/ -#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is +#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/ #define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/ @@ -302,7 +302,7 @@ #define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */ #define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */ #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ -#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in +#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in MDMA mode */ #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_cryp_ex.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_cryp_ex.c index 16edf196d..e02278d76 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_cryp_ex.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_cryp_ex.c @@ -62,7 +62,7 @@ #endif /* USE_HAL_SAES_ONLY */ #define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */ -#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant +#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */ /* CTR0 information to use in CCM algorithm */ diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_eth.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_eth.c index 74a29b6cb..a34995713 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_eth.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_eth.c @@ -309,6 +309,7 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) { uint32_t tickstart; + uint32_t syscfg_config; if (heth == NULL) { @@ -367,11 +368,21 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) { if (heth->Instance == ETH) { - HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH1_RMII); + syscfg_config = SYSCFG_ETH1_RMII; + if (heth->Init.ClockSelection == HAL_ETH1_REF_CLK_RCC) + { + syscfg_config |= SYSCFG_PMCSETR_ETH1_REF_CLK_SEL; + } + HAL_SYSCFG_ETHInterfaceSelect(syscfg_config); } else { - HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH2_RMII); + syscfg_config = SYSCFG_ETH2_RMII; + if (heth->Init.ClockSelection == HAL_ETH2_REF_CLK_RCC) + { + syscfg_config |= SYSCFG_PMCSETR_ETH2_REF_CLK_SEL; + } + HAL_SYSCFG_ETHInterfaceSelect(syscfg_config); } } @@ -1111,7 +1122,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) heth->RxDescList.RxDataLength = 0; } - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + /* Get the Frame Length of the received packet */ bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; /* Check if last descriptor */ @@ -1127,11 +1138,11 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) /* Link data */ #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /*Call registered Link callback*/ - heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + heth->rxLinkCallback(heth, &heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, (uint8_t *)dmarxdesc->BackupAddr0, bufflength); #else /* Link callback */ - HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + HAL_ETH_RxLinkCallback(heth, &heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ heth->RxDescList.RxDescCnt++; @@ -1200,10 +1211,10 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) /* Get a new buffer. */ #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /*Call registered Allocate callback*/ - heth->rxAllocateCallback(&buff); + heth->rxAllocateCallback(heth, &buff); #else /* Allocate callback */ - HAL_ETH_RxAllocateCallback(&buff); + HAL_ETH_RxAllocateCallback(heth, &buff); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ if (buff == NULL) { @@ -1239,7 +1250,7 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) if (heth->RxDescList.RxBuildDescCnt != desccount) { /* Set the tail pointer index */ - tailidx = (descidx + 1U) % ETH_RX_DESC_CNT; + tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT; /* DMB instruction to avoid race condition */ __DMB(); @@ -1293,7 +1304,7 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth) * @param buff: pointer to allocated buffer * @retval None */ -__weak void HAL_ETH_RxAllocateCallback(uint8_t **buff) +__weak void HAL_ETH_RxAllocateCallback(ETH_HandleTypeDef *heth, uint8_t **buff) { /* Prevent unused argument(s) compilation warning */ UNUSED(buff); @@ -1310,7 +1321,7 @@ __weak void HAL_ETH_RxAllocateCallback(uint8_t **buff) * @param Length: received data length * @retval None */ -__weak void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) +__weak void HAL_ETH_RxLinkCallback(ETH_HandleTypeDef *heth, void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) { /* Prevent unused argument(s) compilation warning */ UNUSED(pStart); @@ -1412,7 +1423,7 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth) * @param buff: pointer to buffer to free * @retval None */ -__weak void HAL_ETH_TxFreeCallback(uint32_t *buff) +__weak void HAL_ETH_TxFreeCallback(ETH_HandleTypeDef *heth, uint32_t *buff) { /* Prevent unused argument(s) compilation warning */ UNUSED(buff); @@ -1481,22 +1492,22 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) /* Handle Ptp */ if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX) { - heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); + heth->txPtpCallback(heth, dmatxdesclist->PacketAddress[idx], timestamp); } #endif /* HAL_ETH_USE_PTP */ /* Release the packet. */ - heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]); + heth->txFreeCallback(heth, dmatxdesclist->PacketAddress[idx]); #else /* Call callbacks */ #ifdef HAL_ETH_USE_PTP /* Handle Ptp */ if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX) { - HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); + HAL_ETH_TxPtpCallback(heth, dmatxdesclist->PacketAddress[idx], timestamp); } #endif /* HAL_ETH_USE_PTP */ /* Release the packet. */ - HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]); + HAL_ETH_TxFreeCallback(heth, dmatxdesclist->PacketAddress[idx]); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ /* Clear the entry in the in-use array. */ @@ -1866,7 +1877,7 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth) * transmission timestamp * @retval None */ -__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp) +__weak void HAL_ETH_TxPtpCallback(ETH_HandleTypeDef *heth, uint32_t *buff, ETH_TimeStampTypeDef *timestamp) { /* Prevent unused argument(s) compilation warning */ UNUSED(buff); @@ -1995,7 +2006,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) if ((mac_flag & ETH_MAC_LPI_IT) != 0U) { /* Get MAC LPI interrupt source and clear the status register pending bit */ - heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU); + heth->MACLPIEvent = READ_BIT(heth->Instance->MACLCSR, 0x0000000FU); #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /* Call registered EEE callback*/ @@ -2488,7 +2499,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_ ((uint32_t)pFilterConfig->HashMulticast << 2) | ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | ((uint32_t)pFilterConfig->PassAllMulticast << 4) | - ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | + ((uint32_t)((pFilterConfig->BroadcastFilter == ENABLE) ? 1U : 0U) << 5) | ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | @@ -2521,7 +2532,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_ pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE; - pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE; + pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) > 0U) ? ENABLE : DISABLE; pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF); pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_i2c.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_i2c.c index 2057e4604..582ff8108 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_i2c.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_i2c.c @@ -1385,6 +1385,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData uint32_t Timeout) { uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1478,31 +1480,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until AF flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } - return HAL_ERROR; + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_nand.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_nand.c index c704e5978..0f993e85f 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_nand.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_nand.c @@ -527,7 +527,7 @@ static HAL_StatusTypeDef HAL_NAND_ReadBegin(NAND_HandleTypeDef *restrict hnand, if (hnand->Config.ExtraCommandEnable == ENABLE) { status = HAL_NAND_WaitReady(hnand, NAND_READ_BEGIN_TIMEOUT); - if (status != HAL_OK) + if ((status != HAL_OK) && (status != HAL_ERROR)) { return status; } @@ -1013,7 +1013,12 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp /* End writing */ status = HAL_NAND_WriteEnd(hnand); - if (status != HAL_OK) + if (status == HAL_ERROR) + { + hnand->State = HAL_NAND_STATE_READY; + break; + } + else if (status != HAL_OK) { break; } @@ -1120,7 +1125,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SinglePage(NAND_HandleTypeDef *hnand, NAND_Addr status = HAL_NAND_WriteEnd(hnand); } - if (status == HAL_OK) + if ((status == HAL_OK) || (status == HAL_ERROR)) { hnand->State = HAL_NAND_STATE_READY; } @@ -1415,7 +1420,12 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre /* End writing */ status = HAL_NAND_WriteEnd(hnand); - if (status != HAL_OK) + if (status == HAL_ERROR) + { + hnand->State = HAL_NAND_STATE_READY; + break; + } + else if (status != HAL_OK) { break; } @@ -1522,7 +1532,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SingleSpareArea(NAND_HandleTypeDef *hnand, NAND status = HAL_NAND_WriteEnd(hnand); } - if (status == HAL_OK) + if ((status == HAL_OK) || (status == HAL_ERROR)) { hnand->State = HAL_NAND_STATE_READY; } @@ -1609,7 +1619,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy /* Wait end of erase */ status = HAL_NAND_WaitReady(hnand, NAND_ERASE_BLOCK_TIMEOUT); - if (status == HAL_OK) + if ((status == HAL_OK) || (status == HAL_ERROR)) { hnand->State = HAL_NAND_STATE_READY; } @@ -2795,6 +2805,11 @@ HAL_StatusTypeDef HAL_NAND_ECC_Write_Page(NAND_HandleTypeDef *hnand, NAND_Addre while ((numPagesWritten < NumPagesToWrite) && (nandAddress < nandAddressMax)) { status = HAL_NAND_ECC_Write_SinglePage(hnand, nandAddress, pBuffer, bufferOffset); + if (status == HAL_ERROR) + { + hnand->State = HAL_NAND_STATE_READY; + break; + } if (status != HAL_OK) { break; @@ -2888,7 +2903,6 @@ void HAL_NAND_ECC_GetStatistics(NAND_HandleTypeDef *hnand, NAND_EccStatisticsTyp */ - /** @defgroup NAND_Exported_Functions_Group6 Input and Output functions with error correction * @brief Peripheral State functions * @@ -3614,4 +3628,3 @@ HAL_StatusTypeDef HAL_NAND_Sequencer_ECC_Write_Page_16b(NAND_HandleTypeDef *hnan * @} */ - diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_rcc.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_rcc.c index 665b528a3..0f83bb5ec 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_rcc.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_rcc.c @@ -1117,7 +1117,6 @@ HAL_StatusTypeDef RCC_PLL1_Config(const RCC_PLLInitTypeDef *pll1) } - /** * @brief Initializes the MPU,AXI, AHB and APB busses clocks according to the specified * parameters in the RCC_ClkInitStruct. diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_rcc_ex.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_rcc_ex.c index f3759574a..568563948 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_rcc_ex.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_rcc_ex.c @@ -250,7 +250,6 @@ HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLLInitTypeDef *pll2) } - /** * @brief Configures PLL3 * @param pll3: pointer to a RCC_PLLInitTypeDef structure @@ -624,7 +623,7 @@ HAL_StatusTypeDef RCCEx_PLL4_Config(const RCC_PLLInitTypeDef *pll4) * @arg @ref RCC_PERIPHCLK_DCMIPP DCMIPP peripheral clock * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock * @arg @ref RCC_PERIPHCLK_TIMG1 TIMG1 peripheral clock - * @arg @ref RCC_PERIPHCLK_TIMG2 TIMG2 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIMG2 TIMG2 TIMG3 peripheral clock * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @arg @ref RCC_PERIPHCLK_CKPER CKPER peripheral clock * @@ -1988,6 +1987,29 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef } } + /*---------------------------- TIMG3 configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIMG3) == + RCC_PERIPHCLK_TIMG3) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMG3PRES(PeriphClkInit->TIMG3PresSelection)); + + /* Set TIMG3 division factor */ + __HAL_RCC_TIMG3PRES(PeriphClkInit->TIMG3PresSelection); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till TIMG3 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_TIMG3PRERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + return status; } @@ -2001,7 +2023,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef * USART1, USART2, UART35, UART4, USART6, UART78, LPTIM1, LPTIM2, LPTIM3, * LPTIM45, SAI1, SAI2, FDCAN, SPDIFRX, ADC1, ADC2, SDMMC1, SDMMC2, ETH1, * ETH2, USBPHY, USBO, QSPI, FMC, RNG1, STGEN, DCMIPP, SAES, TIMG1, - * TIMG2, RTC and CKPER + * TIMG2, TIMG3, RTC and CKPER * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @@ -2020,8 +2042,8 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_ETH2 | RCC_PERIPHCLK_USBPHY | RCC_PERIPHCLK_USBO | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG1 | RCC_PERIPHCLK_STGEN | RCC_PERIPHCLK_DCMIPP | RCC_PERIPHCLK_SAES | - RCC_PERIPHCLK_TIMG1 | RCC_PERIPHCLK_TIMG2 | RCC_PERIPHCLK_RTC | - RCC_PERIPHCLK_CKPER; + RCC_PERIPHCLK_TIMG1 | RCC_PERIPHCLK_TIMG2 | RCC_PERIPHCLK_TIMG3 | + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_CKPER; /* Get the CKPER clock source ----------------------------------------------*/ @@ -2108,6 +2130,8 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->TIMG1PresSelection = __HAL_RCC_GET_TIMG1PRES(); /* Get the TIM2 Prescaler configuration ------------------------------------*/ PeriphClkInit->TIMG2PresSelection = __HAL_RCC_GET_TIMG2PRES(); + /* Get the TIM3 Prescaler configuration ------------------------------------*/ + PeriphClkInit->TIMG3PresSelection = __HAL_RCC_GET_TIMG3PRES(); } /** @@ -3485,6 +3509,51 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) break; } + case RCC_PERIPHCLK_TIMG3: + { + frequency = HAL_RCC_GetMLAHBFreq(); + + if (__HAL_RCC_GET_TIMG3PRES() == RCC_TIMG3PRES_ACTIVATED) + { + switch (__HAL_RCC_GET_APB6_DIV()) + { + case RCC_APB6_DIV1: + case RCC_APB6_DIV2: + case RCC_APB6_DIV4: + break; + case RCC_APB6_DIV8: + frequency /= 2U; + break; + case RCC_APB6_DIV16: + frequency /= 4U; + break; + default: + break; + } + } + else + { + switch (__HAL_RCC_GET_APB6_DIV()) + { + case RCC_APB6_DIV1: + case RCC_APB6_DIV2: + break; + case RCC_APB6_DIV4: + frequency /= 2U; + break; + case RCC_APB6_DIV8: + frequency /= 4U; + break; + case RCC_APB6_DIV16: + frequency /= 8U; + break; + default: + break; + } + } + break; + } + default: break; diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_smbus.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_smbus.c index 3149af5e8..25405da8a 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_smbus.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_hal_smbus.c @@ -2619,8 +2619,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); + if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) + { + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + } /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_ll_adc.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_ll_adc.c index d41180c47..4212392d6 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_ll_adc.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_ll_adc.c @@ -78,10 +78,22 @@ /* Check of parameters for configuration of ADC hierarchical scope: */ /* common to several ADC instances. */ +#if defined(ADC1) & !defined(ADC2) +#define IS_LL_ADC_COMMON_INSTANCE(__COMMON_INSTANCE__) \ + ( ((__COMMON_INSTANCE__) == ADC1_COMMON) \ + ) +#endif +#if !defined(ADC1) & defined(ADC2) +#define IS_LL_ADC_COMMON_INSTANCE(__COMMON_INSTANCE__) \ + ( ((__COMMON_INSTANCE__) == ADC2_COMMON) \ + ) +#endif +#if defined(ADC1) & defined(ADC2) #define IS_LL_ADC_COMMON_INSTANCE(__COMMON_INSTANCE__) \ ( ((__COMMON_INSTANCE__) == ADC1_COMMON) \ || ((__COMMON_INSTANCE__) == ADC2_COMMON) \ ) +#endif #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ diff --git a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_ll_delayblock.c b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_ll_delayblock.c index 46f545081..25a356ac6 100644 --- a/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_ll_delayblock.c +++ b/stm32cube/stm32mp13xx/drivers/src/stm32mp13xx_ll_delayblock.c @@ -230,7 +230,7 @@ uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_c /** * @} */ -#endif /* HAL_SD_MODULE_ENABLED || HAL_QSPI_MODULE_ENABLED || +#endif /* HAL_SD_MODULE_ENABLED || HAL_QSPI_MODULE_ENABLED || defined(HAL_XSPI_MODULE_ENABLED)*/ /**