From eb95f05e21a2c1bbc63915eff8bd81d05781e162 Mon Sep 17 00:00:00 2001 From: Alessandro Manganaro Date: Thu, 2 Oct 2025 11:38:57 +0200 Subject: [PATCH 1/3] lib/stm32: update stm32wba to cube version V1.7.0 Update Cube version for STM32WBAxx series on https://github.com/STMicroelectronics from version v1.6.0 to version v1.7.0 Signed-off-by: Alessandro Manganaro --- lib/stm32wba/README.rst | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/lib/stm32wba/README.rst b/lib/stm32wba/README.rst index b1d21e9fc..eb1f4ac33 100644 --- a/lib/stm32wba/README.rst +++ b/lib/stm32wba/README.rst @@ -137,9 +137,10 @@ License Link: opensource.org/license/mit Patch List: - * Discard "static" implementation of ll_sys_bg_temperature_measurement_init to allow specific zephyr implementation - Impacted file: ll_sys_if.c - ll_sys.h + + * Discard "static" implementation of ll_sys_bg_temperature_measurement_init to allow specific zephyr implementation + Impacted file: ll_sys_if.c + ll_sys.h * Enabled extended advertising in CFG_BLE_OPTIONS: Impacted file: app_conf.h From 4f4aeb745cab63ce59195f0688df56fda2034e2b Mon Sep 17 00:00:00 2001 From: Vincent Tardy Date: Thu, 9 Oct 2025 17:42:56 +0200 Subject: [PATCH 2/3] lib: blobs: add stm32wba ble-ieee802.15.4 concurrent Link Layer libraries Add WBA6_LinkLayer_BLE_Basic_15_4_lib_Zephyr.a and WBA6_LinkLayer_BLE_Full_15_4_lib_Zephyr.a Signed-off-by: Vincent Tardy --- zephyr/module.yml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/zephyr/module.yml b/zephyr/module.yml index 4a319c5dc..8a74b1604 100644 --- a/zephyr/module.yml +++ b/zephyr/module.yml @@ -67,3 +67,17 @@ blobs: license-path: zephyr/blobs/stm32wba/lib/license.md url: https://github.com/stm32-hotspot/STM32WBA-Zephyr-custom-binaries/raw/main/lib/1_7_0/WBA6_LinkLayer_Thread_lib_Zephyr.a description: "Binary Link Layer library for the STM32WBA6 Thread subsystem" + - path: stm32wba/lib/WBA6_LinkLayer_BLE_Basic_15_4_lib_Zephyr.a + sha256: a919f3c1469c7aad9a8fbc6aab0a20c32f21ce37731d586b6d14e8c51fddfe02 + type: lib + version: '1.7.0' + license-path: zephyr/blobs/stm32wba/lib/license.md + url: https://github.com/stm32-hotspot/STM32WBA-Zephyr-custom-binaries/raw/main/lib/1_7_0/WBA6_LinkLayer_BLE_Basic_15_4_lib_Zephyr.a + description: "Binary Link Layer library for the STM32WBA6 BLE-802.15.4 Concurrent mode subsystem" + - path: stm32wba/lib/WBA6_LinkLayer_BLE_Full_15_4_lib_Zephyr.a + sha256: 15fb3ab8735fbdd546bfa4726471d8bc5352c289ec0d3bc7a14a2febb4c56c11 + type: lib + version: '1.7.0' + license-path: zephyr/blobs/stm32wba/lib/license.md + url: https://github.com/stm32-hotspot/STM32WBA-Zephyr-custom-binaries/raw/main/lib/1_7_0/WBA6_LinkLayer_BLE_Full_15_4_lib_Zephyr.a + description: "Binary Link Layer library for the STM32WBA6 BLE-802.15.4 Concurrent mode subsystem" From 7cb891ea8bba01957d9947855ffd15df6971f87f Mon Sep 17 00:00:00 2001 From: Vincent Tardy Date: Fri, 10 Oct 2025 08:56:03 +0200 Subject: [PATCH 3/3] lib: stm32wba: ble-802.15.4 concurrent mode integration Add support of ble-ieee 802.15.4 concurrent mode Signed-off-by: Vincent Tardy --- lib/stm32wba/CMakeLists.txt | 69 +- .../IEEE802154/STM32_WPAN/Target/ll_sys_if.c | 2 + lib/stm32wba/README.rst | 2 + lib/stm32wba/STM32_WPAN/CMakeLists.txt | 5 - .../config/concurrent/ble_15_4/ll_fw_config.h | 252 ++++++ .../concurrent/ble_full_15_4/ll_fw_config.h | 252 ++++++ .../link_layer/ll_sys/src/ll_sys_startup.c | 63 +- lib/stm32wba/concurrent/CMakeLists.txt | 14 + lib/stm32wba/concurrent/Core/Inc/app_common.h | 116 +++ .../concurrent/Core/Inc/app_conf/app_conf.h | 498 +++++++++++ lib/stm32wba/concurrent/Core/Inc/main.h | 92 ++ .../concurrent/Core/Inc/utilities_conf.h | 178 ++++ .../concurrent/STM32_WPAN/Target/bpka.c | 223 +++++ .../concurrent/STM32_WPAN/Target/bpka.h | 59 ++ .../STM32_WPAN/Target/linklayer_plat.c | 628 ++++++++++++++ .../concurrent/STM32_WPAN/Target/ll_sys_if.c | 280 ++++++ .../concurrent/STM32_WPAN/Target/ll_sys_if.h | 86 ++ .../STM32_WPAN/Target/power_table.c | 119 +++ .../System/Config/Debug_GPIO/debug_config.h | 804 ++++++++++++++++++ .../System/Config/Log/log_module_conf.h | 298 +++++++ scripts/ble_library.py | 19 + 21 files changed, 4029 insertions(+), 30 deletions(-) create mode 100644 lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/ble_15_4/ll_fw_config.h create mode 100644 lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/ble_full_15_4/ll_fw_config.h create mode 100644 lib/stm32wba/concurrent/CMakeLists.txt create mode 100644 lib/stm32wba/concurrent/Core/Inc/app_common.h create mode 100644 lib/stm32wba/concurrent/Core/Inc/app_conf/app_conf.h create mode 100644 lib/stm32wba/concurrent/Core/Inc/main.h create mode 100644 lib/stm32wba/concurrent/Core/Inc/utilities_conf.h create mode 100644 lib/stm32wba/concurrent/STM32_WPAN/Target/bpka.c create mode 100644 lib/stm32wba/concurrent/STM32_WPAN/Target/bpka.h create mode 100644 lib/stm32wba/concurrent/STM32_WPAN/Target/linklayer_plat.c create mode 100644 lib/stm32wba/concurrent/STM32_WPAN/Target/ll_sys_if.c create mode 100644 lib/stm32wba/concurrent/STM32_WPAN/Target/ll_sys_if.h create mode 100644 lib/stm32wba/concurrent/STM32_WPAN/Target/power_table.c create mode 100644 lib/stm32wba/concurrent/System/Config/Debug_GPIO/debug_config.h create mode 100644 lib/stm32wba/concurrent/System/Config/Log/log_module_conf.h diff --git a/lib/stm32wba/CMakeLists.txt b/lib/stm32wba/CMakeLists.txt index c8d7a6665..5542c2777 100644 --- a/lib/stm32wba/CMakeLists.txt +++ b/lib/stm32wba/CMakeLists.txt @@ -85,39 +85,58 @@ if(CONFIG_BT_STM32WBA) target_link_libraries(app PUBLIC stm32wba_ble_lib) endif() -# Selecting the proper version of link layer lib +if(CONFIG_SOC_STM32WBA65XX) +set(libname_prefix "WBA6_") +elseif(CONFIG_SOC_STM32WBA55XX OR SOC_STM32WBA52XX) +set(libname_prefix "") +else() +# Throw an error for unsupported SoC +message(FATAL_ERROR "Unsupported SoC: ${CONFIG_SOC}") +endif() + +# Selecting the proper version of link layer lib and its associated configuration header file if(CONFIG_BT_STM32WBA) - if(BLE_LIB_TYPE STREQUAL "BLE_LIB_BASIC") + message(STATUS "CONFIG_BT_STM32WBA is enabled") + if(CONFIG_IEEE802154_STM32WBA) + message(STATUS "CONFIG_IEEE802154_STM32WBA is enabled") + if(BLE_LIB_TYPE STREQUAL "BLE_LIB_BASIC") + zephyr_include_directories(STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/ble_15_4) + elseif(BLE_LIB_TYPE STREQUAL "BLE_LIB_FULL") + zephyr_include_directories(STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/ble_full_15_4) + endif() + if(BLE_LIB_TYPE STREQUAL "BLE_LIB_BASIC") + set(LL_LIB ${libname_prefix}LinkLayer_BLE_Basic_15_4_lib_Zephyr.a) + elseif(BLE_LIB_TYPE STREQUAL "BLE_LIB_FULL") + set(LL_LIB ${libname_prefix}LinkLayer_BLE_Full_15_4_lib_Zephyr.a) + endif() + else() + message(STATUS "CONFIG_IEEE802154_STM32WBA is disabled") + if(BLE_LIB_TYPE STREQUAL "BLE_LIB_BASIC") zephyr_include_directories(STM32_WPAN/link_layer/ll_cmd_lib/config/ble_basic) - elseif(BLE_LIB_TYPE STREQUAL "BLE_LIB_FULL") + elseif(BLE_LIB_TYPE STREQUAL "BLE_LIB_FULL") zephyr_include_directories(STM32_WPAN/link_layer/ll_cmd_lib/config/ble_full) - endif() - # Checking all the soc variants and not simply relying on board name - if(CONFIG_SOC_STM32WBA65XX) - message(STATUS "STM32WBA6 link layer lib selected") - if (BLE_LIB_TYPE STREQUAL "BLE_LIB_BASIC") - set(LL_LIB "WBA6_LinkLayer_BLE_Basic_lib.a") - elseif (BLE_LIB_TYPE STREQUAL "BLE_LIB_FULL") - set(LL_LIB "WBA6_LinkLayer_BLE_Full_lib.a") endif() - endif() - if(CONFIG_SOC_STM32WBA55XX OR SOC_STM32WBA52XX) - message(STATUS "STM32WBA5 link layer lib selected") - if (BLE_LIB_TYPE STREQUAL "BLE_LIB_BASIC") - set(LL_LIB "LinkLayer_BLE_Basic_lib.a") - elseif (BLE_LIB_TYPE STREQUAL "BLE_LIB_FULL") - set(LL_LIB "LinkLayer_BLE_Full_lib.a") + if(BLE_LIB_TYPE STREQUAL "BLE_LIB_BASIC") + set(LL_LIB ${libname_prefix}LinkLayer_BLE_Basic_lib.a) + elseif(BLE_LIB_TYPE STREQUAL "BLE_LIB_FULL") + set(LL_LIB ${libname_prefix}LinkLayer_BLE_Full_lib.a) endif() endif() elseif(CONFIG_IEEE802154_STM32WBA) + message(STATUS "CONFIG_IEEE802154_STM32WBA is enabled") + if(CONFIG_OPENTHREAD) + zephyr_include_directories(STM32_WPAN/link_layer/ll_cmd_lib/config/thread) + else() + zephyr_include_directories(STM32_WPAN/link_layer/ll_cmd_lib/config/ieee_15_4_basic) + endif() if(CONFIG_SOC_STM32WBA65XX) if(CONFIG_OPENTHREAD) message(STATUS "WBA6_LinkLayer_Thread_lib_Zephyr.a lib selected") - set(LL_LIB "WBA6_LinkLayer_Thread_lib_Zephyr.a") + set(LL_LIB ${libname_prefix}LinkLayer_Thread_lib_Zephyr.a) else() message(STATUS "WBA6_LinkLayer15_4_Zephyr.a lib selected") - set(LL_LIB "WBA6_LinkLayer15_4_Zephyr.a") + set(LL_LIB ${libname_prefix}LinkLayer15_4_Zephyr.a) endif() endif() endif() @@ -131,6 +150,10 @@ if(CONFIG_BT_STM32WBA OR CONFIG_IEEE802154_STM32WBA) endif() add_subdirectory(STM32_WPAN) - -add_subdirectory_ifdef(CONFIG_BT_STM32WBA ble) -add_subdirectory_ifdef(CONFIG_IEEE802154_STM32WBA IEEE802154) +if(CONFIG_BT_STM32WBA AND CONFIG_IEEE802154_STM32WBA) + zephyr_include_directories(IEEE802154/Inc) + add_subdirectory(concurrent) +else() + add_subdirectory_ifdef(CONFIG_BT_STM32WBA ble) + add_subdirectory_ifdef(CONFIG_IEEE802154_STM32WBA IEEE802154) +endif() diff --git a/lib/stm32wba/IEEE802154/STM32_WPAN/Target/ll_sys_if.c b/lib/stm32wba/IEEE802154/STM32_WPAN/Target/ll_sys_if.c index 2f93e95e9..f185ab54e 100644 --- a/lib/stm32wba/IEEE802154/STM32_WPAN/Target/ll_sys_if.c +++ b/lib/stm32wba/IEEE802154/STM32_WPAN/Target/ll_sys_if.c @@ -210,8 +210,10 @@ void ll_sys_sleep_clock_source_selection(void) ll_intf_cmn_le_select_slp_clk_src((uint8_t)linklayer_slp_clk_src, &freq_value); } +#ifndef __ZEPHYR__ void ll_sys_set_rtl_polling_time(uint8_t rtl_polling_time) { /* first parameter otInstance *aInstance is unused */ radio_set_rtl_polling_time(NULL, rtl_polling_time); } +#endif diff --git a/lib/stm32wba/README.rst b/lib/stm32wba/README.rst index eb1f4ac33..8f96aa1d8 100644 --- a/lib/stm32wba/README.rst +++ b/lib/stm32wba/README.rst @@ -51,6 +51,8 @@ Description: Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/ble_basic/ll_fw_config.h Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/ieee_15_4_basic/ll_fw_config.h Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/thread/ll_fw_config.h + Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/ble_15_4/ll_fw_config.h + Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/ble_full_15_4/ll_fw_config.h Middlewares/ST/STM32_WPAN/link_layer/ll_sys/inc/linklayer_plat.h Middlewares/ST/STM32_WPAN/link_layer/ll_sys/inc/ll_sys.h Middlewares/ST/STM32_WPAN/link_layer/ll_sys/src/ll_sys_cs.c diff --git a/lib/stm32wba/STM32_WPAN/CMakeLists.txt b/lib/stm32wba/STM32_WPAN/CMakeLists.txt index 1df662c9d..899bb7dfa 100644 --- a/lib/stm32wba/STM32_WPAN/CMakeLists.txt +++ b/lib/stm32wba/STM32_WPAN/CMakeLists.txt @@ -15,11 +15,6 @@ if(CONFIG_BT_STM32WBA) endif() if(CONFIG_IEEE802154_STM32WBA) zephyr_include_directories(ieee802154) - if(CONFIG_OPENTHREAD) - zephyr_include_directories(link_layer/ll_cmd_lib/config/thread) - else() - zephyr_include_directories(link_layer/ll_cmd_lib/config/ieee_15_4_basic) - endif() zephyr_include_directories(link_layer/ll_cmd_lib/inc/ot_inc) endif() zephyr_include_directories(inc) diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/ble_15_4/ll_fw_config.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/ble_15_4/ll_fw_config.h new file mode 100644 index 000000000..25ccc183e --- /dev/null +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/ble_15_4/ll_fw_config.h @@ -0,0 +1,252 @@ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/ll_fw_config.h#1 $*/ +/** + ******************************************************************************** + * @file ll_fw_config.h + * @brief This file contains the major configurations to the BLE controller. + ****************************************************************************** + * @copy + * This Synopsys DWC Bluetooth Low Energy Combo Link Layer/MAC software and + * associated documentation ( hereinafter the "Software") is an unsupported + * proprietary work of Synopsys, Inc. unless otherwise expressly agreed to in + * writing between Synopsys and you. The Software IS NOT an item of Licensed + * Software or a Licensed Product under any End User Software License Agreement + * or Agreement for Licensed Products with Synopsys or any supplement thereto. + * Synopsys is a registered trademark of Synopsys, Inc. Other names included in + * the SOFTWARE may be the trademarks of their respective owners. + * + * Synopsys MIT License: + * Copyright (c) 2020-Present Synopsys, Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * the Software), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT, OR OTHERWISE ARISING FROM, + * OUT OF, OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * */ +#ifndef INCLUDE_LL_FW_CONFIG_H +#define INCLUDE_LL_FW_CONFIG_H + +/*************************** General Configuration *********************************/ +#ifndef SUPPORT_GNRC_SCHDLR_IF +#define SUPPORT_GNRC_SCHDLR_IF 1 /* Enable\Disable event EXTRNL_GNRC in Ble event manager. Enable:1 - Disable:0 */ +#endif /* SUPPORT_GNRC_SCHDLR_IF */ + +/*************************** BLE Configuration *************************************/ +/*Configurations of BLE will apply only when BLE is enabled*/ +/* Roles configurations */ +#ifndef SUPPORT_EXPLCT_OBSERVER_ROLE +#define SUPPORT_EXPLCT_OBSERVER_ROLE 1 /* Enable\Disable Explicit observer role. Enable:1 - Disable:0 */ +#endif /* SUPPORT_EXPLCT_OBSERVER_ROLE */ + +#ifndef SUPPORT_EXPLCT_BROADCASTER_ROLE +#define SUPPORT_EXPLCT_BROADCASTER_ROLE 1 /* Enable\Disable Explicit broadcaster role. Enable:1 - Disable:0 */ +#endif /* SUPPORT_EXPLCT_BROADCASTER_ROLE */ + +#ifndef SUPPORT_MASTER_CONNECTION +#define SUPPORT_MASTER_CONNECTION 1 /* Enable\Disable Master connection role. Enable:1 - Disable:0 */ +#endif /* SUPPORT_MASTER_CONNECTION */ + +#ifndef SUPPORT_SLAVE_CONNECTION +#define SUPPORT_SLAVE_CONNECTION 1 /* Enable\Disable Slave connection role. Enable:1 - Disable:0 */ +#endif /* SUPPORT_SLAVE_CONNECTION */ + +/* Standard features configurations */ +#ifndef SUPPORT_LE_ENCRYPTION +#define SUPPORT_LE_ENCRYPTION 1 /* Enable\Disable Encryption feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_ENCRYPTION */ + +#ifndef SUPPORT_PRIVACY +#define SUPPORT_PRIVACY 1 /* Enable\Disable Privacy feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_PRIVACY */ + +#ifndef SUPPORT_LE_EXTENDED_ADVERTISING +#define SUPPORT_LE_EXTENDED_ADVERTISING 0 /* Enable\Disable Extended advertising feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_EXTENDED_ADVERTISING */ + +#ifndef SUPPORT_LE_PERIODIC_ADVERTISING +#define SUPPORT_LE_PERIODIC_ADVERTISING 0 /* Enable\Disable Periodic advertising feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_PERIODIC_ADVERTISING */ + +#ifndef SUPPORT_LE_POWER_CLASS_1 +#define SUPPORT_LE_POWER_CLASS_1 0 /* Enable\Disable Low power class 1 feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_POWER_CLASS_1 */ + +#ifndef SUPPORT_AOA_AOD +#define SUPPORT_AOA_AOD 0 /* Enable\Disable AOA_AOD feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_AOA_AOD */ + +#ifndef SUPPORT_PERIODIC_SYNC_TRANSFER +#define SUPPORT_PERIODIC_SYNC_TRANSFER 0 /* Enable\Disable PAST feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_PERIODIC_SYNC_TRANSFER */ + +#ifndef SUPPORT_SLEEP_CLOCK_ACCURCY_UPDATES +#define SUPPORT_SLEEP_CLOCK_ACCURCY_UPDATES 1 /* Enable\Disable Sleep Clock Accuracy Updates Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_SLEEP_CLOCK_ACCURCY_UPDATES */ + +#ifndef SUPPORT_CONNECTED_ISOCHRONOUS +#define SUPPORT_CONNECTED_ISOCHRONOUS 0 /* Enable\Disable Connected Isochronous Channel Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_CONNECTED_ISOCHRONOUS */ + +#ifndef SUPPORT_BRD_ISOCHRONOUS +#define SUPPORT_BRD_ISOCHRONOUS 0 /* Enable\Disable Broadcast Isochronous Channel Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_BRD_ISOCHRONOUS */ + +#ifndef SUPPORT_SYNC_ISOCHRONOUS +#define SUPPORT_SYNC_ISOCHRONOUS 0 /* Enable\Disable Broadcast Isochronous Synchronizer Channel Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_SYNC_ISOCHRONOUS */ + +#ifndef SUPPORT_LE_POWER_CONTROL +#define SUPPORT_LE_POWER_CONTROL 0 /* Enable\Disable LE Power Control Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_POWER_CONTROL */ + +#ifndef SUPPORT_CHANNEL_CLASSIFICATION +#define SUPPORT_CHANNEL_CLASSIFICATION 0 +#endif /* SUPPORT_CHANNEL_CLASSIFICATION */ + +#ifndef SUPPORT_PERIODIC_ADV_ADI +#define SUPPORT_PERIODIC_ADV_ADI 0 +#endif /* SUPPORT_PERIODIC_ADV_ADI */ + +#ifndef SUPPORT_LE_ENHANCED_CONN_UPDATE +#define SUPPORT_LE_ENHANCED_CONN_UPDATE 0 +#endif /* SUPPORT_LE_ENHANCED_CONN_UPDATE */ + +#ifndef SUPPORT_CSSA +#define SUPPORT_CSSA 0 /* Enable\Disable Coding Selection Scheme on Advertising Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_CSSA */ + +#ifndef SUPPORT_LE_PAWR_ADVERTISER_ROLE +#define SUPPORT_LE_PAWR_ADVERTISER_ROLE 0 /* Enable\Disable PAwR Advertiser role. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_PAWR_ADVERTISER_ROLE */ + +#ifndef SUPPORT_LE_PAWR_SYNC_ROLE +#define SUPPORT_LE_PAWR_SYNC_ROLE 0 /* Enable\Disable PAwR Synchronizer role. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_PAWR_SYNC_ROLE */ + +#ifndef SUPPORT_CHANNEL_SOUNDING +#define SUPPORT_CHANNEL_SOUNDING 0 /* Enable\Disable Channel Sounding Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_CHANNEL_SOUNDING */ + +#ifndef SUPPORT_FRAME_SPACE_UPDATE +#define SUPPORT_FRAME_SPACE_UPDATE 0 /* Enable\Disable Frame Space Update Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_FRAME_SPACE_UPDATE */ + +#ifndef SUPPORT_EXT_FEATURE_SET +#define SUPPORT_EXT_FEATURE_SET 0 /* Enable\Disable Extended Feature Set Exchange. Enable:1 - Disable:0 */ +#endif /* SUPPORT_EXT_FEATURE_SET */ + +#ifndef SUPPORT_ISO_UNSEG_MODE +#define SUPPORT_ISO_UNSEG_MODE 0 /* Enable\Disable Unsegmented Mode for Framed ISO PDUs. Enable: 1 - Disable: 0*/ +#endif /* SUPPORT_ISO_UNSEG_MODE */ + +#ifndef SUPPORT_LE_ADVERTISERS_MONITORING +#define SUPPORT_LE_ADVERTISERS_MONITORING 0 /* Enable\Disable Advertisers Monitoring Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_ADVERTISERS_MONITORING */ + +/* Capabilities configurations */ +#ifndef MAX_NUM_CNCRT_STAT_MCHNS +#define MAX_NUM_CNCRT_STAT_MCHNS 8 /* Set maximum number of states the controller can support */ +#endif /* MAX_NUM_CNCRT_STAT_MCHNS */ + +#ifndef USE_NON_ACCURATE_32K_SLEEP_CLK +#define USE_NON_ACCURATE_32K_SLEEP_CLK 1 /* Allow to drive the sleep clock by sources other than the default crystal oscillator source.*/ + /*LL can use crystal oscillator or RTC or RCO to drive the sleep clock.This selection is done via "DEFAULT_SLEEP_CLOCK_SOURCE" macro. */ +#endif /* USE_NON_ACCURATE_32K_SLEEP_CLK */ + +#ifndef SUPPORT_CTE_DEGRADATION_API +#define SUPPORT_CTE_DEGRADATION_API 1 /* Enable\Disable CTE degradation API. Enable:1 - Disable:0 */ +#endif /* SUPPORT_CTE_DEGRADATION_API */ + +/* Non-standard features configurations */ +#ifndef NUM_OF_CTSM_EMNGR_HNDLS +#define NUM_OF_CTSM_EMNGR_HNDLS 1 /* Number of custom handles in event manager to be used for app specific needs */ +#endif /* NUM_OF_CTSM_EMNGR_HNDLS */ + +#ifndef SUPPORT_AUGMENTED_BLE_MODE +#define SUPPORT_AUGMENTED_BLE_MODE 1 /* Enable\Disable Augmented BLE Support. Enable:1 - Disable:0 */ +#endif /* SUPPORT_AUGMENTED_BLE_MODE */ + +#ifndef SUPPORT_PTA +#define SUPPORT_PTA 1 /* Enable\Disable PTA Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_PTA */ + +#ifndef SUPPORT_CONFIGURABLE_GAIN_FIX +#define SUPPORT_CONFIGURABLE_GAIN_FIX 0 /* Enable\Disable configurable gain fix support */ +#endif /* SUPPORT_CONFIGURABLE_GAIN_FIX */ + +#ifndef CHECK_ANY_MISSED_EVENT_ON_DEEP_SLEEP_EXIT +#define CHECK_ANY_MISSED_EVENT_ON_DEEP_SLEEP_EXIT 1 /* Enable\Disable calling event scheduler handler function at the end of deep sleep exit*/ +#endif /* CHECK_ANY_MISSED_EVENT_ON_DEEP_SLEEP_EXIT */ + +#ifndef LL_BASIC +#define LL_BASIC 0 +#endif /* LL_BASIC */ + +/*************************** MAC Configuration *************************************/ +/*Configurations of MAC will apply only when MAC is enabled*/ +#ifndef FFD_DEVICE_CONFIG +#define FFD_DEVICE_CONFIG 1 /* Enable\Disable FFD:1 - RFD:0 */ +#endif /* FFD_DEVICE_CONFIG */ + +#ifdef RFD_DEVICE_CONFIG +#undef FFD_DEVICE_CONFIG +#define FFD_DEVICE_CONFIG 0 /* Enable\Disable FFD:1 - RFD:0 */ +#endif + +#ifndef RAL_NUMBER_OF_INSTANCE +#define RAL_NUMBER_OF_INSTANCE 1 /* The Number of RAL instances supported */ +#endif /* RAL_NUMBER_OF_INSTANCE */ + +#ifndef MAX_NUMBER_OF_INDIRECT_DATA +#define MAX_NUMBER_OF_INDIRECT_DATA 10 /* The maximum number of supported indirect data buffers */ +#endif /* MAX_NUMBER_OF_INDIRECT_DATA */ + +#ifndef SUPPORT_OPENTHREAD_1_2 +#define SUPPORT_OPENTHREAD_1_2 1 /* Enable / disable FW parts related to new features introduced in openthread 1.2*/ +#endif /* SUPPORT_OPENTHREAD_1_2 */ + +#ifndef SUPPORT_SEC +#define SUPPORT_SEC 1 /* The MAC Security Supported : 1 - Not Supported:0 */ +#endif /* SUPPORT_SEC */ + +#ifndef RADIO_CSMA +#define RADIO_CSMA 1 /* Enable\Disable CSMA Algorithm in Radio Layer, Must be Enabled if MAC_LAYER_BUILD */ +#endif /* RADIO_CSMA */ + +#ifndef SUPPORT_ANT_DIV +#define SUPPORT_ANT_DIV 1 /* Enable/Disable Antenna Diversity Feature */ +#endif /* SUPPORT_ANT_DIV */ + +#ifndef SUPPORT_A_MAC +#define SUPPORT_A_MAC 1 +#endif /* SUPPORT_A_MAC */ + +#ifndef SUPPORT_CONFIG_LIB +#define SUPPORT_CONFIG_LIB 1 /* Enable\Disable Configurable Library feature */ +#endif /* SUPPORT_CONFIG_LIB */ + +#ifndef SMPL_PRTCL_TEST_ENABLE +#define SMPL_PRTCL_TEST_ENABLE 0 +#endif /* SMPL_PRTCL_TEST_ENABLE */ + +#ifndef IEEE_EUI64_VENDOR_SPECIFIC_FUNC +#define IEEE_EUI64_VENDOR_SPECIFIC_FUNC 1 /* Comment to disable EUI-64 vendor specific function, in this case EUI-64 is not unique */ +#endif /* IEEE_EUI64_VENDOR_SPECIFIC_FUNC */ + +/*************************** Zigbee Configuration **********************************/ +#ifndef SUPPORT_ZIGBEE_PHY_CERTIFICATION +#define SUPPORT_ZIGBEE_PHY_CERTIFICATION 0 /* Enable support of hci command required to implement zigbee phy Test cases Enable:1 - Disable:0 */ +#endif /* SUPPORT_ZIGBEE_PHY_CERTIFICATION */ + +#endif /* INCLUDE_LL_FW_CONFIG_H */ diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/ble_full_15_4/ll_fw_config.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/ble_full_15_4/ll_fw_config.h new file mode 100644 index 000000000..12d5049da --- /dev/null +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/ble_full_15_4/ll_fw_config.h @@ -0,0 +1,252 @@ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/ll_fw_config.h#1 $*/ +/** + ******************************************************************************** + * @file ll_fw_config.h + * @brief This file contains the major configurations to the BLE controller. + ****************************************************************************** + * @copy + * This Synopsys DWC Bluetooth Low Energy Combo Link Layer/MAC software and + * associated documentation ( hereinafter the "Software") is an unsupported + * proprietary work of Synopsys, Inc. unless otherwise expressly agreed to in + * writing between Synopsys and you. The Software IS NOT an item of Licensed + * Software or a Licensed Product under any End User Software License Agreement + * or Agreement for Licensed Products with Synopsys or any supplement thereto. + * Synopsys is a registered trademark of Synopsys, Inc. Other names included in + * the SOFTWARE may be the trademarks of their respective owners. + * + * Synopsys MIT License: + * Copyright (c) 2020-Present Synopsys, Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * the Software), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT, OR OTHERWISE ARISING FROM, + * OUT OF, OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * */ +#ifndef INCLUDE_LL_FW_CONFIG_H +#define INCLUDE_LL_FW_CONFIG_H + +/*************************** General Configuration *********************************/ +#ifndef SUPPORT_GNRC_SCHDLR_IF +#define SUPPORT_GNRC_SCHDLR_IF 1 /* Enable\Disable event EXTRNL_GNRC in Ble event manager. Enable:1 - Disable:0 */ +#endif /* SUPPORT_GNRC_SCHDLR_IF */ + +/*************************** BLE Configuration *************************************/ +/*Configurations of BLE will apply only when BLE is enabled*/ +/* Roles configurations */ +#ifndef SUPPORT_EXPLCT_OBSERVER_ROLE +#define SUPPORT_EXPLCT_OBSERVER_ROLE 1 /* Enable\Disable Explicit observer role. Enable:1 - Disable:0 */ +#endif /* SUPPORT_EXPLCT_OBSERVER_ROLE */ + +#ifndef SUPPORT_EXPLCT_BROADCASTER_ROLE +#define SUPPORT_EXPLCT_BROADCASTER_ROLE 1 /* Enable\Disable Explicit broadcaster role. Enable:1 - Disable:0 */ +#endif /* SUPPORT_EXPLCT_BROADCASTER_ROLE */ + +#ifndef SUPPORT_MASTER_CONNECTION +#define SUPPORT_MASTER_CONNECTION 1 /* Enable\Disable Master connection role. Enable:1 - Disable:0 */ +#endif /* SUPPORT_MASTER_CONNECTION */ + +#ifndef SUPPORT_SLAVE_CONNECTION +#define SUPPORT_SLAVE_CONNECTION 1 /* Enable\Disable Slave connection role. Enable:1 - Disable:0 */ +#endif /* SUPPORT_SLAVE_CONNECTION */ + +/* Standard features configurations */ +#ifndef SUPPORT_LE_ENCRYPTION +#define SUPPORT_LE_ENCRYPTION 1 /* Enable\Disable Encryption feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_ENCRYPTION */ + +#ifndef SUPPORT_PRIVACY +#define SUPPORT_PRIVACY 1 /* Enable\Disable Privacy feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_PRIVACY */ + +#ifndef SUPPORT_LE_EXTENDED_ADVERTISING +#define SUPPORT_LE_EXTENDED_ADVERTISING 1 /* Enable\Disable Extended advertising feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_EXTENDED_ADVERTISING */ + +#ifndef SUPPORT_LE_PERIODIC_ADVERTISING +#define SUPPORT_LE_PERIODIC_ADVERTISING 1 /* Enable\Disable Periodic advertising feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_PERIODIC_ADVERTISING */ + +#ifndef SUPPORT_LE_POWER_CLASS_1 +#define SUPPORT_LE_POWER_CLASS_1 1 /* Enable\Disable Low power class 1 feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_POWER_CLASS_1 */ + +#ifndef SUPPORT_AOA_AOD +#define SUPPORT_AOA_AOD 1 /* Enable\Disable AOA_AOD feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_AOA_AOD */ + +#ifndef SUPPORT_PERIODIC_SYNC_TRANSFER +#define SUPPORT_PERIODIC_SYNC_TRANSFER 1 /* Enable\Disable PAST feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_PERIODIC_SYNC_TRANSFER */ + +#ifndef SUPPORT_SLEEP_CLOCK_ACCURCY_UPDATES +#define SUPPORT_SLEEP_CLOCK_ACCURCY_UPDATES 1 /* Enable\Disable Sleep Clock Accuracy Updates Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_SLEEP_CLOCK_ACCURCY_UPDATES */ + +#ifndef SUPPORT_CONNECTED_ISOCHRONOUS +#define SUPPORT_CONNECTED_ISOCHRONOUS 1 /* Enable\Disable Connected Isochronous Channel Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_CONNECTED_ISOCHRONOUS */ + +#ifndef SUPPORT_BRD_ISOCHRONOUS +#define SUPPORT_BRD_ISOCHRONOUS 1 /* Enable\Disable Broadcast Isochronous Channel Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_BRD_ISOCHRONOUS */ + +#ifndef SUPPORT_SYNC_ISOCHRONOUS +#define SUPPORT_SYNC_ISOCHRONOUS 1 /* Enable\Disable Broadcast Isochronous Synchronizer Channel Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_SYNC_ISOCHRONOUS */ + +#ifndef SUPPORT_LE_POWER_CONTROL +#define SUPPORT_LE_POWER_CONTROL 1 /* Enable\Disable LE Power Control Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_POWER_CONTROL */ + +#ifndef SUPPORT_CHANNEL_CLASSIFICATION +#define SUPPORT_CHANNEL_CLASSIFICATION 1 +#endif /* SUPPORT_CHANNEL_CLASSIFICATION */ + +#ifndef SUPPORT_PERIODIC_ADV_ADI +#define SUPPORT_PERIODIC_ADV_ADI 1 +#endif /* SUPPORT_PERIODIC_ADV_ADI */ + +#ifndef SUPPORT_LE_ENHANCED_CONN_UPDATE +#define SUPPORT_LE_ENHANCED_CONN_UPDATE 1 +#endif /* SUPPORT_LE_ENHANCED_CONN_UPDATE */ + +#ifndef SUPPORT_CSSA +#define SUPPORT_CSSA 1 /* Enable\Disable Coding Selection Scheme on Advertising Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_CSSA */ + +#ifndef SUPPORT_LE_PAWR_ADVERTISER_ROLE +#define SUPPORT_LE_PAWR_ADVERTISER_ROLE 0 /* Enable\Disable PAwR Advertiser role. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_PAWR_ADVERTISER_ROLE */ + +#ifndef SUPPORT_LE_PAWR_SYNC_ROLE +#define SUPPORT_LE_PAWR_SYNC_ROLE 0 /* Enable\Disable PAwR Synchronizer role. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_PAWR_SYNC_ROLE */ + +#ifndef SUPPORT_CHANNEL_SOUNDING +#define SUPPORT_CHANNEL_SOUNDING 0 /* Enable\Disable Channel Sounding Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_CHANNEL_SOUNDING */ + +#ifndef SUPPORT_FRAME_SPACE_UPDATE +#define SUPPORT_FRAME_SPACE_UPDATE 0 /* Enable\Disable Frame Space Update Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_FRAME_SPACE_UPDATE */ + +#ifndef SUPPORT_EXT_FEATURE_SET +#define SUPPORT_EXT_FEATURE_SET 0 /* Enable\Disable Extended Feature Set Exchange. Enable:1 - Disable:0 */ +#endif /* SUPPORT_EXT_FEATURE_SET */ + +#ifndef SUPPORT_ISO_UNSEG_MODE +#define SUPPORT_ISO_UNSEG_MODE 0 /* Enable\Disable Unsegmented Mode for Framed ISO PDUs. Enable: 1 - Disable: 0*/ +#endif /* SUPPORT_ISO_UNSEG_MODE */ + +#ifndef SUPPORT_LE_ADVERTISERS_MONITORING +#define SUPPORT_LE_ADVERTISERS_MONITORING 0 /* Enable\Disable Advertisers Monitoring Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_LE_ADVERTISERS_MONITORING */ + +/* Capabilities configurations */ +#ifndef MAX_NUM_CNCRT_STAT_MCHNS +#define MAX_NUM_CNCRT_STAT_MCHNS 8 /* Set maximum number of states the controller can support */ +#endif /* MAX_NUM_CNCRT_STAT_MCHNS */ + +#ifndef USE_NON_ACCURATE_32K_SLEEP_CLK +#define USE_NON_ACCURATE_32K_SLEEP_CLK 1 /* Allow to drive the sleep clock by sources other than the default crystal oscillator source.*/ + /*LL can use crystal oscillator or RTC or RCO to drive the sleep clock.This selection is done via "DEFAULT_SLEEP_CLOCK_SOURCE" macro. */ +#endif /* USE_NON_ACCURATE_32K_SLEEP_CLK */ + +#ifndef SUPPORT_CTE_DEGRADATION_API +#define SUPPORT_CTE_DEGRADATION_API 1 /* Enable\Disable CTE degradation API. Enable:1 - Disable:0 */ +#endif /* SUPPORT_CTE_DEGRADATION_API */ + +/* Non-standard features configurations */ +#ifndef NUM_OF_CTSM_EMNGR_HNDLS +#define NUM_OF_CTSM_EMNGR_HNDLS 1 /* Number of custom handles in event manager to be used for app specific needs */ +#endif /* NUM_OF_CTSM_EMNGR_HNDLS */ + +#ifndef SUPPORT_AUGMENTED_BLE_MODE +#define SUPPORT_AUGMENTED_BLE_MODE 1 /* Enable\Disable Augmented BLE Support. Enable:1 - Disable:0 */ +#endif /* SUPPORT_AUGMENTED_BLE_MODE */ + +#ifndef SUPPORT_PTA +#define SUPPORT_PTA 1 /* Enable\Disable PTA Feature. Enable:1 - Disable:0 */ +#endif /* SUPPORT_PTA */ + +#ifndef SUPPORT_CONFIGURABLE_GAIN_FIX +#define SUPPORT_CONFIGURABLE_GAIN_FIX 0 /* Enable\Disable configurable gain fix support */ +#endif /* SUPPORT_CONFIGURABLE_GAIN_FIX */ + +#ifndef CHECK_ANY_MISSED_EVENT_ON_DEEP_SLEEP_EXIT +#define CHECK_ANY_MISSED_EVENT_ON_DEEP_SLEEP_EXIT 1 /* Enable\Disable calling event scheduler handler function at the end of deep sleep exit*/ +#endif /* CHECK_ANY_MISSED_EVENT_ON_DEEP_SLEEP_EXIT */ + +#ifndef LL_BASIC +#define LL_BASIC 0 +#endif /* LL_BASIC */ + +/*************************** MAC Configuration *************************************/ +/*Configurations of MAC will apply only when MAC is enabled*/ +#ifndef FFD_DEVICE_CONFIG +#define FFD_DEVICE_CONFIG 1 /* Enable\Disable FFD:1 - RFD:0 */ +#endif /* FFD_DEVICE_CONFIG */ + +#ifdef RFD_DEVICE_CONFIG +#undef FFD_DEVICE_CONFIG +#define FFD_DEVICE_CONFIG 0 /* Enable\Disable FFD:1 - RFD:0 */ +#endif + +#ifndef RAL_NUMBER_OF_INSTANCE +#define RAL_NUMBER_OF_INSTANCE 1 /* The Number of RAL instances supported */ +#endif /* RAL_NUMBER_OF_INSTANCE */ + +#ifndef MAX_NUMBER_OF_INDIRECT_DATA +#define MAX_NUMBER_OF_INDIRECT_DATA 10 /* The maximum number of supported indirect data buffers */ +#endif /* MAX_NUMBER_OF_INDIRECT_DATA */ + +#ifndef SUPPORT_OPENTHREAD_1_2 +#define SUPPORT_OPENTHREAD_1_2 1 /* Enable / disable FW parts related to new features introduced in openthread 1.2*/ +#endif /* SUPPORT_OPENTHREAD_1_2 */ + +#ifndef SUPPORT_SEC +#define SUPPORT_SEC 1 /* The MAC Security Supported : 1 - Not Supported:0 */ +#endif /* SUPPORT_SEC */ + +#ifndef RADIO_CSMA +#define RADIO_CSMA 1 /* Enable\Disable CSMA Algorithm in Radio Layer, Must be Enabled if MAC_LAYER_BUILD */ +#endif /* RADIO_CSMA */ + +#ifndef SUPPORT_ANT_DIV +#define SUPPORT_ANT_DIV 1 /* Enable/Disable Antenna Diversity Feature */ +#endif /* SUPPORT_ANT_DIV */ + +#ifndef SUPPORT_A_MAC +#define SUPPORT_A_MAC 1 +#endif /* SUPPORT_A_MAC */ + +#ifndef SUPPORT_CONFIG_LIB +#define SUPPORT_CONFIG_LIB 1 /* Enable\Disable Configurable Library feature */ +#endif /* SUPPORT_CONFIG_LIB */ + +#ifndef SMPL_PRTCL_TEST_ENABLE +#define SMPL_PRTCL_TEST_ENABLE 0 +#endif /* SMPL_PRTCL_TEST_ENABLE */ + +#ifndef IEEE_EUI64_VENDOR_SPECIFIC_FUNC +#define IEEE_EUI64_VENDOR_SPECIFIC_FUNC 1 /* Comment to disable EUI-64 vendor specific function, in this case EUI-64 is not unique */ +#endif /* IEEE_EUI64_VENDOR_SPECIFIC_FUNC */ + +/*************************** Zigbee Configuration **********************************/ +#ifndef SUPPORT_ZIGBEE_PHY_CERTIFICATION +#define SUPPORT_ZIGBEE_PHY_CERTIFICATION 0 /* Enable support of hci command required to implement zigbee phy Test cases Enable:1 - Disable:0 */ +#endif /* SUPPORT_ZIGBEE_PHY_CERTIFICATION */ + +#endif /* INCLUDE_LL_FW_CONFIG_H */ diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_startup.c b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_startup.c index 1a056414a..87a74f99c 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_startup.c +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_startup.c @@ -33,7 +33,9 @@ * @brief Missed HCI event flag */ uint8_t missed_hci_event_flag = 0; - +#ifdef __ZEPHYR__ +static void ll_init(void); +#endif /*__ZEPHYR__*/ static void ll_sys_dependencies_init(void); #ifdef BLE static void ll_sys_event_missed_cb( ble_buff_hdr_t* ptr_evnt_hdr ) @@ -48,6 +50,7 @@ static void ll_sys_event_missed_cb( ble_buff_hdr_t* ptr_evnt_hdr ) */ void ll_sys_ble_cntrl_init(hst_cbk hostCallback) { +#ifndef __ZEPHYR__ const struct hci_dispatch_tbl* p_hci_dis_tbl = NULL; hci_get_dis_tbl( &p_hci_dis_tbl ); @@ -59,6 +62,13 @@ void ll_sys_ble_cntrl_init(hst_cbk hostCallback) ll_intf_rgstr_hst_cbk_ll_queue_full( ll_sys_event_missed_cb ); ll_sys_dependencies_init(); +#else /*__ZEPHYR__*/ + ll_init(); + + ll_intf_rgstr_hst_cbk(hostCallback); + + ll_intf_rgstr_hst_cbk_ll_queue_full( ll_sys_event_missed_cb ); +#endif /*__ZEPHYR__*/ } #endif /* BLE */ #if defined(CONFIG_NET_L2_CUSTOM_IEEE802154_STM32WBA) @@ -71,8 +81,12 @@ void ll_sys_ble_cntrl_init(hst_cbk hostCallback) */ void ll_sys_mac_cntrl_init(void) { +#ifndef __ZEPHYR__ ST_MAC_preInit(); ll_sys_dependencies_init(); +#else /*__ZEPHYR__*/ + ll_init(); +#endif /*__ZEPHYR__*/ } #endif /* OPENTHREAD_CONFIG_FILE */ #endif /* MAC */ @@ -84,7 +98,11 @@ void ll_sys_mac_cntrl_init(void) */ void ll_sys_thread_init(void) { +#ifndef __ZEPHYR__ ll_sys_dependencies_init(); +#else /*__ZEPHYR__*/ + ll_init(); +#endif /*__ZEPHYR__*/ } /** @@ -96,14 +114,18 @@ void ll_sys_thread_init(void) */ static void ll_sys_dependencies_init(void) { +#ifndef __ZEPHYR__ static uint8_t is_ll_initialized = 0; +#endif /*__ZEPHYR__*/ ll_sys_status_t dp_slp_status; +#ifndef __ZEPHYR__ /* Ensure Link Layer resources are created only once */ if (is_ll_initialized == 1) { return; } is_ll_initialized = 1; +#endif /*__ZEPHYR__*/ /* Deep sleep feature initialization */ dp_slp_status = ll_sys_dp_slp_init(); @@ -114,4 +136,41 @@ static void ll_sys_dependencies_init(void) /* Link Layer user parameters application */ ll_sys_config_params(); -} \ No newline at end of file +} + +#ifdef __ZEPHYR__ +/** + * @brief Initialize the Link Layer IP BLE/802.15.4 MAC controller + * @param None + * @retval None + */ +static void ll_init(void) +{ + static uint8_t is_ll_initialized = 0; +#ifdef BLE + const struct hci_dispatch_tbl* p_hci_dis_tbl = NULL; +#endif /* BLE */ + + /* Ensure Link Layer resources are created only once */ + if (is_ll_initialized == 1) { + return; + } + is_ll_initialized = 1; + +#ifdef BLE + hci_get_dis_tbl( &p_hci_dis_tbl ); + + ll_intf_init(p_hci_dis_tbl); +#endif /* BLE */ + +#if defined(CONFIG_NET_L2_CUSTOM_IEEE802154_STM32WBA) +#if defined(MAC) +#ifndef OPENTHREAD_CONFIG_FILE + ST_MAC_preInit(); +#endif /* OPENTHREAD_CONFIG_FILE */ +#endif /* MAC */ +#endif /* CONFIG_NET_L2_CUSTOM_IEEE802154_STM32WBA */ + + ll_sys_dependencies_init(); +} +#endif /*__ZEPHYR__*/ \ No newline at end of file diff --git a/lib/stm32wba/concurrent/CMakeLists.txt b/lib/stm32wba/concurrent/CMakeLists.txt new file mode 100644 index 000000000..3ff9f9829 --- /dev/null +++ b/lib/stm32wba/concurrent/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2025 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 +if(NOT CONFIG_NET_L2_CUSTOM_IEEE802154) + zephyr_include_directories(Core/Inc/app_conf) +endif() +zephyr_include_directories(Core/Inc) +zephyr_include_directories(STM32_WPAN/Target) +zephyr_include_directories(System/Config/Debug_GPIO) +zephyr_include_directories(System/Config/Log) +zephyr_sources(STM32_WPAN/Target/bpka.c) +zephyr_sources(STM32_WPAN/Target/linklayer_plat.c) +zephyr_sources(STM32_WPAN/Target/ll_sys_if.c) +zephyr_sources(STM32_WPAN/Target/power_table.c) diff --git a/lib/stm32wba/concurrent/Core/Inc/app_common.h b/lib/stm32wba/concurrent/Core/Inc/app_common.h new file mode 100644 index 000000000..c548da1f0 --- /dev/null +++ b/lib/stm32wba/concurrent/Core/Inc/app_common.h @@ -0,0 +1,116 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file app_common.h + * @author MCD Application Team + * @brief App Common application configuration file for STM32WPAN Middleware. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef APP_COMMON_H +#define APP_COMMON_H + +#ifdef __cplusplus +extern "C"{ +#endif + +#include +#include +#include +#include +#include +#include + +#include "app_conf.h" +#include "hw.h" +#include "ll_sys.h" + +/* -------------------------------- * + * Basic definitions * + * -------------------------------- */ +#undef NULL +#define NULL 0 + +#undef FALSE +#define FALSE 0 + +#undef TRUE +#define TRUE (!0) + +/* -------------------------------- * + * Critical Section definition * + * -------------------------------- */ +#define BACKUP_PRIMASK() uint32_t primask_bit= __get_PRIMASK() +#define DISABLE_IRQ() __disable_irq() +#define RESTORE_PRIMASK() __set_PRIMASK(primask_bit) + +/* -------------------------------- * + * Macro delimiters * + * -------------------------------- */ +#define M_BEGIN do { + +#define M_END } while(0) + +/* -------------------------------- * + * Some useful macro definitions * + * -------------------------------- */ +#ifndef MAX +#define MAX( x, y ) (((x)>(y))?(x):(y)) +#endif + +#ifndef MIN +#define MIN( x, y ) (((x)<(y))?(x):(y)) +#endif + +#define MODINC( a, m ) M_BEGIN (a)++; if ((a)>=(m)) (a)=0; M_END + +#define MODDEC( a, m ) M_BEGIN if ((a)==0) (a)=(m); (a)--; M_END + +#define MODADD( a, b, m ) M_BEGIN (a)+=(b); if ((a)>=(m)) (a)-=(m); M_END + +#define MODSUB( a, b, m ) MODADD( a, (m)-(b), m ) + +#define PAUSE( t ) M_BEGIN \ + __IO int _i; \ + for ( _i = t; _i > 0; _i -- ); \ + M_END + +#define DIVF( x, y ) ((x)/(y)) + +#define DIVC( x, y ) (((x)+(y)-1)/(y)) + +#define DIVR( x, y ) (((x)+((y)/2))/(y)) + +#define SHRR( x, n ) ((((x)>>((n)-1))+1)>>1) + +#define BITN( w, n ) (((w)[(n)/32] >> ((n)%32)) & 1) + +#define BITNSET( w, n, b ) M_BEGIN (w)[(n)/32] |= ((U32)(b))<<((n)%32); M_END + +/* -------------------------------- * + * Compiler * + * -------------------------------- */ +#define PLACE_IN_SECTION( __x__ ) __attribute__((section (__x__))) + +#ifdef WIN32 +#define ALIGN(n) +#else +#define ALIGN(n) __attribute__((aligned(n))) +#endif + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif /*APP_COMMON_H */ diff --git a/lib/stm32wba/concurrent/Core/Inc/app_conf/app_conf.h b/lib/stm32wba/concurrent/Core/Inc/app_conf/app_conf.h new file mode 100644 index 000000000..7122a40e2 --- /dev/null +++ b/lib/stm32wba/concurrent/Core/Inc/app_conf/app_conf.h @@ -0,0 +1,498 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file app_conf.h + * @author MCD Application Team + * @brief Application configuration file for STM32WPAN Middleware. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef APP_CONF_H +#define APP_CONF_H + +/* Includes ------------------------------------------------------------------*/ +#include "hw_if.h" +#include "utilities_conf.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/****************************************************************************** + * Application Config + ******************************************************************************/ +/**< generic parameters ******************************************************/ + +/** +* Identity root key used to derive IRK and DHK(Legacy) +*/ +#define CFG_BLE_IR {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + +/** +* Encryption root key used to derive LTK(Legacy) and CSRK +*/ +#define CFG_BLE_ER {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + +/* USER CODE BEGIN Generic_Parameters */ + +/* USER CODE END Generic_Parameters */ + +/**< specific parameters */ +/*****************************************************/ + +/* USER CODE BEGIN Specific_Parameters */ + +/* USER CODE END Specific_Parameters */ + +/****************************************************************************** + * BLE Stack + ******************************************************************************/ +/** + * BLE stack options, bitmap to active or not some features at BleStack_Init() function call. + */ +#define CFG_BLE_OPTIONS (0 | \ + 0 | \ + 0 | \ + BLE_OPTIONS_EXTENDED_ADV | \ + 0 | \ + BLE_OPTIONS_GATT_CACHING | \ + 0 | \ + 0 | \ + BLE_OPTIONS_ENHANCED_ATT) + +/** + * Maximum number of simultaneous connections and advertising that the device will support. + * This setting should not exceed the number of BLE connection supported by BLE host stack. + */ +#define CFG_BLE_NUM_LINK (2) + +/** + * Maximum number of Services that can be stored in the GATT database. + * Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services + */ +#define CFG_BLE_NUM_GATT_SERVICES (8) + +/** + * Maximum number of Attributes + * (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services) + * that can be stored in the GATT database. + * Note that certain characteristics and relative descriptors are added automatically during device initialization + * so this parameters should be 9 plus the number of user Attributes + */ +#define CFG_BLE_NUM_GATT_ATTRIBUTES (68) + +/** + * Maximum supported ATT_MTU size + * This setting should be aligned with ATT_MTU value configured in the ble host + */ +#define CFG_BLE_ATT_MTU_MAX (251) + +/** + * Size of the storage area for Attribute values + * This value depends on the number of attributes used by application. In particular the sum of the following quantities (in octets) should be made for each attribute: + * - attribute value length + * - 5, if UUID is 16 bit; 19, if UUID is 128 bit + * - 2, if server configuration descriptor is used + * - 2*DTM_NUM_LINK, if client configuration descriptor is used + * - 2, if extended properties is used + * The total amount of memory needed is the sum of the above quantities for each attribute. + */ +#define CFG_BLE_ATT_VALUE_ARRAY_SIZE (1344) + +/** + * Maximum numbers of bearers that can be created for Enhanced ATT per ACL links + */ +#define CFG_BLE_EATT_BEARER_PER_LINK (0) + +/** + * depth of the PREPARE WRITE queue when PREPARE WRITE REQUEST + */ +#define CFG_BLE_ATTR_PREPARE_WRITE_VALUE_SIZE (30) + +#define CFG_BLE_MBLOCK_COUNT_MARGIN (0x15) + +#define PREP_WRITE_LIST_SIZE (BLE_DEFAULT_PREP_WRITE_LIST_SIZE) + +/** + * Number of allocated memory blocks used to transmit and receive data packets + */ +#define CFG_BLE_MBLOCK_COUNT (BLE_MBLOCKS_CALC(PREP_WRITE_LIST_SIZE, \ + CFG_BLE_ATT_MTU_MAX, CFG_BLE_NUM_LINK) \ + + CFG_BLE_MBLOCK_COUNT_MARGIN) + +/** + * Appearance of device set into BLE GAP + */ +#define CFG_GAP_APPEARANCE (GAP_APPEARANCE_UNKNOWN) + +/** + * Connection Oriented Channel parameters + */ +#define CFG_BLE_COC_NBR_MAX (64) +#define CFG_BLE_COC_MPS_MAX (248) +#define CFG_BLE_COC_INITIATOR_NBR_MAX (32) + +/** + * PHY preferences + */ +#define CFG_PHY_PREF (0) +#define CFG_PHY_PREF_TX (HCI_TX_PHYS_LE_2M_PREF) +#define CFG_PHY_PREF_RX (HCI_RX_PHYS_LE_2M_PREF) + +/* USER CODE BEGIN BLE_Stack */ + +/* USER CODE END BLE_Stack */ + +/****************************************************************************** + * Low Power + * + * When CFG_LPM_LEVEL is set to: + * - 0 : Low Power Mode is not activated, RUN mode will be used. + * - 1 : Low power active, mode selected with CFG_LPM_STDBY_SUPPORTED + * - 2 : In addition log and debug are disabled to reach lowest power figures. + * + * When CFG_LPM_STDBY_SUPPORTED is set to: + * - 2 : Stop mode 2 is used as low power mode (if supported by target) + * - 1 : Standby is used as low power mode. + * - 0 : Stop mode 1 is used as low power mode. + * + ******************************************************************************/ +#define CFG_LPM_LEVEL (1) +#define CFG_LPM_STDBY_SUPPORTED (1) + +/** + * Defines to use dynamic low power wakeup time profilling. + * With this option at boot wake up time is profiled and then is used. + */ +#define CFG_LPM_WAKEUP_TIME_PROFILING (1) + +/** + * Defines time to wake up from standby before radio event to meet timings + * This value will be dynamically updated when using CFG_LPM_WAKEUP_TIME_PROFILING + */ +#define CFG_LPM_STDBY_WAKEUP_TIME (1500) + +/* USER CODE BEGIN Low_Power 0 */ + +/* USER CODE END Low_Power 0 */ + +/** + * Supported requester to the MCU Low Power Manager - can be increased up to 32 + * It list a bit mapping of all user of the Low Power Manager + */ +typedef enum +{ + CFG_LPM_APP, + CFG_LPM_LOG, + CFG_LPM_LL_DEEPSLEEP, + CFG_LPM_LL_HW_RCO_CLBR, + CFG_LPM_APP_BLE, + /* USER CODE BEGIN CFG_LPM_Id_t */ + + /* USER CODE END CFG_LPM_Id_t */ +} CFG_LPM_Id_t; + +/* USER CODE BEGIN Low_Power 1 */ + +/* USER CODE END Low_Power 1 */ + +/****************************************************************************** + * RTC + ******************************************************************************/ + +/* USER CODE BEGIN RTC */ + +/* USER CODE END RTC */ + +/***************************************************************************** + * Logs + * + * Applications must call LOG_INFO_APP for logs. + * By default, CFG_LOG_INSERT_TIME_STAMP_INSIDE_THE_TRACE is set to 0. + * As a result, there is no time stamp insertion inside the logs. + * + * For advanced log use cases, see the log_module.h file. + * This file is customizable, you can create new verbose levels and log regions. + *****************************************************************************/ +/** + * Enable or disable LOG over UART in the application. + * Low power level(CFG_LPM_LEVEL) above 1 will disable LOG. + * Standby low power mode(CFG_LPM_STDBY_SUPPORTED) above 0 will disable LOG. + */ +#define CFG_LOG_SUPPORTED (0U) + +extern UART_HandleTypeDef huart1; +#define LOG_UART_HANDLER huart1 + +/* Configure Log display settings */ +#define CFG_LOG_INSERT_COLOR_INSIDE_THE_TRACE (0U) +#define CFG_LOG_INSERT_TIME_STAMP_INSIDE_THE_TRACE (0U) +#define CFG_LOG_INSERT_EOL_INSIDE_THE_TRACE (0U) + +#define CFG_LOG_TRACE_FIFO_SIZE (4096U) +#define CFG_LOG_TRACE_BUF_SIZE (256U) + +/* USER CODE BEGIN Logs */ + +/* USER CODE END Logs */ + +/****************************************************************************** + * Configure Log level for Application + * + * APPLI_CONFIG_LOG_LEVEL can be any value of the Log_Verbose_Level_t enum. + * + * APPLI_CONFIG_LOG_REGION can either be : + * - LOG_REGION_ALL_REGIONS to enable all regions + * or + * - One or several specific regions (any value except LOG_REGION_ALL_REGIONS) + * from the Log_Region_t enum and matching the mask value. + * + * For example, to enable both LOG_REGION_BLE and LOG_REGION_APP, + * the value assigned to the define is : + * (1U << LOG_REGION_BLE | 1U << LOG_REGION_APP) + ******************************************************************************/ +#define APPLI_CONFIG_LOG_LEVEL LOG_VERBOSE_INFO +#define APPLI_CONFIG_LOG_REGION (LOG_REGION_ALL_REGIONS) +/* USER CODE BEGIN Log_level */ + +/* USER CODE END Log_level */ + +/****************************************************************************** + * Sequencer + ******************************************************************************/ + +/** + * These are the lists of task id registered to the sequencer + * Each task id shall be in the range [0:31] + */ +typedef enum +{ + CFG_TASK_HW_RNG, + CFG_TASK_LINK_LAYER, + CFG_TASK_BLE_HCI_CMD_ID, + CFG_TASK_SYS_HCI_CMD_ID, + CFG_TASK_HCI_ACL_DATA_ID, + CFG_TASK_SYS_LOCAL_CMD_ID, + CFG_TASK_TX_TO_HOST_ID, + CFG_TASK_NOTIFY_EVENT_ID, + CFG_TASK_TEMP_MEAS, + CFG_TASK_BLE_HOST, + CFG_TASK_AMM, + CFG_TASK_BPKA, + CFG_TASK_BLE_TIMER_BCKGND, + CFG_TASK_FLASH_MANAGER, + /* USER CODE BEGIN CFG_Task_Id_t */ + TASK_BUTTON_1, + TASK_BUTTON_2, + TASK_BUTTON_3, + /* USER CODE END CFG_Task_Id_t */ + CFG_TASK_NBR /* Shall be LAST in the list */ +} CFG_Task_Id_t; + +/* USER CODE BEGIN DEFINE_TASK */ + +/* USER CODE END DEFINE_TASK */ + +/** + * This is the list of priority required by the application + * Shall be in the range 0..31 + */ +typedef enum +{ + CFG_SEQ_PRIO_0 = 0, + CFG_SEQ_PRIO_1, + /* USER CODE BEGIN CFG_SEQ_Prio_Id_t */ + + /* USER CODE END CFG_SEQ_Prio_Id_t */ + CFG_SEQ_PRIO_NBR /* Shall be LAST in the list */ +} CFG_SEQ_Prio_Id_t; + +/* Sequencer configuration */ +#define UTIL_SEQ_CONF_PRIO_NBR CFG_SEQ_PRIO_NBR + +/** + * These are the lists of events id registered to the sequencer + * Each event id shall be in the range [0:31] + */ +typedef enum +{ + /* USER CODE BEGIN CFG_Event_Id_t */ + + /* USER CODE END CFG_Event_Id_t */ + CFG_EVENT_NBR /* Shall be LAST in the list */ +} CFG_Event_Id_t; + +/**< Events defines */ +/* USER CODE BEGIN EVENT_ID_Define */ + +/* USER CODE END EVENT_ID_Define */ + +/****************************************************************************** + * NVM configuration + ******************************************************************************/ + +#define CFG_SNVMA_START_SECTOR_ID ((FLASH_SIZE / FLASH_PAGE_SIZE) - 2u) + +#define CFG_SNVMA_START_ADDRESS (FLASH_BASE + (FLASH_PAGE_SIZE * (CFG_SNVMA_START_SECTOR_ID))) + +/* Number of 64-bit words in NVM flash area */ +#define CFG_BLE_NVM_SIZE_MAX ((2048/8)-4) + +/* USER CODE BEGIN NVM_Configuration */ + +/* USER CODE END NVM_Configuration */ + +/****************************************************************************** + * Debugger + * + * When CFG_DEBUGGER_LEVEL is set to: + * - 0 : No Debugger available, SWD/JTAG pins are disabled. + * - 1 : Debugger available in RUN mode only. + * - 2 : Debugger available in low power mode. + * + ******************************************************************************/ +#define CFG_DEBUGGER_LEVEL (2) + +/****************************************************************************** + * RealTime GPIO debug module configuration + ******************************************************************************/ + +#define CFG_RT_DEBUG_GPIO_MODULE (0) +#define CFG_RT_DEBUG_DTB (0) + +/****************************************************************************** + * System Clock Manager module configuration + * + * When CFG_SCM_SUPPORTED is set to: + * - 0 : System Clock Manager is disabled and user must handle himself + * all clock management, taking care of radio requirements. + * (radio operation requires HSE 32MHz with Voltage Scaling Range 1) + * - 1 : System Clock Manager ensures proper clock settings and switchings + * according to radio requirements and user preferences + * + ******************************************************************************/ +#define CFG_SCM_SUPPORTED (0) + +/****************************************************************************** + * HW RADIO configuration + ******************************************************************************/ +/* Link Layer uses temperature based calibration (0 --> NO ; 1 --> YES) */ +#ifndef USE_TEMPERATURE_BASED_RADIO_CALIBRATION +#define USE_TEMPERATURE_BASED_RADIO_CALIBRATION (1) +#endif + +#define RADIO_INTR_NUM RADIO_IRQn /* 2.4GHz RADIO global interrupt */ +#define RADIO_INTR_PRIO_HIGH (0) /* 2.4GHz RADIO interrupt priority when radio is Active */ +#define RADIO_INTR_PRIO_LOW (5) /* 2.4GHz RADIO interrupt priority when radio is Not Active - Sleep Timer Only */ + +#define RADIO_SW_LOW_INTR_NUM HASH_IRQn /* Selected interrupt vector for 2.4GHz RADIO low ISR */ +#ifndef __ZEPHYR__ +#define RADIO_SW_LOW_INTR_PRIO (15) /* 2.4GHz RADIO low ISR priority */ +#else +#define RADIO_SW_LOW_INTR_PRIO (14) /* 2.4GHz RADIO low ISR priority */ +#endif +#define RCC_INTR_PRIO (1) /* HSERDY and PLL1RDY */ + +/* RF TX power table ID selection: + * 0 -> RF TX output level from -20 dBm to +10 dBm + * 1 -> RF TX output level from -20 dBm to +3 dBm + * 2 -> RF TX output level at +20 dBm with an external PA + */ +#define CFG_RF_TX_POWER_TABLE_ID (0) + +#define CFG_EXTERNAL_PA_ENABLE (0) + +#define CFG_BLE_AOA_AOD_ENABLE (0) +#define CFG_RADIO_NUM_OF_ANTENNAS (8) /* Link Layer supported number of antennas */ + +/* Radio sleep clock LSE accuracy configuration */ +#define CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE (0x00) + +/* USER CODE BEGIN Radio_Configuration */ + +/* USER CODE END Radio_Configuration */ + +/****************************************************************************** + * HW_RNG configuration + ******************************************************************************/ + +/* Number of 32-bit random numbers stored in internal pool */ +#define CFG_HW_RNG_POOL_SIZE (32) + +/* Threshold of random numbers available before triggering pool refill */ +#define CFG_HW_RNG_POOL_THRESHOLD (16) + +/* USER CODE BEGIN HW_RNG_Configuration */ + +/* USER CODE END HW_RNG_Configuration */ + +/****************************************************************************** + * MEMORY MANAGER + ******************************************************************************/ + +#define CFG_MM_POOL_SIZE (4000U) /* bytes */ +#define CFG_AMM_VIRTUAL_MEMORY_NUMBER (2U) +#define CFG_AMM_VIRTUAL_STACK_BLE (1U) +#define CFG_AMM_VIRTUAL_STACK_BLE_BUFFER_SIZE (400U) /* words (32 bits) */ +#define CFG_AMM_VIRTUAL_APP_BLE (2U) +#define CFG_AMM_VIRTUAL_APP_BLE_BUFFER_SIZE (200U) /* words (32 bits) */ +#define CFG_AMM_POOL_SIZE ( DIVC(CFG_MM_POOL_SIZE, sizeof (uint32_t)) \ + + (AMM_VIRTUAL_INFO_ELEMENT_SIZE * CFG_AMM_VIRTUAL_MEMORY_NUMBER) ) + +/* USER CODE BEGIN MEMORY_MANAGER_Configuration */ + +/* USER CODE END MEMORY_MANAGER_Configuration */ + +/* USER CODE BEGIN Defines */ +/** + * User interaction + * When CFG_LED_SUPPORTED is set, LEDS are activated if requested + * When CFG_BUTTON_SUPPORTED is set, the push button are activated if requested + */ + +#define CFG_LED_SUPPORTED (1) +#define CFG_BUTTON_SUPPORTED (1) + +/** + * Overwrite some configuration imposed by Low Power level selected. + */ +#if (CFG_LPM_LEVEL > 1) + #if CFG_LED_SUPPORTED + #undef CFG_LED_SUPPORTED + #define CFG_LED_SUPPORTED (0) + #endif /* CFG_LED_SUPPORTED */ +#endif /* CFG_LPM_LEVEL */ + +/* USER CODE END Defines */ + +/** + * Overwrite some configuration imposed by Low Power level selected. + */ +#if (CFG_LPM_LEVEL > 1) + #if CFG_LOG_SUPPORTED + #undef CFG_LOG_SUPPORTED + #define CFG_LOG_SUPPORTED (0) + #endif /* CFG_LOG_SUPPORTED */ + #if CFG_DEBUGGER_LEVEL + #undef CFG_DEBUGGER_LEVEL + #define CFG_DEBUGGER_LEVEL (0) + #endif /* CFG_DEBUGGER_LEVEL */ +#endif /* CFG_LPM_LEVEL */ + +/* USER CODE BEGIN Defines_2 */ + +/* USER CODE END Defines_2 */ + +#endif /*APP_CONF_H */ diff --git a/lib/stm32wba/concurrent/Core/Inc/main.h b/lib/stm32wba/concurrent/Core/Inc/main.h new file mode 100644 index 000000000..d45421b94 --- /dev/null +++ b/lib/stm32wba/concurrent/Core/Inc/main.h @@ -0,0 +1,92 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" +#include "app_conf.h" +#include "app_common.h" + +#include "stm32wbaxx_ll_icache.h" +#include "stm32wbaxx_ll_tim.h" +#include "stm32wbaxx_ll_bus.h" +#include "stm32wbaxx_ll_cortex.h" +#include "stm32wbaxx_ll_rcc.h" +#include "stm32wbaxx_ll_system.h" +#include "stm32wbaxx_ll_utils.h" +#include "stm32wbaxx_ll_pwr.h" +#include "stm32wbaxx_ll_gpio.h" +#include "stm32wbaxx_ll_dma.h" + +#include "stm32wbaxx_ll_exti.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); +void MX_GPIO_Init(void); +void MX_GPDMA1_Init(void); +void MX_RAMCFG_Init(void); +void MX_RTC_Init(void); +void MX_USART1_UART_Init(void); +void MX_ADC4_Init(void); +void MX_CRC_Init(void); +void MX_ICACHE_Init(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/lib/stm32wba/concurrent/Core/Inc/utilities_conf.h b/lib/stm32wba/concurrent/Core/Inc/utilities_conf.h new file mode 100644 index 000000000..05d320779 --- /dev/null +++ b/lib/stm32wba/concurrent/Core/Inc/utilities_conf.h @@ -0,0 +1,178 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file utilities_conf.h + * @author MCD Application Team + * @brief Header for configuration file for STM32 Utilities. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef UTILITIES_CONF_H +#define UTILITIES_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cmsis_compiler.h" +#include "app_conf.h" +/* definitions to be provided to "sequencer" utility */ +#include "stm32_mem.h" +/* definition and callback for tiny_vsnprintf */ +#include "stm32_tiny_vsnprintf.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ + +#define VLEVEL_OFF 0 /*!< used to set UTIL_ADV_TRACE_SetVerboseLevel() (not as message param) */ +#define VLEVEL_ALWAYS 0 /*!< used as message params, if this level is given + trace will be printed even when UTIL_ADV_TRACE_SetVerboseLevel(OFF) */ +#define VLEVEL_L 1 /*!< just essential traces */ +#define VLEVEL_M 2 /*!< functional traces */ +#define VLEVEL_H 3 /*!< all traces */ + +#define TS_OFF 0 /*!< Log without TimeStamp */ +#define TS_ON 1 /*!< Log with TimeStamp */ + +#define T_REG_OFF 0 /*!< Log without bitmask */ + +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macros -----------------------------------------------------------*/ +/** + * @brief Memory placement macro + */ +#if defined(__CC_ARM) +#define UTIL_PLACE_IN_SECTION( __x__ ) __attribute__((section (__x__), zero_init)) +#elif defined(__ICCARM__) +#define UTIL_PLACE_IN_SECTION( __x__ ) __attribute__((section (__x__))) +#else /* __GNUC__ */ +#define UTIL_PLACE_IN_SECTION( __x__ ) __attribute__((section (__x__))) +#endif /* __CC_ARM | __ICCARM__ | __GNUC__ */ + +/** + * @brief Memory alignment macro + */ +#undef ALIGN +#ifdef WIN32 +#define ALIGN(n) +#else +#define ALIGN(n) __attribute__((aligned(n))) +#endif /* WIN32 */ + +/** + * @brief macro used to initialize the critical section + */ +#define UTIL_SEQ_INIT_CRITICAL_SECTION( ) UTILS_INIT_CRITICAL_SECTION() + +/** + * @brief macro used to enter the critical section + */ +#define UTIL_SEQ_ENTER_CRITICAL_SECTION( ) UTILS_ENTER_CRITICAL_SECTION() + +/** + * @brief macro used to exit the critical section + */ +#define UTIL_SEQ_EXIT_CRITICAL_SECTION( ) UTILS_EXIT_CRITICAL_SECTION() + +/** + * @brief Memset utilities interface to application + */ +#define UTIL_SEQ_MEMSET8( dest, value, size ) UTIL_MEM_set_8( dest, value, size ) + +/** + * @brief macro used to initialize the critical section + */ +#define UTILS_INIT_CRITICAL_SECTION() + +/** + * @brief macro used to enter the critical section + */ +#define UTILS_ENTER_CRITICAL_SECTION() uint32_t primask_bit= __get_PRIMASK();\ + __disable_irq() + +/** + * @brief macro used to exit the critical section + */ +#define UTILS_EXIT_CRITICAL_SECTION() __set_PRIMASK(primask_bit) + +/** + * @brief macro used to enter the critical section + */ +#define UTILS_ENTER_LIMITED_CRITICAL_SECTION(x) uint32_t basepri_value= __get_BASEPRI();\ + __set_BASEPRI_MAX(x) + +/** + * @brief macro used to exit the critical section + */ +#define UTILS_EXIT_LIMITED_CRITICAL_SECTION() __set_BASEPRI(basepri_value) + +/****************************************************************************** + * trace\advanced + * the define option + * UTIL_ADV_TRACE_CONDITIONNAL shall be defined if you want use conditional function + * UTIL_ADV_TRACE_UNCHUNK_MODE shall be defined if you want use the unchunk mode + * + ******************************************************************************/ + +#define UTIL_ADV_TRACE_CONDITIONNAL /*!< not used */ +#define UTIL_ADV_TRACE_UNCHUNK_MODE /*!< not used */ +#define UTIL_ADV_TRACE_DEBUG(...) /*!< not used */ +#define UTIL_ADV_TRACE_INIT_CRITICAL_SECTION( ) UTILS_INIT_CRITICAL_SECTION() /*!< init the critical section in trace feature */ +#define UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION( ) UTILS_ENTER_CRITICAL_SECTION() /*!< enter the critical section in trace feature */ +#define UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION( ) UTILS_EXIT_CRITICAL_SECTION() /*!< exit the critical section in trace feature */ +#define UTIL_ADV_TRACE_TMP_BUF_SIZE (CFG_LOG_TRACE_BUF_SIZE) /*!< trace buffer size */ +#define UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE (15U) /*!< trace timestamp size */ +#define UTIL_ADV_TRACE_FIFO_SIZE (CFG_LOG_TRACE_FIFO_SIZE) /*!< trace fifo size */ +#define UTIL_ADV_TRACE_MEMSET8( dest, value, size) UTIL_MEM_set_8((dest),(value),(size)) /*!< memset utilities interface to trace feature */ +#define UTIL_ADV_TRACE_VSNPRINTF(...) vsnprintf(__VA_ARGS__) /*!< vsnprintf utilities interface to trace feature */ + +/****************************************************************************** + * tiny low power manager + ******************************************************************************/ +/* Maximum number of supported LPM drivers */ +#define UTIL_LPM_DRIVER_MAX_NUM (10) +/* Enables LPM legacy APIs */ +#define UTIL_LPM_LEGACY_ENABLED (1) + +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /*UTILITIES_CONF_H */ diff --git a/lib/stm32wba/concurrent/STM32_WPAN/Target/bpka.c b/lib/stm32wba/concurrent/STM32_WPAN/Target/bpka.c new file mode 100644 index 000000000..cefe4bb92 --- /dev/null +++ b/lib/stm32wba/concurrent/STM32_WPAN/Target/bpka.c @@ -0,0 +1,223 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file bpka.c + * @author MCD Application Team + * @brief This file implements the BLE PKA module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#include "app_common.h" +#include "bpka.h" + +/*****************************************************************************/ + +enum +{ + BPKA_IDLE = 0, + BPKA_P256_KEY_GEN, + BPKA_RANGE_X_CHECK, + BPKA_RANGE_Y_CHECK, + BPKA_POINT_CHECK, + BPKA_DH_KEY_GEN, +}; + +/*****************************************************************************/ + +static uint8_t BPKA_state; +static uint8_t BPKA_error; +static uint32_t BPKA_buffer[24]; + +/*****************************************************************************/ + +void BPKA_Reset( void ) +{ + /* Disable PKA hardware */ + HW_PKA_Disable( ); + + BPKA_state = BPKA_IDLE; +} + +/*****************************************************************************/ + +int BPKA_StartP256Key( const uint32_t* local_private_key ) +{ + /* Enable PKA hardware */ + if ( ! HW_PKA_Enable( ) ) + return BPKA_BUSY; + + /* Call the PKA scalar multiplication with the local private key + as k and the standard point as starting point, + in order to compute the local public key */ + HW_PKA_P256_StartEccScalarMul( local_private_key, NULL, NULL ); + + BPKA_state = BPKA_P256_KEY_GEN; + + BPKACB_Process( ); + + return BPKA_OK; +} + +/*****************************************************************************/ + +void BPKA_ReadP256Key( uint32_t* local_public_key ) +{ + /* Get local public key from buffer */ + memcpy( local_public_key, BPKA_buffer, 64 ); +} + +/*****************************************************************************/ + +int BPKA_StartDhKey( const uint32_t* local_private_key, + const uint32_t* remote_public_key ) +{ + /* Enable PKA hardware */ + if ( ! HW_PKA_Enable( ) ) + return BPKA_BUSY; + + /* Call the PKA range check operation for public key X coordinate */ + HW_PKA_P256_StartRangeCheck( remote_public_key ); + + /* Save input data */ + memcpy( BPKA_buffer, local_private_key, 32 ); + memcpy( BPKA_buffer + 8, remote_public_key, 64 ); + + BPKA_state = BPKA_RANGE_X_CHECK; + BPKA_error = 1; + + BPKACB_Process( ); + + return BPKA_OK; +} + +/*****************************************************************************/ + +int BPKA_ReadDhKey( uint32_t* dh_key ) +{ + if ( BPKA_error ) + return BPKA_EOF; + + /* Get DH key from buffer */ + memcpy( dh_key, BPKA_buffer, 32 ); + + return BPKA_OK; +} + +/*****************************************************************************/ + +__WEAK void BPKACB_Complete( void ) +{ +} + +__WEAK void BPKACB_Process( void ) +{ +} + +/*****************************************************************************/ + +int BPKA_Process( void ) +{ + /* This function implements the offline key computation using the PKA + */ + if ( BPKA_state == BPKA_IDLE ) + { + return BPKA_OK; + } + + /* Check if the current operation is finished */ + if ( ! HW_PKA_EndOfOperation( ) ) + return BPKA_BUSY; + + switch ( BPKA_state ) + { + case BPKA_P256_KEY_GEN: + + /* Read the PKA scalar multiplication result which is the local public + key */ + HW_PKA_P256_ReadEccScalarMul( BPKA_buffer, BPKA_buffer + 8 ); + + break; + + case BPKA_RANGE_X_CHECK: + + /* Test result of range check operation for public key X coordinate */ + if ( ! HW_PKA_P256_IsRangeCheckOk( ) ) + break; + + /* Call the PKA range check operation for public key Y coordinate */ + HW_PKA_P256_StartRangeCheck( BPKA_buffer + 16 ); + + BPKA_state = BPKA_RANGE_Y_CHECK; + + return BPKA_BUSY; + + case BPKA_RANGE_Y_CHECK: + + /* Test result of range check operation for public key Y coordinate */ + if ( ! HW_PKA_P256_IsRangeCheckOk( ) ) + break; + + /* Call the PKA point check operation for remote public key */ + HW_PKA_P256_StartPointCheck( BPKA_buffer + 8, + BPKA_buffer + 16 ); + + BPKA_state = BPKA_POINT_CHECK; + + return BPKA_BUSY; + + case BPKA_POINT_CHECK: + + /* Test result of point check operation for remote public key */ + if ( ! HW_PKA_P256_IsPointCheckOk( ) ) + break; + + /* Call the PKA scalar multiplication with the local private key + as k and the remote public key as starting point, + in order to compute the DH key */ + HW_PKA_P256_StartEccScalarMul( BPKA_buffer, + BPKA_buffer + 8, + BPKA_buffer + 16 ); + + BPKA_state = BPKA_DH_KEY_GEN; + + return BPKA_BUSY; + + case BPKA_DH_KEY_GEN: + + /* Read the PKA scalar multiplication result which is the DH key */ + HW_PKA_P256_ReadEccScalarMul( BPKA_buffer, NULL ); + + BPKA_error = 0; + + break; + } + + /* Callback to inform the BLE stack of the completion of PKA operation */ + BPKACB_Complete( ); + + /* End of process: reset the PKA module */ + BPKA_Reset( ); + + return BPKA_OK; +} + +void BPKA_BG_Process( void ) +{ + if( BPKA_Process( ) != 0) + { + BPKACB_Process( ); + } +} + +/*****************************************************************************/ diff --git a/lib/stm32wba/concurrent/STM32_WPAN/Target/bpka.h b/lib/stm32wba/concurrent/STM32_WPAN/Target/bpka.h new file mode 100644 index 000000000..d591e670b --- /dev/null +++ b/lib/stm32wba/concurrent/STM32_WPAN/Target/bpka.h @@ -0,0 +1,59 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file bpka.h + * @author MCD Application Team + * @brief This file contains the interface of the BLE PKA module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#ifndef BPKA_H__ +#define BPKA_H__ + +#include + +/* Enumerated values used for the return of the functions: + * (warning: this enum must be aligned with BLEPLAT corresponding one) + */ +enum +{ + BPKA_OK = 0, + BPKA_FULL = -1, + BPKA_BUSY = -2, + BPKA_EOF = -3, + BPKA_ERROR = -5 +}; + +void BPKA_Reset( void ); + +int BPKA_StartP256Key( const uint32_t* local_private_key ); + +void BPKA_ReadP256Key( uint32_t* local_public_key ); + +int BPKA_StartDhKey( const uint32_t* local_private_key, + const uint32_t* remote_public_key ); + +int BPKA_ReadDhKey( uint32_t* dh_key ); + +int BPKA_Process( void ); + +void BPKA_BG_Process( void ); + +/* Callback used by BPKA_Process to indicate the end of the processing + */ +void BPKACB_Complete( void ); + +void BPKACB_Process( void ); + +#endif /* BPKA_H__ */ diff --git a/lib/stm32wba/concurrent/STM32_WPAN/Target/linklayer_plat.c b/lib/stm32wba/concurrent/STM32_WPAN/Target/linklayer_plat.c new file mode 100644 index 000000000..3472b384d --- /dev/null +++ b/lib/stm32wba/concurrent/STM32_WPAN/Target/linklayer_plat.c @@ -0,0 +1,628 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file linklayer_plat.c + * @author MCD Application Team + * @brief Source file for the linklayer plateform adaptation layer + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#include "stm32wbaxx_hal.h" +#include "stm32wbaxx_hal_conf.h" +#include "stm32wbaxx_ll_rcc.h" + +#include "app_common.h" +#include "app_conf.h" +#include "linklayer_plat.h" +#include "log_module.h" + +#ifndef __ZEPHYR__ +#if (CFG_LPM_LEVEL != 0) +#include "stm32_lpm.h" +#include "stm32_lpm_if.h" +#endif /* (CFG_LPM_LEVEL != 0) */ +#endif + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +#ifndef __ZEPHYR__ +#define max(a,b) ((a) > (b) ? a : b) + +/* 2.4GHz RADIO ISR callbacks */ +void (*radio_callback)(void) = NULL; +void (*low_isr_callback)(void) = NULL; + +/* RNG handle */ +extern RNG_HandleTypeDef hrng; + +/* Radio critical sections */ +static uint32_t primask_bit = 0; +volatile int32_t prio_high_isr_counter = 0; +volatile int32_t prio_low_isr_counter = 0; +volatile int32_t prio_sys_isr_counter = 0; +volatile int32_t irq_counter = 0; +volatile uint32_t local_basepri_value = 0; + +/* Radio SW low ISR global variable */ +volatile uint8_t radio_sw_low_isr_is_running_high_prio = 0; +#endif /* __ZEPHYR__ */ + +/* Radio bus clock control variables */ +uint8_t AHB5_SwitchedOff = 0; +uint32_t radio_sleep_timer_val = 0; + +/** + * @brief Configure the necessary clock sources for the radio. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_ClockInit(void) +{ +#ifndef __ZEPHYR__ + uint32_t linklayer_slp_clk_src = LL_RCC_RADIOSLEEPSOURCE_NONE; + + /* Get the Link Layer sleep timer clock source */ + linklayer_slp_clk_src = LL_RCC_RADIO_GetSleepTimerClockSource(); + if(linklayer_slp_clk_src == LL_RCC_RADIOSLEEPSOURCE_NONE) + { + /* If there is no clock source defined, should be selected before */ + assert_param(0); + } +#else + LINKLAYER_PLAT_EnableBackupDomainAccess(); + + /* Select LSE as Sleep CLK */ + __HAL_RCC_RADIOSLPTIM_CONFIG(RCC_RADIOSTCLKSOURCE_LSE); + + LINKLAYER_PLAT_DisableBackupDomainAccess(); +#endif + + /* Enable AHB5ENR peripheral clock (bus CLK) */ + __HAL_RCC_RADIO_CLK_ENABLE(); +} +#ifndef __ZEPHYR__ +/** + * @brief Link Layer active waiting loop. + * @param delay: delay in us + * @retval None + */ +void LINKLAYER_PLAT_DelayUs(uint32_t delay) +{ + static uint8_t lock = 0; + uint32_t t0; + uint32_t primask_bit; + + /* Enter critical section */ + primask_bit= __get_PRIMASK(); + __disable_irq(); + + if (lock == 0U) + { + /* Initialize counter */ + /* Reset cycle counter to prevent overflow + As a us counter, it is assumed than even with re-entrancy, + overflow will never happen before re-initializing this counter */ + DWT->CYCCNT = 0U; + /* Enable DWT by safety but should be useless (as already set) */ + SET_BIT(DCB->DEMCR, DCB_DEMCR_TRCENA_Msk); + /* Enable counter */ + SET_BIT(DWT->CTRL, DWT_CTRL_CYCCNTENA_Msk); + } + /* Increment 're-entrance' counter */ + lock++; + /* Get starting time stamp */ + t0 = DWT->CYCCNT; + /* Exit critical section */ + __set_PRIMASK(primask_bit); + + /* Turn us into cycles */ + delay = delay * (SystemCoreClock / 1000000U); + delay += t0; + + /* Busy waiting loop */ + while (DWT->CYCCNT < delay) + { + }; + + /* Enter critical section */ + primask_bit= __get_PRIMASK(); + __disable_irq(); + if (lock == 1U) + { + /* Disable counter */ + CLEAR_BIT(DWT->CTRL, DWT_CTRL_CYCCNTENA_Msk); + } + /* Decrement 're-entrance' counter */ + lock--; + /* Exit critical section */ + __set_PRIMASK(primask_bit); + +} + +/** + * @brief Link Layer assertion API + * @param condition: conditional statement to be checked. + * @retval None + */ +void LINKLAYER_PLAT_Assert(uint8_t condition) +{ + assert_param(condition); +} +#endif /* __ZEPHYR__ */ + +/** + * @brief Enable/disable the Link Layer active clock (baseband clock). + * @param enable: boolean value to enable (1) or disable (0) the clock. + * @retval None + */ +void LINKLAYER_PLAT_WaitHclkRdy(void) +{ + /* Wait on radio bus clock readiness if it has been turned of */ + if (AHB5_SwitchedOff == 1) + { + AHB5_SwitchedOff = 0; + while (radio_sleep_timer_val == ll_intf_cmn_get_slptmr_value()); + } +} + +/** + * @brief Notify the Link Layer platform layer the system will enter in WFI + * and AHB5 clock may be turned of regarding the 2.4Ghz radio state. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_NotifyWFIEnter(void) +{ + /* Check if Radio state will allow the AHB5 clock to be cut */ + + /* AHB5 clock will be cut in the following cases: + * - 2.4GHz radio is not in ACTIVE mode (in SLEEP or DEEPSLEEP mode). + * - RADIOSMEN and STRADIOCLKON bits are at 0. + */ + if((LL_PWR_GetRadioMode() != LL_PWR_RADIO_ACTIVE_MODE) || + ((__HAL_RCC_RADIO_IS_CLK_SLEEP_ENABLED() == 0) && (LL_RCC_RADIO_IsEnabledSleepTimerClock() == 0))) + { + AHB5_SwitchedOff = 1; + } +} + +/** + * @brief Notify the Link Layer platform layer the system exited WFI and AHB5 + * clock may be resynchronized as is may have been turned of during + * low power mode entry. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_NotifyWFIExit(void) +{ + /* Check if AHB5 clock has been turned of and needs resynchronisation */ + if (AHB5_SwitchedOff) + { + /* Read sleep register as earlier as possible */ + radio_sleep_timer_val = ll_intf_cmn_get_slptmr_value(); + } +} + +/** + * @brief Active wait on bus clock readiness. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_AclkCtrl(uint8_t enable) +{ + if(enable){ + /* Enable RADIO baseband clock (active CLK) */ + HAL_RCCEx_EnableRadioBBClock(); + + /* Polling on HSE32 activation */ + while ( LL_RCC_HSE_IsReady() == 0); + } + else + { + /* Disable RADIO baseband clock (active CLK) */ + HAL_RCCEx_DisableRadioBBClock(); + } +} + +#ifndef __ZEPHYR__ +/** + * @brief Link Layer RNG request. + * @param ptr_rnd: pointer to the variable that hosts the number. + * @param len: number of byte of anthropy to get. + * @retval None + */ +void LINKLAYER_PLAT_GetRNG(uint8_t *ptr_rnd, uint32_t len) +{ + uint32_t nb_remaining_rng = len; + uint32_t generated_rng; + + /* Get the requested RNGs (4 bytes by 4bytes) */ + while(nb_remaining_rng >= 4) + { + generated_rng = 0; + HW_RNG_Get(1, &generated_rng); + memcpy((ptr_rnd+(len-nb_remaining_rng)), &generated_rng, 4); + nb_remaining_rng -=4; + } + + /* Get the remaining number of RNGs */ + if(nb_remaining_rng>0){ + generated_rng = 0; + HW_RNG_Get(1, &generated_rng); + memcpy((ptr_rnd+(len-nb_remaining_rng)), &generated_rng, nb_remaining_rng); + } +} + +/** + * @brief Initialize Link Layer radio high priority interrupt. + * @param intr_cb: function pointer to assign for the radio high priority ISR routine. + * @retval None + */ +void LINKLAYER_PLAT_SetupRadioIT(void (*intr_cb)()) +{ + radio_callback = intr_cb; + HAL_NVIC_SetPriority((IRQn_Type) RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH, 0); + HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_INTR_NUM); +} + +/** + * @brief Initialize Link Layer SW low priority interrupt. + * @param intr_cb: function pointer to assign for the SW low priority ISR routine. + * @retval None + */ +void LINKLAYER_PLAT_SetupSwLowIT(void (*intr_cb)()) +{ + low_isr_callback = intr_cb; + + HAL_NVIC_SetPriority((IRQn_Type) RADIO_SW_LOW_INTR_NUM, RADIO_SW_LOW_INTR_PRIO, 0); + HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_SW_LOW_INTR_NUM); +} + +/** + * @brief Trigger the link layer SW low interrupt. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_TriggerSwLowIT(uint8_t priority) +{ + uint8_t low_isr_priority = RADIO_INTR_PRIO_LOW; + + /* Check if a SW low interrupt as already been raised. + * Nested call far radio low isr are not supported + **/ + + if(NVIC_GetActive(RADIO_SW_LOW_INTR_NUM) == 0) + { + /* No nested SW low ISR, default behavior */ + + if(priority == 0) + { + low_isr_priority = RADIO_SW_LOW_INTR_PRIO; + } + + HAL_NVIC_SetPriority((IRQn_Type) RADIO_SW_LOW_INTR_NUM, low_isr_priority, 0); + } + else + { + /* Nested call detected */ + /* No change for SW radio low interrupt priority for the moment */ + + if(priority != 0) + { + /* At the end of current SW radio low ISR, this pending SW low interrupt + * will run with RADIO_INTR_PRIO_LOW priority + **/ + radio_sw_low_isr_is_running_high_prio = 1; + } + } + + HAL_NVIC_SetPendingIRQ((IRQn_Type) RADIO_SW_LOW_INTR_NUM); +} + +/** + * @brief Enable interrupts. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_EnableIRQ(void) +{ + irq_counter = max(0,irq_counter-1); + + if(irq_counter == 0) + { + /* When irq_counter reaches 0, restore primask bit */ + __set_PRIMASK(primask_bit); + } +} + +/** + * @brief Disable interrupts. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_DisableIRQ(void) +{ + if(irq_counter == 0) + { + /* Save primask bit at first interrupt disablement */ + primask_bit= __get_PRIMASK(); + } + __disable_irq(); + irq_counter ++; +} + +/** + * @brief Enable specific interrupt group. + * @param isr_type: mask for interrupt group to enable. + * This parameter can be one of the following: + * @arg LL_HIGH_ISR_ONLY: enable link layer high priority ISR. + * @arg LL_LOW_ISR_ONLY: enable link layer SW low priority ISR. + * @arg SYS_LOW_ISR: mask interrupts for all the other system ISR with + * lower priority that link layer SW low interrupt. + * @retval None + */ +void LINKLAYER_PLAT_EnableSpecificIRQ(uint8_t isr_type) +{ + if( (isr_type & LL_HIGH_ISR_ONLY) != 0 ) + { + prio_high_isr_counter--; + if(prio_high_isr_counter == 0) + { + /* When specific counter for link layer high ISR reaches 0, interrupt is enabled */ + HAL_NVIC_EnableIRQ(RADIO_INTR_NUM); + /* USER CODE BEGIN LINKLAYER_PLAT_EnableSpecificIRQ_1 */ + + /* USER CODE END LINKLAYER_PLAT_EnableSpecificIRQ_1 */ + } + } + + if( (isr_type & LL_LOW_ISR_ONLY) != 0 ) + { + prio_low_isr_counter--; + if(prio_low_isr_counter == 0) + { + /* When specific counter for link layer SW low ISR reaches 0, interrupt is enabled */ + HAL_NVIC_EnableIRQ(RADIO_SW_LOW_INTR_NUM); + } + + } + + if( (isr_type & SYS_LOW_ISR) != 0 ) + { + prio_sys_isr_counter--; + if(prio_sys_isr_counter == 0) + { + /* Restore basepri value */ + __set_BASEPRI(local_basepri_value); + } + } +} + +/** + * @brief Disable specific interrupt group. + * @param isr_type: mask for interrupt group to disable. + * This parameter can be one of the following: + * @arg LL_HIGH_ISR_ONLY: disable link layer high priority ISR. + * @arg LL_LOW_ISR_ONLY: disable link layer SW low priority ISR. + * @arg SYS_LOW_ISR: unmask interrupts for all the other system ISR with + * lower priority that link layer SW low interrupt. + * @retval None + */ +void LINKLAYER_PLAT_DisableSpecificIRQ(uint8_t isr_type) +{ + if( (isr_type & LL_HIGH_ISR_ONLY) != 0 ) + { + prio_high_isr_counter++; + if(prio_high_isr_counter == 1) + { + /* USER CODE BEGIN LINKLAYER_PLAT_DisableSpecificIRQ_1 */ + + /* USER CODE END LINKLAYER_PLAT_DisableSpecificIRQ_1 */ + /* When specific counter for link layer high ISR value is 1, interrupt is disabled */ + HAL_NVIC_DisableIRQ(RADIO_INTR_NUM); + } + } + + if( (isr_type & LL_LOW_ISR_ONLY) != 0 ) + { + prio_low_isr_counter++; + if(prio_low_isr_counter == 1) + { + /* When specific counter for link layer SW low ISR value is 1, interrupt is disabled */ + HAL_NVIC_DisableIRQ(RADIO_SW_LOW_INTR_NUM); + } + } + + if( (isr_type & SYS_LOW_ISR) != 0 ) + { + prio_sys_isr_counter++; + if(prio_sys_isr_counter == 1) + { + /* Save basepri register value */ + local_basepri_value = __get_BASEPRI(); + + /* Mask all other interrupts with lower priority that link layer SW low ISR */ + __set_BASEPRI_MAX(RADIO_INTR_PRIO_LOW<<4); + } + } +} + +/** + * @brief Enable link layer high priority ISR only. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_EnableRadioIT(void) +{ + /* USER CODE BEGIN LINKLAYER_PLAT_EnableRadioIT_1 */ + + /* USER CODE END LINKLAYER_PLAT_EnableRadioIT_1 */ + + HAL_NVIC_EnableIRQ((IRQn_Type) RADIO_INTR_NUM); + + /* USER CODE BEGIN LINKLAYER_PLAT_EnableRadioIT_2 */ + + /* USER CODE END LINKLAYER_PLAT_EnableRadioIT_2 */ +} + +/** + * @brief Disable link layer high priority ISR only. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_DisableRadioIT(void) +{ + /* USER CODE BEGIN LINKLAYER_PLAT_DisableRadioIT_1 */ + + /* USER CODE END LINKLAYER_PLAT_DisableRadioIT_1 */ + + HAL_NVIC_DisableIRQ((IRQn_Type) RADIO_INTR_NUM); + + /* USER CODE BEGIN LINKLAYER_PLAT_DisableRadioIT_2 */ + + /* USER CODE END LINKLAYER_PLAT_DisableRadioIT_2 */ +} + +/** + * @brief Link Layer notification for radio activity start. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_StartRadioEvt(void) +{ + __HAL_RCC_RADIO_CLK_SLEEP_ENABLE(); + NVIC_SetPriority(RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH); +} + +/** + * @brief Link Layer notification for radio activity end. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_StopRadioEvt(void) +{ + __HAL_RCC_RADIO_CLK_SLEEP_DISABLE(); + NVIC_SetPriority(RADIO_INTR_NUM, RADIO_INTR_PRIO_LOW); +} + +/** + * @brief Link Layer notification for RCO calibration start. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_RCOStartClbr(void) +{ +#if (CFG_LPM_LEVEL != 0) + PWR_DisableSleepMode(); + /* Disabling stop mode prevents also from entering in standby */ + UTIL_LPM_SetStopMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_DISABLE); +#endif /* (CFG_LPM_LEVEL != 0) */ +} + +/** + * @brief Link Layer notification for RCO calibration end. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_RCOStopClbr(void) +{ +#if (CFG_LPM_LEVEL != 0) + PWR_EnableSleepMode(); + UTIL_LPM_SetStopMode(1U << CFG_LPM_LL_HW_RCO_CLBR, UTIL_LPM_ENABLE); +#endif /* (CFG_LPM_LEVEL != 0) */ +} +#endif /*__ZEPHYR__*/ + +/** + * @brief Link Layer requests temperature. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_RequestTemperature(void) +{ +#if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) + ll_sys_bg_temperature_measurement(); +#endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */ +} + +/** + * @brief PHY Start calibration. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_PhyStartClbr(void) +{ + /* USER CODE BEGIN LINKLAYER_PLAT_PhyStartClbr_0 */ + + /* USER CODE END LINKLAYER_PLAT_PhyStartClbr_0 */ + + /* USER CODE BEGIN LINKLAYER_PLAT_PhyStartClbr_1 */ + + /* USER CODE END LINKLAYER_PLAT_PhyStartClbr_1 */ +} + +/** + * @brief PHY Stop calibration. + * @param None + * @retval None + */ +void LINKLAYER_PLAT_PhyStopClbr(void) +{ + /* USER CODE BEGIN LINKLAYER_PLAT_PhyStopClbr_0 */ + + /* USER CODE END LINKLAYER_PLAT_PhyStopClbr_0 */ + + /* USER CODE BEGIN LINKLAYER_PLAT_PhyStopClbr_1 */ + + /* USER CODE END LINKLAYER_PLAT_PhyStopClbr_1 */ +} + +#ifndef __ZEPHYR__ +/** + * @brief Notify the upper layer that new Link Layer timings have been applied. + * @param evnt_timing[in]: Evnt_timing_t pointer to structure contains drift time , execution time and scheduling time + * @retval None. + */ +void LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT(Evnt_timing_t * p_evnt_timing) +{ + /* USER CODE BEGIN LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT_0 */ + + /* USER CODE END LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT_0 */ +} + +/** + * @brief Get the ST company ID. + * @param None + * @retval Company ID + */ +uint32_t LINKLAYER_PLAT_GetSTCompanyID(void) +{ + return LL_FLASH_GetSTCompanyID(); +} + +/** + * @brief Get the Unique Device Number (UDN). + * @param None + * @retval UDN + */ +uint32_t LINKLAYER_PLAT_GetUDN(void) +{ + return LL_FLASH_GetUDN(); +} +#endif /* __ZEPHYR__ */ +/* USER CODE BEGIN LINKLAYER_PLAT 0 */ + +/* USER CODE END LINKLAYER_PLAT 0 */ diff --git a/lib/stm32wba/concurrent/STM32_WPAN/Target/ll_sys_if.c b/lib/stm32wba/concurrent/STM32_WPAN/Target/ll_sys_if.c new file mode 100644 index 000000000..967d3ba93 --- /dev/null +++ b/lib/stm32wba/concurrent/STM32_WPAN/Target/ll_sys_if.c @@ -0,0 +1,280 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file ll_sys_if.c + * @author MCD Application Team + * @brief Source file for initiating system + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +#include +#include "ll_intf.h" +#include "ll_intf_cmn.h" +#include "ll_sys.h" +#include "ll_sys_if.h" +#include "utilities_common.h" + +/* Private defines -----------------------------------------------------------*/ +/* Radio event scheduling method - must be set at 1 */ +#define USE_RADIO_LOW_ISR (1) +#define NEXT_EVENT_SCHEDULING_FROM_ISR (1) + +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macros ------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private constants ---------------------------------------------------------*/ +/* USER CODE BEGIN PC */ + +/* USER CODE END PC */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Global variables ----------------------------------------------------------*/ + +/* USER CODE BEGIN GV */ + +/* USER CODE END GV */ + +/* Private functions prototypes-----------------------------------------------*/ +#if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) +void ll_sys_bg_temperature_measurement_init(void); +#endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */ +static void ll_sys_sleep_clock_source_selection(void); +static uint8_t ll_sys_BLE_sleep_clock_accuracy_selection(void); +void ll_sys_reset(void); + +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +#ifndef __ZEPHYR__ +/* Functions Definition ------------------------------------------------------*/ + +/** + * @brief Link Layer background process initialization + * @param None + * @retval None + */ +void ll_sys_bg_process_init(void) +{ + /* Register Link Layer task */ + UTIL_SEQ_RegTask(1U << CFG_TASK_LINK_LAYER, UTIL_SEQ_RFU, ll_sys_bg_process); +} + +/** + * @brief Link Layer background process next iteration scheduling + * @param None + * @retval None + */ +void ll_sys_schedule_bg_process(void) +{ + UTIL_SEQ_SetTask(1U << CFG_TASK_LINK_LAYER, TASK_PRIO_LINK_LAYER); +} + +/** + * @brief Link Layer background process next iteration scheduling from ISR + * @param None + * @retval None + */ +void ll_sys_schedule_bg_process_isr(void) +{ + UTIL_SEQ_SetTask(1U << CFG_TASK_LINK_LAYER, TASK_PRIO_LINK_LAYER); +} +#endif + +/** + * @brief Link Layer configuration phase before application startup. + * @param None + * @retval None + */ +void ll_sys_config_params(void) +{ +/* USER CODE BEGIN ll_sys_config_params_0 */ + +/* USER CODE END ll_sys_config_params_0 */ + + /* Configure link layer behavior for low ISR use and next event scheduling method: + * - SW low ISR is used. + * - Next event is scheduled from ISR. + */ + ll_intf_cmn_config_ll_ctx_params(USE_RADIO_LOW_ISR, NEXT_EVENT_SCHEDULING_FROM_ISR); + /* Apply the selected link layer sleep timer source */ + ll_sys_sleep_clock_source_selection(); + +/* USER CODE BEGIN ll_sys_config_params_1 */ + +/* USER CODE END ll_sys_config_params_1 */ + +#if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) + /* Initialize link layer temperature measurement background task */ + ll_sys_bg_temperature_measurement_init(); + + /* Link layer IP uses temperature based calibration instead of periodic one */ + ll_intf_cmn_set_temperature_sensor_state(); +#endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */ + +#ifndef __ZEPHYR__ + /* Link Layer power table */ + ll_intf_cmn_select_tx_power_table(CFG_RF_TX_POWER_TABLE_ID); +#endif /*__ZEPHYR__*/ +/* USER CODE BEGIN ll_sys_config_params_2 */ + +/* USER CODE END ll_sys_config_params_2 */ +} + +uint8_t ll_sys_BLE_sleep_clock_accuracy_selection(void) +{ + uint8_t BLE_sleep_clock_accuracy = 0; +#if (CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE == 0) + uint32_t RevID = LL_DBGMCU_GetRevisionID(); +#endif + uint32_t linklayer_slp_clk_src = LL_RCC_RADIO_GetSleepTimerClockSource(); + + if(linklayer_slp_clk_src == LL_RCC_RADIOSLEEPSOURCE_LSE) + { + /* LSE selected as Link Layer sleep clock source. + Sleep clock accuracy is different regarding the WBA device ID and revision + */ +#if (CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE == 0) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) + if(RevID == REV_ID_A) + { + BLE_sleep_clock_accuracy = STM32WBA5x_REV_ID_A_SCA_RANGE; + } + else if(RevID == REV_ID_B) + { + BLE_sleep_clock_accuracy = STM32WBA5x_REV_ID_B_SCA_RANGE; + } + else + { + /* Revision ID not supported, default value of 500ppm applied */ + BLE_sleep_clock_accuracy = STM32WBA5x_DEFAULT_SCA_RANGE; + } +#elif defined(STM32WBA65xx) + BLE_sleep_clock_accuracy = STM32WBA6x_SCA_RANGE; + UNUSED(RevID); +#else + UNUSED(RevID); +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ +#else /* CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE */ + BLE_sleep_clock_accuracy = CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE; +#endif /* CFG_RADIO_LSE_SLEEP_TIMER_CUSTOM_SCA_RANGE */ + } + else + { + /* LSE is not the Link Layer sleep clock source, sleep clock accurcay default value is 500 ppm */ + BLE_sleep_clock_accuracy = STM32WBA5x_DEFAULT_SCA_RANGE; + } + + return BLE_sleep_clock_accuracy; +} + +void ll_sys_sleep_clock_source_selection(void) +{ + uint16_t freq_value = 0; + uint32_t linklayer_slp_clk_src = LL_RCC_RADIOSLEEPSOURCE_NONE; + + linklayer_slp_clk_src = LL_RCC_RADIO_GetSleepTimerClockSource(); + switch(linklayer_slp_clk_src) + { + case LL_RCC_RADIOSLEEPSOURCE_LSE: + linklayer_slp_clk_src = RTC_SLPTMR; + break; + + case LL_RCC_RADIOSLEEPSOURCE_LSI: + linklayer_slp_clk_src = RCO_SLPTMR; + break; + + case LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000: + linklayer_slp_clk_src = CRYSTAL_OSCILLATOR_SLPTMR; + break; + + case LL_RCC_RADIOSLEEPSOURCE_NONE: + /* No Link Layer sleep clock source selected */ + assert_param(0); + break; + } + ll_intf_cmn_le_select_slp_clk_src((uint8_t)linklayer_slp_clk_src, &freq_value); +} + +void ll_sys_reset(void) +{ + uint8_t bsca = 0; + /* Link layer timings */ + uint8_t drift_time = DRIFT_TIME_DEFAULT; + uint8_t exec_time = EXEC_TIME_DEFAULT; + +/* USER CODE BEGIN ll_sys_reset_0 */ + +/* USER CODE END ll_sys_reset_0 */ + + /* Apply the selected link layer sleep timer source */ + ll_sys_sleep_clock_source_selection(); + + /* Configure the link layer sleep clock accuracy */ + bsca = ll_sys_BLE_sleep_clock_accuracy_selection(); + ll_intf_le_set_sleep_clock_accuracy(bsca); + + /* Update link layer timings depending on selected configuration */ + if(LL_RCC_RADIO_GetSleepTimerClockSource() == LL_RCC_RADIOSLEEPSOURCE_LSI) + { + drift_time += DRIFT_TIME_EXTRA_LSI2; + exec_time += EXEC_TIME_EXTRA_LSI2; + } + else + { +#if defined(__GNUC__) && defined(DEBUG) + drift_time += DRIFT_TIME_EXTRA_GCC_DEBUG; + exec_time += EXEC_TIME_EXTRA_GCC_DEBUG; +#endif +#if defined (__ZEPHYR__) + drift_time += DRIFT_TIME_EXTRA_ZEPHYR; + exec_time += EXEC_TIME_EXTRA_ZEPHYR; +#endif + } + + /* USER CODE BEGIN ll_sys_reset_1 */ + + /* USER CODE END ll_sys_reset_1 */ + + if((drift_time != DRIFT_TIME_DEFAULT) || (exec_time != EXEC_TIME_DEFAULT)) + { + ll_sys_config_BLE_schldr_timings(drift_time, exec_time); + } + /* USER CODE BEGIN ll_sys_reset_2 */ + + /* USER CODE END ll_sys_reset_2 */ +} + +#ifndef __ZEPHYR__ +void ll_sys_set_rtl_polling_time(uint8_t rtl_polling_time) +{ + /* first parameter otInstance *aInstance is unused */ + radio_set_rtl_polling_time(NULL, rtl_polling_time); +} +#endif diff --git a/lib/stm32wba/concurrent/STM32_WPAN/Target/ll_sys_if.h b/lib/stm32wba/concurrent/STM32_WPAN/Target/ll_sys_if.h new file mode 100644 index 000000000..2c04c8b7b --- /dev/null +++ b/lib/stm32wba/concurrent/STM32_WPAN/Target/ll_sys_if.h @@ -0,0 +1,86 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file ll_sys_if.h + * @author MCD Application Team + * @brief Header file for initiating system + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LL_SYS_IF_H +#define LL_SYS_IF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +#define DRIFT_TIME_DEFAULT (13) +#define DRIFT_TIME_EXTRA_LSI2 (9) +#define DRIFT_TIME_EXTRA_GCC_DEBUG (6) +#ifdef __ZEPHYR__ +#define DRIFT_TIME_EXTRA_ZEPHYR (15) +#endif + +#define EXEC_TIME_DEFAULT (24) +#define EXEC_TIME_EXTRA_LSI2 (3) +#define EXEC_TIME_EXTRA_GCC_DEBUG (4) +#ifdef __ZEPHYR__ +#define EXEC_TIME_EXTRA_ZEPHYR (1) +#endif + +#define SCHDL_TIME_DEFAULT (20) +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* External variables --------------------------------------------------------*/ +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +#ifndef __ZEPHYR__ +void ll_sys_set_rtl_polling_time(uint8_t rtl_polling_time); +#endif +#if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) +void ll_sys_bg_temperature_measurement(void); +#endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /*LL_SYS_IF_H */ diff --git a/lib/stm32wba/concurrent/STM32_WPAN/Target/power_table.c b/lib/stm32wba/concurrent/STM32_WPAN/Target/power_table.c new file mode 100644 index 000000000..3741b02d3 --- /dev/null +++ b/lib/stm32wba/concurrent/STM32_WPAN/Target/power_table.c @@ -0,0 +1,119 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file power_table.c + * @author MCD Application Team + * @brief This file contains supported power tables + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "power_table.h" + +/* Private typedef -----------------------------------------------------------*/ + +/* VDD_LDO values to be written in PHY registers to select the TX_Power mode. + * g_vdd_ldo_value_1 : is to be set in PHY register address 0x63. + * g_vdd_ldo_value_2 : is to be set in PHY register address 0xEA. */ + +typedef enum _vdd_ldo_value_e { + VDD_LDO_VALUE_MAX_POWER = 0x70, + VDD_LDO_VALUE_LOW_POWER = 0x20, + VDD_LDO_VALUE_2_ID_0 = 0x00, +} vdd_ldo_value_e; + +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +const power_table_entry ll_tx_power_table_max_power[] = { + {0x02, 0x02, 0x01, -20}, /* Actual_Power = -20.4 dBm */ + {0x02, 0x03, 0x01, -19}, /* Actual_Power = -19.4 dBm */ + {0x02, 0x04, 0x01, -18}, /* Actual_Power = -18.3 dBm */ + {0x02, 0x05, 0x01, -17}, /* Actual_Power = -17.3 dBm */ + {0x02, 0x06, 0x01, -16}, /* Actual_Power = -16.4 dBm */ + {0x02, 0x07, 0x01, -15}, /* Actual_Power = -15.4 dBm */ + {0x02, 0x08, 0x01, -14}, /* Actual_Power = -14.3 dBm */ + {0x02, 0x09, 0x01, -13}, /* Actual_Power = -13.3 dBm */ + {0x02, 0x0A, 0x01, -12}, /* Actual_Power = -12.3 dBm */ + {0x02, 0x0B, 0x01, -11}, /* Actual_Power = -11.4 dBm */ + {0x02, 0x0C, 0x01, -10}, /* Actual_Power = -10.4 dBm */ + {0x02, 0x0D, 0x01, -9}, /* Actual_Power = -9.5 dBm */ + {0x02, 0x0E, 0x01, -8}, /* Actual_Power = -8.4 dBm */ + {0x00, 0x0F, 0x01, -7}, /* Actual_Power = -7.5 dBm */ + {0x00, 0x10, 0x01, -6}, /* Actual_Power = -6.5 dBm */ + {0x00, 0x11, 0x01, -5}, /* Actual_Power = -5.4 dBm */ + {0x00, 0x12, 0x01, -4}, /* Actual_Power = -4.5 dBm */ + {0x00, 0x13, 0x01, -3}, /* Actual_Power = -3.5 dBm */ + {0x02, 0x14, 0x01, -2}, /* Actual_Power = -2.4 dBm */ + {0x00, 0x15, 0x01, -1}, /* Actual_Power = -1.5 dBm */ + {0x02, 0x16, 0x01, 0}, /* Actual_Power = -0.3 dBm */ + {0x00, 0x17, 0x01, 1}, /* Actual_Power = 0.9 dBm */ + {0x00, 0x18, 0x01, 2}, /* Actual_Power = 2.3 dBm */ + {0x02, 0x18, 0x01, 3}, /* Actual_Power = 2.8 dBm */ + {0x00, 0x19, 0x01, 4}, /* Actual_Power = 3.9 dBm */ + {0x02, 0x19, 0x01, 5}, /* Actual_Power = 4.8 dBm */ + {0x03, 0x19, 0x01, 6}, /* Actual_Power = 5.6 dBm */ + {0x05, 0x19, 0x01, 7}, /* Actual_Power = 6.9 dBm */ + {0x06, 0x19, 0x01, 8}, /* Actual_Power = 7.5 dBm */ + {0x08, 0x19, 0x01, 9}, /* Actual_Power = 8.5 dBm */ + {0x0D, 0x19, 0x01, 10}, /* Actual_Power = 10 dBm */ +}; + +const power_table_entry ll_tx_power_table_low_power[] = { + {0x02, 0x02, 0x01, -20}, /* Actual_Power = -20.5 dBm */ + {0x02, 0x03, 0x01, -19}, /* Actual_Power = -19.5 dBm */ + {0x00, 0x05, 0x01, -18}, /* Actual_Power = -17.9 dBm */ + {0x00, 0x06, 0x01, -17}, /* Actual_Power = -17.0 dBm */ + {0x00, 0x07, 0x01, -16}, /* Actual_Power = -16.0 dBm */ + {0x00, 0x08, 0x01, -15}, /* Actual_Power = -15.0 dBm */ + {0x00, 0x09, 0x01, -14}, /* Actual_Power = -14.1 dBm */ + {0x00, 0x0A, 0x01, -13}, /* Actual_Power = -13.1 dBm */ + {0x00, 0x0B, 0x01, -12}, /* Actual_Power = -12.2 dBm */ + {0x00, 0x0C, 0x01, -11}, /* Actual_Power = -11.3 dBm */ + {0x00, 0x0D, 0x01, -10}, /* Actual_Power = -10.4 dBm */ + {0x00, 0x0E, 0x01, -9}, /* Actual_Power = -9.4 dBm */ + {0x00, 0x0F, 0x01, -8}, /* Actual_Power = -8.3 dBm */ + {0x00, 0x10, 0x01, -7}, /* Actual_Power = -7.2 dBm */ + {0x00, 0x11, 0x01, -6}, /* Actual_Power = -6.2 dBm */ + {0x00, 0x12, 0x01, -5}, /* Actual_Power = -5.5 dBm */ + {0x00, 0x13, 0x01, -4}, /* Actual_Power = -4.5 dBm */ + {0x02, 0x14, 0x01, -3}, /* Actual_Power = -3.5 dBm */ + {0x02, 0x15, 0x01, -2}, /* Actual_Power = -2.5 dBm */ + {0x00, 0x17, 0x01, -1}, /* Actual_Power = -0.6 dBm */ + {0x02, 0x17, 0x01, 0}, /* Actual_Power = -0.4 dBm */ + {0x00, 0x18, 0x01, 1}, /* Actual_Power = 0.7 dBm */ + {0x00, 0x19, 0x01, 2}, /* Actual_Power = 2.0 dBm */ + {0x02, 0x19, 0x01, 3}, /* Actual_Power = 2.6 dBm */ +}; + +/* USER CODE BEGIN ll_tx_power_table */ + +/* USER CODE END ll_tx_power_table */ + +/* Supported TX_Power tables. */ +const power_table_id_t ll_tx_power_tables[] = { + {ll_tx_power_table_max_power, sizeof(ll_tx_power_table_max_power)/sizeof(ll_tx_power_table_max_power[0]), VDD_LDO_VALUE_MAX_POWER, VDD_LDO_VALUE_2_ID_0, 0}, + {ll_tx_power_table_low_power, sizeof(ll_tx_power_table_low_power)/sizeof(ll_tx_power_table_low_power[0]), VDD_LDO_VALUE_LOW_POWER, VDD_LDO_VALUE_2_ID_0, 1}, + /* USER CODE BEGIN ll_tx_power_tables */ + + /* USER CODE END ll_tx_power_tables */ +}; + +/* Number of supported TX_Power tables. */ +const uint8_t num_of_supported_power_tables = sizeof(ll_tx_power_tables)/sizeof(ll_tx_power_tables[0]); + +/* Functions Definition ------------------------------------------------------*/ +/* Private functions ----------------------------------------------------------*/ +/* Public functions ----------------------------------------------------------*/ diff --git a/lib/stm32wba/concurrent/System/Config/Debug_GPIO/debug_config.h b/lib/stm32wba/concurrent/System/Config/Debug_GPIO/debug_config.h new file mode 100644 index 000000000..ab9959336 --- /dev/null +++ b/lib/stm32wba/concurrent/System/Config/Debug_GPIO/debug_config.h @@ -0,0 +1,804 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file debug_config.h + * @author MCD Application Team + * @brief Real Time Debug module general configuration file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +#ifndef DEBUG_CONFIG_H +#define DEBUG_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "app_conf.h" + +#if(CFG_RT_DEBUG_GPIO_MODULE == 1) + +/***********************************/ +/** Debug configuration selection **/ +/***********************************/ +/* Debug configuration for System purpose */ +#define USE_RT_DEBUG_CONFIGURATION_SYSTEM (0) + +/* Debug configuration for BLE purpose */ +#define USE_RT_DEBUG_CONFIGURATION_BLE (0) + +/* Debug configuration for MAC purpose */ +#define USE_RT_DEBUG_CONFIGURATION_MAC (0) + +/* Debug configuration for COEX purpose */ +#define USE_RT_DEBUG_CONFIGURATION_COEX (0) + +/*********************************/ +/** GPIO debug signal selection **/ +/*********************************/ + +/* System clock manager - System clock config */ +#define USE_RT_DEBUG_SCM_SYSTEM_CLOCK_CONFIG (0) +#define GPIO_DEBUG_SCM_SYSTEM_CLOCK_CONFIG {GPIOA, LL_PWR_GPIO_PIN_12} + +/* System clock manager - Setup */ +#define USE_RT_DEBUG_SCM_SETUP (0) +#define GPIO_DEBUG_SCM_SETUP {GPIOA, LL_PWR_GPIO_PIN_5} + +/* System clock manager - HSE RDY interrupt handling */ +#define USE_RT_DEBUG_SCM_HSERDY_ISR (0) +#define GPIO_DEBUG_SCM_HSERDY_ISR {GPIOA, LL_PWR_GPIO_PIN_15} + +#define USE_RT_DEBUG_ADC_ACTIVATION (0) +#define GPIO_DEBUG_ADC_ACTIVATION {GPIOB, LL_PWR_GPIO_PIN_4} + +#define USE_RT_DEBUG_ADC_DEACTIVATION (0) +#define GPIO_DEBUG_ADC_DEACTIVATION {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADC_TEMPERATURE_ACQUISITION (0) +#define GPIO_DEBUG_ADC_TEMPERATURE_ACQUISITION {GPIOB, LL_PWR_GPIO_PIN_8} + +#define USE_RT_DEBUG_RNG_ENABLE (0) +#define GPIO_DEBUG_RNG_ENABLE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RNG_DISABLE (0) +#define GPIO_DEBUG_RNG_DISABLE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RNG_GEN_RAND_NUM (0) +#define GPIO_DEBUG_RNG_GEN_RAND_NUM {GPIOB, LL_PWR_GPIO_PIN_12} + +#define USE_RT_DEBUG_LOW_POWER_STOP_MODE_ENTER (0) +#define GPIO_DEBUG_LOW_POWER_STOP_MODE_ENTER {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LOW_POWER_STOP_MODE_EXIT (0) +#define GPIO_DEBUG_LOW_POWER_STOP_MODE_EXIT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LOW_POWER_STOP_MODE_ACTIVE (0) +#define GPIO_DEBUG_LOW_POWER_STOP_MODE_ACTIVE {GPIOB, LL_PWR_GPIO_PIN_3} + +#define USE_RT_DEBUG_LOW_POWER_STOP2_MODE_ENTER (0) +#define GPIO_DEBUG_LOW_POWER_STOP2_MODE_ENTER {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LOW_POWER_STOP2_MODE_EXIT (0) +#define GPIO_DEBUG_LOW_POWER_STOP2_MODE_EXIT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LOW_POWER_STOP2_MODE_ACTIVE (0) +#define GPIO_DEBUG_LOW_POWER_STOP2_MODE_ACTIVE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ENTER (0) +#define GPIO_DEBUG_LOW_POWER_STANDBY_MODE_ENTER {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_EXIT (0) +#define GPIO_DEBUG_LOW_POWER_STANDBY_MODE_EXIT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE (0) +#define GPIO_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE {GPIOB, LL_PWR_GPIO_PIN_15} + +#define USE_RT_DEBUG_HCI_READ_DONE (0) +#define GPIO_DEBUG_HCI_READ_DONE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_HCI_RCVD_CMD (0) +#define GPIO_DEBUG_HCI_RCVD_CMD {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_HCI_WRITE_DONE (0) +#define GPIO_DEBUG_HCI_WRITE_DONE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_SCHDLR_EVNT_UPDATE (0) +#define GPIO_DEBUG_SCHDLR_EVNT_UPDATE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_SCHDLR_TIMER_SET (0) +#define GPIO_DEBUG_SCHDLR_TIMER_SET {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_SCHDLR_PHY_CLBR_TIMER (0) +#define GPIO_DEBUG_SCHDLR_PHY_CLBR_TIMER {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_SCHDLR_EVNT_SKIPPED (0) +#define GPIO_DEBUG_SCHDLR_EVNT_SKIPPED {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE (0) +#define GPIO_DEBUG_SCHDLR_HNDL_NXT_TRACE {GPIOA, LL_PWR_GPIO_PIN_12} + +#define USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_DETEDTED (0) +#define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_DETEDTED {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_GAP_CHECK (0) +#define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_GAP_CHECK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_TIME_CHECK (0) +#define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_TIME_CHECK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_TRACE (0) +#define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_TRACE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_SCHDLR_EVNT_RGSTR (0) +#define GPIO_DEBUG_SCHDLR_EVNT_RGSTR {GPIOB, LL_PWR_GPIO_PIN_8} + +#define USE_RT_DEBUG_SCHDLR_ADD_CONFLICT_Q (0) +#define GPIO_DEBUG_SCHDLR_ADD_CONFLICT_Q {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_SCHDLR_HNDL_MISSED_EVNT (0) +#define GPIO_DEBUG_SCHDLR_HNDL_MISSED_EVNT {GPIOA, LL_PWR_GPIO_PIN_5} + +#define USE_RT_DEBUG_SCHDLR_UNRGSTR_EVNT (0) +#define GPIO_DEBUG_SCHDLR_UNRGSTR_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE (0) +#define GPIO_DEBUG_SCHDLR_EXEC_EVNT_TRACE {GPIOA, LL_PWR_GPIO_PIN_15} + +#define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_PROFILE (0) +#define GPIO_DEBUG_SCHDLR_EXEC_EVNT_PROFILE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_ERROR (0) +#define GPIO_DEBUG_SCHDLR_EXEC_EVNT_ERROR {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_WINDOW_WIDENING (0) +#define GPIO_DEBUG_SCHDLR_EXEC_EVNT_WINDOW_WIDENING {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_CMN_CLR_ISR (0) +#define GPIO_DEBUG_LLHWC_CMN_CLR_ISR {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLWCC_CMN_HG_ISR (0) +#define GPIO_DEBUG_LLWCC_CMN_HG_ISR {GPIOA, LL_PWR_GPIO_PIN_15} + +#define USE_RT_DEBUG_LLHWC_CMN_LW_ISR (0) +#define GPIO_DEBUG_LLHWC_CMN_LW_ISR {GPIOA, LL_PWR_GPIO_PIN_12} + +#define USE_RT_DEBUG_LLHWC_CMN_CLR_TIMER_ERROR (0) +#define GPIO_DEBUG_LLHWC_CMN_CLR_TIMER_ERROR {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_LL_ISR (0) +#define GPIO_DEBUG_LLHWC_LL_ISR {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_SPLTMR_SET (0) +#define GPIO_DEBUG_LLHWC_SPLTMR_SET {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_SPLTMR_GET (0) +#define GPIO_DEBUG_LLHWC_SPLTMR_GET {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_LOW_ISR (0) +#define GPIO_DEBUG_LLHWC_LOW_ISR {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_STOP_SCN (0) +#define GPIO_DEBUG_LLHWC_STOP_SCN {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_WAIT_ENVT_ON_AIR (0) +#define GPIO_DEBUG_LLHWC_WAIT_ENVT_ON_AIR {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_SET_CONN_EVNT_PARAM (0) +#define GPIO_DEBUG_LLHWC_SET_CONN_EVNT_PARAM {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_POST_EVNT (0) +#define GPIO_DEBUG_POST_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_HNDL_ALL_EVNTS (0) +#define GPIO_DEBUG_HNDL_ALL_EVNTS {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PROCESS_EVNT (0) +#define GPIO_DEBUG_PROCESS_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PROCESS_ISO_DATA (0) +#define GPIO_DEBUG_PROCESS_ISO_DATA {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ALLOC_TX_ISO_EMPTY_PKT (0) +#define GPIO_DEBUG_ALLOC_TX_ISO_EMPTY_PKT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BIG_FREE_EMPTY_PKTS (0) +#define GPIO_DEBUG_BIG_FREE_EMPTY_PKTS {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_OK (0) +#define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_OK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_CRC (0) +#define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_CRC {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_NoRX (0) +#define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_NoRX {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_TRACE (0) +#define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_TRACE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ISO_HNDL_SDU (0) +#define GPIO_DEBUG_ISO_HNDL_SDU {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LL_INTF_INIT (0) +#define GPIO_DEBUG_LL_INTF_INIT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_DATA_TO_CNTRLR (0) +#define GPIO_DEBUG_DATA_TO_CNTRLR {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_FREE_LL_PKT_HNDLR (0) +#define GPIO_DEBUG_FREE_LL_PKT_HNDLR {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PHY_INIT_CLBR_TRACE (0) +#define GPIO_DEBUG_PHY_INIT_CLBR_TRACE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PHY_RUNTIME_CLBR_TRACE (0) +#define GPIO_DEBUG_PHY_RUNTIME_CLBR_TRACE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PHY_CLBR_ISR (0) +#define GPIO_DEBUG_PHY_CLBR_ISR {GPIOB, LL_PWR_GPIO_PIN_3} + +#define USE_RT_DEBUG_PHY_INIT_CLBR_SINGLE_CH (0) +#define GPIO_DEBUG_PHY_INIT_CLBR_SINGLE_CH {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PHY_CLBR_STRTD (0) +#define GPIO_DEBUG_PHY_CLBR_STRTD {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PHY_CLBR_EXEC (0) +#define GPIO_DEBUG_PHY_CLBR_EXEC {GPIOB, LL_PWR_GPIO_PIN_4} + +#define USE_RT_DEBUG_RCO_STRT_STOP_RUNTIME_CLBR_ACTV (0) +#define GPIO_DEBUG_RCO_STRT_STOP_RUNTIME_CLBR_ACTV {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RCO_STRT_STOP_RUNTIME_RCO_CLBR (0) +#define GPIO_DEBUG_RCO_STRT_STOP_RUNTIME_RCO_CLBR {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_SWT (0) +#define GPIO_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_SWT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_TRACE (0) +#define GPIO_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_TRACE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RCO_ISR_TRACE (0) +#define GPIO_DEBUG_RCO_ISR_TRACE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RCO_ISR_COMPENDATE (0) +#define GPIO_DEBUG_RCO_ISR_COMPENDATE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RAL_STRT_TX (0) +#define GPIO_DEBUG_RAL_STRT_TX {GPIOA, LL_PWR_GPIO_PIN_5} + +#define USE_RT_DEBUG_RAL_ISR_TIMER_ERROR (0) +#define GPIO_DEBUG_RAL_ISR_TIMER_ERROR {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RAL_ISR_TRACE (0) +#define GPIO_DEBUG_RAL_ISR_TRACE {GPIOB, LL_PWR_GPIO_PIN_3} + +#define USE_RT_DEBUG_RAL_STOP_OPRTN (0) +#define GPIO_DEBUG_RAL_STOP_OPRTN {GPIOB, LL_PWR_GPIO_PIN_8} + +#define USE_RT_DEBUG_RAL_STRT_RX (0) +#define GPIO_DEBUG_RAL_STRT_RX {GPIOB, LL_PWR_GPIO_PIN_12} + +#define USE_RT_DEBUG_RAL_DONE_CLBK_TX (0) +#define GPIO_DEBUG_RAL_DONE_CLBK_TX {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RAL_DONE_CLBK_RX (0) +#define GPIO_DEBUG_RAL_DONE_CLBK_RX {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RAL_DONE_CLBK_ED (0) +#define GPIO_DEBUG_RAL_DONE_CLBK_ED {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RAL_ED_SCAN (0) +#define GPIO_DEBUG_RAL_ED_SCAN {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ERROR_MEM_CAP_EXCED (0) +#define GPIO_DEBUG_ERROR_MEM_CAP_EXCED {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ERROR_COMMAND_DISALLOWED (0) +#define GPIO_DEBUG_ERROR_COMMAND_DISALLOWED {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PTA_INIT (0) +#define GPIO_DEBUG_PTA_INIT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PTA_EN (0) +#define GPIO_DEBUG_PTA_EN {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_PTA_SET_EN (0) +#define GPIO_DEBUG_LLHWC_PTA_SET_EN {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_PTA_SET_PARAMS (0) +#define GPIO_DEBUG_LLHWC_PTA_SET_PARAMS {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_COEX_STRT_ON_IDLE (0) +#define GPIO_DEBUG_COEX_STRT_ON_IDLE {GPIOB, LL_PWR_GPIO_PIN_15} + +#define USE_RT_DEBUG_COEX_ASK_FOR_AIR (0) +#define GPIO_DEBUG_COEX_ASK_FOR_AIR {GPIOB, LL_PWR_GPIO_PIN_3} + +#define USE_RT_DEBUG_COEX_TIMER_EVNT_CLBK (0) +#define GPIO_DEBUG_COEX_TIMER_EVNT_CLBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_COEX_STRT_ONE_SHOT (0) +#define GPIO_DEBUG_COEX_STRT_ONE_SHOT {GPIOA, LL_PWR_GPIO_PIN_5} + +#define USE_RT_DEBUG_COEX_FORCE_STOP_RX (0) +#define GPIO_DEBUG_COEX_FORCE_STOP_RX {GPIOB, LL_PWR_GPIO_PIN_12} + +#define USE_RT_DEBUG_LLHWC_ADV_DONE (0) +#define GPIO_DEBUG_LLHWC_ADV_DONE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_SCN_DONE (0) +#define GPIO_DEBUG_LLHWC_SCN_DONE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_INIT_DONE (0) +#define GPIO_DEBUG_LLHWC_INIT_DONE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_CONN_DONE (0) +#define GPIO_DEBUG_LLHWC_CONN_DONE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_CIG_DONE (0) +#define GPIO_DEBUG_LLHWC_CIG_DONE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_BIG_DONE (0) +#define GPIO_DEBUG_LLHWC_BIG_DONE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_OS_TMR_CREATE (0) +#define GPIO_DEBUG_OS_TMR_CREATE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_TIMEOUT_CBK (0) +#define GPIO_DEBUG_ADV_EXT_TIMEOUT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_SCN_DUR_CBK (0) +#define GPIO_DEBUG_ADV_EXT_SCN_DUR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_SCN_PERIOD_CBK (0) +#define GPIO_DEBUG_ADV_EXT_SCN_PERIOD_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_PRDC_SCN_TIMEOUT_CBK (0) +#define GPIO_DEBUG_ADV_EXT_PRDC_SCN_TIMEOUT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BIS_SYNC_TIMEOUT_TMR_CBK (0) +#define GPIO_DEBUG_BIS_SYNC_TIMEOUT_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BIS_TERM_TMR_CBK (0) +#define GPIO_DEBUG_BIS_TERM_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BIS_TST_MODE_CBK (0) +#define GPIO_DEBUG_BIS_TST_MODE_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BIS_TST_MODE_TMR_CBK (0) +#define GPIO_DEBUG_BIS_TST_MODE_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ISO_POST_TMR_CBK (0) +#define GPIO_DEBUG_ISO_POST_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ISO_TST_MODE_TMR_CBK (0) +#define GPIO_DEBUG_ISO_TST_MODE_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_CONN_POST_TMR_CBK (0) +#define GPIO_DEBUG_CONN_POST_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_EVNT_SCHDLR_TMR_CBK (0) +#define GPIO_DEBUG_EVNT_SCHDLR_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_HCI_POST_TMR_CBK (0) +#define GPIO_DEBUG_HCI_POST_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLCP_POST_TMR_CBK (0) +#define GPIO_DEBUG_LLCP_POST_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_ENRGY_DETECT_CBK (0) +#define GPIO_DEBUG_LLHWC_ENRGY_DETECT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PRVCY_POST_TMR_CBK (0) +#define GPIO_DEBUG_PRVCY_POST_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ANT_PRPR_TMR_CBK (0) +#define GPIO_DEBUG_ANT_PRPR_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_COEX_TMR_FRC_STOP_AIR_GRANT_CBK (0) +#define GPIO_DEBUG_COEX_TMR_FRC_STOP_AIR_GRANT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_MLME_RX_EN_TMR_CBK (0) +#define GPIO_DEBUG_MLME_RX_EN_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_MLME_GNRC_TMR_CBK (0) +#define GPIO_DEBUG_MLME_GNRC_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_MIB_JOIN_LST_TMR_CBK (0) +#define GPIO_DEBUG_MIB_JOIN_LST_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_MLME_PWR_PRES_TMR_CBK (0) +#define GPIO_DEBUG_MLME_PWR_PRES_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PRESISTENCE_TMR_CBK (0) +#define GPIO_DEBUG_PRESISTENCE_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RADIO_PHY_PRDC_CLBK_TMR_CBK (0) +#define GPIO_DEBUG_RADIO_PHY_PRDC_CLBK_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RADIO_CSMA_TMR_CBK (0) +#define GPIO_DEBUG_RADIO_CSMA_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RADIO_CSL_RCV_TMR_CBK (0) +#define GPIO_DEBUG_RADIO_CSL_RCV_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ED_TMR_CBK (0) +#define GPIO_DEBUG_ED_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_DIO_EXT_TMR_CBK (0) +#define GPIO_DEBUG_DIO_EXT_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RCO_CLBR_TMR_CBK (0) +#define GPIO_DEBUG_RCO_CLBR_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_MNGR_ADV_CBK (0) +#define GPIO_DEBUG_ADV_EXT_MNGR_ADV_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_MNGR_SCN_CBK (0) +#define GPIO_DEBUG_ADV_EXT_MNGR_SCN_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_MNGR_SCN_ERR_CBK (0) +#define GPIO_DEBUG_ADV_EXT_MNGR_SCN_ERR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CBK (0) +#define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_ERR_CBK (0) +#define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_ERR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BIG_ADV_CBK (0) +#define GPIO_DEBUG_BIG_ADV_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BIG_ADV_ERR_CBK (0) +#define GPIO_DEBUG_BIG_ADV_ERR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BIG_SYNC_CBK (0) +#define GPIO_DEBUG_BIG_SYNC_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BIG_SYNC_ERR_CBK (0) +#define GPIO_DEBUG_BIG_SYNC_ERR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ISO_CIS_PKT_TRNSM_RECEIVED_CBK (0) +#define GPIO_DEBUG_ISO_CIS_PKT_TRNSM_RECEIVED_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ISO_CIG_ERR_CBK (0) +#define GPIO_DEBUG_ISO_CIG_ERR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_CONN_PKT_TRNSM_RECEIVED_CBK (0) +#define GPIO_DEBUG_CONN_PKT_TRNSM_RECEIVED_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PRDC_CLBR_EXTRL_CBK (0) +#define GPIO_DEBUG_PRDC_CLBR_EXTRL_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PTR_PRDC_ADV_SYNC_CBK (0) +#define GPIO_DEBUG_PTR_PRDC_ADV_SYNC_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_NCONN_SCN_CBK (0) +#define GPIO_DEBUG_NCONN_SCN_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_NCONN_ADV_CBK (0) +#define GPIO_DEBUG_NCONN_ADV_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_NCONN_INIT_CBK (0) +#define GPIO_DEBUG_NCONN_INIT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ANT_RADIO_CMPLT_EVNT_CBK (0) +#define GPIO_DEBUG_ANT_RADIO_CMPLT_EVNT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ANT_STACK_EVNT_CBK (0) +#define GPIO_DEBUG_ANT_STACK_EVNT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_PROCESS_TMOUT_EVNT_CBK (0) +#define GPIO_DEBUG_ADV_EXT_PROCESS_TMOUT_EVNT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_MNGR_SCN_DUR_EVNT (0) +#define GPIO_DEBUG_ADV_EXT_MNGR_SCN_DUR_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_MNGR_SCN_PERIODIC_EVNT (0) +#define GPIO_DEBUG_ADV_EXT_MNGR_SCN_PERIODIC_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_TMOUT_EVNT (0) +#define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_TMOUT_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CNCEL_EVNT (0) +#define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CNCEL_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BIS_MNGR_BIG_TERM_CBK (0) +#define GPIO_DEBUG_BIS_MNGR_BIG_TERM_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BIS_MNGR_SYNC_TMOUT_CBK (0) +#define GPIO_DEBUG_BIS_MNGR_SYNC_TMOUT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ISOAL_MNGR_SDU_GEN (0) +#define GPIO_DEBUG_ISOAL_MNGR_SDU_GEN {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_ISO_MNGR_CIS_PROCESS_EVNT_CBK (0) +#define GPIO_DEBUG_ISO_MNGR_CIS_PROCESS_EVNT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_CONN_MNGR_PROCESS_EVNT_CLBK (0) +#define GPIO_DEBUG_CONN_MNGR_PROCESS_EVNT_CLBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_CONN_MNGR_UPDT_CONN_PARAM_CBK (0) +#define GPIO_DEBUG_CONN_MNGR_UPDT_CONN_PARAM_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_EVNT_SCHDLR_HW_EVNT_CMPLT (0) +#define GPIO_DEBUG_EVNT_SCHDLR_HW_EVNT_CMPLT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_HCI_EVENT_HNDLR (0) +#define GPIO_DEBUG_HCI_EVENT_HNDLR {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_MLME_TMRS_CBK (0) +#define GPIO_DEBUG_MLME_TMRS_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_DIRECT_TX_EVNT_CBK (0) +#define GPIO_DEBUG_DIRECT_TX_EVNT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_INDIRECT_PKT_TOUR_CBK (0) +#define GPIO_DEBUG_INDIRECT_PKT_TOUR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RADIO_CSMA_TMR (0) +#define GPIO_DEBUG_RADIO_CSMA_TMR {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK (0) +#define GPIO_DEBUG_RAL_SM_DONE_EVNT_CBK {GPIOB, LL_PWR_GPIO_PIN_4} + +#define USE_RT_DEBUG_ED_TMR_HNDL (0) +#define GPIO_DEBUG_ED_TMR_HNDL {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_OS_TMR_EVNT_CBK (0) +#define GPIO_DEBUG_OS_TMR_EVNT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PROFILE_MARKER_PHY_WAKEUP_TIME (0) +#define GPIO_DEBUG_PROFILE_MARKER_PHY_WAKEUP_TIME {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PROFILE_END_DRIFT_TIME (0) +#define GPIO_DEBUG_PROFILE_END_DRIFT_TIME {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PROC_RADIO_RCV (0) +#define GPIO_DEBUG_PROC_RADIO_RCV {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_EVNT_TIME_UPDT (0) +#define GPIO_DEBUG_EVNT_TIME_UPDT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_MAC_RECEIVE_DONE (0) +#define GPIO_DEBUG_MAC_RECEIVE_DONE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_MAC_TX_DONE (0) +#define GPIO_DEBUG_MAC_TX_DONE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RADIO_APPLY_CSMA (0) +#define GPIO_DEBUG_RADIO_APPLY_CSMA {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RADIO_TRANSMIT (0) +#define GPIO_DEBUG_RADIO_TRANSMIT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_PROC_RADIO_TX (0) +#define GPIO_DEBUG_PROC_RADIO_TX {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RAL_TX_DONE (0) +#define GPIO_DEBUG_RAL_TX_DONE {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RAL_TX_DONE_INCREMENT_BACKOFF_COUNT (0) +#define GPIO_DEBUG_RAL_TX_DONE_INCREMENT_BACKOFF_COUNT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RAL_TX_DONE_RST_BACKOFF_COUNT (0) +#define GPIO_DEBUG_RAL_TX_DONE_RST_BACKOFF_COUNT {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RAL_CONTINUE_RX (0) +#define GPIO_DEBUG_RAL_CONTINUE_RX {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RAL_PERFORM_CCA (0) +#define GPIO_DEBUG_RAL_PERFORM_CCA {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_RAL_ENABLE_TRANSMITTER (0) +#define GPIO_DEBUG_RAL_ENABLE_TRANSMITTER {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_LLHWC_GET_CH_IDX_ALGO_2 (0) +#define GPIO_DEBUG_LLHWC_GET_CH_IDX_ALGO_2 {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BACK_FROM_DEEP_SLEEP (0) +#define GPIO_DEBUG_BACK_FROM_DEEP_SLEEP {GPIOA, LL_PWR_GPIO_PIN_0} + +/* Application signal selection and GPIO assignment. + CAN BE MODIFIED BY USER */ + +#define USE_RT_DEBUG_APP_APPE_INIT (0) +#define GPIO_DEBUG_APP_APPE_INIT {GPIOA, LL_PWR_GPIO_PIN_0} + +/********************************/ +/** Debug configuration setup **/ +/*******************************/ + +/* + * + * Debug configuration for System purpose + * + */ +#if (USE_RT_DEBUG_CONFIGURATION_SYSTEM == 1U) +/* SCM_SETUP activation */ +#undef USE_RT_DEBUG_SCM_SETUP +#define USE_RT_DEBUG_SCM_SETUP (1U) + +/* SCM_SYSTEM_CLOCK_CONFIG activation */ +#undef USE_RT_DEBUG_SCM_SYSTEM_CLOCK_CONFIG +#define USE_RT_DEBUG_SCM_SYSTEM_CLOCK_CONFIG (1U) + +/* SCM_HSERDY_ISR activation */ +#undef USE_RT_DEBUG_SCM_HSERDY_ISR +#define USE_RT_DEBUG_SCM_HSERDY_ISR (1U) + +/* LOW_POWER_STOP_MODE_ACTIVE activation */ +#undef USE_RT_DEBUG_LOW_POWER_STOP_MODE_ACTIVE +#define USE_RT_DEBUG_LOW_POWER_STOP_MODE_ACTIVE (1U) + +/* ADC_ACTIVATION activation */ +#undef USE_RT_DEBUG_ADC_ACTIVATION +#define USE_RT_DEBUG_ADC_ACTIVATION (1U) + +/* ADC_TEMPERATURE_ACQUISITION activation */ +#undef USE_RT_DEBUG_ADC_TEMPERATURE_ACQUISITION +#define USE_RT_DEBUG_ADC_TEMPERATURE_ACQUISITION (1U) + +/* RNG_GEN_RAND_NUM activation */ +#undef USE_RT_DEBUG_RNG_GEN_RAND_NUM +#define USE_RT_DEBUG_RNG_GEN_RAND_NUM (1U) + +/* LOW_POWER_STANDBY_MODE_ACTIVE activation */ +#undef USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE +#define USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE (1U) + +/* + * + * Debug configuration for BLE purpose + * + */ +#elif (USE_RT_DEBUG_CONFIGURATION_BLE == 1U) + +/* LLHWC_CMN_LW_ISR activation */ +#undef USE_RT_DEBUG_LLHWC_CMN_LW_ISR +#define USE_RT_DEBUG_LLHWC_CMN_LW_ISR (1U) + +/* LLHWC_CMN_HG_ISR activation */ +#undef USE_RT_DEBUG_LLWCC_CMN_HG_ISR +#define USE_RT_DEBUG_LLWCC_CMN_HG_ISR (1U) + +/* PHY_CLBR_EXEC activation */ +#undef USE_RT_DEBUG_PHY_CLBR_EXEC +#define USE_RT_DEBUG_PHY_CLBR_EXEC (1U) + +/* SCHDLR_EVNT_RGSTR activation */ +#undef USE_RT_DEBUG_SCHDLR_EVNT_RGSTR +#define USE_RT_DEBUG_SCHDLR_EVNT_RGSTR (1U) + +/* SCHDLR_HNDL_MISSED_EVNT activation */ +#undef USE_RT_DEBUG_SCHDLR_HNDL_MISSED_EVNT +#define USE_RT_DEBUG_SCHDLR_HNDL_MISSED_EVNT (1U) + +/* SCHDLR_HNDL_NXT_TRACE activation */ +#undef USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE +#define USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE (1U) + +/* SCHDLR_EXEC_EVNT_TRACE activation */ +#undef USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE +#define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE (1U) + +/* PHY_CLBR_ISR activation */ +#undef USE_RT_DEBUG_PHY_CLBR_ISR +#define USE_RT_DEBUG_PHY_CLBR_ISR (1U) + +/* + * + * Debug configuration for MAC purpose + * + */ +#elif (USE_RT_DEBUG_CONFIGURATION_MAC == 1U) + +/* LLHWC_CMN_LW_ISR activation */ +#undef USE_RT_DEBUG_LLHWC_CMN_LW_ISR +#define USE_RT_DEBUG_LLHWC_CMN_LW_ISR (1U) + +/* LLHWC_CMN_HG_ISR activation */ +#undef USE_RT_DEBUG_LLWCC_CMN_HG_ISR +#define USE_RT_DEBUG_LLWCC_CMN_HG_ISR (1U) + +/* RAL_ISR_TRACE activation */ +#undef USE_RT_DEBUG_RAL_ISR_TRACE +#define USE_RT_DEBUG_RAL_ISR_TRACE (1U) + +/* RAL_SM_DONE_EVNT_CBK activation */ +#undef USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK +#define USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK (1U) + +/* RAL_STOP_OPRTN activation */ +#undef USE_RT_DEBUG_RAL_STOP_OPRTN +#define USE_RT_DEBUG_RAL_STOP_OPRTN (1U) + +/* RAL_STRT_RX activation */ +#undef USE_RT_DEBUG_RAL_STRT_RX +#define USE_RT_DEBUG_RAL_STRT_RX (1U) + +/* RAL_STRT_TX activation */ +#undef USE_RT_DEBUG_RAL_STRT_TX +#define USE_RT_DEBUG_RAL_STRT_TX (1U) + +/* + * + * Debug configuration for COEX purpose + * + */ +#elif (USE_RT_DEBUG_CONFIGURATION_COEX == 1U) + +/* COEX_ASK_FOR_AIR activation */ +#undef USE_RT_DEBUG_COEX_ASK_FOR_AIR +#define USE_RT_DEBUG_COEX_ASK_FOR_AIR (1U) + +/* COEX_FORCE_STOP_RX activation */ +#undef USE_RT_DEBUG_COEX_FORCE_STOP_RX +#define USE_RT_DEBUG_COEX_FORCE_STOP_RX (1U) + +/* COEX_STRT_ON_IDLE activation */ +#undef USE_RT_DEBUG_COEX_STRT_ON_IDLE +#define USE_RT_DEBUG_COEX_STRT_ON_IDLE (1U) + +/* COEX_STRT_ONE_SHOT activation */ +#undef USE_RT_DEBUG_COEX_STRT_ONE_SHOT +#define USE_RT_DEBUG_COEX_STRT_ONE_SHOT (1U) + +/* SCHDLR_HNDL_NXT_TRACE activation */ +#undef USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE +#define USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE (1U) + +/* SCHDLR_EXEC_EVNT_TRACE activation */ +#undef USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE +#define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE (1U) + +/* RAL_SM_DONE_EVNT_CBK activation */ +#undef USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK +#define USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK (1U) + +/* RAL_STOP_OPRTN activation */ +#undef USE_RT_DEBUG_RAL_STOP_OPRTN +#define USE_RT_DEBUG_RAL_STOP_OPRTN (1U) + +#else +/* Nothing to do */ +#endif /* (USE_RT_DEBUG_CONFIGURATION_COEX == 1U) */ + +#endif /* CFG_RT_DEBUG_GPIO_MODULE */ + +/******************************************************************/ +/** Association table between general debug signal and used gpio **/ +/******************************************************************/ + +#include "debug_signals.h" + +#if (CFG_RT_DEBUG_GPIO_MODULE == 1) + +#include "stm32wbaxx_hal.h" + +typedef struct { + GPIO_TypeDef* GPIO_port; + uint16_t GPIO_pin; +} st_gpio_debug_t; + +extern const st_gpio_debug_t general_debug_table[RT_DEBUG_SIGNALS_TOTAL_NUM]; + +#endif /* CFG_RT_DEBUG_GPIO_MODULE */ + +#ifdef __cplusplus +} +#endif + +#endif /* DEBUG_CONFIG_H */ diff --git a/lib/stm32wba/concurrent/System/Config/Log/log_module_conf.h b/lib/stm32wba/concurrent/System/Config/Log/log_module_conf.h new file mode 100644 index 000000000..a09f19ba9 --- /dev/null +++ b/lib/stm32wba/concurrent/System/Config/Log/log_module_conf.h @@ -0,0 +1,298 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file log_module_conf.h + * @author MCD Application Team + * @brief Header file of the log module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LOG_MODULE_CONF_H +#define LOG_MODULE_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "app_conf.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Module configuration ------------------------------------------------------*/ +/** + * @brief When this define is set to 0, there is no time stamp added to the trace data. + * When this define is set to 1, the time stamp is added to the trace data, + * according to the function registered with Log_Module_RegisterTimeStampFunction. + */ +#define LOG_INSERT_TIME_STAMP_INSIDE_THE_TRACE CFG_LOG_INSERT_TIME_STAMP_INSIDE_THE_TRACE + +/** + * @brief When this define is set to 0, the color of the trace data remains the same for all regions. + * When this define is set to 1, the color added to the trace data is based on LOG_COLOR_DEFAULT_CONFIGURATION. + */ +#define LOG_INSERT_COLOR_INSIDE_THE_TRACE CFG_LOG_INSERT_COLOR_INSIDE_THE_TRACE + +/** + * @brief When this define is set to 0, the trace data is not modified. + * When this define is set to 1, if there is no ENDOFLINE_CHAR as last + * character in the trace data, then one is added. + */ +#define LOG_INSERT_EOL_INSIDE_THE_TRACE CFG_LOG_INSERT_EOL_INSIDE_THE_TRACE + +/* USER CODE BEGIN Module configuration */ + +/* USER CODE END Module configuration */ + +/* Private defines -----------------------------------------------------------*/ +/* These defines are related to the UTIL_ADV_TRACE. Do not modify them please. */ +#define LOG_MODULE_MIN_VERBOSE_LEVEL (0) +#define LOG_MODULE_MAX_VERBOSE_LEVEL (0xFFFFFFFF) +#define LOG_MODULE_MIN_REGION_VALUE (0) +#define LOG_MODULE_ALL_REGION_MASK (0xFFFFFFFF) + +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Exported types ------------------------------------------------------------*/ +/* Log module types */ +/** + * @brief Customizable enum describing the verbose levels used by the log module. + * The levels include the lower levels in the logs. + * + * E.g. LOG_VERBOSE_ERROR means LOG_VERBOSE_ERROR logs will be printed, + * as well as LOG_VERBOSE_INFO, but not the others with higher values. + * + * The min and max ranges are defined by LOG_MODULE_MIN_VERBOSE_LEVEL + * and LOG_MODULE_MAX_VERBOSE_LEVEL. + * + * The user can add its own levels but must NOT add a value to the said + * levels. Verbose levels are handled by the UTIL_ADV_TRACE. + */ +typedef enum +{ + LOG_VERBOSE_INFO = LOG_MODULE_MIN_VERBOSE_LEVEL, + /* USER CODE BEGIN Log_Verbose_Level_t_0 */ + + /* USER CODE END Log_Verbose_Level_t_0 */ + LOG_VERBOSE_ERROR, + /* USER CODE BEGIN Log_Verbose_Level_t_1 */ + + /* USER CODE END Log_Verbose_Level_t_1 */ + LOG_VERBOSE_WARNING, + /* USER CODE BEGIN Log_Verbose_Level_t_2 */ + + /* USER CODE END Log_Verbose_Level_t_2 */ + LOG_VERBOSE_DEBUG, + /* USER CODE BEGIN Log_Verbose_Level_t_3 */ + + /* USER CODE END Log_Verbose_Level_t_3 */ + LOG_VERBOSE_ALL_LOGS = LOG_MODULE_MAX_VERBOSE_LEVEL, +} Log_Verbose_Level_t; + +/** + * @brief Customizable enum describing the regions used by the log module. + * Regions are used to separate the logs into different places. + * + * Let's say you have a Task 1 and a Task 2. + * Both of them have Info and Debug logs. + * + * By using them as such, i.e. with the same regions, you'll + * print the logs of the 2 tasks as long as the verbose is Info or Debug. + * + * If you create a region for Task 1 and another for Task 2, you can + * split the logs between them, and, if needed, only print the Debug + * logs for Task 1 only (i.e. Task 1 logs for Info and Debug). + * + * Behind the scenes is a mask into which each region is a bit. + * The user can add its own regions but must NOT add a value to them. + * The log module handles the mask on its own. + */ +typedef enum +{ + LOG_REGION_BLE = LOG_MODULE_MIN_REGION_VALUE, + LOG_REGION_SYSTEM, + LOG_REGION_APP, + LOG_REGION_LINKLAYER, + LOG_REGION_MAC, + LOG_REGION_ZIGBEE, + LOG_REGION_THREAD, + LOG_REGION_RTOS, + /* USER CODE BEGIN Log_Region_t */ + + /* USER CODE END Log_Region_t */ + LOG_REGION_ALL_REGIONS = LOG_MODULE_ALL_REGION_MASK, +} Log_Region_t; + +typedef enum +{ + LOG_COLOR_NONE = 0, /* Initialization */ + LOG_COLOR_CODE_DEFAULT = 37, /* White */ + LOG_COLOR_CODE_RED = 91, + LOG_COLOR_CODE_GREEN = 92, + LOG_COLOR_CODE_YELLOW = 93, + LOG_COLOR_CODE_CYAN = 96, + /* USER CODE BEGIN Log_Color_t */ + + /* USER CODE END Log_Color_t */ +} Log_Color_t; + +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported macro ------------------------------------------------------------*/ +/* Display 64 bits number for all compiler. */ +/* Example : LOG_INFO_APP( "New Device : " LOG_DISPLAY64() " installed in %d seconds", LOG_NUMBER64( dlDevice ), iTime ); */ +#define LOG_DISPLAY64() "0x%08X%08X" +#define LOG_NUMBER64( number ) (uint32_t)( number >> 32u ), (uint32_t)( number ) + +/* Module API - Log macros for each region */ +/* LOG_REGION_BLE */ +#if (CFG_LOG_SUPPORTED != 0) +#define LOG_INFO_BLE(...) Log_Module_Print( LOG_VERBOSE_INFO, LOG_REGION_BLE, __VA_ARGS__) +#define LOG_ERROR_BLE(...) Log_Module_Print( LOG_VERBOSE_ERROR, LOG_REGION_BLE, __VA_ARGS__) +#define LOG_WARNING_BLE(...) Log_Module_Print( LOG_VERBOSE_WARNING, LOG_REGION_BLE, __VA_ARGS__) +#define LOG_DEBUG_BLE(...) Log_Module_Print( LOG_VERBOSE_DEBUG, LOG_REGION_BLE, __VA_ARGS__) +#else /* (CFG_LOG_SUPPORTED != 0) */ +#define LOG_INFO_BLE(...) do {} while(0) +#define LOG_ERROR_BLE(...) do {} while(0) +#define LOG_WARNING_BLE(...) do {} while(0) +#define LOG_DEBUG_BLE(...) do {} while(0) +#endif /* (CFG_LOG_SUPPORTED != 0) */ + +/* macro ensuring retrocompatibility with old applications */ +#define APP_DBG LOG_INFO_APP +#define APP_DBG_MSG LOG_INFO_APP + +/* USER CODE BEGIN LOG_REGION_BLE */ +/** + * Add inside this user section your defines to match the new verbose levels you + * created into Log_Verbose_Level_t. + * Example : + * #define LOG_CUSTOM_BLE(...) Log_Module_Print( LOG_VERBOSE_CUSTOM, LOG_REGION_BLE, __VA_ARGS__); + * + * You don't need to update all regions with your custom values. + * Do it accordingly to your needs. E.g you might not need LOG_VERBOSE_CUSTOM for a System region. + */ + +/* USER CODE END LOG_REGION_BLE */ + +/* LOG_REGION_SYSTEM */ +#if (CFG_LOG_SUPPORTED != 0) +#define LOG_INFO_SYSTEM(...) Log_Module_Print( LOG_VERBOSE_INFO, LOG_REGION_SYSTEM, __VA_ARGS__) +#define LOG_ERROR_SYSTEM(...) Log_Module_Print( LOG_VERBOSE_ERROR, LOG_REGION_SYSTEM, __VA_ARGS__) +#define LOG_WARNING_SYSTEM(...) Log_Module_Print( LOG_VERBOSE_WARNING, LOG_REGION_SYSTEM, __VA_ARGS__) +#define LOG_DEBUG_SYSTEM(...) Log_Module_Print( LOG_VERBOSE_DEBUG, LOG_REGION_SYSTEM, __VA_ARGS__) +#else /* (CFG_LOG_SUPPORTED != 0) */ +#define LOG_INFO_SYSTEM(...) do {} while(0) +#define LOG_ERROR_SYSTEM(...) do {} while(0) +#define LOG_WARNING_SYSTEM(...) do {} while(0) +#define LOG_DEBUG_SYSTEM(...) do {} while(0) +#endif /* (CFG_LOG_SUPPORTED != 0) */ + +/* USER CODE BEGIN LOG_REGION_SYSTEM */ +/** + * Add inside this user section your defines to match the new verbose levels you + * created into Log_Verbose_Level_t. + * Example : + * #define LOG_CUSTOM_SYSTEM(...) Log_Module_Print( LOG_VERBOSE_CUSTOM, LOG_REGION_SYSTEM, __VA_ARGS__); + * + * You don't need to update all regions with your custom values. + * Do it accordingly to your needs. E.g you might not need LOG_VERBOSE_CUSTOM for a System region. + */ + +/* USER CODE END LOG_REGION_SYSTEM */ + +/* LOG_REGION_APP */ +#if (CFG_LOG_SUPPORTED != 0) +#define LOG_INFO_APP(...) Log_Module_Print( LOG_VERBOSE_INFO, LOG_REGION_APP, __VA_ARGS__) +#define LOG_ERROR_APP(...) Log_Module_Print( LOG_VERBOSE_ERROR, LOG_REGION_APP, __VA_ARGS__) +#define LOG_WARNING_APP(...) Log_Module_Print( LOG_VERBOSE_WARNING, LOG_REGION_APP, __VA_ARGS__) +#define LOG_DEBUG_APP(...) Log_Module_Print( LOG_VERBOSE_DEBUG, LOG_REGION_APP, __VA_ARGS__) +#else /* (CFG_LOG_SUPPORTED != 0) */ +#define LOG_INFO_APP(...) do {} while(0) +#define LOG_ERROR_APP(...) do {} while(0) +#define LOG_WARNING_APP(...) do {} while(0) +#define LOG_DEBUG_APP(...) do {} while(0) +#endif /* (CFG_LOG_SUPPORTED != 0) */ + +/* USER CODE BEGIN LOG_REGION_APP */ +/** + * Add inside this user section your defines to match the new verbose levels you + * created into Log_Verbose_Level_t. + * Example : + * #define LOG_CUSTOM_APP(...) Log_Module_Print( LOG_VERBOSE_CUSTOM, LOG_REGION_APP, __VA_ARGS__); + * + * You don't need to update all regions with your custom values. + * Do it accordingly to your needs. E.g you might not need LOG_VERBOSE_CUSTOM for a System region. + */ + +/* USER CODE END LOG_REGION_APP */ + +/* LOG_REGION_LINKLAYER */ +#if (CFG_LOG_SUPPORTED != 0) +#define LOG_INFO_LINKLAYER(...) Log_Module_Print( LOG_VERBOSE_INFO, LOG_REGION_LINKLAYER, __VA_ARGS__) +#define LOG_ERROR_LINKLAYER(...) Log_Module_Print( LOG_VERBOSE_ERROR, LOG_REGION_LINKLAYER, __VA_ARGS__) +#define LOG_WARNING_LINKLAYER(...)Log_Module_Print( LOG_VERBOSE_WARNING, LOG_REGION_LINKLAYER, __VA_ARGS__) +#define LOG_DEBUG_LINKLAYER(...) Log_Module_Print( LOG_VERBOSE_DEBUG, LOG_REGION_LINKLAYER, __VA_ARGS__) +#else /* (CFG_LOG_SUPPORTED != 0) */ +#define LOG_INFO_LINKLAYER(...) do {} while(0) +#define LOG_ERROR_LINKLAYER(...) do {} while(0) +#define LOG_WARNING_LINKLAYER(...)do {} while(0) +#define LOG_DEBUG_LINKLAYER(...) do {} while(0) +#endif /* (CFG_LOG_SUPPORTED != 0) */ + +/* USER CODE BEGIN LOG_REGION_LINKLAYER */ +/** + * Add inside this user section your defines to match the new verbose levels you + * created into Log_Verbose_Level_t. + * Example : + * #define LOG_CUSTOM_LINKLAYER(...) Log_Module_Print( LOG_VERBOSE_CUSTOM, LOG_REGION_LINKLAYER, __VA_ARGS__); + * + * You don't need to update all regions with your custom values. + * Do it accordingly to your needs. E.g you might not need LOG_VERBOSE_CUSTOM for a System region. + */ + +/* USER CODE END LOG_REGION_LINKLAYER */ + +/* USER CODE BEGIN APP_LOG_USER_DEFINES */ +/** + * Add inside this user section your defines to match the new regions you + * created into Log_Region_t. + * Example : +#if (CFG_LOG_SUPPORTED != 0) +#define LOG_INFO_CUSTOM(...) Log_Module_Print( LOG_VERBOSE_INFO, LOG_REGION_CUSTOM, __VA_ARGS__) +#define LOG_ERROR_CUSTOM(...) Log_Module_Print( LOG_VERBOSE_ERROR, LOG_REGION_CUSTOM, __VA_ARGS__) +#define LOG_WARNING_CUSTOM(...) Log_Module_Print( LOG_VERBOSE_WARNING, LOG_REGION_CUSTOM, __VA_ARGS__) +#define LOG_DEBUG_CUSTOM(...) Log_Module_Print( LOG_VERBOSE_DEBUG, LOG_REGION_CUSTOM, __VA_ARGS__) +#else +#define LOG_INFO_CUSTOM(...) do {} while(0) +#define LOG_ERROR_CUSTOM(...) do {} while(0) +#define LOG_WARNING_CUSTOM(...) do {} while(0) +#define LOG_DEBUG_CUSTOM(...) do {} while(0) +#endif + */ +/* USER CODE END APP_LOG_USER_DEFINES */ + +#ifdef __cplusplus +} +#endif + +#endif /* LOG_MODULE_CONF_H */ diff --git a/scripts/ble_library.py b/scripts/ble_library.py index 6dc8f8b76..7d599cce8 100644 --- a/scripts/ble_library.py +++ b/scripts/ble_library.py @@ -43,6 +43,8 @@ + "BLE_TransparentMode" zigbee_onoff_client_sed_app_path = "Projects/NUCLEO-WBA65RI/Applications/Zigbee/" \ + "Zigbee_OnOff_Client_SED" +ble_heartrate_zigbee_app_path = "Projects/NUCLEO-WBA65RI/Applications/BLE_Zigbee/" \ + + "BLE_HeartRate_Zigbee" file_list_wba = { "STM32_WPAN": [ "Middlewares/ST/STM32_WPAN/ble/stack/include/auto/ble_types.h", @@ -72,6 +74,10 @@ + "ll_fw_config.h", "Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/thread/" + "ll_fw_config.h", + "Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/" + + "ble_15_4/ll_fw_config.h", + "Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/concurrent/" + + "ble_full_15_4/ll_fw_config.h", "Middlewares/ST/STM32_WPAN/ble/stack/include/ble_bufsize.h", "Middlewares/ST/STM32_WPAN/ble/stack/include/ble_const.h", "Middlewares/ST/STM32_WPAN/ble/stack/include/ble_defs.h", @@ -115,6 +121,19 @@ zigbee_onoff_client_sed_app_path + "/STM32_WPAN/Target/ll_sys_if.c", zigbee_onoff_client_sed_app_path + "/STM32_WPAN/Target/ll_sys_if.h", ], + "concurrent": [ + ble_heartrate_zigbee_app_path + "/Core/Inc/app_common.h", + ble_heartrate_zigbee_app_path + "/Core/Inc/app_conf.h", + ble_heartrate_zigbee_app_path + "/Core/Inc/app_entry.h", + ble_heartrate_zigbee_app_path + "/Core/Inc/utilities_conf.h", + ble_heartrate_zigbee_app_path + "/Core/Inc/main.h", + ble_heartrate_zigbee_app_path + "/System/Config/Debug_GPIO/debug_config.h", + ble_heartrate_zigbee_app_path + "/System/Config/Log/log_module_conf.h", + ble_heartrate_zigbee_app_path + "/STM32_WPAN/Target/power_table.c", + ble_heartrate_zigbee_app_path + "/STM32_WPAN/Target/linklayer_plat.c", + ble_heartrate_zigbee_app_path + "/STM32_WPAN/Target/ll_sys_if.c", + ble_heartrate_zigbee_app_path + "/STM32_WPAN/Target/ll_sys_if.h", + ], "Common": [ "Projects/Common/WPAN/Modules/Flash/rf_timing_synchro.c", "Projects/Common/WPAN/Modules/Flash/rf_timing_synchro.h",