simplelink_lpf3: cc23x0r5: Add missing support for Zephyr

- Add some driverlib files to CMakeLists.
- Add CLKCTL driver.
- Add VIMS functionality for flash. VIMS function API is needed to
enable/disable buffers and check for activity before read/write/erase.
- Extend GPIO functionality with GPIOSetConfigDio and GPIOGetConfigDio.
- Add UARTEnable.
- Add support for DMA mode in ADC driver. Add support to ADC API for DMA
Trigger Event Publisher (INT_EVENT2). The ADC module provides four
interrupt sources (one for each conversion result storage register)
that can be configured to source the DMA trigger.

Signed-off-by: Stoyan Bogdanov <[email protected]>
Signed-off-by: Julien Panis <[email protected]>

Author: jpanisbl

simplelink_lpf3/source/ti/devices/cc23x0r5/CMakeLists.txt

@@ -44,6 +44,11 @@ zephyr_library_sources(
   driverlib/lrfd.c
   driverlib/setup.c
   driverlib/uart.c
+  driverlib/spi.c
+  driverlib/vims.c
+  driverlib/adc.c
+  driverlib/cpu.c
+  driverlib/i2c.c
   )
 
 # RF patches

simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/adc.h

@@ -587,6 +587,126 @@ __STATIC_INLINE void ADCClearInterrupt(uint32_t intFlags)
     HWREG(ADC_BASE + ADC_O_ICLR0) = intFlags;
 }
 
+//*****************************************************************************
+//
+//! \brief Enable DMA trigger for data transfer.
+//!
+//! This function enables DMA trigger for data transfer. DMAEN bit is cleared by hardware
+//! based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN
+//! bit for ADC to generate DMA triggers.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void ADCEnableDMATrigger(void)
+{
+    HWREG(ADC_BASE + ADC_O_CTL2) |= ADC_CTL2_DMAEN;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables individual ADC interrupt sources for DMA Trigger Event Publisher (INT_EVENT2).
+//!
+//! This function enables the indicated ADC interrupt sources (INT_EVENT2).
+//!
+//! \param intFlags is the bit mask of the interrupt sources to be enabled.
+//! The parameter is the bitwise OR of any of the following:
+//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc)
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void ADCEnableDMAInterrupt(uint32_t intFlags)
+{
+    // Enable the specified interrupts.
+    HWREG(ADC_BASE + ADC_O_IMASK2) |= intFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables individual ADC interrupt sources for DMA Trigger Event Publisher (INT_EVENT2).
+//!
+//! This function disables the indicated ADC interrupt sources (INT_EVENT2).
+//!
+//! \param intFlags is the bit mask of the interrupt sources to be disabled.
+//! The parameter is the bitwise OR of any of the following:
+//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc)
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void ADCDisableDMAInterrupt(uint32_t intFlags)
+{
+    // Disable the specified interrupts.
+    HWREG(ADC_BASE + ADC_O_IMASK2) &= ~(intFlags);
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current raw interrupt status for DMA Trigger Event Publisher (INT_EVENT2).
+//!
+//! This function returns the raw interrupt status for the ADC (INT_EVENT2).
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of:
+//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc)
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t ADCRawDMAInterruptStatus(void)
+{
+    return (HWREG(ADC_BASE + ADC_O_RIS2));
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current masked interrupt status for DMA Trigger Event Publisher (INT_EVENT2).
+//!
+//! This function returns the masked interrupt status for the ADC (INT_EVENT2).
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of:
+//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc)
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t ADCMaskedDMAInterruptStatus(void)
+{
+    return (HWREG(ADC_BASE + ADC_O_MIS2));
+}
+
+//*****************************************************************************
+//
+//! \brief Clears ADC interrupt sources for DMA Trigger Event Publisher (INT_EVENT2).
+//!
+//! The specified ADC interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in a module and until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//! At the same time, an early event clear allows new events of the same type to be
+//! pended instead of ignored if the event is cleared later in the ISR.
+//! It is the responsibility of the programmer to make sure that enough time has passed
+//! before returning from the ISR to avoid false re-triggering of the cleared event.
+//! A simple, although not necessarily optimal, way of clearing an event before
+//! returning from the ISR is:
+//! -# Write to clear event (interrupt source). (buffered write)
+//! -# Dummy read from the event source module. (making sure the write has propagated)
+//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any
+//! synchronizers)
+//!
+//! \param intFlags is a bit mask of the interrupt sources to be cleared.
+//! - ADC_INT_MEMRES_N (\ref ADC_INT_MEMRES_00, \ref ADC_INT_MEMRES_01, etc)
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void ADCClearDMAInterrupt(uint32_t intFlags)
+{
+    // Clear the requested interrupt sources
+    HWREG(ADC_BASE + ADC_O_ICLR2) = intFlags;
+}
+
 //*****************************************************************************
 //
 //! \brief Returns ADC gain value for given reference

simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/clkctl.h

@@ -0,0 +1,197 @@
+/******************************************************************************
+ *  Filename:       clkctl.h
+ *
+ *  Description:    Defines and prototypes for the Clock Control (CLKCTL).
+ *
+ *  Copyright (c) 2024 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  1) Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *
+ *  2) Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *  3) Neither the name of the copyright holder nor the names of its
+ *     contributors may be used to endorse or promote products derived from this
+ *     software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************/
+
+#ifndef __CLKCTL_H__
+#define __CLKCTL_H__
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup clkctl_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_ints.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_types.h"
+#include "../inc/hw_clkctl.h"
+#include "debug.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// Values that can be passed to CLKCTLEnable() and CLKCTLDisable().
+//
+//*****************************************************************************
+#define CLKCTL_LGPT3 CLKCTL_CLKENSET0_LGPT3 //!< Configure LGPT3 clock enable
+#define CLKCTL_LGPT2 CLKCTL_CLKENSET0_LGPT2 //!< Configure LGPT2 clock enable
+#define CLKCTL_LGPT1 CLKCTL_CLKENSET0_LGPT1 //!< Configure LGPT1 clock enable
+#define CLKCTL_LGPT0 CLKCTL_CLKENSET0_LGPT0 //!< Configure LGPT0 clock enable
+#define CLKCTL_DMA   CLKCTL_CLKENSET0_DMA   //!< Configure DMA clock enable
+#define CLKCTL_LAES  CLKCTL_CLKENSET0_LAES  //!< Configure LAES clock enable
+#define CLKCTL_ADC0  CLKCTL_CLKENSET0_ADC0  //!< Configure ADC0 clock enable
+#define CLKCTL_SPI0  CLKCTL_CLKENSET0_SPI0  //!< Configure SPI0 clock enable
+#define CLKCTL_I2C0  CLKCTL_CLKENSET0_I2C0  //!< Configure I2C0 clock enable
+#define CLKCTL_UART0 CLKCTL_CLKENSET0_UART0 //!< Configure UART0 clock enable
+#define CLKCTL_LRFD  CLKCTL_CLKENSET0_LRFD  //!< Configure LRFD clock enable
+#define CLKCTL_GPIO  CLKCTL_CLKENSET0_GPIO  //!< Configure GPIO clock enable
+
+//*****************************************************************************
+//
+// API Functions and prototypes.
+//
+//*****************************************************************************
+
+#ifdef DRIVERLIB_DEBUG
+//*****************************************************************************
+//
+//! \internal
+//!
+//! \brief Checks clock control base address.
+//!
+//! This function determines if a clock controle base address is valid.
+//!
+//! \param base specifies the clock control base address.
+//!
+//! \return Returns \c true if the base address is valid and \c false
+//! otherwise.
+//
+//*****************************************************************************
+static bool CLKCTLBaseValid(uint32_t base)
+{
+    return (base == CLKCTL_BASE);
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Enables the clock for a peripheral.
+//!
+//! This function enables the clock for a peripheral.
+//!
+//! \param base specifies the clock control base address.
+//! \param peripheral specifies the peripheral.
+//! The parameter can be one of the following values:
+//! - \ref CLKCTL_LGPT3
+//! - \ref CLKCTL_LGPT2
+//! - \ref CLKCTL_LGPT1
+//! - \ref CLKCTL_LGPT0
+//! - \ref CLKCTL_DMA
+//! - \ref CLKCTL_LAES
+//! - \ref CLKCTL_ADC0
+//! - \ref CLKCTL_SPI0
+//! - \ref CLKCTL_I2C0
+//! - \ref CLKCTL_UART0
+//! - \ref CLKCTL_LRFD
+//! - \ref CLKCTL_GPIO
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void CLKCTLEnable(uint32_t base, uint32_t peripheral)
+{
+    // Check the arguments
+    ASSERT(CLKCTLBaseValid(base));
+
+    // Read-modify-write the set bit
+    HWREG(base + CLKCTL_O_CLKENSET0) |= peripheral;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the clock for a peripheral.
+//!
+//! This function disables the clock for a peripheral.
+//!
+//! \param base specifies the clock control base address.
+//! \param peripheral specifies the peripheral.
+//! The parameter can be one of the following values:
+//! - \ref CLKCTL_LGPT3
+//! - \ref CLKCTL_LGPT2
+//! - \ref CLKCTL_LGPT1
+//! - \ref CLKCTL_LGPT0
+//! - \ref CLKCTL_DMA
+//! - \ref CLKCTL_LAES
+//! - \ref CLKCTL_ADC0
+//! - \ref CLKCTL_SPI0
+//! - \ref CLKCTL_I2C0
+//! - \ref CLKCTL_UART0
+//! - \ref CLKCTL_LRFD
+//! - \ref CLKCTL_GPIO
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void CLKCTLDisable(uint32_t base, uint32_t peripheral)
+{
+    // Check the arguments
+    ASSERT(CLKCTLBaseValid(base));
+
+    // Read-modify-write the clear bit
+    HWREG(base + CLKCTL_O_CLKENCLR0) |= peripheral;
+}
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
+
+#endif // __CLKCTL_H__

simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/gpio.h

@@ -581,6 +581,46 @@ __STATIC_INLINE void GPIOClearEventMultiDio(uint32_t dioMask)
     HWREG( GPIO_BASE + GPIO_O_ICLR ) = dioMask;
 }
 
+//*****************************************************************************
+//
+//! \brief Set configuration to DIO.
+//!
+//! \param iocfgRegAddr is address where config should be written
+//! \param config is the configuration to be written
+//! \return None
+//!
+//! \sa \ref GPIOGetConfigDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void GPIOSetConfigDio(uint32_t iocfgRegAddr, uint32_t config)
+{
+    // Check the arguments.
+    ASSERT(iocfgRegAddr);
+
+    // Set the specified DIO config.
+    HWREG( iocfgRegAddr ) = config;
+}
+
+//*****************************************************************************
+//
+//! \brief Get configuration for DIO.
+//!
+//! \param iocfgRegAddr is address from where config should be read
+//!
+//! \return Raw register value
+//!
+//! \sa \ref GPIOSetConfigDio()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t GPIOGetConfigDio(uint32_t iocfgRegAddr)
+{
+    // Check the arguments.
+    ASSERT(iocfgRegAddr);
+
+    // Return Raw register value.
+    return HWREG( iocfgRegAddr );
+}
+
 //*****************************************************************************
 //
 // Mark the end of the C bindings section for C++ compilers.