simplelink: driver: add DPL and crypto drivers

Port MutexP, SemaphoreP, SwiP, and QueueP to LPF3.
Add support for interrupts of INT_CPUIRQ4, INT_LRFD_IRQ0 and INT_LRFD_IRQ1
used by the RCL (TI's radio driver for F3 devices).

Add AES and ECDH SimpleLink drivers and their dependencies.

Signed-off-by: Vebjorn Myklebust <[email protected]>
Signed-off-by: Lars Thalian Morstad <[email protected]>
Signed-off-by: Min Xu <[email protected]>

Author: vmyklebust

simplelink_lpf3/CMakeLists.txt

@@ -14,23 +14,49 @@ if(CONFIG_HAS_CC23X0_SDK)
   zephyr_library()
   zephyr_library_compile_definitions(${COMPILER})
   zephyr_library_sources(
+    # Default Simplelink configurations
+    source/ti/drivers/config_defaults.c
+
     # Utils
     source/ti/drivers/utils/List.c
 
     # Drivers
+    source/ti/drivers/AESCCM.c
+    source/ti/drivers/AESCMAC.c
+    source/ti/drivers/AESCTR.c
+    source/ti/drivers/AESCTRDRBG.c
+    source/ti/drivers/AESECB.c
+    source/ti/drivers/ECDH.c
+    source/ti/drivers/aesccm/AESCCMLPF3.c
+    source/ti/drivers/aescmac/AESCMACLPF3.c
+    source/ti/drivers/aesctr/AESCTRLPF3.c
+    source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.c
+    source/ti/drivers/aesecb/AESECBLPF3.c
+    source/ti/drivers/cryptoutils/aes/AESCommonLPF3.c
+    source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c
+    source/ti/drivers/cryptoutils/sharedresources/CryptoResourceLPF3.c
+    source/ti/drivers/cryptoutils/utils/CryptoUtils.c
+    source/ti/drivers/dma/UDMALPF3.c
+
     source/ti/drivers/Temperature.c
     source/ti/drivers/power/PowerCC23X0.c
     source/ti/drivers/temperature/TemperatureLPF3.c
     source/ti/drivers/batterymonitor/BatMonSupportLPF3.c
     source/ti/drivers/batterymonitor/BatteryMonitorLPF3.c
 
     # DPL
+    kernel/zephyr/dpl/MutexP_zephyr.c
+    kernel/zephyr/dpl/SemaphoreP_zephyr.c
     kernel/zephyr/dpl/ClockP_zephyr.c
     kernel/zephyr/dpl/HwiP_zephyr.c
+    kernel/zephyr/dpl/SwiP_zephyr.c
     kernel/zephyr/dpl/TaskP_zephyr.c
     kernel/zephyr/dpl/MessageQueueP_zephyr.c
     )
-    if(CONFIG_EVENTS)
-      zephyr_library_sources(kernel/zephyr/dpl/EventP_zephyr.c)
-    endif()
+  if(CONFIG_EVENTS)
+    zephyr_library_sources(kernel/zephyr/dpl/EventP_zephyr.c)
+  endif()
+  zephyr_linker_sources(RAM_SECTIONS
+    ${CMAKE_CURRENT_SOURCE_DIR}/source/ti/drivers/dma/dma.ld
+  )
 endif()

simplelink_lpf3/kernel/zephyr/dpl/ClockP_zephyr.c

@@ -4,10 +4,36 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+
 #include <zephyr/kernel.h>
 #include <zephyr/sys/__assert.h>
-#include <zephyr/sys_clock.h>
+#include <kernel/zephyr/dpl/dpl.h>
 #include <ti/drivers/dpl/ClockP.h>
+#include <ti/drivers/dpl/HwiP.h>
+
+/* Driverlib includes*/
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(inc/hw_types.h)
+#include DeviceFamily_constructPath(inc/hw_memmap.h)
+#include DeviceFamily_constructPath(inc/hw_systim.h)
+
+/** Max number of ClockP ticks into the future supported by this ClockP
+ * implementation.
+ *
+ * Under the hood, ClockP uses the SysTimer whose events trigger immediately if
+ * the compare value is less than 2^22 systimer ticks in the past
+ * (4.194sec at 1us resolution). Therefore, the max number of SysTimer ticks you
+ * can schedule into the future is 2^32 - 2^22 - 1 ticks (~= 4290 sec at 1us
+ * resolution). */
+#define ClockP_PERIOD_MAX     (0xFFBFFFFFU / ClockP_TICK_PERIOD)
+/** Max number of seconds into the future supported by this ClockP
+ * implementation.
+ *
+ * This limit affects ClockP_sleep() */
+#define ClockP_PERIOD_MAX_SEC 4290U
+
+/* Get the current ClockP tick value */
+#define getClockPTick() (HWREG(SYSTIM_BASE + SYSTIM_O_TIME1U) / ClockP_TICK_PERIOD)
 
 /*
  * ClockP_STRUCT_SIZE in ClockP.h must be updated to match the size of this
@@ -36,6 +62,58 @@ static void expiry_fxn(struct k_timer *timer_id)
     obj->clock_fxn(obj->arg);
 }
 
+#ifdef CONFIG_DYNAMIC_DPL_OBJECTS
+
+/* We can't easily dynamically allocate kernel objects so we use memory slabs */
+#define DPL_MAX_CLOCKS 5
+K_MEM_SLAB_DEFINE(clock_slab, sizeof(ClockP_Obj), DPL_MAX_CLOCKS,\
+          MEM_ALIGN);
+
+static ClockP_Obj *dpl_clock_pool_alloc()
+{
+    ClockP_Obj  *clock_ptr = NULL;
+
+    if (k_mem_slab_alloc(&clock_slab, (void **)&clock_ptr, K_NO_WAIT) < 0) {
+
+         __ASSERT(0, "Increase size of DPL clock pool");
+    }
+    return clock_ptr;
+}
+
+static void dpl_clock_pool_free(ClockP_Obj *clock)
+{
+    k_mem_slab_free(&clock_slab, (void *)&clock);
+
+    return;
+}
+
+/*
+ *  ======== ClockP_create ========
+ */
+ClockP_Handle ClockP_create(ClockP_Fxn clkFxn, uint32_t timeout, ClockP_Params *params)
+{
+    ClockP_Handle handle;
+
+    handle = (ClockP_Handle)dpl_clock_pool_alloc();
+
+    /* ClockP_construct will check handle for NULL, no need here */
+    handle = ClockP_construct((ClockP_Struct *)handle, clkFxn, timeout, params);
+
+    return (handle);
+}
+
+/*
+ *  ======== ClockP_delete ========
+ */
+void ClockP_delete(ClockP_Handle handle)
+{
+    ClockP_destruct((ClockP_Struct *)handle);
+
+    dpl_clock_pool_free((ClockP_Obj*) handle);
+}
+
+#endif /* CONFIG_DYNAMIC_DPL_OBJECTS */
+
 /*
  *  ======== ClockP_construct ========
  */
@@ -160,6 +238,37 @@ void ClockP_stop(ClockP_Handle handle)
     obj->active = false;
 }
 
+/*
+ *  ======== ClockP_setFunc ========
+ */
+void ClockP_setFunc(ClockP_Handle handle, ClockP_Fxn clockFxn, uintptr_t arg)
+{
+    ClockP_Obj *obj = (ClockP_Obj *)handle;
+
+    uintptr_t key = HwiP_disable();
+
+    obj->clock_fxn = clockFxn;
+    obj->arg = arg;
+
+    HwiP_restore(key);
+}
+
+/*
+ *  ======== ClockP_sleep ========
+ */
+void ClockP_sleep(uint32_t sec)
+{
+    uint32_t ticksToSleep;
+
+    if (sec > ClockP_PERIOD_MAX_SEC)
+    {
+        sec = ClockP_PERIOD_MAX_SEC;
+    }
+    /* Convert from seconds to number of ticks */
+    ticksToSleep = (sec * USEC_PER_SEC) / ClockP_TICK_PERIOD;
+    k_sleep(K_TICKS(ticksToSleep));
+}
+
 /*
  *  ======== ClockP_usleep ========
  */
@@ -186,6 +295,15 @@ bool ClockP_isActive(ClockP_Handle handle)
     return obj->active;
 }
 
+/*
+ *  ======== ClockP_getCpuFreq ========
+ */
+void ClockP_getCpuFreq(ClockP_FreqHz *freq)
+{
+    freq->lo = (uint32_t)CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
+    freq->hi = 0;
+}
+
 void ClockP_destruct(ClockP_Struct *clockP)
 {
     ClockP_Obj *obj = (ClockP_Obj *)clockP->data;

simplelink_lpf3/kernel/zephyr/dpl/EventP_zephyr.c

@@ -23,25 +23,25 @@
 /* We can't easily dynamically allocate kernel objects */
 #define DPL_MAX_EVENTS 5
 K_MEM_SLAB_DEFINE(event_slab, sizeof(struct k_event), DPL_MAX_EVENTS,\
-		  MEM_ALIGN);
+          MEM_ALIGN);
 
 
 static struct k_event *dpl_event_pool_alloc()
 {
-	struct k_event *event_ptr = NULL;
+    struct k_event *event_ptr = NULL;
 
-	if (k_mem_slab_alloc(&event_slab, (void **)&event_ptr, K_NO_WAIT) < 0) {
+    if (k_mem_slab_alloc(&event_slab, (void **)&event_ptr, K_NO_WAIT) < 0) {
 
-		 __ASSERT(0, "Increase size of DPL event pool");
-	}
-	return event_ptr;
+         __ASSERT(0, "Increase size of DPL event pool");
+    }
+    return event_ptr;
 }
 
 static void dpl_event_pool_free(struct k_event *event)
 {
-	k_mem_slab_free(&event_slab, (void *)event);
+    k_mem_slab_free(&event_slab, (void *)event);
 
-	return;
+    return;
 }
 
 /*
@@ -116,7 +116,7 @@ uint32_t EventP_pend(EventP_Handle event, uint32_t eventMask, bool waitForAll, u
     {
         /* if necessary, convert ClockP ticks to Zephyr ticks */
         /* Should really be ClockP_getSystemTickPeriod() but this causes issues with ielftool post build step */
-        tickPeriod = CLOCKP_TICK_PERIOD;
+        tickPeriod = ClockP_TICK_PERIOD;
         eventTimeout = K_TICKS(timeout);
     }
 

simplelink_lpf3/kernel/zephyr/dpl/HwiP_zephyr.c

@@ -43,8 +43,15 @@ typedef struct _HwiP_Obj
     struct sl_isr_args *cb;
 } HwiP_Obj;
 
+/* interrupt reserved for SwiP */
+int HwiP_swiPIntNum = INT_CPUIRQ1;
+
+static struct sl_isr_args sl_IRQ01_cb = {NULL, 0};
 static struct sl_isr_args sl_IRQ03_cb = {NULL, 0};
+static struct sl_isr_args s1_IRQ04_cb = {NULL, 0};
 static struct sl_isr_args sl_IRQ16_cb = {NULL, 0};
+static struct sl_isr_args s1_LRFD_IRQ0_cb = {NULL, 0};
+static struct sl_isr_args s1_LRFD_IRQ1_cb = {NULL, 0};
 
 /*
  *  ======== HwiP_construct ========
@@ -67,10 +74,12 @@ HwiP_Handle HwiP_construct(HwiP_Struct *handle, int interruptNum, HwiP_Fxn hwiFx
     }
 
     /*
-     * Currently only support INT_CPUIRQ3 (Oscillator ISR) and INT_CPUIRQ16
-     * (Batmon ISR)
+     * Currently only support INT_CPUIRQ1 (SwiP), INT_CPUIRQ3 (Oscillator ISR),
+     * INT_CPUIRQ16 (Batmon ISR), INT_CPUIRQ4 (RCL Scheduler ISR), INT_LRFD_IRQ0
+     * (RCL Command Handler ISR) and INT_LRFD_IRQ1 (RCL Dispatcher ISR)
      */
-    __ASSERT(INT_CPUIRQ3 == interruptNum || INT_CPUIRQ16 == interruptNum,
+    __ASSERT((INT_CPUIRQ1 == interruptNum) || (INT_CPUIRQ3 == interruptNum) || (INT_CPUIRQ4 == interruptNum) ||
+                 (INT_CPUIRQ16 == interruptNum) || (INT_LRFD_IRQ0 == interruptNum) || (INT_LRFD_IRQ1 == interruptNum),
              "Unexpected interruptNum: %d\r\n",
              interruptNum);
 
@@ -95,18 +104,42 @@ HwiP_Handle HwiP_construct(HwiP_Struct *handle, int interruptNum, HwiP_Fxn hwiFx
 
     switch (interruptNum)
     {
+        case INT_CPUIRQ1:
+            sl_IRQ01_cb.cb  = hwiFxn;
+            sl_IRQ01_cb.arg = arg;
+            obj->cb         = &sl_IRQ01_cb;
+            irq_connect_dynamic(INT_CPUIRQ1 - 16, priority, sl_isr, &sl_IRQ01_cb, 0);
+            break;
         case INT_CPUIRQ3:
             sl_IRQ03_cb.cb  = hwiFxn;
             sl_IRQ03_cb.arg = arg;
             obj->cb         = &sl_IRQ03_cb;
             irq_connect_dynamic(INT_CPUIRQ3 - 16, priority, sl_isr, &sl_IRQ03_cb, 0);
             break;
+        case INT_CPUIRQ4:
+            s1_IRQ04_cb.cb  = hwiFxn;
+            s1_IRQ04_cb.arg = arg;
+            obj->cb         = &s1_IRQ04_cb;
+            irq_connect_dynamic(INT_CPUIRQ4 - 16, priority, sl_isr, &s1_IRQ04_cb, 0);
+            break;
         case INT_CPUIRQ16:
             sl_IRQ16_cb.cb  = hwiFxn;
             sl_IRQ16_cb.arg = arg;
             obj->cb         = &sl_IRQ16_cb;
             irq_connect_dynamic(INT_CPUIRQ16 - 16, priority, sl_isr, &sl_IRQ16_cb, 0);
             break;
+        case INT_LRFD_IRQ0:
+            s1_LRFD_IRQ0_cb.cb  = hwiFxn;
+            s1_LRFD_IRQ0_cb.arg = arg;
+            obj->cb             = &s1_LRFD_IRQ0_cb;
+            irq_connect_dynamic(INT_LRFD_IRQ0 - 16, priority, sl_isr, &s1_LRFD_IRQ0_cb, 0);
+            break;
+        case INT_LRFD_IRQ1:
+            s1_LRFD_IRQ1_cb.cb  = hwiFxn;
+            s1_LRFD_IRQ1_cb.arg = arg;
+            obj->cb             = &s1_LRFD_IRQ1_cb;
+            irq_connect_dynamic(INT_LRFD_IRQ1 - 16, priority, sl_isr, &s1_LRFD_IRQ1_cb, 0);
+            break;
         default:
             return (NULL);
     }
@@ -182,3 +215,61 @@ void HwiP_destruct(HwiP_Struct *hwiP)
     obj->cb->arg = (uintptr_t)NULL;
     obj->cb      = NULL;
 }
+
+void HwiP_setPriority(int interruptNum, uint32_t priority)
+{
+    /*
+     * On CM0+, dynamically changing priorities is not allowed. In order to
+     * change priority of an interrupt, after it already has been enabled, the
+     * following must be done:
+     * - Disable the interrupt whose priority needs to be updated
+     * - Set the priority to be at the desired priority level
+     * - Re-enable the interrupt.
+     *
+     * These steps are all handled by IntSetPriority().
+     *
+     * HwiP_disable/enable here serves the purpose of deferring the handling of
+     * user interrupts until the priority of interruptNum has been changed. This
+     * prevents another interrupt from changing the global state potentially
+     * altering the outcome of this function.
+     */
+
+    uintptr_t key = HwiP_disable();
+    IntSetPriority((uint32_t)interruptNum, (uint8_t)priority);
+    HwiP_restore(key);
+}
+
+/*
+ *  ======== HwiP_inISR ========
+ */
+bool HwiP_inISR(void)
+{
+    bool stat;
+
+    if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) == 0)
+    {
+        /* Not currently in an ISR */
+        stat = false;
+    }
+    else
+    {
+        stat = true;
+    }
+
+    return (stat);
+}
+
+/*
+ *  ======== HwiP_inSwi ========
+ */
+bool HwiP_inSwi(void)
+{
+    uint32_t intNum = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
+    if (intNum == HwiP_swiPIntNum)
+    {
+        /* Currently in a Swi */
+        return (true);
+    }
+
+    return (false);
+}