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Tavish Narukantavish
Tavish Naruka
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ntavish
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hal: add startup code for TMS570LC43
Adds soc init code including MPU configuration and PLL errata handling for the TI Hercules family SoC TMS570LC43xx. Portions of this code were taken or adapter from Halcogen code generator. This HAL is not really complete, as the currently implemented drivers do not depend on Halcogen and so were not needed. Signed-off-by: Tavish Naruka <t-naruka@ispace-inc.com>
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‎CMakeLists.txt‎

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add_subdirectory(simplelink)
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add_subdirectory(simplelink_lpf3)
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add_subdirectory(mspm0)
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add_subdirectory(hercules/tms570lc43)

‎hercules/tms570lc43/CMakeLists.txt‎

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if(CONFIG_HAS_TMS570_HALCOGEN_CODE)
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zephyr_include_directories(
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include
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)
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zephyr_library()
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zephyr_library_compile_definitions(${COMPILER})
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zephyr_library_sources(
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source/soc_init.c
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source/asm_funcs.S
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source/soc_pll_errata.c
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)
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endif()

‎hercules/tms570lc43/README.md‎

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Halcogen exported code for TMS570LC43xx MCU
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===========================================
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There is no HAL available from TI to download and include for TMS570
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or hercules series per se, we have code generated by their tool Halcogen
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fo this family if chips.
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This directory contains code exported and adapted from that, and the
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reason to include it here is simply due to licensing of the said code.
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The modifications are mainly to make the code less verbose while still
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mostly keeping it similar. The assembly portions in particular are
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mostly as is.

‎hercules/tms570lc43/source/asm_funcs.S‎

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/*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (C) 2025 ispace, inc.
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*
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* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <zephyr/linker/sections.h>
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#include <zephyr/toolchain.h>
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#include <zephyr/arch/cpu.h>
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/* Exports */
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GTEXT(_mpuInit_)
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GTEXT(soc_reset_hook)
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#define MINITGCR =#0xFFFFFF5C
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#define MSIENA =#0xFFFFFF60
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#define MSTCGSTAT =#0xFFFFFF68
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#define r1Base =#0x00000000
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#define r2Base =#0x00000000
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#define r3Base =#0x08000000
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#define r4Base =#0xF8000000
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#define r5Base =#0x60000000
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#define r6Base =#0x80000000
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#define r7Base =#0xF0000000
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#define r8Base =#0x00000000
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#define r9Base =#0x00000000
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#define r10Base =#0x00000000
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#define r11Base =#0x00000000
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#define r12Base =#0x00000000
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#define r13Base =#0x00000000
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#define r14Base =#0x00000000
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#define r15Base =#0x00000000
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#define r16Base =#0xFFF80000
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/**
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* initialise memory areas (adapted from _memInit_ generated by Halcogen)
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* NOTE: do not use callee saved registers
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*/
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SECTION_FUNC(TEXT, soc_reset_hook)
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ldr r12, MINITGCR /* Load MINITGCR register address */
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mov r10, #0xA
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str r10, [r12] /* Enable global memory hardware initialization */
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ldr r11, MSIENA /* Load MSIENA register address */
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mov r10, #0x1 /* Bit position 0 of MSIENA corresponds to SRAM */
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str r10, [r11] /* Enable auto hardware initalisation for SRAM */
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mloop: /* Loop till memory hardware initialization comletes */
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ldr r9, MSTCGSTAT /* check MSTCGSTAT */
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ldr r10, [r9]
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tst r10, #0x100
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beq mloop
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ldr r11, MSIENA /* Load MSIENA register address */
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mov r10, #0x4 /* Bit position 2 of MSIENA corresponds to VIM RAM */
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str r10, [r11] /* Enable auto hardware initalisation for VIM RAM */
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mloop2: /* Loop till memory hardware initialization comletes */
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ldr r9, MSTCGSTAT /* check MSTCGSTAT */
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ldr r10, [r9]
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tst r10, #0x100
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beq mloop2
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mov r10, #5
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str r10, [r12] /* Disable global memory hardware initialization */
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/* now stack is usable */
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push {lr}
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bl soc_platform_init
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pop {lr}
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bx lr
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SECTION_FUNC(TEXT, _mpuInit_)
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/* Disable mpu */
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mrc p15, #0, r0, c1, c0, #0
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bic r0, r0, #1
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dsb
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mcr p15, #0, r0, c1, c0, #0
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isb
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/* Disable background region */
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mrc p15, #0, r0, c1, c0, #0
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bic r0, r0, #0x20000
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mcr p15, #0, r0, c1, c0, #0
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/* Setup region 1 */
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mov r0, #0
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r1Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0008
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orr r0, r0, #0x1000
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (1 << 12) + (1 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1F << 1) + (1))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 2 */
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mov r0, #1
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r2Base
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mcr p15, #0, r0, c6, c1, #0
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/* non cached flash */
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mov r0, #0x000C
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/* cached flash */
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/* mov r0, #0x0002 */
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orr r0, r0, #0x0600
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (1))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 3 */
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mov r0, #2
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r3Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x000B
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orr r0, r0, #0x1300
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x12 << 1) + (1))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 4 */
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mov r0, #3
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r4Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0010
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orr r0, r0, #0x1300
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1A << 1) + (1))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 5 */
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mov r0, #4
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r5Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0000
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orr r0, r0, #0x0300
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1B << 1) + (1))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 6 */
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mov r0, #5
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r6Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0006
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orr r0, r0, #0x0300
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1A << 1) + (1))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 7 */
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mov r0, #6
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r7Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0008
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orr r0, r0, #0x1200
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x16 << 1) + (1))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 8 */
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mov r0, #7
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r8Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0010
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orr r0, r0, #0x1200
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 9 */
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mov r0, #8
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r9Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0006
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orr r0, r0, #0x1200
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 10 */
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mov r0, #9
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r10Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x000C
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orr r0, r0, #0x1300
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 11 */
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mov r0, #10
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r11Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0006
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orr r0, r0, #0x0600
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 12 */
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mov r0, #11
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r12Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0006
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orr r0, r0, #0x1600
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 13 */
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mov r0, #12
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r13Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0006
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orr r0, r0, #0x1600
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 14 */
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mov r0, #13
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r14Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0006
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orr r0, r0, #0x1600
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 15 */
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mov r0, #14
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r15Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0006
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orr r0, r0, #0x1600
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0))
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mcr p15, #0, r0, c6, c1, #2
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/* Setup region 16 */
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mov r0, #15
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mcr p15, #0, r0, c6, c2, #0
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ldr r0, r16Base
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mcr p15, #0, r0, c6, c1, #0
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mov r0, #0x0010
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orr r0, r0, #0x1200
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mcr p15, #0, r0, c6, c1, #4
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movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x12 << 1) + (1))
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mcr p15, #0, r0, c6, c1, #2
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/* Enable mpu */
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mrc p15, #0, r0, c1, c0, #0
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orr r0, r0, #1
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dsb
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mcr p15, #0, r0, c1, c0, #0
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isb
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bx lr

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