1-
21/******************************************************************************
3- * Filename: crypto.c
4- * Revised: 2020-08-25 16:10:23 +0200 (Tue, 25 Aug 2020)
5- * Revision: 58298
2+ * Filename: aes.c
63*
7- * Description: Driver for the aes functions of the crypto module
4+ * Description: Driver for the AES functions of the crypto module
85*
9- * Copyright (c) 2015 - 2020 , Texas Instruments Incorporated
6+ * Copyright (c) 2015 - 2022 , Texas Instruments Incorporated
107* All rights reserved.
118*
129* Redistribution and use in source and binary forms, with or without
6865
6966
7067
68+ #ifndef CRYPTO_SWRESET_SW_RESET
69+ /* This definition is missing in hw_crypto.h for CC26X0 and CC13X0 devices */
70+ #define CRYPTO_SWRESET_SW_RESET 0x00000001
71+ #endif
72+
73+ #ifndef CRYPTO_DMASWRESET_SWRES
74+ /* This definition is missing in hw_crypto.h for CC26X0 and CC13X0 devices */
75+ #define CRYPTO_DMASWRESET_SWRES 0x00000001
76+ #endif
77+
78+ #ifndef CRYPTO_DMASTAT_CH0_ACT
79+ /* This definition is missing in hw_crypto.h for CC26X0 and CC13X0 devices */
80+ #define CRYPTO_DMASTAT_CH0_ACT 0x00000001
81+ #endif
82+
83+ #ifndef CRYPTO_DMASTAT_CH1_ACT
84+ /* This definition is missing in hw_crypto.h for CC26X0 and CC13X0 devices */
85+ #define CRYPTO_DMASTAT_CH1_ACT 0x00000002
86+ #endif
87+
7188//*****************************************************************************
7289//
7390// Load the initialization vector.
@@ -82,6 +99,36 @@ void AESSetInitializationVector(const uint32_t *initializationVector)
8299 HWREG (CRYPTO_BASE + CRYPTO_O_AESIV3 ) = initializationVector [3 ];
83100}
84101
102+ //*****************************************************************************
103+ //
104+ // Read the IV for Authenticated Modes (CCM or GCM) after the tag has been read.
105+ //
106+ //*****************************************************************************
107+ void AESReadAuthenticationModeIV (uint32_t * iv )
108+ {
109+ /* Read the computed IV out from the hw registers */
110+ iv [0 ] = HWREG (CRYPTO_BASE + CRYPTO_O_AESIV0 );
111+ iv [1 ] = HWREG (CRYPTO_BASE + CRYPTO_O_AESIV1 );
112+ iv [2 ] = HWREG (CRYPTO_BASE + CRYPTO_O_AESIV2 );
113+ /* This read will clear the saved_context_ready bit
114+ * and allow the AES core to start the next operation.
115+ */
116+ iv [3 ] = HWREG (CRYPTO_BASE + CRYPTO_O_AESIV3 );
117+ }
118+
119+ //*****************************************************************************
120+ //
121+ // Read the IV for Non-Authenticated Modes (CBC or CTR).
122+ //
123+ //*****************************************************************************
124+ void AESReadNonAuthenticationModeIV (uint32_t * iv )
125+ {
126+ /* Wait until the saved context is ready */
127+ while (!(HWREG (CRYPTO_BASE + CRYPTO_O_AESCTL ) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M ));
128+
129+ AESReadAuthenticationModeIV (iv );
130+ }
131+
85132//*****************************************************************************
86133//
87134// Start a crypto DMA operation.
@@ -146,7 +193,7 @@ uint32_t AESWaitForIRQFlags(uint32_t irqFlags)
146193
147194//*****************************************************************************
148195//
149- // Transfer a key from CM3 memory to a key store location.
196+ // Transfer a key from CPU memory to a key store location.
150197//
151198//*****************************************************************************
152199uint32_t AESWriteToKeyStore (const uint8_t * aesKey , uint32_t aesKeyLength , uint32_t keyStoreArea )
@@ -165,6 +212,8 @@ uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32
165212 (aesKeyLength == AES_192_KEY_LENGTH_BYTES ) ||
166213 (aesKeyLength == AES_256_KEY_LENGTH_BYTES ));
167214
215+ // This buffer must be declared at function scope to prevent LLVM compiler from optimizing out memcpy.
216+ uint8_t paddedKey [AES_256_KEY_LENGTH_BYTES ] = {0 };
168217 uint32_t keySize = 0 ;
169218
170219 switch (aesKeyLength ) {
@@ -207,8 +256,19 @@ uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32
207256 // Enable key to write (e.g. Key 0).
208257 HWREG (CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA ) = 1 << keyStoreArea ;
209258
210- // Total key length in bytes (16 for 1 x 128-bit key and 32 for 1 x 256-bit key).
211- AESStartDMAOperation (aesKey , aesKeyLength , 0 , 0 );
259+ if (aesKeyLength == AES_192_KEY_LENGTH_BYTES )
260+ {
261+ // Writing a 192-bit key to the key store RAM must be done by writing
262+ // 256 bits of data with the 64 most significant bits set to zero.
263+ memcpy (paddedKey , aesKey , AES_192_KEY_LENGTH_BYTES );
264+
265+ AESStartDMAOperation (paddedKey , AES_256_KEY_LENGTH_BYTES , 0 , 0 );
266+ }
267+ else
268+ {
269+ // Total key length in bytes (16 for 1 x 128-bit key and 32 for 1 x 256-bit key).
270+ AESStartDMAOperation (aesKey , aesKeyLength , 0 , 0 );
271+ }
212272
213273 // Wait for the DMA operation to complete.
214274 uint32_t irqTrigger = AESWaitForIRQFlags (CRYPTO_IRQCLR_RESULT_AVAIL | CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQSTAT_DMA_BUS_ERR | CRYPTO_IRQSTAT_KEY_ST_WR_ERR );
@@ -370,3 +430,122 @@ void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength)
370430
371431 AESSetInitializationVector (initializationVector .word );
372432}
433+
434+ //*****************************************************************************
435+ //
436+ // Write AES_KEY2 registers
437+ //
438+ //*****************************************************************************
439+ void AESWriteKey2 (const uint32_t * key2 ) {
440+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY20 ) = key2 [0 ];
441+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY21 ) = key2 [1 ];
442+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY22 ) = key2 [2 ];
443+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY23 ) = key2 [3 ];
444+ }
445+
446+ //*****************************************************************************
447+ //
448+ // Write AES_KEY3 register
449+ //
450+ //*****************************************************************************
451+ void AESWriteKey3 (const uint32_t * key3 ) {
452+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY30 ) = key3 [0 ];
453+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY31 ) = key3 [1 ];
454+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY32 ) = key3 [2 ];
455+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY33 ) = key3 [3 ];
456+ }
457+
458+ //*****************************************************************************
459+ //
460+ // Clear AES_DATA_IN registers
461+ //
462+ //*****************************************************************************
463+ void AESClearDataIn (void ) {
464+ HWREG (CRYPTO_BASE + CRYPTO_O_AESDATAIN0 ) = 0 ;
465+ HWREG (CRYPTO_BASE + CRYPTO_O_AESDATAIN1 ) = 0 ;
466+ HWREG (CRYPTO_BASE + CRYPTO_O_AESDATAIN2 ) = 0 ;
467+ HWREG (CRYPTO_BASE + CRYPTO_O_AESDATAIN3 ) = 0 ;
468+ }
469+
470+ //*****************************************************************************
471+ //
472+ // Write AES_DATA_IN registers
473+ //
474+ //*****************************************************************************
475+ void AESWriteDataIn (const uint32_t * dataInBuffer ) {
476+ HWREG (CRYPTO_BASE + CRYPTO_O_AESDATAIN0 ) = dataInBuffer [0 ];
477+ HWREG (CRYPTO_BASE + CRYPTO_O_AESDATAIN1 ) = dataInBuffer [1 ];
478+ HWREG (CRYPTO_BASE + CRYPTO_O_AESDATAIN2 ) = dataInBuffer [2 ];
479+ HWREG (CRYPTO_BASE + CRYPTO_O_AESDATAIN3 ) = dataInBuffer [3 ];
480+ }
481+
482+ //*****************************************************************************
483+ //
484+ // Read AES_DATA_OUT registers
485+ //
486+ //*****************************************************************************
487+ void AESReadDataOut (uint32_t * dataOutBuffer ) {
488+ dataOutBuffer [0 ] = HWREG (CRYPTO_BASE + CRYPTO_O_AESDATAOUT0 );
489+ dataOutBuffer [1 ] = HWREG (CRYPTO_BASE + CRYPTO_O_AESDATAOUT1 );
490+ dataOutBuffer [2 ] = HWREG (CRYPTO_BASE + CRYPTO_O_AESDATAOUT2 );
491+ dataOutBuffer [3 ] = HWREG (CRYPTO_BASE + CRYPTO_O_AESDATAOUT3 );
492+ }
493+
494+ //*****************************************************************************
495+ //
496+ // Clear AES_KEY2 registers
497+ //
498+ //*****************************************************************************
499+ void AESClearKey2 (void ) {
500+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY20 ) = 0 ;
501+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY21 ) = 0 ;
502+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY22 ) = 0 ;
503+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY23 ) = 0 ;
504+ }
505+
506+ //*****************************************************************************
507+ //
508+ // Clear AES_KEY3 registers
509+ //
510+ //*****************************************************************************
511+ void AESClearKey3 (void ) {
512+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY30 ) = 0 ;
513+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY31 ) = 0 ;
514+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY32 ) = 0 ;
515+ HWREG (CRYPTO_BASE + CRYPTO_O_AESKEY33 ) = 0 ;
516+ }
517+
518+
519+ //*****************************************************************************
520+ //
521+ // Reset crypto engine
522+ //
523+ //*****************************************************************************
524+ void AESReset (void )
525+ {
526+ /* Soft reset routine per SafeXcel */
527+ HWREG (CRYPTO_BASE + CRYPTO_O_SWRESET ) = CRYPTO_SWRESET_SW_RESET ;
528+ AESSetCtrl (0 );
529+ AESSetDataLength (0 );
530+ AESSetAuthLength (0 );
531+
532+ /* Only CC26X2, CC13X2, CC26X2F6, CC13X2F6, CC26X4, and CC13X4 devices have hash support */
533+ HWREG (CRYPTO_BASE + CRYPTO_O_HASHMODE ) = 0 ;
534+ HWREG (CRYPTO_BASE + CRYPTO_O_HASHINLENL ) = 0 ;
535+ /* CRYPTO_O_HASHINLENH is automatically set to 0 by HW */
536+ }
537+
538+ //*****************************************************************************
539+ //
540+ // Reset crypto DMA
541+ //
542+ //*****************************************************************************
543+ void AESDMAReset (void )
544+ {
545+ /* Reset DMA */
546+ HWREG (CRYPTO_BASE + CRYPTO_O_DMASWRESET ) = CRYPTO_DMASWRESET_SWRES ;
547+
548+ /* Wait for DMA channels to be inactive */
549+ while (HWREG (CRYPTO_BASE + CRYPTO_O_DMASTAT ) &
550+ (CRYPTO_DMASTAT_CH0_ACT | CRYPTO_DMASTAT_CH1_ACT ));
551+ }
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