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simplelink_lpf3: ti: devices: cc23x0r5: Add CLKCTL driver
API is needed to make zephyr driver consistent. Signed-off-by: Julien Panis <[email protected]>
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‎simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/clkctl.h‎

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/******************************************************************************
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* Filename: clkctl.h
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*
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* Description: Defines and prototypes for the Clock Control (CLKCTL).
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*
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* Copyright (c) 2024 Texas Instruments Incorporated
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __CLKCTL_H__
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#define __CLKCTL_H__
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//*****************************************************************************
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//
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//! \addtogroup peripheral_group
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//! @{
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//! \addtogroup clkctl_api
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// If building with a C++ compiler, make all of the definitions in this header
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// have a C binding.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <stdint.h>
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#include "../inc/hw_ints.h"
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#include "../inc/hw_memmap.h"
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#include "../inc/hw_types.h"
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#include "../inc/hw_clkctl.h"
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#include "debug.h"
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#include "interrupt.h"
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//*****************************************************************************
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//
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// Values that can be passed to CLKCTLEnable() and CLKCTLDisable().
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//
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//*****************************************************************************
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#define CLKCTL_LGPT3 CLKCTL_CLKENSET0_LGPT3 //!< Configure LGPT3 clock enable
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#define CLKCTL_LGPT2 CLKCTL_CLKENSET0_LGPT2 //!< Configure LGPT2 clock enable
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#define CLKCTL_LGPT1 CLKCTL_CLKENSET0_LGPT1 //!< Configure LGPT1 clock enable
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#define CLKCTL_LGPT0 CLKCTL_CLKENSET0_LGPT0 //!< Configure LGPT0 clock enable
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#define CLKCTL_DMA CLKCTL_CLKENSET0_DMA //!< Configure DMA clock enable
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#define CLKCTL_LAES CLKCTL_CLKENSET0_LAES //!< Configure LAES clock enable
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#define CLKCTL_ADC0 CLKCTL_CLKENSET0_ADC0 //!< Configure ADC0 clock enable
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#define CLKCTL_SPI0 CLKCTL_CLKENSET0_SPI0 //!< Configure SPI0 clock enable
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#define CLKCTL_I2C0 CLKCTL_CLKENSET0_I2C0 //!< Configure I2C0 clock enable
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#define CLKCTL_UART0 CLKCTL_CLKENSET0_UART0 //!< Configure UART0 clock enable
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#define CLKCTL_LRFD CLKCTL_CLKENSET0_LRFD //!< Configure LRFD clock enable
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#define CLKCTL_GPIO CLKCTL_CLKENSET0_GPIO //!< Configure GPIO clock enable
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//*****************************************************************************
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//
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// API Functions and prototypes.
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//
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//*****************************************************************************
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#ifdef DRIVERLIB_DEBUG
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//*****************************************************************************
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//
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//! \internal
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//!
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//! \brief Checks clock control base address.
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//!
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//! This function determines if a clock controle base address is valid.
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//!
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//! \param base specifies the clock control base address.
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//!
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//! \return Returns \c true if the base address is valid and \c false
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//! otherwise.
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//
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//*****************************************************************************
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static bool CLKCTLBaseValid(uint32_t base)
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{
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return (base == CLKCTL_BASE);
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}
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#endif
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//*****************************************************************************
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//
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//! \brief Enables the clock for a peripheral.
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//!
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//! This function enables the clock for a peripheral.
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//!
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//! \param base specifies the clock control base address.
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//! \param peripheral specifies the peripheral.
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//! The parameter can be one of the following values:
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//! - \ref CLKCTL_LGPT3
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//! - \ref CLKCTL_LGPT2
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//! - \ref CLKCTL_LGPT1
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//! - \ref CLKCTL_LGPT0
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//! - \ref CLKCTL_DMA
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//! - \ref CLKCTL_LAES
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//! - \ref CLKCTL_ADC0
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//! - \ref CLKCTL_SPI0
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//! - \ref CLKCTL_I2C0
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//! - \ref CLKCTL_UART0
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//! - \ref CLKCTL_LRFD
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//! - \ref CLKCTL_GPIO
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//!
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//! \return None
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//
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//*****************************************************************************
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__STATIC_INLINE void CLKCTLEnable(uint32_t base, uint32_t peripheral)
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{
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// Check the arguments
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ASSERT(CLKCTLBaseValid(base));
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// Read-modify-write the set bit
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HWREG(base + CLKCTL_O_CLKENSET0) |= peripheral;
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}
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//*****************************************************************************
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//
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//! \brief Disables the clock for a peripheral.
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//!
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//! This function disables the clock for a peripheral.
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//!
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//! \param base specifies the clock control base address.
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//! \param peripheral specifies the peripheral.
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//! The parameter can be one of the following values:
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//! - \ref CLKCTL_LGPT3
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//! - \ref CLKCTL_LGPT2
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//! - \ref CLKCTL_LGPT1
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//! - \ref CLKCTL_LGPT0
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//! - \ref CLKCTL_DMA
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//! - \ref CLKCTL_LAES
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//! - \ref CLKCTL_ADC0
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//! - \ref CLKCTL_SPI0
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//! - \ref CLKCTL_I2C0
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//! - \ref CLKCTL_UART0
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//! - \ref CLKCTL_LRFD
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//! - \ref CLKCTL_GPIO
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//!
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//! \return None
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//
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//*****************************************************************************
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__STATIC_INLINE void CLKCTLDisable(uint32_t base, uint32_t peripheral)
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{
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// Check the arguments
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ASSERT(CLKCTLBaseValid(base));
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// Read-modify-write the clear bit
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HWREG(base + CLKCTL_O_CLKENCLR0) |= peripheral;
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}
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//*****************************************************************************
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//
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// Mark the end of the C bindings section for C++ compilers.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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}
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#endif
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//*****************************************************************************
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//
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//! Close the Doxygen group.
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//! @}
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//! @}
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//
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//*****************************************************************************
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#endif // __CLKCTL_H__

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